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drm/i915: constify find_section in VBT parsing
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_bios.c
CommitLineData
79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
25e341cf 27#include <linux/dmi.h>
9f0e7ff4 28#include <drm/drm_dp_helper.h>
760285e7
DH
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
79e53945
JB
31#include "i915_drv.h"
32#include "intel_bios.h"
33
9b9d172d 34#define SLAVE_ADDR1 0x70
35#define SLAVE_ADDR2 0x72
79e53945 36
500a8cc4
ZW
37static int panel_type;
38
e8ef3b4c
JN
39static const void *
40find_section(const void *_bdb, int section_id)
79e53945 41{
e8ef3b4c
JN
42 const struct bdb_header *bdb = _bdb;
43 const u8 *base = _bdb;
79e53945
JB
44 int index = 0;
45 u16 total, current_size;
46 u8 current_id;
47
48 /* skip to first section */
49 index += bdb->header_size;
50 total = bdb->bdb_size;
51
52 /* walk the sections looking for section_id */
d1f13fd2 53 while (index + 3 < total) {
79e53945
JB
54 current_id = *(base + index);
55 index++;
d1f13fd2 56
e8ef3b4c 57 current_size = *((const u16 *)(base + index));
79e53945 58 index += 2;
d1f13fd2
CW
59
60 if (index + current_size > total)
61 return NULL;
62
79e53945
JB
63 if (current_id == section_id)
64 return base + index;
d1f13fd2 65
79e53945
JB
66 index += current_size;
67 }
68
69 return NULL;
70}
71
db545019 72static u16
e8ef3b4c 73get_blocksize(const void *p)
db545019
DMEA
74{
75 u16 *block_ptr, block_size;
76
77 block_ptr = (u16 *)((char *)p - 2);
78 block_size = *block_ptr;
79 return block_size;
80}
81
79e53945 82static void
88631706 83fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 84 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
85{
86 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
87 dvo_timing->hactive_lo;
88 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
89 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
90 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
91 dvo_timing->hsync_pulse_width;
92 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
93 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
94
95 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
96 dvo_timing->vactive_lo;
97 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
98 dvo_timing->vsync_off;
99 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
100 dvo_timing->vsync_pulse_width;
101 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
102 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
103 panel_fixed_mode->clock = dvo_timing->clock * 10;
104 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
105
9bc35499
AJ
106 if (dvo_timing->hsync_positive)
107 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
108 else
109 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
110
111 if (dvo_timing->vsync_positive)
112 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
113 else
114 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
115
88631706
ML
116 /* Some VBTs have bogus h/vtotal values */
117 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
118 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
119 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
120 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
121
122 drm_mode_set_name(panel_fixed_mode);
123}
124
99834ea4
CW
125static bool
126lvds_dvo_timing_equal_size(const struct lvds_dvo_timing *a,
127 const struct lvds_dvo_timing *b)
128{
129 if (a->hactive_hi != b->hactive_hi ||
130 a->hactive_lo != b->hactive_lo)
131 return false;
132
133 if (a->hsync_off_hi != b->hsync_off_hi ||
134 a->hsync_off_lo != b->hsync_off_lo)
135 return false;
136
137 if (a->hsync_pulse_width != b->hsync_pulse_width)
138 return false;
139
140 if (a->hblank_hi != b->hblank_hi ||
141 a->hblank_lo != b->hblank_lo)
142 return false;
143
144 if (a->vactive_hi != b->vactive_hi ||
145 a->vactive_lo != b->vactive_lo)
146 return false;
147
148 if (a->vsync_off != b->vsync_off)
149 return false;
150
151 if (a->vsync_pulse_width != b->vsync_pulse_width)
152 return false;
153
154 if (a->vblank_hi != b->vblank_hi ||
155 a->vblank_lo != b->vblank_lo)
156 return false;
157
158 return true;
159}
160
161static const struct lvds_dvo_timing *
162get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
163 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
164 int index)
165{
166 /*
167 * the size of fp_timing varies on the different platform.
168 * So calculate the DVO timing relative offset in LVDS data
169 * entry to get the DVO timing entry
170 */
171
172 int lfp_data_size =
173 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
174 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
175 int dvo_timing_offset =
176 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
177 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
178 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
179
180 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
181}
182
b0354385
TI
183/* get lvds_fp_timing entry
184 * this function may return NULL if the corresponding entry is invalid
185 */
186static const struct lvds_fp_timing *
187get_lvds_fp_timing(const struct bdb_header *bdb,
188 const struct bdb_lvds_lfp_data *data,
189 const struct bdb_lvds_lfp_data_ptrs *ptrs,
190 int index)
191{
192 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
193 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
194 size_t ofs;
195
196 if (index >= ARRAY_SIZE(ptrs->ptr))
197 return NULL;
198 ofs = ptrs->ptr[index].fp_timing_offset;
199 if (ofs < data_ofs ||
200 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
201 return NULL;
202 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
203}
204
88631706
ML
205/* Try to find integrated panel data */
206static void
207parse_lfp_panel_data(struct drm_i915_private *dev_priv,
208 struct bdb_header *bdb)
79e53945 209{
99834ea4
CW
210 const struct bdb_lvds_options *lvds_options;
211 const struct bdb_lvds_lfp_data *lvds_lfp_data;
212 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
213 const struct lvds_dvo_timing *panel_dvo_timing;
b0354385 214 const struct lvds_fp_timing *fp_timing;
79e53945 215 struct drm_display_mode *panel_fixed_mode;
83a7280e 216 int i, downclock, drrs_mode;
79e53945 217
79e53945
JB
218 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
219 if (!lvds_options)
220 return;
221
41aa3448 222 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
79e53945
JB
223 if (lvds_options->panel_type == 0xff)
224 return;
6a04002b 225
500a8cc4 226 panel_type = lvds_options->panel_type;
79e53945 227
83a7280e
PB
228 drrs_mode = (lvds_options->dps_panel_type_bits
229 >> (panel_type * 2)) & MODE_MASK;
230 /*
231 * VBT has static DRRS = 0 and seamless DRRS = 2.
232 * The below piece of code is required to adjust vbt.drrs_type
233 * to match the enum drrs_support_type.
234 */
235 switch (drrs_mode) {
236 case 0:
237 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
238 DRM_DEBUG_KMS("DRRS supported mode is static\n");
239 break;
240 case 2:
241 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
242 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
243 break;
244 default:
245 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
246 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
247 break;
248 }
249
79e53945
JB
250 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
251 if (!lvds_lfp_data)
252 return;
253
1b16de0b
JB
254 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
255 if (!lvds_lfp_data_ptrs)
256 return;
257
41aa3448 258 dev_priv->vbt.lvds_vbt = 1;
79e53945 259
99834ea4
CW
260 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
261 lvds_lfp_data_ptrs,
262 lvds_options->panel_type);
79e53945 263
9a298b2a 264 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
265 if (!panel_fixed_mode)
266 return;
79e53945 267
99834ea4 268 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 269
41aa3448 270 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 271
28c97730 272 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
88631706 273 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 274
d1fcea6a 275 /*
99834ea4
CW
276 * Iterate over the LVDS panel timing info to find the lowest clock
277 * for the native resolution.
d1fcea6a 278 */
99834ea4 279 downclock = panel_dvo_timing->clock;
d1fcea6a 280 for (i = 0; i < 16; i++) {
99834ea4
CW
281 const struct lvds_dvo_timing *dvo_timing;
282
283 dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
284 lvds_lfp_data_ptrs,
285 i);
286 if (lvds_dvo_timing_equal_size(dvo_timing, panel_dvo_timing) &&
287 dvo_timing->clock < downclock)
288 downclock = dvo_timing->clock;
d1fcea6a 289 }
99834ea4 290
d330a953 291 if (downclock < panel_dvo_timing->clock && i915.lvds_downclock) {
d1fcea6a 292 dev_priv->lvds_downclock_avail = 1;
99834ea4 293 dev_priv->lvds_downclock = downclock * 10;
bbb0aef5
JP
294 DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
295 "Normal Clock %dKHz, downclock %dKHz\n",
99834ea4 296 panel_fixed_mode->clock, 10*downclock);
d1fcea6a 297 }
b0354385
TI
298
299 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
300 lvds_lfp_data_ptrs,
301 lvds_options->panel_type);
302 if (fp_timing) {
303 /* check the resolution, just to be sure */
304 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
305 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 306 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
b0354385 307 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
41aa3448 308 dev_priv->vbt.bios_lvds_val);
b0354385
TI
309 }
310 }
88631706
ML
311}
312
f00076d2
JN
313static void
314parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
315{
316 const struct bdb_lfp_backlight_data *backlight_data;
317 const struct bdb_lfp_backlight_data_entry *entry;
318
319 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
320 if (!backlight_data)
321 return;
322
323 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
324 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
325 backlight_data->entry_size);
326 return;
327 }
328
329 entry = &backlight_data->data[panel_type];
330
39fbc9c8
JN
331 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
332 if (!dev_priv->vbt.backlight.present) {
333 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
334 entry->type);
335 return;
336 }
337
f00076d2
JN
338 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
339 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1de6068e 340 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
f00076d2
JN
341 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
342 "active %s, min brightness %u, level %u\n",
343 dev_priv->vbt.backlight.pwm_freq_hz,
344 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
1de6068e 345 dev_priv->vbt.backlight.min_brightness,
f00076d2
JN
346 backlight_data->level[panel_type]);
347}
348
88631706
ML
349/* Try to find sdvo panel data */
350static void
351parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
352 struct bdb_header *bdb)
353{
e8ef3b4c 354 const struct lvds_dvo_timing *dvo_timing;
88631706 355 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 356 int index;
79e53945 357
d330a953 358 index = i915.vbt_sdvo_panel_type;
c10e408a
MF
359 if (index == -2) {
360 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
361 return;
362 }
363
5a1e5b6c 364 if (index == -1) {
e8ef3b4c 365 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
5a1e5b6c
CW
366
367 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
368 if (!sdvo_lvds_options)
369 return;
370
371 index = sdvo_lvds_options->panel_type;
372 }
88631706
ML
373
374 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
375 if (!dvo_timing)
376 return;
377
9a298b2a 378 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
379 if (!panel_fixed_mode)
380 return;
381
5a1e5b6c 382 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
88631706 383
41aa3448 384 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 385
5a1e5b6c
CW
386 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
387 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
388}
389
9a4114ff
BF
390static int intel_bios_ssc_frequency(struct drm_device *dev,
391 bool alternate)
392{
393 switch (INTEL_INFO(dev)->gen) {
394 case 2:
e91e941b 395 return alternate ? 66667 : 48000;
9a4114ff
BF
396 case 3:
397 case 4:
e91e941b 398 return alternate ? 100000 : 96000;
9a4114ff 399 default:
e91e941b 400 return alternate ? 100000 : 120000;
9a4114ff
BF
401 }
402}
403
79e53945
JB
404static void
405parse_general_features(struct drm_i915_private *dev_priv,
406 struct bdb_header *bdb)
407{
bad720ff 408 struct drm_device *dev = dev_priv->dev;
e8ef3b4c 409 const struct bdb_general_features *general;
79e53945 410
79e53945
JB
411 general = find_section(bdb, BDB_GENERAL_FEATURES);
412 if (general) {
41aa3448
RV
413 dev_priv->vbt.int_tv_support = general->int_tv_support;
414 dev_priv->vbt.int_crt_support = general->int_crt_support;
415 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
416 dev_priv->vbt.lvds_ssc_freq =
9a4114ff 417 intel_bios_ssc_frequency(dev, general->ssc_freq);
41aa3448
RV
418 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
419 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
3f704fa2 420 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
41aa3448
RV
421 dev_priv->vbt.int_tv_support,
422 dev_priv->vbt.int_crt_support,
423 dev_priv->vbt.lvds_use_ssc,
424 dev_priv->vbt.lvds_ssc_freq,
425 dev_priv->vbt.display_clock_mode,
426 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
427 }
428}
429
db545019
DMEA
430static void
431parse_general_definitions(struct drm_i915_private *dev_priv,
432 struct bdb_header *bdb)
433{
e8ef3b4c 434 const struct bdb_general_definitions *general;
db545019 435
db545019
DMEA
436 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
437 if (general) {
438 u16 block_size = get_blocksize(general);
439 if (block_size >= sizeof(*general)) {
440 int bus_pin = general->crt_ddc_gmbus_pin;
28c97730 441 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
88ac7939 442 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
41aa3448 443 dev_priv->vbt.crt_ddc_pin = bus_pin;
db545019 444 } else {
28c97730 445 DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
3bd7d909 446 block_size);
db545019
DMEA
447 }
448 }
449}
450
e8ef3b4c
JN
451static const union child_device_config *
452child_device_ptr(const struct bdb_general_definitions *p_defs, int i)
90e4f159 453{
e8ef3b4c 454 return (const void *) &p_defs->devices[i * p_defs->child_dev_size];
90e4f159
VS
455}
456
9b9d172d 457static void
458parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
44834a67 459 struct bdb_header *bdb)
9b9d172d 460{
461 struct sdvo_device_mapping *p_mapping;
e8ef3b4c
JN
462 const struct bdb_general_definitions *p_defs;
463 const union child_device_config *p_child;
9b9d172d 464 int i, child_device_num, count;
db545019 465 u16 block_size;
9b9d172d 466
467 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
468 if (!p_defs) {
44834a67 469 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
9b9d172d 470 return;
471 }
472 /* judge whether the size of child device meets the requirements.
473 * If the child device size obtained from general definition block
474 * is different with sizeof(struct child_device_config), skip the
475 * parsing of sdvo device info
476 */
477 if (p_defs->child_dev_size != sizeof(*p_child)) {
478 /* different child dev size . Ignore it */
28c97730 479 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
9b9d172d 480 return;
481 }
482 /* get the block size of general definitions */
db545019 483 block_size = get_blocksize(p_defs);
9b9d172d 484 /* get the number of child device */
485 child_device_num = (block_size - sizeof(*p_defs)) /
90e4f159 486 p_defs->child_dev_size;
9b9d172d 487 count = 0;
488 for (i = 0; i < child_device_num; i++) {
90e4f159 489 p_child = child_device_ptr(p_defs, i);
768f69c9 490 if (!p_child->old.device_type) {
9b9d172d 491 /* skip the device block if device type is invalid */
492 continue;
493 }
768f69c9
PZ
494 if (p_child->old.slave_addr != SLAVE_ADDR1 &&
495 p_child->old.slave_addr != SLAVE_ADDR2) {
9b9d172d 496 /*
497 * If the slave address is neither 0x70 nor 0x72,
498 * it is not a SDVO device. Skip it.
499 */
500 continue;
501 }
768f69c9
PZ
502 if (p_child->old.dvo_port != DEVICE_PORT_DVOB &&
503 p_child->old.dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 504 /* skip the incorrect SDVO port */
0206e353 505 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
9b9d172d 506 continue;
507 }
28c97730
ZY
508 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
509 " %s port\n",
768f69c9
PZ
510 p_child->old.slave_addr,
511 (p_child->old.dvo_port == DEVICE_PORT_DVOB) ?
9b9d172d 512 "SDVOB" : "SDVOC");
768f69c9 513 p_mapping = &(dev_priv->sdvo_mappings[p_child->old.dvo_port - 1]);
9b9d172d 514 if (!p_mapping->initialized) {
768f69c9
PZ
515 p_mapping->dvo_port = p_child->old.dvo_port;
516 p_mapping->slave_addr = p_child->old.slave_addr;
517 p_mapping->dvo_wiring = p_child->old.dvo_wiring;
518 p_mapping->ddc_pin = p_child->old.ddc_pin;
519 p_mapping->i2c_pin = p_child->old.i2c_pin;
9b9d172d 520 p_mapping->initialized = 1;
46eb3036 521 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
e957d772
CW
522 p_mapping->dvo_port,
523 p_mapping->slave_addr,
524 p_mapping->dvo_wiring,
525 p_mapping->ddc_pin,
46eb3036 526 p_mapping->i2c_pin);
9b9d172d 527 } else {
28c97730 528 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
9b9d172d 529 "two SDVO device.\n");
530 }
768f69c9 531 if (p_child->old.slave2_addr) {
9b9d172d 532 /* Maybe this is a SDVO device with multiple inputs */
533 /* And the mapping info is not added */
28c97730
ZY
534 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
535 " is a SDVO device with multiple inputs.\n");
9b9d172d 536 }
537 count++;
538 }
539
540 if (!count) {
541 /* No SDVO device info is found */
28c97730 542 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
9b9d172d 543 }
544 return;
545}
32f9d658
ZW
546
547static void
548parse_driver_features(struct drm_i915_private *dev_priv,
549 struct bdb_header *bdb)
550{
e8ef3b4c 551 const struct bdb_driver_features *driver;
32f9d658 552
32f9d658 553 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
554 if (!driver)
555 return;
556
6fca55b1 557 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
41aa3448 558 dev_priv->vbt.edp_support = 1;
652c393a 559
5ceb0f9b 560 if (driver->dual_frequency)
652c393a 561 dev_priv->render_reclock_avail = true;
83a7280e
PB
562
563 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
564 /*
565 * If DRRS is not supported, drrs_type has to be set to 0.
566 * This is because, VBT is configured in such a way that
567 * static DRRS is 0 and DRRS not supported is represented by
568 * driver->drrs_enabled=false
569 */
570 if (!driver->drrs_enabled)
571 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
32f9d658
ZW
572}
573
500a8cc4
ZW
574static void
575parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
576{
e8ef3b4c
JN
577 const struct bdb_edp *edp;
578 const struct edp_power_seq *edp_pps;
579 const struct edp_link_params *edp_link_params;
500a8cc4
ZW
580
581 edp = find_section(bdb, BDB_EDP);
582 if (!edp) {
6fca55b1 583 if (dev_priv->vbt.edp_support)
9a30a61f 584 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
500a8cc4
ZW
585 return;
586 }
587
588 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
589 case EDP_18BPP:
41aa3448 590 dev_priv->vbt.edp_bpp = 18;
500a8cc4
ZW
591 break;
592 case EDP_24BPP:
41aa3448 593 dev_priv->vbt.edp_bpp = 24;
500a8cc4
ZW
594 break;
595 case EDP_30BPP:
41aa3448 596 dev_priv->vbt.edp_bpp = 30;
500a8cc4
ZW
597 break;
598 }
5ceb0f9b 599
9f0e7ff4
JB
600 /* Get the eDP sequencing and link info */
601 edp_pps = &edp->power_seqs[panel_type];
602 edp_link_params = &edp->link_params[panel_type];
5ceb0f9b 603
41aa3448 604 dev_priv->vbt.edp_pps = *edp_pps;
5ceb0f9b 605
e13e2b2c
JN
606 switch (edp_link_params->rate) {
607 case EDP_RATE_1_62:
608 dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
609 break;
610 case EDP_RATE_2_7:
611 dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
612 break;
613 default:
614 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
615 edp_link_params->rate);
616 break;
617 }
618
9f0e7ff4 619 switch (edp_link_params->lanes) {
e13e2b2c 620 case EDP_LANE_1:
41aa3448 621 dev_priv->vbt.edp_lanes = 1;
9f0e7ff4 622 break;
e13e2b2c 623 case EDP_LANE_2:
41aa3448 624 dev_priv->vbt.edp_lanes = 2;
9f0e7ff4 625 break;
e13e2b2c 626 case EDP_LANE_4:
41aa3448 627 dev_priv->vbt.edp_lanes = 4;
9f0e7ff4 628 break;
e13e2b2c
JN
629 default:
630 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
631 edp_link_params->lanes);
632 break;
9f0e7ff4 633 }
e13e2b2c 634
9f0e7ff4 635 switch (edp_link_params->preemphasis) {
e13e2b2c 636 case EDP_PREEMPHASIS_NONE:
bd60018a 637 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
9f0e7ff4 638 break;
e13e2b2c 639 case EDP_PREEMPHASIS_3_5dB:
bd60018a 640 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
9f0e7ff4 641 break;
e13e2b2c 642 case EDP_PREEMPHASIS_6dB:
bd60018a 643 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
9f0e7ff4 644 break;
e13e2b2c 645 case EDP_PREEMPHASIS_9_5dB:
bd60018a 646 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
9f0e7ff4 647 break;
e13e2b2c
JN
648 default:
649 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
650 edp_link_params->preemphasis);
651 break;
9f0e7ff4 652 }
e13e2b2c 653
9f0e7ff4 654 switch (edp_link_params->vswing) {
e13e2b2c 655 case EDP_VSWING_0_4V:
bd60018a 656 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
9f0e7ff4 657 break;
e13e2b2c 658 case EDP_VSWING_0_6V:
bd60018a 659 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
9f0e7ff4 660 break;
e13e2b2c 661 case EDP_VSWING_0_8V:
bd60018a 662 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
9f0e7ff4 663 break;
e13e2b2c 664 case EDP_VSWING_1_2V:
bd60018a 665 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
9f0e7ff4 666 break;
e13e2b2c
JN
667 default:
668 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
669 edp_link_params->vswing);
670 break;
9f0e7ff4 671 }
9a57f5bb
SJ
672
673 if (bdb->version >= 173) {
674 uint8_t vswing;
675
9e458034
SJ
676 /* Don't read from VBT if module parameter has valid value*/
677 if (i915.edp_vswing) {
678 dev_priv->edp_low_vswing = i915.edp_vswing == 1;
679 } else {
680 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
681 dev_priv->edp_low_vswing = vswing == 0;
682 }
9a57f5bb 683 }
500a8cc4
ZW
684}
685
bfd7ebda
RV
686static void
687parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
688{
e8ef3b4c
JN
689 const struct bdb_psr *psr;
690 const struct psr_table *psr_table;
bfd7ebda
RV
691
692 psr = find_section(bdb, BDB_PSR);
693 if (!psr) {
694 DRM_DEBUG_KMS("No PSR BDB found.\n");
695 return;
696 }
697
698 psr_table = &psr->psr_table[panel_type];
699
700 dev_priv->vbt.psr.full_link = psr_table->full_link;
701 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
702
703 /* Allowed VBT values goes from 0 to 15 */
704 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
705 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
706
707 switch (psr_table->lines_to_wait) {
708 case 0:
709 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
710 break;
711 case 1:
712 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
713 break;
714 case 2:
715 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
716 break;
717 case 3:
718 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
719 break;
720 default:
721 DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
722 psr_table->lines_to_wait);
723 break;
724 }
725
726 dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
727 dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
728}
729
d3b542fc
SK
730static u8 *goto_next_sequence(u8 *data, int *size)
731{
732 u16 len;
733 int tmp = *size;
734
735 if (--tmp < 0)
736 return NULL;
737
738 /* goto first element */
739 data++;
740 while (1) {
741 switch (*data) {
742 case MIPI_SEQ_ELEM_SEND_PKT:
743 /*
744 * skip by this element payload size
745 * skip elem id, command flag and data type
746 */
b0256cdc
SK
747 tmp -= 5;
748 if (tmp < 0)
d3b542fc
SK
749 return NULL;
750
751 data += 3;
752 len = *((u16 *)data);
753
b0256cdc
SK
754 tmp -= len;
755 if (tmp < 0)
d3b542fc
SK
756 return NULL;
757
758 /* skip by len */
759 data = data + 2 + len;
760 break;
761 case MIPI_SEQ_ELEM_DELAY:
762 /* skip by elem id, and delay is 4 bytes */
b0256cdc
SK
763 tmp -= 5;
764 if (tmp < 0)
d3b542fc
SK
765 return NULL;
766
767 data += 5;
768 break;
769 case MIPI_SEQ_ELEM_GPIO:
b0256cdc
SK
770 tmp -= 3;
771 if (tmp < 0)
d3b542fc
SK
772 return NULL;
773
774 data += 3;
775 break;
776 default:
777 DRM_ERROR("Unknown element\n");
778 return NULL;
779 }
780
781 /* end of sequence ? */
782 if (*data == 0)
783 break;
784 }
785
786 /* goto next sequence or end of block byte */
787 if (--tmp < 0)
788 return NULL;
789
790 data++;
791
792 /* update amount of data left for the sequence block to be parsed */
793 *size = tmp;
794 return data;
795}
796
d17c5443
SK
797static void
798parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
799{
e8ef3b4c
JN
800 const struct bdb_mipi_config *start;
801 const struct bdb_mipi_sequence *sequence;
802 const struct mipi_config *config;
803 const struct mipi_pps_data *pps;
804 u8 *data;
805 const u8 *seq_data;
d3b542fc
SK
806 int i, panel_id, seq_size;
807 u16 block_size;
808
3e6bd011
SK
809 /* parse MIPI blocks only if LFP type is MIPI */
810 if (!dev_priv->vbt.has_mipi)
811 return;
812
d3b542fc
SK
813 /* Initialize this to undefined indicating no generic MIPI support */
814 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
815
816 /* Block #40 is already parsed and panel_fixed_mode is
817 * stored in dev_priv->lfp_lvds_vbt_mode
818 * resuse this when needed
819 */
d17c5443 820
d3b542fc
SK
821 /* Parse #52 for panel index used from panel_type already
822 * parsed
823 */
824 start = find_section(bdb, BDB_MIPI_CONFIG);
825 if (!start) {
826 DRM_DEBUG_KMS("No MIPI config BDB found");
d17c5443
SK
827 return;
828 }
829
d3b542fc
SK
830 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
831 panel_type);
832
833 /*
834 * get hold of the correct configuration block and pps data as per
835 * the panel_type as index
836 */
837 config = &start->config[panel_type];
838 pps = &start->pps[panel_type];
839
840 /* store as of now full data. Trim when we realise all is not needed */
841 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
842 if (!dev_priv->vbt.dsi.config)
843 return;
844
845 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
846 if (!dev_priv->vbt.dsi.pps) {
847 kfree(dev_priv->vbt.dsi.config);
848 return;
849 }
850
851 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 852 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
d3b542fc
SK
853
854 /* Check if we have sequence block as well */
855 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
856 if (!sequence) {
857 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
858 return;
859 }
860
861 DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
862
863 block_size = get_blocksize(sequence);
864
865 /*
866 * parse the sequence block for individual sequences
867 */
868 dev_priv->vbt.dsi.seq_version = sequence->version;
869
870 seq_data = &sequence->data[0];
871
872 /*
873 * sequence block is variable length and hence we need to parse and
874 * get the sequence data for specific panel id
875 */
876 for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) {
877 panel_id = *seq_data;
878 seq_size = *((u16 *) (seq_data + 1));
879 if (panel_id == panel_type)
880 break;
881
882 /* skip the sequence including seq header of 3 bytes */
883 seq_data = seq_data + 3 + seq_size;
884 if ((seq_data - &sequence->data[0]) > block_size) {
885 DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n");
886 return;
887 }
888 }
889
890 if (i == MAX_MIPI_CONFIGURATIONS) {
891 DRM_ERROR("Sequence block detected but no valid configuration\n");
892 return;
893 }
894
895 /* check if found sequence is completely within the sequence block
896 * just being paranoid */
897 if (seq_size > block_size) {
898 DRM_ERROR("Corrupted sequence/size, bailing out\n");
899 return;
900 }
901
902 /* skip the panel id(1 byte) and seq size(2 bytes) */
903 dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL);
904 if (!dev_priv->vbt.dsi.data)
905 return;
906
907 /*
908 * loop into the sequence data and split into multiple sequneces
909 * There are only 5 types of sequences as of now
910 */
911 data = dev_priv->vbt.dsi.data;
912 dev_priv->vbt.dsi.size = seq_size;
913
914 /* two consecutive 0x00 indicate end of all sequences */
915 while (1) {
916 int seq_id = *data;
917 if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) {
918 dev_priv->vbt.dsi.sequence[seq_id] = data;
919 DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id);
920 } else {
921 DRM_ERROR("undefined sequence\n");
922 goto err;
923 }
924
925 /* partial parsing to skip elements */
926 data = goto_next_sequence(data, &seq_size);
927
928 if (data == NULL) {
929 DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n");
930 goto err;
931 }
932
933 if (*data == 0)
934 break; /* end of sequence reached */
935 }
936
937 DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n");
938 return;
939err:
940 kfree(dev_priv->vbt.dsi.data);
941 dev_priv->vbt.dsi.data = NULL;
942
943 /* error during parsing so set all pointers to null
944 * because of partial parsing */
ed3b6679 945 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
d17c5443
SK
946}
947
6acab15a
PZ
948static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
949 struct bdb_header *bdb)
950{
951 union child_device_config *it, *child = NULL;
952 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
953 uint8_t hdmi_level_shift;
954 int i, j;
554d6af5 955 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
6bf19e7c 956 uint8_t aux_channel;
6acab15a
PZ
957 /* Each DDI port can have more than one value on the "DVO Port" field,
958 * so look for all the possible values for each port and abort if more
959 * than one is found. */
960 int dvo_ports[][2] = {
961 {DVO_PORT_HDMIA, DVO_PORT_DPA},
962 {DVO_PORT_HDMIB, DVO_PORT_DPB},
963 {DVO_PORT_HDMIC, DVO_PORT_DPC},
964 {DVO_PORT_HDMID, DVO_PORT_DPD},
965 {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ },
966 };
967
968 /* Find the child device to use, abort if more than one found. */
969 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
970 it = dev_priv->vbt.child_dev + i;
971
972 for (j = 0; j < 2; j++) {
973 if (dvo_ports[port][j] == -1)
974 break;
975
976 if (it->common.dvo_port == dvo_ports[port][j]) {
977 if (child) {
978 DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n",
979 port_name(port));
980 return;
981 }
982 child = it;
983 }
984 }
985 }
986 if (!child)
987 return;
988
6bf19e7c
PZ
989 aux_channel = child->raw[25];
990
78eb06c3
VS
991 is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
992 is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
993 is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
994 is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
995 is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 996
311a2094
PZ
997 info->supports_dvi = is_dvi;
998 info->supports_hdmi = is_hdmi;
999 info->supports_dp = is_dp;
1000
554d6af5
PZ
1001 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
1002 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
1003
1004 if (is_edp && is_dvi)
1005 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
1006 port_name(port));
1007 if (is_crt && port != PORT_E)
1008 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
1009 if (is_crt && (is_dvi || is_dp))
1010 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
1011 port_name(port));
1012 if (is_dvi && (port == PORT_A || port == PORT_E))
9b13494c 1013 DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port));
554d6af5
PZ
1014 if (!is_dvi && !is_dp && !is_crt)
1015 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
1016 port_name(port));
1017 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
1018 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
6bf19e7c
PZ
1019
1020 if (is_dvi) {
1021 if (child->common.ddc_pin == 0x05 && port != PORT_B)
1022 DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
1023 if (child->common.ddc_pin == 0x04 && port != PORT_C)
1024 DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
1025 if (child->common.ddc_pin == 0x06 && port != PORT_D)
1026 DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
1027 }
1028
1029 if (is_dp) {
1030 if (aux_channel == 0x40 && port != PORT_A)
1031 DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
1032 if (aux_channel == 0x10 && port != PORT_B)
1033 DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
1034 if (aux_channel == 0x20 && port != PORT_C)
1035 DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
1036 if (aux_channel == 0x30 && port != PORT_D)
1037 DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
1038 }
1039
6acab15a
PZ
1040 if (bdb->version >= 158) {
1041 /* The VBT HDMI level shift values match the table we have. */
1042 hdmi_level_shift = child->raw[7] & 0xF;
ce4dd49e
DL
1043 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1044 port_name(port),
1045 hdmi_level_shift);
1046 info->hdmi_level_shift = hdmi_level_shift;
6acab15a
PZ
1047 }
1048}
1049
1050static void parse_ddi_ports(struct drm_i915_private *dev_priv,
1051 struct bdb_header *bdb)
1052{
1053 struct drm_device *dev = dev_priv->dev;
1054 enum port port;
1055
1056 if (!HAS_DDI(dev))
1057 return;
1058
1059 if (!dev_priv->vbt.child_dev_num)
1060 return;
1061
1062 if (bdb->version < 155)
1063 return;
1064
1065 for (port = PORT_A; port < I915_MAX_PORTS; port++)
1066 parse_ddi_port(dev_priv, port, bdb);
1067}
1068
6363ee6f
ZY
1069static void
1070parse_device_mapping(struct drm_i915_private *dev_priv,
1071 struct bdb_header *bdb)
1072{
e8ef3b4c
JN
1073 const struct bdb_general_definitions *p_defs;
1074 const union child_device_config *p_child;
1075 union child_device_config *child_dev_ptr;
6363ee6f
ZY
1076 int i, child_device_num, count;
1077 u16 block_size;
1078
1079 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1080 if (!p_defs) {
44834a67 1081 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1082 return;
1083 }
90e4f159
VS
1084 if (p_defs->child_dev_size < sizeof(*p_child)) {
1085 DRM_ERROR("General definiton block child device size is too small.\n");
6363ee6f
ZY
1086 return;
1087 }
1088 /* get the block size of general definitions */
1089 block_size = get_blocksize(p_defs);
1090 /* get the number of child device */
1091 child_device_num = (block_size - sizeof(*p_defs)) /
90e4f159 1092 p_defs->child_dev_size;
6363ee6f
ZY
1093 count = 0;
1094 /* get the number of child device that is present */
1095 for (i = 0; i < child_device_num; i++) {
90e4f159 1096 p_child = child_device_ptr(p_defs, i);
768f69c9 1097 if (!p_child->common.device_type) {
6363ee6f
ZY
1098 /* skip the device block if device type is invalid */
1099 continue;
1100 }
1101 count++;
1102 }
1103 if (!count) {
0206e353 1104 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
6363ee6f
ZY
1105 return;
1106 }
41aa3448
RV
1107 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
1108 if (!dev_priv->vbt.child_dev) {
6363ee6f
ZY
1109 DRM_DEBUG_KMS("No memory space for child device\n");
1110 return;
1111 }
1112
41aa3448 1113 dev_priv->vbt.child_dev_num = count;
6363ee6f
ZY
1114 count = 0;
1115 for (i = 0; i < child_device_num; i++) {
90e4f159 1116 p_child = child_device_ptr(p_defs, i);
768f69c9 1117 if (!p_child->common.device_type) {
6363ee6f
ZY
1118 /* skip the device block if device type is invalid */
1119 continue;
1120 }
3e6bd011
SK
1121
1122 if (p_child->common.dvo_port >= DVO_PORT_MIPIA
1123 && p_child->common.dvo_port <= DVO_PORT_MIPID
1124 &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
1125 DRM_DEBUG_KMS("Found MIPI as LFP\n");
1126 dev_priv->vbt.has_mipi = 1;
1127 dev_priv->vbt.dsi.port = p_child->common.dvo_port;
1128 }
1129
41aa3448 1130 child_dev_ptr = dev_priv->vbt.child_dev + count;
6363ee6f 1131 count++;
e8ef3b4c 1132 memcpy(child_dev_ptr, p_child, sizeof(*p_child));
6363ee6f
ZY
1133 }
1134 return;
1135}
44834a67 1136
6a04002b
SQ
1137static void
1138init_vbt_defaults(struct drm_i915_private *dev_priv)
1139{
9a4114ff 1140 struct drm_device *dev = dev_priv->dev;
6acab15a 1141 enum port port;
9a4114ff 1142
988c7015 1143 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
6a04002b 1144
56c4b63a
JN
1145 /* Default to having backlight */
1146 dev_priv->vbt.backlight.present = true;
1147
6a04002b 1148 /* LFP panel data */
41aa3448
RV
1149 dev_priv->vbt.lvds_dither = 1;
1150 dev_priv->vbt.lvds_vbt = 0;
6a04002b
SQ
1151
1152 /* SDVO panel data */
41aa3448 1153 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1154
1155 /* general features */
41aa3448
RV
1156 dev_priv->vbt.int_tv_support = 1;
1157 dev_priv->vbt.int_crt_support = 1;
9a4114ff
BF
1158
1159 /* Default to using SSC */
41aa3448 1160 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1161 /*
1162 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1163 * clock for LVDS.
1164 */
1165 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
1166 !HAS_PCH_SPLIT(dev));
e91e941b 1167 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
6acab15a
PZ
1168
1169 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
311a2094
PZ
1170 struct ddi_vbt_port_info *info =
1171 &dev_priv->vbt.ddi_port_info[port];
1172
ce4dd49e 1173 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
311a2094
PZ
1174
1175 info->supports_dvi = (port != PORT_A && port != PORT_E);
1176 info->supports_hdmi = info->supports_dvi;
1177 info->supports_dp = (port != PORT_E);
6acab15a 1178 }
6a04002b
SQ
1179}
1180
bbe1c274 1181static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
25e341cf
DV
1182{
1183 DRM_DEBUG_KMS("Falling back to manually reading VBT from "
1184 "VBIOS ROM for %s\n",
1185 id->ident);
1186 return 1;
1187}
1188
1189static const struct dmi_system_id intel_no_opregion_vbt[] = {
1190 {
1191 .callback = intel_no_opregion_vbt_callback,
1192 .ident = "ThinkCentre A57",
1193 .matches = {
1194 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1195 DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"),
1196 },
1197 },
1198 { }
1199};
1200
3dd4e846
CW
1201static struct bdb_header *validate_vbt(char *base, size_t size,
1202 struct vbt_header *vbt,
1203 const char *source)
1204{
1205 size_t offset;
1206 struct bdb_header *bdb;
1207
1208 if (vbt == NULL) {
1209 DRM_DEBUG_DRIVER("VBT signature missing\n");
1210 return NULL;
1211 }
1212
1213 offset = (char *)vbt - base;
1214 if (offset + sizeof(struct vbt_header) > size) {
1215 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1216 return NULL;
1217 }
1218
1219 if (memcmp(vbt->signature, "$VBT", 4)) {
1220 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1221 return NULL;
1222 }
1223
1224 offset += vbt->bdb_offset;
1225 if (offset + sizeof(struct bdb_header) > size) {
1226 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1227 return NULL;
1228 }
1229
1230 bdb = (struct bdb_header *)(base + offset);
1231 if (offset + bdb->bdb_size > size) {
1232 DRM_DEBUG_DRIVER("BDB incomplete\n");
1233 return NULL;
1234 }
1235
1236 DRM_DEBUG_KMS("Using VBT from %s: %20s\n",
1237 source, vbt->signature);
1238 return bdb;
1239}
1240
79e53945 1241/**
6d139a87 1242 * intel_parse_bios - find VBT and initialize settings from the BIOS
79e53945
JB
1243 * @dev: DRM device
1244 *
1245 * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
1246 * to appropriate values.
1247 *
79e53945
JB
1248 * Returns 0 on success, nonzero on failure.
1249 */
0317c6ce 1250int
6d139a87 1251intel_parse_bios(struct drm_device *dev)
79e53945
JB
1252{
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 struct pci_dev *pdev = dev->pdev;
44834a67
CW
1255 struct bdb_header *bdb = NULL;
1256 u8 __iomem *bios = NULL;
1257
ab5c608b
BW
1258 if (HAS_PCH_NOP(dev))
1259 return -ENODEV;
1260
6a04002b 1261 init_vbt_defaults(dev_priv);
f899fc64 1262
44834a67 1263 /* XXX Should this validation be moved to intel_opregion.c? */
3dd4e846
CW
1264 if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
1265 bdb = validate_vbt((char *)dev_priv->opregion.header, OPREGION_SIZE,
1266 (struct vbt_header *)dev_priv->opregion.vbt,
1267 "OpRegion");
79e53945 1268
44834a67 1269 if (bdb == NULL) {
3dd4e846 1270 size_t i, size;
79e53945 1271
44834a67
CW
1272 bios = pci_map_rom(pdev, &size);
1273 if (!bios)
1274 return -1;
1275
1276 /* Scour memory looking for the VBT signature */
1277 for (i = 0; i + 4 < size; i++) {
3dd4e846
CW
1278 if (memcmp(bios + i, "$VBT", 4) == 0) {
1279 bdb = validate_vbt(bios, size,
1280 (struct vbt_header *)(bios + i),
1281 "PCI ROM");
44834a67
CW
1282 break;
1283 }
1284 }
1285
3dd4e846 1286 if (!bdb) {
44834a67
CW
1287 pci_unmap_rom(pdev, bios);
1288 return -1;
1289 }
44834a67 1290 }
79e53945
JB
1291
1292 /* Grab useful general definitions */
1293 parse_general_features(dev_priv, bdb);
db545019 1294 parse_general_definitions(dev_priv, bdb);
88631706 1295 parse_lfp_panel_data(dev_priv, bdb);
f00076d2 1296 parse_lfp_backlight(dev_priv, bdb);
88631706 1297 parse_sdvo_panel_data(dev_priv, bdb);
9b9d172d 1298 parse_sdvo_device_mapping(dev_priv, bdb);
6363ee6f 1299 parse_device_mapping(dev_priv, bdb);
32f9d658 1300 parse_driver_features(dev_priv, bdb);
500a8cc4 1301 parse_edp(dev_priv, bdb);
bfd7ebda 1302 parse_psr(dev_priv, bdb);
d17c5443 1303 parse_mipi(dev_priv, bdb);
6acab15a 1304 parse_ddi_ports(dev_priv, bdb);
32f9d658 1305
44834a67
CW
1306 if (bios)
1307 pci_unmap_rom(pdev, bios);
79e53945
JB
1308
1309 return 0;
1310}
6d139a87
BF
1311
1312/* Ensure that vital registers have been initialised, even if the BIOS
1313 * is absent or just failing to do its job.
1314 */
1315void intel_setup_bios(struct drm_device *dev)
1316{
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318
1319 /* Set the Panel Power On/Off timings if uninitialized. */
42d42e7e
DL
1320 if (!HAS_PCH_SPLIT(dev) &&
1321 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
6d139a87
BF
1322 /* Set T2 to 40ms and T5 to 200ms */
1323 I915_WRITE(PP_ON_DELAYS, 0x019007d0);
1324
1325 /* Set T3 to 35ms and Tx to 200ms */
1326 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
1327 }
1328}