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79e53945 | 1 | /* |
f01eca2e | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #ifndef _I830_BIOS_H_ | |
29 | #define _I830_BIOS_H_ | |
30 | ||
760285e7 | 31 | #include <drm/drmP.h> |
79e53945 JB |
32 | |
33 | struct vbt_header { | |
34 | u8 signature[20]; /**< Always starts with 'VBT$' */ | |
35 | u16 version; /**< decimal */ | |
36 | u16 header_size; /**< in bytes */ | |
37 | u16 vbt_size; /**< in bytes */ | |
38 | u8 vbt_checksum; | |
39 | u8 reserved0; | |
40 | u32 bdb_offset; /**< from beginning of VBT */ | |
41 | u32 aim_offset[4]; /**< from beginning of VBT */ | |
42 | } __attribute__((packed)); | |
43 | ||
44 | struct bdb_header { | |
45 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ | |
46 | u16 version; /**< decimal */ | |
47 | u16 header_size; /**< in bytes */ | |
48 | u16 bdb_size; /**< in bytes */ | |
49 | }; | |
50 | ||
51 | /* strictly speaking, this is a "skip" block, but it has interesting info */ | |
52 | struct vbios_data { | |
53 | u8 type; /* 0 == desktop, 1 == mobile */ | |
54 | u8 relstage; | |
55 | u8 chipset; | |
56 | u8 lvds_present:1; | |
57 | u8 tv_present:1; | |
58 | u8 rsvd2:6; /* finish byte */ | |
59 | u8 rsvd3[4]; | |
60 | u8 signon[155]; | |
61 | u8 copyright[61]; | |
62 | u16 code_segment; | |
63 | u8 dos_boot_mode; | |
64 | u8 bandwidth_percent; | |
65 | u8 rsvd4; /* popup memory size */ | |
66 | u8 resize_pci_bios; | |
67 | u8 rsvd5; /* is crt already on ddc2 */ | |
68 | } __attribute__((packed)); | |
69 | ||
70 | /* | |
71 | * There are several types of BIOS data blocks (BDBs), each block has | |
72 | * an ID and size in the first 3 bytes (ID in first, size in next 2). | |
73 | * Known types are listed below. | |
74 | */ | |
75 | #define BDB_GENERAL_FEATURES 1 | |
76 | #define BDB_GENERAL_DEFINITIONS 2 | |
77 | #define BDB_OLD_TOGGLE_LIST 3 | |
78 | #define BDB_MODE_SUPPORT_LIST 4 | |
79 | #define BDB_GENERIC_MODE_TABLE 5 | |
80 | #define BDB_EXT_MMIO_REGS 6 | |
81 | #define BDB_SWF_IO 7 | |
82 | #define BDB_SWF_MMIO 8 | |
83 | #define BDB_DOT_CLOCK_TABLE 9 | |
84 | #define BDB_MODE_REMOVAL_TABLE 10 | |
85 | #define BDB_CHILD_DEVICE_TABLE 11 | |
86 | #define BDB_DRIVER_FEATURES 12 | |
87 | #define BDB_DRIVER_PERSISTENCE 13 | |
88 | #define BDB_EXT_TABLE_PTRS 14 | |
89 | #define BDB_DOT_CLOCK_OVERRIDE 15 | |
90 | #define BDB_DISPLAY_SELECT 16 | |
91 | /* 17 rsvd */ | |
92 | #define BDB_DRIVER_ROTATION 18 | |
93 | #define BDB_DISPLAY_REMOVE 19 | |
94 | #define BDB_OEM_CUSTOM 20 | |
95 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ | |
96 | #define BDB_SDVO_LVDS_OPTIONS 22 | |
97 | #define BDB_SDVO_PANEL_DTDS 23 | |
98 | #define BDB_SDVO_LVDS_PNP_IDS 24 | |
99 | #define BDB_SDVO_LVDS_POWER_SEQ 25 | |
100 | #define BDB_TV_OPTIONS 26 | |
500a8cc4 | 101 | #define BDB_EDP 27 |
79e53945 JB |
102 | #define BDB_LVDS_OPTIONS 40 |
103 | #define BDB_LVDS_LFP_DATA_PTRS 41 | |
104 | #define BDB_LVDS_LFP_DATA 42 | |
105 | #define BDB_LVDS_BACKLIGHT 43 | |
106 | #define BDB_LVDS_POWER 44 | |
d17c5443 | 107 | #define BDB_MIPI 50 |
79e53945 JB |
108 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
109 | ||
110 | struct bdb_general_features { | |
111 | /* bits 1 */ | |
112 | u8 panel_fitting:2; | |
113 | u8 flexaim:1; | |
114 | u8 msg_enable:1; | |
115 | u8 clear_screen:3; | |
116 | u8 color_flip:1; | |
117 | ||
118 | /* bits 2 */ | |
119 | u8 download_ext_vbt:1; | |
120 | u8 enable_ssc:1; | |
121 | u8 ssc_freq:1; | |
122 | u8 enable_lfp_on_override:1; | |
123 | u8 disable_ssc_ddt:1; | |
abd06860 KP |
124 | u8 rsvd7:1; |
125 | u8 display_clock_mode:1; | |
126 | u8 rsvd8:1; /* finish byte */ | |
79e53945 JB |
127 | |
128 | /* bits 3 */ | |
129 | u8 disable_smooth_vision:1; | |
130 | u8 single_dvi:1; | |
3f704fa2 PZ |
131 | u8 rsvd9:1; |
132 | u8 fdi_rx_polarity_inverted:1; | |
133 | u8 rsvd10:4; /* finish byte */ | |
79e53945 JB |
134 | |
135 | /* bits 4 */ | |
136 | u8 legacy_monitor_detect; | |
137 | ||
138 | /* bits 5 */ | |
139 | u8 int_crt_support:1; | |
140 | u8 int_tv_support:1; | |
d2830bdb KP |
141 | u8 int_efp_support:1; |
142 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ | |
143 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ | |
144 | u8 rsvd11:3; /* finish byte */ | |
79e53945 JB |
145 | } __attribute__((packed)); |
146 | ||
59a036cf | 147 | /* pre-915 */ |
148 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ | |
149 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ | |
150 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ | |
151 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ | |
152 | ||
153 | /* Pre 915 */ | |
154 | #define DEVICE_TYPE_NONE 0x00 | |
155 | #define DEVICE_TYPE_CRT 0x01 | |
156 | #define DEVICE_TYPE_TV 0x09 | |
157 | #define DEVICE_TYPE_EFP 0x12 | |
158 | #define DEVICE_TYPE_LFP 0x22 | |
159 | /* On 915+ */ | |
160 | #define DEVICE_TYPE_CRT_DPMS 0x6001 | |
161 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 | |
162 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 | |
163 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 | |
164 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c | |
165 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 | |
166 | #define DEVICE_TYPE_TV_SCART 0x0209 | |
167 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 | |
168 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 | |
169 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 | |
170 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 | |
171 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 | |
172 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 | |
173 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 | |
174 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 | |
175 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 | |
176 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 | |
177 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 | |
178 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 | |
179 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 | |
180 | ||
181 | #define DEVICE_CFG_NONE 0x00 | |
182 | #define DEVICE_CFG_12BIT_DVOB 0x01 | |
183 | #define DEVICE_CFG_12BIT_DVOC 0x02 | |
184 | #define DEVICE_CFG_24BIT_DVOBC 0x09 | |
185 | #define DEVICE_CFG_24BIT_DVOCB 0x0a | |
186 | #define DEVICE_CFG_DUAL_DVOB 0x11 | |
187 | #define DEVICE_CFG_DUAL_DVOC 0x12 | |
188 | #define DEVICE_CFG_DUAL_DVOBC 0x13 | |
189 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 | |
190 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a | |
191 | ||
192 | #define DEVICE_WIRE_NONE 0x00 | |
193 | #define DEVICE_WIRE_DVOB 0x01 | |
194 | #define DEVICE_WIRE_DVOC 0x02 | |
195 | #define DEVICE_WIRE_DVOBC 0x03 | |
196 | #define DEVICE_WIRE_DVOBB 0x05 | |
197 | #define DEVICE_WIRE_DVOCC 0x06 | |
198 | #define DEVICE_WIRE_DVOB_MASTER 0x0d | |
199 | #define DEVICE_WIRE_DVOC_MASTER 0x0e | |
200 | ||
201 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ | |
202 | #define DEVICE_PORT_DVOB 0x01 | |
203 | #define DEVICE_PORT_DVOC 0x02 | |
204 | ||
768f69c9 PZ |
205 | /* We used to keep this struct but without any version control. We should avoid |
206 | * using it in the future, but it should be safe to keep using it in the old | |
207 | * code. */ | |
208 | struct old_child_dev_config { | |
59a036cf | 209 | u16 handle; |
210 | u16 device_type; | |
46eb3036 | 211 | u8 device_id[10]; /* ascii string */ |
59a036cf | 212 | u16 addin_offset; |
213 | u8 dvo_port; /* See Device_PORT_* above */ | |
214 | u8 i2c_pin; | |
215 | u8 slave_addr; | |
216 | u8 ddc_pin; | |
217 | u16 edid_ptr; | |
218 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ | |
219 | u8 dvo2_port; | |
220 | u8 i2c2_pin; | |
221 | u8 slave2_addr; | |
222 | u8 ddc2_pin; | |
223 | u8 capabilities; | |
224 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ | |
225 | u8 dvo2_wiring; | |
226 | u16 extended_type; | |
227 | u8 dvo_function; | |
228 | } __attribute__((packed)); | |
229 | ||
768f69c9 PZ |
230 | /* This one contains field offsets that are known to be common for all BDB |
231 | * versions. Notice that the meaning of the contents contents may still change, | |
232 | * but at least the offsets are consistent. */ | |
233 | struct common_child_dev_config { | |
234 | u16 handle; | |
235 | u16 device_type; | |
236 | u8 not_common1[12]; | |
237 | u8 dvo_port; | |
238 | u8 not_common2[2]; | |
239 | u8 ddc_pin; | |
240 | u16 edid_ptr; | |
241 | } __attribute__((packed)); | |
242 | ||
243 | /* This field changes depending on the BDB version, so the most reliable way to | |
244 | * read it is by checking the BDB version and reading the raw pointer. */ | |
245 | union child_device_config { | |
246 | /* This one is safe to be used anywhere, but the code should still check | |
247 | * the BDB version. */ | |
248 | u8 raw[33]; | |
249 | /* This one should only be kept for legacy code. */ | |
250 | struct old_child_dev_config old; | |
251 | /* This one should also be safe to use anywhere, even without version | |
252 | * checks. */ | |
253 | struct common_child_dev_config common; | |
254 | }; | |
255 | ||
79e53945 JB |
256 | struct bdb_general_definitions { |
257 | /* DDC GPIO */ | |
258 | u8 crt_ddc_gmbus_pin; | |
259 | ||
260 | /* DPMS bits */ | |
261 | u8 dpms_acpi:1; | |
262 | u8 skip_boot_crt_detect:1; | |
263 | u8 dpms_aim:1; | |
264 | u8 rsvd1:5; /* finish byte */ | |
265 | ||
266 | /* boot device bits */ | |
267 | u8 boot_display[2]; | |
268 | u8 child_dev_size; | |
269 | ||
59a036cf | 270 | /* |
271 | * Device info: | |
272 | * If TV is present, it'll be at devices[0]. | |
273 | * LVDS will be next, either devices[0] or [1], if present. | |
274 | * On some platforms the number of device is 6. But could be as few as | |
275 | * 4 if both TV and LVDS are missing. | |
276 | * And the device num is related with the size of general definition | |
277 | * block. It is obtained by using the following formula: | |
278 | * number = (block_size - sizeof(bdb_general_definitions))/ | |
0206e353 | 279 | * sizeof(child_device_config); |
59a036cf | 280 | */ |
768f69c9 | 281 | union child_device_config devices[0]; |
59a036cf | 282 | } __attribute__((packed)); |
79e53945 JB |
283 | |
284 | struct bdb_lvds_options { | |
285 | u8 panel_type; | |
286 | u8 rsvd1; | |
287 | /* LVDS capabilities, stored in a dword */ | |
79e53945 | 288 | u8 pfit_mode:2; |
2b5cde2b LP |
289 | u8 pfit_text_mode_enhanced:1; |
290 | u8 pfit_gfx_mode_enhanced:1; | |
291 | u8 pfit_ratio_auto:1; | |
292 | u8 pixel_dither:1; | |
293 | u8 lvds_edid:1; | |
294 | u8 rsvd2:1; | |
79e53945 JB |
295 | u8 rsvd4; |
296 | } __attribute__((packed)); | |
297 | ||
298 | /* LFP pointer table contains entries to the struct below */ | |
299 | struct bdb_lvds_lfp_data_ptr { | |
300 | u16 fp_timing_offset; /* offsets are from start of bdb */ | |
301 | u8 fp_table_size; | |
302 | u16 dvo_timing_offset; | |
303 | u8 dvo_table_size; | |
304 | u16 panel_pnp_id_offset; | |
305 | u8 pnp_table_size; | |
306 | } __attribute__((packed)); | |
307 | ||
308 | struct bdb_lvds_lfp_data_ptrs { | |
309 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ | |
310 | struct bdb_lvds_lfp_data_ptr ptr[16]; | |
311 | } __attribute__((packed)); | |
312 | ||
313 | /* LFP data has 3 blocks per entry */ | |
314 | struct lvds_fp_timing { | |
315 | u16 x_res; | |
316 | u16 y_res; | |
317 | u32 lvds_reg; | |
318 | u32 lvds_reg_val; | |
319 | u32 pp_on_reg; | |
320 | u32 pp_on_reg_val; | |
321 | u32 pp_off_reg; | |
322 | u32 pp_off_reg_val; | |
323 | u32 pp_cycle_reg; | |
324 | u32 pp_cycle_reg_val; | |
325 | u32 pfit_reg; | |
326 | u32 pfit_reg_val; | |
327 | u16 terminator; | |
328 | } __attribute__((packed)); | |
329 | ||
330 | struct lvds_dvo_timing { | |
331 | u16 clock; /**< In 10khz */ | |
332 | u8 hactive_lo; | |
333 | u8 hblank_lo; | |
334 | u8 hblank_hi:4; | |
335 | u8 hactive_hi:4; | |
336 | u8 vactive_lo; | |
337 | u8 vblank_lo; | |
338 | u8 vblank_hi:4; | |
339 | u8 vactive_hi:4; | |
340 | u8 hsync_off_lo; | |
341 | u8 hsync_pulse_width; | |
342 | u8 vsync_pulse_width:4; | |
343 | u8 vsync_off:4; | |
344 | u8 rsvd0:6; | |
345 | u8 hsync_off_hi:2; | |
346 | u8 h_image; | |
347 | u8 v_image; | |
348 | u8 max_hv; | |
349 | u8 h_border; | |
350 | u8 v_border; | |
351 | u8 rsvd1:3; | |
352 | u8 digital:2; | |
353 | u8 vsync_positive:1; | |
354 | u8 hsync_positive:1; | |
355 | u8 rsvd2:1; | |
356 | } __attribute__((packed)); | |
357 | ||
358 | struct lvds_pnp_id { | |
359 | u16 mfg_name; | |
360 | u16 product_code; | |
361 | u32 serial; | |
362 | u8 mfg_week; | |
363 | u8 mfg_year; | |
364 | } __attribute__((packed)); | |
365 | ||
366 | struct bdb_lvds_lfp_data_entry { | |
367 | struct lvds_fp_timing fp_timing; | |
368 | struct lvds_dvo_timing dvo_timing; | |
369 | struct lvds_pnp_id pnp_id; | |
370 | } __attribute__((packed)); | |
371 | ||
372 | struct bdb_lvds_lfp_data { | |
373 | struct bdb_lvds_lfp_data_entry data[16]; | |
374 | } __attribute__((packed)); | |
375 | ||
376 | struct aimdb_header { | |
377 | char signature[16]; | |
378 | char oem_device[20]; | |
379 | u16 aimdb_version; | |
380 | u16 aimdb_header_size; | |
381 | u16 aimdb_size; | |
382 | } __attribute__((packed)); | |
383 | ||
384 | struct aimdb_block { | |
385 | u8 aimdb_id; | |
386 | u16 aimdb_size; | |
387 | } __attribute__((packed)); | |
388 | ||
389 | struct vch_panel_data { | |
390 | u16 fp_timing_offset; | |
391 | u8 fp_timing_size; | |
392 | u16 dvo_timing_offset; | |
393 | u8 dvo_timing_size; | |
394 | u16 text_fitting_offset; | |
395 | u8 text_fitting_size; | |
396 | u16 graphics_fitting_offset; | |
397 | u8 graphics_fitting_size; | |
398 | } __attribute__((packed)); | |
399 | ||
400 | struct vch_bdb_22 { | |
401 | struct aimdb_block aimdb_block; | |
402 | struct vch_panel_data panels[16]; | |
403 | } __attribute__((packed)); | |
404 | ||
88631706 ML |
405 | struct bdb_sdvo_lvds_options { |
406 | u8 panel_backlight; | |
407 | u8 h40_set_panel_type; | |
408 | u8 panel_type; | |
409 | u8 ssc_clk_freq; | |
410 | u16 als_low_trip; | |
411 | u16 als_high_trip; | |
412 | u8 sclalarcoeff_tab_row_num; | |
413 | u8 sclalarcoeff_tab_row_size; | |
414 | u8 coefficient[8]; | |
415 | u8 panel_misc_bits_1; | |
416 | u8 panel_misc_bits_2; | |
417 | u8 panel_misc_bits_3; | |
418 | u8 panel_misc_bits_4; | |
419 | } __attribute__((packed)); | |
420 | ||
421 | ||
32f9d658 ZW |
422 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
423 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 | |
424 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 | |
425 | #define BDB_DRIVER_FEATURE_EDP 3 | |
426 | ||
427 | struct bdb_driver_features { | |
428 | u8 boot_dev_algorithm:1; | |
429 | u8 block_display_switch:1; | |
430 | u8 allow_display_switch:1; | |
431 | u8 hotplug_dvo:1; | |
432 | u8 dual_view_zoom:1; | |
433 | u8 int15h_hook:1; | |
434 | u8 sprite_in_clone:1; | |
435 | u8 primary_lfp_id:1; | |
436 | ||
437 | u16 boot_mode_x; | |
438 | u16 boot_mode_y; | |
439 | u8 boot_mode_bpp; | |
440 | u8 boot_mode_refresh; | |
441 | ||
442 | u16 enable_lfp_primary:1; | |
443 | u16 selective_mode_pruning:1; | |
444 | u16 dual_frequency:1; | |
445 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ | |
446 | u16 nt_clone_support:1; | |
447 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ | |
448 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ | |
449 | u16 cui_aspect_scaling:1; | |
450 | u16 preserve_aspect_ratio:1; | |
451 | u16 sdvo_device_power_down:1; | |
452 | u16 crt_hotplug:1; | |
453 | u16 lvds_config:2; | |
454 | u16 tv_hotplug:1; | |
455 | u16 hdmi_config:2; | |
456 | ||
457 | u8 static_display:1; | |
458 | u8 reserved2:7; | |
459 | u16 legacy_crt_max_x; | |
460 | u16 legacy_crt_max_y; | |
461 | u8 legacy_crt_max_refresh; | |
462 | ||
463 | u8 hdmi_termination; | |
464 | u8 custom_vbt_version; | |
465 | } __attribute__((packed)); | |
466 | ||
500a8cc4 ZW |
467 | #define EDP_18BPP 0 |
468 | #define EDP_24BPP 1 | |
469 | #define EDP_30BPP 2 | |
470 | #define EDP_RATE_1_62 0 | |
471 | #define EDP_RATE_2_7 1 | |
472 | #define EDP_LANE_1 0 | |
473 | #define EDP_LANE_2 1 | |
474 | #define EDP_LANE_4 3 | |
475 | #define EDP_PREEMPHASIS_NONE 0 | |
476 | #define EDP_PREEMPHASIS_3_5dB 1 | |
477 | #define EDP_PREEMPHASIS_6dB 2 | |
478 | #define EDP_PREEMPHASIS_9_5dB 3 | |
479 | #define EDP_VSWING_0_4V 0 | |
480 | #define EDP_VSWING_0_6V 1 | |
481 | #define EDP_VSWING_0_8V 2 | |
482 | #define EDP_VSWING_1_2V 3 | |
483 | ||
484 | struct edp_power_seq { | |
f01eca2e KP |
485 | u16 t1_t3; |
486 | u16 t8; | |
500a8cc4 ZW |
487 | u16 t9; |
488 | u16 t10; | |
f01eca2e | 489 | u16 t11_t12; |
500a8cc4 ZW |
490 | } __attribute__ ((packed)); |
491 | ||
492 | struct edp_link_params { | |
493 | u8 rate:4; | |
494 | u8 lanes:4; | |
495 | u8 preemphasis:4; | |
496 | u8 vswing:4; | |
497 | } __attribute__ ((packed)); | |
498 | ||
499 | struct bdb_edp { | |
500 | struct edp_power_seq power_seqs[16]; | |
501 | u32 color_depth; | |
500a8cc4 | 502 | struct edp_link_params link_params[16]; |
96c0a2f5 RJ |
503 | u32 sdrrs_msa_timing_delay; |
504 | ||
505 | /* ith bit indicates enabled/disabled for (i+1)th panel */ | |
506 | u16 edp_s3d_feature; | |
507 | u16 edp_t3_optimization; | |
500a8cc4 ZW |
508 | } __attribute__ ((packed)); |
509 | ||
6d139a87 | 510 | void intel_setup_bios(struct drm_device *dev); |
0317c6ce | 511 | int intel_parse_bios(struct drm_device *dev); |
79e53945 JB |
512 | |
513 | /* | |
514 | * Driver<->VBIOS interaction occurs through scratch bits in | |
515 | * GR18 & SWF*. | |
516 | */ | |
517 | ||
518 | /* GR18 bits are set on display switch and hotkey events */ | |
519 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ | |
520 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ | |
521 | #define GR18_HK_NONE (0x0<<3) | |
522 | #define GR18_HK_LFP_STRETCH (0x1<<3) | |
523 | #define GR18_HK_TOGGLE_DISP (0x2<<3) | |
524 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ | |
525 | #define GR18_HK_POPUP_DISABLED (0x6<<3) | |
526 | #define GR18_HK_POPUP_ENABLED (0x7<<3) | |
527 | #define GR18_HK_PFIT (0x8<<3) | |
528 | #define GR18_HK_APM_CHANGE (0xa<<3) | |
529 | #define GR18_HK_MULTIPLE (0xc<<3) | |
530 | #define GR18_USER_INT_EN (1<<2) | |
531 | #define GR18_A0000_FLUSH_EN (1<<1) | |
532 | #define GR18_SMM_EN (1<<0) | |
533 | ||
534 | /* Set by driver, cleared by VBIOS */ | |
535 | #define SWF00_YRES_SHIFT 16 | |
536 | #define SWF00_XRES_SHIFT 0 | |
537 | #define SWF00_RES_MASK 0xffff | |
538 | ||
539 | /* Set by VBIOS at boot time and driver at runtime */ | |
540 | #define SWF01_TV2_FORMAT_SHIFT 8 | |
541 | #define SWF01_TV1_FORMAT_SHIFT 0 | |
542 | #define SWF01_TV_FORMAT_MASK 0xffff | |
543 | ||
544 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) | |
545 | #define SWF10_GTT_OVERRIDE_EN (1<<28) | |
546 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ | |
547 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) | |
548 | #define SWF10_OLD_TOGGLE 0x0 | |
549 | #define SWF10_TOGGLE_LIST_1 0x1 | |
550 | #define SWF10_TOGGLE_LIST_2 0x2 | |
551 | #define SWF10_TOGGLE_LIST_3 0x3 | |
552 | #define SWF10_TOGGLE_LIST_4 0x4 | |
553 | #define SWF10_PANNING_EN (1<<23) | |
554 | #define SWF10_DRIVER_LOADED (1<<22) | |
555 | #define SWF10_EXTENDED_DESKTOP (1<<21) | |
556 | #define SWF10_EXCLUSIVE_MODE (1<<20) | |
557 | #define SWF10_OVERLAY_EN (1<<19) | |
558 | #define SWF10_PLANEB_HOLDOFF (1<<18) | |
559 | #define SWF10_PLANEA_HOLDOFF (1<<17) | |
560 | #define SWF10_VGA_HOLDOFF (1<<16) | |
561 | #define SWF10_ACTIVE_DISP_MASK 0xffff | |
562 | #define SWF10_PIPEB_LFP2 (1<<15) | |
563 | #define SWF10_PIPEB_EFP2 (1<<14) | |
564 | #define SWF10_PIPEB_TV2 (1<<13) | |
565 | #define SWF10_PIPEB_CRT2 (1<<12) | |
566 | #define SWF10_PIPEB_LFP (1<<11) | |
567 | #define SWF10_PIPEB_EFP (1<<10) | |
568 | #define SWF10_PIPEB_TV (1<<9) | |
569 | #define SWF10_PIPEB_CRT (1<<8) | |
570 | #define SWF10_PIPEA_LFP2 (1<<7) | |
571 | #define SWF10_PIPEA_EFP2 (1<<6) | |
572 | #define SWF10_PIPEA_TV2 (1<<5) | |
573 | #define SWF10_PIPEA_CRT2 (1<<4) | |
574 | #define SWF10_PIPEA_LFP (1<<3) | |
575 | #define SWF10_PIPEA_EFP (1<<2) | |
576 | #define SWF10_PIPEA_TV (1<<1) | |
577 | #define SWF10_PIPEA_CRT (1<<0) | |
578 | ||
579 | #define SWF11_MEMORY_SIZE_SHIFT 16 | |
580 | #define SWF11_SV_TEST_EN (1<<15) | |
581 | #define SWF11_IS_AGP (1<<14) | |
582 | #define SWF11_DISPLAY_HOLDOFF (1<<13) | |
583 | #define SWF11_DPMS_REDUCED (1<<12) | |
584 | #define SWF11_IS_VBE_MODE (1<<11) | |
585 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ | |
586 | #define SWF11_DPMS_MASK 0x07 | |
587 | #define SWF11_DPMS_OFF (1<<2) | |
588 | #define SWF11_DPMS_SUSPEND (1<<1) | |
589 | #define SWF11_DPMS_STANDBY (1<<0) | |
590 | #define SWF11_DPMS_ON 0 | |
591 | ||
592 | #define SWF14_GFX_PFIT_EN (1<<31) | |
593 | #define SWF14_TEXT_PFIT_EN (1<<30) | |
594 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ | |
595 | #define SWF14_POPUP_EN (1<<28) | |
596 | #define SWF14_DISPLAY_HOLDOFF (1<<27) | |
597 | #define SWF14_DISP_DETECT_EN (1<<26) | |
598 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ | |
599 | #define SWF14_DRIVER_STATUS (1<<24) | |
600 | #define SWF14_OS_TYPE_WIN9X (1<<23) | |
601 | #define SWF14_OS_TYPE_WINNT (1<<22) | |
602 | /* 21:19 rsvd */ | |
603 | #define SWF14_PM_TYPE_MASK 0x00070000 | |
604 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) | |
605 | #define SWF14_PM_ACPI (0x3 << 16) | |
606 | #define SWF14_PM_APM_12 (0x2 << 16) | |
607 | #define SWF14_PM_APM_11 (0x1 << 16) | |
608 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ | |
609 | /* if GR18 indicates a display switch */ | |
610 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) | |
611 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) | |
612 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) | |
613 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) | |
614 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) | |
615 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) | |
616 | #define SWF14_DS_PIPEB_TV_EN (1<<9) | |
617 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) | |
618 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) | |
619 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) | |
620 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) | |
621 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) | |
622 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) | |
623 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) | |
624 | #define SWF14_DS_PIPEA_TV_EN (1<<1) | |
625 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) | |
626 | /* if GR18 indicates a panel fitting request */ | |
627 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ | |
628 | /* if GR18 indicates an APM change request */ | |
629 | #define SWF14_APM_HIBERNATE 0x4 | |
630 | #define SWF14_APM_SUSPEND 0x3 | |
631 | #define SWF14_APM_STANDBY 0x1 | |
632 | #define SWF14_APM_RESTORE 0x0 | |
633 | ||
6363ee6f ZY |
634 | /* Add the device class for LFP, TV, HDMI */ |
635 | #define DEVICE_TYPE_INT_LFP 0x1022 | |
636 | #define DEVICE_TYPE_INT_TV 0x1009 | |
637 | #define DEVICE_TYPE_HDMI 0x60D2 | |
638 | #define DEVICE_TYPE_DP 0x68C6 | |
639 | #define DEVICE_TYPE_eDP 0x78C6 | |
640 | ||
641 | /* define the DVO port for HDMI output type */ | |
642 | #define DVO_B 1 | |
643 | #define DVO_C 2 | |
644 | #define DVO_D 3 | |
645 | ||
646 | /* define the PORT for DP output type */ | |
647 | #define PORT_IDPB 7 | |
648 | #define PORT_IDPC 8 | |
649 | #define PORT_IDPD 9 | |
650 | ||
d17c5443 SK |
651 | /* MIPI DSI panel info */ |
652 | struct bdb_mipi { | |
653 | u16 panel_id; | |
654 | u16 bridge_revision; | |
655 | ||
656 | /* General params */ | |
657 | u32 dithering:1; | |
658 | u32 bpp_pixel_format:1; | |
659 | u32 rsvd1:1; | |
660 | u32 dphy_valid:1; | |
661 | u32 resvd2:28; | |
662 | ||
663 | u16 port_info; | |
664 | u16 rsvd3:2; | |
665 | u16 num_lanes:2; | |
666 | u16 rsvd4:12; | |
667 | ||
668 | /* DSI config */ | |
669 | u16 virt_ch_num:2; | |
670 | u16 vtm:2; | |
671 | u16 rsvd5:12; | |
672 | ||
673 | u32 dsi_clock; | |
674 | u32 bridge_ref_clk; | |
675 | u16 rsvd_pwr; | |
676 | ||
677 | /* Dphy Params */ | |
678 | u32 prepare_cnt:5; | |
679 | u32 rsvd6:3; | |
680 | u32 clk_zero_cnt:8; | |
681 | u32 trail_cnt:5; | |
682 | u32 rsvd7:3; | |
683 | u32 exit_zero_cnt:6; | |
684 | u32 rsvd8:2; | |
685 | ||
686 | u32 hl_switch_cnt; | |
687 | u32 lp_byte_clk; | |
688 | u32 clk_lane_switch_cnt; | |
689 | } __attribute__((packed)); | |
690 | ||
79e53945 | 691 | #endif /* _I830_BIOS_H_ */ |