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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "intel_drv.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | ||
37 | static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |
38 | { | |
39 | struct drm_device *dev = encoder->dev; | |
40 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 41 | u32 temp, reg; |
79e53945 | 42 | |
bad720ff | 43 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
44 | reg = PCH_ADPA; |
45 | else | |
46 | reg = ADPA; | |
47 | ||
48 | temp = I915_READ(reg); | |
79e53945 | 49 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 50 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 JB |
51 | |
52 | switch(mode) { | |
53 | case DRM_MODE_DPMS_ON: | |
54 | temp |= ADPA_DAC_ENABLE; | |
55 | break; | |
56 | case DRM_MODE_DPMS_STANDBY: | |
57 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
58 | break; | |
59 | case DRM_MODE_DPMS_SUSPEND: | |
60 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
61 | break; | |
62 | case DRM_MODE_DPMS_OFF: | |
63 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
64 | break; | |
65 | } | |
66 | ||
2c07245f | 67 | I915_WRITE(reg, temp); |
79e53945 JB |
68 | } |
69 | ||
70 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
71 | struct drm_display_mode *mode) | |
72 | { | |
6bcdcd9e ZY |
73 | struct drm_device *dev = connector->dev; |
74 | ||
75 | int max_clock = 0; | |
79e53945 JB |
76 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
77 | return MODE_NO_DBLESCAN; | |
78 | ||
6bcdcd9e ZY |
79 | if (mode->clock < 25000) |
80 | return MODE_CLOCK_LOW; | |
81 | ||
82 | if (!IS_I9XX(dev)) | |
83 | max_clock = 350000; | |
84 | else | |
85 | max_clock = 400000; | |
86 | if (mode->clock > max_clock) | |
87 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
88 | |
89 | return MODE_OK; | |
90 | } | |
91 | ||
92 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
93 | struct drm_display_mode *mode, | |
94 | struct drm_display_mode *adjusted_mode) | |
95 | { | |
96 | return true; | |
97 | } | |
98 | ||
99 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
100 | struct drm_display_mode *mode, | |
101 | struct drm_display_mode *adjusted_mode) | |
102 | { | |
103 | ||
104 | struct drm_device *dev = encoder->dev; | |
105 | struct drm_crtc *crtc = encoder->crtc; | |
106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
108 | int dpll_md_reg; | |
109 | u32 adpa, dpll_md; | |
2c07245f | 110 | u32 adpa_reg; |
79e53945 JB |
111 | |
112 | if (intel_crtc->pipe == 0) | |
113 | dpll_md_reg = DPLL_A_MD; | |
114 | else | |
115 | dpll_md_reg = DPLL_B_MD; | |
116 | ||
bad720ff | 117 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
118 | adpa_reg = PCH_ADPA; |
119 | else | |
120 | adpa_reg = ADPA; | |
121 | ||
79e53945 JB |
122 | /* |
123 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
124 | * XXX this needs to be adjusted when we really are cloning | |
125 | */ | |
bad720ff | 126 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { |
79e53945 JB |
127 | dpll_md = I915_READ(dpll_md_reg); |
128 | I915_WRITE(dpll_md_reg, | |
129 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
130 | } | |
131 | ||
132 | adpa = 0; | |
133 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
134 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
135 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
136 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
137 | ||
6bcdcd9e | 138 | if (intel_crtc->pipe == 0) { |
8db9d77b ZW |
139 | if (HAS_PCH_CPT(dev)) |
140 | adpa |= PORT_TRANS_A_SEL_CPT; | |
141 | else | |
142 | adpa |= ADPA_PIPE_A_SELECT; | |
bad720ff | 143 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 144 | I915_WRITE(BCLRPAT_A, 0); |
6bcdcd9e | 145 | } else { |
8db9d77b ZW |
146 | if (HAS_PCH_CPT(dev)) |
147 | adpa |= PORT_TRANS_B_SEL_CPT; | |
148 | else | |
149 | adpa |= ADPA_PIPE_B_SELECT; | |
bad720ff | 150 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 151 | I915_WRITE(BCLRPAT_B, 0); |
6bcdcd9e | 152 | } |
79e53945 | 153 | |
2c07245f ZW |
154 | I915_WRITE(adpa_reg, adpa); |
155 | } | |
156 | ||
f2b115e6 | 157 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
158 | { |
159 | struct drm_device *dev = connector->dev; | |
160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a6b901 | 161 | u32 adpa, temp; |
2c07245f | 162 | bool ret; |
d5dd96cb | 163 | bool turn_off_dac = false; |
2c07245f | 164 | |
a4a6b901 | 165 | temp = adpa = I915_READ(PCH_ADPA); |
67941da2 | 166 | |
d5dd96cb DA |
167 | if (HAS_PCH_SPLIT(dev)) |
168 | turn_off_dac = true; | |
169 | ||
170 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | |
171 | if (turn_off_dac) | |
172 | adpa &= ~ADPA_DAC_ENABLE; | |
173 | ||
174 | /* disable HPD first */ | |
175 | I915_WRITE(PCH_ADPA, adpa); | |
176 | (void)I915_READ(PCH_ADPA); | |
2c07245f ZW |
177 | |
178 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | |
179 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | |
180 | ADPA_CRT_HOTPLUG_SAMPLE_4S | | |
181 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */ | |
182 | ADPA_CRT_HOTPLUG_VOLREF_325MV | | |
183 | ADPA_CRT_HOTPLUG_ENABLE | | |
184 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | |
185 | ||
28c97730 | 186 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); |
2c07245f ZW |
187 | I915_WRITE(PCH_ADPA, adpa); |
188 | ||
913d8d11 | 189 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
481b6af3 | 190 | 1000)) |
913d8d11 | 191 | DRM_ERROR("timed out waiting for FORCE_TRIGGER"); |
2c07245f | 192 | |
d5dd96cb | 193 | if (turn_off_dac) { |
a4a6b901 ZW |
194 | I915_WRITE(PCH_ADPA, temp); |
195 | (void)I915_READ(PCH_ADPA); | |
196 | } | |
197 | ||
2c07245f ZW |
198 | /* Check the status to see if both blue and green are on now */ |
199 | adpa = I915_READ(PCH_ADPA); | |
67941da2 ZW |
200 | adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK; |
201 | if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) || | |
202 | (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO)) | |
2c07245f ZW |
203 | ret = true; |
204 | else | |
205 | ret = false; | |
206 | ||
2c07245f | 207 | return ret; |
79e53945 JB |
208 | } |
209 | ||
210 | /** | |
211 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
212 | * | |
213 | * Not for i915G/i915GM | |
214 | * | |
215 | * \return true if CRT is connected. | |
216 | * \return false if CRT is disconnected. | |
217 | */ | |
218 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
219 | { | |
220 | struct drm_device *dev = connector->dev; | |
221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
222 | u32 hotplug_en, orig, stat; |
223 | bool ret = false; | |
771cb081 | 224 | int i, tries = 0; |
2c07245f | 225 | |
bad720ff | 226 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 227 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 228 | |
771cb081 ZY |
229 | /* |
230 | * On 4 series desktop, CRT detect sequence need to be done twice | |
231 | * to get a reliable result. | |
232 | */ | |
79e53945 | 233 | |
771cb081 ZY |
234 | if (IS_G4X(dev) && !IS_GM45(dev)) |
235 | tries = 2; | |
236 | else | |
237 | tries = 1; | |
7a772c49 | 238 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
239 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
240 | ||
771cb081 | 241 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
242 | /* turn on the FORCE_DETECT */ |
243 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 244 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
245 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
246 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 247 | 1000)) |
913d8d11 | 248 | DRM_ERROR("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 249 | } |
79e53945 | 250 | |
7a772c49 AJ |
251 | stat = I915_READ(PORT_HOTPLUG_STAT); |
252 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
253 | ret = true; | |
254 | ||
255 | /* clear the interrupt we just generated, if any */ | |
256 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 257 | |
7a772c49 AJ |
258 | /* and put the bits back */ |
259 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
260 | ||
261 | return ret; | |
79e53945 JB |
262 | } |
263 | ||
454c1ca8 | 264 | static bool intel_crt_detect_ddc(struct drm_encoder *encoder) |
79e53945 | 265 | { |
4ef69c7a | 266 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
79e53945 JB |
267 | |
268 | /* CRT should always be at 0, but check anyway */ | |
21d40d37 | 269 | if (intel_encoder->type != INTEL_OUTPUT_ANALOG) |
79e53945 JB |
270 | return false; |
271 | ||
21d40d37 | 272 | return intel_ddc_probe(intel_encoder); |
79e53945 JB |
273 | } |
274 | ||
e4a5d54f | 275 | static enum drm_connector_status |
21d40d37 | 276 | intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder) |
e4a5d54f | 277 | { |
4ef69c7a | 278 | struct drm_encoder *encoder = &intel_encoder->base; |
e4a5d54f ML |
279 | struct drm_device *dev = encoder->dev; |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
282 | uint32_t pipe = intel_crtc->pipe; | |
283 | uint32_t save_bclrpat; | |
284 | uint32_t save_vtotal; | |
285 | uint32_t vtotal, vactive; | |
286 | uint32_t vsample; | |
287 | uint32_t vblank, vblank_start, vblank_end; | |
288 | uint32_t dsl; | |
289 | uint32_t bclrpat_reg; | |
290 | uint32_t vtotal_reg; | |
291 | uint32_t vblank_reg; | |
292 | uint32_t vsync_reg; | |
293 | uint32_t pipeconf_reg; | |
294 | uint32_t pipe_dsl_reg; | |
295 | uint8_t st00; | |
296 | enum drm_connector_status status; | |
297 | ||
298 | if (pipe == 0) { | |
299 | bclrpat_reg = BCLRPAT_A; | |
300 | vtotal_reg = VTOTAL_A; | |
301 | vblank_reg = VBLANK_A; | |
302 | vsync_reg = VSYNC_A; | |
303 | pipeconf_reg = PIPEACONF; | |
304 | pipe_dsl_reg = PIPEADSL; | |
305 | } else { | |
306 | bclrpat_reg = BCLRPAT_B; | |
307 | vtotal_reg = VTOTAL_B; | |
308 | vblank_reg = VBLANK_B; | |
309 | vsync_reg = VSYNC_B; | |
310 | pipeconf_reg = PIPEBCONF; | |
311 | pipe_dsl_reg = PIPEBDSL; | |
312 | } | |
313 | ||
314 | save_bclrpat = I915_READ(bclrpat_reg); | |
315 | save_vtotal = I915_READ(vtotal_reg); | |
316 | vblank = I915_READ(vblank_reg); | |
317 | ||
318 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
319 | vactive = (save_vtotal & 0x7ff) + 1; | |
320 | ||
321 | vblank_start = (vblank & 0xfff) + 1; | |
322 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
323 | ||
324 | /* Set the border color to purple. */ | |
325 | I915_WRITE(bclrpat_reg, 0x500050); | |
326 | ||
327 | if (IS_I9XX(dev)) { | |
328 | uint32_t pipeconf = I915_READ(pipeconf_reg); | |
329 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 330 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
331 | /* Wait for next Vblank to substitue |
332 | * border color for Color info */ | |
9d0498a2 | 333 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
334 | st00 = I915_READ8(VGA_MSR_WRITE); |
335 | status = ((st00 & (1 << 4)) != 0) ? | |
336 | connector_status_connected : | |
337 | connector_status_disconnected; | |
338 | ||
339 | I915_WRITE(pipeconf_reg, pipeconf); | |
340 | } else { | |
341 | bool restore_vblank = false; | |
342 | int count, detect; | |
343 | ||
344 | /* | |
345 | * If there isn't any border, add some. | |
346 | * Yes, this will flicker | |
347 | */ | |
348 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
349 | uint32_t vsync = I915_READ(vsync_reg); | |
350 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
351 | ||
352 | vblank_start = vsync_start; | |
353 | I915_WRITE(vblank_reg, | |
354 | (vblank_start - 1) | | |
355 | ((vblank_end - 1) << 16)); | |
356 | restore_vblank = true; | |
357 | } | |
358 | /* sample in the vertical border, selecting the larger one */ | |
359 | if (vblank_start - vactive >= vtotal - vblank_end) | |
360 | vsample = (vblank_start + vactive) >> 1; | |
361 | else | |
362 | vsample = (vtotal + vblank_end) >> 1; | |
363 | ||
364 | /* | |
365 | * Wait for the border to be displayed | |
366 | */ | |
367 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
368 | ; | |
369 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
370 | ; | |
371 | /* | |
372 | * Watch ST00 for an entire scanline | |
373 | */ | |
374 | detect = 0; | |
375 | count = 0; | |
376 | do { | |
377 | count++; | |
378 | /* Read the ST00 VGA status register */ | |
379 | st00 = I915_READ8(VGA_MSR_WRITE); | |
380 | if (st00 & (1 << 4)) | |
381 | detect++; | |
382 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
383 | ||
384 | /* restore vblank if necessary */ | |
385 | if (restore_vblank) | |
386 | I915_WRITE(vblank_reg, vblank); | |
387 | /* | |
388 | * If more than 3/4 of the scanline detected a monitor, | |
389 | * then it is assumed to be present. This works even on i830, | |
390 | * where there isn't any way to force the border color across | |
391 | * the screen | |
392 | */ | |
393 | status = detect * 4 > count * 3 ? | |
394 | connector_status_connected : | |
395 | connector_status_disconnected; | |
396 | } | |
397 | ||
398 | /* Restore previous settings */ | |
399 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
400 | ||
401 | return status; | |
402 | } | |
403 | ||
79e53945 JB |
404 | static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) |
405 | { | |
406 | struct drm_device *dev = connector->dev; | |
df0e9248 | 407 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
e4a5d54f ML |
408 | struct drm_crtc *crtc; |
409 | int dpms_mode; | |
410 | enum drm_connector_status status; | |
79e53945 JB |
411 | |
412 | if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) { | |
413 | if (intel_crt_detect_hotplug(connector)) | |
414 | return connector_status_connected; | |
415 | else | |
416 | return connector_status_disconnected; | |
417 | } | |
418 | ||
df0e9248 | 419 | if (intel_crt_detect_ddc(&encoder->base)) |
79e53945 JB |
420 | return connector_status_connected; |
421 | ||
e4a5d54f | 422 | /* for pre-945g platforms use load detect */ |
df0e9248 CW |
423 | if (encoder->base.crtc && encoder->base.crtc->enabled) { |
424 | status = intel_crt_load_detect(encoder->base.crtc, encoder); | |
e4a5d54f | 425 | } else { |
df0e9248 | 426 | crtc = intel_get_load_detect_pipe(encoder, connector, |
e4a5d54f ML |
427 | NULL, &dpms_mode); |
428 | if (crtc) { | |
df0e9248 CW |
429 | status = intel_crt_load_detect(crtc, encoder); |
430 | intel_release_load_detect_pipe(encoder, | |
c1c43977 | 431 | connector, dpms_mode); |
e4a5d54f ML |
432 | } else |
433 | status = connector_status_unknown; | |
434 | } | |
435 | ||
436 | return status; | |
79e53945 JB |
437 | } |
438 | ||
439 | static void intel_crt_destroy(struct drm_connector *connector) | |
440 | { | |
79e53945 JB |
441 | drm_sysfs_connector_remove(connector); |
442 | drm_connector_cleanup(connector); | |
443 | kfree(connector); | |
444 | } | |
445 | ||
446 | static int intel_crt_get_modes(struct drm_connector *connector) | |
447 | { | |
8e4d36b9 | 448 | int ret; |
df0e9248 | 449 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
335af9a2 | 450 | struct i2c_adapter *ddc_bus; |
8e4d36b9 | 451 | struct drm_device *dev = connector->dev; |
452 | ||
453 | ||
df0e9248 | 454 | ret = intel_ddc_get_modes(connector, encoder->ddc_bus); |
8e4d36b9 | 455 | if (ret || !IS_G4X(dev)) |
456 | goto end; | |
457 | ||
8e4d36b9 | 458 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
335af9a2 | 459 | ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D"); |
8e4d36b9 | 460 | |
335af9a2 | 461 | if (!ddc_bus) { |
8e4d36b9 | 462 | dev_printk(KERN_ERR, &connector->dev->pdev->dev, |
463 | "DDC bus registration failed for CRTDDC_D.\n"); | |
464 | goto end; | |
465 | } | |
466 | /* Try to get modes by GPIOD port */ | |
335af9a2 ZW |
467 | ret = intel_ddc_get_modes(connector, ddc_bus); |
468 | intel_i2c_destroy(ddc_bus); | |
8e4d36b9 | 469 | |
470 | end: | |
471 | return ret; | |
472 | ||
79e53945 JB |
473 | } |
474 | ||
475 | static int intel_crt_set_property(struct drm_connector *connector, | |
476 | struct drm_property *property, | |
477 | uint64_t value) | |
478 | { | |
79e53945 JB |
479 | return 0; |
480 | } | |
481 | ||
482 | /* | |
483 | * Routines for controlling stuff on the analog port | |
484 | */ | |
485 | ||
486 | static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = { | |
487 | .dpms = intel_crt_dpms, | |
488 | .mode_fixup = intel_crt_mode_fixup, | |
489 | .prepare = intel_encoder_prepare, | |
490 | .commit = intel_encoder_commit, | |
491 | .mode_set = intel_crt_mode_set, | |
492 | }; | |
493 | ||
494 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
c9fb15f6 | 495 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
496 | .detect = intel_crt_detect, |
497 | .fill_modes = drm_helper_probe_single_connector_modes, | |
498 | .destroy = intel_crt_destroy, | |
499 | .set_property = intel_crt_set_property, | |
500 | }; | |
501 | ||
502 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
503 | .mode_valid = intel_crt_mode_valid, | |
504 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 505 | .best_encoder = intel_best_encoder, |
79e53945 JB |
506 | }; |
507 | ||
79e53945 | 508 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 509 | .destroy = intel_encoder_destroy, |
79e53945 JB |
510 | }; |
511 | ||
512 | void intel_crt_init(struct drm_device *dev) | |
513 | { | |
514 | struct drm_connector *connector; | |
21d40d37 | 515 | struct intel_encoder *intel_encoder; |
454c1ca8 | 516 | struct intel_connector *intel_connector; |
db545019 | 517 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 518 | u32 i2c_reg; |
79e53945 | 519 | |
21d40d37 EA |
520 | intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL); |
521 | if (!intel_encoder) | |
79e53945 JB |
522 | return; |
523 | ||
454c1ca8 ZW |
524 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
525 | if (!intel_connector) { | |
526 | kfree(intel_encoder); | |
527 | return; | |
528 | } | |
529 | ||
530 | connector = &intel_connector->base; | |
531 | drm_connector_init(dev, &intel_connector->base, | |
79e53945 JB |
532 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
533 | ||
4ef69c7a | 534 | drm_encoder_init(dev, &intel_encoder->base, &intel_crt_enc_funcs, |
79e53945 JB |
535 | DRM_MODE_ENCODER_DAC); |
536 | ||
df0e9248 | 537 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 JB |
538 | |
539 | /* Set up the DDC bus. */ | |
bad720ff | 540 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 541 | i2c_reg = PCH_GPIOA; |
db545019 | 542 | else { |
2c07245f | 543 | i2c_reg = GPIOA; |
db545019 | 544 | /* Use VBT information for CRT DDC if available */ |
29874f44 | 545 | if (dev_priv->crt_ddc_bus != 0) |
db545019 DMEA |
546 | i2c_reg = dev_priv->crt_ddc_bus; |
547 | } | |
21d40d37 EA |
548 | intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); |
549 | if (!intel_encoder->ddc_bus) { | |
79e53945 JB |
550 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
551 | "failed.\n"); | |
552 | return; | |
553 | } | |
554 | ||
21d40d37 EA |
555 | intel_encoder->type = INTEL_OUTPUT_ANALOG; |
556 | intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
f8aed700 ML |
557 | (1 << INTEL_ANALOG_CLONE_BIT) | |
558 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
21d40d37 | 559 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
734b4157 | 560 | connector->interlace_allowed = 1; |
79e53945 JB |
561 | connector->doublescan_allowed = 0; |
562 | ||
4ef69c7a | 563 | drm_encoder_helper_add(&intel_encoder->base, &intel_crt_helper_funcs); |
79e53945 JB |
564 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
565 | ||
566 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 567 | |
eb1f8e4f DA |
568 | if (I915_HAS_HOTPLUG(dev)) |
569 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
570 | else | |
571 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
572 | ||
b01f2c3a | 573 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
79e53945 | 574 | } |