[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_crt.c

/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 temp, reg;

	if (HAS_PCH_SPLIT(dev))
		reg = PCH_ADPA;
	else
		reg = ADPA;

	temp = I915_READ(reg);
	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
	temp &= ~ADPA_DAC_ENABLE;

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		temp |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}

	I915_WRITE(reg, temp);
}

static int intel_crt_mode_valid(struct drm_connector *connector,
				struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;

	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;

	if (!IS_I9XX(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void intel_crt_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode)
{

	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dpll_md_reg;
	u32 adpa, dpll_md;
	u32 adpa_reg;

	if (intel_crtc->pipe == 0)
		dpll_md_reg = DPLL_A_MD;
	else
		dpll_md_reg = DPLL_B_MD;

	if (HAS_PCH_SPLIT(dev))
		adpa_reg = PCH_ADPA;
	else
		adpa_reg = ADPA;

	/*
	 * Disable separate mode multiplier used when cloning SDVO to CRT
	 * XXX this needs to be adjusted when we really are cloning
	 */
	if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
		dpll_md = I915_READ(dpll_md_reg);
		I915_WRITE(dpll_md_reg,
			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	}

	adpa = 0;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;

	if (intel_crtc->pipe == 0) {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_A_SEL_CPT;
		else
			adpa |= ADPA_PIPE_A_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_A, 0);
	} else {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_B_SEL_CPT;
		else
			adpa |= ADPA_PIPE_B_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_B, 0);
	}

	I915_WRITE(adpa_reg, adpa);
}

static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;

	adpa = I915_READ(PCH_ADPA);

	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
	/* disable HPD first */
	I915_WRITE(PCH_ADPA, adpa);
	(void)I915_READ(PCH_ADPA);

	adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
			ADPA_CRT_HOTPLUG_WARMUP_10MS |
			ADPA_CRT_HOTPLUG_SAMPLE_4S |
			ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
			ADPA_CRT_HOTPLUG_VOLREF_325MV |
			ADPA_CRT_HOTPLUG_ENABLE |
			ADPA_CRT_HOTPLUG_FORCE_TRIGGER);

	DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
	I915_WRITE(PCH_ADPA, adpa);

	while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
		;

	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(PCH_ADPA);
	adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
	if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
		(adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
		ret = true;
	else
		ret = false;

	return ret;
}

/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_en;
	int i, tries = 0;

	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);

	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */

	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;

	if (IS_G4X(dev))
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;

	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	for (i = 0; i < tries ; i++) {
		unsigned long timeout;
		/* turn on the FORCE_DETECT */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
		timeout = jiffies + msecs_to_jiffies(1000);
		/* wait for FORCE_DETECT to go off */
		do {
			if (!(I915_READ(PORT_HOTPLUG_EN) &
					CRT_HOTPLUG_FORCE_DETECT))
				break;
			msleep(1);
		} while (time_after(timeout, jiffies));
	}

	if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
	    CRT_HOTPLUG_MONITOR_NONE)
		return true;

	return false;
}

static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
	struct intel_encoder *intel_encoder = to_intel_encoder(connector);

	/* CRT should always be at 0, but check anyway */
	if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
		return false;

	return intel_ddc_probe(intel_encoder);
}

static enum drm_connector_status
intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
{
	struct drm_encoder *encoder = &intel_encoder->enc;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pipe = intel_crtc->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;

	if (pipe == 0) {
		bclrpat_reg = BCLRPAT_A;
		vtotal_reg = VTOTAL_A;
		vblank_reg = VBLANK_A;
		vsync_reg = VSYNC_A;
		pipeconf_reg = PIPEACONF;
		pipe_dsl_reg = PIPEADSL;
	} else {
		bclrpat_reg = BCLRPAT_B;
		vtotal_reg = VTOTAL_B;
		vblank_reg = VBLANK_B;
		vsync_reg = VSYNC_B;
		pipeconf_reg = PIPEBCONF;
		pipe_dsl_reg = PIPEBDSL;
	}

	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);

	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;

	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;

	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);

	if (IS_I9XX(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;

		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;

		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;

			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;

		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));

		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}

	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);

	return status;
}

static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
	struct drm_encoder *encoder = &intel_encoder->enc;
	struct drm_crtc *crtc;
	int dpms_mode;
	enum drm_connector_status status;

	if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
		if (intel_crt_detect_hotplug(connector))
			return connector_status_connected;
		else
			return connector_status_disconnected;
	}

	if (intel_crt_detect_ddc(connector))
		return connector_status_connected;

	/* for pre-945g platforms use load detect */
	if (encoder->crtc && encoder->crtc->enabled) {
		status = intel_crt_load_detect(encoder->crtc, intel_encoder);
	} else {
		crtc = intel_get_load_detect_pipe(intel_encoder, connector,
						  NULL, &dpms_mode);
		if (crtc) {
			status = intel_crt_load_detect(crtc, intel_encoder);
			intel_release_load_detect_pipe(intel_encoder,
						       connector, dpms_mode);
		} else
			status = connector_status_unknown;
	}

	return status;
}

static void intel_crt_destroy(struct drm_connector *connector)
{
	struct intel_encoder *intel_encoder = to_intel_encoder(connector);

	intel_i2c_destroy(intel_encoder->ddc_bus);
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static int intel_crt_get_modes(struct drm_connector *connector)
{
	int ret;
	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
	struct i2c_adapter *ddc_bus;
	struct drm_device *dev = connector->dev;


	ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
	if (ret || !IS_G4X(dev))
		goto end;

	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");

	if (!ddc_bus) {
		dev_printk(KERN_ERR, &connector->dev->pdev->dev,
			   "DDC bus registration failed for CRTDDC_D.\n");
		goto end;
	}
	/* Try to get modes by GPIOD port */
	ret = intel_ddc_get_modes(connector, ddc_bus);
	intel_i2c_destroy(ddc_bus);

end:
	return ret;

}

static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}

/*
 * Routines for controlling stuff on the analog port
 */

static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	.dpms = intel_crt_dpms,
	.mode_fixup = intel_crt_mode_fixup,
	.prepare = intel_encoder_prepare,
	.commit = intel_encoder_commit,
	.mode_set = intel_crt_mode_set,
};

static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
};

static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};

static void intel_crt_enc_destroy(struct drm_encoder *encoder)
{
	drm_encoder_cleanup(encoder);
}

static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_crt_enc_destroy,
};

void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 i2c_reg;

	intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
	if (!intel_encoder)
		return;

	connector = &intel_encoder->base;
	drm_connector_init(dev, &intel_encoder->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

	drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);

	drm_mode_connector_attach_encoder(&intel_encoder->base,
					  &intel_encoder->enc);

	/* Set up the DDC bus. */
	if (HAS_PCH_SPLIT(dev))
		i2c_reg = PCH_GPIOA;
	else {
		i2c_reg = GPIOA;
		/* Use VBT information for CRT DDC if available */
		if (dev_priv->crt_ddc_bus != 0)
			i2c_reg = dev_priv->crt_ddc_bus;
	}
	intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
	if (!intel_encoder->ddc_bus) {
		dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
			   "failed.\n");
		return;
	}

	intel_encoder->type = INTEL_OUTPUT_ANALOG;
	intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
				   (1 << INTEL_ANALOG_CLONE_BIT) |
				   (1 << INTEL_SDVO_LVDS_CLONE_BIT);
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	connector->interlace_allowed = 0;
	connector->doublescan_allowed = 0;

	drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

	drm_sysfs_connector_add(connector);

	dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006-2007 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*/
	26
	27	#include <linux/i2c.h>
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "drm_crtc.h"
	31	#include "drm_crtc_helper.h"
	32	#include "intel_drv.h"
	33	#include "i915_drm.h"
	34	#include "i915_drv.h"
	35
	36	static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
	37	{
	38	struct drm_device *dev = encoder->dev;
	39	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	40	u32 temp, reg;
79e53945	41
bad720ff	42	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	43	reg = PCH_ADPA;
	44	else
	45	reg = ADPA;
	46
	47	temp = I915_READ(reg);
79e53945	48	temp &= ~(ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE);
febc7694	49	temp &= ~ADPA_DAC_ENABLE;
79e53945 JB	50
	51	switch(mode) {
	52	case DRM_MODE_DPMS_ON:
	53	temp \|= ADPA_DAC_ENABLE;
	54	break;
	55	case DRM_MODE_DPMS_STANDBY:
	56	temp \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
	57	break;
	58	case DRM_MODE_DPMS_SUSPEND:
	59	temp \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
	60	break;
	61	case DRM_MODE_DPMS_OFF:
	62	temp \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
	63	break;
	64	}
	65
2c07245f	66	I915_WRITE(reg, temp);
79e53945 JB	67	}
	68
	69	static int intel_crt_mode_valid(struct drm_connector *connector,
	70	struct drm_display_mode *mode)
	71	{
6bcdcd9e ZY	72	struct drm_device *dev = connector->dev;
	73
	74	int max_clock = 0;
79e53945 JB	75	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	76	return MODE_NO_DBLESCAN;
	77
6bcdcd9e ZY	78	if (mode->clock < 25000)
	79	return MODE_CLOCK_LOW;
	80
	81	if (!IS_I9XX(dev))
	82	max_clock = 350000;
	83	else
	84	max_clock = 400000;
	85	if (mode->clock > max_clock)
	86	return MODE_CLOCK_HIGH;
79e53945 JB	87
	88	return MODE_OK;
	89	}
	90
	91	static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
	92	struct drm_display_mode *mode,
	93	struct drm_display_mode *adjusted_mode)
	94	{
	95	return true;
	96	}
	97
	98	static void intel_crt_mode_set(struct drm_encoder *encoder,
	99	struct drm_display_mode *mode,
	100	struct drm_display_mode *adjusted_mode)
	101	{
	102
	103	struct drm_device *dev = encoder->dev;
	104	struct drm_crtc *crtc = encoder->crtc;
	105	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	106	struct drm_i915_private *dev_priv = dev->dev_private;
	107	int dpll_md_reg;
	108	u32 adpa, dpll_md;
2c07245f	109	u32 adpa_reg;
79e53945 JB	110
	111	if (intel_crtc->pipe == 0)
	112	dpll_md_reg = DPLL_A_MD;
	113	else
	114	dpll_md_reg = DPLL_B_MD;
	115
bad720ff	116	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	117	adpa_reg = PCH_ADPA;
	118	else
	119	adpa_reg = ADPA;
	120
79e53945 JB	121	/*
	122	* Disable separate mode multiplier used when cloning SDVO to CRT
	123	* XXX this needs to be adjusted when we really are cloning
	124	*/
bad720ff	125	if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
79e53945 JB	126	dpll_md = I915_READ(dpll_md_reg);
	127	I915_WRITE(dpll_md_reg,
	128	dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	129	}
	130
	131	adpa = 0;
	132	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	133	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
	134	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	135	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
	136
6bcdcd9e	137	if (intel_crtc->pipe == 0) {
8db9d77b ZW	138	if (HAS_PCH_CPT(dev))
	139	adpa \|= PORT_TRANS_A_SEL_CPT;
	140	else
	141	adpa \|= ADPA_PIPE_A_SELECT;
bad720ff	142	if (!HAS_PCH_SPLIT(dev))
2c07245f	143	I915_WRITE(BCLRPAT_A, 0);
6bcdcd9e	144	} else {
8db9d77b ZW	145	if (HAS_PCH_CPT(dev))
	146	adpa \|= PORT_TRANS_B_SEL_CPT;
	147	else
	148	adpa \|= ADPA_PIPE_B_SELECT;
bad720ff	149	if (!HAS_PCH_SPLIT(dev))
2c07245f	150	I915_WRITE(BCLRPAT_B, 0);
6bcdcd9e	151	}
79e53945	152
2c07245f ZW	153	I915_WRITE(adpa_reg, adpa);
	154	}
	155
f2b115e6	156	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f ZW	157	{
	158	struct drm_device *dev = connector->dev;
	159	struct drm_i915_private *dev_priv = dev->dev_private;
730915d6	160	u32 adpa;
2c07245f ZW	161	bool ret;
2c07245f ZW	162
730915d6	163	adpa = I915_READ(PCH_ADPA);
67941da2	164
2c07245f	165	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
eceb784c ZW	166	/* disable HPD first */
	167	I915_WRITE(PCH_ADPA, adpa);
	168	(void)I915_READ(PCH_ADPA);
2c07245f ZW	169
	170	adpa \|= (ADPA_CRT_HOTPLUG_PERIOD_128 \|
	171	ADPA_CRT_HOTPLUG_WARMUP_10MS \|
	172	ADPA_CRT_HOTPLUG_SAMPLE_4S \|
	173	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| /* default */
	174	ADPA_CRT_HOTPLUG_VOLREF_325MV \|
	175	ADPA_CRT_HOTPLUG_ENABLE \|
	176	ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
	177
28c97730	178	DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
2c07245f ZW	179	I915_WRITE(PCH_ADPA, adpa);
2c07245f ZW	180
67941da2 ZW	181	while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
67941da2 ZW	182	;
2c07245f ZW	183
	184	/* Check the status to see if both blue and green are on now */
	185	adpa = I915_READ(PCH_ADPA);
67941da2 ZW	186	adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
	187	if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) \|\|
	188	(adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
2c07245f ZW	189	ret = true;
	190	else
	191	ret = false;
	192
2c07245f	193	return ret;
79e53945 JB	194	}
	195
	196	/**
	197	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
	198	*
	199	* Not for i915G/i915GM
	200	*
	201	* \return true if CRT is connected.
	202	* \return false if CRT is disconnected.
	203	*/
	204	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
	205	{
	206	struct drm_device *dev = connector->dev;
	207	struct drm_i915_private *dev_priv = dev->dev_private;
771cb081 ZY	208	u32 hotplug_en;
771cb081 ZY	209	int i, tries = 0;
2c07245f	210
bad720ff	211	if (HAS_PCH_SPLIT(dev))
f2b115e6	212	return intel_ironlake_crt_detect_hotplug(connector);
2c07245f	213
771cb081 ZY	214	/*
	215	* On 4 series desktop, CRT detect sequence need to be done twice
	216	* to get a reliable result.
	217	*/
79e53945	218
771cb081 ZY	219	if (IS_G4X(dev) && !IS_GM45(dev))
	220	tries = 2;
	221	else
	222	tries = 1;
	223	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
5ca58282	224	hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
771cb081 ZY	225	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;
771cb081 ZY	226
e92597cf	227	if (IS_G4X(dev))
771cb081 ZY	228	hotplug_en \|= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	229
	230	hotplug_en \|= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
	231
	232	for (i = 0; i < tries ; i++) {
	233	unsigned long timeout;
	234	/* turn on the FORCE_DETECT */
	235	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	236	timeout = jiffies + msecs_to_jiffies(1000);
	237	/* wait for FORCE_DETECT to go off */
	238	do {
	239	if (!(I915_READ(PORT_HOTPLUG_EN) &
	240	CRT_HOTPLUG_FORCE_DETECT))
	241	break;
	242	msleep(1);
	243	} while (time_after(timeout, jiffies));
	244	}
79e53945	245
8e9e0eea ZW	246	if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
8e9e0eea ZW	247	CRT_HOTPLUG_MONITOR_NONE)
79e53945 JB	248	return true;
	249
	250	return false;
	251	}
	252
	253	static bool intel_crt_detect_ddc(struct drm_connector *connector)
	254	{
21d40d37	255	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
79e53945 JB	256
79e53945 JB	257	/* CRT should always be at 0, but check anyway */
21d40d37	258	if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
79e53945 JB	259	return false;
79e53945 JB	260
21d40d37	261	return intel_ddc_probe(intel_encoder);
79e53945 JB	262	}
79e53945 JB	263
e4a5d54f	264	static enum drm_connector_status
21d40d37	265	intel_crt_load_detect(struct drm_crtc crtc, struct intel_encoder intel_encoder)
e4a5d54f	266	{
21d40d37	267	struct drm_encoder *encoder = &intel_encoder->enc;
e4a5d54f ML	268	struct drm_device *dev = encoder->dev;
	269	struct drm_i915_private *dev_priv = dev->dev_private;
	270	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	271	uint32_t pipe = intel_crtc->pipe;
	272	uint32_t save_bclrpat;
	273	uint32_t save_vtotal;
	274	uint32_t vtotal, vactive;
	275	uint32_t vsample;
	276	uint32_t vblank, vblank_start, vblank_end;
	277	uint32_t dsl;
	278	uint32_t bclrpat_reg;
	279	uint32_t vtotal_reg;
	280	uint32_t vblank_reg;
	281	uint32_t vsync_reg;
	282	uint32_t pipeconf_reg;
	283	uint32_t pipe_dsl_reg;
	284	uint8_t st00;
	285	enum drm_connector_status status;
	286
	287	if (pipe == 0) {
	288	bclrpat_reg = BCLRPAT_A;
	289	vtotal_reg = VTOTAL_A;
	290	vblank_reg = VBLANK_A;
	291	vsync_reg = VSYNC_A;
	292	pipeconf_reg = PIPEACONF;
	293	pipe_dsl_reg = PIPEADSL;
	294	} else {
	295	bclrpat_reg = BCLRPAT_B;
	296	vtotal_reg = VTOTAL_B;
	297	vblank_reg = VBLANK_B;
	298	vsync_reg = VSYNC_B;
	299	pipeconf_reg = PIPEBCONF;
	300	pipe_dsl_reg = PIPEBDSL;
	301	}
	302
	303	save_bclrpat = I915_READ(bclrpat_reg);
	304	save_vtotal = I915_READ(vtotal_reg);
	305	vblank = I915_READ(vblank_reg);
	306
	307	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	308	vactive = (save_vtotal & 0x7ff) + 1;
	309
	310	vblank_start = (vblank & 0xfff) + 1;
	311	vblank_end = ((vblank >> 16) & 0xfff) + 1;
	312
	313	/* Set the border color to purple. */
	314	I915_WRITE(bclrpat_reg, 0x500050);
	315
	316	if (IS_I9XX(dev)) {
	317	uint32_t pipeconf = I915_READ(pipeconf_reg);
	318	I915_WRITE(pipeconf_reg, pipeconf \| PIPECONF_FORCE_BORDER);
	319	/* Wait for next Vblank to substitue
	320	* border color for Color info */
	321	intel_wait_for_vblank(dev);
	322	st00 = I915_READ8(VGA_MSR_WRITE);
	323	status = ((st00 & (1 << 4)) != 0) ?
	324	connector_status_connected :
	325	connector_status_disconnected;
	326
	327	I915_WRITE(pipeconf_reg, pipeconf);
	328	} else {
	329	bool restore_vblank = false;
	330	int count, detect;
	331
332	/*
333	* If there isn't any border, add some.
334	* Yes, this will flicker
335	*/
336	if (vblank_start <= vactive && vblank_end >= vtotal) {
337	uint32_t vsync = I915_READ(vsync_reg);
338	uint32_t vsync_start = (vsync & 0xffff) + 1;
339
340	vblank_start = vsync_start;
341	I915_WRITE(vblank_reg,
342	(vblank_start - 1) \|
343	((vblank_end - 1) << 16));
344	restore_vblank = true;
345	}
346	/* sample in the vertical border, selecting the larger one */
347	if (vblank_start - vactive >= vtotal - vblank_end)
348	vsample = (vblank_start + vactive) >> 1;
349	else
350	vsample = (vtotal + vblank_end) >> 1;
351
352	/*
353	* Wait for the border to be displayed
354	*/
355	while (I915_READ(pipe_dsl_reg) >= vactive)
356	;
357	while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
358	;
359	/*
360	* Watch ST00 for an entire scanline
361	*/
362	detect = 0;
363	count = 0;
364	do {
365	count++;
366	/* Read the ST00 VGA status register */
367	st00 = I915_READ8(VGA_MSR_WRITE);
368	if (st00 & (1 << 4))
369	detect++;
370	} while ((I915_READ(pipe_dsl_reg) == dsl));
371
372	/* restore vblank if necessary */
373	if (restore_vblank)
374	I915_WRITE(vblank_reg, vblank);
375	/*
376	* If more than 3/4 of the scanline detected a monitor,
377	* then it is assumed to be present. This works even on i830,
378	* where there isn't any way to force the border color across
379	* the screen
380	*/
381	status = detect * 4 > count * 3 ?
382	connector_status_connected :
383	connector_status_disconnected;
384	}
385
386	/* Restore previous settings */
387	I915_WRITE(bclrpat_reg, save_bclrpat);
388
389	return status;
390	}
391
79e53945 JB	392	static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
	393	{
	394	struct drm_device *dev = connector->dev;
21d40d37 EA	395	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
21d40d37 EA	396	struct drm_encoder *encoder = &intel_encoder->enc;
e4a5d54f ML	397	struct drm_crtc *crtc;
	398	int dpms_mode;
	399	enum drm_connector_status status;
79e53945 JB	400
	401	if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
	402	if (intel_crt_detect_hotplug(connector))
	403	return connector_status_connected;
	404	else
	405	return connector_status_disconnected;
	406	}
	407
	408	if (intel_crt_detect_ddc(connector))
	409	return connector_status_connected;
	410
e4a5d54f ML	411	/* for pre-945g platforms use load detect */
e4a5d54f ML	412	if (encoder->crtc && encoder->crtc->enabled) {
21d40d37	413	status = intel_crt_load_detect(encoder->crtc, intel_encoder);
e4a5d54f	414	} else {
c1c43977	415	crtc = intel_get_load_detect_pipe(intel_encoder, connector,
e4a5d54f ML	416	NULL, &dpms_mode);
e4a5d54f ML	417	if (crtc) {
21d40d37	418	status = intel_crt_load_detect(crtc, intel_encoder);
c1c43977 ZW	419	intel_release_load_detect_pipe(intel_encoder,
c1c43977 ZW	420	connector, dpms_mode);
e4a5d54f ML	421	} else
	422	status = connector_status_unknown;
	423	}
	424
	425	return status;
79e53945 JB	426	}
	427
	428	static void intel_crt_destroy(struct drm_connector *connector)
	429	{
21d40d37	430	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
79e53945	431
21d40d37	432	intel_i2c_destroy(intel_encoder->ddc_bus);
79e53945 JB	433	drm_sysfs_connector_remove(connector);
	434	drm_connector_cleanup(connector);
	435	kfree(connector);
	436	}
	437
	438	static int intel_crt_get_modes(struct drm_connector *connector)
	439	{
8e4d36b9	440	int ret;
21d40d37	441	struct intel_encoder *intel_encoder = to_intel_encoder(connector);
335af9a2	442	struct i2c_adapter *ddc_bus;
8e4d36b9	443	struct drm_device *dev = connector->dev;
	444
	445
335af9a2	446	ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
8e4d36b9	447	if (ret \|\| !IS_G4X(dev))
	448	goto end;
	449
8e4d36b9	450	/* Try to probe digital port for output in DVI-I -> VGA mode. */
335af9a2	451	ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
8e4d36b9	452
335af9a2	453	if (!ddc_bus) {
8e4d36b9	454	dev_printk(KERN_ERR, &connector->dev->pdev->dev,
	455	"DDC bus registration failed for CRTDDC_D.\n");
	456	goto end;
	457	}
	458	/* Try to get modes by GPIOD port */
335af9a2 ZW	459	ret = intel_ddc_get_modes(connector, ddc_bus);
335af9a2 ZW	460	intel_i2c_destroy(ddc_bus);
8e4d36b9	461
	462	end:
	463	return ret;
	464
79e53945 JB	465	}
	466
	467	static int intel_crt_set_property(struct drm_connector *connector,
	468	struct drm_property *property,
	469	uint64_t value)
	470	{
79e53945 JB	471	return 0;
	472	}
	473
	474	/*
	475	* Routines for controlling stuff on the analog port
	476	*/
	477
	478	static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	479	.dpms = intel_crt_dpms,
	480	.mode_fixup = intel_crt_mode_fixup,
	481	.prepare = intel_encoder_prepare,
	482	.commit = intel_encoder_commit,
	483	.mode_set = intel_crt_mode_set,
	484	};
	485
	486	static const struct drm_connector_funcs intel_crt_connector_funcs = {
c9fb15f6	487	.dpms = drm_helper_connector_dpms,
79e53945 JB	488	.detect = intel_crt_detect,
	489	.fill_modes = drm_helper_probe_single_connector_modes,
	490	.destroy = intel_crt_destroy,
	491	.set_property = intel_crt_set_property,
	492	};
	493
	494	static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	495	.mode_valid = intel_crt_mode_valid,
	496	.get_modes = intel_crt_get_modes,
	497	.best_encoder = intel_best_encoder,
	498	};
	499
b358d0a6	500	static void intel_crt_enc_destroy(struct drm_encoder *encoder)
79e53945 JB	501	{
	502	drm_encoder_cleanup(encoder);
	503	}
	504
	505	static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	506	.destroy = intel_crt_enc_destroy,
	507	};
	508
	509	void intel_crt_init(struct drm_device *dev)
	510	{
	511	struct drm_connector *connector;
21d40d37	512	struct intel_encoder *intel_encoder;
db545019	513	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	514	u32 i2c_reg;
79e53945	515
21d40d37 EA	516	intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
21d40d37 EA	517	if (!intel_encoder)
79e53945 JB	518	return;
79e53945 JB	519
21d40d37 EA	520	connector = &intel_encoder->base;
21d40d37 EA	521	drm_connector_init(dev, &intel_encoder->base,
79e53945 JB	522	&intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
79e53945 JB	523
21d40d37	524	drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs,
79e53945 JB	525	DRM_MODE_ENCODER_DAC);
79e53945 JB	526
21d40d37 EA	527	drm_mode_connector_attach_encoder(&intel_encoder->base,
21d40d37 EA	528	&intel_encoder->enc);
79e53945 JB	529
79e53945 JB	530	/* Set up the DDC bus. */
bad720ff	531	if (HAS_PCH_SPLIT(dev))
2c07245f	532	i2c_reg = PCH_GPIOA;
db545019	533	else {
2c07245f	534	i2c_reg = GPIOA;
db545019	535	/* Use VBT information for CRT DDC if available */
29874f44	536	if (dev_priv->crt_ddc_bus != 0)
db545019 DMEA	537	i2c_reg = dev_priv->crt_ddc_bus;
db545019 DMEA	538	}
21d40d37 EA	539	intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
21d40d37 EA	540	if (!intel_encoder->ddc_bus) {
79e53945 JB	541	dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
	542	"failed.\n");
	543	return;
	544	}
	545
21d40d37 EA	546	intel_encoder->type = INTEL_OUTPUT_ANALOG;
21d40d37 EA	547	intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) \|
f8aed700 ML	548	(1 << INTEL_ANALOG_CLONE_BIT) \|
f8aed700 ML	549	(1 << INTEL_SDVO_LVDS_CLONE_BIT);
21d40d37	550	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
79e53945 JB	551	connector->interlace_allowed = 0;
	552	connector->doublescan_allowed = 0;
	553
21d40d37	554	drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
79e53945 JB	555	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
	556
	557	drm_sysfs_connector_add(connector);
b01f2c3a JB	558
b01f2c3a JB	559	dev_priv->hotplug_supported_mask \|= CRT_HOTPLUG_INT_STATUS;
79e53945	560	}