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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 JB |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
f5afcd3d | 34 | #include "drm_edid.h" |
79e53945 JB |
35 | #include "intel_drv.h" |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
e7dbb2f2 | 49 | bool force_hotplug_required; |
c9a1c4cd CW |
50 | }; |
51 | ||
52 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) | |
53 | { | |
54 | return container_of(intel_attached_encoder(connector), | |
55 | struct intel_crt, base); | |
56 | } | |
57 | ||
df0323c4 | 58 | static void pch_crt_dpms(struct drm_encoder *encoder, int mode) |
79e53945 JB |
59 | { |
60 | struct drm_device *dev = encoder->dev; | |
61 | struct drm_i915_private *dev_priv = dev->dev_private; | |
df0323c4 | 62 | u32 temp; |
79e53945 | 63 | |
df0323c4 JB |
64 | temp = I915_READ(PCH_ADPA); |
65 | temp &= ~ADPA_DAC_ENABLE; | |
66 | ||
67 | switch (mode) { | |
68 | case DRM_MODE_DPMS_ON: | |
69 | temp |= ADPA_DAC_ENABLE; | |
70 | break; | |
71 | case DRM_MODE_DPMS_STANDBY: | |
72 | case DRM_MODE_DPMS_SUSPEND: | |
73 | case DRM_MODE_DPMS_OFF: | |
74 | /* Just leave port enable cleared */ | |
75 | break; | |
76 | } | |
77 | ||
78 | I915_WRITE(PCH_ADPA, temp); | |
79 | } | |
2c07245f | 80 | |
df0323c4 JB |
81 | static void gmch_crt_dpms(struct drm_encoder *encoder, int mode) |
82 | { | |
83 | struct drm_device *dev = encoder->dev; | |
84 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85 | u32 temp; | |
86 | ||
87 | temp = I915_READ(ADPA); | |
79e53945 | 88 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 89 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 | 90 | |
0206e353 | 91 | switch (mode) { |
79e53945 JB |
92 | case DRM_MODE_DPMS_ON: |
93 | temp |= ADPA_DAC_ENABLE; | |
94 | break; | |
95 | case DRM_MODE_DPMS_STANDBY: | |
96 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
97 | break; | |
98 | case DRM_MODE_DPMS_SUSPEND: | |
99 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
100 | break; | |
101 | case DRM_MODE_DPMS_OFF: | |
102 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
103 | break; | |
104 | } | |
105 | ||
df0323c4 | 106 | I915_WRITE(ADPA, temp); |
79e53945 JB |
107 | } |
108 | ||
109 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
110 | struct drm_display_mode *mode) | |
111 | { | |
6bcdcd9e ZY |
112 | struct drm_device *dev = connector->dev; |
113 | ||
114 | int max_clock = 0; | |
79e53945 JB |
115 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
116 | return MODE_NO_DBLESCAN; | |
117 | ||
6bcdcd9e ZY |
118 | if (mode->clock < 25000) |
119 | return MODE_CLOCK_LOW; | |
120 | ||
a6c45cf0 | 121 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
122 | max_clock = 350000; |
123 | else | |
124 | max_clock = 400000; | |
125 | if (mode->clock > max_clock) | |
126 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
127 | |
128 | return MODE_OK; | |
129 | } | |
130 | ||
131 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
132 | struct drm_display_mode *mode, | |
133 | struct drm_display_mode *adjusted_mode) | |
134 | { | |
135 | return true; | |
136 | } | |
137 | ||
138 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
139 | struct drm_display_mode *mode, | |
140 | struct drm_display_mode *adjusted_mode) | |
141 | { | |
142 | ||
143 | struct drm_device *dev = encoder->dev; | |
144 | struct drm_crtc *crtc = encoder->crtc; | |
145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | int dpll_md_reg; | |
148 | u32 adpa, dpll_md; | |
2c07245f | 149 | u32 adpa_reg; |
79e53945 | 150 | |
9db4a9c7 | 151 | dpll_md_reg = DPLL_MD(intel_crtc->pipe); |
79e53945 | 152 | |
bad720ff | 153 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
154 | adpa_reg = PCH_ADPA; |
155 | else | |
156 | adpa_reg = ADPA; | |
157 | ||
79e53945 JB |
158 | /* |
159 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
160 | * XXX this needs to be adjusted when we really are cloning | |
161 | */ | |
a6c45cf0 | 162 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
79e53945 JB |
163 | dpll_md = I915_READ(dpll_md_reg); |
164 | I915_WRITE(dpll_md_reg, | |
165 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
166 | } | |
167 | ||
e7dbb2f2 | 168 | adpa = ADPA_HOTPLUG_BITS; |
79e53945 JB |
169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
170 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
171 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
172 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
173 | ||
75770564 JB |
174 | /* For CPT allow 3 pipe config, for others just use A or B */ |
175 | if (HAS_PCH_CPT(dev)) | |
176 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
177 | else if (intel_crtc->pipe == 0) | |
178 | adpa |= ADPA_PIPE_A_SELECT; | |
179 | else | |
180 | adpa |= ADPA_PIPE_B_SELECT; | |
79e53945 | 181 | |
9db4a9c7 JB |
182 | if (!HAS_PCH_SPLIT(dev)) |
183 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); | |
184 | ||
2c07245f ZW |
185 | I915_WRITE(adpa_reg, adpa); |
186 | } | |
187 | ||
f2b115e6 | 188 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
189 | { |
190 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 191 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 192 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 193 | u32 adpa; |
2c07245f ZW |
194 | bool ret; |
195 | ||
e7dbb2f2 KP |
196 | /* The first time through, trigger an explicit detection cycle */ |
197 | if (crt->force_hotplug_required) { | |
198 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
199 | u32 save_adpa; | |
67941da2 | 200 | |
e7dbb2f2 KP |
201 | crt->force_hotplug_required = 0; |
202 | ||
203 | save_adpa = adpa = I915_READ(PCH_ADPA); | |
204 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); | |
205 | ||
206 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
207 | if (turn_off_dac) | |
208 | adpa &= ~ADPA_DAC_ENABLE; | |
209 | ||
210 | I915_WRITE(PCH_ADPA, adpa); | |
211 | ||
212 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, | |
213 | 1000)) | |
214 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
215 | ||
216 | if (turn_off_dac) { | |
217 | I915_WRITE(PCH_ADPA, save_adpa); | |
218 | POSTING_READ(PCH_ADPA); | |
219 | } | |
a4a6b901 ZW |
220 | } |
221 | ||
2c07245f ZW |
222 | /* Check the status to see if both blue and green are on now */ |
223 | adpa = I915_READ(PCH_ADPA); | |
e7dbb2f2 | 224 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
225 | ret = true; |
226 | else | |
227 | ret = false; | |
e7dbb2f2 | 228 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 229 | |
2c07245f | 230 | return ret; |
79e53945 JB |
231 | } |
232 | ||
233 | /** | |
234 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
235 | * | |
236 | * Not for i915G/i915GM | |
237 | * | |
238 | * \return true if CRT is connected. | |
239 | * \return false if CRT is disconnected. | |
240 | */ | |
241 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
242 | { | |
243 | struct drm_device *dev = connector->dev; | |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
245 | u32 hotplug_en, orig, stat; |
246 | bool ret = false; | |
771cb081 | 247 | int i, tries = 0; |
2c07245f | 248 | |
bad720ff | 249 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 250 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 251 | |
771cb081 ZY |
252 | /* |
253 | * On 4 series desktop, CRT detect sequence need to be done twice | |
254 | * to get a reliable result. | |
255 | */ | |
79e53945 | 256 | |
771cb081 ZY |
257 | if (IS_G4X(dev) && !IS_GM45(dev)) |
258 | tries = 2; | |
259 | else | |
260 | tries = 1; | |
7a772c49 | 261 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
262 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
263 | ||
771cb081 | 264 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
265 | /* turn on the FORCE_DETECT */ |
266 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 267 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
268 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
269 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 270 | 1000)) |
79077319 | 271 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 272 | } |
79e53945 | 273 | |
7a772c49 AJ |
274 | stat = I915_READ(PORT_HOTPLUG_STAT); |
275 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
276 | ret = true; | |
277 | ||
278 | /* clear the interrupt we just generated, if any */ | |
279 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 280 | |
7a772c49 AJ |
281 | /* and put the bits back */ |
282 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
283 | ||
284 | return ret; | |
79e53945 JB |
285 | } |
286 | ||
f5afcd3d | 287 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 288 | { |
f5afcd3d | 289 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 290 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
79e53945 JB |
291 | |
292 | /* CRT should always be at 0, but check anyway */ | |
c9a1c4cd | 293 | if (crt->base.type != INTEL_OUTPUT_ANALOG) |
79e53945 JB |
294 | return false; |
295 | ||
c9a1c4cd | 296 | if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) { |
f5afcd3d DM |
297 | struct edid *edid; |
298 | bool is_digital = false; | |
3bd7d909 | 299 | struct i2c_adapter *i2c; |
f5afcd3d | 300 | |
3bd7d909 DK |
301 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
302 | edid = drm_get_edid(connector, i2c); | |
f5afcd3d DM |
303 | /* |
304 | * This may be a DVI-I connector with a shared DDC | |
305 | * link between analog and digital outputs, so we | |
306 | * have to check the EDID input spec of the attached device. | |
d3bcb757 CW |
307 | * |
308 | * On the other hand, what should we do if it is a broken EDID? | |
f5afcd3d DM |
309 | */ |
310 | if (edid != NULL) { | |
311 | is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
312 | connector->display_info.raw_edid = NULL; | |
313 | kfree(edid); | |
314 | } | |
315 | ||
316 | if (!is_digital) { | |
317 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
318 | return true; | |
d3bcb757 CW |
319 | } else { |
320 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
f5afcd3d | 321 | } |
6ec3d0c0 CW |
322 | } |
323 | ||
324 | return false; | |
79e53945 JB |
325 | } |
326 | ||
e4a5d54f | 327 | static enum drm_connector_status |
7173188d | 328 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 329 | { |
7173188d | 330 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 331 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 332 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
333 | uint32_t save_bclrpat; |
334 | uint32_t save_vtotal; | |
335 | uint32_t vtotal, vactive; | |
336 | uint32_t vsample; | |
337 | uint32_t vblank, vblank_start, vblank_end; | |
338 | uint32_t dsl; | |
339 | uint32_t bclrpat_reg; | |
340 | uint32_t vtotal_reg; | |
341 | uint32_t vblank_reg; | |
342 | uint32_t vsync_reg; | |
343 | uint32_t pipeconf_reg; | |
344 | uint32_t pipe_dsl_reg; | |
345 | uint8_t st00; | |
346 | enum drm_connector_status status; | |
347 | ||
6ec3d0c0 CW |
348 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
349 | ||
9db4a9c7 JB |
350 | bclrpat_reg = BCLRPAT(pipe); |
351 | vtotal_reg = VTOTAL(pipe); | |
352 | vblank_reg = VBLANK(pipe); | |
353 | vsync_reg = VSYNC(pipe); | |
354 | pipeconf_reg = PIPECONF(pipe); | |
355 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
356 | |
357 | save_bclrpat = I915_READ(bclrpat_reg); | |
358 | save_vtotal = I915_READ(vtotal_reg); | |
359 | vblank = I915_READ(vblank_reg); | |
360 | ||
361 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
362 | vactive = (save_vtotal & 0x7ff) + 1; | |
363 | ||
364 | vblank_start = (vblank & 0xfff) + 1; | |
365 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
366 | ||
367 | /* Set the border color to purple. */ | |
368 | I915_WRITE(bclrpat_reg, 0x500050); | |
369 | ||
a6c45cf0 | 370 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
371 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
372 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 373 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
374 | /* Wait for next Vblank to substitue |
375 | * border color for Color info */ | |
9d0498a2 | 376 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
377 | st00 = I915_READ8(VGA_MSR_WRITE); |
378 | status = ((st00 & (1 << 4)) != 0) ? | |
379 | connector_status_connected : | |
380 | connector_status_disconnected; | |
381 | ||
382 | I915_WRITE(pipeconf_reg, pipeconf); | |
383 | } else { | |
384 | bool restore_vblank = false; | |
385 | int count, detect; | |
386 | ||
387 | /* | |
388 | * If there isn't any border, add some. | |
389 | * Yes, this will flicker | |
390 | */ | |
391 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
392 | uint32_t vsync = I915_READ(vsync_reg); | |
393 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
394 | ||
395 | vblank_start = vsync_start; | |
396 | I915_WRITE(vblank_reg, | |
397 | (vblank_start - 1) | | |
398 | ((vblank_end - 1) << 16)); | |
399 | restore_vblank = true; | |
400 | } | |
401 | /* sample in the vertical border, selecting the larger one */ | |
402 | if (vblank_start - vactive >= vtotal - vblank_end) | |
403 | vsample = (vblank_start + vactive) >> 1; | |
404 | else | |
405 | vsample = (vtotal + vblank_end) >> 1; | |
406 | ||
407 | /* | |
408 | * Wait for the border to be displayed | |
409 | */ | |
410 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
411 | ; | |
412 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
413 | ; | |
414 | /* | |
415 | * Watch ST00 for an entire scanline | |
416 | */ | |
417 | detect = 0; | |
418 | count = 0; | |
419 | do { | |
420 | count++; | |
421 | /* Read the ST00 VGA status register */ | |
422 | st00 = I915_READ8(VGA_MSR_WRITE); | |
423 | if (st00 & (1 << 4)) | |
424 | detect++; | |
425 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
426 | ||
427 | /* restore vblank if necessary */ | |
428 | if (restore_vblank) | |
429 | I915_WRITE(vblank_reg, vblank); | |
430 | /* | |
431 | * If more than 3/4 of the scanline detected a monitor, | |
432 | * then it is assumed to be present. This works even on i830, | |
433 | * where there isn't any way to force the border color across | |
434 | * the screen | |
435 | */ | |
436 | status = detect * 4 > count * 3 ? | |
437 | connector_status_connected : | |
438 | connector_status_disconnected; | |
439 | } | |
440 | ||
441 | /* Restore previous settings */ | |
442 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
443 | ||
444 | return status; | |
445 | } | |
446 | ||
7b334fcb | 447 | static enum drm_connector_status |
930a9e28 | 448 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
449 | { |
450 | struct drm_device *dev = connector->dev; | |
c9a1c4cd | 451 | struct intel_crt *crt = intel_attached_crt(connector); |
e4a5d54f | 452 | enum drm_connector_status status; |
e95c8438 | 453 | struct intel_load_detect_pipe tmp; |
79e53945 | 454 | |
a6c45cf0 | 455 | if (I915_HAS_HOTPLUG(dev)) { |
6ec3d0c0 CW |
456 | if (intel_crt_detect_hotplug(connector)) { |
457 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
79e53945 | 458 | return connector_status_connected; |
e7dbb2f2 KP |
459 | } else { |
460 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); | |
79e53945 | 461 | return connector_status_disconnected; |
e7dbb2f2 | 462 | } |
79e53945 JB |
463 | } |
464 | ||
f5afcd3d | 465 | if (intel_crt_detect_ddc(connector)) |
79e53945 JB |
466 | return connector_status_connected; |
467 | ||
930a9e28 | 468 | if (!force) |
7b334fcb CW |
469 | return connector->status; |
470 | ||
e4a5d54f | 471 | /* for pre-945g platforms use load detect */ |
e95c8438 DV |
472 | if (intel_get_load_detect_pipe(&crt->base, connector, NULL, |
473 | &tmp)) { | |
474 | if (intel_crt_detect_ddc(connector)) | |
475 | status = connector_status_connected; | |
476 | else | |
477 | status = intel_crt_load_detect(crt); | |
478 | intel_release_load_detect_pipe(&crt->base, connector, | |
479 | &tmp); | |
480 | } else | |
481 | status = connector_status_unknown; | |
e4a5d54f ML |
482 | |
483 | return status; | |
79e53945 JB |
484 | } |
485 | ||
486 | static void intel_crt_destroy(struct drm_connector *connector) | |
487 | { | |
79e53945 JB |
488 | drm_sysfs_connector_remove(connector); |
489 | drm_connector_cleanup(connector); | |
490 | kfree(connector); | |
491 | } | |
492 | ||
493 | static int intel_crt_get_modes(struct drm_connector *connector) | |
494 | { | |
8e4d36b9 | 495 | struct drm_device *dev = connector->dev; |
f899fc64 | 496 | struct drm_i915_private *dev_priv = dev->dev_private; |
890f3359 | 497 | int ret; |
3bd7d909 | 498 | struct i2c_adapter *i2c; |
8e4d36b9 | 499 | |
3bd7d909 DK |
500 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
501 | ret = intel_ddc_get_modes(connector, i2c); | |
8e4d36b9 | 502 | if (ret || !IS_G4X(dev)) |
f899fc64 | 503 | return ret; |
8e4d36b9 | 504 | |
8e4d36b9 | 505 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 DK |
506 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
507 | return intel_ddc_get_modes(connector, i2c); | |
79e53945 JB |
508 | } |
509 | ||
510 | static int intel_crt_set_property(struct drm_connector *connector, | |
511 | struct drm_property *property, | |
512 | uint64_t value) | |
513 | { | |
79e53945 JB |
514 | return 0; |
515 | } | |
516 | ||
f3269058 CW |
517 | static void intel_crt_reset(struct drm_connector *connector) |
518 | { | |
519 | struct drm_device *dev = connector->dev; | |
520 | struct intel_crt *crt = intel_attached_crt(connector); | |
521 | ||
522 | if (HAS_PCH_SPLIT(dev)) | |
523 | crt->force_hotplug_required = 1; | |
524 | } | |
525 | ||
79e53945 JB |
526 | /* |
527 | * Routines for controlling stuff on the analog port | |
528 | */ | |
529 | ||
df0323c4 JB |
530 | static const struct drm_encoder_helper_funcs pch_encoder_funcs = { |
531 | .mode_fixup = intel_crt_mode_fixup, | |
532 | .prepare = intel_encoder_prepare, | |
533 | .commit = intel_encoder_commit, | |
534 | .mode_set = intel_crt_mode_set, | |
535 | .dpms = pch_crt_dpms, | |
536 | }; | |
537 | ||
538 | static const struct drm_encoder_helper_funcs gmch_encoder_funcs = { | |
79e53945 JB |
539 | .mode_fixup = intel_crt_mode_fixup, |
540 | .prepare = intel_encoder_prepare, | |
541 | .commit = intel_encoder_commit, | |
542 | .mode_set = intel_crt_mode_set, | |
df0323c4 | 543 | .dpms = gmch_crt_dpms, |
79e53945 JB |
544 | }; |
545 | ||
546 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
f3269058 | 547 | .reset = intel_crt_reset, |
c9fb15f6 | 548 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
549 | .detect = intel_crt_detect, |
550 | .fill_modes = drm_helper_probe_single_connector_modes, | |
551 | .destroy = intel_crt_destroy, | |
552 | .set_property = intel_crt_set_property, | |
553 | }; | |
554 | ||
555 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
556 | .mode_valid = intel_crt_mode_valid, | |
557 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 558 | .best_encoder = intel_best_encoder, |
79e53945 JB |
559 | }; |
560 | ||
79e53945 | 561 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 562 | .destroy = intel_encoder_destroy, |
79e53945 JB |
563 | }; |
564 | ||
8ca4013d DL |
565 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
566 | { | |
bc0daf48 | 567 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
568 | return 1; |
569 | } | |
570 | ||
571 | static const struct dmi_system_id intel_no_crt[] = { | |
572 | { | |
573 | .callback = intel_no_crt_dmi_callback, | |
574 | .ident = "ACER ZGB", | |
575 | .matches = { | |
576 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
577 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
578 | }, | |
579 | }, | |
580 | { } | |
581 | }; | |
582 | ||
79e53945 JB |
583 | void intel_crt_init(struct drm_device *dev) |
584 | { | |
585 | struct drm_connector *connector; | |
c9a1c4cd | 586 | struct intel_crt *crt; |
454c1ca8 | 587 | struct intel_connector *intel_connector; |
db545019 | 588 | struct drm_i915_private *dev_priv = dev->dev_private; |
df0323c4 | 589 | const struct drm_encoder_helper_funcs *encoder_helper_funcs; |
79e53945 | 590 | |
8ca4013d DL |
591 | /* Skip machines without VGA that falsely report hotplug events */ |
592 | if (dmi_check_system(intel_no_crt)) | |
593 | return; | |
594 | ||
c9a1c4cd CW |
595 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
596 | if (!crt) | |
79e53945 JB |
597 | return; |
598 | ||
454c1ca8 ZW |
599 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
600 | if (!intel_connector) { | |
c9a1c4cd | 601 | kfree(crt); |
454c1ca8 ZW |
602 | return; |
603 | } | |
604 | ||
605 | connector = &intel_connector->base; | |
606 | drm_connector_init(dev, &intel_connector->base, | |
79e53945 JB |
607 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
608 | ||
c9a1c4cd | 609 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
610 | DRM_MODE_ENCODER_DAC); |
611 | ||
c9a1c4cd | 612 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 613 | |
c9a1c4cd CW |
614 | crt->base.type = INTEL_OUTPUT_ANALOG; |
615 | crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT | | |
616 | 1 << INTEL_ANALOG_CLONE_BIT | | |
617 | 1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
59c859d6 ED |
618 | if (IS_HASWELL(dev)) |
619 | crt->base.crtc_mask = (1 << 0); | |
620 | else | |
621 | crt->base.crtc_mask = (1 << 0) | (1 << 1); | |
622 | ||
dbb02575 DV |
623 | if (IS_GEN2(dev)) |
624 | connector->interlace_allowed = 0; | |
625 | else | |
626 | connector->interlace_allowed = 1; | |
79e53945 JB |
627 | connector->doublescan_allowed = 0; |
628 | ||
df0323c4 JB |
629 | if (HAS_PCH_SPLIT(dev)) |
630 | encoder_helper_funcs = &pch_encoder_funcs; | |
631 | else | |
632 | encoder_helper_funcs = &gmch_encoder_funcs; | |
633 | ||
634 | drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs); | |
79e53945 JB |
635 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
636 | ||
637 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 638 | |
eb1f8e4f DA |
639 | if (I915_HAS_HOTPLUG(dev)) |
640 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
641 | else | |
642 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
643 | ||
e7dbb2f2 KP |
644 | /* |
645 | * Configure the automatic hotplug detection stuff | |
646 | */ | |
647 | crt->force_hotplug_required = 0; | |
648 | if (HAS_PCH_SPLIT(dev)) { | |
649 | u32 adpa; | |
650 | ||
651 | adpa = I915_READ(PCH_ADPA); | |
652 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | |
653 | adpa |= ADPA_HOTPLUG_BITS; | |
654 | I915_WRITE(PCH_ADPA, adpa); | |
655 | POSTING_READ(PCH_ADPA); | |
656 | ||
657 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); | |
658 | crt->force_hotplug_required = 1; | |
659 | } | |
660 | ||
b01f2c3a | 661 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
79e53945 | 662 | } |