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Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_edid.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
79e53945 JB |
36 | #include "i915_drv.h" |
37 | ||
e7dbb2f2 KP |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
44 | ADPA_CRT_HOTPLUG_ENABLE) | |
45 | ||
c9a1c4cd CW |
46 | struct intel_crt { |
47 | struct intel_encoder base; | |
637f44d2 AJ |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ | |
50 | struct intel_connector *connector; | |
e7dbb2f2 | 51 | bool force_hotplug_required; |
540a8950 | 52 | u32 adpa_reg; |
c9a1c4cd CW |
53 | }; |
54 | ||
eebe6f0b | 55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 56 | { |
eebe6f0b | 57 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
58 | } |
59 | ||
eebe6f0b | 60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 61 | { |
eebe6f0b | 62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
63 | } |
64 | ||
e403fc94 DV |
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
66 | enum pipe *pipe) | |
79e53945 | 67 | { |
e403fc94 | 68 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 DV |
70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
71 | u32 tmp; | |
72 | ||
73 | tmp = I915_READ(crt->adpa_reg); | |
74 | ||
75 | if (!(tmp & ADPA_DAC_ENABLE)) | |
76 | return false; | |
77 | ||
78 | if (HAS_PCH_CPT(dev)) | |
79 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
80 | else | |
81 | *pipe = PORT_TO_PIPE(tmp); | |
82 | ||
83 | return true; | |
84 | } | |
85 | ||
6801c18c | 86 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
87 | { |
88 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
89 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
90 | u32 tmp, flags = 0; | |
91 | ||
92 | tmp = I915_READ(crt->adpa_reg); | |
93 | ||
94 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
95 | flags |= DRM_MODE_FLAG_PHSYNC; | |
96 | else | |
97 | flags |= DRM_MODE_FLAG_NHSYNC; | |
98 | ||
99 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
100 | flags |= DRM_MODE_FLAG_PVSYNC; | |
101 | else | |
102 | flags |= DRM_MODE_FLAG_NVSYNC; | |
103 | ||
6801c18c VS |
104 | return flags; |
105 | } | |
106 | ||
107 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
108 | struct intel_crtc_config *pipe_config) | |
109 | { | |
110 | struct drm_device *dev = encoder->base.dev; | |
111 | int dotclock; | |
112 | ||
113 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); | |
18442d08 VS |
114 | |
115 | dotclock = pipe_config->port_clock; | |
116 | ||
6801c18c | 117 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
118 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
119 | ||
241bfc38 | 120 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
121 | } |
122 | ||
6801c18c VS |
123 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
124 | struct intel_crtc_config *pipe_config) | |
125 | { | |
126 | intel_ddi_get_config(encoder, pipe_config); | |
127 | ||
128 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | | |
129 | DRM_MODE_FLAG_NHSYNC | | |
130 | DRM_MODE_FLAG_PVSYNC | | |
131 | DRM_MODE_FLAG_NVSYNC); | |
132 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); | |
133 | } | |
134 | ||
b2cabb0e DV |
135 | /* Note: The caller is required to filter out dpms modes not supported by the |
136 | * platform. */ | |
137 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 138 | { |
b2cabb0e | 139 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 140 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 141 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
df0323c4 JB |
142 | u32 temp; |
143 | ||
b2cabb0e | 144 | temp = I915_READ(crt->adpa_reg); |
79e53945 | 145 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 146 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 | 147 | |
0206e353 | 148 | switch (mode) { |
79e53945 JB |
149 | case DRM_MODE_DPMS_ON: |
150 | temp |= ADPA_DAC_ENABLE; | |
151 | break; | |
152 | case DRM_MODE_DPMS_STANDBY: | |
153 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
154 | break; | |
155 | case DRM_MODE_DPMS_SUSPEND: | |
156 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
157 | break; | |
158 | case DRM_MODE_DPMS_OFF: | |
159 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
160 | break; | |
161 | } | |
162 | ||
b2cabb0e | 163 | I915_WRITE(crt->adpa_reg, temp); |
df0323c4 | 164 | } |
2c07245f | 165 | |
637f44d2 AJ |
166 | static void intel_disable_crt(struct intel_encoder *encoder) |
167 | { | |
168 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
169 | } | |
170 | ||
171 | static void intel_enable_crt(struct intel_encoder *encoder) | |
172 | { | |
173 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
174 | ||
175 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
176 | } | |
177 | ||
6b1c087b | 178 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 179 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 180 | { |
b2cabb0e DV |
181 | struct drm_device *dev = connector->dev; |
182 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
183 | struct drm_crtc *crtc; | |
184 | int old_dpms; | |
79e53945 | 185 | |
b2cabb0e | 186 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 187 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
188 | mode = DRM_MODE_DPMS_OFF; |
189 | ||
b2cabb0e DV |
190 | if (mode == connector->dpms) |
191 | return; | |
192 | ||
193 | old_dpms = connector->dpms; | |
194 | connector->dpms = mode; | |
195 | ||
196 | /* Only need to change hw state when actually enabled */ | |
197 | crtc = encoder->base.crtc; | |
198 | if (!crtc) { | |
199 | encoder->connectors_active = false; | |
200 | return; | |
79e53945 JB |
201 | } |
202 | ||
b2cabb0e DV |
203 | /* We need the pipe to run for anything but OFF. */ |
204 | if (mode == DRM_MODE_DPMS_OFF) | |
205 | encoder->connectors_active = false; | |
206 | else | |
207 | encoder->connectors_active = true; | |
208 | ||
6b1c087b JN |
209 | /* We call connector dpms manually below in case pipe dpms doesn't |
210 | * change due to cloning. */ | |
b2cabb0e DV |
211 | if (mode < old_dpms) { |
212 | /* From off to on, enable the pipe first. */ | |
213 | intel_crtc_update_dpms(crtc); | |
214 | ||
215 | intel_crt_set_dpms(encoder, mode); | |
216 | } else { | |
217 | intel_crt_set_dpms(encoder, mode); | |
218 | ||
219 | intel_crtc_update_dpms(crtc); | |
220 | } | |
0a91ca29 | 221 | |
b980514c | 222 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
223 | } |
224 | ||
c19de8eb DL |
225 | static enum drm_mode_status |
226 | intel_crt_mode_valid(struct drm_connector *connector, | |
227 | struct drm_display_mode *mode) | |
79e53945 | 228 | { |
6bcdcd9e ZY |
229 | struct drm_device *dev = connector->dev; |
230 | ||
231 | int max_clock = 0; | |
79e53945 JB |
232 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
233 | return MODE_NO_DBLESCAN; | |
234 | ||
6bcdcd9e ZY |
235 | if (mode->clock < 25000) |
236 | return MODE_CLOCK_LOW; | |
237 | ||
a6c45cf0 | 238 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
239 | max_clock = 350000; |
240 | else | |
241 | max_clock = 400000; | |
242 | if (mode->clock > max_clock) | |
243 | return MODE_CLOCK_HIGH; | |
79e53945 | 244 | |
d4b1931c PZ |
245 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
246 | if (HAS_PCH_LPT(dev) && | |
247 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
248 | return MODE_CLOCK_HIGH; | |
249 | ||
79e53945 JB |
250 | return MODE_OK; |
251 | } | |
252 | ||
5bfe2ac0 DV |
253 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
254 | struct intel_crtc_config *pipe_config) | |
79e53945 | 255 | { |
5bfe2ac0 DV |
256 | struct drm_device *dev = encoder->base.dev; |
257 | ||
258 | if (HAS_PCH_SPLIT(dev)) | |
259 | pipe_config->has_pch_encoder = true; | |
260 | ||
2a7aceec DV |
261 | /* LPT FDI RX only supports 8bpc. */ |
262 | if (HAS_PCH_LPT(dev)) | |
263 | pipe_config->pipe_bpp = 24; | |
264 | ||
79e53945 JB |
265 | return true; |
266 | } | |
267 | ||
eebe6f0b | 268 | static void intel_crt_mode_set(struct intel_encoder *encoder) |
79e53945 JB |
269 | { |
270 | ||
eebe6f0b DV |
271 | struct drm_device *dev = encoder->base.dev; |
272 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
273 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
79e53945 | 274 | struct drm_i915_private *dev_priv = dev->dev_private; |
eebe6f0b | 275 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
6478d414 | 276 | u32 adpa; |
79e53945 | 277 | |
533df0fe | 278 | if (INTEL_INFO(dev)->gen >= 5) |
912d812e DV |
279 | adpa = ADPA_HOTPLUG_BITS; |
280 | else | |
281 | adpa = 0; | |
282 | ||
79e53945 JB |
283 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
284 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
285 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
286 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
287 | ||
75770564 | 288 | /* For CPT allow 3 pipe config, for others just use A or B */ |
4837813a PZ |
289 | if (HAS_PCH_LPT(dev)) |
290 | ; /* Those bits don't exist here */ | |
291 | else if (HAS_PCH_CPT(dev)) | |
eebe6f0b DV |
292 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
293 | else if (crtc->pipe == 0) | |
75770564 JB |
294 | adpa |= ADPA_PIPE_A_SELECT; |
295 | else | |
296 | adpa |= ADPA_PIPE_B_SELECT; | |
79e53945 | 297 | |
9db4a9c7 | 298 | if (!HAS_PCH_SPLIT(dev)) |
eebe6f0b | 299 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
9db4a9c7 | 300 | |
540a8950 | 301 | I915_WRITE(crt->adpa_reg, adpa); |
2c07245f ZW |
302 | } |
303 | ||
f2b115e6 | 304 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
305 | { |
306 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 307 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 308 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 309 | u32 adpa; |
2c07245f ZW |
310 | bool ret; |
311 | ||
e7dbb2f2 KP |
312 | /* The first time through, trigger an explicit detection cycle */ |
313 | if (crt->force_hotplug_required) { | |
314 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
315 | u32 save_adpa; | |
67941da2 | 316 | |
e7dbb2f2 KP |
317 | crt->force_hotplug_required = 0; |
318 | ||
ca54b810 | 319 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
320 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
321 | ||
322 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
323 | if (turn_off_dac) | |
324 | adpa &= ~ADPA_DAC_ENABLE; | |
325 | ||
ca54b810 | 326 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 327 | |
ca54b810 | 328 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
329 | 1000)) |
330 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
331 | ||
332 | if (turn_off_dac) { | |
ca54b810 VS |
333 | I915_WRITE(crt->adpa_reg, save_adpa); |
334 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 335 | } |
a4a6b901 ZW |
336 | } |
337 | ||
2c07245f | 338 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 339 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 340 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
341 | ret = true; |
342 | else | |
343 | ret = false; | |
e7dbb2f2 | 344 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 345 | |
2c07245f | 346 | return ret; |
79e53945 JB |
347 | } |
348 | ||
7d2c24e8 JB |
349 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
350 | { | |
351 | struct drm_device *dev = connector->dev; | |
ca54b810 | 352 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
353 | struct drm_i915_private *dev_priv = dev->dev_private; |
354 | u32 adpa; | |
355 | bool ret; | |
356 | u32 save_adpa; | |
357 | ||
ca54b810 | 358 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
359 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
360 | ||
361 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
362 | ||
ca54b810 | 363 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 364 | |
ca54b810 | 365 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
366 | 1000)) { |
367 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 368 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
369 | } |
370 | ||
371 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 372 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
373 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
374 | ret = true; | |
375 | else | |
376 | ret = false; | |
377 | ||
378 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
379 | ||
7d2c24e8 JB |
380 | return ret; |
381 | } | |
382 | ||
79e53945 JB |
383 | /** |
384 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
385 | * | |
386 | * Not for i915G/i915GM | |
387 | * | |
388 | * \return true if CRT is connected. | |
389 | * \return false if CRT is disconnected. | |
390 | */ | |
391 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
392 | { | |
393 | struct drm_device *dev = connector->dev; | |
394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
395 | u32 hotplug_en, orig, stat; |
396 | bool ret = false; | |
771cb081 | 397 | int i, tries = 0; |
2c07245f | 398 | |
bad720ff | 399 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 400 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 401 | |
7d2c24e8 JB |
402 | if (IS_VALLEYVIEW(dev)) |
403 | return valleyview_crt_detect_hotplug(connector); | |
404 | ||
771cb081 ZY |
405 | /* |
406 | * On 4 series desktop, CRT detect sequence need to be done twice | |
407 | * to get a reliable result. | |
408 | */ | |
79e53945 | 409 | |
771cb081 ZY |
410 | if (IS_G4X(dev) && !IS_GM45(dev)) |
411 | tries = 2; | |
412 | else | |
413 | tries = 1; | |
7a772c49 | 414 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
415 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
416 | ||
771cb081 | 417 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
418 | /* turn on the FORCE_DETECT */ |
419 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 420 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
421 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
422 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 423 | 1000)) |
79077319 | 424 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 425 | } |
79e53945 | 426 | |
7a772c49 AJ |
427 | stat = I915_READ(PORT_HOTPLUG_STAT); |
428 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
429 | ret = true; | |
430 | ||
431 | /* clear the interrupt we just generated, if any */ | |
432 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 433 | |
7a772c49 AJ |
434 | /* and put the bits back */ |
435 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
436 | ||
437 | return ret; | |
79e53945 JB |
438 | } |
439 | ||
f1a2f5b7 JN |
440 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
441 | struct i2c_adapter *i2c) | |
442 | { | |
443 | struct edid *edid; | |
444 | ||
445 | edid = drm_get_edid(connector, i2c); | |
446 | ||
447 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
448 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
449 | intel_gmbus_force_bit(i2c, true); | |
450 | edid = drm_get_edid(connector, i2c); | |
451 | intel_gmbus_force_bit(i2c, false); | |
452 | } | |
453 | ||
454 | return edid; | |
455 | } | |
456 | ||
457 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
458 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
459 | struct i2c_adapter *adapter) | |
460 | { | |
461 | struct edid *edid; | |
ebda95a9 | 462 | int ret; |
f1a2f5b7 JN |
463 | |
464 | edid = intel_crt_get_edid(connector, adapter); | |
465 | if (!edid) | |
466 | return 0; | |
467 | ||
ebda95a9 JN |
468 | ret = intel_connector_update_modes(connector, edid); |
469 | kfree(edid); | |
470 | ||
471 | return ret; | |
f1a2f5b7 JN |
472 | } |
473 | ||
f5afcd3d | 474 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 475 | { |
f5afcd3d | 476 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 477 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
478 | struct edid *edid; |
479 | struct i2c_adapter *i2c; | |
79e53945 | 480 | |
a2bd1f54 | 481 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 482 | |
41aa3448 | 483 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 484 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
485 | |
486 | if (edid) { | |
487 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 488 | |
f5afcd3d DM |
489 | /* |
490 | * This may be a DVI-I connector with a shared DDC | |
491 | * link between analog and digital outputs, so we | |
492 | * have to check the EDID input spec of the attached device. | |
493 | */ | |
f5afcd3d DM |
494 | if (!is_digital) { |
495 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
496 | return true; | |
497 | } | |
a2bd1f54 DV |
498 | |
499 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
500 | } else { | |
501 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
502 | } |
503 | ||
a2bd1f54 DV |
504 | kfree(edid); |
505 | ||
6ec3d0c0 | 506 | return false; |
79e53945 JB |
507 | } |
508 | ||
e4a5d54f | 509 | static enum drm_connector_status |
7173188d | 510 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 511 | { |
7173188d | 512 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 513 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 514 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
515 | uint32_t save_bclrpat; |
516 | uint32_t save_vtotal; | |
517 | uint32_t vtotal, vactive; | |
518 | uint32_t vsample; | |
519 | uint32_t vblank, vblank_start, vblank_end; | |
520 | uint32_t dsl; | |
521 | uint32_t bclrpat_reg; | |
522 | uint32_t vtotal_reg; | |
523 | uint32_t vblank_reg; | |
524 | uint32_t vsync_reg; | |
525 | uint32_t pipeconf_reg; | |
526 | uint32_t pipe_dsl_reg; | |
527 | uint8_t st00; | |
528 | enum drm_connector_status status; | |
529 | ||
6ec3d0c0 CW |
530 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
531 | ||
9db4a9c7 JB |
532 | bclrpat_reg = BCLRPAT(pipe); |
533 | vtotal_reg = VTOTAL(pipe); | |
534 | vblank_reg = VBLANK(pipe); | |
535 | vsync_reg = VSYNC(pipe); | |
536 | pipeconf_reg = PIPECONF(pipe); | |
537 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
538 | |
539 | save_bclrpat = I915_READ(bclrpat_reg); | |
540 | save_vtotal = I915_READ(vtotal_reg); | |
541 | vblank = I915_READ(vblank_reg); | |
542 | ||
543 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
544 | vactive = (save_vtotal & 0x7ff) + 1; | |
545 | ||
546 | vblank_start = (vblank & 0xfff) + 1; | |
547 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
548 | ||
549 | /* Set the border color to purple. */ | |
550 | I915_WRITE(bclrpat_reg, 0x500050); | |
551 | ||
a6c45cf0 | 552 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
553 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
554 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 555 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
556 | /* Wait for next Vblank to substitue |
557 | * border color for Color info */ | |
9d0498a2 | 558 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
559 | st00 = I915_READ8(VGA_MSR_WRITE); |
560 | status = ((st00 & (1 << 4)) != 0) ? | |
561 | connector_status_connected : | |
562 | connector_status_disconnected; | |
563 | ||
564 | I915_WRITE(pipeconf_reg, pipeconf); | |
565 | } else { | |
566 | bool restore_vblank = false; | |
567 | int count, detect; | |
568 | ||
569 | /* | |
570 | * If there isn't any border, add some. | |
571 | * Yes, this will flicker | |
572 | */ | |
573 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
574 | uint32_t vsync = I915_READ(vsync_reg); | |
575 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
576 | ||
577 | vblank_start = vsync_start; | |
578 | I915_WRITE(vblank_reg, | |
579 | (vblank_start - 1) | | |
580 | ((vblank_end - 1) << 16)); | |
581 | restore_vblank = true; | |
582 | } | |
583 | /* sample in the vertical border, selecting the larger one */ | |
584 | if (vblank_start - vactive >= vtotal - vblank_end) | |
585 | vsample = (vblank_start + vactive) >> 1; | |
586 | else | |
587 | vsample = (vtotal + vblank_end) >> 1; | |
588 | ||
589 | /* | |
590 | * Wait for the border to be displayed | |
591 | */ | |
592 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
593 | ; | |
594 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
595 | ; | |
596 | /* | |
597 | * Watch ST00 for an entire scanline | |
598 | */ | |
599 | detect = 0; | |
600 | count = 0; | |
601 | do { | |
602 | count++; | |
603 | /* Read the ST00 VGA status register */ | |
604 | st00 = I915_READ8(VGA_MSR_WRITE); | |
605 | if (st00 & (1 << 4)) | |
606 | detect++; | |
607 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
608 | ||
609 | /* restore vblank if necessary */ | |
610 | if (restore_vblank) | |
611 | I915_WRITE(vblank_reg, vblank); | |
612 | /* | |
613 | * If more than 3/4 of the scanline detected a monitor, | |
614 | * then it is assumed to be present. This works even on i830, | |
615 | * where there isn't any way to force the border color across | |
616 | * the screen | |
617 | */ | |
618 | status = detect * 4 > count * 3 ? | |
619 | connector_status_connected : | |
620 | connector_status_disconnected; | |
621 | } | |
622 | ||
623 | /* Restore previous settings */ | |
624 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
625 | ||
626 | return status; | |
627 | } | |
628 | ||
7b334fcb | 629 | static enum drm_connector_status |
930a9e28 | 630 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
631 | { |
632 | struct drm_device *dev = connector->dev; | |
c9a1c4cd | 633 | struct intel_crt *crt = intel_attached_crt(connector); |
e4a5d54f | 634 | enum drm_connector_status status; |
e95c8438 | 635 | struct intel_load_detect_pipe tmp; |
79e53945 | 636 | |
164c8598 CW |
637 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
638 | connector->base.id, drm_get_connector_name(connector), | |
639 | force); | |
640 | ||
a6c45cf0 | 641 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
642 | /* We can not rely on the HPD pin always being correctly wired |
643 | * up, for example many KVM do not pass it through, and so | |
644 | * only trust an assertion that the monitor is connected. | |
645 | */ | |
6ec3d0c0 CW |
646 | if (intel_crt_detect_hotplug(connector)) { |
647 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
79e53945 | 648 | return connector_status_connected; |
aaa37730 | 649 | } else |
e7dbb2f2 | 650 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
651 | } |
652 | ||
f5afcd3d | 653 | if (intel_crt_detect_ddc(connector)) |
79e53945 JB |
654 | return connector_status_connected; |
655 | ||
aaa37730 DV |
656 | /* Load detection is broken on HPD capable machines. Whoever wants a |
657 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
658 | * to have the right resistors for HP detection) needs to fix this up. | |
659 | * For now just bail out. */ | |
660 | if (I915_HAS_HOTPLUG(dev)) | |
661 | return connector_status_disconnected; | |
662 | ||
930a9e28 | 663 | if (!force) |
7b334fcb CW |
664 | return connector->status; |
665 | ||
e4a5d54f | 666 | /* for pre-945g platforms use load detect */ |
d2434ab7 | 667 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
e95c8438 DV |
668 | if (intel_crt_detect_ddc(connector)) |
669 | status = connector_status_connected; | |
670 | else | |
671 | status = intel_crt_load_detect(crt); | |
d2434ab7 | 672 | intel_release_load_detect_pipe(connector, &tmp); |
e95c8438 DV |
673 | } else |
674 | status = connector_status_unknown; | |
e4a5d54f ML |
675 | |
676 | return status; | |
79e53945 JB |
677 | } |
678 | ||
679 | static void intel_crt_destroy(struct drm_connector *connector) | |
680 | { | |
79e53945 JB |
681 | drm_connector_cleanup(connector); |
682 | kfree(connector); | |
683 | } | |
684 | ||
685 | static int intel_crt_get_modes(struct drm_connector *connector) | |
686 | { | |
8e4d36b9 | 687 | struct drm_device *dev = connector->dev; |
f899fc64 | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
890f3359 | 689 | int ret; |
3bd7d909 | 690 | struct i2c_adapter *i2c; |
8e4d36b9 | 691 | |
41aa3448 | 692 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 693 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 694 | if (ret || !IS_G4X(dev)) |
f899fc64 | 695 | return ret; |
8e4d36b9 | 696 | |
8e4d36b9 | 697 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 | 698 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
f1a2f5b7 | 699 | return intel_crt_ddc_get_modes(connector, i2c); |
79e53945 JB |
700 | } |
701 | ||
702 | static int intel_crt_set_property(struct drm_connector *connector, | |
703 | struct drm_property *property, | |
704 | uint64_t value) | |
705 | { | |
79e53945 JB |
706 | return 0; |
707 | } | |
708 | ||
f3269058 CW |
709 | static void intel_crt_reset(struct drm_connector *connector) |
710 | { | |
711 | struct drm_device *dev = connector->dev; | |
2e938892 | 712 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
713 | struct intel_crt *crt = intel_attached_crt(connector); |
714 | ||
10603caa | 715 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
716 | u32 adpa; |
717 | ||
ca54b810 | 718 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
719 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
720 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
721 | I915_WRITE(crt->adpa_reg, adpa); |
722 | POSTING_READ(crt->adpa_reg); | |
2e938892 DV |
723 | |
724 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); | |
f3269058 | 725 | crt->force_hotplug_required = 1; |
2e938892 DV |
726 | } |
727 | ||
f3269058 CW |
728 | } |
729 | ||
79e53945 JB |
730 | /* |
731 | * Routines for controlling stuff on the analog port | |
732 | */ | |
733 | ||
79e53945 | 734 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 735 | .reset = intel_crt_reset, |
b2cabb0e | 736 | .dpms = intel_crt_dpms, |
79e53945 JB |
737 | .detect = intel_crt_detect, |
738 | .fill_modes = drm_helper_probe_single_connector_modes, | |
739 | .destroy = intel_crt_destroy, | |
740 | .set_property = intel_crt_set_property, | |
741 | }; | |
742 | ||
743 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
744 | .mode_valid = intel_crt_mode_valid, | |
745 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 746 | .best_encoder = intel_best_encoder, |
79e53945 JB |
747 | }; |
748 | ||
79e53945 | 749 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 750 | .destroy = intel_encoder_destroy, |
79e53945 JB |
751 | }; |
752 | ||
8ca4013d DL |
753 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
754 | { | |
bc0daf48 | 755 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
756 | return 1; |
757 | } | |
758 | ||
759 | static const struct dmi_system_id intel_no_crt[] = { | |
760 | { | |
761 | .callback = intel_no_crt_dmi_callback, | |
762 | .ident = "ACER ZGB", | |
763 | .matches = { | |
764 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
765 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
766 | }, | |
767 | }, | |
768 | { } | |
769 | }; | |
770 | ||
79e53945 JB |
771 | void intel_crt_init(struct drm_device *dev) |
772 | { | |
773 | struct drm_connector *connector; | |
c9a1c4cd | 774 | struct intel_crt *crt; |
454c1ca8 | 775 | struct intel_connector *intel_connector; |
db545019 | 776 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 777 | |
8ca4013d DL |
778 | /* Skip machines without VGA that falsely report hotplug events */ |
779 | if (dmi_check_system(intel_no_crt)) | |
780 | return; | |
781 | ||
c9a1c4cd CW |
782 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
783 | if (!crt) | |
79e53945 JB |
784 | return; |
785 | ||
b14c5679 | 786 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
454c1ca8 | 787 | if (!intel_connector) { |
c9a1c4cd | 788 | kfree(crt); |
454c1ca8 ZW |
789 | return; |
790 | } | |
791 | ||
792 | connector = &intel_connector->base; | |
637f44d2 | 793 | crt->connector = intel_connector; |
454c1ca8 | 794 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
795 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
796 | ||
c9a1c4cd | 797 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
798 | DRM_MODE_ENCODER_DAC); |
799 | ||
c9a1c4cd | 800 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 801 | |
c9a1c4cd | 802 | crt->base.type = INTEL_OUTPUT_ANALOG; |
66a9278e | 803 | crt->base.cloneable = true; |
d63fa0dc | 804 | if (IS_I830(dev)) |
59c859d6 ED |
805 | crt->base.crtc_mask = (1 << 0); |
806 | else | |
0826874a | 807 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 808 | |
dbb02575 DV |
809 | if (IS_GEN2(dev)) |
810 | connector->interlace_allowed = 0; | |
811 | else | |
812 | connector->interlace_allowed = 1; | |
79e53945 JB |
813 | connector->doublescan_allowed = 0; |
814 | ||
df0323c4 | 815 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
816 | crt->adpa_reg = PCH_ADPA; |
817 | else if (IS_VALLEYVIEW(dev)) | |
818 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 819 | else |
540a8950 DV |
820 | crt->adpa_reg = ADPA; |
821 | ||
5bfe2ac0 | 822 | crt->base.compute_config = intel_crt_compute_config; |
eebe6f0b | 823 | crt->base.mode_set = intel_crt_mode_set; |
2124604b DV |
824 | crt->base.disable = intel_disable_crt; |
825 | crt->base.enable = intel_enable_crt; | |
1d843f9d EE |
826 | if (I915_HAS_HOTPLUG(dev)) |
827 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
828 | if (HAS_DDI(dev)) { |
829 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 830 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
a2985791 VS |
831 | } else { |
832 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 833 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 834 | } |
e403fc94 | 835 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 836 | |
79e53945 JB |
837 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
838 | ||
839 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 840 | |
821450c6 EE |
841 | if (!I915_HAS_HOTPLUG(dev)) |
842 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 843 | |
e7dbb2f2 KP |
844 | /* |
845 | * Configure the automatic hotplug detection stuff | |
846 | */ | |
847 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 848 | |
68d18ad7 | 849 | /* |
3e68320e DL |
850 | * TODO: find a proper way to discover whether we need to set the the |
851 | * polarity and link reversal bits or not, instead of relying on the | |
852 | * BIOS. | |
68d18ad7 | 853 | */ |
3e68320e DL |
854 | if (HAS_PCH_LPT(dev)) { |
855 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
856 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
857 | ||
858 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
859 | } | |
79e53945 | 860 | } |