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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
f0f59a00 | 53 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 70 | struct drm_i915_private *dev_priv = to_i915(dev); |
e403fc94 | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 72 | enum intel_display_power_domain power_domain; |
e403fc94 | 73 | u32 tmp; |
1c8fdda1 | 74 | bool ret; |
e403fc94 | 75 | |
6d129bea | 76 | power_domain = intel_display_port_power_domain(encoder); |
1c8fdda1 | 77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
78 | return false; |
79 | ||
1c8fdda1 ID |
80 | ret = false; |
81 | ||
e403fc94 DV |
82 | tmp = I915_READ(crt->adpa_reg); |
83 | ||
84 | if (!(tmp & ADPA_DAC_ENABLE)) | |
1c8fdda1 | 85 | goto out; |
e403fc94 DV |
86 | |
87 | if (HAS_PCH_CPT(dev)) | |
88 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
89 | else | |
90 | *pipe = PORT_TO_PIPE(tmp); | |
91 | ||
1c8fdda1 ID |
92 | ret = true; |
93 | out: | |
94 | intel_display_power_put(dev_priv, power_domain); | |
95 | ||
96 | return ret; | |
e403fc94 DV |
97 | } |
98 | ||
6801c18c | 99 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 100 | { |
fac5e23e | 101 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
102 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
103 | u32 tmp, flags = 0; | |
104 | ||
105 | tmp = I915_READ(crt->adpa_reg); | |
106 | ||
107 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
108 | flags |= DRM_MODE_FLAG_PHSYNC; | |
109 | else | |
110 | flags |= DRM_MODE_FLAG_NHSYNC; | |
111 | ||
112 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
113 | flags |= DRM_MODE_FLAG_PVSYNC; | |
114 | else | |
115 | flags |= DRM_MODE_FLAG_NVSYNC; | |
116 | ||
6801c18c VS |
117 | return flags; |
118 | } | |
119 | ||
120 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 121 | struct intel_crtc_state *pipe_config) |
6801c18c | 122 | { |
2d112de7 | 123 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 124 | |
e3b247da | 125 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
126 | } |
127 | ||
6801c18c | 128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 129 | struct intel_crtc_state *pipe_config) |
6801c18c | 130 | { |
8802e5b6 VS |
131 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
132 | ||
6801c18c VS |
133 | intel_ddi_get_config(encoder, pipe_config); |
134 | ||
2d112de7 | 135 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
136 | DRM_MODE_FLAG_NHSYNC | |
137 | DRM_MODE_FLAG_PVSYNC | | |
138 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 139 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
8802e5b6 VS |
140 | |
141 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); | |
6801c18c VS |
142 | } |
143 | ||
b2cabb0e DV |
144 | /* Note: The caller is required to filter out dpms modes not supported by the |
145 | * platform. */ | |
225cc348 ML |
146 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
147 | struct intel_crtc_state *crtc_state, | |
148 | int mode) | |
df0323c4 | 149 | { |
b2cabb0e | 150 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 151 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2cabb0e | 152 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225cc348 ML |
153 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
154 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; | |
894ed1ec DV |
155 | u32 adpa; |
156 | ||
157 | if (INTEL_INFO(dev)->gen >= 5) | |
158 | adpa = ADPA_HOTPLUG_BITS; | |
159 | else | |
160 | adpa = 0; | |
df0323c4 | 161 | |
894ed1ec DV |
162 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
163 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
164 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
165 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
166 | ||
167 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
168 | if (HAS_PCH_LPT(dev)) | |
169 | ; /* Those bits don't exist here */ | |
170 | else if (HAS_PCH_CPT(dev)) | |
171 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
172 | else if (crtc->pipe == 0) | |
173 | adpa |= ADPA_PIPE_A_SELECT; | |
174 | else | |
175 | adpa |= ADPA_PIPE_B_SELECT; | |
176 | ||
177 | if (!HAS_PCH_SPLIT(dev)) | |
178 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 179 | |
0206e353 | 180 | switch (mode) { |
79e53945 | 181 | case DRM_MODE_DPMS_ON: |
894ed1ec | 182 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
183 | break; |
184 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 185 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
186 | break; |
187 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 188 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
189 | break; |
190 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 191 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
192 | break; |
193 | } | |
194 | ||
894ed1ec | 195 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 196 | } |
2c07245f | 197 | |
fd6bbda9 ML |
198 | static void intel_disable_crt(struct intel_encoder *encoder, |
199 | struct intel_crtc_state *old_crtc_state, | |
200 | struct drm_connector_state *old_conn_state) | |
637f44d2 | 201 | { |
225cc348 | 202 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
203 | } |
204 | ||
fd6bbda9 ML |
205 | static void pch_disable_crt(struct intel_encoder *encoder, |
206 | struct intel_crtc_state *old_crtc_state, | |
207 | struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
208 | { |
209 | } | |
210 | ||
fd6bbda9 ML |
211 | static void pch_post_disable_crt(struct intel_encoder *encoder, |
212 | struct intel_crtc_state *old_crtc_state, | |
213 | struct drm_connector_state *old_conn_state) | |
1ea56e26 | 214 | { |
fd6bbda9 | 215 | intel_disable_crt(encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 216 | } |
abfdc1e3 | 217 | |
b7076546 ML |
218 | static void hsw_post_disable_crt(struct intel_encoder *encoder, |
219 | struct intel_crtc_state *old_crtc_state, | |
220 | struct drm_connector_state *old_conn_state) | |
221 | { | |
222 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
223 | ||
224 | pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); | |
225 | ||
226 | lpt_disable_pch_transcoder(dev_priv); | |
227 | lpt_disable_iclkip(dev_priv); | |
228 | ||
229 | intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); | |
230 | } | |
231 | ||
fd6bbda9 ML |
232 | static void intel_enable_crt(struct intel_encoder *encoder, |
233 | struct intel_crtc_state *pipe_config, | |
234 | struct drm_connector_state *conn_state) | |
637f44d2 | 235 | { |
225cc348 | 236 | intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
237 | } |
238 | ||
c19de8eb DL |
239 | static enum drm_mode_status |
240 | intel_crt_mode_valid(struct drm_connector *connector, | |
241 | struct drm_display_mode *mode) | |
79e53945 | 242 | { |
6bcdcd9e | 243 | struct drm_device *dev = connector->dev; |
f8700b34 | 244 | int max_dotclk = to_i915(dev)->max_dotclk_freq; |
debded84 | 245 | int max_clock; |
6bcdcd9e | 246 | |
79e53945 JB |
247 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
248 | return MODE_NO_DBLESCAN; | |
249 | ||
6bcdcd9e ZY |
250 | if (mode->clock < 25000) |
251 | return MODE_CLOCK_LOW; | |
252 | ||
debded84 VS |
253 | if (HAS_PCH_LPT(dev)) |
254 | max_clock = 180000; | |
255 | else if (IS_VALLEYVIEW(dev)) | |
256 | /* | |
257 | * 270 MHz due to current DPLL limits, | |
258 | * DAC limit supposedly 355 MHz. | |
259 | */ | |
260 | max_clock = 270000; | |
261 | else if (IS_GEN3(dev) || IS_GEN4(dev)) | |
6bcdcd9e | 262 | max_clock = 400000; |
debded84 VS |
263 | else |
264 | max_clock = 350000; | |
6bcdcd9e ZY |
265 | if (mode->clock > max_clock) |
266 | return MODE_CLOCK_HIGH; | |
79e53945 | 267 | |
f8700b34 MK |
268 | if (mode->clock > max_dotclk) |
269 | return MODE_CLOCK_HIGH; | |
270 | ||
d4b1931c PZ |
271 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
272 | if (HAS_PCH_LPT(dev) && | |
273 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
274 | return MODE_CLOCK_HIGH; | |
275 | ||
79e53945 JB |
276 | return MODE_OK; |
277 | } | |
278 | ||
5bfe2ac0 | 279 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
280 | struct intel_crtc_state *pipe_config, |
281 | struct drm_connector_state *conn_state) | |
79e53945 | 282 | { |
5bfe2ac0 DV |
283 | struct drm_device *dev = encoder->base.dev; |
284 | ||
285 | if (HAS_PCH_SPLIT(dev)) | |
286 | pipe_config->has_pch_encoder = true; | |
287 | ||
2a7aceec | 288 | /* LPT FDI RX only supports 8bpc. */ |
f58a1acc DV |
289 | if (HAS_PCH_LPT(dev)) { |
290 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { | |
291 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | |
292 | return false; | |
293 | } | |
294 | ||
2a7aceec | 295 | pipe_config->pipe_bpp = 24; |
f58a1acc | 296 | } |
2a7aceec | 297 | |
8f7abfd8 | 298 | /* FDI must always be 2.7 GHz */ |
daedf20a | 299 | if (HAS_DDI(dev)) |
8f7abfd8 | 300 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 301 | |
79e53945 JB |
302 | return true; |
303 | } | |
304 | ||
f2b115e6 | 305 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
306 | { |
307 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 308 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 309 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 310 | u32 adpa; |
2c07245f ZW |
311 | bool ret; |
312 | ||
e7dbb2f2 KP |
313 | /* The first time through, trigger an explicit detection cycle */ |
314 | if (crt->force_hotplug_required) { | |
315 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
316 | u32 save_adpa; | |
67941da2 | 317 | |
e7dbb2f2 KP |
318 | crt->force_hotplug_required = 0; |
319 | ||
ca54b810 | 320 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
321 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
322 | ||
323 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
324 | if (turn_off_dac) | |
325 | adpa &= ~ADPA_DAC_ENABLE; | |
326 | ||
ca54b810 | 327 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 328 | |
e1672d1c CW |
329 | if (intel_wait_for_register(dev_priv, |
330 | crt->adpa_reg, | |
331 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
332 | 1000)) | |
e7dbb2f2 KP |
333 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
334 | ||
335 | if (turn_off_dac) { | |
ca54b810 VS |
336 | I915_WRITE(crt->adpa_reg, save_adpa); |
337 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 338 | } |
a4a6b901 ZW |
339 | } |
340 | ||
2c07245f | 341 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 342 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 343 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
344 | ret = true; |
345 | else | |
346 | ret = false; | |
e7dbb2f2 | 347 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 348 | |
2c07245f | 349 | return ret; |
79e53945 JB |
350 | } |
351 | ||
7d2c24e8 JB |
352 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
353 | { | |
354 | struct drm_device *dev = connector->dev; | |
ca54b810 | 355 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 356 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 357 | bool reenable_hpd; |
7d2c24e8 JB |
358 | u32 adpa; |
359 | bool ret; | |
360 | u32 save_adpa; | |
361 | ||
b236d7c8 L |
362 | /* |
363 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
364 | * get us stuck in a loop if we're polling: | |
365 | * - We enable power wells and reset the ADPA | |
366 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
367 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
368 | * - output_poll_exec shuts off the ADPA, unlocks | |
369 | * dev->mode_config.mutex | |
370 | * - HPD handler runs, resets ADPA and brings us back to the start | |
371 | * | |
372 | * Just disable HPD interrupts here to prevent this | |
373 | */ | |
374 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
375 | ||
ca54b810 | 376 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
377 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
378 | ||
379 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
380 | ||
ca54b810 | 381 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 382 | |
a522ae4b CW |
383 | if (intel_wait_for_register(dev_priv, |
384 | crt->adpa_reg, | |
385 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
386 | 1000)) { | |
7d2c24e8 | 387 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
ca54b810 | 388 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
389 | } |
390 | ||
391 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 392 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
393 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
394 | ret = true; | |
395 | else | |
396 | ret = false; | |
397 | ||
398 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
399 | ||
b236d7c8 L |
400 | if (reenable_hpd) |
401 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
402 | ||
7d2c24e8 JB |
403 | return ret; |
404 | } | |
405 | ||
79e53945 JB |
406 | /** |
407 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
408 | * | |
409 | * Not for i915G/i915GM | |
410 | * | |
411 | * \return true if CRT is connected. | |
412 | * \return false if CRT is disconnected. | |
413 | */ | |
414 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
415 | { | |
416 | struct drm_device *dev = connector->dev; | |
fac5e23e | 417 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 418 | u32 stat; |
7a772c49 | 419 | bool ret = false; |
771cb081 | 420 | int i, tries = 0; |
2c07245f | 421 | |
bad720ff | 422 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 423 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 424 | |
7d2c24e8 JB |
425 | if (IS_VALLEYVIEW(dev)) |
426 | return valleyview_crt_detect_hotplug(connector); | |
427 | ||
771cb081 ZY |
428 | /* |
429 | * On 4 series desktop, CRT detect sequence need to be done twice | |
430 | * to get a reliable result. | |
431 | */ | |
79e53945 | 432 | |
771cb081 ZY |
433 | if (IS_G4X(dev) && !IS_GM45(dev)) |
434 | tries = 2; | |
435 | else | |
436 | tries = 1; | |
771cb081 | 437 | |
771cb081 | 438 | for (i = 0; i < tries ; i++) { |
771cb081 | 439 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
440 | i915_hotplug_interrupt_update(dev_priv, |
441 | CRT_HOTPLUG_FORCE_DETECT, | |
442 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 443 | /* wait for FORCE_DETECT to go off */ |
fd3790d4 CW |
444 | if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, |
445 | CRT_HOTPLUG_FORCE_DETECT, 0, | |
446 | 1000)) | |
79077319 | 447 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 448 | } |
79e53945 | 449 | |
7a772c49 AJ |
450 | stat = I915_READ(PORT_HOTPLUG_STAT); |
451 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
452 | ret = true; | |
453 | ||
454 | /* clear the interrupt we just generated, if any */ | |
455 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 456 | |
0706f17c | 457 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
458 | |
459 | return ret; | |
79e53945 JB |
460 | } |
461 | ||
f1a2f5b7 JN |
462 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
463 | struct i2c_adapter *i2c) | |
464 | { | |
465 | struct edid *edid; | |
466 | ||
467 | edid = drm_get_edid(connector, i2c); | |
468 | ||
469 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
470 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
471 | intel_gmbus_force_bit(i2c, true); | |
472 | edid = drm_get_edid(connector, i2c); | |
473 | intel_gmbus_force_bit(i2c, false); | |
474 | } | |
475 | ||
476 | return edid; | |
477 | } | |
478 | ||
479 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
480 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
481 | struct i2c_adapter *adapter) | |
482 | { | |
483 | struct edid *edid; | |
ebda95a9 | 484 | int ret; |
f1a2f5b7 JN |
485 | |
486 | edid = intel_crt_get_edid(connector, adapter); | |
487 | if (!edid) | |
488 | return 0; | |
489 | ||
ebda95a9 JN |
490 | ret = intel_connector_update_modes(connector, edid); |
491 | kfree(edid); | |
492 | ||
493 | return ret; | |
f1a2f5b7 JN |
494 | } |
495 | ||
f5afcd3d | 496 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 497 | { |
f5afcd3d | 498 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 499 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
a2bd1f54 DV |
500 | struct edid *edid; |
501 | struct i2c_adapter *i2c; | |
79e53945 | 502 | |
a2bd1f54 | 503 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 504 | |
41aa3448 | 505 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 506 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
507 | |
508 | if (edid) { | |
509 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 510 | |
f5afcd3d DM |
511 | /* |
512 | * This may be a DVI-I connector with a shared DDC | |
513 | * link between analog and digital outputs, so we | |
514 | * have to check the EDID input spec of the attached device. | |
515 | */ | |
f5afcd3d DM |
516 | if (!is_digital) { |
517 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
518 | return true; | |
519 | } | |
a2bd1f54 DV |
520 | |
521 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
522 | } else { | |
523 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
524 | } |
525 | ||
a2bd1f54 DV |
526 | kfree(edid); |
527 | ||
6ec3d0c0 | 528 | return false; |
79e53945 JB |
529 | } |
530 | ||
e4a5d54f | 531 | static enum drm_connector_status |
c8ecb2f1 | 532 | intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) |
e4a5d54f | 533 | { |
7173188d | 534 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 535 | struct drm_i915_private *dev_priv = to_i915(dev); |
e4a5d54f ML |
536 | uint32_t save_bclrpat; |
537 | uint32_t save_vtotal; | |
538 | uint32_t vtotal, vactive; | |
539 | uint32_t vsample; | |
540 | uint32_t vblank, vblank_start, vblank_end; | |
541 | uint32_t dsl; | |
f0f59a00 VS |
542 | i915_reg_t bclrpat_reg, vtotal_reg, |
543 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
e4a5d54f ML |
544 | uint8_t st00; |
545 | enum drm_connector_status status; | |
546 | ||
6ec3d0c0 CW |
547 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
548 | ||
9db4a9c7 JB |
549 | bclrpat_reg = BCLRPAT(pipe); |
550 | vtotal_reg = VTOTAL(pipe); | |
551 | vblank_reg = VBLANK(pipe); | |
552 | vsync_reg = VSYNC(pipe); | |
553 | pipeconf_reg = PIPECONF(pipe); | |
554 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
555 | |
556 | save_bclrpat = I915_READ(bclrpat_reg); | |
557 | save_vtotal = I915_READ(vtotal_reg); | |
558 | vblank = I915_READ(vblank_reg); | |
559 | ||
560 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
561 | vactive = (save_vtotal & 0x7ff) + 1; | |
562 | ||
563 | vblank_start = (vblank & 0xfff) + 1; | |
564 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
565 | ||
566 | /* Set the border color to purple. */ | |
567 | I915_WRITE(bclrpat_reg, 0x500050); | |
568 | ||
a6c45cf0 | 569 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
570 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
571 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 572 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
573 | /* Wait for next Vblank to substitue |
574 | * border color for Color info */ | |
9d0498a2 | 575 | intel_wait_for_vblank(dev, pipe); |
f0f59a00 | 576 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
577 | status = ((st00 & (1 << 4)) != 0) ? |
578 | connector_status_connected : | |
579 | connector_status_disconnected; | |
580 | ||
581 | I915_WRITE(pipeconf_reg, pipeconf); | |
582 | } else { | |
583 | bool restore_vblank = false; | |
584 | int count, detect; | |
585 | ||
586 | /* | |
587 | * If there isn't any border, add some. | |
588 | * Yes, this will flicker | |
589 | */ | |
590 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
591 | uint32_t vsync = I915_READ(vsync_reg); | |
592 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
593 | ||
594 | vblank_start = vsync_start; | |
595 | I915_WRITE(vblank_reg, | |
596 | (vblank_start - 1) | | |
597 | ((vblank_end - 1) << 16)); | |
598 | restore_vblank = true; | |
599 | } | |
600 | /* sample in the vertical border, selecting the larger one */ | |
601 | if (vblank_start - vactive >= vtotal - vblank_end) | |
602 | vsample = (vblank_start + vactive) >> 1; | |
603 | else | |
604 | vsample = (vtotal + vblank_end) >> 1; | |
605 | ||
606 | /* | |
607 | * Wait for the border to be displayed | |
608 | */ | |
609 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
610 | ; | |
611 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
612 | ; | |
613 | /* | |
614 | * Watch ST00 for an entire scanline | |
615 | */ | |
616 | detect = 0; | |
617 | count = 0; | |
618 | do { | |
619 | count++; | |
620 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 621 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
622 | if (st00 & (1 << 4)) |
623 | detect++; | |
624 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
625 | ||
626 | /* restore vblank if necessary */ | |
627 | if (restore_vblank) | |
628 | I915_WRITE(vblank_reg, vblank); | |
629 | /* | |
630 | * If more than 3/4 of the scanline detected a monitor, | |
631 | * then it is assumed to be present. This works even on i830, | |
632 | * where there isn't any way to force the border color across | |
633 | * the screen | |
634 | */ | |
635 | status = detect * 4 > count * 3 ? | |
636 | connector_status_connected : | |
637 | connector_status_disconnected; | |
638 | } | |
639 | ||
640 | /* Restore previous settings */ | |
641 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
642 | ||
643 | return status; | |
644 | } | |
645 | ||
7b334fcb | 646 | static enum drm_connector_status |
930a9e28 | 647 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
648 | { |
649 | struct drm_device *dev = connector->dev; | |
fac5e23e | 650 | struct drm_i915_private *dev_priv = to_i915(dev); |
c9a1c4cd | 651 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
652 | struct intel_encoder *intel_encoder = &crt->base; |
653 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 654 | enum drm_connector_status status; |
e95c8438 | 655 | struct intel_load_detect_pipe tmp; |
51fd371b | 656 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 657 | |
164c8598 | 658 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 659 | connector->base.id, connector->name, |
164c8598 CW |
660 | force); |
661 | ||
671dedd2 ID |
662 | power_domain = intel_display_port_power_domain(intel_encoder); |
663 | intel_display_power_get(dev_priv, power_domain); | |
664 | ||
a6c45cf0 | 665 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
666 | /* We can not rely on the HPD pin always being correctly wired |
667 | * up, for example many KVM do not pass it through, and so | |
668 | * only trust an assertion that the monitor is connected. | |
669 | */ | |
6ec3d0c0 CW |
670 | if (intel_crt_detect_hotplug(connector)) { |
671 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
672 | status = connector_status_connected; |
673 | goto out; | |
aaa37730 | 674 | } else |
e7dbb2f2 | 675 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
676 | } |
677 | ||
c19a0df2 PZ |
678 | if (intel_crt_detect_ddc(connector)) { |
679 | status = connector_status_connected; | |
680 | goto out; | |
681 | } | |
79e53945 | 682 | |
aaa37730 DV |
683 | /* Load detection is broken on HPD capable machines. Whoever wants a |
684 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
685 | * to have the right resistors for HP detection) needs to fix this up. | |
686 | * For now just bail out. */ | |
5bedeb2d | 687 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
c19a0df2 PZ |
688 | status = connector_status_disconnected; |
689 | goto out; | |
690 | } | |
aaa37730 | 691 | |
c19a0df2 PZ |
692 | if (!force) { |
693 | status = connector->status; | |
694 | goto out; | |
695 | } | |
7b334fcb | 696 | |
208bf9fd VS |
697 | drm_modeset_acquire_init(&ctx, 0); |
698 | ||
e4a5d54f | 699 | /* for pre-945g platforms use load detect */ |
51fd371b | 700 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
701 | if (intel_crt_detect_ddc(connector)) |
702 | status = connector_status_connected; | |
5bedeb2d | 703 | else if (INTEL_INFO(dev)->gen < 4) |
c8ecb2f1 ML |
704 | status = intel_crt_load_detect(crt, |
705 | to_intel_crtc(connector->state->crtc)->pipe); | |
32fff610 ML |
706 | else if (i915.load_detect_test) |
707 | status = connector_status_disconnected; | |
5bedeb2d DV |
708 | else |
709 | status = connector_status_unknown; | |
49172fee | 710 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
e95c8438 DV |
711 | } else |
712 | status = connector_status_unknown; | |
e4a5d54f | 713 | |
208bf9fd VS |
714 | drm_modeset_drop_locks(&ctx); |
715 | drm_modeset_acquire_fini(&ctx); | |
716 | ||
c19a0df2 | 717 | out: |
671dedd2 | 718 | intel_display_power_put(dev_priv, power_domain); |
e4a5d54f | 719 | return status; |
79e53945 JB |
720 | } |
721 | ||
722 | static void intel_crt_destroy(struct drm_connector *connector) | |
723 | { | |
79e53945 JB |
724 | drm_connector_cleanup(connector); |
725 | kfree(connector); | |
726 | } | |
727 | ||
728 | static int intel_crt_get_modes(struct drm_connector *connector) | |
729 | { | |
8e4d36b9 | 730 | struct drm_device *dev = connector->dev; |
fac5e23e | 731 | struct drm_i915_private *dev_priv = to_i915(dev); |
671dedd2 ID |
732 | struct intel_crt *crt = intel_attached_crt(connector); |
733 | struct intel_encoder *intel_encoder = &crt->base; | |
734 | enum intel_display_power_domain power_domain; | |
890f3359 | 735 | int ret; |
3bd7d909 | 736 | struct i2c_adapter *i2c; |
8e4d36b9 | 737 | |
671dedd2 ID |
738 | power_domain = intel_display_port_power_domain(intel_encoder); |
739 | intel_display_power_get(dev_priv, power_domain); | |
740 | ||
41aa3448 | 741 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 742 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 743 | if (ret || !IS_G4X(dev)) |
671dedd2 | 744 | goto out; |
8e4d36b9 | 745 | |
8e4d36b9 | 746 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 747 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
748 | ret = intel_crt_ddc_get_modes(connector, i2c); |
749 | ||
750 | out: | |
751 | intel_display_power_put(dev_priv, power_domain); | |
752 | ||
753 | return ret; | |
79e53945 JB |
754 | } |
755 | ||
756 | static int intel_crt_set_property(struct drm_connector *connector, | |
757 | struct drm_property *property, | |
758 | uint64_t value) | |
759 | { | |
79e53945 JB |
760 | return 0; |
761 | } | |
762 | ||
9504a892 | 763 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 764 | { |
28cf71ce | 765 | struct drm_device *dev = encoder->dev; |
fac5e23e | 766 | struct drm_i915_private *dev_priv = to_i915(dev); |
28cf71ce | 767 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 768 | |
10603caa | 769 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
770 | u32 adpa; |
771 | ||
ca54b810 | 772 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
773 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
774 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
775 | I915_WRITE(crt->adpa_reg, adpa); |
776 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 777 | |
0039a4b3 | 778 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 779 | crt->force_hotplug_required = 1; |
2e938892 DV |
780 | } |
781 | ||
f3269058 CW |
782 | } |
783 | ||
79e53945 JB |
784 | /* |
785 | * Routines for controlling stuff on the analog port | |
786 | */ | |
787 | ||
79e53945 | 788 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
4d688a2a | 789 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
790 | .detect = intel_crt_detect, |
791 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1ebaa0b9 | 792 | .late_register = intel_connector_register, |
c191eca1 | 793 | .early_unregister = intel_connector_unregister, |
79e53945 JB |
794 | .destroy = intel_crt_destroy, |
795 | .set_property = intel_crt_set_property, | |
c6f95f27 | 796 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 797 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2545e4a6 | 798 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 JB |
799 | }; |
800 | ||
801 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
802 | .mode_valid = intel_crt_mode_valid, | |
803 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
804 | }; |
805 | ||
79e53945 | 806 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 807 | .reset = intel_crt_reset, |
ea5b213a | 808 | .destroy = intel_encoder_destroy, |
79e53945 JB |
809 | }; |
810 | ||
bbe1c274 | 811 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
8ca4013d | 812 | { |
bc0daf48 | 813 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
814 | return 1; |
815 | } | |
816 | ||
817 | static const struct dmi_system_id intel_no_crt[] = { | |
818 | { | |
819 | .callback = intel_no_crt_dmi_callback, | |
820 | .ident = "ACER ZGB", | |
821 | .matches = { | |
822 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
823 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
824 | }, | |
825 | }, | |
10b6ee4a GC |
826 | { |
827 | .callback = intel_no_crt_dmi_callback, | |
828 | .ident = "DELL XPS 8700", | |
829 | .matches = { | |
830 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
831 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
832 | }, | |
833 | }, | |
8ca4013d DL |
834 | { } |
835 | }; | |
836 | ||
79e53945 JB |
837 | void intel_crt_init(struct drm_device *dev) |
838 | { | |
839 | struct drm_connector *connector; | |
c9a1c4cd | 840 | struct intel_crt *crt; |
454c1ca8 | 841 | struct intel_connector *intel_connector; |
fac5e23e | 842 | struct drm_i915_private *dev_priv = to_i915(dev); |
6c03a6bd VS |
843 | i915_reg_t adpa_reg; |
844 | u32 adpa; | |
79e53945 | 845 | |
8ca4013d DL |
846 | /* Skip machines without VGA that falsely report hotplug events */ |
847 | if (dmi_check_system(intel_no_crt)) | |
848 | return; | |
849 | ||
6c03a6bd VS |
850 | if (HAS_PCH_SPLIT(dev)) |
851 | adpa_reg = PCH_ADPA; | |
852 | else if (IS_VALLEYVIEW(dev)) | |
853 | adpa_reg = VLV_ADPA; | |
854 | else | |
855 | adpa_reg = ADPA; | |
856 | ||
857 | adpa = I915_READ(adpa_reg); | |
858 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
859 | /* | |
860 | * On some machines (some IVB at least) CRT can be | |
861 | * fused off, but there's no known fuse bit to | |
862 | * indicate that. On these machine the ADPA register | |
863 | * works normally, except the DAC enable bit won't | |
864 | * take. So the only way to tell is attempt to enable | |
865 | * it and see what happens. | |
866 | */ | |
867 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
868 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
869 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
870 | return; | |
871 | I915_WRITE(adpa_reg, adpa); | |
872 | } | |
873 | ||
c9a1c4cd CW |
874 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
875 | if (!crt) | |
79e53945 JB |
876 | return; |
877 | ||
9bdbd0b9 | 878 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 879 | if (!intel_connector) { |
c9a1c4cd | 880 | kfree(crt); |
454c1ca8 ZW |
881 | return; |
882 | } | |
883 | ||
884 | connector = &intel_connector->base; | |
637f44d2 | 885 | crt->connector = intel_connector; |
454c1ca8 | 886 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
887 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
888 | ||
c9a1c4cd | 889 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 890 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 891 | |
c9a1c4cd | 892 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 893 | |
c9a1c4cd | 894 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 895 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 896 | if (IS_I830(dev)) |
59c859d6 ED |
897 | crt->base.crtc_mask = (1 << 0); |
898 | else | |
0826874a | 899 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 900 | |
dbb02575 DV |
901 | if (IS_GEN2(dev)) |
902 | connector->interlace_allowed = 0; | |
903 | else | |
904 | connector->interlace_allowed = 1; | |
79e53945 JB |
905 | connector->doublescan_allowed = 0; |
906 | ||
6c03a6bd | 907 | crt->adpa_reg = adpa_reg; |
540a8950 | 908 | |
5bfe2ac0 | 909 | crt->base.compute_config = intel_crt_compute_config; |
92966a37 | 910 | if (HAS_PCH_SPLIT(dev)) { |
1ea56e26 VS |
911 | crt->base.disable = pch_disable_crt; |
912 | crt->base.post_disable = pch_post_disable_crt; | |
913 | } else { | |
914 | crt->base.disable = intel_disable_crt; | |
915 | } | |
2124604b | 916 | crt->base.enable = intel_enable_crt; |
1d843f9d EE |
917 | if (I915_HAS_HOTPLUG(dev)) |
918 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
919 | if (HAS_DDI(dev)) { |
920 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 921 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
b7076546 | 922 | crt->base.post_disable = hsw_post_disable_crt; |
a2985791 VS |
923 | } else { |
924 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 925 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 926 | } |
e403fc94 | 927 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 928 | |
79e53945 JB |
929 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
930 | ||
821450c6 EE |
931 | if (!I915_HAS_HOTPLUG(dev)) |
932 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 933 | |
e7dbb2f2 KP |
934 | /* |
935 | * Configure the automatic hotplug detection stuff | |
936 | */ | |
937 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 938 | |
68d18ad7 | 939 | /* |
3e68320e DL |
940 | * TODO: find a proper way to discover whether we need to set the the |
941 | * polarity and link reversal bits or not, instead of relying on the | |
942 | * BIOS. | |
68d18ad7 | 943 | */ |
3e68320e DL |
944 | if (HAS_PCH_LPT(dev)) { |
945 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
946 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
947 | ||
eede3b53 | 948 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 949 | } |
754970ee | 950 | |
28cf71ce | 951 | intel_crt_reset(&crt->base.base); |
79e53945 | 952 | } |