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eb805623 DV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include "i915_drv.h" | |
26 | #include "i915_reg.h" | |
27 | ||
aa9145c4 AM |
28 | /** |
29 | * DOC: csr support for dmc | |
30 | * | |
31 | * Display Context Save and Restore (CSR) firmware support added from gen9 | |
32 | * onwards to drive newly added DMC (Display microcontroller) in display | |
33 | * engine to save and restore the state of display engine when it enter into | |
34 | * low-power state and comes back to normal. | |
35 | * | |
36 | * Firmware loading status will be one of the below states: FW_UNINITIALIZED, | |
37 | * FW_LOADED, FW_FAILED. | |
38 | * | |
39 | * Once the firmware is written into the registers status will be moved from | |
40 | * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will | |
41 | * be moved to FW_FAILED. | |
42 | */ | |
43 | ||
4aa7fb9c | 44 | #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" |
4922d491 RV |
45 | MODULE_FIRMWARE(I915_CSR_KBL); |
46 | #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) | |
47 | ||
4aa7fb9c | 48 | #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" |
4922d491 | 49 | MODULE_FIRMWARE(I915_CSR_SKL); |
4aa7fb9c | 50 | #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) |
4922d491 | 51 | |
4aa7fb9c | 52 | #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" |
4922d491 RV |
53 | MODULE_FIRMWARE(I915_CSR_BXT); |
54 | #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) | |
eb805623 | 55 | |
cbfc2d26 CW |
56 | #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares" |
57 | ||
eb805623 | 58 | |
4922d491 | 59 | |
9c5308ea | 60 | |
eb805623 DV |
61 | #define CSR_MAX_FW_SIZE 0x2FFF |
62 | #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF | |
eb805623 DV |
63 | |
64 | struct intel_css_header { | |
65 | /* 0x09 for DMC */ | |
66 | uint32_t module_type; | |
67 | ||
68 | /* Includes the DMC specific header in dwords */ | |
69 | uint32_t header_len; | |
70 | ||
71 | /* always value would be 0x10000 */ | |
72 | uint32_t header_ver; | |
73 | ||
74 | /* Not used */ | |
75 | uint32_t module_id; | |
76 | ||
77 | /* Not used */ | |
78 | uint32_t module_vendor; | |
79 | ||
80 | /* in YYYYMMDD format */ | |
81 | uint32_t date; | |
82 | ||
83 | /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ | |
84 | uint32_t size; | |
85 | ||
86 | /* Not used */ | |
87 | uint32_t key_size; | |
88 | ||
89 | /* Not used */ | |
90 | uint32_t modulus_size; | |
91 | ||
92 | /* Not used */ | |
93 | uint32_t exponent_size; | |
94 | ||
95 | /* Not used */ | |
96 | uint32_t reserved1[12]; | |
97 | ||
98 | /* Major Minor */ | |
99 | uint32_t version; | |
100 | ||
101 | /* Not used */ | |
102 | uint32_t reserved2[8]; | |
103 | ||
104 | /* Not used */ | |
105 | uint32_t kernel_header_info; | |
106 | } __packed; | |
107 | ||
108 | struct intel_fw_info { | |
109 | uint16_t reserved1; | |
110 | ||
111 | /* Stepping (A, B, C, ..., *). * is a wildcard */ | |
112 | char stepping; | |
113 | ||
114 | /* Sub-stepping (0, 1, ..., *). * is a wildcard */ | |
115 | char substepping; | |
116 | ||
117 | uint32_t offset; | |
118 | uint32_t reserved2; | |
119 | } __packed; | |
120 | ||
121 | struct intel_package_header { | |
122 | /* DMC container header length in dwords */ | |
123 | unsigned char header_len; | |
124 | ||
125 | /* always value would be 0x01 */ | |
126 | unsigned char header_ver; | |
127 | ||
128 | unsigned char reserved[10]; | |
129 | ||
130 | /* Number of valid entries in the FWInfo array below */ | |
131 | uint32_t num_entries; | |
132 | ||
133 | struct intel_fw_info fw_info[20]; | |
134 | } __packed; | |
135 | ||
136 | struct intel_dmc_header { | |
137 | /* always value would be 0x40403E3E */ | |
138 | uint32_t signature; | |
139 | ||
140 | /* DMC binary header length */ | |
141 | unsigned char header_len; | |
142 | ||
143 | /* 0x01 */ | |
144 | unsigned char header_ver; | |
145 | ||
146 | /* Reserved */ | |
147 | uint16_t dmcc_ver; | |
148 | ||
149 | /* Major, Minor */ | |
150 | uint32_t project; | |
151 | ||
152 | /* Firmware program size (excluding header) in dwords */ | |
153 | uint32_t fw_size; | |
154 | ||
155 | /* Major Minor version */ | |
156 | uint32_t fw_version; | |
157 | ||
158 | /* Number of valid MMIO cycles present. */ | |
159 | uint32_t mmio_count; | |
160 | ||
161 | /* MMIO address */ | |
162 | uint32_t mmioaddr[8]; | |
163 | ||
164 | /* MMIO data */ | |
165 | uint32_t mmiodata[8]; | |
166 | ||
167 | /* FW filename */ | |
168 | unsigned char dfile[32]; | |
169 | ||
170 | uint32_t reserved1[2]; | |
171 | } __packed; | |
172 | ||
173 | struct stepping_info { | |
174 | char stepping; | |
175 | char substepping; | |
176 | }; | |
177 | ||
a25c9f00 | 178 | static const struct stepping_info kbl_stepping_info[] = { |
4922d491 RV |
179 | {'A', '0'}, {'B', '0'}, {'C', '0'}, |
180 | {'D', '0'}, {'E', '0'}, {'F', '0'}, | |
181 | {'G', '0'}, {'H', '0'}, {'I', '0'}, | |
a25c9f00 RV |
182 | }; |
183 | ||
eb805623 | 184 | static const struct stepping_info skl_stepping_info[] = { |
84cb00ec JN |
185 | {'A', '0'}, {'B', '0'}, {'C', '0'}, |
186 | {'D', '0'}, {'E', '0'}, {'F', '0'}, | |
a41c8882 MM |
187 | {'G', '0'}, {'H', '0'}, {'I', '0'}, |
188 | {'J', '0'}, {'K', '0'} | |
eb805623 DV |
189 | }; |
190 | ||
b9cd5bfd | 191 | static const struct stepping_info bxt_stepping_info[] = { |
cff765fb AM |
192 | {'A', '0'}, {'A', '1'}, {'A', '2'}, |
193 | {'B', '0'}, {'B', '1'}, {'B', '2'} | |
194 | }; | |
195 | ||
1bb4308e CW |
196 | static const struct stepping_info no_stepping_info = { '*', '*' }; |
197 | ||
198 | static const struct stepping_info * | |
199 | intel_get_stepping_info(struct drm_i915_private *dev_priv) | |
eb805623 | 200 | { |
b1a14c6e JN |
201 | const struct stepping_info *si; |
202 | unsigned int size; | |
203 | ||
1bb4308e | 204 | if (IS_KABYLAKE(dev_priv)) { |
a25c9f00 RV |
205 | size = ARRAY_SIZE(kbl_stepping_info); |
206 | si = kbl_stepping_info; | |
1bb4308e | 207 | } else if (IS_SKYLAKE(dev_priv)) { |
b1a14c6e JN |
208 | size = ARRAY_SIZE(skl_stepping_info); |
209 | si = skl_stepping_info; | |
1bb4308e | 210 | } else if (IS_BROXTON(dev_priv)) { |
b1a14c6e JN |
211 | size = ARRAY_SIZE(bxt_stepping_info); |
212 | si = bxt_stepping_info; | |
213 | } else { | |
1bb4308e | 214 | size = 0; |
b1a14c6e | 215 | } |
eb805623 | 216 | |
1bb4308e CW |
217 | if (INTEL_REVID(dev_priv) < size) |
218 | return si + INTEL_REVID(dev_priv); | |
b1a14c6e | 219 | |
1bb4308e | 220 | return &no_stepping_info; |
eb805623 DV |
221 | } |
222 | ||
2abc525b ID |
223 | static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) |
224 | { | |
225 | uint32_t val, mask; | |
226 | ||
227 | mask = DC_STATE_DEBUG_MASK_MEMORY_UP; | |
228 | ||
229 | if (IS_BROXTON(dev_priv)) | |
230 | mask |= DC_STATE_DEBUG_MASK_CORES; | |
231 | ||
232 | /* The below bit doesn't need to be cleared ever afterwards */ | |
233 | val = I915_READ(DC_STATE_DEBUG); | |
234 | if ((val & mask) != mask) { | |
235 | val |= mask; | |
236 | I915_WRITE(DC_STATE_DEBUG, val); | |
237 | POSTING_READ(DC_STATE_DEBUG); | |
238 | } | |
239 | } | |
240 | ||
aa9145c4 AM |
241 | /** |
242 | * intel_csr_load_program() - write the firmware from memory to register. | |
f4448375 | 243 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
244 | * |
245 | * CSR firmware is read from a .bin file and kept in internal memory one time. | |
246 | * Everytime display comes back from low power state this function is called to | |
247 | * copy the firmware from internal memory to registers. | |
248 | */ | |
2abc525b | 249 | void intel_csr_load_program(struct drm_i915_private *dev_priv) |
eb805623 | 250 | { |
a7f749f9 | 251 | u32 *payload = dev_priv->csr.dmc_payload; |
eb805623 DV |
252 | uint32_t i, fw_size; |
253 | ||
f4448375 | 254 | if (!IS_GEN9(dev_priv)) { |
eb805623 | 255 | DRM_ERROR("No CSR support available for this platform\n"); |
2abc525b | 256 | return; |
eb805623 DV |
257 | } |
258 | ||
fc131bf2 PJ |
259 | if (!dev_priv->csr.dmc_payload) { |
260 | DRM_ERROR("Tried to program CSR with empty payload\n"); | |
2abc525b | 261 | return; |
fc131bf2 | 262 | } |
4b7ab5fc | 263 | |
eb805623 DV |
264 | fw_size = dev_priv->csr.dmc_fw_size; |
265 | for (i = 0; i < fw_size; i++) | |
d2aa5ae8 | 266 | I915_WRITE(CSR_PROGRAM(i), payload[i]); |
eb805623 DV |
267 | |
268 | for (i = 0; i < dev_priv->csr.mmio_count; i++) { | |
269 | I915_WRITE(dev_priv->csr.mmioaddr[i], | |
f98f70d9 | 270 | dev_priv->csr.mmiodata[i]); |
eb805623 | 271 | } |
832dba88 PJ |
272 | |
273 | dev_priv->csr.dc_state = 0; | |
1e657ad7 | 274 | |
2abc525b | 275 | gen9_set_dc_state_debugmask(dev_priv); |
eb805623 DV |
276 | } |
277 | ||
6a6582bf DV |
278 | static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, |
279 | const struct firmware *fw) | |
eb805623 | 280 | { |
eb805623 DV |
281 | struct intel_css_header *css_header; |
282 | struct intel_package_header *package_header; | |
283 | struct intel_dmc_header *dmc_header; | |
284 | struct intel_csr *csr = &dev_priv->csr; | |
1bb4308e | 285 | const struct stepping_info *si = intel_get_stepping_info(dev_priv); |
eb805623 DV |
286 | uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; |
287 | uint32_t i; | |
a7f749f9 | 288 | uint32_t *dmc_payload; |
4aa7fb9c | 289 | uint32_t required_version; |
eb805623 | 290 | |
9c5308ea | 291 | if (!fw) |
6a6582bf | 292 | return NULL; |
eb805623 | 293 | |
eb805623 DV |
294 | /* Extract CSS Header information*/ |
295 | css_header = (struct intel_css_header *)fw->data; | |
296 | if (sizeof(struct intel_css_header) != | |
f98f70d9 | 297 | (css_header->header_len * 4)) { |
eb805623 | 298 | DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", |
f98f70d9 | 299 | (css_header->header_len * 4)); |
6a6582bf | 300 | return NULL; |
eb805623 | 301 | } |
b6e7d894 DL |
302 | |
303 | csr->version = css_header->version; | |
304 | ||
4922d491 | 305 | if (IS_KABYLAKE(dev_priv)) { |
4aa7fb9c | 306 | required_version = KBL_CSR_VERSION_REQUIRED; |
4922d491 | 307 | } else if (IS_SKYLAKE(dev_priv)) { |
4aa7fb9c | 308 | required_version = SKL_CSR_VERSION_REQUIRED; |
e7968531 | 309 | } else if (IS_BROXTON(dev_priv)) { |
4aa7fb9c | 310 | required_version = BXT_CSR_VERSION_REQUIRED; |
e7968531 ID |
311 | } else { |
312 | MISSING_CASE(INTEL_REVID(dev_priv)); | |
4aa7fb9c | 313 | required_version = 0; |
e7968531 ID |
314 | } |
315 | ||
4aa7fb9c PJ |
316 | if (csr->version != required_version) { |
317 | DRM_INFO("Refusing to load DMC firmware v%u.%u," | |
318 | " please use v%u.%u [" FIRMWARE_URL "].\n", | |
9c5308ea MK |
319 | CSR_VERSION_MAJOR(csr->version), |
320 | CSR_VERSION_MINOR(csr->version), | |
4aa7fb9c PJ |
321 | CSR_VERSION_MAJOR(required_version), |
322 | CSR_VERSION_MINOR(required_version)); | |
6a6582bf | 323 | return NULL; |
9c5308ea MK |
324 | } |
325 | ||
eb805623 DV |
326 | readcount += sizeof(struct intel_css_header); |
327 | ||
328 | /* Extract Package Header information*/ | |
329 | package_header = (struct intel_package_header *) | |
f98f70d9 | 330 | &fw->data[readcount]; |
eb805623 | 331 | if (sizeof(struct intel_package_header) != |
f98f70d9 | 332 | (package_header->header_len * 4)) { |
eb805623 | 333 | DRM_ERROR("Firmware has wrong package header length %u bytes\n", |
f98f70d9 | 334 | (package_header->header_len * 4)); |
6a6582bf | 335 | return NULL; |
eb805623 DV |
336 | } |
337 | readcount += sizeof(struct intel_package_header); | |
338 | ||
339 | /* Search for dmc_offset to find firware binary. */ | |
340 | for (i = 0; i < package_header->num_entries; i++) { | |
341 | if (package_header->fw_info[i].substepping == '*' && | |
1bb4308e | 342 | si->stepping == package_header->fw_info[i].stepping) { |
eb805623 DV |
343 | dmc_offset = package_header->fw_info[i].offset; |
344 | break; | |
1bb4308e CW |
345 | } else if (si->stepping == package_header->fw_info[i].stepping && |
346 | si->substepping == package_header->fw_info[i].substepping) { | |
eb805623 DV |
347 | dmc_offset = package_header->fw_info[i].offset; |
348 | break; | |
349 | } else if (package_header->fw_info[i].stepping == '*' && | |
f98f70d9 | 350 | package_header->fw_info[i].substepping == '*') |
eb805623 DV |
351 | dmc_offset = package_header->fw_info[i].offset; |
352 | } | |
353 | if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { | |
1bb4308e CW |
354 | DRM_ERROR("Firmware not supported for %c stepping\n", |
355 | si->stepping); | |
6a6582bf | 356 | return NULL; |
eb805623 DV |
357 | } |
358 | readcount += dmc_offset; | |
359 | ||
360 | /* Extract dmc_header information. */ | |
361 | dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; | |
362 | if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { | |
363 | DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", | |
f98f70d9 | 364 | (dmc_header->header_len)); |
6a6582bf | 365 | return NULL; |
eb805623 DV |
366 | } |
367 | readcount += sizeof(struct intel_dmc_header); | |
368 | ||
369 | /* Cache the dmc header info. */ | |
370 | if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { | |
371 | DRM_ERROR("Firmware has wrong mmio count %u\n", | |
f98f70d9 | 372 | dmc_header->mmio_count); |
6a6582bf | 373 | return NULL; |
eb805623 DV |
374 | } |
375 | csr->mmio_count = dmc_header->mmio_count; | |
376 | for (i = 0; i < dmc_header->mmio_count; i++) { | |
982b0b2d | 377 | if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || |
f98f70d9 | 378 | dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { |
eb805623 | 379 | DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", |
f98f70d9 | 380 | dmc_header->mmioaddr[i]); |
6a6582bf | 381 | return NULL; |
eb805623 | 382 | } |
f0f59a00 | 383 | csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); |
eb805623 DV |
384 | csr->mmiodata[i] = dmc_header->mmiodata[i]; |
385 | } | |
386 | ||
387 | /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ | |
388 | nbytes = dmc_header->fw_size * 4; | |
389 | if (nbytes > CSR_MAX_FW_SIZE) { | |
390 | DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); | |
6a6582bf | 391 | return NULL; |
eb805623 DV |
392 | } |
393 | csr->dmc_fw_size = dmc_header->fw_size; | |
394 | ||
6a6582bf DV |
395 | dmc_payload = kmalloc(nbytes, GFP_KERNEL); |
396 | if (!dmc_payload) { | |
eb805623 | 397 | DRM_ERROR("Memory allocation failed for dmc payload\n"); |
6a6582bf | 398 | return NULL; |
eb805623 DV |
399 | } |
400 | ||
1bb4308e | 401 | return memcpy(dmc_payload, &fw->data[readcount], nbytes); |
6a6582bf DV |
402 | } |
403 | ||
8144ac59 | 404 | static void csr_load_work_fn(struct work_struct *work) |
6a6582bf | 405 | { |
8144ac59 DV |
406 | struct drm_i915_private *dev_priv; |
407 | struct intel_csr *csr; | |
408 | const struct firmware *fw; | |
409 | int ret; | |
410 | ||
411 | dev_priv = container_of(work, typeof(*dev_priv), csr.work); | |
412 | csr = &dev_priv->csr; | |
6a6582bf | 413 | |
8144ac59 DV |
414 | ret = request_firmware(&fw, dev_priv->csr.fw_path, |
415 | &dev_priv->dev->pdev->dev); | |
2abc525b ID |
416 | if (fw) |
417 | dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); | |
6a6582bf | 418 | |
6a6582bf | 419 | if (dev_priv->csr.dmc_payload) { |
2abc525b ID |
420 | intel_csr_load_program(dev_priv); |
421 | ||
01a6908c | 422 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
9c5308ea MK |
423 | |
424 | DRM_INFO("Finished loading %s (v%u.%u)\n", | |
425 | dev_priv->csr.fw_path, | |
426 | CSR_VERSION_MAJOR(csr->version), | |
427 | CSR_VERSION_MINOR(csr->version)); | |
428 | } else { | |
cbfc2d26 CW |
429 | dev_notice(dev_priv->dev->dev, |
430 | "Failed to load DMC firmware" | |
431 | " [" FIRMWARE_URL "]," | |
432 | " disabling runtime power management.\n"); | |
9c5308ea MK |
433 | } |
434 | ||
eb805623 DV |
435 | release_firmware(fw); |
436 | } | |
437 | ||
aa9145c4 AM |
438 | /** |
439 | * intel_csr_ucode_init() - initialize the firmware loading. | |
f4448375 | 440 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
441 | * |
442 | * This function is called at the time of loading the display driver to read | |
443 | * firmware from a .bin file and copied into a internal memory. | |
444 | */ | |
f4448375 | 445 | void intel_csr_ucode_init(struct drm_i915_private *dev_priv) |
eb805623 | 446 | { |
eb805623 | 447 | struct intel_csr *csr = &dev_priv->csr; |
8144ac59 DV |
448 | |
449 | INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); | |
eb805623 | 450 | |
f4448375 | 451 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
452 | return; |
453 | ||
4922d491 RV |
454 | if (IS_KABYLAKE(dev_priv)) |
455 | csr->fw_path = I915_CSR_KBL; | |
456 | else if (IS_SKYLAKE(dev_priv)) | |
eb805623 | 457 | csr->fw_path = I915_CSR_SKL; |
18c237c0 AM |
458 | else if (IS_BROXTON(dev_priv)) |
459 | csr->fw_path = I915_CSR_BXT; | |
eb805623 DV |
460 | else { |
461 | DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); | |
462 | return; | |
463 | } | |
464 | ||
abd41dc9 DL |
465 | DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); |
466 | ||
dc174300 SS |
467 | /* |
468 | * Obtain a runtime pm reference, until CSR is loaded, | |
469 | * to avoid entering runtime-suspend. | |
470 | */ | |
01a6908c | 471 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
dc174300 | 472 | |
8144ac59 | 473 | schedule_work(&dev_priv->csr.work); |
eb805623 DV |
474 | } |
475 | ||
f74ed08d ID |
476 | /** |
477 | * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend | |
478 | * @dev_priv: i915 drm device | |
479 | * | |
480 | * Prepare the DMC firmware before entering system suspend. This includes | |
481 | * flushing pending work items and releasing any resources acquired during | |
482 | * init. | |
483 | */ | |
484 | void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) | |
485 | { | |
486 | if (!HAS_CSR(dev_priv)) | |
487 | return; | |
488 | ||
489 | flush_work(&dev_priv->csr.work); | |
490 | ||
491 | /* Drop the reference held in case DMC isn't loaded. */ | |
492 | if (!dev_priv->csr.dmc_payload) | |
493 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
494 | } | |
495 | ||
496 | /** | |
497 | * intel_csr_ucode_resume() - init CSR firmware during system resume | |
498 | * @dev_priv: i915 drm device | |
499 | * | |
500 | * Reinitialize the DMC firmware during system resume, reacquiring any | |
501 | * resources released in intel_csr_ucode_suspend(). | |
502 | */ | |
503 | void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) | |
504 | { | |
505 | if (!HAS_CSR(dev_priv)) | |
506 | return; | |
507 | ||
508 | /* | |
509 | * Reacquire the reference to keep RPM disabled in case DMC isn't | |
510 | * loaded. | |
511 | */ | |
512 | if (!dev_priv->csr.dmc_payload) | |
513 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
514 | } | |
515 | ||
aa9145c4 AM |
516 | /** |
517 | * intel_csr_ucode_fini() - unload the CSR firmware. | |
f4448375 | 518 | * @dev_priv: i915 drm device. |
aa9145c4 | 519 | * |
f74ed08d | 520 | * Firmmware unloading includes freeing the internal memory and reset the |
aa9145c4 AM |
521 | * firmware loading status. |
522 | */ | |
f4448375 | 523 | void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) |
eb805623 | 524 | { |
f4448375 | 525 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
526 | return; |
527 | ||
f74ed08d | 528 | intel_csr_ucode_suspend(dev_priv); |
15e72c1f | 529 | |
eb805623 DV |
530 | kfree(dev_priv->csr.dmc_payload); |
531 | } |