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Merge tag 'nios2-v3.20-rc1' of git://git.rocketboards.org/linux-socfpga-next
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
142static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
154};
155
20f4dbe4 156enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 157{
0bdee30e 158 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 159 int type = intel_encoder->type;
160
0e32b39c
DA		 161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
0bdee30e 169
fc914639
PZ		 170 } else if (type == INTEL_OUTPUT_ANALOG) {
171 return PORT_E;
0bdee30e 172
fc914639
PZ		 173 } else {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
175 BUG();
176 }
177}
178
e58623cb
AR		 179/*
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
184 * of those
185 */
ad8d270c 186static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 u32 reg;
ce4dd49e 190 int i, n_hdmi_entries, hdmi_800mV_0dB;
6acab15a 191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
e58623cb 197
7f88e3af
DL		 198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
204 hdmi_800mV_0dB = 7;
205 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 208 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
10122051 210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 211 hdmi_800mV_0dB = 7;
e58623cb
AR		 212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 215 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
10122051 217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
ce4dd49e 218 hdmi_800mV_0dB = 6;
e58623cb
AR		 219 } else {
220 WARN(1, "ddi translation table missing\n");
300644c7 221 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
10122051 225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 226 hdmi_800mV_0dB = 7;
e58623cb
AR		 227 }
228
300644c7
PZ		 229 switch (port) {
230 case PORT_A:
231 ddi_translations = ddi_translations_edp;
232 break;
233 case PORT_B:
234 case PORT_C:
300644c7
PZ		 235 ddi_translations = ddi_translations_dp;
236 break;
77d8d009 237 case PORT_D:
5d8a7752 238 if (intel_dp_is_edp(dev, PORT_D))
77d8d009
PZ		 239 ddi_translations = ddi_translations_edp;
240 else
241 ddi_translations = ddi_translations_dp;
242 break;
300644c7 243 case PORT_E:
7f88e3af
DL		 244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
246 else
247 ddi_translations = ddi_translations_dp;
300644c7
PZ		 248 break;
249 default:
250 BUG();
251 }
45244b87 252
f72d19f0
PZ		 253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
10122051
JN		 255 I915_WRITE(reg, ddi_translations[i].trans1);
256 reg += 4;
257 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 258 reg += 4;
259 }
ce4dd49e
DL		 260
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
265
6acab15a 266 /* Entry 9 is for HDMI: */
10122051
JN		 267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
268 reg += 4;
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
270 reg += 4;
45244b87
ED		 271}
272
273/* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
275 */
276void intel_prepare_ddi(struct drm_device *dev)
277{
278 int port;
279
0d536cb4
PZ		 280 if (!HAS_DDI(dev))
281 return;
45244b87 282
ad8d270c
PZ		 283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
45244b87 285}
c82e4d26 286
248138b5
PZ		 287static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
288 enum port port)
289{
290 uint32_t reg = DDI_BUF_CTL(port);
291 int i;
292
293 for (i = 0; i < 8; i++) {
294 udelay(1);
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
296 return;
297 }
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
299}
c82e4d26
ED		 300
301/* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
304 *
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
308 */
309
310void hsw_fdi_link_train(struct drm_crtc *crtc)
311{
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 315 u32 temp, i, rx_ctl_val;
c82e4d26 316
04945641
PZ		 317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
320 * - FDI delay to 90h
8693a824
DL		 321 *
322 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 323 */
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
327
328 /* Enable the PCH Receiver FDI PLL */
3e68320e 329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 330 FDI_RX_PLL_ENABLE |
6e3c9717 331 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220);
335
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339
340 /* Configure Port Clock Select */
6e3c9717
ACO		 341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
342 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 343
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
10122051 346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
352 DP_TP_CTL_ENABLE);
353
876a8cdf
DL		 354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
c82e4d26 358 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 359 DDI_BUF_CTL_ENABLE |
6e3c9717 360 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 361 DDI_BUF_TRANS_SELECT(i / 2));
04945641 362 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 363
364 udelay(600);
365
04945641
PZ		 366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
368
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
373
374 /* Wait for FDI receiver lane calibration */
375 udelay(30);
376
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
382
383 /* Wait for FDI auto training time */
384 udelay(5);
c82e4d26
ED		 385
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 389
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
395 DP_TP_CTL_ENABLE);
c82e4d26 396
04945641 397 return;
c82e4d26 398 }
04945641 399
248138b5
PZ		 400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
404
04945641 405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
411
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 413
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 416 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 417
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 423 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 424 }
425
04945641 426 DRM_ERROR("FDI link training failed!\n");
c82e4d26 427}
0e72a5b5 428
44905a27
DA		 429void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
430{
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
434
435 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
438
439}
440
8d9ddbcb
PZ		 441static struct intel_encoder *
442intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
443{
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
448
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
450 ret = intel_encoder;
451 num_encoders++;
452 }
453
454 if (num_encoders != 1)
84f44ce7
VS		 455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 457
458 BUG_ON(ret == NULL);
459 return ret;
460}
461
d0737e1d
ACO		 462static struct intel_encoder *
463intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
464{
465 struct drm_device *dev = crtc->base.dev;
466 struct intel_encoder *intel_encoder, *ret = NULL;
467 int num_encoders = 0;
468
469 for_each_intel_encoder(dev, intel_encoder) {
470 if (intel_encoder->new_crtc == crtc) {
471 ret = intel_encoder;
472 num_encoders++;
473 }
474 }
475
476 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
477 pipe_name(crtc->pipe));
478
479 BUG_ON(ret == NULL);
480 return ret;
481}
482
1c0b85c5 483#define LC_FREQ 2700
27893390 484#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 485
486#define P_MIN 2
487#define P_MAX 64
488#define P_INC 2
489
490/* Constraints for PLL good behavior */
491#define REF_MIN 48
492#define REF_MAX 400
493#define VCO_MIN 2400
494#define VCO_MAX 4800
495
27893390
DL		 496#define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 501
502struct wrpll_rnp {
503 unsigned p, n2, r2;
504};
505
506static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 507{
1c0b85c5
DL		 508 unsigned budget;
509
510 switch (clock) {
511 case 25175000:
512 case 25200000:
513 case 27000000:
514 case 27027000:
515 case 37762500:
516 case 37800000:
517 case 40500000:
518 case 40541000:
519 case 54000000:
520 case 54054000:
521 case 59341000:
522 case 59400000:
523 case 72000000:
524 case 74176000:
525 case 74250000:
526 case 81000000:
527 case 81081000:
528 case 89012000:
529 case 89100000:
530 case 108000000:
531 case 108108000:
532 case 111264000:
533 case 111375000:
534 case 148352000:
535 case 148500000:
536 case 162000000:
537 case 162162000:
538 case 222525000:
539 case 222750000:
540 case 296703000:
541 case 297000000:
542 budget = 0;
543 break;
544 case 233500000:
545 case 245250000:
546 case 247750000:
547 case 253250000:
548 case 298000000:
549 budget = 1500;
550 break;
551 case 169128000:
552 case 169500000:
553 case 179500000:
554 case 202000000:
555 budget = 2000;
556 break;
557 case 256250000:
558 case 262500000:
559 case 270000000:
560 case 272500000:
561 case 273750000:
562 case 280750000:
563 case 281250000:
564 case 286000000:
565 case 291750000:
566 budget = 4000;
567 break;
568 case 267250000:
569 case 268500000:
570 budget = 5000;
571 break;
572 default:
573 budget = 1000;
574 break;
575 }
6441ab5f 576
1c0b85c5
DL		 577 return budget;
578}
579
580static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 unsigned r2, unsigned n2, unsigned p,
582 struct wrpll_rnp *best)
583{
584 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 585
1c0b85c5
DL		 586 /* No best (r,n,p) yet */
587 if (best->p == 0) {
588 best->p = p;
589 best->n2 = n2;
590 best->r2 = r2;
591 return;
592 }
6441ab5f 593
1c0b85c5
DL		 594 /*
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * freq2k.
597 *
598 * delta = 1e6 *
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
600 * freq2k;
601 *
602 * and we would like delta <= budget.
603 *
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
607 */
608 a = freq2k * budget * p * r2;
609 b = freq2k * budget * best->p * best->r2;
27893390
DL		 610 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
611 diff_best = abs_diff(freq2k * best->p * best->r2,
612 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 613 c = 1000000 * diff;
614 d = 1000000 * diff_best;
615
616 if (a < c && b < d) {
617 /* If both are above the budget, pick the closer */
618 if (best->p * best->r2 * diff < p * r2 * diff_best) {
619 best->p = p;
620 best->n2 = n2;
621 best->r2 = r2;
622 }
623 } else if (a >= c && b < d) {
624 /* If A is below the threshold but B is above it? Update. */
625 best->p = p;
626 best->n2 = n2;
627 best->r2 = r2;
628 } else if (a >= c && b >= d) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
631 best->p = p;
632 best->n2 = n2;
633 best->r2 = r2;
634 }
635 }
636 /* Otherwise a < c && b >= d, do nothing */
637}
638
11578553
JB		 639static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
640 int reg)
641{
642 int refclk = LC_FREQ;
643 int n, p, r;
644 u32 wrpll;
645
646 wrpll = I915_READ(reg);
114fe488
DV		 647 switch (wrpll & WRPLL_PLL_REF_MASK) {
648 case WRPLL_PLL_SSC:
649 case WRPLL_PLL_NON_SSC:
11578553
JB		 650 /*
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
653 * 0.5% downspread.
654 */
655 refclk = 135;
656 break;
114fe488 657 case WRPLL_PLL_LCPLL:
11578553
JB		 658 refclk = LC_FREQ;
659 break;
660 default:
661 WARN(1, "bad wrpll refclk\n");
662 return 0;
663 }
664
665 r = wrpll & WRPLL_DIVIDER_REF_MASK;
666 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
667 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
668
20f0ec16
JB		 669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk * n * 100) / (p * r);
11578553
JB		 671}
672
540e732c
S		 673static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
674 uint32_t dpll)
675{
676 uint32_t cfgcr1_reg, cfgcr2_reg;
677 uint32_t cfgcr1_val, cfgcr2_val;
678 uint32_t p0, p1, p2, dco_freq;
679
680 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
681 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
682
683 cfgcr1_val = I915_READ(cfgcr1_reg);
684 cfgcr2_val = I915_READ(cfgcr2_reg);
685
686 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
687 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
688
689 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
690 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
691 else
692 p1 = 1;
693
694
695 switch (p0) {
696 case DPLL_CFGCR2_PDIV_1:
697 p0 = 1;
698 break;
699 case DPLL_CFGCR2_PDIV_2:
700 p0 = 2;
701 break;
702 case DPLL_CFGCR2_PDIV_3:
703 p0 = 3;
704 break;
705 case DPLL_CFGCR2_PDIV_7:
706 p0 = 7;
707 break;
708 }
709
710 switch (p2) {
711 case DPLL_CFGCR2_KDIV_5:
712 p2 = 5;
713 break;
714 case DPLL_CFGCR2_KDIV_2:
715 p2 = 2;
716 break;
717 case DPLL_CFGCR2_KDIV_3:
718 p2 = 3;
719 break;
720 case DPLL_CFGCR2_KDIV_1:
721 p2 = 1;
722 break;
723 }
724
725 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
726
727 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
728 1000) / 0x8000;
729
730 return dco_freq / (p0 * p1 * p2 * 5);
731}
732
733
734static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 735 struct intel_crtc_state *pipe_config)
540e732c
S		 736{
737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 738 int link_clock = 0;
739 uint32_t dpll_ctl1, dpll;
740
134ffa44 741 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 742
743 dpll_ctl1 = I915_READ(DPLL_CTRL1);
744
745 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
746 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
747 } else {
748 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
749 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
750
751 switch (link_clock) {
752 case DPLL_CRTL1_LINK_RATE_810:
753 link_clock = 81000;
754 break;
755 case DPLL_CRTL1_LINK_RATE_1350:
756 link_clock = 135000;
757 break;
758 case DPLL_CRTL1_LINK_RATE_2700:
759 link_clock = 270000;
760 break;
761 default:
762 WARN(1, "Unsupported link rate\n");
763 break;
764 }
765 link_clock *= 2;
766 }
767
768 pipe_config->port_clock = link_clock;
769
770 if (pipe_config->has_dp_encoder)
2d112de7 771 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 772 intel_dotclock_calculate(pipe_config->port_clock,
773 &pipe_config->dp_m_n);
774 else
2d112de7 775 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 776}
777
3d51278a 778static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 779 struct intel_crtc_state *pipe_config)
11578553
JB		 780{
781 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 782 int link_clock = 0;
783 u32 val, pll;
784
26804afd 785 val = pipe_config->ddi_pll_sel;
11578553
JB		 786 switch (val & PORT_CLK_SEL_MASK) {
787 case PORT_CLK_SEL_LCPLL_810:
788 link_clock = 81000;
789 break;
790 case PORT_CLK_SEL_LCPLL_1350:
791 link_clock = 135000;
792 break;
793 case PORT_CLK_SEL_LCPLL_2700:
794 link_clock = 270000;
795 break;
796 case PORT_CLK_SEL_WRPLL1:
797 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
798 break;
799 case PORT_CLK_SEL_WRPLL2:
800 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
801 break;
802 case PORT_CLK_SEL_SPLL:
803 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
804 if (pll == SPLL_PLL_FREQ_810MHz)
805 link_clock = 81000;
806 else if (pll == SPLL_PLL_FREQ_1350MHz)
807 link_clock = 135000;
808 else if (pll == SPLL_PLL_FREQ_2700MHz)
809 link_clock = 270000;
810 else {
811 WARN(1, "bad spll freq\n");
812 return;
813 }
814 break;
815 default:
816 WARN(1, "bad port clock sel\n");
817 return;
818 }
819
820 pipe_config->port_clock = link_clock * 2;
821
822 if (pipe_config->has_pch_encoder)
2d112de7 823 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 824 intel_dotclock_calculate(pipe_config->port_clock,
825 &pipe_config->fdi_m_n);
826 else if (pipe_config->has_dp_encoder)
2d112de7 827 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 828 intel_dotclock_calculate(pipe_config->port_clock,
829 &pipe_config->dp_m_n);
830 else
2d112de7 831 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 832}
833
3d51278a 834void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 835 struct intel_crtc_state *pipe_config)
3d51278a 836{
22606a18
DL		 837 struct drm_device *dev = encoder->base.dev;
838
839 if (INTEL_INFO(dev)->gen <= 8)
840 hsw_ddi_clock_get(encoder, pipe_config);
841 else
842 skl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 843}
844
1c0b85c5 845static void
d664c0ce
DL		 846hsw_ddi_calculate_wrpll(int clock /* in Hz */,
847 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 848{
849 uint64_t freq2k;
850 unsigned p, n2, r2;
851 struct wrpll_rnp best = { 0, 0, 0 };
852 unsigned budget;
853
854 freq2k = clock / 100;
855
856 budget = wrpll_get_budget_for_freq(clock);
857
858 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
859 * and directly pass the LC PLL to it. */
860 if (freq2k == 5400000) {
861 *n2_out = 2;
862 *p_out = 1;
863 *r2_out = 2;
864 return;
865 }
866
867 /*
868 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
869 * the WR PLL.
870 *
871 * We want R so that REF_MIN <= Ref <= REF_MAX.
872 * Injecting R2 = 2 * R gives:
873 * REF_MAX * r2 > LC_FREQ * 2 and
874 * REF_MIN * r2 < LC_FREQ * 2
875 *
876 * Which means the desired boundaries for r2 are:
877 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
878 *
879 */
880 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
881 r2 <= LC_FREQ * 2 / REF_MIN;
882 r2++) {
883
884 /*
885 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
886 *
887 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
888 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
889 * VCO_MAX * r2 > n2 * LC_FREQ and
890 * VCO_MIN * r2 < n2 * LC_FREQ)
891 *
892 * Which means the desired boundaries for n2 are:
893 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
894 */
895 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
896 n2 <= VCO_MAX * r2 / LC_FREQ;
897 n2++) {
898
899 for (p = P_MIN; p <= P_MAX; p += P_INC)
900 wrpll_update_rnp(freq2k, budget,
901 r2, n2, p, &best);
902 }
903 }
6441ab5f 904
1c0b85c5
DL		 905 *n2_out = best.n2;
906 *p_out = best.p;
907 *r2_out = best.r2;
6441ab5f
PZ		 908}
909
0220ab6e 910static bool
d664c0ce 911hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 912 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 913 struct intel_encoder *intel_encoder,
914 int clock)
6441ab5f 915{
d664c0ce 916 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 917 struct intel_shared_dpll *pll;
716c2e55 918 uint32_t val;
1c0b85c5 919 unsigned p, n2, r2;
6441ab5f 920
d664c0ce 921 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 922
114fe488 923 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 924 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
925 WRPLL_DIVIDER_POST(p);
926
190f68c5 927 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 928
190f68c5 929 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 930 if (pll == NULL) {
931 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
932 pipe_name(intel_crtc->pipe));
933 return false;
0694001b 934 }
d452c5b6 935
190f68c5 936 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 937 }
938
6441ab5f
PZ		 939 return true;
940}
941
82d35437
S		 942struct skl_wrpll_params {
943 uint32_t dco_fraction;
944 uint32_t dco_integer;
945 uint32_t qdiv_ratio;
946 uint32_t qdiv_mode;
947 uint32_t kdiv;
948 uint32_t pdiv;
949 uint32_t central_freq;
950};
951
952static void
953skl_ddi_calculate_wrpll(int clock /* in Hz */,
954 struct skl_wrpll_params *wrpll_params)
955{
956 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 957 uint64_t dco_central_freq[3] = {8400000000ULL,
958 9000000000ULL,
959 9600000000ULL};
82d35437
S		 960 uint32_t min_dco_deviation = 400;
961 uint32_t min_dco_index = 3;
962 uint32_t P0[4] = {1, 2, 3, 7};
963 uint32_t P2[4] = {1, 2, 3, 5};
964 bool found = false;
965 uint32_t candidate_p = 0;
966 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
967 uint32_t candidate_p2[3] = {0};
968 uint32_t dco_central_freq_deviation[3];
969 uint32_t i, P1, k, dco_count;
970 bool retry_with_odd = false;
971 uint64_t dco_freq;
972
973 /* Determine P0, P1 or P2 */
974 for (dco_count = 0; dco_count < 3; dco_count++) {
975 found = false;
976 candidate_p =
977 div64_u64(dco_central_freq[dco_count], afe_clock);
978 if (retry_with_odd == false)
979 candidate_p = (candidate_p % 2 == 0 ?
980 candidate_p : candidate_p + 1);
981
982 for (P1 = 1; P1 < candidate_p; P1++) {
983 for (i = 0; i < 4; i++) {
984 if (!(P0[i] != 1 || P1 == 1))
985 continue;
986
987 for (k = 0; k < 4; k++) {
988 if (P1 != 1 && P2[k] != 2)
989 continue;
990
991 if (candidate_p == P0[i] * P1 * P2[k]) {
992 /* Found possible P0, P1, P2 */
993 found = true;
994 candidate_p0[dco_count] = P0[i];
995 candidate_p1[dco_count] = P1;
996 candidate_p2[dco_count] = P2[k];
997 goto found;
998 }
999
1000 }
1001 }
1002 }
1003
1004found:
1005 if (found) {
1006 dco_central_freq_deviation[dco_count] =
1007 div64_u64(10000 *
1008 abs_diff((candidate_p * afe_clock),
1009 dco_central_freq[dco_count]),
1010 dco_central_freq[dco_count]);
1011
1012 if (dco_central_freq_deviation[dco_count] <
1013 min_dco_deviation) {
1014 min_dco_deviation =
1015 dco_central_freq_deviation[dco_count];
1016 min_dco_index = dco_count;
1017 }
1018 }
1019
1020 if (min_dco_index > 2 && dco_count == 2) {
1021 retry_with_odd = true;
1022 dco_count = 0;
1023 }
1024 }
1025
1026 if (min_dco_index > 2) {
1027 WARN(1, "No valid values found for the given pixel clock\n");
1028 } else {
1029 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1030
1031 switch (dco_central_freq[min_dco_index]) {
21318cce 1032 case 9600000000ULL:
82d35437
S		 1033 wrpll_params->central_freq = 0;
1034 break;
21318cce 1035 case 9000000000ULL:
82d35437
S		 1036 wrpll_params->central_freq = 1;
1037 break;
21318cce 1038 case 8400000000ULL:
82d35437
S		 1039 wrpll_params->central_freq = 3;
1040 }
1041
1042 switch (candidate_p0[min_dco_index]) {
1043 case 1:
1044 wrpll_params->pdiv = 0;
1045 break;
1046 case 2:
1047 wrpll_params->pdiv = 1;
1048 break;
1049 case 3:
1050 wrpll_params->pdiv = 2;
1051 break;
1052 case 7:
1053 wrpll_params->pdiv = 4;
1054 break;
1055 default:
1056 WARN(1, "Incorrect PDiv\n");
1057 }
1058
1059 switch (candidate_p2[min_dco_index]) {
1060 case 5:
1061 wrpll_params->kdiv = 0;
1062 break;
1063 case 2:
1064 wrpll_params->kdiv = 1;
1065 break;
1066 case 3:
1067 wrpll_params->kdiv = 2;
1068 break;
1069 case 1:
1070 wrpll_params->kdiv = 3;
1071 break;
1072 default:
1073 WARN(1, "Incorrect KDiv\n");
1074 }
1075
1076 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1077 wrpll_params->qdiv_mode =
1078 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1079
1080 dco_freq = candidate_p0[min_dco_index] *
1081 candidate_p1[min_dco_index] *
1082 candidate_p2[min_dco_index] * afe_clock;
1083
1084 /*
1085 * Intermediate values are in Hz.
1086 * Divide by MHz to match bsepc
1087 */
1088 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1089 wrpll_params->dco_fraction =
1090 div_u64(((div_u64(dco_freq, 24) -
1091 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1092
1093 }
1094}
1095
1096
1097static bool
1098skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1099 struct intel_crtc_state *crtc_state,
82d35437
S		 1100 struct intel_encoder *intel_encoder,
1101 int clock)
1102{
1103 struct intel_shared_dpll *pll;
1104 uint32_t ctrl1, cfgcr1, cfgcr2;
1105
1106 /*
1107 * See comment in intel_dpll_hw_state to understand why we always use 0
1108 * as the DPLL id in this function.
1109 */
1110
1111 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1112
1113 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1114 struct skl_wrpll_params wrpll_params = { 0, };
1115
1116 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1117
1118 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1119
1120 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1121 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1122 wrpll_params.dco_integer;
1123
1124 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1125 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1126 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1127 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1128 wrpll_params.central_freq;
1129 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1130 struct drm_encoder *encoder = &intel_encoder->base;
1131 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1132
1133 switch (intel_dp->link_bw) {
1134 case DP_LINK_BW_1_62:
1135 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1136 break;
1137 case DP_LINK_BW_2_7:
1138 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1139 break;
1140 case DP_LINK_BW_5_4:
1141 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1142 break;
1143 }
1144
1145 cfgcr1 = cfgcr2 = 0;
1146 } else /* eDP */
1147 return true;
1148
190f68c5
ACO		 1149 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1150 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1151 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1152
190f68c5 1153 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1154 if (pll == NULL) {
1155 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1156 pipe_name(intel_crtc->pipe));
1157 return false;
1158 }
1159
1160 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1161 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1162
1163 return true;
1164}
0220ab6e
DL		 1165
1166/*
1167 * Tries to find a *shared* PLL for the CRTC and store it in
1168 * intel_crtc->ddi_pll_sel.
1169 *
1170 * For private DPLLs, compute_config() should do the selection for us. This
1171 * function should be folded into compute_config() eventually.
1172 */
190f68c5
ACO		 1173bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1174 struct intel_crtc_state *crtc_state)
0220ab6e 1175{
82d35437 1176 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d
ACO		 1177 struct intel_encoder *intel_encoder =
1178 intel_ddi_get_crtc_new_encoder(intel_crtc);
190f68c5 1179 int clock = crtc_state->port_clock;
0220ab6e 1180
82d35437 1181 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1182 return skl_ddi_pll_select(intel_crtc, crtc_state,
1183 intel_encoder, clock);
82d35437 1184 else
190f68c5
ACO		 1185 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1186 intel_encoder, clock);
0220ab6e
DL		 1187}
1188
dae84799
PZ		 1189void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1193 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1194 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1195 int type = intel_encoder->type;
1196 uint32_t temp;
1197
0e32b39c 1198 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1199 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1200 switch (intel_crtc->config->pipe_bpp) {
dae84799 1201 case 18:
c9809791 1202 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1203 break;
1204 case 24:
c9809791 1205 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1206 break;
1207 case 30:
c9809791 1208 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1209 break;
1210 case 36:
c9809791 1211 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1212 break;
1213 default:
4e53c2e0 1214 BUG();
dae84799 1215 }
c9809791 1216 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1217 }
1218}
1219
0e32b39c
DA		 1220void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1221{
1222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1223 struct drm_device *dev = crtc->dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1225 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1226 uint32_t temp;
1227 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1228 if (state == true)
1229 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1230 else
1231 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1232 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1233}
1234
8228c251 1235void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1236{
1237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1238 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1239 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1240 struct drm_device *dev = crtc->dev;
1241 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1242 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1243 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1244 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1245 int type = intel_encoder->type;
8d9ddbcb
PZ		 1246 uint32_t temp;
1247
ad80a810
PZ		 1248 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1249 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1250 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1251
6e3c9717 1252 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1253 case 18:
ad80a810 1254 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1255 break;
1256 case 24:
ad80a810 1257 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1258 break;
1259 case 30:
ad80a810 1260 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1261 break;
1262 case 36:
ad80a810 1263 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1264 break;
1265 default:
4e53c2e0 1266 BUG();
dfcef252 1267 }
72662e10 1268
6e3c9717 1269 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1270 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1271 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1272 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1273
e6f0bfc4
PZ		 1274 if (cpu_transcoder == TRANSCODER_EDP) {
1275 switch (pipe) {
1276 case PIPE_A:
c7670b10
PZ		 1277 /* On Haswell, can only use the always-on power well for
1278 * eDP when not using the panel fitter, and when not
1279 * using motion blur mitigation (which we don't
1280 * support). */
fabf6e51 1281 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1282 (intel_crtc->config->pch_pfit.enabled ||
1283 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1284 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1285 else
1286 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1287 break;
1288 case PIPE_B:
1289 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1290 break;
1291 case PIPE_C:
1292 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1293 break;
1294 default:
1295 BUG();
1296 break;
1297 }
1298 }
1299
7739c33b 1300 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1301 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1302 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1303 else
ad80a810 1304 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1305
7739c33b 1306 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1307 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1308 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1309
1310 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1311 type == INTEL_OUTPUT_EDP) {
1312 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1313
0e32b39c
DA		 1314 if (intel_dp->is_mst) {
1315 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1316 } else
1317 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1318
1319 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1320 } else if (type == INTEL_OUTPUT_DP_MST) {
1321 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1322
1323 if (intel_dp->is_mst) {
1324 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1325 } else
1326 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1327
17aa6be9 1328 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1329 } else {
84f44ce7
VS		 1330 WARN(1, "Invalid encoder type %d for pipe %c\n",
1331 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1332 }
1333
ad80a810 1334 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1335}
72662e10 1336
ad80a810
PZ		 1337void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1338 enum transcoder cpu_transcoder)
8d9ddbcb 1339{
ad80a810 1340 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1341 uint32_t val = I915_READ(reg);
1342
0e32b39c 1343 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1344 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1345 I915_WRITE(reg, val);
72662e10
ED		 1346}
1347
bcbc889b
PZ		 1348bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1349{
1350 struct drm_device *dev = intel_connector->base.dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 struct intel_encoder *intel_encoder = intel_connector->encoder;
1353 int type = intel_connector->base.connector_type;
1354 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1355 enum pipe pipe = 0;
1356 enum transcoder cpu_transcoder;
882244a3 1357 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1358 uint32_t tmp;
1359
882244a3 1360 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1361 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1362 return false;
1363
bcbc889b
PZ		 1364 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1365 return false;
1366
1367 if (port == PORT_A)
1368 cpu_transcoder = TRANSCODER_EDP;
1369 else
1a240d4d 1370 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1371
1372 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1373
1374 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1375 case TRANS_DDI_MODE_SELECT_HDMI:
1376 case TRANS_DDI_MODE_SELECT_DVI:
1377 return (type == DRM_MODE_CONNECTOR_HDMIA);
1378
1379 case TRANS_DDI_MODE_SELECT_DP_SST:
1380 if (type == DRM_MODE_CONNECTOR_eDP)
1381 return true;
bcbc889b 1382 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1383 case TRANS_DDI_MODE_SELECT_DP_MST:
1384 /* if the transcoder is in MST state then
1385 * connector isn't connected */
1386 return false;
bcbc889b
PZ		 1387
1388 case TRANS_DDI_MODE_SELECT_FDI:
1389 return (type == DRM_MODE_CONNECTOR_VGA);
1390
1391 default:
1392 return false;
1393 }
1394}
1395
85234cdc
DV		 1396bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1397 enum pipe *pipe)
1398{
1399 struct drm_device *dev = encoder->base.dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1401 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1402 enum intel_display_power_domain power_domain;
85234cdc
DV		 1403 u32 tmp;
1404 int i;
1405
6d129bea 1406 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1407 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1408 return false;
1409
fe43d3f5 1410 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1411
1412 if (!(tmp & DDI_BUF_CTL_ENABLE))
1413 return false;
1414
ad80a810
PZ		 1415 if (port == PORT_A) {
1416 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1417
ad80a810
PZ		 1418 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1419 case TRANS_DDI_EDP_INPUT_A_ON:
1420 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1421 *pipe = PIPE_A;
1422 break;
1423 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1424 *pipe = PIPE_B;
1425 break;
1426 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1427 *pipe = PIPE_C;
1428 break;
1429 }
1430
1431 return true;
1432 } else {
1433 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1434 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1435
1436 if ((tmp & TRANS_DDI_PORT_MASK)
1437 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1438 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1439 return false;
1440
ad80a810
PZ		 1441 *pipe = i;
1442 return true;
1443 }
85234cdc
DV		 1444 }
1445 }
1446
84f44ce7 1447 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1448
22f9fe50 1449 return false;
85234cdc
DV		 1450}
1451
fc914639
PZ		 1452void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1453{
1454 struct drm_crtc *crtc = &intel_crtc->base;
1455 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1456 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1457 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1458 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1459
bb523fc0
PZ		 1460 if (cpu_transcoder != TRANSCODER_EDP)
1461 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1462 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1463}
1464
1465void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1466{
1467 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1468 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1469
bb523fc0
PZ		 1470 if (cpu_transcoder != TRANSCODER_EDP)
1471 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1472 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1473}
1474
00c09d70 1475static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1476{
c19b0669 1477 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1478 struct drm_device *dev = encoder->dev;
1479 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1480 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1481 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1482 int type = intel_encoder->type;
6441ab5f 1483
82a4d9c0
PZ		 1484 if (type == INTEL_OUTPUT_EDP) {
1485 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1486 intel_edp_panel_on(intel_dp);
82a4d9c0 1487 }
6441ab5f 1488
efa80add 1489 if (IS_SKYLAKE(dev)) {
6e3c9717 1490 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1491 uint32_t val;
1492
5416d871
DL		 1493 /*
1494 * DPLL0 is used for eDP and is the only "private" DPLL (as
1495 * opposed to shared) on SKL
1496 */
1497 if (type == INTEL_OUTPUT_EDP) {
1498 WARN_ON(dpll != SKL_DPLL0);
1499
1500 val = I915_READ(DPLL_CTRL1);
1501
1502 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1503 DPLL_CTRL1_SSC(dpll) |
1504 DPLL_CRTL1_LINK_RATE_MASK(dpll));
6e3c9717 1505 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1506
1507 I915_WRITE(DPLL_CTRL1, val);
1508 POSTING_READ(DPLL_CTRL1);
1509 }
1510
1511 /* DDI -> PLL mapping */
efa80add
S		 1512 val = I915_READ(DPLL_CTRL2);
1513
1514 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1515 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1516 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1517 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1518
1519 I915_WRITE(DPLL_CTRL2, val);
5416d871 1520
efa80add 1521 } else {
6e3c9717
ACO		 1522 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1523 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1524 }
c19b0669 1525
82a4d9c0 1526 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1527 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1528
44905a27 1529 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1530
1531 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1532 intel_dp_start_link_train(intel_dp);
1533 intel_dp_complete_link_train(intel_dp);
23f08d83 1534 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1535 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1536 } else if (type == INTEL_OUTPUT_HDMI) {
1537 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1538
1539 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1540 crtc->config->has_hdmi_sink,
1541 &crtc->config->base.adjusted_mode);
c19b0669 1542 }
6441ab5f
PZ		 1543}
1544
00c09d70 1545static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1546{
1547 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1548 struct drm_device *dev = encoder->dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1550 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1551 int type = intel_encoder->type;
2886e93f 1552 uint32_t val;
a836bdf9 1553 bool wait = false;
2886e93f
PZ		 1554
1555 val = I915_READ(DDI_BUF_CTL(port));
1556 if (val & DDI_BUF_CTL_ENABLE) {
1557 val &= ~DDI_BUF_CTL_ENABLE;
1558 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1559 wait = true;
2886e93f 1560 }
6441ab5f 1561
a836bdf9
PZ		 1562 val = I915_READ(DP_TP_CTL(port));
1563 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1564 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1565 I915_WRITE(DP_TP_CTL(port), val);
1566
1567 if (wait)
1568 intel_wait_ddi_buf_idle(dev_priv, port);
1569
76bb80ed 1570 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1571 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1572 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1573 intel_edp_panel_vdd_on(intel_dp);
4be73780 1574 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1575 }
1576
efa80add
S		 1577 if (IS_SKYLAKE(dev))
1578 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1579 DPLL_CTRL2_DDI_CLK_OFF(port)));
1580 else
1581 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1582}
1583
00c09d70 1584static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1585{
6547fef8 1586 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1587 struct drm_crtc *crtc = encoder->crtc;
1588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1589 struct drm_device *dev = encoder->dev;
72662e10 1590 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1591 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1592 int type = intel_encoder->type;
72662e10 1593
6547fef8 1594 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1595 struct intel_digital_port *intel_dig_port =
1596 enc_to_dig_port(encoder);
1597
6547fef8
PZ		 1598 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1599 * are ignored so nothing special needs to be done besides
1600 * enabling the port.
1601 */
876a8cdf 1602 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1603 intel_dig_port->saved_port_bits |
1604 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1605 } else if (type == INTEL_OUTPUT_EDP) {
1606 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1607
23f08d83 1608 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1609 intel_dp_stop_link_train(intel_dp);
1610
4be73780 1611 intel_edp_backlight_on(intel_dp);
0bc12bcb 1612 intel_psr_enable(intel_dp);
c395578e 1613 intel_edp_drrs_enable(intel_dp);
6547fef8 1614 }
7b9f35a6 1615
6e3c9717 1616 if (intel_crtc->config->has_audio) {
d45a0bf5 1617 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1618 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1619 }
5ab432ef
DV		 1620}
1621
00c09d70 1622static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1623{
d6c50ff8 1624 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1625 struct drm_crtc *crtc = encoder->crtc;
1626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1627 int type = intel_encoder->type;
7b9f35a6
WX		 1628 struct drm_device *dev = encoder->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1630
6e3c9717 1631 if (intel_crtc->config->has_audio) {
69bfe1a9 1632 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1633 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1634 }
2831d842 1635
d6c50ff8
PZ		 1636 if (type == INTEL_OUTPUT_EDP) {
1637 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1638
c395578e 1639 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1640 intel_psr_disable(intel_dp);
4be73780 1641 intel_edp_backlight_off(intel_dp);
d6c50ff8 1642 }
72662e10 1643}
79f689aa 1644
121643c2
S		 1645static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1646{
1647 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1648 uint32_t cdctl = I915_READ(CDCLK_CTL);
1649 uint32_t linkrate;
1650
1651 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1652 WARN(1, "LCPLL1 not enabled\n");
1653 return 24000; /* 24MHz is the cd freq with NSSC ref */
1654 }
1655
1656 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1657 return 540000;
1658
1659 linkrate = (I915_READ(DPLL_CTRL1) &
1660 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1661
1662 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1663 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1664 /* vco 8640 */
1665 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1666 case CDCLK_FREQ_450_432:
1667 return 432000;
1668 case CDCLK_FREQ_337_308:
1669 return 308570;
1670 case CDCLK_FREQ_675_617:
1671 return 617140;
1672 default:
1673 WARN(1, "Unknown cd freq selection\n");
1674 }
1675 } else {
1676 /* vco 8100 */
1677 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1678 case CDCLK_FREQ_450_432:
1679 return 450000;
1680 case CDCLK_FREQ_337_308:
1681 return 337500;
1682 case CDCLK_FREQ_675_617:
1683 return 675000;
1684 default:
1685 WARN(1, "Unknown cd freq selection\n");
1686 }
1687 }
1688
1689 /* error case, do as if DPLL0 isn't enabled */
1690 return 24000;
1691}
1692
ad13d604
DL		 1693static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1694{
1695 uint32_t lcpll = I915_READ(LCPLL_CTL);
1696 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1697
1698 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1699 return 800000;
1700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1701 return 450000;
1702 else if (freq == LCPLL_CLK_FREQ_450)
1703 return 450000;
1704 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1705 return 540000;
1706 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1707 return 337500;
1708 else
1709 return 675000;
1710}
1711
1712static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1713{
e39bf98a 1714 struct drm_device *dev = dev_priv->dev;
a4006641 1715 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1716 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1717
ad13d604 1718 if (lcpll & LCPLL_CD_SOURCE_FCLK)
a4006641 1719 return 800000;
ad13d604 1720 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
b2b877ff 1721 return 450000;
ad13d604 1722 else if (freq == LCPLL_CLK_FREQ_450)
b2b877ff 1723 return 450000;
95626e7c 1724 else if (IS_HSW_ULT(dev))
ad13d604
DL		 1725 return 337500;
1726 else
1727 return 540000;
1728}
1729
1730int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1731{
1732 struct drm_device *dev = dev_priv->dev;
1733
121643c2
S		 1734 if (IS_SKYLAKE(dev))
1735 return skl_get_cdclk_freq(dev_priv);
1736
ad13d604
DL		 1737 if (IS_BROADWELL(dev))
1738 return bdw_get_cdclk_freq(dev_priv);
1739
1740 /* Haswell */
1741 return hsw_get_cdclk_freq(dev_priv);
79f689aa
PZ		 1742}
1743
e0b01be4
DV		 1744static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1745 struct intel_shared_dpll *pll)
1746{
3e369b76 1747 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 1748 POSTING_READ(WRPLL_CTL(pll->id));
1749 udelay(20);
1750}
1751
12030431
DV		 1752static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1753 struct intel_shared_dpll *pll)
1754{
1755 uint32_t val;
1756
1757 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 1758 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1759 POSTING_READ(WRPLL_CTL(pll->id));
1760}
1761
d452c5b6
DV		 1762static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1763 struct intel_shared_dpll *pll,
1764 struct intel_dpll_hw_state *hw_state)
1765{
1766 uint32_t val;
1767
f458ebbc 1768 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 1769 return false;
1770
1771 val = I915_READ(WRPLL_CTL(pll->id));
1772 hw_state->wrpll = val;
1773
1774 return val & WRPLL_PLL_ENABLE;
1775}
1776
ca1381b5 1777static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 1778 "WRPLL 1",
1779 "WRPLL 2",
1780};
1781
143b307c 1782static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 1783{
9cd86933
DV		 1784 int i;
1785
716c2e55 1786 dev_priv->num_shared_dpll = 2;
9cd86933 1787
716c2e55 1788 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 1789 dev_priv->shared_dplls[i].id = i;
1790 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 1791 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 1792 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 1793 dev_priv->shared_dplls[i].get_hw_state =
1794 hsw_ddi_pll_get_hw_state;
9cd86933 1795 }
143b307c
DL		 1796}
1797
d1a2dc78
S		 1798static const char * const skl_ddi_pll_names[] = {
1799 "DPLL 1",
1800 "DPLL 2",
1801 "DPLL 3",
1802};
1803
1804struct skl_dpll_regs {
1805 u32 ctl, cfgcr1, cfgcr2;
1806};
1807
1808/* this array is indexed by the *shared* pll id */
1809static const struct skl_dpll_regs skl_dpll_regs[3] = {
1810 {
1811 /* DPLL 1 */
1812 .ctl = LCPLL2_CTL,
1813 .cfgcr1 = DPLL1_CFGCR1,
1814 .cfgcr2 = DPLL1_CFGCR2,
1815 },
1816 {
1817 /* DPLL 2 */
1818 .ctl = WRPLL_CTL1,
1819 .cfgcr1 = DPLL2_CFGCR1,
1820 .cfgcr2 = DPLL2_CFGCR2,
1821 },
1822 {
1823 /* DPLL 3 */
1824 .ctl = WRPLL_CTL2,
1825 .cfgcr1 = DPLL3_CFGCR1,
1826 .cfgcr2 = DPLL3_CFGCR2,
1827 },
1828};
1829
1830static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1831 struct intel_shared_dpll *pll)
1832{
1833 uint32_t val;
1834 unsigned int dpll;
1835 const struct skl_dpll_regs *regs = skl_dpll_regs;
1836
1837 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1838 dpll = pll->id + 1;
1839
1840 val = I915_READ(DPLL_CTRL1);
1841
1842 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1843 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1844 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1845
1846 I915_WRITE(DPLL_CTRL1, val);
1847 POSTING_READ(DPLL_CTRL1);
1848
1849 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1850 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1851 POSTING_READ(regs[pll->id].cfgcr1);
1852 POSTING_READ(regs[pll->id].cfgcr2);
1853
1854 /* the enable bit is always bit 31 */
1855 I915_WRITE(regs[pll->id].ctl,
1856 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1857
1858 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1859 DRM_ERROR("DPLL %d not locked\n", dpll);
1860}
1861
1862static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1863 struct intel_shared_dpll *pll)
1864{
1865 const struct skl_dpll_regs *regs = skl_dpll_regs;
1866
1867 /* the enable bit is always bit 31 */
1868 I915_WRITE(regs[pll->id].ctl,
1869 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1870 POSTING_READ(regs[pll->id].ctl);
1871}
1872
1873static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1874 struct intel_shared_dpll *pll,
1875 struct intel_dpll_hw_state *hw_state)
1876{
1877 uint32_t val;
1878 unsigned int dpll;
1879 const struct skl_dpll_regs *regs = skl_dpll_regs;
1880
1881 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1882 return false;
1883
1884 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1885 dpll = pll->id + 1;
1886
1887 val = I915_READ(regs[pll->id].ctl);
1888 if (!(val & LCPLL_PLL_ENABLE))
1889 return false;
1890
1891 val = I915_READ(DPLL_CTRL1);
1892 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1893
1894 /* avoid reading back stale values if HDMI mode is not enabled */
1895 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1896 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1897 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1898 }
1899
1900 return true;
1901}
1902
1903static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1904{
1905 int i;
1906
1907 dev_priv->num_shared_dpll = 3;
1908
1909 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1910 dev_priv->shared_dplls[i].id = i;
1911 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1912 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1913 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1914 dev_priv->shared_dplls[i].get_hw_state =
1915 skl_ddi_pll_get_hw_state;
1916 }
1917}
1918
143b307c
DL		 1919void intel_ddi_pll_init(struct drm_device *dev)
1920{
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 uint32_t val = I915_READ(LCPLL_CTL);
1923
d1a2dc78
S		 1924 if (IS_SKYLAKE(dev))
1925 skl_shared_dplls_init(dev_priv);
1926 else
1927 hsw_shared_dplls_init(dev_priv);
79f689aa 1928
b2b877ff 1929 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1930 intel_ddi_get_cdclk_freq(dev_priv));
1931
121643c2
S		 1932 if (IS_SKYLAKE(dev)) {
1933 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1934 DRM_ERROR("LCPLL1 is disabled\n");
1935 } else {
1936 /*
1937 * The LCPLL register should be turned on by the BIOS. For now
1938 * let's just check its state and print errors in case
1939 * something is wrong. Don't even try to turn it on.
1940 */
1941
1942 if (val & LCPLL_CD_SOURCE_FCLK)
1943 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 1944
121643c2
S		 1945 if (val & LCPLL_PLL_DISABLE)
1946 DRM_ERROR("LCPLL is disabled\n");
1947 }
79f689aa 1948}
c19b0669
PZ		 1949
1950void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1951{
174edf1f
PZ		 1952 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1953 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1954 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1955 enum port port = intel_dig_port->port;
c19b0669 1956 uint32_t val;
f3e227df 1957 bool wait = false;
c19b0669
PZ		 1958
1959 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1960 val = I915_READ(DDI_BUF_CTL(port));
1961 if (val & DDI_BUF_CTL_ENABLE) {
1962 val &= ~DDI_BUF_CTL_ENABLE;
1963 I915_WRITE(DDI_BUF_CTL(port), val);
1964 wait = true;
1965 }
1966
1967 val = I915_READ(DP_TP_CTL(port));
1968 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1969 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1970 I915_WRITE(DP_TP_CTL(port), val);
1971 POSTING_READ(DP_TP_CTL(port));
1972
1973 if (wait)
1974 intel_wait_ddi_buf_idle(dev_priv, port);
1975 }
1976
0e32b39c 1977 val = DP_TP_CTL_ENABLE |
c19b0669 1978 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 1979 if (intel_dp->is_mst)
1980 val |= DP_TP_CTL_MODE_MST;
1981 else {
1982 val |= DP_TP_CTL_MODE_SST;
1983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1984 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1985 }
c19b0669
PZ		 1986 I915_WRITE(DP_TP_CTL(port), val);
1987 POSTING_READ(DP_TP_CTL(port));
1988
1989 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1990 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1991 POSTING_READ(DDI_BUF_CTL(port));
1992
1993 udelay(600);
1994}
00c09d70 1995
1ad960f2
PZ		 1996void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1997{
1998 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1999 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2000 uint32_t val;
2001
2002 intel_ddi_post_disable(intel_encoder);
2003
2004 val = I915_READ(_FDI_RXA_CTL);
2005 val &= ~FDI_RX_ENABLE;
2006 I915_WRITE(_FDI_RXA_CTL, val);
2007
2008 val = I915_READ(_FDI_RXA_MISC);
2009 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2010 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2011 I915_WRITE(_FDI_RXA_MISC, val);
2012
2013 val = I915_READ(_FDI_RXA_CTL);
2014 val &= ~FDI_PCDCLK;
2015 I915_WRITE(_FDI_RXA_CTL, val);
2016
2017 val = I915_READ(_FDI_RXA_CTL);
2018 val &= ~FDI_RX_PLL_ENABLE;
2019 I915_WRITE(_FDI_RXA_CTL, val);
2020}
2021
00c09d70
PZ		 2022static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2023{
0e32b39c
DA		 2024 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2025 int type = intel_dig_port->base.type;
2026
2027 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2028 type != INTEL_OUTPUT_EDP &&
2029 type != INTEL_OUTPUT_UNKNOWN) {
2030 return;
2031 }
00c09d70 2032
0e32b39c 2033 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2034}
2035
6801c18c 2036void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2037 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2038{
2039 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2040 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2041 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2042 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2043 u32 temp, flags = 0;
2044
2045 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2046 if (temp & TRANS_DDI_PHSYNC)
2047 flags |= DRM_MODE_FLAG_PHSYNC;
2048 else
2049 flags |= DRM_MODE_FLAG_NHSYNC;
2050 if (temp & TRANS_DDI_PVSYNC)
2051 flags |= DRM_MODE_FLAG_PVSYNC;
2052 else
2053 flags |= DRM_MODE_FLAG_NVSYNC;
2054
2d112de7 2055 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2056
2057 switch (temp & TRANS_DDI_BPC_MASK) {
2058 case TRANS_DDI_BPC_6:
2059 pipe_config->pipe_bpp = 18;
2060 break;
2061 case TRANS_DDI_BPC_8:
2062 pipe_config->pipe_bpp = 24;
2063 break;
2064 case TRANS_DDI_BPC_10:
2065 pipe_config->pipe_bpp = 30;
2066 break;
2067 case TRANS_DDI_BPC_12:
2068 pipe_config->pipe_bpp = 36;
2069 break;
2070 default:
2071 break;
2072 }
eb14cb74
VS		 2073
2074 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2075 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2076 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2077 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2078
2079 if (intel_hdmi->infoframe_enabled(&encoder->base))
2080 pipe_config->has_infoframe = true;
cbc572a9 2081 break;
eb14cb74
VS		 2082 case TRANS_DDI_MODE_SELECT_DVI:
2083 case TRANS_DDI_MODE_SELECT_FDI:
2084 break;
2085 case TRANS_DDI_MODE_SELECT_DP_SST:
2086 case TRANS_DDI_MODE_SELECT_DP_MST:
2087 pipe_config->has_dp_encoder = true;
2088 intel_dp_get_m_n(intel_crtc, pipe_config);
2089 break;
2090 default:
2091 break;
2092 }
10214420 2093
f458ebbc 2094 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2095 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2096 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2097 pipe_config->has_audio = true;
2098 }
9ed109a7 2099
10214420
DV		 2100 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2101 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2102 /*
2103 * This is a big fat ugly hack.
2104 *
2105 * Some machines in UEFI boot mode provide us a VBT that has 18
2106 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2107 * unknown we fail to light up. Yet the same BIOS boots up with
2108 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2109 * max, not what it tells us to use.
2110 *
2111 * Note: This will still be broken if the eDP panel is not lit
2112 * up by the BIOS, and thus we can't get the mode at module
2113 * load.
2114 */
2115 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2116 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2117 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2118 }
11578553 2119
22606a18 2120 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2121}
2122
00c09d70
PZ		 2123static void intel_ddi_destroy(struct drm_encoder *encoder)
2124{
2125 /* HDMI has nothing special to destroy, so we can go with this. */
2126 intel_dp_encoder_destroy(encoder);
2127}
2128
5bfe2ac0 2129static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2130 struct intel_crtc_state *pipe_config)
00c09d70 2131{
5bfe2ac0 2132 int type = encoder->type;
eccb140b 2133 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2134
5bfe2ac0 2135 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2136
eccb140b
DV		 2137 if (port == PORT_A)
2138 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2139
00c09d70 2140 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2141 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2142 else
5bfe2ac0 2143 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2144}
2145
2146static const struct drm_encoder_funcs intel_ddi_funcs = {
2147 .destroy = intel_ddi_destroy,
2148};
2149
4a28ae58
PZ		 2150static struct intel_connector *
2151intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2152{
2153 struct intel_connector *connector;
2154 enum port port = intel_dig_port->port;
2155
2156 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2157 if (!connector)
2158 return NULL;
2159
2160 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2161 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2162 kfree(connector);
2163 return NULL;
2164 }
2165
2166 return connector;
2167}
2168
2169static struct intel_connector *
2170intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2171{
2172 struct intel_connector *connector;
2173 enum port port = intel_dig_port->port;
2174
2175 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2176 if (!connector)
2177 return NULL;
2178
2179 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2180 intel_hdmi_init_connector(intel_dig_port, connector);
2181
2182 return connector;
2183}
2184
00c09d70
PZ		 2185void intel_ddi_init(struct drm_device *dev, enum port port)
2186{
876a8cdf 2187 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2188 struct intel_digital_port *intel_dig_port;
2189 struct intel_encoder *intel_encoder;
2190 struct drm_encoder *encoder;
311a2094
PZ		 2191 bool init_hdmi, init_dp;
2192
2193 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2194 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2195 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2196 if (!init_dp && !init_hdmi) {
f68d697e 2197 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2198 port_name(port));
2199 init_hdmi = true;
2200 init_dp = true;
2201 }
00c09d70 2202
b14c5679 2203 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2204 if (!intel_dig_port)
2205 return;
2206
00c09d70
PZ		 2207 intel_encoder = &intel_dig_port->base;
2208 encoder = &intel_encoder->base;
2209
2210 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2211 DRM_MODE_ENCODER_TMDS);
00c09d70 2212
5bfe2ac0 2213 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2214 intel_encoder->enable = intel_enable_ddi;
2215 intel_encoder->pre_enable = intel_ddi_pre_enable;
2216 intel_encoder->disable = intel_disable_ddi;
2217 intel_encoder->post_disable = intel_ddi_post_disable;
2218 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2219 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2220
2221 intel_dig_port->port = port;
bcf53de4
SM		 2222 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2223 (DDI_BUF_PORT_REVERSAL |
2224 DDI_A_4_LANES);
00c09d70
PZ		 2225
2226 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2227 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2228 intel_encoder->cloneable = 0;
00c09d70
PZ		 2229 intel_encoder->hot_plug = intel_ddi_hot_plug;
2230
f68d697e
CW		 2231 if (init_dp) {
2232 if (!intel_ddi_init_dp_connector(intel_dig_port))
2233 goto err;
13cf5504 2234
f68d697e
CW		 2235 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2236 dev_priv->hpd_irq_port[port] = intel_dig_port;
2237 }
21a8e6a4 2238
311a2094
PZ		 2239 /* In theory we don't need the encoder->type check, but leave it just in
2240 * case we have some really bad VBTs... */
f68d697e
CW		 2241 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2242 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2243 goto err;
21a8e6a4 2244 }
f68d697e
CW		 2245
2246 return;
2247
2248err:
2249 drm_encoder_cleanup(encoder);
2250 kfree(intel_dig_port);
00c09d70 2251}
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