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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 | 75 | static const u32 bdw_ddi_translations_edp[] = { |
e1b22732 | 76 | 0x00FFFFFF, 0x00000012, /* eDP parameters */ |
300644c7 PZ |
77 | 0x00EBAFFF, 0x00020011, |
78 | 0x00C71FFF, 0x0006000F, | |
9576c27f | 79 | 0x00AAAFFF, 0x000E000A, |
300644c7 PZ |
80 | 0x00FFFFFF, 0x00020011, |
81 | 0x00DB6FFF, 0x0005000F, | |
82 | 0x00BEEFFF, 0x000A000C, | |
83 | 0x00FFFFFF, 0x0005000F, | |
84 | 0x00DB6FFF, 0x000A000C, | |
300644c7 PZ |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
86 | }; | |
87 | ||
e58623cb AR |
88 | static const u32 bdw_ddi_translations_dp[] = { |
89 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
90 | 0x00D75FFF, 0x000E000A, | |
91 | 0x00BEFFFF, 0x00140006, | |
9576c27f | 92 | 0x80B2CFFF, 0x001B0002, |
e58623cb AR |
93 | 0x00FFFFFF, 0x000E000A, |
94 | 0x00D75FFF, 0x00180004, | |
95 | 0x80CB2FFF, 0x001B0002, | |
96 | 0x00F7DFFF, 0x00180004, | |
97 | 0x80D75FFF, 0x001B0002, | |
e58623cb AR |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
99 | }; | |
100 | ||
101 | static const u32 bdw_ddi_translations_fdi[] = { | |
102 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
103 | 0x00D75FFF, 0x0004000A, | |
104 | 0x00C30FFF, 0x00070006, | |
105 | 0x00AAAFFF, 0x000C0000, | |
106 | 0x00FFFFFF, 0x0004000A, | |
107 | 0x00D75FFF, 0x00090004, | |
108 | 0x00C30FFF, 0x000C0000, | |
109 | 0x00FFFFFF, 0x00070006, | |
110 | 0x00D75FFF, 0x000C0000, | |
111 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
112 | }; | |
113 | ||
20f4dbe4 | 114 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 115 | { |
0bdee30e | 116 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
117 | int type = intel_encoder->type; |
118 | ||
0e32b39c DA |
119 | if (type == INTEL_OUTPUT_DP_MST) { |
120 | struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; | |
121 | return intel_dig_port->port; | |
122 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || | |
00c09d70 | 123 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
124 | struct intel_digital_port *intel_dig_port = |
125 | enc_to_dig_port(encoder); | |
126 | return intel_dig_port->port; | |
0bdee30e | 127 | |
fc914639 PZ |
128 | } else if (type == INTEL_OUTPUT_ANALOG) { |
129 | return PORT_E; | |
0bdee30e | 130 | |
fc914639 PZ |
131 | } else { |
132 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
133 | BUG(); | |
134 | } | |
135 | } | |
136 | ||
e58623cb AR |
137 | /* |
138 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
139 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
140 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
141 | * in either FDI or DP modes only, as HDMI connections will work with both | |
142 | * of those | |
143 | */ | |
ad8d270c | 144 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
145 | { |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | u32 reg; | |
148 | int i; | |
6acab15a | 149 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
150 | const u32 *ddi_translations_fdi; |
151 | const u32 *ddi_translations_dp; | |
300644c7 | 152 | const u32 *ddi_translations_edp; |
e58623cb AR |
153 | const u32 *ddi_translations; |
154 | ||
155 | if (IS_BROADWELL(dev)) { | |
156 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
157 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 158 | ddi_translations_edp = bdw_ddi_translations_edp; |
e58623cb AR |
159 | } else if (IS_HASWELL(dev)) { |
160 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
161 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 162 | ddi_translations_edp = hsw_ddi_translations_dp; |
e58623cb AR |
163 | } else { |
164 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 165 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
166 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
167 | ddi_translations_dp = bdw_ddi_translations_dp; | |
168 | } | |
169 | ||
300644c7 PZ |
170 | switch (port) { |
171 | case PORT_A: | |
172 | ddi_translations = ddi_translations_edp; | |
173 | break; | |
174 | case PORT_B: | |
175 | case PORT_C: | |
300644c7 PZ |
176 | ddi_translations = ddi_translations_dp; |
177 | break; | |
77d8d009 | 178 | case PORT_D: |
5d8a7752 | 179 | if (intel_dp_is_edp(dev, PORT_D)) |
77d8d009 PZ |
180 | ddi_translations = ddi_translations_edp; |
181 | else | |
182 | ddi_translations = ddi_translations_dp; | |
183 | break; | |
300644c7 PZ |
184 | case PORT_E: |
185 | ddi_translations = ddi_translations_fdi; | |
186 | break; | |
187 | default: | |
188 | BUG(); | |
189 | } | |
45244b87 | 190 | |
f72d19f0 PZ |
191 | for (i = 0, reg = DDI_BUF_TRANS(port); |
192 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
193 | I915_WRITE(reg, ddi_translations[i]); |
194 | reg += 4; | |
195 | } | |
6acab15a PZ |
196 | /* Entry 9 is for HDMI: */ |
197 | for (i = 0; i < 2; i++) { | |
198 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
199 | reg += 4; | |
200 | } | |
45244b87 ED |
201 | } |
202 | ||
203 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
204 | * mode and port E for FDI. | |
205 | */ | |
206 | void intel_prepare_ddi(struct drm_device *dev) | |
207 | { | |
208 | int port; | |
209 | ||
0d536cb4 PZ |
210 | if (!HAS_DDI(dev)) |
211 | return; | |
45244b87 | 212 | |
ad8d270c PZ |
213 | for (port = PORT_A; port <= PORT_E; port++) |
214 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 215 | } |
c82e4d26 ED |
216 | |
217 | static const long hsw_ddi_buf_ctl_values[] = { | |
218 | DDI_BUF_EMP_400MV_0DB_HSW, | |
219 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
220 | DDI_BUF_EMP_400MV_6DB_HSW, | |
221 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
222 | DDI_BUF_EMP_600MV_0DB_HSW, | |
223 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
224 | DDI_BUF_EMP_600MV_6DB_HSW, | |
225 | DDI_BUF_EMP_800MV_0DB_HSW, | |
226 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
227 | }; | |
228 | ||
248138b5 PZ |
229 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
230 | enum port port) | |
231 | { | |
232 | uint32_t reg = DDI_BUF_CTL(port); | |
233 | int i; | |
234 | ||
235 | for (i = 0; i < 8; i++) { | |
236 | udelay(1); | |
237 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
238 | return; | |
239 | } | |
240 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
241 | } | |
c82e4d26 ED |
242 | |
243 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
244 | * connection to the PCH-located connectors. For this, it is necessary to train | |
245 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
246 | * | |
247 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
248 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
249 | * DDI A (which is used for eDP) | |
250 | */ | |
251 | ||
252 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
253 | { | |
254 | struct drm_device *dev = crtc->dev; | |
255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 257 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 258 | |
04945641 PZ |
259 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
260 | * mode set "sequence for CRT port" document: | |
261 | * - TP1 to TP2 time with the default value | |
262 | * - FDI delay to 90h | |
8693a824 DL |
263 | * |
264 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
265 | */ |
266 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
267 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
268 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
269 | ||
270 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 271 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 272 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 273 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
274 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
275 | POSTING_READ(_FDI_RXA_CTL); | |
276 | udelay(220); | |
277 | ||
278 | /* Switch from Rawclk to PCDclk */ | |
279 | rx_ctl_val |= FDI_PCDCLK; | |
280 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
281 | ||
282 | /* Configure Port Clock Select */ | |
de7cfc63 DV |
283 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); |
284 | WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
285 | |
286 | /* Start the training iterating through available voltages and emphasis, | |
287 | * testing each value twice. */ | |
288 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
289 | /* Configure DP_TP_CTL with auto-training */ |
290 | I915_WRITE(DP_TP_CTL(PORT_E), | |
291 | DP_TP_CTL_FDI_AUTOTRAIN | | |
292 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
293 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
294 | DP_TP_CTL_ENABLE); | |
295 | ||
876a8cdf DL |
296 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
297 | * DDI E does not support port reversal, the functionality is | |
298 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
299 | * port reversal bit */ | |
c82e4d26 | 300 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 301 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 302 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
303 | hsw_ddi_buf_ctl_values[i / 2]); |
304 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
305 | |
306 | udelay(600); | |
307 | ||
04945641 PZ |
308 | /* Program PCH FDI Receiver TU */ |
309 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
310 | ||
311 | /* Enable PCH FDI Receiver with auto-training */ | |
312 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
313 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
314 | POSTING_READ(_FDI_RXA_CTL); | |
315 | ||
316 | /* Wait for FDI receiver lane calibration */ | |
317 | udelay(30); | |
318 | ||
319 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
320 | temp = I915_READ(_FDI_RXA_MISC); | |
321 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
322 | I915_WRITE(_FDI_RXA_MISC, temp); | |
323 | POSTING_READ(_FDI_RXA_MISC); | |
324 | ||
325 | /* Wait for FDI auto training time */ | |
326 | udelay(5); | |
c82e4d26 ED |
327 | |
328 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
329 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 330 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
331 | |
332 | /* Enable normal pixel sending for FDI */ | |
333 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
334 | DP_TP_CTL_FDI_AUTOTRAIN | |
335 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
336 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
337 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 338 | |
04945641 | 339 | return; |
c82e4d26 | 340 | } |
04945641 | 341 | |
248138b5 PZ |
342 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
343 | temp &= ~DDI_BUF_CTL_ENABLE; | |
344 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
345 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
346 | ||
04945641 | 347 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
348 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
349 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
350 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
351 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
352 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
353 | ||
354 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
355 | |
356 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
357 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 358 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
359 | |
360 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
361 | temp = I915_READ(_FDI_RXA_MISC); | |
362 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
363 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
364 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 365 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
366 | } |
367 | ||
04945641 | 368 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 369 | } |
0e72a5b5 | 370 | |
44905a27 DA |
371 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
372 | { | |
373 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
374 | struct intel_digital_port *intel_dig_port = | |
375 | enc_to_dig_port(&encoder->base); | |
376 | ||
377 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
378 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | |
379 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
380 | ||
381 | } | |
382 | ||
8d9ddbcb PZ |
383 | static struct intel_encoder * |
384 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
385 | { | |
386 | struct drm_device *dev = crtc->dev; | |
387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
388 | struct intel_encoder *intel_encoder, *ret = NULL; | |
389 | int num_encoders = 0; | |
390 | ||
391 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
392 | ret = intel_encoder; | |
393 | num_encoders++; | |
394 | } | |
395 | ||
396 | if (num_encoders != 1) | |
84f44ce7 VS |
397 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
398 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
399 | |
400 | BUG_ON(ret == NULL); | |
401 | return ret; | |
402 | } | |
403 | ||
1c0b85c5 DL |
404 | #define LC_FREQ 2700 |
405 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
406 | ||
407 | #define P_MIN 2 | |
408 | #define P_MAX 64 | |
409 | #define P_INC 2 | |
410 | ||
411 | /* Constraints for PLL good behavior */ | |
412 | #define REF_MIN 48 | |
413 | #define REF_MAX 400 | |
414 | #define VCO_MIN 2400 | |
415 | #define VCO_MAX 4800 | |
416 | ||
417 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
418 | ||
419 | struct wrpll_rnp { | |
420 | unsigned p, n2, r2; | |
421 | }; | |
422 | ||
423 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 424 | { |
1c0b85c5 DL |
425 | unsigned budget; |
426 | ||
427 | switch (clock) { | |
428 | case 25175000: | |
429 | case 25200000: | |
430 | case 27000000: | |
431 | case 27027000: | |
432 | case 37762500: | |
433 | case 37800000: | |
434 | case 40500000: | |
435 | case 40541000: | |
436 | case 54000000: | |
437 | case 54054000: | |
438 | case 59341000: | |
439 | case 59400000: | |
440 | case 72000000: | |
441 | case 74176000: | |
442 | case 74250000: | |
443 | case 81000000: | |
444 | case 81081000: | |
445 | case 89012000: | |
446 | case 89100000: | |
447 | case 108000000: | |
448 | case 108108000: | |
449 | case 111264000: | |
450 | case 111375000: | |
451 | case 148352000: | |
452 | case 148500000: | |
453 | case 162000000: | |
454 | case 162162000: | |
455 | case 222525000: | |
456 | case 222750000: | |
457 | case 296703000: | |
458 | case 297000000: | |
459 | budget = 0; | |
460 | break; | |
461 | case 233500000: | |
462 | case 245250000: | |
463 | case 247750000: | |
464 | case 253250000: | |
465 | case 298000000: | |
466 | budget = 1500; | |
467 | break; | |
468 | case 169128000: | |
469 | case 169500000: | |
470 | case 179500000: | |
471 | case 202000000: | |
472 | budget = 2000; | |
473 | break; | |
474 | case 256250000: | |
475 | case 262500000: | |
476 | case 270000000: | |
477 | case 272500000: | |
478 | case 273750000: | |
479 | case 280750000: | |
480 | case 281250000: | |
481 | case 286000000: | |
482 | case 291750000: | |
483 | budget = 4000; | |
484 | break; | |
485 | case 267250000: | |
486 | case 268500000: | |
487 | budget = 5000; | |
488 | break; | |
489 | default: | |
490 | budget = 1000; | |
491 | break; | |
492 | } | |
6441ab5f | 493 | |
1c0b85c5 DL |
494 | return budget; |
495 | } | |
496 | ||
497 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
498 | unsigned r2, unsigned n2, unsigned p, | |
499 | struct wrpll_rnp *best) | |
500 | { | |
501 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 502 | |
1c0b85c5 DL |
503 | /* No best (r,n,p) yet */ |
504 | if (best->p == 0) { | |
505 | best->p = p; | |
506 | best->n2 = n2; | |
507 | best->r2 = r2; | |
508 | return; | |
509 | } | |
6441ab5f | 510 | |
1c0b85c5 DL |
511 | /* |
512 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
513 | * freq2k. | |
514 | * | |
515 | * delta = 1e6 * | |
516 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
517 | * freq2k; | |
518 | * | |
519 | * and we would like delta <= budget. | |
520 | * | |
521 | * If the discrepancy is above the PPM-based budget, always prefer to | |
522 | * improve upon the previous solution. However, if you're within the | |
523 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
524 | */ | |
525 | a = freq2k * budget * p * r2; | |
526 | b = freq2k * budget * best->p * best->r2; | |
527 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
528 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
529 | (LC_FREQ_2K * best->n2)); | |
530 | c = 1000000 * diff; | |
531 | d = 1000000 * diff_best; | |
532 | ||
533 | if (a < c && b < d) { | |
534 | /* If both are above the budget, pick the closer */ | |
535 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
536 | best->p = p; | |
537 | best->n2 = n2; | |
538 | best->r2 = r2; | |
539 | } | |
540 | } else if (a >= c && b < d) { | |
541 | /* If A is below the threshold but B is above it? Update. */ | |
542 | best->p = p; | |
543 | best->n2 = n2; | |
544 | best->r2 = r2; | |
545 | } else if (a >= c && b >= d) { | |
546 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
547 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
548 | best->p = p; | |
549 | best->n2 = n2; | |
550 | best->r2 = r2; | |
551 | } | |
552 | } | |
553 | /* Otherwise a < c && b >= d, do nothing */ | |
554 | } | |
555 | ||
11578553 JB |
556 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
557 | int reg) | |
558 | { | |
559 | int refclk = LC_FREQ; | |
560 | int n, p, r; | |
561 | u32 wrpll; | |
562 | ||
563 | wrpll = I915_READ(reg); | |
114fe488 DV |
564 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
565 | case WRPLL_PLL_SSC: | |
566 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
567 | /* |
568 | * We could calculate spread here, but our checking | |
569 | * code only cares about 5% accuracy, and spread is a max of | |
570 | * 0.5% downspread. | |
571 | */ | |
572 | refclk = 135; | |
573 | break; | |
114fe488 | 574 | case WRPLL_PLL_LCPLL: |
11578553 JB |
575 | refclk = LC_FREQ; |
576 | break; | |
577 | default: | |
578 | WARN(1, "bad wrpll refclk\n"); | |
579 | return 0; | |
580 | } | |
581 | ||
582 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
583 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
584 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
585 | ||
20f0ec16 JB |
586 | /* Convert to KHz, p & r have a fixed point portion */ |
587 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
588 | } |
589 | ||
0e32b39c DA |
590 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
591 | struct intel_crtc_config *pipe_config) | |
11578553 JB |
592 | { |
593 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
594 | int link_clock = 0; |
595 | u32 val, pll; | |
596 | ||
26804afd | 597 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
598 | switch (val & PORT_CLK_SEL_MASK) { |
599 | case PORT_CLK_SEL_LCPLL_810: | |
600 | link_clock = 81000; | |
601 | break; | |
602 | case PORT_CLK_SEL_LCPLL_1350: | |
603 | link_clock = 135000; | |
604 | break; | |
605 | case PORT_CLK_SEL_LCPLL_2700: | |
606 | link_clock = 270000; | |
607 | break; | |
608 | case PORT_CLK_SEL_WRPLL1: | |
609 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
610 | break; | |
611 | case PORT_CLK_SEL_WRPLL2: | |
612 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
613 | break; | |
614 | case PORT_CLK_SEL_SPLL: | |
615 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
616 | if (pll == SPLL_PLL_FREQ_810MHz) | |
617 | link_clock = 81000; | |
618 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
619 | link_clock = 135000; | |
620 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
621 | link_clock = 270000; | |
622 | else { | |
623 | WARN(1, "bad spll freq\n"); | |
624 | return; | |
625 | } | |
626 | break; | |
627 | default: | |
628 | WARN(1, "bad port clock sel\n"); | |
629 | return; | |
630 | } | |
631 | ||
632 | pipe_config->port_clock = link_clock * 2; | |
633 | ||
634 | if (pipe_config->has_pch_encoder) | |
635 | pipe_config->adjusted_mode.crtc_clock = | |
636 | intel_dotclock_calculate(pipe_config->port_clock, | |
637 | &pipe_config->fdi_m_n); | |
638 | else if (pipe_config->has_dp_encoder) | |
639 | pipe_config->adjusted_mode.crtc_clock = | |
640 | intel_dotclock_calculate(pipe_config->port_clock, | |
641 | &pipe_config->dp_m_n); | |
642 | else | |
643 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
644 | } | |
645 | ||
1c0b85c5 DL |
646 | static void |
647 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
648 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
649 | { | |
650 | uint64_t freq2k; | |
651 | unsigned p, n2, r2; | |
652 | struct wrpll_rnp best = { 0, 0, 0 }; | |
653 | unsigned budget; | |
654 | ||
655 | freq2k = clock / 100; | |
656 | ||
657 | budget = wrpll_get_budget_for_freq(clock); | |
658 | ||
659 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
660 | * and directly pass the LC PLL to it. */ | |
661 | if (freq2k == 5400000) { | |
662 | *n2_out = 2; | |
663 | *p_out = 1; | |
664 | *r2_out = 2; | |
665 | return; | |
666 | } | |
667 | ||
668 | /* | |
669 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
670 | * the WR PLL. | |
671 | * | |
672 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
673 | * Injecting R2 = 2 * R gives: | |
674 | * REF_MAX * r2 > LC_FREQ * 2 and | |
675 | * REF_MIN * r2 < LC_FREQ * 2 | |
676 | * | |
677 | * Which means the desired boundaries for r2 are: | |
678 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
679 | * | |
680 | */ | |
681 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
682 | r2 <= LC_FREQ * 2 / REF_MIN; | |
683 | r2++) { | |
684 | ||
685 | /* | |
686 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
687 | * | |
688 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
689 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
690 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
691 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
692 | * | |
693 | * Which means the desired boundaries for n2 are: | |
694 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
695 | */ | |
696 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
697 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
698 | n2++) { | |
699 | ||
700 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
701 | wrpll_update_rnp(freq2k, budget, | |
702 | r2, n2, p, &best); | |
703 | } | |
704 | } | |
6441ab5f | 705 | |
1c0b85c5 DL |
706 | *n2_out = best.n2; |
707 | *p_out = best.p; | |
708 | *r2_out = best.r2; | |
6441ab5f PZ |
709 | } |
710 | ||
0220ab6e DL |
711 | static bool |
712 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, int output, int clock) | |
6441ab5f | 713 | { |
0220ab6e | 714 | if (output == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 715 | struct intel_shared_dpll *pll; |
716c2e55 | 716 | uint32_t val; |
1c0b85c5 | 717 | unsigned p, n2, r2; |
6441ab5f | 718 | |
0694001b PZ |
719 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
720 | ||
114fe488 | 721 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
722 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
723 | WRPLL_DIVIDER_POST(p); | |
724 | ||
716c2e55 | 725 | intel_crtc->config.dpll_hw_state.wrpll = val; |
6441ab5f | 726 | |
716c2e55 DV |
727 | pll = intel_get_shared_dpll(intel_crtc); |
728 | if (pll == NULL) { | |
729 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
730 | pipe_name(intel_crtc->pipe)); | |
731 | return false; | |
0694001b | 732 | } |
d452c5b6 | 733 | |
716c2e55 | 734 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
6441ab5f PZ |
735 | } |
736 | ||
6441ab5f PZ |
737 | return true; |
738 | } | |
739 | ||
0220ab6e DL |
740 | |
741 | /* | |
742 | * Tries to find a *shared* PLL for the CRTC and store it in | |
743 | * intel_crtc->ddi_pll_sel. | |
744 | * | |
745 | * For private DPLLs, compute_config() should do the selection for us. This | |
746 | * function should be folded into compute_config() eventually. | |
747 | */ | |
748 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
749 | { | |
750 | struct drm_crtc *crtc = &intel_crtc->base; | |
751 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
752 | int type = intel_encoder->type; | |
753 | int clock = intel_crtc->config.port_clock; | |
754 | ||
755 | intel_put_shared_dpll(intel_crtc); | |
756 | ||
757 | return hsw_ddi_pll_select(intel_crtc, type, clock); | |
758 | } | |
759 | ||
dae84799 PZ |
760 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
761 | { | |
762 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
764 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 765 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
766 | int type = intel_encoder->type; |
767 | uint32_t temp; | |
768 | ||
0e32b39c | 769 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
c9809791 | 770 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 771 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 772 | case 18: |
c9809791 | 773 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
774 | break; |
775 | case 24: | |
c9809791 | 776 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
777 | break; |
778 | case 30: | |
c9809791 | 779 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
780 | break; |
781 | case 36: | |
c9809791 | 782 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
783 | break; |
784 | default: | |
4e53c2e0 | 785 | BUG(); |
dae84799 | 786 | } |
c9809791 | 787 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
788 | } |
789 | } | |
790 | ||
0e32b39c DA |
791 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
792 | { | |
793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
794 | struct drm_device *dev = crtc->dev; | |
795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
796 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
797 | uint32_t temp; | |
798 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
799 | if (state == true) | |
800 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
801 | else | |
802 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
803 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
804 | } | |
805 | ||
8228c251 | 806 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
807 | { |
808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
809 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 810 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
811 | struct drm_device *dev = crtc->dev; |
812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 813 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 814 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 815 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 816 | int type = intel_encoder->type; |
8d9ddbcb PZ |
817 | uint32_t temp; |
818 | ||
ad80a810 PZ |
819 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
820 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 821 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 822 | |
965e0c48 | 823 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 824 | case 18: |
ad80a810 | 825 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
826 | break; |
827 | case 24: | |
ad80a810 | 828 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
829 | break; |
830 | case 30: | |
ad80a810 | 831 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
832 | break; |
833 | case 36: | |
ad80a810 | 834 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
835 | break; |
836 | default: | |
4e53c2e0 | 837 | BUG(); |
dfcef252 | 838 | } |
72662e10 | 839 | |
a666283e | 840 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 841 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 842 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 843 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 844 | |
e6f0bfc4 PZ |
845 | if (cpu_transcoder == TRANSCODER_EDP) { |
846 | switch (pipe) { | |
847 | case PIPE_A: | |
c7670b10 PZ |
848 | /* On Haswell, can only use the always-on power well for |
849 | * eDP when not using the panel fitter, and when not | |
850 | * using motion blur mitigation (which we don't | |
851 | * support). */ | |
fabf6e51 DV |
852 | if (IS_HASWELL(dev) && |
853 | (intel_crtc->config.pch_pfit.enabled || | |
854 | intel_crtc->config.pch_pfit.force_thru)) | |
d6dd9eb1 DV |
855 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
856 | else | |
857 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
858 | break; |
859 | case PIPE_B: | |
860 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
861 | break; | |
862 | case PIPE_C: | |
863 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
864 | break; | |
865 | default: | |
866 | BUG(); | |
867 | break; | |
868 | } | |
869 | } | |
870 | ||
7739c33b | 871 | if (type == INTEL_OUTPUT_HDMI) { |
6897b4b5 | 872 | if (intel_crtc->config.has_hdmi_sink) |
ad80a810 | 873 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 874 | else |
ad80a810 | 875 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 876 | |
7739c33b | 877 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 878 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 879 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
880 | |
881 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
882 | type == INTEL_OUTPUT_EDP) { | |
883 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
884 | ||
0e32b39c DA |
885 | if (intel_dp->is_mst) { |
886 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
887 | } else | |
888 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
889 | ||
890 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
891 | } else if (type == INTEL_OUTPUT_DP_MST) { | |
892 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; | |
893 | ||
894 | if (intel_dp->is_mst) { | |
895 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
896 | } else | |
897 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
7739c33b | 898 | |
17aa6be9 | 899 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 900 | } else { |
84f44ce7 VS |
901 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
902 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
903 | } |
904 | ||
ad80a810 | 905 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 906 | } |
72662e10 | 907 | |
ad80a810 PZ |
908 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
909 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 910 | { |
ad80a810 | 911 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
912 | uint32_t val = I915_READ(reg); |
913 | ||
0e32b39c | 914 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 915 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 916 | I915_WRITE(reg, val); |
72662e10 ED |
917 | } |
918 | ||
bcbc889b PZ |
919 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
920 | { | |
921 | struct drm_device *dev = intel_connector->base.dev; | |
922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
923 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
924 | int type = intel_connector->base.connector_type; | |
925 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
926 | enum pipe pipe = 0; | |
927 | enum transcoder cpu_transcoder; | |
882244a3 | 928 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
929 | uint32_t tmp; |
930 | ||
882244a3 PZ |
931 | power_domain = intel_display_port_power_domain(intel_encoder); |
932 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
933 | return false; | |
934 | ||
bcbc889b PZ |
935 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
936 | return false; | |
937 | ||
938 | if (port == PORT_A) | |
939 | cpu_transcoder = TRANSCODER_EDP; | |
940 | else | |
1a240d4d | 941 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
942 | |
943 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
944 | ||
945 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
946 | case TRANS_DDI_MODE_SELECT_HDMI: | |
947 | case TRANS_DDI_MODE_SELECT_DVI: | |
948 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
949 | ||
950 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
951 | if (type == DRM_MODE_CONNECTOR_eDP) | |
952 | return true; | |
bcbc889b | 953 | return (type == DRM_MODE_CONNECTOR_DisplayPort); |
0e32b39c DA |
954 | case TRANS_DDI_MODE_SELECT_DP_MST: |
955 | /* if the transcoder is in MST state then | |
956 | * connector isn't connected */ | |
957 | return false; | |
bcbc889b PZ |
958 | |
959 | case TRANS_DDI_MODE_SELECT_FDI: | |
960 | return (type == DRM_MODE_CONNECTOR_VGA); | |
961 | ||
962 | default: | |
963 | return false; | |
964 | } | |
965 | } | |
966 | ||
85234cdc DV |
967 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
968 | enum pipe *pipe) | |
969 | { | |
970 | struct drm_device *dev = encoder->base.dev; | |
971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 972 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 973 | enum intel_display_power_domain power_domain; |
85234cdc DV |
974 | u32 tmp; |
975 | int i; | |
976 | ||
6d129bea ID |
977 | power_domain = intel_display_port_power_domain(encoder); |
978 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
979 | return false; | |
980 | ||
fe43d3f5 | 981 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
982 | |
983 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
984 | return false; | |
985 | ||
ad80a810 PZ |
986 | if (port == PORT_A) { |
987 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 988 | |
ad80a810 PZ |
989 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
990 | case TRANS_DDI_EDP_INPUT_A_ON: | |
991 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
992 | *pipe = PIPE_A; | |
993 | break; | |
994 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
995 | *pipe = PIPE_B; | |
996 | break; | |
997 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
998 | *pipe = PIPE_C; | |
999 | break; | |
1000 | } | |
1001 | ||
1002 | return true; | |
1003 | } else { | |
1004 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1005 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1006 | ||
1007 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1008 | == TRANS_DDI_SELECT_PORT(port)) { | |
0e32b39c DA |
1009 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
1010 | return false; | |
1011 | ||
ad80a810 PZ |
1012 | *pipe = i; |
1013 | return true; | |
1014 | } | |
85234cdc DV |
1015 | } |
1016 | } | |
1017 | ||
84f44ce7 | 1018 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1019 | |
22f9fe50 | 1020 | return false; |
85234cdc DV |
1021 | } |
1022 | ||
fc914639 PZ |
1023 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1024 | { | |
1025 | struct drm_crtc *crtc = &intel_crtc->base; | |
1026 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1027 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1028 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1029 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1030 | |
bb523fc0 PZ |
1031 | if (cpu_transcoder != TRANSCODER_EDP) |
1032 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1033 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1034 | } |
1035 | ||
1036 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1037 | { | |
1038 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1039 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1040 | |
bb523fc0 PZ |
1041 | if (cpu_transcoder != TRANSCODER_EDP) |
1042 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1043 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1044 | } |
1045 | ||
00c09d70 | 1046 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1047 | { |
c19b0669 | 1048 | struct drm_encoder *encoder = &intel_encoder->base; |
c19b0669 | 1049 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
30cf6db8 | 1050 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1051 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1052 | int type = intel_encoder->type; |
6441ab5f | 1053 | |
30cf6db8 DV |
1054 | if (crtc->config.has_audio) { |
1055 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1056 | pipe_name(crtc->pipe)); | |
1057 | ||
1058 | /* write eld */ | |
1059 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1060 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1061 | } | |
1062 | ||
82a4d9c0 PZ |
1063 | if (type == INTEL_OUTPUT_EDP) { |
1064 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1065 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1066 | } |
6441ab5f | 1067 | |
de7cfc63 DV |
1068 | WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); |
1069 | I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); | |
c19b0669 | 1070 | |
82a4d9c0 | 1071 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1072 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1073 | |
44905a27 | 1074 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1075 | |
1076 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1077 | intel_dp_start_link_train(intel_dp); | |
1078 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1079 | if (port != PORT_A) |
1080 | intel_dp_stop_link_train(intel_dp); | |
30cf6db8 DV |
1081 | } else if (type == INTEL_OUTPUT_HDMI) { |
1082 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1083 | ||
1084 | intel_hdmi->set_infoframes(encoder, | |
1085 | crtc->config.has_hdmi_sink, | |
1086 | &crtc->config.adjusted_mode); | |
c19b0669 | 1087 | } |
6441ab5f PZ |
1088 | } |
1089 | ||
00c09d70 | 1090 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1091 | { |
1092 | struct drm_encoder *encoder = &intel_encoder->base; | |
1093 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1094 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1095 | int type = intel_encoder->type; |
2886e93f | 1096 | uint32_t val; |
a836bdf9 | 1097 | bool wait = false; |
2886e93f PZ |
1098 | |
1099 | val = I915_READ(DDI_BUF_CTL(port)); | |
1100 | if (val & DDI_BUF_CTL_ENABLE) { | |
1101 | val &= ~DDI_BUF_CTL_ENABLE; | |
1102 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1103 | wait = true; |
2886e93f | 1104 | } |
6441ab5f | 1105 | |
a836bdf9 PZ |
1106 | val = I915_READ(DP_TP_CTL(port)); |
1107 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1108 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1109 | I915_WRITE(DP_TP_CTL(port), val); | |
1110 | ||
1111 | if (wait) | |
1112 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1113 | ||
76bb80ed | 1114 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1115 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1116 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1117 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1118 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1119 | } |
1120 | ||
6441ab5f PZ |
1121 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1122 | } | |
1123 | ||
00c09d70 | 1124 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1125 | { |
6547fef8 | 1126 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1127 | struct drm_crtc *crtc = encoder->crtc; |
1128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1129 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1130 | struct drm_device *dev = encoder->dev; |
72662e10 | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1132 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1133 | int type = intel_encoder->type; | |
7b9f35a6 | 1134 | uint32_t tmp; |
72662e10 | 1135 | |
6547fef8 | 1136 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1137 | struct intel_digital_port *intel_dig_port = |
1138 | enc_to_dig_port(encoder); | |
1139 | ||
6547fef8 PZ |
1140 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1141 | * are ignored so nothing special needs to be done besides | |
1142 | * enabling the port. | |
1143 | */ | |
876a8cdf | 1144 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1145 | intel_dig_port->saved_port_bits | |
1146 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1147 | } else if (type == INTEL_OUTPUT_EDP) { |
1148 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1149 | ||
3ab9c637 ID |
1150 | if (port == PORT_A) |
1151 | intel_dp_stop_link_train(intel_dp); | |
1152 | ||
4be73780 | 1153 | intel_edp_backlight_on(intel_dp); |
4906557e | 1154 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1155 | } |
7b9f35a6 | 1156 | |
9ed109a7 | 1157 | if (intel_crtc->config.has_audio) { |
d45a0bf5 | 1158 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
7b9f35a6 WX |
1159 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1160 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1161 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1162 | } | |
5ab432ef DV |
1163 | } |
1164 | ||
00c09d70 | 1165 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1166 | { |
d6c50ff8 | 1167 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1168 | struct drm_crtc *crtc = encoder->crtc; |
1169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1170 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1171 | int type = intel_encoder->type; |
7b9f35a6 WX |
1172 | struct drm_device *dev = encoder->dev; |
1173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1174 | uint32_t tmp; | |
d6c50ff8 | 1175 | |
d45a0bf5 PZ |
1176 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1177 | * register is part of the power well on Haswell. */ | |
1178 | if (intel_crtc->config.has_audio) { | |
1179 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1180 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1181 | (pipe * 4)); | |
1182 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1183 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
1184 | } | |
2831d842 | 1185 | |
d6c50ff8 PZ |
1186 | if (type == INTEL_OUTPUT_EDP) { |
1187 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1188 | ||
4906557e | 1189 | intel_edp_psr_disable(intel_dp); |
4be73780 | 1190 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1191 | } |
72662e10 | 1192 | } |
79f689aa | 1193 | |
b8fc2f6a | 1194 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1195 | { |
e39bf98a | 1196 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1197 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1198 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1199 | |
e39bf98a | 1200 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1201 | return 800000; |
e3589908 | 1202 | } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1203 | return 450000; |
e39bf98a | 1204 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1205 | return 450000; |
e39bf98a PZ |
1206 | } else if (IS_HASWELL(dev)) { |
1207 | if (IS_ULT(dev)) | |
1208 | return 337500; | |
1209 | else | |
1210 | return 540000; | |
1211 | } else { | |
1212 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1213 | return 540000; | |
1214 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1215 | return 337500; | |
1216 | else | |
1217 | return 675000; | |
1218 | } | |
79f689aa PZ |
1219 | } |
1220 | ||
e0b01be4 DV |
1221 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
1222 | struct intel_shared_dpll *pll) | |
1223 | { | |
e0b01be4 DV |
1224 | I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll); |
1225 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1226 | udelay(20); | |
1227 | } | |
1228 | ||
12030431 DV |
1229 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
1230 | struct intel_shared_dpll *pll) | |
1231 | { | |
1232 | uint32_t val; | |
1233 | ||
1234 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
1235 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
1236 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1237 | } | |
1238 | ||
d452c5b6 DV |
1239 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
1240 | struct intel_shared_dpll *pll, | |
1241 | struct intel_dpll_hw_state *hw_state) | |
1242 | { | |
1243 | uint32_t val; | |
1244 | ||
1245 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
1246 | return false; | |
1247 | ||
1248 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1249 | hw_state->wrpll = val; | |
1250 | ||
1251 | return val & WRPLL_PLL_ENABLE; | |
1252 | } | |
1253 | ||
ca1381b5 | 1254 | static const char * const hsw_ddi_pll_names[] = { |
9cd86933 DV |
1255 | "WRPLL 1", |
1256 | "WRPLL 2", | |
1257 | }; | |
1258 | ||
143b307c | 1259 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
79f689aa | 1260 | { |
9cd86933 DV |
1261 | int i; |
1262 | ||
716c2e55 | 1263 | dev_priv->num_shared_dpll = 2; |
9cd86933 | 1264 | |
716c2e55 | 1265 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9cd86933 DV |
1266 | dev_priv->shared_dplls[i].id = i; |
1267 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
12030431 | 1268 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
e0b01be4 | 1269 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
d452c5b6 DV |
1270 | dev_priv->shared_dplls[i].get_hw_state = |
1271 | hsw_ddi_pll_get_hw_state; | |
9cd86933 | 1272 | } |
143b307c DL |
1273 | } |
1274 | ||
1275 | void intel_ddi_pll_init(struct drm_device *dev) | |
1276 | { | |
1277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1278 | uint32_t val = I915_READ(LCPLL_CTL); | |
1279 | ||
1280 | hsw_shared_dplls_init(dev_priv); | |
79f689aa PZ |
1281 | |
1282 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1283 | * just check its state and print errors in case something is wrong. | |
1284 | * Don't even try to turn it on. | |
1285 | */ | |
1286 | ||
b2b877ff | 1287 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1288 | intel_ddi_get_cdclk_freq(dev_priv)); |
1289 | ||
1290 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1291 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1292 | ||
1293 | if (val & LCPLL_PLL_DISABLE) | |
1294 | DRM_ERROR("LCPLL is disabled\n"); | |
1295 | } | |
c19b0669 PZ |
1296 | |
1297 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1298 | { | |
174edf1f PZ |
1299 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1300 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1301 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1302 | enum port port = intel_dig_port->port; |
c19b0669 | 1303 | uint32_t val; |
f3e227df | 1304 | bool wait = false; |
c19b0669 PZ |
1305 | |
1306 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1307 | val = I915_READ(DDI_BUF_CTL(port)); | |
1308 | if (val & DDI_BUF_CTL_ENABLE) { | |
1309 | val &= ~DDI_BUF_CTL_ENABLE; | |
1310 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1311 | wait = true; | |
1312 | } | |
1313 | ||
1314 | val = I915_READ(DP_TP_CTL(port)); | |
1315 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1316 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1317 | I915_WRITE(DP_TP_CTL(port), val); | |
1318 | POSTING_READ(DP_TP_CTL(port)); | |
1319 | ||
1320 | if (wait) | |
1321 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1322 | } | |
1323 | ||
0e32b39c | 1324 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 1325 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
0e32b39c DA |
1326 | if (intel_dp->is_mst) |
1327 | val |= DP_TP_CTL_MODE_MST; | |
1328 | else { | |
1329 | val |= DP_TP_CTL_MODE_SST; | |
1330 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1331 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1332 | } | |
c19b0669 PZ |
1333 | I915_WRITE(DP_TP_CTL(port), val); |
1334 | POSTING_READ(DP_TP_CTL(port)); | |
1335 | ||
1336 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1337 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1338 | POSTING_READ(DDI_BUF_CTL(port)); | |
1339 | ||
1340 | udelay(600); | |
1341 | } | |
00c09d70 | 1342 | |
1ad960f2 PZ |
1343 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1344 | { | |
1345 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1346 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1347 | uint32_t val; | |
1348 | ||
1349 | intel_ddi_post_disable(intel_encoder); | |
1350 | ||
1351 | val = I915_READ(_FDI_RXA_CTL); | |
1352 | val &= ~FDI_RX_ENABLE; | |
1353 | I915_WRITE(_FDI_RXA_CTL, val); | |
1354 | ||
1355 | val = I915_READ(_FDI_RXA_MISC); | |
1356 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1357 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1358 | I915_WRITE(_FDI_RXA_MISC, val); | |
1359 | ||
1360 | val = I915_READ(_FDI_RXA_CTL); | |
1361 | val &= ~FDI_PCDCLK; | |
1362 | I915_WRITE(_FDI_RXA_CTL, val); | |
1363 | ||
1364 | val = I915_READ(_FDI_RXA_CTL); | |
1365 | val &= ~FDI_RX_PLL_ENABLE; | |
1366 | I915_WRITE(_FDI_RXA_CTL, val); | |
1367 | } | |
1368 | ||
00c09d70 PZ |
1369 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1370 | { | |
0e32b39c DA |
1371 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
1372 | int type = intel_dig_port->base.type; | |
1373 | ||
1374 | if (type != INTEL_OUTPUT_DISPLAYPORT && | |
1375 | type != INTEL_OUTPUT_EDP && | |
1376 | type != INTEL_OUTPUT_UNKNOWN) { | |
1377 | return; | |
1378 | } | |
00c09d70 | 1379 | |
0e32b39c | 1380 | intel_dp_hot_plug(intel_encoder); |
00c09d70 PZ |
1381 | } |
1382 | ||
6801c18c VS |
1383 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1384 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1385 | { |
1386 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1387 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1388 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1389 | u32 temp, flags = 0; | |
1390 | ||
1391 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1392 | if (temp & TRANS_DDI_PHSYNC) | |
1393 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1394 | else | |
1395 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1396 | if (temp & TRANS_DDI_PVSYNC) | |
1397 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1398 | else | |
1399 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1400 | ||
1401 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1402 | |
1403 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1404 | case TRANS_DDI_BPC_6: | |
1405 | pipe_config->pipe_bpp = 18; | |
1406 | break; | |
1407 | case TRANS_DDI_BPC_8: | |
1408 | pipe_config->pipe_bpp = 24; | |
1409 | break; | |
1410 | case TRANS_DDI_BPC_10: | |
1411 | pipe_config->pipe_bpp = 30; | |
1412 | break; | |
1413 | case TRANS_DDI_BPC_12: | |
1414 | pipe_config->pipe_bpp = 36; | |
1415 | break; | |
1416 | default: | |
1417 | break; | |
1418 | } | |
eb14cb74 VS |
1419 | |
1420 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1421 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 1422 | pipe_config->has_hdmi_sink = true; |
eb14cb74 VS |
1423 | case TRANS_DDI_MODE_SELECT_DVI: |
1424 | case TRANS_DDI_MODE_SELECT_FDI: | |
1425 | break; | |
1426 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1427 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1428 | pipe_config->has_dp_encoder = true; | |
1429 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1430 | break; | |
1431 | default: | |
1432 | break; | |
1433 | } | |
10214420 | 1434 | |
a60551b1 PZ |
1435 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1436 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1437 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1438 | pipe_config->has_audio = true; | |
1439 | } | |
9ed109a7 | 1440 | |
10214420 DV |
1441 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1442 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1443 | /* | |
1444 | * This is a big fat ugly hack. | |
1445 | * | |
1446 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1447 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1448 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1449 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1450 | * max, not what it tells us to use. | |
1451 | * | |
1452 | * Note: This will still be broken if the eDP panel is not lit | |
1453 | * up by the BIOS, and thus we can't get the mode at module | |
1454 | * load. | |
1455 | */ | |
1456 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1457 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1458 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1459 | } | |
11578553 JB |
1460 | |
1461 | intel_ddi_clock_get(encoder, pipe_config); | |
045ac3b5 JB |
1462 | } |
1463 | ||
00c09d70 PZ |
1464 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1465 | { | |
1466 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1467 | intel_dp_encoder_destroy(encoder); | |
1468 | } | |
1469 | ||
5bfe2ac0 DV |
1470 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1471 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1472 | { |
5bfe2ac0 | 1473 | int type = encoder->type; |
eccb140b | 1474 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1475 | |
5bfe2ac0 | 1476 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1477 | |
eccb140b DV |
1478 | if (port == PORT_A) |
1479 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1480 | ||
00c09d70 | 1481 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1482 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1483 | else |
5bfe2ac0 | 1484 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1485 | } |
1486 | ||
1487 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1488 | .destroy = intel_ddi_destroy, | |
1489 | }; | |
1490 | ||
4a28ae58 PZ |
1491 | static struct intel_connector * |
1492 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1493 | { | |
1494 | struct intel_connector *connector; | |
1495 | enum port port = intel_dig_port->port; | |
1496 | ||
1497 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1498 | if (!connector) | |
1499 | return NULL; | |
1500 | ||
1501 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1502 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1503 | kfree(connector); | |
1504 | return NULL; | |
1505 | } | |
1506 | ||
1507 | return connector; | |
1508 | } | |
1509 | ||
1510 | static struct intel_connector * | |
1511 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1512 | { | |
1513 | struct intel_connector *connector; | |
1514 | enum port port = intel_dig_port->port; | |
1515 | ||
1516 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1517 | if (!connector) | |
1518 | return NULL; | |
1519 | ||
1520 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1521 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1522 | ||
1523 | return connector; | |
1524 | } | |
1525 | ||
00c09d70 PZ |
1526 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1527 | { | |
876a8cdf | 1528 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1529 | struct intel_digital_port *intel_dig_port; |
1530 | struct intel_encoder *intel_encoder; | |
1531 | struct drm_encoder *encoder; | |
311a2094 PZ |
1532 | bool init_hdmi, init_dp; |
1533 | ||
1534 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1535 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1536 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1537 | if (!init_dp && !init_hdmi) { | |
f68d697e | 1538 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
311a2094 PZ |
1539 | port_name(port)); |
1540 | init_hdmi = true; | |
1541 | init_dp = true; | |
1542 | } | |
00c09d70 | 1543 | |
b14c5679 | 1544 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1545 | if (!intel_dig_port) |
1546 | return; | |
1547 | ||
00c09d70 PZ |
1548 | intel_encoder = &intel_dig_port->base; |
1549 | encoder = &intel_encoder->base; | |
1550 | ||
1551 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1552 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1553 | |
5bfe2ac0 | 1554 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
1555 | intel_encoder->enable = intel_enable_ddi; |
1556 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1557 | intel_encoder->disable = intel_disable_ddi; | |
1558 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1559 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1560 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1561 | |
1562 | intel_dig_port->port = port; | |
bcf53de4 SM |
1563 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1564 | (DDI_BUF_PORT_REVERSAL | | |
1565 | DDI_A_4_LANES); | |
00c09d70 PZ |
1566 | |
1567 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
f68d697e | 1568 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 1569 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
1570 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1571 | ||
f68d697e CW |
1572 | if (init_dp) { |
1573 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
1574 | goto err; | |
13cf5504 | 1575 | |
f68d697e CW |
1576 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
1577 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
1578 | } | |
21a8e6a4 | 1579 | |
311a2094 PZ |
1580 | /* In theory we don't need the encoder->type check, but leave it just in |
1581 | * case we have some really bad VBTs... */ | |
f68d697e CW |
1582 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
1583 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
1584 | goto err; | |
21a8e6a4 | 1585 | } |
f68d697e CW |
1586 | |
1587 | return; | |
1588 | ||
1589 | err: | |
1590 | drm_encoder_cleanup(encoder); | |
1591 | kfree(intel_dig_port); | |
00c09d70 | 1592 | } |