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drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
cfda08cd 32#include "intel_combo_phy.h"
ec7f29ff 33#include "intel_connector.h"
fdc24cf3 34#include "intel_ddi.h"
27fec1f9 35#include "intel_dp.h"
e075094f 36#include "intel_dp_link_training.h"
b1ad4c39 37#include "intel_dpio_phy.h"
45244b87 38#include "intel_drv.h"
1dd07e56 39#include "intel_dsi.h"
8834e365 40#include "intel_fifo_underrun.h"
3ce2ea65 41#include "intel_gmbus.h"
408bd917 42#include "intel_hdcp.h"
0550691d 43#include "intel_hdmi.h"
dbeb38d9 44#include "intel_hotplug.h"
f3e18947 45#include "intel_lspcon.h"
44c1220a 46#include "intel_panel.h"
55367a27 47#include "intel_psr.h"
b375d0ef 48#include "intel_vdsc.h"
45244b87 49
10122051
JN		 50struct ddi_buf_trans {
51 u32 trans1; /* balance leg enable, de-emph level */
52 u32 trans2; /* vref sel, vswing */
f8896f5d 53 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 54};
55
97eeb872
VS		 56static const u8 index_to_dp_signal_levels[] = {
57 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
58 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
59 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
60 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
61 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
62 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
63 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
64 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
65 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
66 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
67};
68
45244b87
ED		 69/* HDMI/DVI modes ignore everything but the last 2 items. So we share
70 * them for both DP and FDI transports, allowing those ports to
71 * automatically adapt to HDMI connections as well
72 */
10122051 73static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 74 { 0x00FFFFFF, 0x0006000E, 0x0 },
75 { 0x00D75FFF, 0x0005000A, 0x0 },
76 { 0x00C30FFF, 0x00040006, 0x0 },
77 { 0x80AAAFFF, 0x000B0000, 0x0 },
78 { 0x00FFFFFF, 0x0005000A, 0x0 },
79 { 0x00D75FFF, 0x000C0004, 0x0 },
80 { 0x80C30FFF, 0x000B0000, 0x0 },
81 { 0x00FFFFFF, 0x00040006, 0x0 },
82 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 83};
84
10122051 85static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 86 { 0x00FFFFFF, 0x0007000E, 0x0 },
87 { 0x00D75FFF, 0x000F000A, 0x0 },
88 { 0x00C30FFF, 0x00060006, 0x0 },
89 { 0x00AAAFFF, 0x001E0000, 0x0 },
90 { 0x00FFFFFF, 0x000F000A, 0x0 },
91 { 0x00D75FFF, 0x00160004, 0x0 },
92 { 0x00C30FFF, 0x001E0000, 0x0 },
93 { 0x00FFFFFF, 0x00060006, 0x0 },
94 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 95};
96
10122051
JN		 97static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
98 /* Idx NT mV d T mV d db */
f8896f5d
DW		 99 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
100 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
101 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
102 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
103 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
104 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
105 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
106 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
107 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
108 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
109 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
110 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 111};
112
10122051 113static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 114 { 0x00FFFFFF, 0x00000012, 0x0 },
115 { 0x00EBAFFF, 0x00020011, 0x0 },
116 { 0x00C71FFF, 0x0006000F, 0x0 },
117 { 0x00AAAFFF, 0x000E000A, 0x0 },
118 { 0x00FFFFFF, 0x00020011, 0x0 },
119 { 0x00DB6FFF, 0x0005000F, 0x0 },
120 { 0x00BEEFFF, 0x000A000C, 0x0 },
121 { 0x00FFFFFF, 0x0005000F, 0x0 },
122 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 123};
124
10122051 125static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 126 { 0x00FFFFFF, 0x0007000E, 0x0 },
127 { 0x00D75FFF, 0x000E000A, 0x0 },
128 { 0x00BEFFFF, 0x00140006, 0x0 },
129 { 0x80B2CFFF, 0x001B0002, 0x0 },
130 { 0x00FFFFFF, 0x000E000A, 0x0 },
131 { 0x00DB6FFF, 0x00160005, 0x0 },
132 { 0x80C71FFF, 0x001A0002, 0x0 },
133 { 0x00F7DFFF, 0x00180004, 0x0 },
134 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 135};
136
10122051 137static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 138 { 0x00FFFFFF, 0x0001000E, 0x0 },
139 { 0x00D75FFF, 0x0004000A, 0x0 },
140 { 0x00C30FFF, 0x00070006, 0x0 },
141 { 0x00AAAFFF, 0x000C0000, 0x0 },
142 { 0x00FFFFFF, 0x0004000A, 0x0 },
143 { 0x00D75FFF, 0x00090004, 0x0 },
144 { 0x00C30FFF, 0x000C0000, 0x0 },
145 { 0x00FFFFFF, 0x00070006, 0x0 },
146 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 147};
148
10122051
JN		 149static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
150 /* Idx NT mV d T mV df db */
f8896f5d
DW		 151 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
152 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
153 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
154 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
155 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
156 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
157 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
158 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
159 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
160 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 161};
162
5f8b2531 163/* Skylake H and S */
7f88e3af 164static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 165 { 0x00002016, 0x000000A0, 0x0 },
166 { 0x00005012, 0x0000009B, 0x0 },
167 { 0x00007011, 0x00000088, 0x0 },
d7097cff 168 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 169 { 0x00002016, 0x0000009B, 0x0 },
170 { 0x00005012, 0x00000088, 0x0 },
d7097cff 171 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 172 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 173 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 174};
175
f8896f5d
DW		 176/* Skylake U */
177static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 178 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 179 { 0x00005012, 0x00000088, 0x0 },
5ac90567 180 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 181 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 182 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 183 { 0x80005012, 0x000000C0, 0x1 },
184 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 185 { 0x00002016, 0x00000088, 0x0 },
d7097cff 186 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 187};
188
5f8b2531
RV		 189/* Skylake Y */
190static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 191 { 0x00000018, 0x000000A2, 0x0 },
192 { 0x00005012, 0x00000088, 0x0 },
5ac90567 193 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 194 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 195 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 196 { 0x80005012, 0x000000C0, 0x3 },
197 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 198 { 0x00000018, 0x00000088, 0x0 },
d7097cff 199 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 200};
201
0fdd4918
RV		 202/* Kabylake H and S */
203static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
204 { 0x00002016, 0x000000A0, 0x0 },
205 { 0x00005012, 0x0000009B, 0x0 },
206 { 0x00007011, 0x00000088, 0x0 },
207 { 0x80009010, 0x000000C0, 0x1 },
208 { 0x00002016, 0x0000009B, 0x0 },
209 { 0x00005012, 0x00000088, 0x0 },
210 { 0x80007011, 0x000000C0, 0x1 },
211 { 0x00002016, 0x00000097, 0x0 },
212 { 0x80005012, 0x000000C0, 0x1 },
213};
214
215/* Kabylake U */
216static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
217 { 0x0000201B, 0x000000A1, 0x0 },
218 { 0x00005012, 0x00000088, 0x0 },
219 { 0x80007011, 0x000000CD, 0x3 },
220 { 0x80009010, 0x000000C0, 0x3 },
221 { 0x0000201B, 0x0000009D, 0x0 },
222 { 0x80005012, 0x000000C0, 0x3 },
223 { 0x80007011, 0x000000C0, 0x3 },
224 { 0x00002016, 0x0000004F, 0x0 },
225 { 0x80005012, 0x000000C0, 0x3 },
226};
227
228/* Kabylake Y */
229static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
230 { 0x00001017, 0x000000A1, 0x0 },
231 { 0x00005012, 0x00000088, 0x0 },
232 { 0x80007011, 0x000000CD, 0x3 },
233 { 0x8000800F, 0x000000C0, 0x3 },
234 { 0x00001017, 0x0000009D, 0x0 },
235 { 0x80005012, 0x000000C0, 0x3 },
236 { 0x80007011, 0x000000C0, 0x3 },
237 { 0x00001017, 0x0000004C, 0x0 },
238 { 0x80005012, 0x000000C0, 0x3 },
239};
240
f8896f5d 241/*
0fdd4918 242 * Skylake/Kabylake H and S
f8896f5d
DW		 243 * eDP 1.4 low vswing translation parameters
244 */
7ad14a29 245static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 246 { 0x00000018, 0x000000A8, 0x0 },
247 { 0x00004013, 0x000000A9, 0x0 },
248 { 0x00007011, 0x000000A2, 0x0 },
249 { 0x00009010, 0x0000009C, 0x0 },
250 { 0x00000018, 0x000000A9, 0x0 },
251 { 0x00006013, 0x000000A2, 0x0 },
252 { 0x00007011, 0x000000A6, 0x0 },
253 { 0x00000018, 0x000000AB, 0x0 },
254 { 0x00007013, 0x0000009F, 0x0 },
255 { 0x00000018, 0x000000DF, 0x0 },
256};
257
258/*
0fdd4918 259 * Skylake/Kabylake U
f8896f5d
DW		 260 * eDP 1.4 low vswing translation parameters
261 */
262static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
263 { 0x00000018, 0x000000A8, 0x0 },
264 { 0x00004013, 0x000000A9, 0x0 },
265 { 0x00007011, 0x000000A2, 0x0 },
266 { 0x00009010, 0x0000009C, 0x0 },
267 { 0x00000018, 0x000000A9, 0x0 },
268 { 0x00006013, 0x000000A2, 0x0 },
269 { 0x00007011, 0x000000A6, 0x0 },
270 { 0x00002016, 0x000000AB, 0x0 },
271 { 0x00005013, 0x0000009F, 0x0 },
272 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 273};
274
f8896f5d 275/*
0fdd4918 276 * Skylake/Kabylake Y
f8896f5d
DW		 277 * eDP 1.4 low vswing translation parameters
278 */
5f8b2531 279static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 280 { 0x00000018, 0x000000A8, 0x0 },
281 { 0x00004013, 0x000000AB, 0x0 },
282 { 0x00007011, 0x000000A4, 0x0 },
283 { 0x00009010, 0x000000DF, 0x0 },
284 { 0x00000018, 0x000000AA, 0x0 },
285 { 0x00006013, 0x000000A4, 0x0 },
286 { 0x00007011, 0x0000009D, 0x0 },
287 { 0x00000018, 0x000000A0, 0x0 },
288 { 0x00006012, 0x000000DF, 0x0 },
289 { 0x00000018, 0x0000008A, 0x0 },
290};
7ad14a29 291
0fdd4918 292/* Skylake/Kabylake U, H and S */
7f88e3af 293static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 294 { 0x00000018, 0x000000AC, 0x0 },
295 { 0x00005012, 0x0000009D, 0x0 },
296 { 0x00007011, 0x00000088, 0x0 },
297 { 0x00000018, 0x000000A1, 0x0 },
298 { 0x00000018, 0x00000098, 0x0 },
299 { 0x00004013, 0x00000088, 0x0 },
2e78416e 300 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 301 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 302 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
303 { 0x80003015, 0x000000C0, 0x1 },
304 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 305};
306
0fdd4918 307/* Skylake/Kabylake Y */
5f8b2531 308static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 309 { 0x00000018, 0x000000A1, 0x0 },
310 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 311 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 312 { 0x00000018, 0x000000A4, 0x0 },
313 { 0x00000018, 0x0000009D, 0x0 },
314 { 0x00004013, 0x00000080, 0x0 },
2e78416e 315 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 316 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 317 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
318 { 0x80003015, 0x000000C0, 0x3 },
319 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 320};
321
96fb9f9b 322struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 323 u8 margin; /* swing value */
324 u8 scale; /* scale value */
325 u8 enable; /* scale enable */
326 u8 deemphasis;
96fb9f9b
VK		 327};
328
96fb9f9b
VK		 329static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
330 /* Idx NT mV diff db */
043eaf36
VS		 331 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
332 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
333 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
334 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
335 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
336 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
337 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
338 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
339 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
340 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 341};
342
d9d7000d
SJ		 343static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
344 /* Idx NT mV diff db */
043eaf36
VS		 345 { 26, 0, 0, 128, }, /* 0: 200 0 */
346 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
347 { 48, 0, 0, 96, }, /* 2: 200 4 */
348 { 54, 0, 0, 69, }, /* 3: 200 6 */
349 { 32, 0, 0, 128, }, /* 4: 250 0 */
350 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
351 { 54, 0, 0, 85, }, /* 6: 250 4 */
352 { 43, 0, 0, 128, }, /* 7: 300 0 */
353 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
354 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 355};
356
96fb9f9b
VK		 357/* BSpec has 2 recommended values - entries 0 and 8.
358 * Using the entry with higher vswing.
359 */
360static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
361 /* Idx NT mV diff db */
043eaf36
VS		 362 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
363 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
364 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
365 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
366 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
367 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
368 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
369 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
370 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
371 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 372};
373
83fb7ab4 374struct cnl_ddi_buf_trans {
fb5f4e96
VS		 375 u8 dw2_swing_sel;
376 u8 dw7_n_scalar;
377 u8 dw4_cursor_coeff;
378 u8 dw4_post_cursor_2;
379 u8 dw4_post_cursor_1;
83fb7ab4
RV		 380};
381
382/* Voltage Swing Programming for VccIO 0.85V for DP */
383static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
384 /* NT mV Trans mV db */
385 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
386 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
387 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
388 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
389 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
390 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
391 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
392 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
393 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
394 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
395};
396
397/* Voltage Swing Programming for VccIO 0.85V for HDMI */
398static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
399 /* NT mV Trans mV db */
400 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
401 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
402 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
403 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
404 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
405 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
406 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
407};
408
409/* Voltage Swing Programming for VccIO 0.85V for eDP */
410static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
411 /* NT mV Trans mV db */
412 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
413 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
414 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
415 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
416 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
417 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
418 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
419 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
420 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
421};
422
423/* Voltage Swing Programming for VccIO 0.95V for DP */
424static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
425 /* NT mV Trans mV db */
426 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
427 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
428 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
429 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
430 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
431 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
432 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
433 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
434 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
435 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
436};
437
438/* Voltage Swing Programming for VccIO 0.95V for HDMI */
439static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
440 /* NT mV Trans mV db */
441 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
442 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
443 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
444 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
445 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
446 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
447 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
448 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
449 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
450 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
451 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
452};
453
454/* Voltage Swing Programming for VccIO 0.95V for eDP */
455static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
456 /* NT mV Trans mV db */
457 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
458 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
459 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
460 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
461 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
462 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
463 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
464 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
465 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
466 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
467};
468
469/* Voltage Swing Programming for VccIO 1.05V for DP */
470static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
471 /* NT mV Trans mV db */
472 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
473 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
474 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
475 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
476 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
477 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
478 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
479 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
480 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
481 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
482};
483
484/* Voltage Swing Programming for VccIO 1.05V for HDMI */
485static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
486 /* NT mV Trans mV db */
487 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
488 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
489 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
490 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
491 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
492 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
493 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
494 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
495 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
496 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
497 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
498};
499
500/* Voltage Swing Programming for VccIO 1.05V for eDP */
501static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
502 /* NT mV Trans mV db */
503 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
504 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
505 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
506 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
507 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
508 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
509 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
510 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
511 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
512};
513
b265a2a6
CT		 514/* icl_combo_phy_ddi_translations */
515static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
516 /* NT mV Trans mV db */
517 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
518 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
519 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
520 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
521 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
522 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
523 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
524 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
525 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
526 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 527};
528
b265a2a6
CT		 529static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
530 /* NT mV Trans mV db */
531 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
532 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
533 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
534 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
535 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
536 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
537 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
538 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
539 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
540 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 541};
542
b265a2a6
CT		 543static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
544 /* NT mV Trans mV db */
545 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
546 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
547 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
548 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
549 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
550 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
551 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
552 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
553 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
554 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 555};
556
b265a2a6
CT		 557static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
558 /* NT mV Trans mV db */
559 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
560 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
561 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
562 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
563 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
564 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
565 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 566};
567
cd96bea7
MN		 568struct icl_mg_phy_ddi_buf_trans {
569 u32 cri_txdeemph_override_5_0;
570 u32 cri_txdeemph_override_11_6;
571 u32 cri_txdeemph_override_17_12;
572};
573
574static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
575 /* Voltage swing pre-emphasis */
576 { 0x0, 0x1B, 0x00 }, /* 0 0 */
577 { 0x0, 0x23, 0x08 }, /* 0 1 */
578 { 0x0, 0x2D, 0x12 }, /* 0 2 */
579 { 0x0, 0x00, 0x00 }, /* 0 3 */
580 { 0x0, 0x23, 0x00 }, /* 1 0 */
581 { 0x0, 0x2B, 0x09 }, /* 1 1 */
582 { 0x0, 0x2E, 0x11 }, /* 1 2 */
583 { 0x0, 0x2F, 0x00 }, /* 2 0 */
584 { 0x0, 0x33, 0x0C }, /* 2 1 */
585 { 0x0, 0x00, 0x00 }, /* 3 0 */
586};
587
a930acd9
VS		 588static const struct ddi_buf_trans *
589bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
590{
591 if (dev_priv->vbt.edp.low_vswing) {
592 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
593 return bdw_ddi_translations_edp;
594 } else {
595 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
596 return bdw_ddi_translations_dp;
597 }
598}
599
acee2998 600static const struct ddi_buf_trans *
78ab0bae 601skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 602{
0fdd4918 603 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 604 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 605 return skl_y_ddi_translations_dp;
0fdd4918 606 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 607 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 608 return skl_u_ddi_translations_dp;
f8896f5d 609 } else {
f8896f5d 610 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 611 return skl_ddi_translations_dp;
f8896f5d 612 }
f8896f5d
DW		 613}
614
0fdd4918
RV		 615static const struct ddi_buf_trans *
616kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
617{
dfdaa566 618 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
0fdd4918
RV		 619 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
620 return kbl_y_ddi_translations_dp;
da411a48 621 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 622 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
623 return kbl_u_ddi_translations_dp;
624 } else {
625 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
626 return kbl_ddi_translations_dp;
627 }
628}
629
acee2998 630static const struct ddi_buf_trans *
78ab0bae 631skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 632{
06411f08 633 if (dev_priv->vbt.edp.low_vswing) {
dfdaa566 634 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 635 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 636 return skl_y_ddi_translations_edp;
da411a48
RV		 637 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
638 IS_CFL_ULT(dev_priv)) {
f8896f5d 639 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 640 return skl_u_ddi_translations_edp;
f8896f5d 641 } else {
f8896f5d 642 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 643 return skl_ddi_translations_edp;
f8896f5d
DW		 644 }
645 }
cd1101cb 646
da411a48 647 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 648 return kbl_get_buf_trans_dp(dev_priv, n_entries);
649 else
650 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 651}
652
653static const struct ddi_buf_trans *
78ab0bae 654skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 655{
dfdaa566 656 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 657 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 658 return skl_y_ddi_translations_hdmi;
f8896f5d 659 } else {
f8896f5d 660 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 661 return skl_ddi_translations_hdmi;
f8896f5d 662 }
f8896f5d
DW		 663}
664
edba48fd
VS		 665static int skl_buf_trans_num_entries(enum port port, int n_entries)
666{
667 /* Only DDIA and DDIE can select the 10th register with DP */
668 if (port == PORT_A || port == PORT_E)
669 return min(n_entries, 10);
670 else
671 return min(n_entries, 9);
672}
673
d8fe2c7f
VS		 674static const struct ddi_buf_trans *
675intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 676 enum port port, int *n_entries)
d8fe2c7f
VS		 677{
678 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 679 const struct ddi_buf_trans *ddi_translations =
680 kbl_get_buf_trans_dp(dev_priv, n_entries);
681 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
682 return ddi_translations;
d8fe2c7f 683 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 684 const struct ddi_buf_trans *ddi_translations =
685 skl_get_buf_trans_dp(dev_priv, n_entries);
686 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
687 return ddi_translations;
d8fe2c7f
VS		 688 } else if (IS_BROADWELL(dev_priv)) {
689 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
690 return bdw_ddi_translations_dp;
691 } else if (IS_HASWELL(dev_priv)) {
692 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
693 return hsw_ddi_translations_dp;
694 }
695
696 *n_entries = 0;
697 return NULL;
698}
699
700static const struct ddi_buf_trans *
701intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 702 enum port port, int *n_entries)
d8fe2c7f
VS		 703{
704 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 705 const struct ddi_buf_trans *ddi_translations =
706 skl_get_buf_trans_edp(dev_priv, n_entries);
707 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
708 return ddi_translations;
d8fe2c7f
VS		 709 } else if (IS_BROADWELL(dev_priv)) {
710 return bdw_get_buf_trans_edp(dev_priv, n_entries);
711 } else if (IS_HASWELL(dev_priv)) {
712 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
713 return hsw_ddi_translations_dp;
714 }
715
716 *n_entries = 0;
717 return NULL;
718}
719
720static const struct ddi_buf_trans *
721intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
722 int *n_entries)
723{
724 if (IS_BROADWELL(dev_priv)) {
725 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
726 return bdw_ddi_translations_fdi;
727 } else if (IS_HASWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
729 return hsw_ddi_translations_fdi;
730 }
731
732 *n_entries = 0;
733 return NULL;
734}
735
975786ee
VS		 736static const struct ddi_buf_trans *
737intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
738 int *n_entries)
739{
740 if (IS_GEN9_BC(dev_priv)) {
741 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
742 } else if (IS_BROADWELL(dev_priv)) {
743 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
744 return bdw_ddi_translations_hdmi;
745 } else if (IS_HASWELL(dev_priv)) {
746 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
747 return hsw_ddi_translations_hdmi;
748 }
749
750 *n_entries = 0;
751 return NULL;
752}
753
7d4f37b5
VS		 754static const struct bxt_ddi_buf_trans *
755bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
756{
757 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
758 return bxt_ddi_translations_dp;
759}
760
761static const struct bxt_ddi_buf_trans *
762bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
763{
764 if (dev_priv->vbt.edp.low_vswing) {
765 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
766 return bxt_ddi_translations_edp;
767 }
768
769 return bxt_get_buf_trans_dp(dev_priv, n_entries);
770}
771
772static const struct bxt_ddi_buf_trans *
773bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
774{
775 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
776 return bxt_ddi_translations_hdmi;
777}
778
cf3e0fb4
RV		 779static const struct cnl_ddi_buf_trans *
780cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
781{
782 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
783
784 if (voltage == VOLTAGE_INFO_0_85V) {
785 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
786 return cnl_ddi_translations_hdmi_0_85V;
787 } else if (voltage == VOLTAGE_INFO_0_95V) {
788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
789 return cnl_ddi_translations_hdmi_0_95V;
790 } else if (voltage == VOLTAGE_INFO_1_05V) {
791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
792 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 793 } else {
794 *n_entries = 1; /* shut up gcc */
cf3e0fb4 795 MISSING_CASE(voltage);
83482ca3 796 }
cf3e0fb4
RV		 797 return NULL;
798}
799
800static const struct cnl_ddi_buf_trans *
801cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
802{
803 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
804
805 if (voltage == VOLTAGE_INFO_0_85V) {
806 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
807 return cnl_ddi_translations_dp_0_85V;
808 } else if (voltage == VOLTAGE_INFO_0_95V) {
809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
810 return cnl_ddi_translations_dp_0_95V;
811 } else if (voltage == VOLTAGE_INFO_1_05V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
813 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 814 } else {
815 *n_entries = 1; /* shut up gcc */
cf3e0fb4 816 MISSING_CASE(voltage);
83482ca3 817 }
cf3e0fb4
RV		 818 return NULL;
819}
820
821static const struct cnl_ddi_buf_trans *
822cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
823{
824 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
825
826 if (dev_priv->vbt.edp.low_vswing) {
827 if (voltage == VOLTAGE_INFO_0_85V) {
828 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
829 return cnl_ddi_translations_edp_0_85V;
830 } else if (voltage == VOLTAGE_INFO_0_95V) {
831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
832 return cnl_ddi_translations_edp_0_95V;
833 } else if (voltage == VOLTAGE_INFO_1_05V) {
834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
835 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 836 } else {
837 *n_entries = 1; /* shut up gcc */
cf3e0fb4 838 MISSING_CASE(voltage);
83482ca3 839 }
cf3e0fb4
RV		 840 return NULL;
841 } else {
842 return cnl_get_buf_trans_dp(dev_priv, n_entries);
843 }
844}
845
b265a2a6 846static const struct cnl_ddi_buf_trans *
fb5c8e9d 847icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
b265a2a6 848 int type, int rate, int *n_entries)
fb5c8e9d 849{
b265a2a6
CT		 850 if (type == INTEL_OUTPUT_HDMI) {
851 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
852 return icl_combo_phy_ddi_translations_hdmi;
853 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
855 return icl_combo_phy_ddi_translations_edp_hbr3;
856 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
858 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 859 }
b265a2a6
CT		 860
861 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
862 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 863}
864
8d8bb85e
VS		 865static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
866{
d02ace87 867 int n_entries, level, default_entry;
8d8bb85e 868
d02ace87 869 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 870
2dd24a9c 871 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 872 if (intel_port_is_combophy(dev_priv, port))
b265a2a6
CT		 873 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
874 0, &n_entries);
dccc7228
MN		 875 else
876 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
877 default_entry = n_entries - 1;
878 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 879 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
880 default_entry = n_entries - 1;
043eaf36 881 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 882 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
883 default_entry = n_entries - 1;
bf503556 884 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 885 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
886 default_entry = 8;
8d8bb85e 887 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 888 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
889 default_entry = 7;
8d8bb85e 890 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 891 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
892 default_entry = 6;
8d8bb85e
VS		 893 } else {
894 WARN(1, "ddi translation table missing\n");
975786ee 895 return 0;
8d8bb85e
VS		 896 }
897
898 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 899 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
900 level = default_entry;
8d8bb85e 901
d02ace87 902 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 903 return 0;
d02ace87
VS		 904 if (WARN_ON_ONCE(level >= n_entries))
905 level = n_entries - 1;
21b39d2a 906
d02ace87 907 return level;
8d8bb85e
VS		 908}
909
e58623cb
AR		 910/*
911 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 912 * values in advance. This function programs the correct values for
913 * DP/eDP/FDI use cases.
45244b87 914 */
3a6d84e6
VS		 915static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
916 const struct intel_crtc_state *crtc_state)
45244b87 917{
6a7e4f99 918 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 919 u32 iboost_bit = 0;
7d1c42e6 920 int i, n_entries;
0fce04c8 921 enum port port = encoder->port;
10122051 922 const struct ddi_buf_trans *ddi_translations;
e58623cb 923
3a6d84e6
VS		 924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
925 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
926 &n_entries);
927 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 928 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 929 &n_entries);
3a6d84e6 930 else
edba48fd 931 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 932 &n_entries);
e58623cb 933
edba48fd
VS		 934 /* If we're boosting the current, set bit 31 of trans1 */
935 if (IS_GEN9_BC(dev_priv) &&
936 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
937 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 938
7d1c42e6 939 for (i = 0; i < n_entries; i++) {
9712e688
VS		 940 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
941 ddi_translations[i].trans1 | iboost_bit);
942 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
943 ddi_translations[i].trans2);
45244b87 944 }
32bdc400
VS		 945}
946
947/*
948 * Starting with Haswell, DDI port buffers must be programmed with correct
949 * values in advance. This function programs the correct values for
950 * HDMI/DVI use cases.
951 */
7ea79333 952static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 953 int level)
32bdc400
VS		 954{
955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
956 u32 iboost_bit = 0;
d02ace87 957 int n_entries;
0fce04c8 958 enum port port = encoder->port;
d02ace87 959 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 960
d02ace87 961 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 962
d02ace87 963 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 964 return;
d02ace87
VS		 965 if (WARN_ON_ONCE(level >= n_entries))
966 level = n_entries - 1;
21b39d2a 967
975786ee
VS		 968 /* If we're boosting the current, set bit 31 of trans1 */
969 if (IS_GEN9_BC(dev_priv) &&
970 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
971 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 972
6acab15a 973 /* Entry 9 is for HDMI: */
ed9c77d2 974 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 975 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 976 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 977 ddi_translations[level].trans2);
45244b87
ED		 978}
979
248138b5
PZ		 980static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
981 enum port port)
982{
f0f59a00 983 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 984 int i;
985
3449ca85 986 for (i = 0; i < 16; i++) {
248138b5
PZ		 987 udelay(1);
988 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
989 return;
990 }
991 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
992}
c82e4d26 993
3d0c5005 994static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 995{
0823eb9c 996 switch (pll->info->id) {
c856052a
ACO		 997 case DPLL_ID_WRPLL1:
998 return PORT_CLK_SEL_WRPLL1;
999 case DPLL_ID_WRPLL2:
1000 return PORT_CLK_SEL_WRPLL2;
1001 case DPLL_ID_SPLL:
1002 return PORT_CLK_SEL_SPLL;
1003 case DPLL_ID_LCPLL_810:
1004 return PORT_CLK_SEL_LCPLL_810;
1005 case DPLL_ID_LCPLL_1350:
1006 return PORT_CLK_SEL_LCPLL_1350;
1007 case DPLL_ID_LCPLL_2700:
1008 return PORT_CLK_SEL_LCPLL_2700;
1009 default:
0823eb9c 1010 MISSING_CASE(pll->info->id);
c856052a
ACO		 1011 return PORT_CLK_SEL_NONE;
1012 }
1013}
1014
20fd2ab7 1015static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1016 const struct intel_crtc_state *crtc_state)
c27e917e 1017{
0e5fa646
ML		 1018 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1019 int clock = crtc_state->port_clock;
c27e917e
PZ		 1020 const enum intel_dpll_id id = pll->info->id;
1021
1022 switch (id) {
1023 default:
20fd2ab7
LDM		 1024 /*
1025 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1026 * here, so do warn if this get passed in
1027 */
c27e917e 1028 MISSING_CASE(id);
c27e917e 1029 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1030 case DPLL_ID_ICL_TBTPLL:
1031 switch (clock) {
1032 case 162000:
1033 return DDI_CLK_SEL_TBT_162;
1034 case 270000:
1035 return DDI_CLK_SEL_TBT_270;
1036 case 540000:
1037 return DDI_CLK_SEL_TBT_540;
1038 case 810000:
1039 return DDI_CLK_SEL_TBT_810;
1040 default:
1041 MISSING_CASE(clock);
7a61a6de 1042 return DDI_CLK_SEL_NONE;
1fa11ee2 1043 }
c27e917e
PZ		 1044 case DPLL_ID_ICL_MGPLL1:
1045 case DPLL_ID_ICL_MGPLL2:
1046 case DPLL_ID_ICL_MGPLL3:
1047 case DPLL_ID_ICL_MGPLL4:
1048 return DDI_CLK_SEL_MG;
1049 }
1050}
1051
c82e4d26
ED		 1052/* Starting with Haswell, different DDI ports can work in FDI mode for
1053 * connection to the PCH-located connectors. For this, it is necessary to train
1054 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1055 *
1056 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1057 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1058 * DDI A (which is used for eDP)
1059 */
1060
dc4a1094
ACO		 1061void hsw_fdi_link_train(struct intel_crtc *crtc,
1062 const struct intel_crtc_state *crtc_state)
c82e4d26 1063{
4cbe4b2b 1064 struct drm_device *dev = crtc->base.dev;
fac5e23e 1065 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1066 struct intel_encoder *encoder;
c856052a 1067 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1068
4cbe4b2b 1069 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1070 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1071 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1072 }
1073
04945641
PZ		 1074 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1075 * mode set "sequence for CRT port" document:
1076 * - TP1 to TP2 time with the default value
1077 * - FDI delay to 90h
8693a824
DL		 1078 *
1079 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1080 */
eede3b53 1081 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1082 FDI_RX_PWRDN_LANE0_VAL(2) |
1083 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1084
1085 /* Enable the PCH Receiver FDI PLL */
3e68320e 1086 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1087 FDI_RX_PLL_ENABLE |
dc4a1094 1088 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1089 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1090 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1091 udelay(220);
1092
1093 /* Switch from Rawclk to PCDclk */
1094 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1095 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1096
1097 /* Configure Port Clock Select */
dc4a1094 1098 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1099 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1100 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1101
1102 /* Start the training iterating through available voltages and emphasis,
1103 * testing each value twice. */
10122051 1104 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1105 /* Configure DP_TP_CTL with auto-training */
1106 I915_WRITE(DP_TP_CTL(PORT_E),
1107 DP_TP_CTL_FDI_AUTOTRAIN |
1108 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1109 DP_TP_CTL_LINK_TRAIN_PAT1 |
1110 DP_TP_CTL_ENABLE);
1111
876a8cdf
DL		 1112 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1113 * DDI E does not support port reversal, the functionality is
1114 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1115 * port reversal bit */
c82e4d26 1116 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1117 DDI_BUF_CTL_ENABLE |
dc4a1094 1118 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1119 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1120 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1121
1122 udelay(600);
1123
04945641 1124 /* Program PCH FDI Receiver TU */
eede3b53 1125 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1126
1127 /* Enable PCH FDI Receiver with auto-training */
1128 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1129 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1130 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1131
1132 /* Wait for FDI receiver lane calibration */
1133 udelay(30);
1134
1135 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1136 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1137 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1138 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1139 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1140
1141 /* Wait for FDI auto training time */
1142 udelay(5);
c82e4d26
ED		 1143
1144 temp = I915_READ(DP_TP_STATUS(PORT_E));
1145 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1146 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1147 break;
1148 }
c82e4d26 1149
a308ccb3
VS		 1150 /*
1151 * Leave things enabled even if we failed to train FDI.
1152 * Results in less fireworks from the state checker.
1153 */
1154 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1155 DRM_ERROR("FDI link training failed!\n");
1156 break;
c82e4d26 1157 }
04945641 1158
5b421c57
VS		 1159 rx_ctl_val &= ~FDI_RX_ENABLE;
1160 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1161 POSTING_READ(FDI_RX_CTL(PIPE_A));
1162
248138b5
PZ		 1163 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1164 temp &= ~DDI_BUF_CTL_ENABLE;
1165 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
04945641 1168 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1169 temp = I915_READ(DP_TP_CTL(PORT_E));
1170 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1171 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1172 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1173 POSTING_READ(DP_TP_CTL(PORT_E));
1174
1175 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1176
04945641 1177 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1178 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1179 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1180 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1181 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1182 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1183 }
1184
a308ccb3
VS		 1185 /* Enable normal pixel sending for FDI */
1186 I915_WRITE(DP_TP_CTL(PORT_E),
1187 DP_TP_CTL_FDI_AUTOTRAIN |
1188 DP_TP_CTL_LINK_TRAIN_NORMAL |
1189 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1190 DP_TP_CTL_ENABLE);
c82e4d26 1191}
0e72a5b5 1192
d7c530b2 1193static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1194{
1195 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1196 struct intel_digital_port *intel_dig_port =
1197 enc_to_dig_port(&encoder->base);
1198
1199 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1200 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1201 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1202}
1203
8d9ddbcb 1204static struct intel_encoder *
e9ce1a62 1205intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1206{
e9ce1a62 1207 struct drm_device *dev = crtc->base.dev;
1524e93e 1208 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1209 int num_encoders = 0;
1210
1524e93e
SS		 1211 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1212 ret = encoder;
8d9ddbcb
PZ		 1213 num_encoders++;
1214 }
1215
1216 if (num_encoders != 1)
84f44ce7 1217 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1218 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1219
1220 BUG_ON(ret == NULL);
1221 return ret;
1222}
1223
1c0b85c5 1224#define LC_FREQ 2700
1c0b85c5 1225
f0f59a00
VS		 1226static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1227 i915_reg_t reg)
11578553
JB		 1228{
1229 int refclk = LC_FREQ;
1230 int n, p, r;
1231 u32 wrpll;
1232
1233 wrpll = I915_READ(reg);
114fe488
DV		 1234 switch (wrpll & WRPLL_PLL_REF_MASK) {
1235 case WRPLL_PLL_SSC:
1236 case WRPLL_PLL_NON_SSC:
11578553
JB		 1237 /*
1238 * We could calculate spread here, but our checking
1239 * code only cares about 5% accuracy, and spread is a max of
1240 * 0.5% downspread.
1241 */
1242 refclk = 135;
1243 break;
114fe488 1244 case WRPLL_PLL_LCPLL:
11578553
JB		 1245 refclk = LC_FREQ;
1246 break;
1247 default:
1248 WARN(1, "bad wrpll refclk\n");
1249 return 0;
1250 }
1251
1252 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1253 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1254 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1255
20f0ec16
JB		 1256 /* Convert to KHz, p & r have a fixed point portion */
1257 return (refclk * n * 100) / (p * r);
11578553
JB		 1258}
1259
947f4417 1260static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1261{
3d0c5005 1262 u32 p0, p1, p2, dco_freq;
540e732c 1263
947f4417
LDM		 1264 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1265 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1266
947f4417
LDM		 1267 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1268 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1269 else
1270 p1 = 1;
1271
1272
1273 switch (p0) {
1274 case DPLL_CFGCR2_PDIV_1:
1275 p0 = 1;
1276 break;
1277 case DPLL_CFGCR2_PDIV_2:
1278 p0 = 2;
1279 break;
1280 case DPLL_CFGCR2_PDIV_3:
1281 p0 = 3;
1282 break;
1283 case DPLL_CFGCR2_PDIV_7:
1284 p0 = 7;
1285 break;
1286 }
1287
1288 switch (p2) {
1289 case DPLL_CFGCR2_KDIV_5:
1290 p2 = 5;
1291 break;
1292 case DPLL_CFGCR2_KDIV_2:
1293 p2 = 2;
1294 break;
1295 case DPLL_CFGCR2_KDIV_3:
1296 p2 = 3;
1297 break;
1298 case DPLL_CFGCR2_KDIV_1:
1299 p2 = 1;
1300 break;
1301 }
1302
947f4417
LDM		 1303 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1304 * 24 * 1000;
540e732c 1305
947f4417
LDM		 1306 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1307 * 24 * 1000) / 0x8000;
540e732c 1308
b8449c43
YX		 1309 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1310 return 0;
1311
540e732c
S		 1312 return dco_freq / (p0 * p1 * p2 * 5);
1313}
1314
8327af28 1315int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1316 struct intel_dpll_hw_state *pll_state)
a9701a89 1317{
3d0c5005 1318 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1319
5e65216d
LDM		 1320 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1321 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1322
5e65216d
LDM		 1323 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1324 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1325 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1326 else
1327 p1 = 1;
1328
1329
1330 switch (p0) {
1331 case DPLL_CFGCR1_PDIV_2:
1332 p0 = 2;
1333 break;
1334 case DPLL_CFGCR1_PDIV_3:
1335 p0 = 3;
1336 break;
1337 case DPLL_CFGCR1_PDIV_5:
1338 p0 = 5;
1339 break;
1340 case DPLL_CFGCR1_PDIV_7:
1341 p0 = 7;
1342 break;
1343 }
1344
1345 switch (p2) {
1346 case DPLL_CFGCR1_KDIV_1:
1347 p2 = 1;
1348 break;
1349 case DPLL_CFGCR1_KDIV_2:
1350 p2 = 2;
1351 break;
2ee7fd1e
VS		 1352 case DPLL_CFGCR1_KDIV_3:
1353 p2 = 3;
a9701a89
RV		 1354 break;
1355 }
1356
9f9d594d 1357 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1358
5e65216d
LDM		 1359 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1360 * ref_clock;
a9701a89 1361
5e65216d 1362 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1363 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1364
0e005888
PZ		 1365 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1366 return 0;
1367
a9701a89
RV		 1368 return dco_freq / (p0 * p1 * p2 * 5);
1369}
1370
7b19f544
MN		 1371static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1372 enum port port)
1373{
1374 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1375
1376 switch (val) {
1377 case DDI_CLK_SEL_NONE:
1378 return 0;
1379 case DDI_CLK_SEL_TBT_162:
1380 return 162000;
1381 case DDI_CLK_SEL_TBT_270:
1382 return 270000;
1383 case DDI_CLK_SEL_TBT_540:
1384 return 540000;
1385 case DDI_CLK_SEL_TBT_810:
1386 return 810000;
1387 default:
1388 MISSING_CASE(val);
1389 return 0;
1390 }
1391}
1392
1393static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1394 const struct intel_dpll_hw_state *pll_state)
7b19f544 1395{
02c99d26 1396 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1397 u64 tmp;
1398
02c99d26 1399 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1400
02c99d26
LDM		 1401 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1402 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1403 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1404 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1405 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1406
02c99d26
LDM		 1407 switch (pll_state->mg_clktop2_hsclkctl &
1408 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1409 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1410 div1 = 2;
1411 break;
1412 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1413 div1 = 3;
1414 break;
1415 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1416 div1 = 5;
1417 break;
1418 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1419 div1 = 7;
1420 break;
1421 default:
02c99d26 1422 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1423 return 0;
1424 }
1425
02c99d26
LDM		 1426 div2 = (pll_state->mg_clktop2_hsclkctl &
1427 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1428 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1429
7b19f544
MN		 1430 /* div2 value of 0 is same as 1 means no div */
1431 if (div2 == 0)
1432 div2 = 1;
1433
1434 /*
1435 * Adjust the original formula to delay the division by 2^22 in order to
1436 * minimize possible rounding errors.
1437 */
02c99d26
LDM		 1438 tmp = (u64)m1 * m2_int * ref_clock +
1439 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1440 tmp = div_u64(tmp, 5 * div1 * div2);
1441
1442 return tmp;
1443}
1444
398a017e
VS		 1445static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1446{
1447 int dotclock;
1448
1449 if (pipe_config->has_pch_encoder)
1450 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1451 &pipe_config->fdi_m_n);
37a5650b 1452 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1453 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1454 &pipe_config->dp_m_n);
1455 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1456 dotclock = pipe_config->port_clock * 2 / 3;
1457 else
1458 dotclock = pipe_config->port_clock;
1459
33b7f3ee 1460 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
b22ca995
SS		 1461 dotclock *= 2;
1462
398a017e
VS		 1463 if (pipe_config->pixel_multiplier)
1464 dotclock /= pipe_config->pixel_multiplier;
1465
1466 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1467}
540e732c 1468
51c83cfa
MN		 1469static void icl_ddi_clock_get(struct intel_encoder *encoder,
1470 struct intel_crtc_state *pipe_config)
1471{
1472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1473 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1474 enum port port = encoder->port;
5e65216d 1475 int link_clock;
51c83cfa 1476
176597a1 1477 if (intel_port_is_combophy(dev_priv, port)) {
5e65216d 1478 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1479 } else {
077973c8
LDM		 1480 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1481 pipe_config->shared_dpll);
1482
7b19f544
MN		 1483 if (pll_id == DPLL_ID_ICL_TBTPLL)
1484 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1485 else
02c99d26 1486 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1487 }
1488
1489 pipe_config->port_clock = link_clock;
02c99d26 1490
51c83cfa
MN		 1491 ddi_dotclock_get(pipe_config);
1492}
1493
a9701a89
RV		 1494static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1495 struct intel_crtc_state *pipe_config)
1496{
1497 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1498 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1499 int link_clock;
a9701a89 1500
5e65216d
LDM		 1501 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1502 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1503 } else {
5e65216d 1504 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1505
1506 switch (link_clock) {
1507 case DPLL_CFGCR0_LINK_RATE_810:
1508 link_clock = 81000;
1509 break;
1510 case DPLL_CFGCR0_LINK_RATE_1080:
1511 link_clock = 108000;
1512 break;
1513 case DPLL_CFGCR0_LINK_RATE_1350:
1514 link_clock = 135000;
1515 break;
1516 case DPLL_CFGCR0_LINK_RATE_1620:
1517 link_clock = 162000;
1518 break;
1519 case DPLL_CFGCR0_LINK_RATE_2160:
1520 link_clock = 216000;
1521 break;
1522 case DPLL_CFGCR0_LINK_RATE_2700:
1523 link_clock = 270000;
1524 break;
1525 case DPLL_CFGCR0_LINK_RATE_3240:
1526 link_clock = 324000;
1527 break;
1528 case DPLL_CFGCR0_LINK_RATE_4050:
1529 link_clock = 405000;
1530 break;
1531 default:
1532 WARN(1, "Unsupported link rate\n");
1533 break;
1534 }
1535 link_clock *= 2;
1536 }
1537
1538 pipe_config->port_clock = link_clock;
1539
1540 ddi_dotclock_get(pipe_config);
1541}
1542
540e732c 1543static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1544 struct intel_crtc_state *pipe_config)
540e732c 1545{
947f4417
LDM		 1546 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1547 int link_clock;
540e732c 1548
947f4417
LDM		 1549 /*
1550 * ctrl1 register is already shifted for each pll, just use 0 to get
1551 * the internal shift for each field
1552 */
1553 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1554 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1555 } else {
947f4417
LDM		 1556 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1557 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1558
1559 switch (link_clock) {
71cd8423 1560 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1561 link_clock = 81000;
1562 break;
71cd8423 1563 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1564 link_clock = 108000;
1565 break;
71cd8423 1566 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1567 link_clock = 135000;
1568 break;
71cd8423 1569 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1570 link_clock = 162000;
1571 break;
71cd8423 1572 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1573 link_clock = 216000;
1574 break;
71cd8423 1575 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1576 link_clock = 270000;
1577 break;
1578 default:
1579 WARN(1, "Unsupported link rate\n");
1580 break;
1581 }
1582 link_clock *= 2;
1583 }
1584
1585 pipe_config->port_clock = link_clock;
1586
398a017e 1587 ddi_dotclock_get(pipe_config);
540e732c
S		 1588}
1589
3d51278a 1590static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1591 struct intel_crtc_state *pipe_config)
11578553 1592{
fac5e23e 1593 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1594 int link_clock = 0;
1595 u32 val, pll;
1596
c856052a 1597 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1598 switch (val & PORT_CLK_SEL_MASK) {
1599 case PORT_CLK_SEL_LCPLL_810:
1600 link_clock = 81000;
1601 break;
1602 case PORT_CLK_SEL_LCPLL_1350:
1603 link_clock = 135000;
1604 break;
1605 case PORT_CLK_SEL_LCPLL_2700:
1606 link_clock = 270000;
1607 break;
1608 case PORT_CLK_SEL_WRPLL1:
01403de3 1609 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1610 break;
1611 case PORT_CLK_SEL_WRPLL2:
01403de3 1612 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1613 break;
1614 case PORT_CLK_SEL_SPLL:
1615 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1616 if (pll == SPLL_PLL_FREQ_810MHz)
1617 link_clock = 81000;
1618 else if (pll == SPLL_PLL_FREQ_1350MHz)
1619 link_clock = 135000;
1620 else if (pll == SPLL_PLL_FREQ_2700MHz)
1621 link_clock = 270000;
1622 else {
1623 WARN(1, "bad spll freq\n");
1624 return;
1625 }
1626 break;
1627 default:
1628 WARN(1, "bad port clock sel\n");
1629 return;
1630 }
1631
1632 pipe_config->port_clock = link_clock * 2;
1633
398a017e 1634 ddi_dotclock_get(pipe_config);
11578553
JB		 1635}
1636
47c9877e 1637static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1638{
9e2c8475 1639 struct dpll clock;
aa610dcb 1640
aa610dcb 1641 clock.m1 = 2;
47c9877e
LDM		 1642 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1643 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1644 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1645 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1646 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1647 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1648
1649 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1650}
1651
1652static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1653 struct intel_crtc_state *pipe_config)
977bb38d 1654{
47c9877e
LDM		 1655 pipe_config->port_clock =
1656 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1657
398a017e 1658 ddi_dotclock_get(pipe_config);
977bb38d
S		 1659}
1660
35686a44
VS		 1661static void intel_ddi_clock_get(struct intel_encoder *encoder,
1662 struct intel_crtc_state *pipe_config)
3d51278a 1663{
0853723b 1664 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1665
2dd24a9c 1666 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1667 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1668 else if (IS_CANNONLAKE(dev_priv))
1669 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1670 else if (IS_GEN9_LP(dev_priv))
1671 bxt_ddi_clock_get(encoder, pipe_config);
1672 else if (IS_GEN9_BC(dev_priv))
1673 skl_ddi_clock_get(encoder, pipe_config);
1674 else if (INTEL_GEN(dev_priv) <= 8)
1675 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1676}
1677
3dc38eea 1678void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1679{
3dc38eea 1680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1682 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1683 u32 temp;
dae84799 1684
5448f53f
VS		 1685 if (!intel_crtc_has_dp_encoder(crtc_state))
1686 return;
4d1de975 1687
5448f53f
VS		 1688 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1689
1690 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1691
1692 if (crtc_state->limited_color_range)
1693 temp |= TRANS_MSA_CEA_RANGE;
1694
5448f53f
VS		 1695 switch (crtc_state->pipe_bpp) {
1696 case 18:
1697 temp |= TRANS_MSA_6_BPC;
1698 break;
1699 case 24:
1700 temp |= TRANS_MSA_8_BPC;
1701 break;
1702 case 30:
1703 temp |= TRANS_MSA_10_BPC;
1704 break;
1705 case 36:
1706 temp |= TRANS_MSA_12_BPC;
1707 break;
1708 default:
1709 MISSING_CASE(crtc_state->pipe_bpp);
1710 break;
dae84799 1711 }
5448f53f 1712
668b6c17
SS		 1713 /*
1714 * As per DP 1.2 spec section 2.3.4.3 while sending
1715 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1716 * colorspace information. The output colorspace encoding is BT601.
1717 */
1718 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1719 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
5448f53f 1720 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1721}
1722
3dc38eea
ACO		 1723void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1724 bool state)
0e32b39c 1725{
3dc38eea 1726 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1728 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1729 u32 temp;
7e732cac 1730
0e32b39c
DA		 1731 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1732 if (state == true)
1733 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1734 else
1735 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1736 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1737}
1738
3dc38eea 1739void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1740{
3dc38eea 1741 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1742 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1744 enum pipe pipe = crtc->pipe;
3dc38eea 1745 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1746 enum port port = encoder->port;
3d0c5005 1747 u32 temp;
8d9ddbcb 1748
ad80a810
PZ		 1749 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1750 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1751 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1752
3dc38eea 1753 switch (crtc_state->pipe_bpp) {
dfcef252 1754 case 18:
ad80a810 1755 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1756 break;
1757 case 24:
ad80a810 1758 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1759 break;
1760 case 30:
ad80a810 1761 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1762 break;
1763 case 36:
ad80a810 1764 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1765 break;
1766 default:
4e53c2e0 1767 BUG();
dfcef252 1768 }
72662e10 1769
3dc38eea 1770 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1771 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1772 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1773 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1774
e6f0bfc4
PZ		 1775 if (cpu_transcoder == TRANSCODER_EDP) {
1776 switch (pipe) {
1777 case PIPE_A:
c7670b10
PZ		 1778 /* On Haswell, can only use the always-on power well for
1779 * eDP when not using the panel fitter, and when not
1780 * using motion blur mitigation (which we don't
1781 * support). */
772c2a51 1782 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1783 (crtc_state->pch_pfit.enabled ||
1784 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1785 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1786 else
1787 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1788 break;
1789 case PIPE_B:
1790 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1791 break;
1792 case PIPE_C:
1793 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1794 break;
1795 default:
1796 BUG();
1797 break;
1798 }
1799 }
1800
742745f1 1801 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1802 if (crtc_state->has_hdmi_sink)
ad80a810 1803 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1804 else
ad80a810 1805 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1806
1807 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1808 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1809 if (crtc_state->hdmi_high_tmds_clock_ratio)
1810 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1811 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1812 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1813 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1814 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1815 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1816 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1817 } else {
742745f1
VS		 1818 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1819 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1820 }
1821
ad80a810 1822 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1823}
72662e10 1824
90c3e219 1825void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1826{
90c3e219
CT		 1827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1829 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1830 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1831 u32 val = I915_READ(reg);
8d9ddbcb 1832
0e32b39c 1833 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1834 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1835 I915_WRITE(reg, val);
90c3e219
CT		 1836
1837 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1838 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1839 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1840 /* Quirk time at 100ms for reliable operation */
1841 msleep(100);
1842 }
72662e10
ED		 1843}
1844
2320175f
SP		 1845int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1846 bool enable)
1847{
1848 struct drm_device *dev = intel_encoder->base.dev;
1849 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1850 intel_wakeref_t wakeref;
2320175f
SP		 1851 enum pipe pipe = 0;
1852 int ret = 0;
3d0c5005 1853 u32 tmp;
2320175f 1854
0e6e0be4
CW		 1855 wakeref = intel_display_power_get_if_enabled(dev_priv,
1856 intel_encoder->power_domain);
1857 if (WARN_ON(!wakeref))
2320175f
SP		 1858 return -ENXIO;
1859
1860 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1861 ret = -EIO;
1862 goto out;
1863 }
1864
1865 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1866 if (enable)
1867 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1868 else
1869 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1870 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1871out:
0e6e0be4 1872 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1873 return ret;
1874}
1875
bcbc889b
PZ		 1876bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1877{
1878 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1879 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1880 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1881 int type = intel_connector->base.connector_type;
0fce04c8 1882 enum port port = encoder->port;
bcbc889b 1883 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1884 intel_wakeref_t wakeref;
1885 enum pipe pipe = 0;
3d0c5005 1886 u32 tmp;
e27daab4 1887 bool ret;
bcbc889b 1888
0e6e0be4
CW		 1889 wakeref = intel_display_power_get_if_enabled(dev_priv,
1890 encoder->power_domain);
1891 if (!wakeref)
882244a3
PZ		 1892 return false;
1893
1524e93e 1894 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1895 ret = false;
1896 goto out;
1897 }
bcbc889b 1898
bc7e3525 1899 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1900 cpu_transcoder = TRANSCODER_EDP;
1901 else
1a240d4d 1902 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1903
1904 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1905
1906 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1907 case TRANS_DDI_MODE_SELECT_HDMI:
1908 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1909 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1910 break;
bcbc889b
PZ		 1911
1912 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1913 ret = type == DRM_MODE_CONNECTOR_eDP ||
1914 type == DRM_MODE_CONNECTOR_DisplayPort;
1915 break;
1916
0e32b39c
DA		 1917 case TRANS_DDI_MODE_SELECT_DP_MST:
1918 /* if the transcoder is in MST state then
1919 * connector isn't connected */
e27daab4
ID		 1920 ret = false;
1921 break;
bcbc889b
PZ		 1922
1923 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1924 ret = type == DRM_MODE_CONNECTOR_VGA;
1925 break;
bcbc889b
PZ		 1926
1927 default:
e27daab4
ID		 1928 ret = false;
1929 break;
bcbc889b 1930 }
e27daab4
ID		 1931
1932out:
0e6e0be4 1933 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 1934
1935 return ret;
bcbc889b
PZ		 1936}
1937
9199c322
ID		 1938static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1939 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 1940{
1941 struct drm_device *dev = encoder->base.dev;
fac5e23e 1942 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1943 enum port port = encoder->port;
0e6e0be4 1944 intel_wakeref_t wakeref;
3657e927 1945 enum pipe p;
85234cdc 1946 u32 tmp;
9199c322
ID		 1947 u8 mst_pipe_mask;
1948
1949 *pipe_mask = 0;
1950 *is_dp_mst = false;
85234cdc 1951
0e6e0be4
CW		 1952 wakeref = intel_display_power_get_if_enabled(dev_priv,
1953 encoder->power_domain);
1954 if (!wakeref)
9199c322 1955 return;
e27daab4 1956
fe43d3f5 1957 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 1958 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1959 goto out;
85234cdc 1960
bc7e3525 1961 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 1962 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1963
ad80a810 1964 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 1965 default:
1966 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1967 /* fallthrough */
ad80a810
PZ		 1968 case TRANS_DDI_EDP_INPUT_A_ON:
1969 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 1970 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 1971 break;
1972 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 1973 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 1974 break;
1975 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 1976 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 1977 break;
1978 }
1979
e27daab4
ID		 1980 goto out;
1981 }
0e32b39c 1982
9199c322 1983 mst_pipe_mask = 0;
3657e927 1984 for_each_pipe(dev_priv, p) {
9199c322 1985 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 1986
1987 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 1988
9199c322
ID		 1989 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1990 continue;
e27daab4 1991
9199c322
ID		 1992 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1993 TRANS_DDI_MODE_SELECT_DP_MST)
1994 mst_pipe_mask |= BIT(p);
e27daab4 1995
9199c322 1996 *pipe_mask |= BIT(p);
85234cdc
DV		 1997 }
1998
9199c322
ID		 1999 if (!*pipe_mask)
2000 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2001 port_name(port));
2002
2003 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2004 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2005 port_name(port), *pipe_mask);
2006 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2007 }
2008
2009 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2010 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2011 port_name(port), *pipe_mask, mst_pipe_mask);
2012 else
2013 *is_dp_mst = mst_pipe_mask;
85234cdc 2014
e27daab4 2015out:
9199c322 2016 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2017 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2018 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2019 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2020 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2021 DRM_ERROR("Port %c enabled but PHY powered down? "
2022 "(PHY_CTL %08x)\n", port_name(port), tmp);
2023 }
2024
0e6e0be4 2025 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2026}
e27daab4 2027
9199c322
ID		 2028bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2029 enum pipe *pipe)
2030{
2031 u8 pipe_mask;
2032 bool is_mst;
2033
2034 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2035
2036 if (is_mst || !pipe_mask)
2037 return false;
2038
2039 *pipe = ffs(pipe_mask) - 1;
2040
2041 return true;
85234cdc
DV		 2042}
2043
52528055 2044static inline enum intel_display_power_domain
bdaa29b6 2045intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2046{
9e3b5ce9 2047 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2048 * DC states enabled at the same time, while for driver initiated AUX
2049 * transfers we need the same AUX IOs to be powered but with DC states
2050 * disabled. Accordingly use the AUX power domain here which leaves DC
2051 * states enabled.
2052 * However, for non-A AUX ports the corresponding non-EDP transcoders
2053 * would have already enabled power well 2 and DC_OFF. This means we can
2054 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2055 * specific AUX_IO reference without powering up any extra wells.
2056 * Note that PSR is enabled only on Port A even though this function
2057 * returns the correct domain for other ports too.
2058 */
563d22a0 2059 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2060 intel_aux_power_domain(dig_port);
52528055
ID		 2061}
2062
3a52fb7e
ID		 2063static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2064 struct intel_crtc_state *crtc_state)
62b69566 2065{
8e4a3ad9 2066 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2067 struct intel_digital_port *dig_port;
62b69566 2068
52528055
ID		 2069 /*
2070 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2071 * happen since fake-MST encoders don't set their get_power_domains()
2072 * hook.
52528055
ID		 2073 */
2074 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2075 return;
b79ebe74
ID		 2076
2077 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2078 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2079
8e4a3ad9
ID		 2080 /*
2081 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2082 * ports.
2083 */
2084 if (intel_crtc_has_dp_encoder(crtc_state) ||
2085 intel_port_is_tc(dev_priv, encoder->port))
3a52fb7e
ID		 2086 intel_display_power_get(dev_priv,
2087 intel_ddi_main_link_aux_domain(dig_port));
52528055 2088
a24c62f9
MN		 2089 /*
2090 * VDSC power is needed when DSC is enabled
2091 */
2092 if (crtc_state->dsc_params.compression_enable)
3a52fb7e
ID		 2093 intel_display_power_get(dev_priv,
2094 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2095}
2096
3dc38eea 2097void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2098{
3dc38eea 2099 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2100 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2101 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2102 enum port port = encoder->port;
3dc38eea 2103 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2104
bb523fc0
PZ		 2105 if (cpu_transcoder != TRANSCODER_EDP)
2106 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2107 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2108}
2109
3dc38eea 2110void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2111{
3dc38eea
ACO		 2112 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2113 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2114
bb523fc0
PZ		 2115 if (cpu_transcoder != TRANSCODER_EDP)
2116 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2117 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2118}
2119
a7d8dbc0 2120static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2121 enum port port, u8 iboost)
f8896f5d 2122{
a7d8dbc0
VS		 2123 u32 tmp;
2124
2125 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2126 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2127 if (iboost)
2128 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2129 else
2130 tmp |= BALANCE_LEG_DISABLE(port);
2131 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2132}
2133
081dfcfa
VS		 2134static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2135 int level, enum intel_output_type type)
a7d8dbc0
VS		 2136{
2137 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2139 enum port port = encoder->port;
3d0c5005 2140 u8 iboost;
f8896f5d 2141
081dfcfa
VS		 2142 if (type == INTEL_OUTPUT_HDMI)
2143 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2144 else
2145 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2146
081dfcfa
VS		 2147 if (iboost == 0) {
2148 const struct ddi_buf_trans *ddi_translations;
2149 int n_entries;
2150
2151 if (type == INTEL_OUTPUT_HDMI)
2152 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2153 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2154 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2155 else
edba48fd 2156 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2157
21b39d2a
VS		 2158 if (WARN_ON_ONCE(!ddi_translations))
2159 return;
2160 if (WARN_ON_ONCE(level >= n_entries))
2161 level = n_entries - 1;
2162
081dfcfa 2163 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2164 }
2165
2166 /* Make sure that the requested I_boost is valid */
2167 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2168 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2169 return;
2170 }
2171
a7d8dbc0 2172 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2173
a7d8dbc0
VS		 2174 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2175 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2176}
2177
7d4f37b5
VS		 2178static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2179 int level, enum intel_output_type type)
96fb9f9b 2180{
7d4f37b5 2181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2182 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2183 enum port port = encoder->port;
043eaf36 2184 int n_entries;
7d4f37b5
VS		 2185
2186 if (type == INTEL_OUTPUT_HDMI)
2187 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2188 else if (type == INTEL_OUTPUT_EDP)
2189 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2190 else
2191 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2192
21b39d2a
VS		 2193 if (WARN_ON_ONCE(!ddi_translations))
2194 return;
2195 if (WARN_ON_ONCE(level >= n_entries))
2196 level = n_entries - 1;
2197
b6e08203
ACO		 2198 bxt_ddi_phy_set_signal_level(dev_priv, port,
2199 ddi_translations[level].margin,
2200 ddi_translations[level].scale,
2201 ddi_translations[level].enable,
2202 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2203}
2204
ffe5111e
VS		 2205u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2206{
2207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2208 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2209 enum port port = encoder->port;
ffe5111e
VS		 2210 int n_entries;
2211
2dd24a9c 2212 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2213 if (intel_port_is_combophy(dev_priv, port))
36cf89f5 2214 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
b265a2a6 2215 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2216 else
2217 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2218 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2219 if (encoder->type == INTEL_OUTPUT_EDP)
2220 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2221 else
2222 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2223 } else if (IS_GEN9_LP(dev_priv)) {
2224 if (encoder->type == INTEL_OUTPUT_EDP)
2225 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2226 else
2227 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2228 } else {
2229 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2230 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2231 else
edba48fd 2232 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2233 }
ffe5111e
VS		 2234
2235 if (WARN_ON(n_entries < 1))
2236 n_entries = 1;
2237 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2238 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2239
2240 return index_to_dp_signal_levels[n_entries - 1] &
2241 DP_TRAIN_VOLTAGE_SWING_MASK;
2242}
2243
4718a365
VS		 2244/*
2245 * We assume that the full set of pre-emphasis values can be
2246 * used on all DDI platforms. Should that change we need to
2247 * rethink this code.
2248 */
2249u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2250{
2251 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2253 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2255 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2257 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2259 default:
2260 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2261 }
2262}
2263
f3cf4ba4
VS		 2264static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2265 int level, enum intel_output_type type)
cf54ca8b 2266{
f3cf4ba4 2267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2268 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2269 enum port port = encoder->port;
f3cf4ba4
VS		 2270 int n_entries, ln;
2271 u32 val;
cf54ca8b 2272
f3cf4ba4 2273 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2274 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2275 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2276 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2277 else
2278 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2279
21b39d2a 2280 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2281 return;
21b39d2a 2282 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2283 level = n_entries - 1;
cf54ca8b
RV		 2284
2285 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2286 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2287 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2288 val |= SCALING_MODE_SEL(2);
2289 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2290
2291 /* Program PORT_TX_DW2 */
2292 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2293 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2294 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2295 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2296 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2297 /* Rcomp scalar is fixed as 0x98 for every table entry */
2298 val |= RCOMP_SCALAR(0x98);
2299 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2300
20303eb4 2301 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2302 /* We cannot write to GRP. It would overrite individual loadgen */
2303 for (ln = 0; ln < 4; ln++) {
9194e42a 2304 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2305 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2306 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2307 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2308 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2309 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2310 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2311 }
2312
20303eb4 2313 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2314 /* All DW5 values are fixed for every table entry */
2315 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2316 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2317 val |= RTERM_SELECT(6);
2318 val |= TAP3_DISABLE;
2319 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2320
20303eb4 2321 /* Program PORT_TX_DW7 */
cf54ca8b 2322 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2323 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2324 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2325 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2326}
2327
f3cf4ba4
VS		 2328static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2329 int level, enum intel_output_type type)
cf54ca8b 2330{
0091abc3 2331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2332 enum port port = encoder->port;
f3cf4ba4 2333 int width, rate, ln;
cf54ca8b 2334 u32 val;
0091abc3 2335
f3cf4ba4 2336 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2337 width = 4;
f3cf4ba4 2338 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2339 } else {
f3cf4ba4
VS		 2340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2341
2342 width = intel_dp->lane_count;
2343 rate = intel_dp->link_rate;
0091abc3 2344 }
cf54ca8b
RV		 2345
2346 /*
2347 * 1. If port type is eDP or DP,
2348 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2349 * else clear to 0b.
2350 */
2351 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2352 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2353 val |= COMMON_KEEPER_EN;
2354 else
2355 val &= ~COMMON_KEEPER_EN;
2356 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2357
2358 /* 2. Program loadgen select */
2359 /*
0091abc3
CT		 2360 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2361 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2362 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2363 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2364 */
0091abc3 2365 for (ln = 0; ln <= 3; ln++) {
9194e42a 2366 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2367 val &= ~LOADGEN_SELECT;
2368
a8e45a1c
NM		 2369 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2370 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2371 val |= LOADGEN_SELECT;
2372 }
9194e42a 2373 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2374 }
cf54ca8b
RV		 2375
2376 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2377 val = I915_READ(CNL_PORT_CL1CM_DW5);
2378 val |= SUS_CLOCK_CONFIG;
2379 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2380
2381 /* 4. Clear training enable to change swing values */
2382 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2383 val &= ~TX_TRAINING_EN;
2384 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2385
2386 /* 5. Program swing and de-emphasis */
f3cf4ba4 2387 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2388
2389 /* 6. Set training enable to trigger update */
2390 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2391 val |= TX_TRAINING_EN;
2392 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2393}
2394
fb5c8e9d 2395static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
b265a2a6
CT		 2396 u32 level, enum port port, int type,
2397 int rate)
fb5c8e9d 2398{
b265a2a6 2399 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2400 u32 n_entries, val;
2401 int ln;
2402
2403 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
b265a2a6 2404 rate, &n_entries);
fb5c8e9d
MN		 2405 if (!ddi_translations)
2406 return;
2407
2408 if (level >= n_entries) {
2409 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2410 level = n_entries - 1;
2411 }
2412
b265a2a6 2413 /* Set PORT_TX_DW5 */
fb5c8e9d 2414 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
b265a2a6
CT		 2415 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2416 TAP2_DISABLE | TAP3_DISABLE);
2417 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2418 val |= RTERM_SELECT(0x6);
b265a2a6 2419 val |= TAP3_DISABLE;
fb5c8e9d
MN		 2420 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2421
2422 /* Program PORT_TX_DW2 */
2423 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2424 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2425 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2426 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2427 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2428 /* Program Rcomp scalar for every table entry */
b265a2a6 2429 val |= RCOMP_SCALAR(0x98);
fb5c8e9d
MN		 2430 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2431
2432 /* Program PORT_TX_DW4 */
2433 /* We cannot write to GRP. It would overwrite individual loadgen. */
2434 for (ln = 0; ln <= 3; ln++) {
9194e42a 2435 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2436 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2437 CURSOR_COEFF_MASK);
b265a2a6
CT		 2438 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2439 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2440 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2441 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d 2442 }
b265a2a6
CT		 2443
2444 /* Program PORT_TX_DW7 */
2445 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2446 val &= ~N_SCALAR_MASK;
2447 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2448 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
fb5c8e9d
MN		 2449}
2450
2451static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2452 u32 level,
2453 enum intel_output_type type)
2454{
2455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2456 enum port port = encoder->port;
2457 int width = 0;
2458 int rate = 0;
2459 u32 val;
2460 int ln = 0;
2461
2462 if (type == INTEL_OUTPUT_HDMI) {
2463 width = 4;
2464 /* Rate is always < than 6GHz for HDMI */
2465 } else {
2466 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2467
2468 width = intel_dp->lane_count;
2469 rate = intel_dp->link_rate;
2470 }
2471
2472 /*
2473 * 1. If port type is eDP or DP,
2474 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2475 * else clear to 0b.
2476 */
2477 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2478 if (type == INTEL_OUTPUT_HDMI)
2479 val &= ~COMMON_KEEPER_EN;
2480 else
2481 val |= COMMON_KEEPER_EN;
2482 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2483
2484 /* 2. Program loadgen select */
2485 /*
2486 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2487 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2488 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2489 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2490 */
2491 for (ln = 0; ln <= 3; ln++) {
9194e42a 2492 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2493 val &= ~LOADGEN_SELECT;
2494
2495 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2496 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2497 val |= LOADGEN_SELECT;
2498 }
9194e42a 2499 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d
MN		 2500 }
2501
2502 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2503 val = I915_READ(ICL_PORT_CL_DW5(port));
2504 val |= SUS_CLOCK_CONFIG;
2505 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2506
2507 /* 4. Clear training enable to change swing values */
2508 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2509 val &= ~TX_TRAINING_EN;
2510 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2511
2512 /* 5. Program swing and de-emphasis */
b265a2a6 2513 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
fb5c8e9d
MN		 2514
2515 /* 6. Set training enable to trigger update */
2516 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2517 val |= TX_TRAINING_EN;
2518 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2519}
2520
07685c82
MN		 2521static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2522 int link_clock,
2523 u32 level)
2524{
2525 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2526 enum port port = encoder->port;
2527 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2528 u32 n_entries, val;
2529 int ln;
2530
2531 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2532 ddi_translations = icl_mg_phy_ddi_translations;
2533 /* The table does not have values for level 3 and level 9. */
2534 if (level >= n_entries || level == 3 || level == 9) {
2535 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2536 level, n_entries - 2);
2537 level = n_entries - 2;
2538 }
2539
2540 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2541 for (ln = 0; ln < 2; ln++) {
58106b7d 2542 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2543 val &= ~CRI_USE_FS32;
58106b7d 2544 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2545
58106b7d 2546 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2547 val &= ~CRI_USE_FS32;
58106b7d 2548 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2549 }
2550
2551 /* Program MG_TX_SWINGCTRL with values from vswing table */
2552 for (ln = 0; ln < 2; ln++) {
58106b7d 2553 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2554 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2555 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2556 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2557 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2558
58106b7d 2559 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2560 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2561 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2562 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2563 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2564 }
2565
2566 /* Program MG_TX_DRVCTRL with values from vswing table */
2567 for (ln = 0; ln < 2; ln++) {
58106b7d 2568 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2569 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2570 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2571 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2572 ddi_translations[level].cri_txdeemph_override_5_0) |
2573 CRI_TXDEEMPH_OVERRIDE_11_6(
2574 ddi_translations[level].cri_txdeemph_override_11_6) |
2575 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2576 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2577
58106b7d 2578 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2579 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2580 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2581 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2582 ddi_translations[level].cri_txdeemph_override_5_0) |
2583 CRI_TXDEEMPH_OVERRIDE_11_6(
2584 ddi_translations[level].cri_txdeemph_override_11_6) |
2585 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2586 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2587
2588 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2589 }
2590
2591 /*
2592 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2593 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2594 * values from table for which TX1 and TX2 enabled.
2595 */
2596 for (ln = 0; ln < 2; ln++) {
58106b7d 2597 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2598 if (link_clock < 300000)
2599 val |= CFG_LOW_RATE_LKREN_EN;
2600 else
2601 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2602 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2603 }
2604
2605 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2606 for (ln = 0; ln < 2; ln++) {
58106b7d 2607 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2608 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2609 if (link_clock <= 500000) {
2610 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2611 } else {
2612 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2613 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2614 }
58106b7d 2615 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2616
58106b7d 2617 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2618 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2619 if (link_clock <= 500000) {
2620 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2621 } else {
2622 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2623 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2624 }
58106b7d 2625 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2626 }
2627
2628 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2629 for (ln = 0; ln < 2; ln++) {
58106b7d 2630 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2631 val |= CRI_CALCINIT;
58106b7d 2632 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2633
58106b7d 2634 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2635 val |= CRI_CALCINIT;
58106b7d 2636 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2637 }
2638}
2639
2640static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2641 int link_clock,
2642 u32 level,
fb5c8e9d
MN		 2643 enum intel_output_type type)
2644{
176597a1 2645 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2646 enum port port = encoder->port;
2647
176597a1 2648 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2649 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2650 else
07685c82 2651 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2652}
2653
3d0c5005 2654static u32 translate_signal_level(int signal_levels)
f8896f5d 2655{
97eeb872 2656 int i;
f8896f5d 2657
97eeb872
VS		 2658 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2659 if (index_to_dp_signal_levels[i] == signal_levels)
2660 return i;
f8896f5d
DW		 2661 }
2662
97eeb872
VS		 2663 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2664 signal_levels);
2665
2666 return 0;
f8896f5d
DW		 2667}
2668
3d0c5005 2669static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2670{
3d0c5005 2671 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2672 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2673 DP_TRAIN_PRE_EMPHASIS_MASK);
2674
2675 return translate_signal_level(signal_levels);
2676}
2677
d509af6c 2678u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2679{
2680 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2681 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2682 struct intel_encoder *encoder = &dport->base;
d02ace87 2683 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2684
2dd24a9c 2685 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2686 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2687 level, encoder->type);
fb5c8e9d 2688 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2689 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2690 else
7d4f37b5 2691 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2692
2693 return 0;
2694}
2695
3d0c5005 2696u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2697{
2698 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2699 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2700 struct intel_encoder *encoder = &dport->base;
d02ace87 2701 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2702
b976dc53 2703 if (IS_GEN9_BC(dev_priv))
081dfcfa 2704 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2705
f8896f5d
DW		 2706 return DDI_BUF_TRANS_SELECT(level);
2707}
2708
bb1c7edc 2709static inline
3d0c5005
JN		 2710u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2711 enum port port)
bb1c7edc
MK		 2712{
2713 if (intel_port_is_combophy(dev_priv, port)) {
2714 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2715 } else if (intel_port_is_tc(dev_priv, port)) {
2716 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2717
2718 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2719 }
2720
2721 return 0;
2722}
2723
3b8c0d5b
JN		 2724static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2725 const struct intel_crtc_state *crtc_state)
c27e917e 2726{
3b8c0d5b 2727 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2728 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3b8c0d5b
JN		 2729 enum port port = encoder->port;
2730 u32 val;
c27e917e 2731
3b8c0d5b 2732 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2733
3b8c0d5b
JN		 2734 val = I915_READ(DPCLKA_CFGCR0_ICL);
2735 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2736
3b8c0d5b
JN		 2737 if (intel_port_is_combophy(dev_priv, port)) {
2738 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2739 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
c27e917e 2740 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
3b8c0d5b 2741 POSTING_READ(DPCLKA_CFGCR0_ICL);
c27e917e 2742 }
3b8c0d5b
JN		 2743
2744 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2745 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2746
2747 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2748}
2749
3b8c0d5b 2750static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2751{
3b8c0d5b
JN		 2752 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2753 enum port port = encoder->port;
2754 u32 val;
c27e917e 2755
3b8c0d5b 2756 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2757
3b8c0d5b
JN		 2758 val = I915_READ(DPCLKA_CFGCR0_ICL);
2759 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2760 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
c27e917e 2761
3b8c0d5b 2762 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2763}
2764
70332ac5
ID		 2765void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2766{
2767 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2768 u32 val;
1dd07e56
ID		 2769 enum port port;
2770 u32 port_mask;
2771 bool ddi_clk_needed;
30f5ccfa
ID		 2772
2773 /*
2774 * In case of DP MST, we sanitize the primary encoder only, not the
2775 * virtual ones.
2776 */
2777 if (encoder->type == INTEL_OUTPUT_DP_MST)
2778 return;
2779
30f5ccfa
ID		 2780 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2781 u8 pipe_mask;
2782 bool is_mst;
2783
2784 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2785 /*
2786 * In the unlikely case that BIOS enables DP in MST mode, just
2787 * warn since our MST HW readout is incomplete.
2788 */
2789 if (WARN_ON(is_mst))
2790 return;
2791 }
70332ac5 2792
1dd07e56
ID		 2793 port_mask = BIT(encoder->port);
2794 ddi_clk_needed = encoder->base.crtc;
70332ac5 2795
1dd07e56
ID		 2796 if (encoder->type == INTEL_OUTPUT_DSI) {
2797 struct intel_encoder *other_encoder;
70332ac5 2798
1dd07e56
ID		 2799 port_mask = intel_dsi_encoder_ports(encoder);
2800 /*
2801 * Sanity check that we haven't incorrectly registered another
2802 * encoder using any of the ports of this DSI encoder.
2803 */
2804 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2805 if (other_encoder == encoder)
2806 continue;
2807
2808 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2809 return;
2810 }
2811 /*
942d1cf4
VK		 2812 * For DSI we keep the ddi clocks gated
2813 * except during enable/disable sequence.
1dd07e56 2814 */
942d1cf4 2815 ddi_clk_needed = false;
1dd07e56
ID		 2816 }
2817
2818 val = I915_READ(DPCLKA_CFGCR0_ICL);
2819 for_each_port_masked(port, port_mask) {
2820 bool ddi_clk_ungated = !(val &
2821 icl_dpclka_cfgcr0_clk_off(dev_priv,
2822 port));
2823
2824 if (ddi_clk_needed == ddi_clk_ungated)
2825 continue;
2826
2827 /*
2828 * Punt on the case now where clock is gated, but it would
2829 * be needed by the port. Something else is really broken then.
2830 */
2831 if (WARN_ON(ddi_clk_needed))
2832 continue;
2833
2834 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2835 port_name(port));
2836 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2837 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2838 }
70332ac5
ID		 2839}
2840
d7c530b2 2841static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2842 const struct intel_crtc_state *crtc_state)
6441ab5f 2843{
e404ba8d 2844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2845 enum port port = encoder->port;
3d0c5005 2846 u32 val;
0e5fa646 2847 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2848
c856052a
ACO		 2849 if (WARN_ON(!pll))
2850 return;
2851
04bf68bb 2852 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2853
2dd24a9c 2854 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2855 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2856 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2857 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c27e917e 2858 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2859 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2860 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2861 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2862 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2863 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2864
555e38d2
RV		 2865 /*
2866 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2867 * This step and the step before must be done with separate
2868 * register writes.
2869 */
2870 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2871 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2872 I915_WRITE(DPCLKA_CFGCR0, val);
2873 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2874 /* DDI -> PLL mapping */
efa80add
S		 2875 val = I915_READ(DPLL_CTRL2);
2876
2877 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2878 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2879 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2880 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2881
2882 I915_WRITE(DPLL_CTRL2, val);
5416d871 2883
c56b89f1 2884 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2885 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2886 }
8edcda12
RV		 2887
2888 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2889}
2890
6b8506d5
VS		 2891static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2892{
2893 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2894 enum port port = encoder->port;
6b8506d5 2895
2dd24a9c 2896 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2897 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2898 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2899 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2900 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2901 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2902 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2903 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2904 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2905 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2906 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2907 }
6b8506d5
VS		 2908}
2909
cb9ff519
ID		 2910static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2911{
2912 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2913 enum port port = dig_port->base.port;
2914 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2915 u32 val;
9c11b121 2916 int ln;
cb9ff519
ID		 2917
2918 if (tc_port == PORT_TC_NONE)
2919 return;
2920
9c11b121
ID		 2921 for (ln = 0; ln < 2; ln++) {
2922 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2923 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2924 MG_DP_MODE_CFG_TRPWR_GATING |
2925 MG_DP_MODE_CFG_CLNPWR_GATING |
2926 MG_DP_MODE_CFG_DIGPWR_GATING |
2927 MG_DP_MODE_CFG_GAONPWR_GATING;
9c11b121 2928 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2929 }
2930
2931 val = I915_READ(MG_MISC_SUS0(tc_port));
2932 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2933 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2934 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2935 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2936 MG_MISC_SUS0_CFG_TRPWR_GATING |
2937 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2938 MG_MISC_SUS0_CFG_DGPWR_GATING;
2939 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2940}
2941
2942static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2943{
2944 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2945 enum port port = dig_port->base.port;
2946 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2947 u32 val;
9c11b121 2948 int ln;
cb9ff519
ID		 2949
2950 if (tc_port == PORT_TC_NONE)
2951 return;
2952
9c11b121
ID		 2953 for (ln = 0; ln < 2; ln++) {
2954 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2955 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2956 MG_DP_MODE_CFG_TRPWR_GATING |
2957 MG_DP_MODE_CFG_CLNPWR_GATING |
2958 MG_DP_MODE_CFG_DIGPWR_GATING |
2959 MG_DP_MODE_CFG_GAONPWR_GATING);
9c11b121 2960 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2961 }
2962
2963 val = I915_READ(MG_MISC_SUS0(tc_port));
2964 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2965 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2966 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2967 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2968 MG_MISC_SUS0_CFG_TRPWR_GATING |
2969 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2970 MG_MISC_SUS0_CFG_DGPWR_GATING);
2971 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2972}
2973
93b662d3
ID		 2974static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2975{
2976 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2977 enum port port = intel_dig_port->base.port;
2978 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2979 u32 ln0, ln1, lane_info;
2980
2981 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2982 return;
2983
37fc7845
JRS		 2984 ln0 = I915_READ(MG_DP_MODE(0, port));
2985 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3
ID		 2986
2987 switch (intel_dig_port->tc_type) {
2988 case TC_PORT_TYPEC:
2989 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2990 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2991
2992 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2993 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2994 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2995
2996 switch (lane_info) {
2997 case 0x1:
2998 case 0x4:
2999 break;
3000 case 0x2:
3001 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3002 break;
3003 case 0x3:
3004 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3005 MG_DP_MODE_CFG_DP_X2_MODE;
3006 break;
3007 case 0x8:
3008 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3009 break;
3010 case 0xC:
3011 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012 MG_DP_MODE_CFG_DP_X2_MODE;
3013 break;
3014 case 0xF:
3015 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3016 MG_DP_MODE_CFG_DP_X2_MODE;
3017 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3018 MG_DP_MODE_CFG_DP_X2_MODE;
3019 break;
3020 default:
3021 MISSING_CASE(lane_info);
3022 }
3023 break;
3024
3025 case TC_PORT_LEGACY:
3026 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3027 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3028 break;
3029
3030 default:
3031 MISSING_CASE(intel_dig_port->tc_type);
3032 return;
3033 }
3034
37fc7845
JRS		 3035 I915_WRITE(MG_DP_MODE(0, port), ln0);
3036 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3037}
3038
a322b975
AS		 3039static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3040 const struct intel_crtc_state *crtc_state)
3041{
3042 if (!crtc_state->fec_enable)
3043 return;
3044
3045 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3046 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3047}
3048
5c44b938
AS		 3049static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3050 const struct intel_crtc_state *crtc_state)
3051{
3052 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3053 enum port port = encoder->port;
3054 u32 val;
3055
3056 if (!crtc_state->fec_enable)
3057 return;
3058
3059 val = I915_READ(DP_TP_CTL(port));
3060 val |= DP_TP_CTL_FEC_ENABLE;
3061 I915_WRITE(DP_TP_CTL(port), val);
3062
97a04e0d 3063 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
5c44b938
AS		 3064 DP_TP_STATUS_FEC_ENABLE_LIVE,
3065 DP_TP_STATUS_FEC_ENABLE_LIVE,
3066 1))
3067 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3068}
3069
d6a09cee
AS		 3070static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3071 const struct intel_crtc_state *crtc_state)
3072{
3073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3074 enum port port = encoder->port;
3075 u32 val;
3076
3077 if (!crtc_state->fec_enable)
3078 return;
3079
3080 val = I915_READ(DP_TP_CTL(port));
3081 val &= ~DP_TP_CTL_FEC_ENABLE;
3082 I915_WRITE(DP_TP_CTL(port), val);
3083 POSTING_READ(DP_TP_CTL(port));
3084}
3085
ba88d153 3086static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3087 const struct intel_crtc_state *crtc_state,
3088 const struct drm_connector_state *conn_state)
e404ba8d 3089{
ba88d153
MN		 3090 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3092 enum port port = encoder->port;
62b69566 3093 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3094 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3095 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3096
45e0327e 3097 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3098
45e0327e
VS		 3099 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3100 crtc_state->lane_count, is_mst);
680b71c2
VS		 3101
3102 intel_edp_panel_on(intel_dp);
32bdc400 3103
0e5fa646 3104 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3105
3106 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3107
93b662d3 3108 icl_program_mg_dp_mode(dig_port);
bc334d91 3109 icl_disable_phy_clock_gating(dig_port);
340a44be 3110
2dd24a9c 3111 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3112 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3113 level, encoder->type);
fb5c8e9d 3114 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3115 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3116 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3117 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3118 else
3a6d84e6 3119 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3120
cfda08cd
ID		 3121 if (intel_port_is_combophy(dev_priv, port)) {
3122 bool lane_reversal =
3123 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3124
3125 intel_combo_phy_power_up_lanes(dev_priv, port, false,
3126 crtc_state->lane_count,
3127 lane_reversal);
3128 }
3129
ba88d153 3130 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3131 if (!is_mst)
3132 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3133 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3134 true);
a322b975 3135 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3136 intel_dp_start_link_train(intel_dp);
3137 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3138 intel_dp_stop_link_train(intel_dp);
afb2c443 3139
5c44b938
AS		 3140 intel_ddi_enable_fec(encoder, crtc_state);
3141
bc334d91
PZ		 3142 icl_enable_phy_clock_gating(dig_port);
3143
2b5cf4ef
ID		 3144 if (!is_mst)
3145 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3146
3147 intel_dsc_enable(encoder, crtc_state);
ba88d153 3148}
901c2daf 3149
ba88d153 3150static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3151 const struct intel_crtc_state *crtc_state,
45e0327e 3152 const struct drm_connector_state *conn_state)
ba88d153 3153{
f99be1b3
VS		 3154 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3155 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3157 enum port port = encoder->port;
ba88d153 3158 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3159 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3160
ba88d153 3161 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3162 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3163
3164 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3165
93b662d3 3166 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3167 icl_disable_phy_clock_gating(dig_port);
3168
2dd24a9c 3169 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3170 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3171 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3172 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3173 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3174 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3175 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3176 else
7ea79333 3177 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3178
cb9ff519
ID		 3179 icl_enable_phy_clock_gating(dig_port);
3180
2f7460a7 3181 if (IS_GEN9_BC(dev_priv))
081dfcfa 3182 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3183
c7373764
ID		 3184 intel_ddi_enable_pipe_clock(crtc_state);
3185
790ea70c 3186 intel_dig_port->set_infoframes(encoder,
45e0327e 3187 crtc_state->has_infoframe,
f99be1b3 3188 crtc_state, conn_state);
ba88d153 3189}
32bdc400 3190
1524e93e 3191static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3192 const struct intel_crtc_state *crtc_state,
5f88a9c6 3193 const struct drm_connector_state *conn_state)
ba88d153 3194{
45e0327e
VS		 3195 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3197 enum pipe pipe = crtc->pipe;
30cf6db8 3198
1939ba51
VS		 3199 /*
3200 * When called from DP MST code:
3201 * - conn_state will be NULL
3202 * - encoder will be the main encoder (ie. mst->primary)
3203 * - the main connector associated with this port
3204 * won't be active or linked to a crtc
3205 * - crtc_state will be the state of the first stream to
3206 * be activated on this port, and it may not be the same
3207 * stream that will be deactivated last, but each stream
3208 * should have a state that is identical when it comes to
3209 * the DP link parameteres
3210 */
3211
45e0327e 3212 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3213
3b8c0d5b
JN		 3214 if (INTEL_GEN(dev_priv) >= 11)
3215 icl_map_plls_to_ports(encoder, crtc_state);
3216
364a3fe1
JN		 3217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3218
06c812d7 3219 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3220 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3221 } else {
3222 struct intel_lspcon *lspcon =
3223 enc_to_intel_lspcon(&encoder->base);
3224
45e0327e 3225 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3226 if (lspcon->active) {
3227 struct intel_digital_port *dig_port =
3228 enc_to_dig_port(&encoder->base);
3229
3230 dig_port->set_infoframes(encoder,
3231 crtc_state->has_infoframe,
3232 crtc_state, conn_state);
3233 }
3234 }
6441ab5f
PZ		 3235}
3236
d6a09cee
AS		 3237static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3238 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3239{
3240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3241 enum port port = encoder->port;
e725f645
VS		 3242 bool wait = false;
3243 u32 val;
3244
3245 val = I915_READ(DDI_BUF_CTL(port));
3246 if (val & DDI_BUF_CTL_ENABLE) {
3247 val &= ~DDI_BUF_CTL_ENABLE;
3248 I915_WRITE(DDI_BUF_CTL(port), val);
3249 wait = true;
3250 }
3251
3252 val = I915_READ(DP_TP_CTL(port));
3253 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3254 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3255 I915_WRITE(DP_TP_CTL(port), val);
3256
d6a09cee
AS		 3257 /* Disable FEC in DP Sink */
3258 intel_ddi_disable_fec_state(encoder, crtc_state);
3259
e725f645
VS		 3260 if (wait)
3261 intel_wait_ddi_buf_idle(dev_priv, port);
3262}
3263
f45f3da7
VS		 3264static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3265 const struct intel_crtc_state *old_crtc_state,
3266 const struct drm_connector_state *old_conn_state)
6441ab5f 3267{
f45f3da7
VS		 3268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3269 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3270 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3271 bool is_mst = intel_crtc_has_type(old_crtc_state,
3272 INTEL_OUTPUT_DP_MST);
2886e93f 3273
2b5cf4ef
ID		 3274 if (!is_mst) {
3275 intel_ddi_disable_pipe_clock(old_crtc_state);
3276 /*
3277 * Power down sink before disabling the port, otherwise we end
3278 * up getting interrupts from the sink on detecting link loss.
3279 */
be1c63c8 3280 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3281 }
c5f93fcf 3282
d6a09cee 3283 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3284
f45f3da7
VS		 3285 intel_edp_panel_vdd_on(intel_dp);
3286 intel_edp_panel_off(intel_dp);
a836bdf9 3287
0e6e0be4
CW		 3288 intel_display_power_put_unchecked(dev_priv,
3289 dig_port->ddi_io_power_domain);
c5f93fcf 3290
f45f3da7
VS		 3291 intel_ddi_clk_disable(encoder);
3292}
c5f93fcf 3293
f45f3da7
VS		 3294static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3295 const struct intel_crtc_state *old_crtc_state,
3296 const struct drm_connector_state *old_conn_state)
3297{
3298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3299 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3300 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3301
790ea70c 3302 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3303 old_crtc_state, old_conn_state);
3304
afb2c443
ID		 3305 intel_ddi_disable_pipe_clock(old_crtc_state);
3306
d6a09cee 3307 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3308
0e6e0be4
CW		 3309 intel_display_power_put_unchecked(dev_priv,
3310 dig_port->ddi_io_power_domain);
b2ccb822 3311
f45f3da7
VS		 3312 intel_ddi_clk_disable(encoder);
3313
3314 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3315}
3316
3317static void intel_ddi_post_disable(struct intel_encoder *encoder,
3318 const struct intel_crtc_state *old_crtc_state,
3319 const struct drm_connector_state *old_conn_state)
3320{
3b8c0d5b
JN		 3321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3322
f45f3da7 3323 /*
1939ba51
VS		 3324 * When called from DP MST code:
3325 * - old_conn_state will be NULL
3326 * - encoder will be the main encoder (ie. mst->primary)
3327 * - the main connector associated with this port
3328 * won't be active or linked to a crtc
3329 * - old_crtc_state will be the state of the last stream to
3330 * be deactivated on this port, and it may not be the same
3331 * stream that was activated last, but each stream
3332 * should have a state that is identical when it comes to
3333 * the DP link parameteres
f45f3da7 3334 */
1939ba51
VS		 3335
3336 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3337 intel_ddi_post_disable_hdmi(encoder,
3338 old_crtc_state, old_conn_state);
3339 else
3340 intel_ddi_post_disable_dp(encoder,
3341 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3342
3343 if (INTEL_GEN(dev_priv) >= 11)
3344 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3345}
3346
1524e93e 3347void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3348 const struct intel_crtc_state *old_crtc_state,
3349 const struct drm_connector_state *old_conn_state)
b7076546 3350{
1524e93e 3351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3352 u32 val;
b7076546
ML		 3353
3354 /*
3355 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3356 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3357 * step 13 is the correct place for it. Step 18 is where it was
3358 * originally before the BUN.
3359 */
3360 val = I915_READ(FDI_RX_CTL(PIPE_A));
3361 val &= ~FDI_RX_ENABLE;
3362 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3363
d6a09cee 3364 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3365 intel_ddi_clk_disable(encoder);
b7076546
ML		 3366
3367 val = I915_READ(FDI_RX_MISC(PIPE_A));
3368 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3369 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3370 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3371
3372 val = I915_READ(FDI_RX_CTL(PIPE_A));
3373 val &= ~FDI_PCDCLK;
3374 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3375
3376 val = I915_READ(FDI_RX_CTL(PIPE_A));
3377 val &= ~FDI_RX_PLL_ENABLE;
3378 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3379}
3380
15d05f0e
VS		 3381static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3382 const struct intel_crtc_state *crtc_state,
3383 const struct drm_connector_state *conn_state)
72662e10 3384{
15d05f0e
VS		 3385 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3386 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3387 enum port port = encoder->port;
72662e10 3388
15d05f0e
VS		 3389 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3390 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3391
15d05f0e
VS		 3392 intel_edp_backlight_on(crtc_state, conn_state);
3393 intel_psr_enable(intel_dp, crtc_state);
3394 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3395
15d05f0e
VS		 3396 if (crtc_state->has_audio)
3397 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3398}
3399
8f19b401
ID		 3400static i915_reg_t
3401gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3402 enum port port)
3403{
3404 static const i915_reg_t regs[] = {
3405 [PORT_A] = CHICKEN_TRANS_EDP,
3406 [PORT_B] = CHICKEN_TRANS_A,
3407 [PORT_C] = CHICKEN_TRANS_B,
3408 [PORT_D] = CHICKEN_TRANS_C,
3409 [PORT_E] = CHICKEN_TRANS_A,
3410 };
3411
3412 WARN_ON(INTEL_GEN(dev_priv) < 9);
3413
3414 if (WARN_ON(port < PORT_A || port > PORT_E))
3415 port = PORT_A;
3416
3417 return regs[port];
3418}
3419
15d05f0e
VS		 3420static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3421 const struct intel_crtc_state *crtc_state,
3422 const struct drm_connector_state *conn_state)
3423{
3424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3425 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3426 struct drm_connector *connector = conn_state->connector;
0fce04c8 3427 enum port port = encoder->port;
15d05f0e 3428
277ab5ab
VS		 3429 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3430 crtc_state->hdmi_high_tmds_clock_ratio,
3431 crtc_state->hdmi_scrambling))
3432 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3433 connector->base.id, connector->name);
15d05f0e 3434
0519c102
VS		 3435 /* Display WA #1143: skl,kbl,cfl */
3436 if (IS_GEN9_BC(dev_priv)) {
3437 /*
3438 * For some reason these chicken bits have been
3439 * stuffed into a transcoder register, event though
3440 * the bits affect a specific DDI port rather than
3441 * a specific transcoder.
3442 */
8f19b401 3443 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3444 u32 val;
3445
8f19b401 3446 val = I915_READ(reg);
0519c102
VS		 3447
3448 if (port == PORT_E)
3449 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3450 DDIE_TRAINING_OVERRIDE_VALUE;
3451 else
3452 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3453 DDI_TRAINING_OVERRIDE_VALUE;
3454
8f19b401
ID		 3455 I915_WRITE(reg, val);
3456 POSTING_READ(reg);
0519c102
VS		 3457
3458 udelay(1);
3459
3460 if (port == PORT_E)
3461 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3462 DDIE_TRAINING_OVERRIDE_VALUE);
3463 else
3464 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3465 DDI_TRAINING_OVERRIDE_VALUE);
3466
8f19b401 3467 I915_WRITE(reg, val);
0519c102
VS		 3468 }
3469
15d05f0e
VS		 3470 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3471 * are ignored so nothing special needs to be done besides
3472 * enabling the port.
3473 */
3474 I915_WRITE(DDI_BUF_CTL(port),
3475 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3476
15d05f0e
VS		 3477 if (crtc_state->has_audio)
3478 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3479}
3480
3481static void intel_enable_ddi(struct intel_encoder *encoder,
3482 const struct intel_crtc_state *crtc_state,
3483 const struct drm_connector_state *conn_state)
3484{
3485 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3486 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3487 else
3488 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3489
3490 /* Enable hdcp if it's desired */
3491 if (conn_state->content_protection ==
3492 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3493 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3494}
3495
33f083f0
VS		 3496static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3497 const struct intel_crtc_state *old_crtc_state,
3498 const struct drm_connector_state *old_conn_state)
5ab432ef 3499{
33f083f0 3500 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3501
edb2e530
VS		 3502 intel_dp->link_trained = false;
3503
37255d8d 3504 if (old_crtc_state->has_audio)
8ec47de2
VS		 3505 intel_audio_codec_disable(encoder,
3506 old_crtc_state, old_conn_state);
2831d842 3507
33f083f0
VS		 3508 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3509 intel_psr_disable(intel_dp, old_crtc_state);
3510 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3511 /* Disable the decompression in DP Sink */
3512 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3513 false);
33f083f0 3514}
15953637 3515
33f083f0
VS		 3516static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3517 const struct intel_crtc_state *old_crtc_state,
3518 const struct drm_connector_state *old_conn_state)
3519{
277ab5ab
VS		 3520 struct drm_connector *connector = old_conn_state->connector;
3521
33f083f0 3522 if (old_crtc_state->has_audio)
8ec47de2
VS		 3523 intel_audio_codec_disable(encoder,
3524 old_crtc_state, old_conn_state);
d6c50ff8 3525
277ab5ab
VS		 3526 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3527 false, false))
3528 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3529 connector->base.id, connector->name);
33f083f0
VS		 3530}
3531
3532static void intel_disable_ddi(struct intel_encoder *encoder,
3533 const struct intel_crtc_state *old_crtc_state,
3534 const struct drm_connector_state *old_conn_state)
3535{
ee5e5e7a
SP		 3536 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3537
33f083f0
VS		 3538 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3539 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3540 else
3541 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3542}
79f689aa 3543
2ef82327
HG		 3544static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3545 const struct intel_crtc_state *crtc_state,
3546 const struct drm_connector_state *conn_state)
3547{
3548 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3549
5aa2c9ae
VS		 3550 intel_ddi_set_pipe_settings(crtc_state);
3551
23ec9f52 3552 intel_psr_update(intel_dp, crtc_state);
2ef82327 3553 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3554
3555 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3556}
3557
3558static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3559 const struct intel_crtc_state *crtc_state,
3560 const struct drm_connector_state *conn_state)
3561{
3562 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3563 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1
R		 3564
3565 if (conn_state->content_protection ==
3566 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3567 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3568 else if (conn_state->content_protection ==
3569 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3570 intel_hdcp_disable(to_intel_connector(conn_state->connector));
2ef82327
HG		 3571}
3572
03ad7d88
MN		 3573static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3574 const struct intel_crtc_state *pipe_config,
3575 enum port port)
3576{
3577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3578 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3579 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3580 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3581 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3582
3583 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3584 switch (pipe_config->lane_count) {
3585 case 1:
3586 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3587 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3588 break;
3589 case 2:
3590 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3591 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3592 break;
3593 case 4:
3594 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3595 break;
3596 default:
3597 MISSING_CASE(pipe_config->lane_count);
3598 }
3599 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3600}
3601
bdaa29b6
ID		 3602static void
3603intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3604 const struct intel_crtc_state *crtc_state,
3605 const struct drm_connector_state *conn_state)
03ad7d88 3606{
bdaa29b6 3607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3608 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bdaa29b6
ID		 3609 enum port port = encoder->port;
3610
8e4a3ad9
ID		 3611 if (intel_crtc_has_dp_encoder(crtc_state) ||
3612 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6
ID		 3613 intel_display_power_get(dev_priv,
3614 intel_ddi_main_link_aux_domain(dig_port));
3615
3616 if (IS_GEN9_LP(dev_priv))
3617 bxt_ddi_phy_set_lane_optim_mask(encoder,
3618 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3619
3620 /*
3621 * Program the lane count for static/dynamic connections on Type-C ports.
3622 * Skip this step for TBT.
3623 */
3624 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3625 dig_port->tc_type == TC_PORT_TBT)
3626 return;
3627
bdaa29b6
ID		 3628 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3629}
3630
3631static void
3632intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3633 const struct intel_crtc_state *crtc_state,
3634 const struct drm_connector_state *conn_state)
3635{
3636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3637 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3638
3639 if (intel_crtc_has_dp_encoder(crtc_state) ||
3640 intel_port_is_tc(dev_priv, encoder->port))
0e6e0be4
CW		 3641 intel_display_power_put_unchecked(dev_priv,
3642 intel_ddi_main_link_aux_domain(dig_port));
03ad7d88
MN		 3643}
3644
ad64217b 3645void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3646{
ad64217b
ACO		 3647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648 struct drm_i915_private *dev_priv =
3649 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3650 enum port port = intel_dig_port->base.port;
3d0c5005 3651 u32 val;
f3e227df 3652 bool wait = false;
c19b0669
PZ		 3653
3654 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3655 val = I915_READ(DDI_BUF_CTL(port));
3656 if (val & DDI_BUF_CTL_ENABLE) {
3657 val &= ~DDI_BUF_CTL_ENABLE;
3658 I915_WRITE(DDI_BUF_CTL(port), val);
3659 wait = true;
3660 }
3661
3662 val = I915_READ(DP_TP_CTL(port));
3663 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3664 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3665 I915_WRITE(DP_TP_CTL(port), val);
3666 POSTING_READ(DP_TP_CTL(port));
3667
3668 if (wait)
3669 intel_wait_ddi_buf_idle(dev_priv, port);
3670 }
3671
0e32b39c 3672 val = DP_TP_CTL_ENABLE |
c19b0669 3673 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3674 if (intel_dp->link_mst)
0e32b39c
DA		 3675 val |= DP_TP_CTL_MODE_MST;
3676 else {
3677 val |= DP_TP_CTL_MODE_SST;
3678 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3679 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3680 }
c19b0669
PZ		 3681 I915_WRITE(DP_TP_CTL(port), val);
3682 POSTING_READ(DP_TP_CTL(port));
3683
3684 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3685 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3686 POSTING_READ(DDI_BUF_CTL(port));
3687
3688 udelay(600);
3689}
00c09d70 3690
2085cc5d
VS		 3691static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3692 enum transcoder cpu_transcoder)
9935f7fa 3693{
2085cc5d
VS		 3694 if (cpu_transcoder == TRANSCODER_EDP)
3695 return false;
9935f7fa 3696
2085cc5d
VS		 3697 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3698 return false;
3699
3700 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3701 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3702}
3703
53e9bf5e
VS		 3704void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3705 struct intel_crtc_state *crtc_state)
3706{
2dd24a9c 3707 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3708 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3709 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3710 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3711}
3712
6801c18c 3713void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3714 struct intel_crtc_state *pipe_config)
045ac3b5 3715{
fac5e23e 3716 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3717 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3718 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3719 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3720 u32 temp, flags = 0;
3721
4d1de975
JN		 3722 /* XXX: DSI transcoder paranoia */
3723 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3724 return;
3725
045ac3b5
JB		 3726 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3727 if (temp & TRANS_DDI_PHSYNC)
3728 flags |= DRM_MODE_FLAG_PHSYNC;
3729 else
3730 flags |= DRM_MODE_FLAG_NHSYNC;
3731 if (temp & TRANS_DDI_PVSYNC)
3732 flags |= DRM_MODE_FLAG_PVSYNC;
3733 else
3734 flags |= DRM_MODE_FLAG_NVSYNC;
3735
2d112de7 3736 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3737
3738 switch (temp & TRANS_DDI_BPC_MASK) {
3739 case TRANS_DDI_BPC_6:
3740 pipe_config->pipe_bpp = 18;
3741 break;
3742 case TRANS_DDI_BPC_8:
3743 pipe_config->pipe_bpp = 24;
3744 break;
3745 case TRANS_DDI_BPC_10:
3746 pipe_config->pipe_bpp = 30;
3747 break;
3748 case TRANS_DDI_BPC_12:
3749 pipe_config->pipe_bpp = 36;
3750 break;
3751 default:
3752 break;
3753 }
eb14cb74
VS		 3754
3755 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3756 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3757 pipe_config->has_hdmi_sink = true;
f99be1b3 3758 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3759
e5e70d4a
VS		 3760 pipe_config->infoframes.enable |=
3761 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3762
3763 if (pipe_config->infoframes.enable)
bbd440fb 3764 pipe_config->has_infoframe = true;
15953637 3765
ab2cb2cb 3766 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 3767 pipe_config->hdmi_scrambling = true;
3768 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3769 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3770 /* fall through */
eb14cb74 3771 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3772 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3773 pipe_config->lane_count = 4;
3774 break;
eb14cb74 3775 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3776 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3777 break;
3778 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3779 if (encoder->type == INTEL_OUTPUT_EDP)
3780 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3781 else
3782 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3783 pipe_config->lane_count =
3784 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3785 intel_dp_get_m_n(intel_crtc, pipe_config);
3786 break;
eb14cb74 3787 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3788 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3789 pipe_config->lane_count =
3790 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3791 intel_dp_get_m_n(intel_crtc, pipe_config);
3792 break;
3793 default:
3794 break;
3795 }
10214420 3796
9935f7fa 3797 pipe_config->has_audio =
2085cc5d 3798 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3799
6aa23e65
JN		 3800 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3801 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3802 /*
3803 * This is a big fat ugly hack.
3804 *
3805 * Some machines in UEFI boot mode provide us a VBT that has 18
3806 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3807 * unknown we fail to light up. Yet the same BIOS boots up with
3808 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3809 * max, not what it tells us to use.
3810 *
3811 * Note: This will still be broken if the eDP panel is not lit
3812 * up by the BIOS, and thus we can't get the mode at module
3813 * load.
3814 */
3815 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3816 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3817 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3818 }
11578553 3819
22606a18 3820 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3821
cc3f90f0 3822 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3823 pipe_config->lane_lat_optim_mask =
3824 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3825
3826 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 3827
3828 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3829
3830 intel_read_infoframe(encoder, pipe_config,
3831 HDMI_INFOFRAME_TYPE_AVI,
3832 &pipe_config->infoframes.avi);
3833 intel_read_infoframe(encoder, pipe_config,
3834 HDMI_INFOFRAME_TYPE_SPD,
3835 &pipe_config->infoframes.spd);
3836 intel_read_infoframe(encoder, pipe_config,
3837 HDMI_INFOFRAME_TYPE_VENDOR,
3838 &pipe_config->infoframes.hdmi);
045ac3b5
JB		 3839}
3840
7e732cac
VS		 3841static enum intel_output_type
3842intel_ddi_compute_output_type(struct intel_encoder *encoder,
3843 struct intel_crtc_state *crtc_state,
3844 struct drm_connector_state *conn_state)
3845{
3846 switch (conn_state->connector->connector_type) {
3847 case DRM_MODE_CONNECTOR_HDMIA:
3848 return INTEL_OUTPUT_HDMI;
3849 case DRM_MODE_CONNECTOR_eDP:
3850 return INTEL_OUTPUT_EDP;
3851 case DRM_MODE_CONNECTOR_DisplayPort:
3852 return INTEL_OUTPUT_DP;
3853 default:
3854 MISSING_CASE(conn_state->connector->connector_type);
3855 return INTEL_OUTPUT_UNUSED;
3856 }
3857}
3858
204474a6
LP		 3859static int intel_ddi_compute_config(struct intel_encoder *encoder,
3860 struct intel_crtc_state *pipe_config,
3861 struct drm_connector_state *conn_state)
00c09d70 3862{
fac5e23e 3863 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3864 enum port port = encoder->port;
95a7a2ae 3865 int ret;
00c09d70 3866
bc7e3525 3867 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 3868 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3869
7e732cac 3870 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3871 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3872 else
0a478c27 3873 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
7a412b8f
VS		 3874 if (ret)
3875 return ret;
95a7a2ae 3876
7a412b8f 3877 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3878 pipe_config->lane_lat_optim_mask =
5161d058 3879 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3880
53e9bf5e
VS		 3881 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3882
7a412b8f 3883 return 0;
95a7a2ae 3884
00c09d70
PZ		 3885}
3886
f6bff60e
ID		 3887static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3888{
3889 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3890 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3891
3892 intel_dp_encoder_suspend(encoder);
3893
3894 /*
3895 * TODO: disconnect also from USB DP alternate mode once we have a
3896 * way to handle the modeset restore in that mode during resume
3897 * even if the sink has disappeared while being suspended.
3898 */
3899 if (dig_port->tc_legacy_port)
3900 icl_tc_phy_disconnect(i915, dig_port);
3901}
3902
3903static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3904{
3905 struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3906 struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3907
3908 if (intel_port_is_tc(i915, dig_port->base.port))
3909 intel_digital_port_connected(&dig_port->base);
3910
3911 intel_dp_encoder_reset(drm_encoder);
3912}
3913
3914static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3915{
3916 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3917 struct drm_i915_private *i915 = to_i915(encoder->dev);
3918
3919 intel_dp_encoder_flush_work(encoder);
3920
3921 if (intel_port_is_tc(i915, dig_port->base.port))
3922 icl_tc_phy_disconnect(i915, dig_port);
3923
3924 drm_encoder_cleanup(encoder);
3925 kfree(dig_port);
3926}
3927
00c09d70 3928static const struct drm_encoder_funcs intel_ddi_funcs = {
f6bff60e
ID		 3929 .reset = intel_ddi_encoder_reset,
3930 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 3931};
3932
4a28ae58
PZ		 3933static struct intel_connector *
3934intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3935{
3936 struct intel_connector *connector;
8f4f2797 3937 enum port port = intel_dig_port->base.port;
4a28ae58 3938
9bdbd0b9 3939 connector = intel_connector_alloc();
4a28ae58
PZ		 3940 if (!connector)
3941 return NULL;
3942
3943 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3944 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3945 kfree(connector);
3946 return NULL;
3947 }
3948
3949 return connector;
3950}
3951
dba14b27
VS		 3952static int modeset_pipe(struct drm_crtc *crtc,
3953 struct drm_modeset_acquire_ctx *ctx)
3954{
3955 struct drm_atomic_state *state;
3956 struct drm_crtc_state *crtc_state;
3957 int ret;
3958
3959 state = drm_atomic_state_alloc(crtc->dev);
3960 if (!state)
3961 return -ENOMEM;
3962
3963 state->acquire_ctx = ctx;
3964
3965 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3966 if (IS_ERR(crtc_state)) {
3967 ret = PTR_ERR(crtc_state);
3968 goto out;
3969 }
3970
b8fe992a 3971 crtc_state->connectors_changed = true;
dba14b27 3972
dba14b27 3973 ret = drm_atomic_commit(state);
a551cd66 3974out:
dba14b27
VS		 3975 drm_atomic_state_put(state);
3976
3977 return ret;
3978}
3979
3980static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3981 struct drm_modeset_acquire_ctx *ctx)
3982{
3983 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3984 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3985 struct intel_connector *connector = hdmi->attached_connector;
3986 struct i2c_adapter *adapter =
3987 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3988 struct drm_connector_state *conn_state;
3989 struct intel_crtc_state *crtc_state;
3990 struct intel_crtc *crtc;
3991 u8 config;
3992 int ret;
3993
3994 if (!connector || connector->base.status != connector_status_connected)
3995 return 0;
3996
3997 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3998 ctx);
3999 if (ret)
4000 return ret;
4001
4002 conn_state = connector->base.state;
4003
4004 crtc = to_intel_crtc(conn_state->crtc);
4005 if (!crtc)
4006 return 0;
4007
4008 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4009 if (ret)
4010 return ret;
4011
4012 crtc_state = to_intel_crtc_state(crtc->base.state);
4013
4014 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4015
4016 if (!crtc_state->base.active)
4017 return 0;
4018
4019 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4020 !crtc_state->hdmi_scrambling)
4021 return 0;
4022
4023 if (conn_state->commit &&
4024 !try_wait_for_completion(&conn_state->commit->hw_done))
4025 return 0;
4026
4027 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4028 if (ret < 0) {
4029 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4030 return 0;
4031 }
4032
4033 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4034 crtc_state->hdmi_high_tmds_clock_ratio &&
4035 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4036 crtc_state->hdmi_scrambling)
4037 return 0;
4038
4039 /*
4040 * HDMI 2.0 says that one should not send scrambled data
4041 * prior to configuring the sink scrambling, and that
4042 * TMDS clock/data transmission should be suspended when
4043 * changing the TMDS clock rate in the sink. So let's
4044 * just do a full modeset here, even though some sinks
4045 * would be perfectly happy if were to just reconfigure
4046 * the SCDC settings on the fly.
4047 */
4048 return modeset_pipe(&crtc->base, ctx);
4049}
4050
4051static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4052 struct intel_connector *connector)
4053{
4054 struct drm_modeset_acquire_ctx ctx;
4055 bool changed;
4056 int ret;
4057
4058 changed = intel_encoder_hotplug(encoder, connector);
4059
4060 drm_modeset_acquire_init(&ctx, 0);
4061
4062 for (;;) {
c85d200e
VS		 4063 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4064 ret = intel_hdmi_reset_link(encoder, &ctx);
4065 else
4066 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4067
4068 if (ret == -EDEADLK) {
4069 drm_modeset_backoff(&ctx);
4070 continue;
4071 }
4072
4073 break;
4074 }
4075
4076 drm_modeset_drop_locks(&ctx);
4077 drm_modeset_acquire_fini(&ctx);
4078 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4079
4080 return changed;
4081}
4082
4a28ae58
PZ		 4083static struct intel_connector *
4084intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4085{
4086 struct intel_connector *connector;
8f4f2797 4087 enum port port = intel_dig_port->base.port;
4a28ae58 4088
9bdbd0b9 4089 connector = intel_connector_alloc();
4a28ae58
PZ		 4090 if (!connector)
4091 return NULL;
4092
4093 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4094 intel_hdmi_init_connector(intel_dig_port, connector);
4095
4096 return connector;
4097}
4098
436009b5
RV		 4099static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4100{
4101 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4102
8f4f2797 4103 if (dport->base.port != PORT_A)
436009b5
RV		 4104 return false;
4105
4106 if (dport->saved_port_bits & DDI_A_4_LANES)
4107 return false;
4108
4109 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4110 * supported configuration
4111 */
4112 if (IS_GEN9_LP(dev_priv))
4113 return true;
4114
4115 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4116 * one who does also have a full A/E split called
4117 * DDI_F what makes DDI_E useless. However for this
4118 * case let's trust VBT info.
4119 */
4120 if (IS_CANNONLAKE(dev_priv) &&
4121 !intel_bios_is_port_present(dev_priv, PORT_E))
4122 return true;
4123
4124 return false;
4125}
4126
3d2011cf
MK		 4127static int
4128intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4129{
4130 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4131 enum port port = intel_dport->base.port;
4132 int max_lanes = 4;
4133
4134 if (INTEL_GEN(dev_priv) >= 11)
4135 return max_lanes;
4136
4137 if (port == PORT_A || port == PORT_E) {
4138 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4139 max_lanes = port == PORT_A ? 4 : 0;
4140 else
4141 /* Both A and E share 2 lanes */
4142 max_lanes = 2;
4143 }
4144
4145 /*
4146 * Some BIOS might fail to set this bit on port A if eDP
4147 * wasn't lit up at boot. Force this bit set when needed
4148 * so we use the proper lane count for our calculations.
4149 */
4150 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4151 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4152 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4153 max_lanes = 4;
4154 }
4155
4156 return max_lanes;
4157}
4158
c39055b0 4159void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4160{
f6bff60e
ID		 4161 struct ddi_vbt_port_info *port_info =
4162 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4163 struct intel_digital_port *intel_dig_port;
4164 struct intel_encoder *intel_encoder;
4165 struct drm_encoder *encoder;
ff662124 4166 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4167 enum pipe pipe;
10e7bec3 4168
f6bff60e
ID		 4169 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4170 init_dp = port_info->supports_dp;
ff662124
SS		 4171
4172 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4173 /*
4174 * Lspcon device needs to be driven with DP connector
4175 * with special detection sequence. So make sure DP
4176 * is initialized before lspcon.
4177 */
4178 init_dp = true;
4179 init_lspcon = true;
4180 init_hdmi = false;
4181 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4182 }
4183
311a2094 4184 if (!init_dp && !init_hdmi) {
500ea70d 4185 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4186 port_name(port));
500ea70d 4187 return;
311a2094 4188 }
00c09d70 4189
b14c5679 4190 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4191 if (!intel_dig_port)
4192 return;
4193
00c09d70
PZ		 4194 intel_encoder = &intel_dig_port->base;
4195 encoder = &intel_encoder->base;
4196
c39055b0 4197 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4198 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4199
c85d200e 4200 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4201 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4202 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4203 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4204 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4205 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4206 intel_encoder->pre_enable = intel_ddi_pre_enable;
4207 intel_encoder->disable = intel_disable_ddi;
4208 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4209 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4210 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4211 intel_encoder->get_config = intel_ddi_get_config;
f6bff60e 4212 intel_encoder->suspend = intel_ddi_encoder_suspend;
62b69566 4213 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4214 intel_encoder->type = INTEL_OUTPUT_DDI;
4215 intel_encoder->power_domain = intel_port_to_power_domain(port);
4216 intel_encoder->port = port;
3d2011cf 4217 intel_encoder->cloneable = 0;
570b16b5
MK		 4218 for_each_pipe(dev_priv, pipe)
4219 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4220
1e6aa7e5
JN		 4221 if (INTEL_GEN(dev_priv) >= 11)
4222 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4223 DDI_BUF_PORT_REVERSAL;
4224 else
4225 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4226 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4227 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4228 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4229 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4230
f6bff60e
ID		 4231 intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4232 !port_info->supports_typec_usb &&
4233 !port_info->supports_tbt;
4234
62b69566
ACO		 4235 switch (port) {
4236 case PORT_A:
4237 intel_dig_port->ddi_io_power_domain =
4238 POWER_DOMAIN_PORT_DDI_A_IO;
4239 break;
4240 case PORT_B:
4241 intel_dig_port->ddi_io_power_domain =
4242 POWER_DOMAIN_PORT_DDI_B_IO;
4243 break;
4244 case PORT_C:
4245 intel_dig_port->ddi_io_power_domain =
4246 POWER_DOMAIN_PORT_DDI_C_IO;
4247 break;
4248 case PORT_D:
4249 intel_dig_port->ddi_io_power_domain =
4250 POWER_DOMAIN_PORT_DDI_D_IO;
4251 break;
4252 case PORT_E:
4253 intel_dig_port->ddi_io_power_domain =
4254 POWER_DOMAIN_PORT_DDI_E_IO;
4255 break;
9787e835
RV		 4256 case PORT_F:
4257 intel_dig_port->ddi_io_power_domain =
4258 POWER_DOMAIN_PORT_DDI_F_IO;
4259 break;
62b69566
ACO		 4260 default:
4261 MISSING_CASE(port);
4262 }
4263
f68d697e
CW		 4264 if (init_dp) {
4265 if (!intel_ddi_init_dp_connector(intel_dig_port))
4266 goto err;
13cf5504 4267
f68d697e 4268 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4269 }
21a8e6a4 4270
311a2094
PZ		 4271 /* In theory we don't need the encoder->type check, but leave it just in
4272 * case we have some really bad VBTs... */
f68d697e
CW		 4273 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4274 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4275 goto err;
21a8e6a4 4276 }
f68d697e 4277
ff662124
SS		 4278 if (init_lspcon) {
4279 if (lspcon_init(intel_dig_port))
4280 /* TODO: handle hdmi info frame part */
4281 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4282 port_name(port));
4283 else
4284 /*
4285 * LSPCON init faied, but DP init was success, so
4286 * lets try to drive as DP++ port.
4287 */
4288 DRM_ERROR("LSPCON init failed on port %c\n",
4289 port_name(port));
4290 }
4291
06c812d7 4292 intel_infoframe_init(intel_dig_port);
f6bff60e
ID		 4293
4294 if (intel_port_is_tc(dev_priv, port))
4295 intel_digital_port_connected(intel_encoder);
4296
f68d697e
CW		 4297 return;
4298
4299err:
4300 drm_encoder_cleanup(encoder);
4301 kfree(intel_dig_port);
00c09d70 4302}
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