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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
35 | }; |
36 | ||
45244b87 ED |
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
38 | * them for both DP and FDI transports, allowing those ports to | |
39 | * automatically adapt to HDMI connections as well | |
40 | */ | |
10122051 | 41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
42 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
43 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
44 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
45 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
46 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
47 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
48 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
49 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
50 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
51 | }; |
52 | ||
10122051 | 53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
54 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
55 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
56 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
57 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
58 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
59 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
60 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
61 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
62 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
63 | }; |
64 | ||
10122051 JN |
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
66 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
67 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
68 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
69 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
70 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
71 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
72 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
73 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
74 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
75 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
76 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
77 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
78 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
79 | }; |
80 | ||
10122051 | 81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
82 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
83 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
84 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
85 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
86 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
87 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
88 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
89 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
90 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
91 | }; |
92 | ||
10122051 | 93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
94 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
95 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
96 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
97 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
98 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
99 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
100 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
101 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
102 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
103 | }; |
104 | ||
10122051 | 105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
106 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
107 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
108 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
109 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
110 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
111 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
112 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
113 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
114 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
115 | }; |
116 | ||
10122051 JN |
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
118 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
119 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
120 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
121 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
122 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
123 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
124 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
125 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
126 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
127 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
128 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
129 | }; |
130 | ||
5f8b2531 | 131 | /* Skylake H and S */ |
7f88e3af | 132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, | |
135 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 136 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 139 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 140 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 141 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
142 | }; |
143 | ||
f8896f5d DW |
144 | /* Skylake U */ |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 146 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 147 | { 0x00005012, 0x00000088, 0x0 }, |
5ac90567 | 148 | { 0x80007011, 0x000000CD, 0x1 }, |
d7097cff | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 150 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
151 | { 0x80005012, 0x000000C0, 0x1 }, |
152 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 153 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
155 | }; |
156 | ||
5f8b2531 RV |
157 | /* Skylake Y */ |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, | |
5ac90567 | 161 | { 0x80007011, 0x000000CD, 0x3 }, |
d7097cff | 162 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 163 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
164 | { 0x80005012, 0x000000C0, 0x3 }, |
165 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 166 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 167 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
168 | }; |
169 | ||
170 | /* | |
5f8b2531 | 171 | * Skylake H and S |
f8896f5d DW |
172 | * eDP 1.4 low vswing translation parameters |
173 | */ | |
7ad14a29 | 174 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
175 | { 0x00000018, 0x000000A8, 0x0 }, |
176 | { 0x00004013, 0x000000A9, 0x0 }, | |
177 | { 0x00007011, 0x000000A2, 0x0 }, | |
178 | { 0x00009010, 0x0000009C, 0x0 }, | |
179 | { 0x00000018, 0x000000A9, 0x0 }, | |
180 | { 0x00006013, 0x000000A2, 0x0 }, | |
181 | { 0x00007011, 0x000000A6, 0x0 }, | |
182 | { 0x00000018, 0x000000AB, 0x0 }, | |
183 | { 0x00007013, 0x0000009F, 0x0 }, | |
184 | { 0x00000018, 0x000000DF, 0x0 }, | |
185 | }; | |
186 | ||
187 | /* | |
188 | * Skylake U | |
189 | * eDP 1.4 low vswing translation parameters | |
190 | */ | |
191 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
192 | { 0x00000018, 0x000000A8, 0x0 }, | |
193 | { 0x00004013, 0x000000A9, 0x0 }, | |
194 | { 0x00007011, 0x000000A2, 0x0 }, | |
195 | { 0x00009010, 0x0000009C, 0x0 }, | |
196 | { 0x00000018, 0x000000A9, 0x0 }, | |
197 | { 0x00006013, 0x000000A2, 0x0 }, | |
198 | { 0x00007011, 0x000000A6, 0x0 }, | |
199 | { 0x00002016, 0x000000AB, 0x0 }, | |
200 | { 0x00005013, 0x0000009F, 0x0 }, | |
201 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
202 | }; |
203 | ||
f8896f5d | 204 | /* |
5f8b2531 | 205 | * Skylake Y |
f8896f5d DW |
206 | * eDP 1.4 low vswing translation parameters |
207 | */ | |
5f8b2531 | 208 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
209 | { 0x00000018, 0x000000A8, 0x0 }, |
210 | { 0x00004013, 0x000000AB, 0x0 }, | |
211 | { 0x00007011, 0x000000A4, 0x0 }, | |
212 | { 0x00009010, 0x000000DF, 0x0 }, | |
213 | { 0x00000018, 0x000000AA, 0x0 }, | |
214 | { 0x00006013, 0x000000A4, 0x0 }, | |
215 | { 0x00007011, 0x0000009D, 0x0 }, | |
216 | { 0x00000018, 0x000000A0, 0x0 }, | |
217 | { 0x00006012, 0x000000DF, 0x0 }, | |
218 | { 0x00000018, 0x0000008A, 0x0 }, | |
219 | }; | |
7ad14a29 | 220 | |
5f8b2531 | 221 | /* Skylake U, H and S */ |
7f88e3af | 222 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
223 | { 0x00000018, 0x000000AC, 0x0 }, |
224 | { 0x00005012, 0x0000009D, 0x0 }, | |
225 | { 0x00007011, 0x00000088, 0x0 }, | |
226 | { 0x00000018, 0x000000A1, 0x0 }, | |
227 | { 0x00000018, 0x00000098, 0x0 }, | |
228 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 229 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 230 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
231 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
232 | { 0x80003015, 0x000000C0, 0x1 }, | |
233 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
234 | }; |
235 | ||
5f8b2531 RV |
236 | /* Skylake Y */ |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { | |
f8896f5d DW |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 240 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, | |
243 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 244 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 245 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
246 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
247 | { 0x80003015, 0x000000C0, 0x3 }, | |
248 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
249 | }; |
250 | ||
96fb9f9b VK |
251 | struct bxt_ddi_buf_trans { |
252 | u32 margin; /* swing value */ | |
253 | u32 scale; /* scale value */ | |
254 | u32 enable; /* scale enable */ | |
255 | u32 deemphasis; | |
256 | bool default_index; /* true if the entry represents default value */ | |
257 | }; | |
258 | ||
96fb9f9b VK |
259 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
260 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
261 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
262 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
263 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
264 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
265 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
266 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
267 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
268 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
269 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
f8896f5d | 270 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
96fb9f9b VK |
271 | }; |
272 | ||
d9d7000d SJ |
273 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
274 | /* Idx NT mV diff db */ | |
275 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ | |
276 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ | |
277 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ | |
278 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ | |
279 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ | |
280 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ | |
281 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ | |
282 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ | |
283 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ | |
284 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ | |
285 | }; | |
286 | ||
96fb9f9b VK |
287 | /* BSpec has 2 recommended values - entries 0 and 8. |
288 | * Using the entry with higher vswing. | |
289 | */ | |
290 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
291 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
292 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
293 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
294 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
295 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
296 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
297 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
298 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
96fb9f9b VK |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
302 | }; | |
303 | ||
5a5d24dc | 304 | enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) |
fc914639 | 305 | { |
5a5d24dc | 306 | switch (encoder->type) { |
8cd21b7f | 307 | case INTEL_OUTPUT_DP_MST: |
5a5d24dc | 308 | return enc_to_mst(&encoder->base)->primary->port; |
cca0502b | 309 | case INTEL_OUTPUT_DP: |
8cd21b7f JN |
310 | case INTEL_OUTPUT_EDP: |
311 | case INTEL_OUTPUT_HDMI: | |
312 | case INTEL_OUTPUT_UNKNOWN: | |
5a5d24dc | 313 | return enc_to_dig_port(&encoder->base)->port; |
8cd21b7f | 314 | case INTEL_OUTPUT_ANALOG: |
5a5d24dc VS |
315 | return PORT_E; |
316 | default: | |
317 | MISSING_CASE(encoder->type); | |
318 | return PORT_A; | |
fc914639 PZ |
319 | } |
320 | } | |
321 | ||
a930acd9 VS |
322 | static const struct ddi_buf_trans * |
323 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
324 | { | |
325 | if (dev_priv->vbt.edp.low_vswing) { | |
326 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
327 | return bdw_ddi_translations_edp; | |
328 | } else { | |
329 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
330 | return bdw_ddi_translations_dp; | |
331 | } | |
332 | } | |
333 | ||
acee2998 | 334 | static const struct ddi_buf_trans * |
78ab0bae | 335 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 336 | { |
78ab0bae | 337 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 338 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 339 | return skl_y_ddi_translations_dp; |
78ab0bae | 340 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 341 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 342 | return skl_u_ddi_translations_dp; |
f8896f5d | 343 | } else { |
f8896f5d | 344 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 345 | return skl_ddi_translations_dp; |
f8896f5d | 346 | } |
f8896f5d DW |
347 | } |
348 | ||
acee2998 | 349 | static const struct ddi_buf_trans * |
78ab0bae | 350 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 351 | { |
06411f08 | 352 | if (dev_priv->vbt.edp.low_vswing) { |
78ab0bae | 353 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 354 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 355 | return skl_y_ddi_translations_edp; |
78ab0bae | 356 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 357 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 358 | return skl_u_ddi_translations_edp; |
f8896f5d | 359 | } else { |
f8896f5d | 360 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 361 | return skl_ddi_translations_edp; |
f8896f5d DW |
362 | } |
363 | } | |
cd1101cb | 364 | |
78ab0bae | 365 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
f8896f5d DW |
366 | } |
367 | ||
368 | static const struct ddi_buf_trans * | |
78ab0bae | 369 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 370 | { |
78ab0bae | 371 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 372 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 373 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 374 | } else { |
f8896f5d | 375 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 376 | return skl_ddi_translations_hdmi; |
f8896f5d | 377 | } |
f8896f5d DW |
378 | } |
379 | ||
8d8bb85e VS |
380 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
381 | { | |
382 | int n_hdmi_entries; | |
383 | int hdmi_level; | |
384 | int hdmi_default_entry; | |
385 | ||
386 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; | |
387 | ||
388 | if (IS_BROXTON(dev_priv)) | |
389 | return hdmi_level; | |
390 | ||
391 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
392 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); | |
393 | hdmi_default_entry = 8; | |
394 | } else if (IS_BROADWELL(dev_priv)) { | |
395 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
396 | hdmi_default_entry = 7; | |
397 | } else if (IS_HASWELL(dev_priv)) { | |
398 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
399 | hdmi_default_entry = 6; | |
400 | } else { | |
401 | WARN(1, "ddi translation table missing\n"); | |
402 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
403 | hdmi_default_entry = 7; | |
404 | } | |
405 | ||
406 | /* Choose a good default if VBT is badly populated */ | |
407 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
408 | hdmi_level >= n_hdmi_entries) | |
409 | hdmi_level = hdmi_default_entry; | |
410 | ||
411 | return hdmi_level; | |
412 | } | |
413 | ||
e58623cb AR |
414 | /* |
415 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
32bdc400 VS |
416 | * values in advance. This function programs the correct values for |
417 | * DP/eDP/FDI use cases. | |
45244b87 | 418 | */ |
32bdc400 | 419 | void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) |
45244b87 | 420 | { |
6a7e4f99 | 421 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 422 | u32 iboost_bit = 0; |
32bdc400 VS |
423 | int i, n_dp_entries, n_edp_entries, size; |
424 | enum port port = intel_ddi_get_encoder_port(encoder); | |
10122051 JN |
425 | const struct ddi_buf_trans *ddi_translations_fdi; |
426 | const struct ddi_buf_trans *ddi_translations_dp; | |
427 | const struct ddi_buf_trans *ddi_translations_edp; | |
10122051 | 428 | const struct ddi_buf_trans *ddi_translations; |
e58623cb | 429 | |
9f332437 | 430 | if (IS_BROXTON(dev_priv)) |
96fb9f9b | 431 | return; |
6a7e4f99 VS |
432 | |
433 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
c30400fc | 434 | ddi_translations_fdi = NULL; |
f8896f5d | 435 | ddi_translations_dp = |
78ab0bae | 436 | skl_get_buf_trans_dp(dev_priv, &n_dp_entries); |
f8896f5d | 437 | ddi_translations_edp = |
78ab0bae | 438 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); |
32bdc400 | 439 | |
75067dde | 440 | /* If we're boosting the current, set bit 31 of trans1 */ |
1edaaa2f | 441 | if (dev_priv->vbt.ddi_port_info[port].dp_boost_level) |
c110ae6c | 442 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
10afa0b6 | 443 | |
ceccad59 VS |
444 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && |
445 | port != PORT_A && port != PORT_E && | |
446 | n_edp_entries > 9)) | |
10afa0b6 | 447 | n_edp_entries = 9; |
78ab0bae | 448 | } else if (IS_BROADWELL(dev_priv)) { |
e58623cb AR |
449 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
450 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a930acd9 | 451 | ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries); |
7ad14a29 | 452 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
78ab0bae | 453 | } else if (IS_HASWELL(dev_priv)) { |
e58623cb AR |
454 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
455 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 456 | ddi_translations_edp = hsw_ddi_translations_dp; |
7ad14a29 | 457 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
e58623cb AR |
458 | } else { |
459 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 460 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
461 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
462 | ddi_translations_dp = bdw_ddi_translations_dp; | |
7ad14a29 SJ |
463 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
464 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
e58623cb AR |
465 | } |
466 | ||
6a7e4f99 VS |
467 | switch (encoder->type) { |
468 | case INTEL_OUTPUT_EDP: | |
300644c7 | 469 | ddi_translations = ddi_translations_edp; |
7ad14a29 | 470 | size = n_edp_entries; |
300644c7 | 471 | break; |
cca0502b | 472 | case INTEL_OUTPUT_DP: |
300644c7 | 473 | ddi_translations = ddi_translations_dp; |
7ad14a29 | 474 | size = n_dp_entries; |
300644c7 | 475 | break; |
6a7e4f99 VS |
476 | case INTEL_OUTPUT_ANALOG: |
477 | ddi_translations = ddi_translations_fdi; | |
7ad14a29 | 478 | size = n_dp_entries; |
300644c7 PZ |
479 | break; |
480 | default: | |
481 | BUG(); | |
482 | } | |
45244b87 | 483 | |
9712e688 VS |
484 | for (i = 0; i < size; i++) { |
485 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), | |
486 | ddi_translations[i].trans1 | iboost_bit); | |
487 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
488 | ddi_translations[i].trans2); | |
45244b87 | 489 | } |
32bdc400 VS |
490 | } |
491 | ||
492 | /* | |
493 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
494 | * values in advance. This function programs the correct values for | |
495 | * HDMI/DVI use cases. | |
496 | */ | |
497 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) | |
498 | { | |
499 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
500 | u32 iboost_bit = 0; | |
501 | int n_hdmi_entries, hdmi_level; | |
502 | enum port port = intel_ddi_get_encoder_port(encoder); | |
503 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
ce4dd49e | 504 | |
32bdc400 | 505 | if (IS_BROXTON(dev_priv)) |
ce3b7e9b DL |
506 | return; |
507 | ||
32bdc400 VS |
508 | hdmi_level = intel_ddi_hdmi_level(dev_priv, port); |
509 | ||
510 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
511 | ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); | |
1edaaa2f | 512 | |
32bdc400 | 513 | /* If we're boosting the current, set bit 31 of trans1 */ |
1edaaa2f | 514 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) |
32bdc400 VS |
515 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
516 | } else if (IS_BROADWELL(dev_priv)) { | |
517 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
518 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
519 | } else if (IS_HASWELL(dev_priv)) { | |
520 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; | |
521 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
522 | } else { | |
523 | WARN(1, "ddi translation table missing\n"); | |
524 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
525 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
526 | } | |
527 | ||
6acab15a | 528 | /* Entry 9 is for HDMI: */ |
ed9c77d2 | 529 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
9712e688 | 530 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
ed9c77d2 | 531 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
9712e688 | 532 | ddi_translations_hdmi[hdmi_level].trans2); |
45244b87 ED |
533 | } |
534 | ||
248138b5 PZ |
535 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
536 | enum port port) | |
537 | { | |
f0f59a00 | 538 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
539 | int i; |
540 | ||
3449ca85 | 541 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
542 | udelay(1); |
543 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
544 | return; | |
545 | } | |
546 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
547 | } | |
c82e4d26 ED |
548 | |
549 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
550 | * connection to the PCH-located connectors. For this, it is necessary to train | |
551 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
552 | * | |
553 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
554 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
555 | * DDI A (which is used for eDP) | |
556 | */ | |
557 | ||
558 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
559 | { | |
560 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 561 | struct drm_i915_private *dev_priv = to_i915(dev); |
c82e4d26 | 562 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6a7e4f99 | 563 | struct intel_encoder *encoder; |
04945641 | 564 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 565 | |
6a7e4f99 VS |
566 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
567 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); | |
32bdc400 | 568 | intel_prepare_dp_ddi_buffers(encoder); |
6a7e4f99 VS |
569 | } |
570 | ||
04945641 PZ |
571 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
572 | * mode set "sequence for CRT port" document: | |
573 | * - TP1 to TP2 time with the default value | |
574 | * - FDI delay to 90h | |
8693a824 DL |
575 | * |
576 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 577 | */ |
eede3b53 | 578 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
579 | FDI_RX_PWRDN_LANE0_VAL(2) | |
580 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
581 | ||
582 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 583 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 584 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 585 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
eede3b53 VS |
586 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
587 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
588 | udelay(220); |
589 | ||
590 | /* Switch from Rawclk to PCDclk */ | |
591 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 592 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
593 | |
594 | /* Configure Port Clock Select */ | |
6e3c9717 ACO |
595 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
596 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
597 | |
598 | /* Start the training iterating through available voltages and emphasis, | |
599 | * testing each value twice. */ | |
10122051 | 600 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
601 | /* Configure DP_TP_CTL with auto-training */ |
602 | I915_WRITE(DP_TP_CTL(PORT_E), | |
603 | DP_TP_CTL_FDI_AUTOTRAIN | | |
604 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
605 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
606 | DP_TP_CTL_ENABLE); | |
607 | ||
876a8cdf DL |
608 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
609 | * DDI E does not support port reversal, the functionality is | |
610 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
611 | * port reversal bit */ | |
c82e4d26 | 612 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 613 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 614 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 615 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 616 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
617 | |
618 | udelay(600); | |
619 | ||
04945641 | 620 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 621 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
622 | |
623 | /* Enable PCH FDI Receiver with auto-training */ | |
624 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
625 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
626 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
627 | |
628 | /* Wait for FDI receiver lane calibration */ | |
629 | udelay(30); | |
630 | ||
631 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 632 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 633 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
634 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
635 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
636 | |
637 | /* Wait for FDI auto training time */ | |
638 | udelay(5); | |
c82e4d26 ED |
639 | |
640 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
641 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 642 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
643 | break; |
644 | } | |
c82e4d26 | 645 | |
a308ccb3 VS |
646 | /* |
647 | * Leave things enabled even if we failed to train FDI. | |
648 | * Results in less fireworks from the state checker. | |
649 | */ | |
650 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
651 | DRM_ERROR("FDI link training failed!\n"); | |
652 | break; | |
c82e4d26 | 653 | } |
04945641 | 654 | |
5b421c57 VS |
655 | rx_ctl_val &= ~FDI_RX_ENABLE; |
656 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); | |
657 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
658 | ||
248138b5 PZ |
659 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
660 | temp &= ~DDI_BUF_CTL_ENABLE; | |
661 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
662 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
663 | ||
04945641 | 664 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
665 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
666 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
667 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
668 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
669 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
670 | ||
671 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 | 672 | |
04945641 | 673 | /* Reset FDI_RX_MISC pwrdn lanes */ |
eede3b53 | 674 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
675 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
676 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
677 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
678 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
679 | } |
680 | ||
a308ccb3 VS |
681 | /* Enable normal pixel sending for FDI */ |
682 | I915_WRITE(DP_TP_CTL(PORT_E), | |
683 | DP_TP_CTL_FDI_AUTOTRAIN | | |
684 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
685 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
686 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 687 | } |
0e72a5b5 | 688 | |
44905a27 DA |
689 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
690 | { | |
691 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
692 | struct intel_digital_port *intel_dig_port = | |
693 | enc_to_dig_port(&encoder->base); | |
694 | ||
695 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 696 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 697 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
698 | } |
699 | ||
8d9ddbcb PZ |
700 | static struct intel_encoder * |
701 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
702 | { | |
703 | struct drm_device *dev = crtc->dev; | |
704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
705 | struct intel_encoder *intel_encoder, *ret = NULL; | |
706 | int num_encoders = 0; | |
707 | ||
708 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
709 | ret = intel_encoder; | |
710 | num_encoders++; | |
711 | } | |
712 | ||
713 | if (num_encoders != 1) | |
84f44ce7 VS |
714 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
715 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
716 | |
717 | BUG_ON(ret == NULL); | |
718 | return ret; | |
719 | } | |
720 | ||
bcddf610 | 721 | struct intel_encoder * |
3165c074 | 722 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 723 | { |
3165c074 ACO |
724 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
725 | struct intel_encoder *ret = NULL; | |
726 | struct drm_atomic_state *state; | |
da3ced29 ACO |
727 | struct drm_connector *connector; |
728 | struct drm_connector_state *connector_state; | |
d0737e1d | 729 | int num_encoders = 0; |
3165c074 | 730 | int i; |
d0737e1d | 731 | |
3165c074 ACO |
732 | state = crtc_state->base.state; |
733 | ||
da3ced29 ACO |
734 | for_each_connector_in_state(state, connector, connector_state, i) { |
735 | if (connector_state->crtc != crtc_state->base.crtc) | |
3165c074 ACO |
736 | continue; |
737 | ||
da3ced29 | 738 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 739 | num_encoders++; |
d0737e1d ACO |
740 | } |
741 | ||
742 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
743 | pipe_name(crtc->pipe)); | |
744 | ||
745 | BUG_ON(ret == NULL); | |
746 | return ret; | |
747 | } | |
748 | ||
1c0b85c5 | 749 | #define LC_FREQ 2700 |
1c0b85c5 | 750 | |
f0f59a00 VS |
751 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
752 | i915_reg_t reg) | |
11578553 JB |
753 | { |
754 | int refclk = LC_FREQ; | |
755 | int n, p, r; | |
756 | u32 wrpll; | |
757 | ||
758 | wrpll = I915_READ(reg); | |
114fe488 DV |
759 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
760 | case WRPLL_PLL_SSC: | |
761 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
762 | /* |
763 | * We could calculate spread here, but our checking | |
764 | * code only cares about 5% accuracy, and spread is a max of | |
765 | * 0.5% downspread. | |
766 | */ | |
767 | refclk = 135; | |
768 | break; | |
114fe488 | 769 | case WRPLL_PLL_LCPLL: |
11578553 JB |
770 | refclk = LC_FREQ; |
771 | break; | |
772 | default: | |
773 | WARN(1, "bad wrpll refclk\n"); | |
774 | return 0; | |
775 | } | |
776 | ||
777 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
778 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
779 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
780 | ||
20f0ec16 JB |
781 | /* Convert to KHz, p & r have a fixed point portion */ |
782 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
783 | } |
784 | ||
540e732c S |
785 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
786 | uint32_t dpll) | |
787 | { | |
f0f59a00 | 788 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
540e732c S |
789 | uint32_t cfgcr1_val, cfgcr2_val; |
790 | uint32_t p0, p1, p2, dco_freq; | |
791 | ||
923c1241 VS |
792 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
793 | cfgcr2_reg = DPLL_CFGCR2(dpll); | |
540e732c S |
794 | |
795 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
796 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
797 | ||
798 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
799 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
800 | ||
801 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
802 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
803 | else | |
804 | p1 = 1; | |
805 | ||
806 | ||
807 | switch (p0) { | |
808 | case DPLL_CFGCR2_PDIV_1: | |
809 | p0 = 1; | |
810 | break; | |
811 | case DPLL_CFGCR2_PDIV_2: | |
812 | p0 = 2; | |
813 | break; | |
814 | case DPLL_CFGCR2_PDIV_3: | |
815 | p0 = 3; | |
816 | break; | |
817 | case DPLL_CFGCR2_PDIV_7: | |
818 | p0 = 7; | |
819 | break; | |
820 | } | |
821 | ||
822 | switch (p2) { | |
823 | case DPLL_CFGCR2_KDIV_5: | |
824 | p2 = 5; | |
825 | break; | |
826 | case DPLL_CFGCR2_KDIV_2: | |
827 | p2 = 2; | |
828 | break; | |
829 | case DPLL_CFGCR2_KDIV_3: | |
830 | p2 = 3; | |
831 | break; | |
832 | case DPLL_CFGCR2_KDIV_1: | |
833 | p2 = 1; | |
834 | break; | |
835 | } | |
836 | ||
837 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
838 | ||
839 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
840 | 1000) / 0x8000; | |
841 | ||
842 | return dco_freq / (p0 * p1 * p2 * 5); | |
843 | } | |
844 | ||
398a017e VS |
845 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
846 | { | |
847 | int dotclock; | |
848 | ||
849 | if (pipe_config->has_pch_encoder) | |
850 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
851 | &pipe_config->fdi_m_n); | |
37a5650b | 852 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
398a017e VS |
853 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
854 | &pipe_config->dp_m_n); | |
855 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) | |
856 | dotclock = pipe_config->port_clock * 2 / 3; | |
857 | else | |
858 | dotclock = pipe_config->port_clock; | |
859 | ||
860 | if (pipe_config->pixel_multiplier) | |
861 | dotclock /= pipe_config->pixel_multiplier; | |
862 | ||
863 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
864 | } | |
540e732c S |
865 | |
866 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 867 | struct intel_crtc_state *pipe_config) |
540e732c | 868 | { |
fac5e23e | 869 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
540e732c S |
870 | int link_clock = 0; |
871 | uint32_t dpll_ctl1, dpll; | |
872 | ||
134ffa44 | 873 | dpll = pipe_config->ddi_pll_sel; |
540e732c S |
874 | |
875 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
876 | ||
877 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
878 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
879 | } else { | |
71cd8423 DL |
880 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
881 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); | |
540e732c S |
882 | |
883 | switch (link_clock) { | |
71cd8423 | 884 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
885 | link_clock = 81000; |
886 | break; | |
71cd8423 | 887 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
888 | link_clock = 108000; |
889 | break; | |
71cd8423 | 890 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
891 | link_clock = 135000; |
892 | break; | |
71cd8423 | 893 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
894 | link_clock = 162000; |
895 | break; | |
71cd8423 | 896 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
897 | link_clock = 216000; |
898 | break; | |
71cd8423 | 899 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
900 | link_clock = 270000; |
901 | break; | |
902 | default: | |
903 | WARN(1, "Unsupported link rate\n"); | |
904 | break; | |
905 | } | |
906 | link_clock *= 2; | |
907 | } | |
908 | ||
909 | pipe_config->port_clock = link_clock; | |
910 | ||
398a017e | 911 | ddi_dotclock_get(pipe_config); |
540e732c S |
912 | } |
913 | ||
3d51278a | 914 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 915 | struct intel_crtc_state *pipe_config) |
11578553 | 916 | { |
fac5e23e | 917 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
11578553 JB |
918 | int link_clock = 0; |
919 | u32 val, pll; | |
920 | ||
26804afd | 921 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
922 | switch (val & PORT_CLK_SEL_MASK) { |
923 | case PORT_CLK_SEL_LCPLL_810: | |
924 | link_clock = 81000; | |
925 | break; | |
926 | case PORT_CLK_SEL_LCPLL_1350: | |
927 | link_clock = 135000; | |
928 | break; | |
929 | case PORT_CLK_SEL_LCPLL_2700: | |
930 | link_clock = 270000; | |
931 | break; | |
932 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 933 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
934 | break; |
935 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 936 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
937 | break; |
938 | case PORT_CLK_SEL_SPLL: | |
939 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
940 | if (pll == SPLL_PLL_FREQ_810MHz) | |
941 | link_clock = 81000; | |
942 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
943 | link_clock = 135000; | |
944 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
945 | link_clock = 270000; | |
946 | else { | |
947 | WARN(1, "bad spll freq\n"); | |
948 | return; | |
949 | } | |
950 | break; | |
951 | default: | |
952 | WARN(1, "bad port clock sel\n"); | |
953 | return; | |
954 | } | |
955 | ||
956 | pipe_config->port_clock = link_clock * 2; | |
957 | ||
398a017e | 958 | ddi_dotclock_get(pipe_config); |
11578553 JB |
959 | } |
960 | ||
977bb38d S |
961 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
962 | enum intel_dpll_id dpll) | |
963 | { | |
aa610dcb ID |
964 | struct intel_shared_dpll *pll; |
965 | struct intel_dpll_hw_state *state; | |
9e2c8475 | 966 | struct dpll clock; |
aa610dcb ID |
967 | |
968 | /* For DDI ports we always use a shared PLL. */ | |
969 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) | |
970 | return 0; | |
971 | ||
972 | pll = &dev_priv->shared_dplls[dpll]; | |
973 | state = &pll->config.hw_state; | |
974 | ||
975 | clock.m1 = 2; | |
976 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; | |
977 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
978 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
979 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
980 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
981 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
982 | ||
983 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
984 | } |
985 | ||
986 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
987 | struct intel_crtc_state *pipe_config) | |
988 | { | |
fac5e23e | 989 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
977bb38d S |
990 | enum port port = intel_ddi_get_encoder_port(encoder); |
991 | uint32_t dpll = port; | |
992 | ||
398a017e | 993 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
977bb38d | 994 | |
398a017e | 995 | ddi_dotclock_get(pipe_config); |
977bb38d S |
996 | } |
997 | ||
3d51278a | 998 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 999 | struct intel_crtc_state *pipe_config) |
3d51278a | 1000 | { |
22606a18 DL |
1001 | struct drm_device *dev = encoder->base.dev; |
1002 | ||
1003 | if (INTEL_INFO(dev)->gen <= 8) | |
1004 | hsw_ddi_clock_get(encoder, pipe_config); | |
ef11bdb3 | 1005 | else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
22606a18 | 1006 | skl_ddi_clock_get(encoder, pipe_config); |
977bb38d S |
1007 | else if (IS_BROXTON(dev)) |
1008 | bxt_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
1009 | } |
1010 | ||
0220ab6e | 1011 | static bool |
d664c0ce | 1012 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 1013 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1014 | struct intel_encoder *intel_encoder) |
6441ab5f | 1015 | { |
daedf20a | 1016 | struct intel_shared_dpll *pll; |
6441ab5f | 1017 | |
9d16da65 ACO |
1018 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, |
1019 | intel_encoder); | |
1020 | if (!pll) | |
1021 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1022 | pipe_name(intel_crtc->pipe)); | |
1023 | ||
1024 | return pll; | |
6441ab5f PZ |
1025 | } |
1026 | ||
82d35437 S |
1027 | static bool |
1028 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1029 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1030 | struct intel_encoder *intel_encoder) |
82d35437 S |
1031 | { |
1032 | struct intel_shared_dpll *pll; | |
82d35437 | 1033 | |
daedf20a | 1034 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
82d35437 S |
1035 | if (pll == NULL) { |
1036 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1037 | pipe_name(intel_crtc->pipe)); | |
1038 | return false; | |
1039 | } | |
1040 | ||
82d35437 S |
1041 | return true; |
1042 | } | |
0220ab6e | 1043 | |
d683f3bc S |
1044 | static bool |
1045 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1046 | struct intel_crtc_state *crtc_state, | |
96f3f1f9 | 1047 | struct intel_encoder *intel_encoder) |
d683f3bc | 1048 | { |
34177c24 | 1049 | return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
d683f3bc S |
1050 | } |
1051 | ||
0220ab6e DL |
1052 | /* |
1053 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1054 | * intel_crtc->ddi_pll_sel. | |
1055 | * | |
1056 | * For private DPLLs, compute_config() should do the selection for us. This | |
1057 | * function should be folded into compute_config() eventually. | |
1058 | */ | |
190f68c5 ACO |
1059 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1060 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1061 | { |
82d35437 | 1062 | struct drm_device *dev = intel_crtc->base.dev; |
d0737e1d | 1063 | struct intel_encoder *intel_encoder = |
3165c074 | 1064 | intel_ddi_get_crtc_new_encoder(crtc_state); |
0220ab6e | 1065 | |
ef11bdb3 | 1066 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
190f68c5 | 1067 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1068 | intel_encoder); |
d683f3bc S |
1069 | else if (IS_BROXTON(dev)) |
1070 | return bxt_ddi_pll_select(intel_crtc, crtc_state, | |
96f3f1f9 | 1071 | intel_encoder); |
82d35437 | 1072 | else |
190f68c5 | 1073 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1074 | intel_encoder); |
0220ab6e DL |
1075 | } |
1076 | ||
dae84799 PZ |
1077 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1078 | { | |
fac5e23e | 1079 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
dae84799 PZ |
1080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1081 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1082 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1083 | int type = intel_encoder->type; |
1084 | uint32_t temp; | |
1085 | ||
cca0502b | 1086 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
4d1de975 JN |
1087 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
1088 | ||
c9809791 | 1089 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1090 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1091 | case 18: |
c9809791 | 1092 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1093 | break; |
1094 | case 24: | |
c9809791 | 1095 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1096 | break; |
1097 | case 30: | |
c9809791 | 1098 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1099 | break; |
1100 | case 36: | |
c9809791 | 1101 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1102 | break; |
1103 | default: | |
4e53c2e0 | 1104 | BUG(); |
dae84799 | 1105 | } |
c9809791 | 1106 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1107 | } |
1108 | } | |
1109 | ||
0e32b39c DA |
1110 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1111 | { | |
1112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1113 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 1114 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1115 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1116 | uint32_t temp; |
1117 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1118 | if (state == true) | |
1119 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1120 | else | |
1121 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1122 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1123 | } | |
1124 | ||
8228c251 | 1125 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1126 | { |
1127 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1128 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
c7670b10 | 1129 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1130 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d9ddbcb | 1131 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1132 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1133 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1134 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1135 | uint32_t temp; |
1136 | ||
ad80a810 PZ |
1137 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1138 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1139 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1140 | |
6e3c9717 | 1141 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1142 | case 18: |
ad80a810 | 1143 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1144 | break; |
1145 | case 24: | |
ad80a810 | 1146 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1147 | break; |
1148 | case 30: | |
ad80a810 | 1149 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1150 | break; |
1151 | case 36: | |
ad80a810 | 1152 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1153 | break; |
1154 | default: | |
4e53c2e0 | 1155 | BUG(); |
dfcef252 | 1156 | } |
72662e10 | 1157 | |
6e3c9717 | 1158 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1159 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1160 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1161 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1162 | |
e6f0bfc4 PZ |
1163 | if (cpu_transcoder == TRANSCODER_EDP) { |
1164 | switch (pipe) { | |
1165 | case PIPE_A: | |
c7670b10 PZ |
1166 | /* On Haswell, can only use the always-on power well for |
1167 | * eDP when not using the panel fitter, and when not | |
1168 | * using motion blur mitigation (which we don't | |
1169 | * support). */ | |
fabf6e51 | 1170 | if (IS_HASWELL(dev) && |
6e3c9717 ACO |
1171 | (intel_crtc->config->pch_pfit.enabled || |
1172 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1173 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1174 | else | |
1175 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1176 | break; |
1177 | case PIPE_B: | |
1178 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1179 | break; | |
1180 | case PIPE_C: | |
1181 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1182 | break; | |
1183 | default: | |
1184 | BUG(); | |
1185 | break; | |
1186 | } | |
1187 | } | |
1188 | ||
7739c33b | 1189 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1190 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1191 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1192 | else |
ad80a810 | 1193 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
7739c33b | 1194 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1195 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1196 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
cca0502b | 1197 | } else if (type == INTEL_OUTPUT_DP || |
7739c33b | 1198 | type == INTEL_OUTPUT_EDP) { |
64ee2fd2 | 1199 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
90a6b7b0 | 1200 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
0e32b39c | 1201 | } else if (type == INTEL_OUTPUT_DP_MST) { |
64ee2fd2 | 1202 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
90a6b7b0 | 1203 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
8d9ddbcb | 1204 | } else { |
84f44ce7 VS |
1205 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1206 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1207 | } |
1208 | ||
ad80a810 | 1209 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1210 | } |
72662e10 | 1211 | |
ad80a810 PZ |
1212 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1213 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1214 | { |
f0f59a00 | 1215 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1216 | uint32_t val = I915_READ(reg); |
1217 | ||
0e32b39c | 1218 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1219 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1220 | I915_WRITE(reg, val); |
72662e10 ED |
1221 | } |
1222 | ||
bcbc889b PZ |
1223 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1224 | { | |
1225 | struct drm_device *dev = intel_connector->base.dev; | |
fac5e23e | 1226 | struct drm_i915_private *dev_priv = to_i915(dev); |
bcbc889b PZ |
1227 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
1228 | int type = intel_connector->base.connector_type; | |
1229 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1230 | enum pipe pipe = 0; | |
1231 | enum transcoder cpu_transcoder; | |
882244a3 | 1232 | enum intel_display_power_domain power_domain; |
bcbc889b | 1233 | uint32_t tmp; |
e27daab4 | 1234 | bool ret; |
bcbc889b | 1235 | |
882244a3 | 1236 | power_domain = intel_display_port_power_domain(intel_encoder); |
e27daab4 | 1237 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1238 | return false; |
1239 | ||
e27daab4 ID |
1240 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1241 | ret = false; | |
1242 | goto out; | |
1243 | } | |
bcbc889b PZ |
1244 | |
1245 | if (port == PORT_A) | |
1246 | cpu_transcoder = TRANSCODER_EDP; | |
1247 | else | |
1a240d4d | 1248 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1249 | |
1250 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1251 | ||
1252 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1253 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1254 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
1255 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1256 | break; | |
bcbc889b PZ |
1257 | |
1258 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
1259 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1260 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
1261 | break; | |
1262 | ||
0e32b39c DA |
1263 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1264 | /* if the transcoder is in MST state then | |
1265 | * connector isn't connected */ | |
e27daab4 ID |
1266 | ret = false; |
1267 | break; | |
bcbc889b PZ |
1268 | |
1269 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
1270 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1271 | break; | |
bcbc889b PZ |
1272 | |
1273 | default: | |
e27daab4 ID |
1274 | ret = false; |
1275 | break; | |
bcbc889b | 1276 | } |
e27daab4 ID |
1277 | |
1278 | out: | |
1279 | intel_display_power_put(dev_priv, power_domain); | |
1280 | ||
1281 | return ret; | |
bcbc889b PZ |
1282 | } |
1283 | ||
85234cdc DV |
1284 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1285 | enum pipe *pipe) | |
1286 | { | |
1287 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1288 | struct drm_i915_private *dev_priv = to_i915(dev); |
fe43d3f5 | 1289 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1290 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1291 | u32 tmp; |
1292 | int i; | |
e27daab4 | 1293 | bool ret; |
85234cdc | 1294 | |
6d129bea | 1295 | power_domain = intel_display_port_power_domain(encoder); |
e27daab4 | 1296 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
1297 | return false; |
1298 | ||
e27daab4 ID |
1299 | ret = false; |
1300 | ||
fe43d3f5 | 1301 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1302 | |
1303 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
e27daab4 | 1304 | goto out; |
85234cdc | 1305 | |
ad80a810 PZ |
1306 | if (port == PORT_A) { |
1307 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1308 | |
ad80a810 PZ |
1309 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1310 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1311 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1312 | *pipe = PIPE_A; | |
1313 | break; | |
1314 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1315 | *pipe = PIPE_B; | |
1316 | break; | |
1317 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1318 | *pipe = PIPE_C; | |
1319 | break; | |
1320 | } | |
1321 | ||
e27daab4 | 1322 | ret = true; |
ad80a810 | 1323 | |
e27daab4 ID |
1324 | goto out; |
1325 | } | |
0e32b39c | 1326 | |
e27daab4 ID |
1327 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
1328 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1329 | ||
1330 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { | |
1331 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == | |
1332 | TRANS_DDI_MODE_SELECT_DP_MST) | |
1333 | goto out; | |
1334 | ||
1335 | *pipe = i; | |
1336 | ret = true; | |
1337 | ||
1338 | goto out; | |
85234cdc DV |
1339 | } |
1340 | } | |
1341 | ||
84f44ce7 | 1342 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1343 | |
e27daab4 | 1344 | out: |
e93da0a0 ID |
1345 | if (ret && IS_BROXTON(dev_priv)) { |
1346 | tmp = I915_READ(BXT_PHY_CTL(port)); | |
1347 | if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK | | |
1348 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) | |
1349 | DRM_ERROR("Port %c enabled but PHY powered down? " | |
1350 | "(PHY_CTL %08x)\n", port_name(port), tmp); | |
1351 | } | |
1352 | ||
e27daab4 ID |
1353 | intel_display_power_put(dev_priv, power_domain); |
1354 | ||
1355 | return ret; | |
85234cdc DV |
1356 | } |
1357 | ||
fc914639 PZ |
1358 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1359 | { | |
1360 | struct drm_crtc *crtc = &intel_crtc->base; | |
7d4aefd0 | 1361 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1362 | struct drm_i915_private *dev_priv = to_i915(dev); |
fc914639 PZ |
1363 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1364 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 1365 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1366 | |
bb523fc0 PZ |
1367 | if (cpu_transcoder != TRANSCODER_EDP) |
1368 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1369 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1370 | } |
1371 | ||
1372 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1373 | { | |
fac5e23e | 1374 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
6e3c9717 | 1375 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1376 | |
bb523fc0 PZ |
1377 | if (cpu_transcoder != TRANSCODER_EDP) |
1378 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1379 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1380 | } |
1381 | ||
a7d8dbc0 VS |
1382 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
1383 | enum port port, uint8_t iboost) | |
f8896f5d | 1384 | { |
a7d8dbc0 VS |
1385 | u32 tmp; |
1386 | ||
1387 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
1388 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); | |
1389 | if (iboost) | |
1390 | tmp |= iboost << BALANCE_LEG_SHIFT(port); | |
1391 | else | |
1392 | tmp |= BALANCE_LEG_DISABLE(port); | |
1393 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); | |
1394 | } | |
1395 | ||
1396 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) | |
1397 | { | |
1398 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
1399 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
1400 | enum port port = intel_dig_port->port; | |
1401 | int type = encoder->type; | |
f8896f5d DW |
1402 | const struct ddi_buf_trans *ddi_translations; |
1403 | uint8_t iboost; | |
75067dde | 1404 | uint8_t dp_iboost, hdmi_iboost; |
f8896f5d | 1405 | int n_entries; |
f8896f5d | 1406 | |
75067dde AK |
1407 | /* VBT may override standard boost values */ |
1408 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
1409 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
1410 | ||
cca0502b | 1411 | if (type == INTEL_OUTPUT_DP) { |
75067dde AK |
1412 | if (dp_iboost) { |
1413 | iboost = dp_iboost; | |
1414 | } else { | |
78ab0bae | 1415 | ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); |
e4d4c05b | 1416 | iboost = ddi_translations[level].i_boost; |
75067dde | 1417 | } |
f8896f5d | 1418 | } else if (type == INTEL_OUTPUT_EDP) { |
75067dde AK |
1419 | if (dp_iboost) { |
1420 | iboost = dp_iboost; | |
1421 | } else { | |
78ab0bae | 1422 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
10afa0b6 VS |
1423 | |
1424 | if (WARN_ON(port != PORT_A && | |
1425 | port != PORT_E && n_entries > 9)) | |
1426 | n_entries = 9; | |
1427 | ||
e4d4c05b | 1428 | iboost = ddi_translations[level].i_boost; |
75067dde | 1429 | } |
f8896f5d | 1430 | } else if (type == INTEL_OUTPUT_HDMI) { |
75067dde AK |
1431 | if (hdmi_iboost) { |
1432 | iboost = hdmi_iboost; | |
1433 | } else { | |
78ab0bae | 1434 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
e4d4c05b | 1435 | iboost = ddi_translations[level].i_boost; |
75067dde | 1436 | } |
f8896f5d DW |
1437 | } else { |
1438 | return; | |
1439 | } | |
1440 | ||
1441 | /* Make sure that the requested I_boost is valid */ | |
1442 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
1443 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
1444 | return; | |
1445 | } | |
1446 | ||
a7d8dbc0 | 1447 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
f8896f5d | 1448 | |
a7d8dbc0 VS |
1449 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
1450 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); | |
f8896f5d DW |
1451 | } |
1452 | ||
78ab0bae VS |
1453 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
1454 | u32 level, enum port port, int type) | |
96fb9f9b | 1455 | { |
96fb9f9b VK |
1456 | const struct bxt_ddi_buf_trans *ddi_translations; |
1457 | u32 n_entries, i; | |
1458 | uint32_t val; | |
1459 | ||
06411f08 | 1460 | if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { |
d9d7000d SJ |
1461 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
1462 | ddi_translations = bxt_ddi_translations_edp; | |
cca0502b | 1463 | } else if (type == INTEL_OUTPUT_DP |
d9d7000d | 1464 | || type == INTEL_OUTPUT_EDP) { |
96fb9f9b VK |
1465 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
1466 | ddi_translations = bxt_ddi_translations_dp; | |
1467 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1468 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
1469 | ddi_translations = bxt_ddi_translations_hdmi; | |
1470 | } else { | |
1471 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", | |
1472 | type); | |
1473 | return; | |
1474 | } | |
1475 | ||
1476 | /* Check if default value has to be used */ | |
1477 | if (level >= n_entries || | |
1478 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { | |
1479 | for (i = 0; i < n_entries; i++) { | |
1480 | if (ddi_translations[i].default_index) { | |
1481 | level = i; | |
1482 | break; | |
1483 | } | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | /* | |
1488 | * While we write to the group register to program all lanes at once we | |
1489 | * can read only lane registers and we pick lanes 0/1 for that. | |
1490 | */ | |
1491 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1492 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); | |
1493 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1494 | ||
1495 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); | |
1496 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); | |
1497 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | | |
1498 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; | |
1499 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); | |
1500 | ||
1501 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); | |
9c58a049 | 1502 | val &= ~SCALE_DCOMP_METHOD; |
96fb9f9b | 1503 | if (ddi_translations[level].enable) |
9c58a049 SJ |
1504 | val |= SCALE_DCOMP_METHOD; |
1505 | ||
1506 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
1507 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); | |
1508 | ||
96fb9f9b VK |
1509 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); |
1510 | ||
1511 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); | |
1512 | val &= ~DE_EMPHASIS; | |
1513 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; | |
1514 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); | |
1515 | ||
1516 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1517 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; | |
1518 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1519 | } | |
1520 | ||
f8896f5d DW |
1521 | static uint32_t translate_signal_level(int signal_levels) |
1522 | { | |
1523 | uint32_t level; | |
1524 | ||
1525 | switch (signal_levels) { | |
1526 | default: | |
1527 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", | |
1528 | signal_levels); | |
1529 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1530 | level = 0; | |
1531 | break; | |
1532 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1533 | level = 1; | |
1534 | break; | |
1535 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
1536 | level = 2; | |
1537 | break; | |
1538 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: | |
1539 | level = 3; | |
1540 | break; | |
1541 | ||
1542 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1543 | level = 4; | |
1544 | break; | |
1545 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1546 | level = 5; | |
1547 | break; | |
1548 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
1549 | level = 6; | |
1550 | break; | |
1551 | ||
1552 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1553 | level = 7; | |
1554 | break; | |
1555 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1556 | level = 8; | |
1557 | break; | |
1558 | ||
1559 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1560 | level = 9; | |
1561 | break; | |
1562 | } | |
1563 | ||
1564 | return level; | |
1565 | } | |
1566 | ||
1567 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) | |
1568 | { | |
1569 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 1570 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d DW |
1571 | struct intel_encoder *encoder = &dport->base; |
1572 | uint8_t train_set = intel_dp->train_set[0]; | |
1573 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
1574 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1575 | enum port port = dport->port; | |
1576 | uint32_t level; | |
1577 | ||
1578 | level = translate_signal_level(signal_levels); | |
1579 | ||
78ab0bae | 1580 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
a7d8dbc0 | 1581 | skl_ddi_set_iboost(encoder, level); |
78ab0bae VS |
1582 | else if (IS_BROXTON(dev_priv)) |
1583 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); | |
f8896f5d DW |
1584 | |
1585 | return DDI_BUF_TRANS_SELECT(level); | |
1586 | } | |
1587 | ||
e404ba8d VS |
1588 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
1589 | const struct intel_crtc_state *pipe_config) | |
6441ab5f | 1590 | { |
e404ba8d VS |
1591 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1592 | enum port port = intel_ddi_get_encoder_port(encoder); | |
6441ab5f | 1593 | |
e404ba8d VS |
1594 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
1595 | uint32_t dpll = pipe_config->ddi_pll_sel; | |
efa80add S |
1596 | uint32_t val; |
1597 | ||
5416d871 | 1598 | /* DDI -> PLL mapping */ |
efa80add S |
1599 | val = I915_READ(DPLL_CTRL2); |
1600 | ||
1601 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
1602 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
1603 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | | |
1604 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); | |
1605 | ||
1606 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 1607 | |
e404ba8d VS |
1608 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
1609 | WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); | |
1610 | I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); | |
efa80add | 1611 | } |
e404ba8d VS |
1612 | } |
1613 | ||
fd6bbda9 ML |
1614 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder, |
1615 | struct intel_crtc_state *pipe_config, | |
1616 | struct drm_connector_state *conn_state) | |
e404ba8d VS |
1617 | { |
1618 | struct drm_encoder *encoder = &intel_encoder->base; | |
6a7e4f99 | 1619 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
e404ba8d VS |
1620 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
1621 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1622 | int type = intel_encoder->type; | |
6a7e4f99 | 1623 | |
b2ccb822 VS |
1624 | if (type == INTEL_OUTPUT_HDMI) { |
1625 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1626 | ||
1627 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); | |
1628 | } | |
1629 | ||
e404ba8d VS |
1630 | if (type == INTEL_OUTPUT_EDP) { |
1631 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1632 | intel_edp_panel_on(intel_dp); | |
1633 | } | |
1634 | ||
1635 | intel_ddi_clk_select(intel_encoder, crtc->config); | |
c19b0669 | 1636 | |
cca0502b | 1637 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1638 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1639 | |
32bdc400 VS |
1640 | intel_prepare_dp_ddi_buffers(intel_encoder); |
1641 | ||
901c2daf VS |
1642 | intel_dp_set_link_params(intel_dp, crtc->config); |
1643 | ||
44905a27 | 1644 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1645 | |
1646 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1647 | intel_dp_start_link_train(intel_dp); | |
6a7e4f99 | 1648 | if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) |
3ab9c637 | 1649 | intel_dp_stop_link_train(intel_dp); |
30cf6db8 DV |
1650 | } else if (type == INTEL_OUTPUT_HDMI) { |
1651 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d8bb85e VS |
1652 | int level = intel_ddi_hdmi_level(dev_priv, port); |
1653 | ||
32bdc400 VS |
1654 | intel_prepare_hdmi_ddi_buffers(intel_encoder); |
1655 | ||
8d8bb85e VS |
1656 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1657 | skl_ddi_set_iboost(intel_encoder, level); | |
9f332437 VS |
1658 | else if (IS_BROXTON(dev_priv)) |
1659 | bxt_ddi_vswing_sequence(dev_priv, level, port, | |
1660 | INTEL_OUTPUT_HDMI); | |
30cf6db8 DV |
1661 | |
1662 | intel_hdmi->set_infoframes(encoder, | |
6e3c9717 ACO |
1663 | crtc->config->has_hdmi_sink, |
1664 | &crtc->config->base.adjusted_mode); | |
c19b0669 | 1665 | } |
6441ab5f PZ |
1666 | } |
1667 | ||
fd6bbda9 ML |
1668 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, |
1669 | struct intel_crtc_state *old_crtc_state, | |
1670 | struct drm_connector_state *old_conn_state) | |
6441ab5f PZ |
1671 | { |
1672 | struct drm_encoder *encoder = &intel_encoder->base; | |
efa80add | 1673 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1674 | struct drm_i915_private *dev_priv = to_i915(dev); |
6441ab5f | 1675 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1676 | int type = intel_encoder->type; |
2886e93f | 1677 | uint32_t val; |
a836bdf9 | 1678 | bool wait = false; |
2886e93f | 1679 | |
fd6bbda9 ML |
1680 | /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ |
1681 | ||
2886e93f PZ |
1682 | val = I915_READ(DDI_BUF_CTL(port)); |
1683 | if (val & DDI_BUF_CTL_ENABLE) { | |
1684 | val &= ~DDI_BUF_CTL_ENABLE; | |
1685 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1686 | wait = true; |
2886e93f | 1687 | } |
6441ab5f | 1688 | |
a836bdf9 PZ |
1689 | val = I915_READ(DP_TP_CTL(port)); |
1690 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1691 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1692 | I915_WRITE(DP_TP_CTL(port), val); | |
1693 | ||
1694 | if (wait) | |
1695 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1696 | ||
cca0502b | 1697 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1698 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1699 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1700 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1701 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1702 | } |
1703 | ||
ef11bdb3 | 1704 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
efa80add S |
1705 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
1706 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
1ab23380 | 1707 | else if (INTEL_INFO(dev)->gen < 9) |
efa80add | 1708 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
b2ccb822 VS |
1709 | |
1710 | if (type == INTEL_OUTPUT_HDMI) { | |
1711 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1712 | ||
1713 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
1714 | } | |
6441ab5f PZ |
1715 | } |
1716 | ||
fd6bbda9 ML |
1717 | static void intel_enable_ddi(struct intel_encoder *intel_encoder, |
1718 | struct intel_crtc_state *pipe_config, | |
1719 | struct drm_connector_state *conn_state) | |
72662e10 | 1720 | { |
6547fef8 | 1721 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1722 | struct drm_crtc *crtc = encoder->crtc; |
1723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6547fef8 | 1724 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1725 | struct drm_i915_private *dev_priv = to_i915(dev); |
6547fef8 PZ |
1726 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1727 | int type = intel_encoder->type; | |
72662e10 | 1728 | |
6547fef8 | 1729 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1730 | struct intel_digital_port *intel_dig_port = |
1731 | enc_to_dig_port(encoder); | |
1732 | ||
6547fef8 PZ |
1733 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1734 | * are ignored so nothing special needs to be done besides | |
1735 | * enabling the port. | |
1736 | */ | |
876a8cdf | 1737 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1738 | intel_dig_port->saved_port_bits | |
1739 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1740 | } else if (type == INTEL_OUTPUT_EDP) { |
1741 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1742 | ||
23f08d83 | 1743 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
3ab9c637 ID |
1744 | intel_dp_stop_link_train(intel_dp); |
1745 | ||
4be73780 | 1746 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 1747 | intel_psr_enable(intel_dp); |
c395578e | 1748 | intel_edp_drrs_enable(intel_dp); |
6547fef8 | 1749 | } |
7b9f35a6 | 1750 | |
6e3c9717 | 1751 | if (intel_crtc->config->has_audio) { |
d45a0bf5 | 1752 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
69bfe1a9 | 1753 | intel_audio_codec_enable(intel_encoder); |
7b9f35a6 | 1754 | } |
5ab432ef DV |
1755 | } |
1756 | ||
fd6bbda9 ML |
1757 | static void intel_disable_ddi(struct intel_encoder *intel_encoder, |
1758 | struct intel_crtc_state *old_crtc_state, | |
1759 | struct drm_connector_state *old_conn_state) | |
5ab432ef | 1760 | { |
d6c50ff8 | 1761 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1762 | struct drm_crtc *crtc = encoder->crtc; |
1763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d6c50ff8 | 1764 | int type = intel_encoder->type; |
7b9f35a6 | 1765 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1766 | struct drm_i915_private *dev_priv = to_i915(dev); |
d6c50ff8 | 1767 | |
6e3c9717 | 1768 | if (intel_crtc->config->has_audio) { |
69bfe1a9 | 1769 | intel_audio_codec_disable(intel_encoder); |
d45a0bf5 PZ |
1770 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
1771 | } | |
2831d842 | 1772 | |
d6c50ff8 PZ |
1773 | if (type == INTEL_OUTPUT_EDP) { |
1774 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1775 | ||
c395578e | 1776 | intel_edp_drrs_disable(intel_dp); |
0bc12bcb | 1777 | intel_psr_disable(intel_dp); |
4be73780 | 1778 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1779 | } |
72662e10 | 1780 | } |
79f689aa | 1781 | |
9c8d0b8e ID |
1782 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, |
1783 | enum dpio_phy phy) | |
bd480061 | 1784 | { |
e93da0a0 ID |
1785 | enum port port; |
1786 | ||
bd480061 ID |
1787 | if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy))) |
1788 | return false; | |
1789 | ||
1790 | if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
1791 | (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { | |
1792 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", | |
1793 | phy); | |
1794 | ||
1795 | return false; | |
1796 | } | |
1797 | ||
1798 | if (phy == DPIO_PHY1 && | |
1799 | !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) { | |
1800 | DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n"); | |
1801 | ||
1802 | return false; | |
1803 | } | |
1804 | ||
1805 | if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { | |
1806 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", | |
1807 | phy); | |
1808 | ||
1809 | return false; | |
1810 | } | |
1811 | ||
e93da0a0 ID |
1812 | for_each_port_masked(port, |
1813 | phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) : | |
1814 | BIT(PORT_A)) { | |
1815 | u32 tmp = I915_READ(BXT_PHY_CTL(port)); | |
1816 | ||
1817 | if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) { | |
1818 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane " | |
1819 | "for port %c powered down " | |
1820 | "(PHY_CTL %08x)\n", | |
1821 | phy, port_name(port), tmp); | |
1822 | ||
1823 | return false; | |
1824 | } | |
1825 | } | |
1826 | ||
bd480061 ID |
1827 | return true; |
1828 | } | |
1829 | ||
324513c0 | 1830 | static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
adc7f04b ID |
1831 | { |
1832 | u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); | |
1833 | ||
1834 | return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
1835 | } | |
1836 | ||
324513c0 ID |
1837 | static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, |
1838 | enum dpio_phy phy) | |
01a01ef2 | 1839 | { |
058fee93 CW |
1840 | if (intel_wait_for_register(dev_priv, |
1841 | BXT_PORT_REF_DW3(phy), | |
1842 | GRC_DONE, GRC_DONE, | |
1843 | 10)) | |
01a01ef2 ID |
1844 | DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); |
1845 | } | |
1846 | ||
9c8d0b8e | 1847 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
5c6706e5 | 1848 | { |
95a7a2ae | 1849 | u32 val; |
5c6706e5 | 1850 | |
9c8d0b8e | 1851 | if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { |
adc7f04b | 1852 | /* Still read out the GRC value for state verification */ |
67856d4d | 1853 | if (phy == DPIO_PHY0) |
324513c0 | 1854 | dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); |
bd480061 | 1855 | |
9c8d0b8e | 1856 | if (bxt_ddi_phy_verify_state(dev_priv, phy)) { |
47baf2a5 ID |
1857 | DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " |
1858 | "won't reprogram it\n", phy); | |
1859 | ||
1860 | return; | |
1861 | } | |
bd480061 | 1862 | |
47baf2a5 ID |
1863 | DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " |
1864 | "force reprogramming it\n", phy); | |
47baf2a5 | 1865 | } |
bd480061 | 1866 | |
5c6706e5 VK |
1867 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); |
1868 | val |= GT_DISPLAY_POWER_ON(phy); | |
1869 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
1870 | ||
b61e7996 VK |
1871 | /* |
1872 | * The PHY registers start out inaccessible and respond to reads with | |
1873 | * all 1s. Eventually they become accessible as they power up, then | |
1874 | * the reserved bit will give the default 0. Poll on the reserved bit | |
1875 | * becoming 0 to find when the PHY is accessible. | |
1876 | * HW team confirmed that the time to reach phypowergood status is | |
1877 | * anywhere between 50 us and 100us. | |
1878 | */ | |
1879 | if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
1880 | (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { | |
5c6706e5 | 1881 | DRM_ERROR("timeout during PHY%d power on\n", phy); |
b61e7996 | 1882 | } |
5c6706e5 | 1883 | |
5c6706e5 VK |
1884 | /* Program PLL Rcomp code offset */ |
1885 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
1886 | val &= ~IREF0RC_OFFSET_MASK; | |
1887 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
1888 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
1889 | ||
1890 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
1891 | val &= ~IREF1RC_OFFSET_MASK; | |
1892 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
1893 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
1894 | ||
1895 | /* Program power gating */ | |
1896 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
1897 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
1898 | SUS_CLK_CONFIG; | |
1899 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
1900 | ||
1901 | if (phy == DPIO_PHY0) { | |
1902 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); | |
1903 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; | |
1904 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); | |
1905 | } | |
1906 | ||
1907 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); | |
1908 | val &= ~OCL2_LDOFUSE_PWR_DIS; | |
1909 | /* | |
1910 | * On PHY1 disable power on the second channel, since no port is | |
1911 | * connected there. On PHY0 both channels have a port, so leave it | |
1912 | * enabled. | |
1913 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should | |
1914 | * power down the second channel on PHY0 as well. | |
28ca6931 ID |
1915 | * |
1916 | * FIXME: Clarify programming of the following, the register is | |
1917 | * read-only with bit 6 fixed at 0 at least in stepping A. | |
5c6706e5 VK |
1918 | */ |
1919 | if (phy == DPIO_PHY1) | |
1920 | val |= OCL2_LDOFUSE_PWR_DIS; | |
1921 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); | |
1922 | ||
1923 | if (phy == DPIO_PHY0) { | |
1924 | uint32_t grc_code; | |
1925 | /* | |
1926 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
1927 | * the corresponding calibrated value from PHY1, and disable | |
1928 | * the automatic calibration on PHY0. | |
1929 | */ | |
324513c0 | 1930 | val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1); |
5c6706e5 VK |
1931 | grc_code = val << GRC_CODE_FAST_SHIFT | |
1932 | val << GRC_CODE_SLOW_SHIFT | | |
1933 | val; | |
1934 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); | |
1935 | ||
1936 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); | |
1937 | val |= GRC_DIS | GRC_RDY_OVRD; | |
1938 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); | |
1939 | } | |
1940 | ||
1941 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
1942 | val |= COMMON_RESET_DIS; | |
1943 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
e4c49e0f ID |
1944 | |
1945 | if (phy == DPIO_PHY1) | |
324513c0 | 1946 | bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1); |
5c6706e5 VK |
1947 | } |
1948 | ||
9c8d0b8e | 1949 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
5c6706e5 VK |
1950 | { |
1951 | uint32_t val; | |
1952 | ||
1953 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
1954 | val &= ~COMMON_RESET_DIS; | |
1955 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
d7d33fd8 ID |
1956 | |
1957 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
1958 | val &= ~GT_DISPLAY_POWER_ON(phy); | |
1959 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
5c6706e5 VK |
1960 | } |
1961 | ||
adc7f04b ID |
1962 | static bool __printf(6, 7) |
1963 | __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
1964 | i915_reg_t reg, u32 mask, u32 expected, | |
1965 | const char *reg_fmt, ...) | |
1966 | { | |
1967 | struct va_format vaf; | |
1968 | va_list args; | |
1969 | u32 val; | |
1970 | ||
1971 | val = I915_READ(reg); | |
1972 | if ((val & mask) == expected) | |
1973 | return true; | |
1974 | ||
1975 | va_start(args, reg_fmt); | |
1976 | vaf.fmt = reg_fmt; | |
1977 | vaf.va = &args; | |
1978 | ||
1979 | DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " | |
1980 | "current %08x, expected %08x (mask %08x)\n", | |
1981 | phy, &vaf, reg.reg, val, (val & ~mask) | expected, | |
1982 | mask); | |
1983 | ||
1984 | va_end(args); | |
1985 | ||
1986 | return false; | |
1987 | } | |
1988 | ||
9c8d0b8e ID |
1989 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, |
1990 | enum dpio_phy phy) | |
adc7f04b | 1991 | { |
adc7f04b ID |
1992 | uint32_t mask; |
1993 | bool ok; | |
1994 | ||
1995 | #define _CHK(reg, mask, exp, fmt, ...) \ | |
1996 | __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ | |
1997 | ## __VA_ARGS__) | |
1998 | ||
9c8d0b8e | 1999 | if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) |
adc7f04b ID |
2000 | return false; |
2001 | ||
2002 | ok = true; | |
2003 | ||
adc7f04b ID |
2004 | /* PLL Rcomp code offset */ |
2005 | ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), | |
2006 | IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, | |
2007 | "BXT_PORT_CL1CM_DW9(%d)", phy); | |
2008 | ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), | |
2009 | IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, | |
2010 | "BXT_PORT_CL1CM_DW10(%d)", phy); | |
2011 | ||
2012 | /* Power gating */ | |
2013 | mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; | |
2014 | ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, | |
2015 | "BXT_PORT_CL1CM_DW28(%d)", phy); | |
2016 | ||
2017 | if (phy == DPIO_PHY0) | |
2018 | ok &= _CHK(BXT_PORT_CL2CM_DW6_BC, | |
2019 | DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, | |
2020 | "BXT_PORT_CL2CM_DW6_BC"); | |
2021 | ||
2022 | /* | |
2023 | * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS, | |
2024 | * at least on stepping A this bit is read-only and fixed at 0. | |
2025 | */ | |
2026 | ||
2027 | if (phy == DPIO_PHY0) { | |
2028 | u32 grc_code = dev_priv->bxt_phy_grc; | |
2029 | ||
2030 | grc_code = grc_code << GRC_CODE_FAST_SHIFT | | |
2031 | grc_code << GRC_CODE_SLOW_SHIFT | | |
2032 | grc_code; | |
2033 | mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | | |
2034 | GRC_CODE_NOM_MASK; | |
2035 | ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code, | |
2036 | "BXT_PORT_REF_DW6(%d)", DPIO_PHY0); | |
2037 | ||
2038 | mask = GRC_DIS | GRC_RDY_OVRD; | |
2039 | ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask, | |
2040 | "BXT_PORT_REF_DW8(%d)", DPIO_PHY0); | |
2041 | } | |
2042 | ||
2043 | return ok; | |
2044 | #undef _CHK | |
2045 | } | |
2046 | ||
95a7a2ae ID |
2047 | static uint8_t |
2048 | bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
2049 | struct intel_crtc_state *pipe_config) | |
2050 | { | |
2051 | switch (pipe_config->lane_count) { | |
2052 | case 1: | |
2053 | return 0; | |
2054 | case 2: | |
2055 | return BIT(2) | BIT(0); | |
2056 | case 4: | |
2057 | return BIT(3) | BIT(2) | BIT(0); | |
2058 | default: | |
2059 | MISSING_CASE(pipe_config->lane_count); | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | } | |
2064 | ||
fd6bbda9 ML |
2065 | static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, |
2066 | struct intel_crtc_state *pipe_config, | |
2067 | struct drm_connector_state *conn_state) | |
95a7a2ae ID |
2068 | { |
2069 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2070 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
2071 | enum port port = dport->port; | |
2072 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
2073 | int lane; | |
2074 | ||
2075 | for (lane = 0; lane < 4; lane++) { | |
2076 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
2077 | ||
2078 | /* | |
2079 | * Note that on CHV this flag is called UPAR, but has | |
2080 | * the same function. | |
2081 | */ | |
2082 | val &= ~LATENCY_OPTIM; | |
2083 | if (intel_crtc->config->lane_lat_optim_mask & BIT(lane)) | |
2084 | val |= LATENCY_OPTIM; | |
2085 | ||
2086 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); | |
2087 | } | |
2088 | } | |
2089 | ||
2090 | static uint8_t | |
2091 | bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) | |
2092 | { | |
2093 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2094 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
2095 | enum port port = dport->port; | |
2096 | int lane; | |
2097 | uint8_t mask; | |
2098 | ||
2099 | mask = 0; | |
2100 | for (lane = 0; lane < 4; lane++) { | |
2101 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
2102 | ||
2103 | if (val & LATENCY_OPTIM) | |
2104 | mask |= BIT(lane); | |
2105 | } | |
2106 | ||
2107 | return mask; | |
2108 | } | |
2109 | ||
ad64217b | 2110 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 2111 | { |
ad64217b ACO |
2112 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2113 | struct drm_i915_private *dev_priv = | |
2114 | to_i915(intel_dig_port->base.base.dev); | |
174edf1f | 2115 | enum port port = intel_dig_port->port; |
c19b0669 | 2116 | uint32_t val; |
f3e227df | 2117 | bool wait = false; |
c19b0669 PZ |
2118 | |
2119 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
2120 | val = I915_READ(DDI_BUF_CTL(port)); | |
2121 | if (val & DDI_BUF_CTL_ENABLE) { | |
2122 | val &= ~DDI_BUF_CTL_ENABLE; | |
2123 | I915_WRITE(DDI_BUF_CTL(port), val); | |
2124 | wait = true; | |
2125 | } | |
2126 | ||
2127 | val = I915_READ(DP_TP_CTL(port)); | |
2128 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2129 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2130 | I915_WRITE(DP_TP_CTL(port), val); | |
2131 | POSTING_READ(DP_TP_CTL(port)); | |
2132 | ||
2133 | if (wait) | |
2134 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2135 | } | |
2136 | ||
0e32b39c | 2137 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 2138 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
64ee2fd2 | 2139 | if (intel_dp->link_mst) |
0e32b39c DA |
2140 | val |= DP_TP_CTL_MODE_MST; |
2141 | else { | |
2142 | val |= DP_TP_CTL_MODE_SST; | |
2143 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2144 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
2145 | } | |
c19b0669 PZ |
2146 | I915_WRITE(DP_TP_CTL(port), val); |
2147 | POSTING_READ(DP_TP_CTL(port)); | |
2148 | ||
2149 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
2150 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
2151 | POSTING_READ(DDI_BUF_CTL(port)); | |
2152 | ||
2153 | udelay(600); | |
2154 | } | |
00c09d70 | 2155 | |
fd6bbda9 ML |
2156 | void intel_ddi_fdi_disable(struct intel_encoder *intel_encoder, |
2157 | struct intel_crtc_state *old_crtc_state, | |
2158 | struct drm_connector_state *old_conn_state) | |
1ad960f2 | 2159 | { |
fd6bbda9 | 2160 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
1ad960f2 PZ |
2161 | uint32_t val; |
2162 | ||
5b421c57 VS |
2163 | /* |
2164 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) | |
2165 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, | |
2166 | * step 13 is the correct place for it. Step 18 is where it was | |
2167 | * originally before the BUN. | |
2168 | */ | |
eede3b53 | 2169 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 2170 | val &= ~FDI_RX_ENABLE; |
eede3b53 | 2171 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 | 2172 | |
fd6bbda9 | 2173 | intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state); |
5b421c57 | 2174 | |
eede3b53 | 2175 | val = I915_READ(FDI_RX_MISC(PIPE_A)); |
1ad960f2 PZ |
2176 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
2177 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 | 2178 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); |
1ad960f2 | 2179 | |
eede3b53 | 2180 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 2181 | val &= ~FDI_PCDCLK; |
eede3b53 | 2182 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 | 2183 | |
eede3b53 | 2184 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 2185 | val &= ~FDI_RX_PLL_ENABLE; |
eede3b53 | 2186 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 PZ |
2187 | } |
2188 | ||
6801c18c | 2189 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 2190 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 2191 | { |
fac5e23e | 2192 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 | 2193 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
0cb09a97 | 2194 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 2195 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
2196 | u32 temp, flags = 0; |
2197 | ||
4d1de975 JN |
2198 | /* XXX: DSI transcoder paranoia */ |
2199 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) | |
2200 | return; | |
2201 | ||
045ac3b5 JB |
2202 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
2203 | if (temp & TRANS_DDI_PHSYNC) | |
2204 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2205 | else | |
2206 | flags |= DRM_MODE_FLAG_NHSYNC; | |
2207 | if (temp & TRANS_DDI_PVSYNC) | |
2208 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2209 | else | |
2210 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2211 | ||
2d112de7 | 2212 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2213 | |
2214 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2215 | case TRANS_DDI_BPC_6: | |
2216 | pipe_config->pipe_bpp = 18; | |
2217 | break; | |
2218 | case TRANS_DDI_BPC_8: | |
2219 | pipe_config->pipe_bpp = 24; | |
2220 | break; | |
2221 | case TRANS_DDI_BPC_10: | |
2222 | pipe_config->pipe_bpp = 30; | |
2223 | break; | |
2224 | case TRANS_DDI_BPC_12: | |
2225 | pipe_config->pipe_bpp = 36; | |
2226 | break; | |
2227 | default: | |
2228 | break; | |
2229 | } | |
eb14cb74 VS |
2230 | |
2231 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2232 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2233 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
2234 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2235 | ||
cda0aaaf | 2236 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
bbd440fb | 2237 | pipe_config->has_infoframe = true; |
d4d6279a | 2238 | /* fall through */ |
eb14cb74 | 2239 | case TRANS_DDI_MODE_SELECT_DVI: |
d4d6279a ACO |
2240 | pipe_config->lane_count = 4; |
2241 | break; | |
eb14cb74 VS |
2242 | case TRANS_DDI_MODE_SELECT_FDI: |
2243 | break; | |
2244 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2245 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
90a6b7b0 VS |
2246 | pipe_config->lane_count = |
2247 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
2248 | intel_dp_get_m_n(intel_crtc, pipe_config); |
2249 | break; | |
2250 | default: | |
2251 | break; | |
2252 | } | |
10214420 | 2253 | |
5a8f97ea L |
2254 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
2255 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
2256 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) | |
2257 | pipe_config->has_audio = true; | |
2258 | } | |
9ed109a7 | 2259 | |
6aa23e65 JN |
2260 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
2261 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
10214420 DV |
2262 | /* |
2263 | * This is a big fat ugly hack. | |
2264 | * | |
2265 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2266 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2267 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2268 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2269 | * max, not what it tells us to use. | |
2270 | * | |
2271 | * Note: This will still be broken if the eDP panel is not lit | |
2272 | * up by the BIOS, and thus we can't get the mode at module | |
2273 | * load. | |
2274 | */ | |
2275 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2276 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2277 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
10214420 | 2278 | } |
11578553 | 2279 | |
22606a18 | 2280 | intel_ddi_clock_get(encoder, pipe_config); |
95a7a2ae ID |
2281 | |
2282 | if (IS_BROXTON(dev_priv)) | |
2283 | pipe_config->lane_lat_optim_mask = | |
2284 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); | |
045ac3b5 JB |
2285 | } |
2286 | ||
5bfe2ac0 | 2287 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
2288 | struct intel_crtc_state *pipe_config, |
2289 | struct drm_connector_state *conn_state) | |
00c09d70 | 2290 | { |
fac5e23e | 2291 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5bfe2ac0 | 2292 | int type = encoder->type; |
eccb140b | 2293 | int port = intel_ddi_get_encoder_port(encoder); |
95a7a2ae | 2294 | int ret; |
00c09d70 | 2295 | |
5bfe2ac0 | 2296 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2297 | |
eccb140b DV |
2298 | if (port == PORT_A) |
2299 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2300 | ||
00c09d70 | 2301 | if (type == INTEL_OUTPUT_HDMI) |
0a478c27 | 2302 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
00c09d70 | 2303 | else |
0a478c27 | 2304 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
95a7a2ae ID |
2305 | |
2306 | if (IS_BROXTON(dev_priv) && ret) | |
2307 | pipe_config->lane_lat_optim_mask = | |
2308 | bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, | |
2309 | pipe_config); | |
2310 | ||
2311 | return ret; | |
2312 | ||
00c09d70 PZ |
2313 | } |
2314 | ||
2315 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
bf93ba67 ID |
2316 | .reset = intel_dp_encoder_reset, |
2317 | .destroy = intel_dp_encoder_destroy, | |
00c09d70 PZ |
2318 | }; |
2319 | ||
4a28ae58 PZ |
2320 | static struct intel_connector * |
2321 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2322 | { | |
2323 | struct intel_connector *connector; | |
2324 | enum port port = intel_dig_port->port; | |
2325 | ||
9bdbd0b9 | 2326 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2327 | if (!connector) |
2328 | return NULL; | |
2329 | ||
2330 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2331 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2332 | kfree(connector); | |
2333 | return NULL; | |
2334 | } | |
2335 | ||
2336 | return connector; | |
2337 | } | |
2338 | ||
2339 | static struct intel_connector * | |
2340 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2341 | { | |
2342 | struct intel_connector *connector; | |
2343 | enum port port = intel_dig_port->port; | |
2344 | ||
9bdbd0b9 | 2345 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2346 | if (!connector) |
2347 | return NULL; | |
2348 | ||
2349 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2350 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2351 | ||
2352 | return connector; | |
2353 | } | |
2354 | ||
00c09d70 PZ |
2355 | void intel_ddi_init(struct drm_device *dev, enum port port) |
2356 | { | |
fac5e23e | 2357 | struct drm_i915_private *dev_priv = to_i915(dev); |
00c09d70 PZ |
2358 | struct intel_digital_port *intel_dig_port; |
2359 | struct intel_encoder *intel_encoder; | |
2360 | struct drm_encoder *encoder; | |
311a2094 | 2361 | bool init_hdmi, init_dp; |
10e7bec3 VS |
2362 | int max_lanes; |
2363 | ||
2364 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { | |
2365 | switch (port) { | |
2366 | case PORT_A: | |
2367 | max_lanes = 4; | |
2368 | break; | |
2369 | case PORT_E: | |
2370 | max_lanes = 0; | |
2371 | break; | |
2372 | default: | |
2373 | max_lanes = 4; | |
2374 | break; | |
2375 | } | |
2376 | } else { | |
2377 | switch (port) { | |
2378 | case PORT_A: | |
2379 | max_lanes = 2; | |
2380 | break; | |
2381 | case PORT_E: | |
2382 | max_lanes = 2; | |
2383 | break; | |
2384 | default: | |
2385 | max_lanes = 4; | |
2386 | break; | |
2387 | } | |
2388 | } | |
311a2094 PZ |
2389 | |
2390 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2391 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2392 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
2393 | if (!init_dp && !init_hdmi) { | |
500ea70d | 2394 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 2395 | port_name(port)); |
500ea70d | 2396 | return; |
311a2094 | 2397 | } |
00c09d70 | 2398 | |
b14c5679 | 2399 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2400 | if (!intel_dig_port) |
2401 | return; | |
2402 | ||
00c09d70 PZ |
2403 | intel_encoder = &intel_dig_port->base; |
2404 | encoder = &intel_encoder->base; | |
2405 | ||
2406 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
580d8ed5 | 2407 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
00c09d70 | 2408 | |
5bfe2ac0 | 2409 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 | 2410 | intel_encoder->enable = intel_enable_ddi; |
95a7a2ae ID |
2411 | if (IS_BROXTON(dev_priv)) |
2412 | intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; | |
00c09d70 PZ |
2413 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
2414 | intel_encoder->disable = intel_disable_ddi; | |
2415 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2416 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2417 | intel_encoder->get_config = intel_ddi_get_config; |
bf93ba67 | 2418 | intel_encoder->suspend = intel_dp_encoder_suspend; |
00c09d70 PZ |
2419 | |
2420 | intel_dig_port->port = port; | |
bcf53de4 SM |
2421 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2422 | (DDI_BUF_PORT_REVERSAL | | |
2423 | DDI_A_4_LANES); | |
00c09d70 | 2424 | |
6c566dc9 MR |
2425 | /* |
2426 | * Bspec says that DDI_A_4_LANES is the only supported configuration | |
2427 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP | |
2428 | * wasn't lit up at boot. Force this bit on in our internal | |
2429 | * configuration so that we use the proper lane count for our | |
2430 | * calculations. | |
2431 | */ | |
2432 | if (IS_BROXTON(dev) && port == PORT_A) { | |
2433 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { | |
2434 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); | |
2435 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; | |
ed8d60f4 | 2436 | max_lanes = 4; |
6c566dc9 MR |
2437 | } |
2438 | } | |
2439 | ||
ed8d60f4 MR |
2440 | intel_dig_port->max_lanes = max_lanes; |
2441 | ||
00c09d70 | 2442 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
f68d697e | 2443 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2444 | intel_encoder->cloneable = 0; |
00c09d70 | 2445 | |
f68d697e CW |
2446 | if (init_dp) { |
2447 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2448 | goto err; | |
13cf5504 | 2449 | |
f68d697e | 2450 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
cf1d5883 SJ |
2451 | /* |
2452 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
2453 | * interrupts to check the external panel connection. | |
2454 | */ | |
e87a005d | 2455 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) |
cf1d5883 SJ |
2456 | dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
2457 | else | |
2458 | dev_priv->hotplug.irq_port[port] = intel_dig_port; | |
f68d697e | 2459 | } |
21a8e6a4 | 2460 | |
311a2094 PZ |
2461 | /* In theory we don't need the encoder->type check, but leave it just in |
2462 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2463 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2464 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2465 | goto err; | |
21a8e6a4 | 2466 | } |
f68d697e CW |
2467 | |
2468 | return; | |
2469 | ||
2470 | err: | |
2471 | drm_encoder_cleanup(encoder); | |
2472 | kfree(intel_dig_port); | |
00c09d70 | 2473 | } |