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drm/i915/cnl: Enable wrpll computation for CNL
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b
VK		 303struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4
RV		 356struct cnl_ddi_buf_trans {
357 u32 dw2_swing_sel;
358 u32 dw7_n_scalar;
359 u32 dw4_cursor_coeff;
360 u32 dw4_post_cursor_2;
361 u32 dw4_post_cursor_1;
362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
547 } else if (IS_KBL_ULT(dev_priv)) {
548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
78ab0bae 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 564 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 565 return skl_u_ddi_translations_edp;
f8896f5d 566 } else {
f8896f5d 567 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 568 return skl_ddi_translations_edp;
f8896f5d
DW		 569 }
570 }
cd1101cb 571
0fdd4918
RV		 572 if (IS_KABYLAKE(dev_priv))
573 return kbl_get_buf_trans_dp(dev_priv, n_entries);
574 else
575 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 576}
577
578static const struct ddi_buf_trans *
78ab0bae 579skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 580{
78ab0bae 581 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 582 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 583 return skl_y_ddi_translations_hdmi;
f8896f5d 584 } else {
f8896f5d 585 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 586 return skl_ddi_translations_hdmi;
f8896f5d 587 }
f8896f5d
DW		 588}
589
8d8bb85e
VS		 590static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
591{
592 int n_hdmi_entries;
593 int hdmi_level;
594 int hdmi_default_entry;
595
596 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
597
cc3f90f0 598 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 599 return hdmi_level;
600
b976dc53 601 if (IS_GEN9_BC(dev_priv)) {
8d8bb85e
VS		 602 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
603 hdmi_default_entry = 8;
604 } else if (IS_BROADWELL(dev_priv)) {
605 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
606 hdmi_default_entry = 7;
607 } else if (IS_HASWELL(dev_priv)) {
608 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
609 hdmi_default_entry = 6;
610 } else {
611 WARN(1, "ddi translation table missing\n");
612 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
613 hdmi_default_entry = 7;
614 }
615
616 /* Choose a good default if VBT is badly populated */
617 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
618 hdmi_level >= n_hdmi_entries)
619 hdmi_level = hdmi_default_entry;
620
621 return hdmi_level;
622}
623
7d1c42e6
VS		 624static const struct ddi_buf_trans *
625intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
626 int *n_entries)
627{
628 if (IS_KABYLAKE(dev_priv)) {
629 return kbl_get_buf_trans_dp(dev_priv, n_entries);
630 } else if (IS_SKYLAKE(dev_priv)) {
631 return skl_get_buf_trans_dp(dev_priv, n_entries);
632 } else if (IS_BROADWELL(dev_priv)) {
633 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
634 return bdw_ddi_translations_dp;
635 } else if (IS_HASWELL(dev_priv)) {
636 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
637 return hsw_ddi_translations_dp;
638 }
639
640 *n_entries = 0;
641 return NULL;
642}
643
644static const struct ddi_buf_trans *
645intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
646 int *n_entries)
647{
648 if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
649 return skl_get_buf_trans_edp(dev_priv, n_entries);
650 } else if (IS_BROADWELL(dev_priv)) {
651 return bdw_get_buf_trans_edp(dev_priv, n_entries);
652 } else if (IS_HASWELL(dev_priv)) {
653 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
654 return hsw_ddi_translations_dp;
655 }
656
657 *n_entries = 0;
658 return NULL;
659}
660
661static const struct ddi_buf_trans *
662intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
663 int *n_entries)
664{
665 if (IS_BROADWELL(dev_priv)) {
666 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
667 return hsw_ddi_translations_fdi;
668 } else if (IS_HASWELL(dev_priv)) {
669 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
670 return hsw_ddi_translations_fdi;
671 }
672
673 *n_entries = 0;
674 return NULL;
675}
676
e58623cb
AR		 677/*
678 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 679 * values in advance. This function programs the correct values for
680 * DP/eDP/FDI use cases.
45244b87 681 */
d7c530b2 682static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 683{
6a7e4f99 684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 685 u32 iboost_bit = 0;
7d1c42e6 686 int i, n_entries;
32bdc400 687 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 688 const struct ddi_buf_trans *ddi_translations;
e58623cb 689
cc3f90f0 690 if (IS_GEN9_LP(dev_priv))
96fb9f9b 691 return;
6a7e4f99 692
7d1c42e6
VS		 693 switch (encoder->type) {
694 case INTEL_OUTPUT_EDP:
695 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
696 &n_entries);
697 break;
698 case INTEL_OUTPUT_DP:
699 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
700 &n_entries);
701 break;
702 case INTEL_OUTPUT_ANALOG:
703 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
704 &n_entries);
705 break;
706 default:
707 MISSING_CASE(encoder->type);
708 return;
e58623cb
AR		 709 }
710
b976dc53 711 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 712 /* If we're boosting the current, set bit 31 of trans1 */
713 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
714 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
715
716 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
717 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 718 n_entries > 9))
719 n_entries = 9;
300644c7 720 }
45244b87 721
7d1c42e6 722 for (i = 0; i < n_entries; i++) {
9712e688
VS		 723 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
724 ddi_translations[i].trans1 | iboost_bit);
725 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
726 ddi_translations[i].trans2);
45244b87 727 }
32bdc400
VS		 728}
729
730/*
731 * Starting with Haswell, DDI port buffers must be programmed with correct
732 * values in advance. This function programs the correct values for
733 * HDMI/DVI use cases.
734 */
735static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
736{
737 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
738 u32 iboost_bit = 0;
739 int n_hdmi_entries, hdmi_level;
740 enum port port = intel_ddi_get_encoder_port(encoder);
741 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 742
cc3f90f0 743 if (IS_GEN9_LP(dev_priv))
ce3b7e9b
DL		 744 return;
745
32bdc400
VS		 746 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
747
b976dc53 748 if (IS_GEN9_BC(dev_priv)) {
32bdc400 749 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 750
32bdc400 751 /* If we're boosting the current, set bit 31 of trans1 */
1edaaa2f 752 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
32bdc400
VS		 753 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
754 } else if (IS_BROADWELL(dev_priv)) {
755 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
756 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
757 } else if (IS_HASWELL(dev_priv)) {
758 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
759 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
760 } else {
761 WARN(1, "ddi translation table missing\n");
762 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
763 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
764 }
765
6acab15a 766 /* Entry 9 is for HDMI: */
ed9c77d2 767 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 768 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 769 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 770 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 771}
772
248138b5
PZ		 773static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
774 enum port port)
775{
f0f59a00 776 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 777 int i;
778
3449ca85 779 for (i = 0; i < 16; i++) {
248138b5
PZ		 780 udelay(1);
781 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
782 return;
783 }
784 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
785}
c82e4d26 786
c856052a
ACO		 787static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
788{
789 switch (pll->id) {
790 case DPLL_ID_WRPLL1:
791 return PORT_CLK_SEL_WRPLL1;
792 case DPLL_ID_WRPLL2:
793 return PORT_CLK_SEL_WRPLL2;
794 case DPLL_ID_SPLL:
795 return PORT_CLK_SEL_SPLL;
796 case DPLL_ID_LCPLL_810:
797 return PORT_CLK_SEL_LCPLL_810;
798 case DPLL_ID_LCPLL_1350:
799 return PORT_CLK_SEL_LCPLL_1350;
800 case DPLL_ID_LCPLL_2700:
801 return PORT_CLK_SEL_LCPLL_2700;
802 default:
803 MISSING_CASE(pll->id);
804 return PORT_CLK_SEL_NONE;
805 }
806}
807
c82e4d26
ED		 808/* Starting with Haswell, different DDI ports can work in FDI mode for
809 * connection to the PCH-located connectors. For this, it is necessary to train
810 * both the DDI port and PCH receiver for the desired DDI buffer settings.
811 *
812 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
813 * please note that when FDI mode is active on DDI E, it shares 2 lines with
814 * DDI A (which is used for eDP)
815 */
816
dc4a1094
ACO		 817void hsw_fdi_link_train(struct intel_crtc *crtc,
818 const struct intel_crtc_state *crtc_state)
c82e4d26 819{
4cbe4b2b 820 struct drm_device *dev = crtc->base.dev;
fac5e23e 821 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 822 struct intel_encoder *encoder;
c856052a 823 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 824
4cbe4b2b 825 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 826 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 827 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 828 }
829
04945641
PZ		 830 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
831 * mode set "sequence for CRT port" document:
832 * - TP1 to TP2 time with the default value
833 * - FDI delay to 90h
8693a824
DL		 834 *
835 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 836 */
eede3b53 837 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 838 FDI_RX_PWRDN_LANE0_VAL(2) |
839 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
840
841 /* Enable the PCH Receiver FDI PLL */
3e68320e 842 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 843 FDI_RX_PLL_ENABLE |
dc4a1094 844 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 845 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
846 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 847 udelay(220);
848
849 /* Switch from Rawclk to PCDclk */
850 rx_ctl_val |= FDI_PCDCLK;
eede3b53 851 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 852
853 /* Configure Port Clock Select */
dc4a1094 854 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 855 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
856 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 857
858 /* Start the training iterating through available voltages and emphasis,
859 * testing each value twice. */
10122051 860 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 861 /* Configure DP_TP_CTL with auto-training */
862 I915_WRITE(DP_TP_CTL(PORT_E),
863 DP_TP_CTL_FDI_AUTOTRAIN |
864 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
865 DP_TP_CTL_LINK_TRAIN_PAT1 |
866 DP_TP_CTL_ENABLE);
867
876a8cdf
DL		 868 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
869 * DDI E does not support port reversal, the functionality is
870 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
871 * port reversal bit */
c82e4d26 872 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 873 DDI_BUF_CTL_ENABLE |
dc4a1094 874 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 875 DDI_BUF_TRANS_SELECT(i / 2));
04945641 876 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 877
878 udelay(600);
879
04945641 880 /* Program PCH FDI Receiver TU */
eede3b53 881 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 882
883 /* Enable PCH FDI Receiver with auto-training */
884 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 885 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
886 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 887
888 /* Wait for FDI receiver lane calibration */
889 udelay(30);
890
891 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 892 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 893 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 894 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
895 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 896
897 /* Wait for FDI auto training time */
898 udelay(5);
c82e4d26
ED		 899
900 temp = I915_READ(DP_TP_STATUS(PORT_E));
901 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 902 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 903 break;
904 }
c82e4d26 905
a308ccb3
VS		 906 /*
907 * Leave things enabled even if we failed to train FDI.
908 * Results in less fireworks from the state checker.
909 */
910 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
911 DRM_ERROR("FDI link training failed!\n");
912 break;
c82e4d26 913 }
04945641 914
5b421c57
VS		 915 rx_ctl_val &= ~FDI_RX_ENABLE;
916 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
917 POSTING_READ(FDI_RX_CTL(PIPE_A));
918
248138b5
PZ		 919 temp = I915_READ(DDI_BUF_CTL(PORT_E));
920 temp &= ~DDI_BUF_CTL_ENABLE;
921 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
922 POSTING_READ(DDI_BUF_CTL(PORT_E));
923
04945641 924 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 925 temp = I915_READ(DP_TP_CTL(PORT_E));
926 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
927 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
928 I915_WRITE(DP_TP_CTL(PORT_E), temp);
929 POSTING_READ(DP_TP_CTL(PORT_E));
930
931 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 932
04945641 933 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 934 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 935 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
936 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 937 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
938 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 939 }
940
a308ccb3
VS		 941 /* Enable normal pixel sending for FDI */
942 I915_WRITE(DP_TP_CTL(PORT_E),
943 DP_TP_CTL_FDI_AUTOTRAIN |
944 DP_TP_CTL_LINK_TRAIN_NORMAL |
945 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
946 DP_TP_CTL_ENABLE);
c82e4d26 947}
0e72a5b5 948
d7c530b2 949static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 950{
951 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
952 struct intel_digital_port *intel_dig_port =
953 enc_to_dig_port(&encoder->base);
954
955 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 956 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 957 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 958}
959
8d9ddbcb 960static struct intel_encoder *
e9ce1a62 961intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 962{
e9ce1a62 963 struct drm_device *dev = crtc->base.dev;
1524e93e 964 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 965 int num_encoders = 0;
966
1524e93e
SS		 967 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
968 ret = encoder;
8d9ddbcb
PZ		 969 num_encoders++;
970 }
971
972 if (num_encoders != 1)
84f44ce7 973 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 974 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 975
976 BUG_ON(ret == NULL);
977 return ret;
978}
979
44a126ba
PZ		 980/* Finds the only possible encoder associated with the given CRTC. */
981struct intel_encoder *
3165c074 982intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 983{
3165c074
ACO		 984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
985 struct intel_encoder *ret = NULL;
986 struct drm_atomic_state *state;
da3ced29
ACO		 987 struct drm_connector *connector;
988 struct drm_connector_state *connector_state;
d0737e1d 989 int num_encoders = 0;
3165c074 990 int i;
d0737e1d 991
3165c074
ACO		 992 state = crtc_state->base.state;
993
b77c7a90 994 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 995 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 996 continue;
997
da3ced29 998 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 999 num_encoders++;
d0737e1d
ACO		 1000 }
1001
1002 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1003 pipe_name(crtc->pipe));
1004
1005 BUG_ON(ret == NULL);
1006 return ret;
1007}
1008
1c0b85c5 1009#define LC_FREQ 2700
1c0b85c5 1010
f0f59a00
VS		 1011static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1012 i915_reg_t reg)
11578553
JB		 1013{
1014 int refclk = LC_FREQ;
1015 int n, p, r;
1016 u32 wrpll;
1017
1018 wrpll = I915_READ(reg);
114fe488
DV		 1019 switch (wrpll & WRPLL_PLL_REF_MASK) {
1020 case WRPLL_PLL_SSC:
1021 case WRPLL_PLL_NON_SSC:
11578553
JB		 1022 /*
1023 * We could calculate spread here, but our checking
1024 * code only cares about 5% accuracy, and spread is a max of
1025 * 0.5% downspread.
1026 */
1027 refclk = 135;
1028 break;
114fe488 1029 case WRPLL_PLL_LCPLL:
11578553
JB		 1030 refclk = LC_FREQ;
1031 break;
1032 default:
1033 WARN(1, "bad wrpll refclk\n");
1034 return 0;
1035 }
1036
1037 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1038 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1039 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1040
20f0ec16
JB		 1041 /* Convert to KHz, p & r have a fixed point portion */
1042 return (refclk * n * 100) / (p * r);
11578553
JB		 1043}
1044
540e732c
S		 1045static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1046 uint32_t dpll)
1047{
f0f59a00 1048 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1049 uint32_t cfgcr1_val, cfgcr2_val;
1050 uint32_t p0, p1, p2, dco_freq;
1051
923c1241
VS		 1052 cfgcr1_reg = DPLL_CFGCR1(dpll);
1053 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1054
1055 cfgcr1_val = I915_READ(cfgcr1_reg);
1056 cfgcr2_val = I915_READ(cfgcr2_reg);
1057
1058 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1059 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1060
1061 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1062 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1063 else
1064 p1 = 1;
1065
1066
1067 switch (p0) {
1068 case DPLL_CFGCR2_PDIV_1:
1069 p0 = 1;
1070 break;
1071 case DPLL_CFGCR2_PDIV_2:
1072 p0 = 2;
1073 break;
1074 case DPLL_CFGCR2_PDIV_3:
1075 p0 = 3;
1076 break;
1077 case DPLL_CFGCR2_PDIV_7:
1078 p0 = 7;
1079 break;
1080 }
1081
1082 switch (p2) {
1083 case DPLL_CFGCR2_KDIV_5:
1084 p2 = 5;
1085 break;
1086 case DPLL_CFGCR2_KDIV_2:
1087 p2 = 2;
1088 break;
1089 case DPLL_CFGCR2_KDIV_3:
1090 p2 = 3;
1091 break;
1092 case DPLL_CFGCR2_KDIV_1:
1093 p2 = 1;
1094 break;
1095 }
1096
1097 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1098
1099 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1100 1000) / 0x8000;
1101
1102 return dco_freq / (p0 * p1 * p2 * 5);
1103}
1104
398a017e
VS		 1105static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1106{
1107 int dotclock;
1108
1109 if (pipe_config->has_pch_encoder)
1110 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1111 &pipe_config->fdi_m_n);
37a5650b 1112 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1113 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1114 &pipe_config->dp_m_n);
1115 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1116 dotclock = pipe_config->port_clock * 2 / 3;
1117 else
1118 dotclock = pipe_config->port_clock;
1119
1120 if (pipe_config->pixel_multiplier)
1121 dotclock /= pipe_config->pixel_multiplier;
1122
1123 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1124}
540e732c
S		 1125
1126static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1127 struct intel_crtc_state *pipe_config)
540e732c 1128{
fac5e23e 1129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1130 int link_clock = 0;
1131 uint32_t dpll_ctl1, dpll;
1132
c856052a 1133 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1134
1135 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1136
1137 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1138 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1139 } else {
71cd8423
DL		 1140 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1141 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1142
1143 switch (link_clock) {
71cd8423 1144 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1145 link_clock = 81000;
1146 break;
71cd8423 1147 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1148 link_clock = 108000;
1149 break;
71cd8423 1150 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1151 link_clock = 135000;
1152 break;
71cd8423 1153 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1154 link_clock = 162000;
1155 break;
71cd8423 1156 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1157 link_clock = 216000;
1158 break;
71cd8423 1159 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1160 link_clock = 270000;
1161 break;
1162 default:
1163 WARN(1, "Unsupported link rate\n");
1164 break;
1165 }
1166 link_clock *= 2;
1167 }
1168
1169 pipe_config->port_clock = link_clock;
1170
398a017e 1171 ddi_dotclock_get(pipe_config);
540e732c
S		 1172}
1173
3d51278a 1174static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1175 struct intel_crtc_state *pipe_config)
11578553 1176{
fac5e23e 1177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1178 int link_clock = 0;
1179 u32 val, pll;
1180
c856052a 1181 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1182 switch (val & PORT_CLK_SEL_MASK) {
1183 case PORT_CLK_SEL_LCPLL_810:
1184 link_clock = 81000;
1185 break;
1186 case PORT_CLK_SEL_LCPLL_1350:
1187 link_clock = 135000;
1188 break;
1189 case PORT_CLK_SEL_LCPLL_2700:
1190 link_clock = 270000;
1191 break;
1192 case PORT_CLK_SEL_WRPLL1:
01403de3 1193 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1194 break;
1195 case PORT_CLK_SEL_WRPLL2:
01403de3 1196 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1197 break;
1198 case PORT_CLK_SEL_SPLL:
1199 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1200 if (pll == SPLL_PLL_FREQ_810MHz)
1201 link_clock = 81000;
1202 else if (pll == SPLL_PLL_FREQ_1350MHz)
1203 link_clock = 135000;
1204 else if (pll == SPLL_PLL_FREQ_2700MHz)
1205 link_clock = 270000;
1206 else {
1207 WARN(1, "bad spll freq\n");
1208 return;
1209 }
1210 break;
1211 default:
1212 WARN(1, "bad port clock sel\n");
1213 return;
1214 }
1215
1216 pipe_config->port_clock = link_clock * 2;
1217
398a017e 1218 ddi_dotclock_get(pipe_config);
11578553
JB		 1219}
1220
977bb38d
S		 1221static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1222 enum intel_dpll_id dpll)
1223{
aa610dcb
ID		 1224 struct intel_shared_dpll *pll;
1225 struct intel_dpll_hw_state *state;
9e2c8475 1226 struct dpll clock;
aa610dcb
ID		 1227
1228 /* For DDI ports we always use a shared PLL. */
1229 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1230 return 0;
1231
1232 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1233 state = &pll->state.hw_state;
aa610dcb
ID		 1234
1235 clock.m1 = 2;
1236 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1237 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1238 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1239 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1240 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1241 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1242
1243 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1244}
1245
1246static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1247 struct intel_crtc_state *pipe_config)
1248{
fac5e23e 1249 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1250 enum port port = intel_ddi_get_encoder_port(encoder);
1251 uint32_t dpll = port;
1252
398a017e 1253 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1254
398a017e 1255 ddi_dotclock_get(pipe_config);
977bb38d
S		 1256}
1257
3d51278a 1258void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1259 struct intel_crtc_state *pipe_config)
3d51278a 1260{
0853723b 1261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1262
0853723b 1263 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1264 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1265 else if (IS_GEN9_BC(dev_priv))
22606a18 1266 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1267 else if (IS_GEN9_LP(dev_priv))
977bb38d 1268 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1269}
1270
3dc38eea 1271void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1272{
3dc38eea 1273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1275 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1276 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1277 int type = encoder->type;
dae84799
PZ		 1278 uint32_t temp;
1279
cca0502b 1280 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1281 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1282
c9809791 1283 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1284 switch (crtc_state->pipe_bpp) {
dae84799 1285 case 18:
c9809791 1286 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1287 break;
1288 case 24:
c9809791 1289 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1290 break;
1291 case 30:
c9809791 1292 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1293 break;
1294 case 36:
c9809791 1295 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1296 break;
1297 default:
4e53c2e0 1298 BUG();
dae84799 1299 }
c9809791 1300 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1301 }
1302}
1303
3dc38eea
ACO		 1304void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1305 bool state)
0e32b39c 1306{
3dc38eea 1307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1308 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1309 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1310 uint32_t temp;
1311 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1312 if (state == true)
1313 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1314 else
1315 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1316 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1317}
1318
3dc38eea 1319void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1320{
3dc38eea 1321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1322 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1324 enum pipe pipe = crtc->pipe;
3dc38eea 1325 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1326 enum port port = intel_ddi_get_encoder_port(encoder);
1327 int type = encoder->type;
8d9ddbcb
PZ		 1328 uint32_t temp;
1329
ad80a810
PZ		 1330 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1331 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1332 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1333
3dc38eea 1334 switch (crtc_state->pipe_bpp) {
dfcef252 1335 case 18:
ad80a810 1336 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1337 break;
1338 case 24:
ad80a810 1339 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1340 break;
1341 case 30:
ad80a810 1342 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1343 break;
1344 case 36:
ad80a810 1345 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1346 break;
1347 default:
4e53c2e0 1348 BUG();
dfcef252 1349 }
72662e10 1350
3dc38eea 1351 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1352 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1353 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1354 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1355
e6f0bfc4
PZ		 1356 if (cpu_transcoder == TRANSCODER_EDP) {
1357 switch (pipe) {
1358 case PIPE_A:
c7670b10
PZ		 1359 /* On Haswell, can only use the always-on power well for
1360 * eDP when not using the panel fitter, and when not
1361 * using motion blur mitigation (which we don't
1362 * support). */
772c2a51 1363 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1364 (crtc_state->pch_pfit.enabled ||
1365 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1366 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1367 else
1368 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1369 break;
1370 case PIPE_B:
1371 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1372 break;
1373 case PIPE_C:
1374 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1375 break;
1376 default:
1377 BUG();
1378 break;
1379 }
1380 }
1381
7739c33b 1382 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1383 if (crtc_state->has_hdmi_sink)
ad80a810 1384 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1385 else
ad80a810 1386 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1387
1388 if (crtc_state->hdmi_scrambling)
1389 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1390 if (crtc_state->hdmi_high_tmds_clock_ratio)
1391 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1392 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1393 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1394 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1395 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1396 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1397 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1398 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1399 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1400 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1401 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1402 } else {
84f44ce7 1403 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1404 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1405 }
1406
ad80a810 1407 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1408}
72662e10 1409
ad80a810
PZ		 1410void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1411 enum transcoder cpu_transcoder)
8d9ddbcb 1412{
f0f59a00 1413 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1414 uint32_t val = I915_READ(reg);
1415
0e32b39c 1416 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1417 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1418 I915_WRITE(reg, val);
72662e10
ED		 1419}
1420
bcbc889b
PZ		 1421bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1422{
1423 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1424 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1425 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1426 int type = intel_connector->base.connector_type;
1524e93e 1427 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1428 enum pipe pipe = 0;
1429 enum transcoder cpu_transcoder;
1430 uint32_t tmp;
e27daab4 1431 bool ret;
bcbc889b 1432
79f255a0 1433 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1434 encoder->power_domain))
882244a3
PZ		 1435 return false;
1436
1524e93e 1437 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1438 ret = false;
1439 goto out;
1440 }
bcbc889b
PZ		 1441
1442 if (port == PORT_A)
1443 cpu_transcoder = TRANSCODER_EDP;
1444 else
1a240d4d 1445 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1446
1447 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1448
1449 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1450 case TRANS_DDI_MODE_SELECT_HDMI:
1451 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1452 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1453 break;
bcbc889b
PZ		 1454
1455 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1456 ret = type == DRM_MODE_CONNECTOR_eDP ||
1457 type == DRM_MODE_CONNECTOR_DisplayPort;
1458 break;
1459
0e32b39c
DA		 1460 case TRANS_DDI_MODE_SELECT_DP_MST:
1461 /* if the transcoder is in MST state then
1462 * connector isn't connected */
e27daab4
ID		 1463 ret = false;
1464 break;
bcbc889b
PZ		 1465
1466 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1467 ret = type == DRM_MODE_CONNECTOR_VGA;
1468 break;
bcbc889b
PZ		 1469
1470 default:
e27daab4
ID		 1471 ret = false;
1472 break;
bcbc889b 1473 }
e27daab4
ID		 1474
1475out:
1524e93e 1476 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1477
1478 return ret;
bcbc889b
PZ		 1479}
1480
85234cdc
DV		 1481bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1482 enum pipe *pipe)
1483{
1484 struct drm_device *dev = encoder->base.dev;
fac5e23e 1485 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1486 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1487 u32 tmp;
1488 int i;
e27daab4 1489 bool ret;
85234cdc 1490
79f255a0
ACO		 1491 if (!intel_display_power_get_if_enabled(dev_priv,
1492 encoder->power_domain))
6d129bea
ID		 1493 return false;
1494
e27daab4
ID		 1495 ret = false;
1496
fe43d3f5 1497 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1498
1499 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1500 goto out;
85234cdc 1501
ad80a810
PZ		 1502 if (port == PORT_A) {
1503 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1504
ad80a810
PZ		 1505 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1506 case TRANS_DDI_EDP_INPUT_A_ON:
1507 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1508 *pipe = PIPE_A;
1509 break;
1510 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1511 *pipe = PIPE_B;
1512 break;
1513 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1514 *pipe = PIPE_C;
1515 break;
1516 }
1517
e27daab4 1518 ret = true;
ad80a810 1519
e27daab4
ID		 1520 goto out;
1521 }
0e32b39c 1522
e27daab4
ID		 1523 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1524 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1525
1526 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1527 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1528 TRANS_DDI_MODE_SELECT_DP_MST)
1529 goto out;
1530
1531 *pipe = i;
1532 ret = true;
1533
1534 goto out;
85234cdc
DV		 1535 }
1536 }
1537
84f44ce7 1538 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1539
e27daab4 1540out:
cc3f90f0 1541 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0
ID		 1542 tmp = I915_READ(BXT_PHY_CTL(port));
1543 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1544 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1545 DRM_ERROR("Port %c enabled but PHY powered down? "
1546 "(PHY_CTL %08x)\n", port_name(port), tmp);
1547 }
1548
79f255a0 1549 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1550
1551 return ret;
85234cdc
DV		 1552}
1553
62b69566
ACO		 1554static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1555{
1556 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1557 enum pipe pipe;
1558
1559 if (intel_ddi_get_hw_state(encoder, &pipe))
1560 return BIT_ULL(dig_port->ddi_io_power_domain);
1561
1562 return 0;
1563}
1564
3dc38eea 1565void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1566{
3dc38eea 1567 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1569 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1570 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1571 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1572
bb523fc0
PZ		 1573 if (cpu_transcoder != TRANSCODER_EDP)
1574 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1575 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1576}
1577
3dc38eea 1578void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1579{
3dc38eea
ACO		 1580 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1581 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1582
bb523fc0
PZ		 1583 if (cpu_transcoder != TRANSCODER_EDP)
1584 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1585 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1586}
1587
a7d8dbc0
VS		 1588static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1589 enum port port, uint8_t iboost)
f8896f5d 1590{
a7d8dbc0
VS		 1591 u32 tmp;
1592
1593 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1594 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1595 if (iboost)
1596 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1597 else
1598 tmp |= BALANCE_LEG_DISABLE(port);
1599 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1600}
1601
1602static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1603{
1604 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1605 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1606 enum port port = intel_dig_port->port;
1607 int type = encoder->type;
f8896f5d
DW		 1608 const struct ddi_buf_trans *ddi_translations;
1609 uint8_t iboost;
75067dde 1610 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1611 int n_entries;
f8896f5d 1612
75067dde
AK		 1613 /* VBT may override standard boost values */
1614 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1615 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1616
cca0502b 1617 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1618 if (dp_iboost) {
1619 iboost = dp_iboost;
1620 } else {
0fdd4918
RV		 1621 if (IS_KABYLAKE(dev_priv))
1622 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1623 &n_entries);
1624 else
1625 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1626 &n_entries);
e4d4c05b 1627 iboost = ddi_translations[level].i_boost;
75067dde 1628 }
f8896f5d 1629 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1630 if (dp_iboost) {
1631 iboost = dp_iboost;
1632 } else {
78ab0bae 1633 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1634
1635 if (WARN_ON(port != PORT_A &&
1636 port != PORT_E && n_entries > 9))
1637 n_entries = 9;
1638
e4d4c05b 1639 iboost = ddi_translations[level].i_boost;
75067dde 1640 }
f8896f5d 1641 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1642 if (hdmi_iboost) {
1643 iboost = hdmi_iboost;
1644 } else {
78ab0bae 1645 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1646 iboost = ddi_translations[level].i_boost;
75067dde 1647 }
f8896f5d
DW		 1648 } else {
1649 return;
1650 }
1651
1652 /* Make sure that the requested I_boost is valid */
1653 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1654 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1655 return;
1656 }
1657
a7d8dbc0 1658 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1659
a7d8dbc0
VS		 1660 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1661 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1662}
1663
78ab0bae
VS		 1664static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1665 u32 level, enum port port, int type)
96fb9f9b 1666{
96fb9f9b
VK		 1667 const struct bxt_ddi_buf_trans *ddi_translations;
1668 u32 n_entries, i;
96fb9f9b 1669
06411f08 1670 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1671 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1672 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1673 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1674 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1675 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1676 ddi_translations = bxt_ddi_translations_dp;
1677 } else if (type == INTEL_OUTPUT_HDMI) {
1678 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1679 ddi_translations = bxt_ddi_translations_hdmi;
1680 } else {
1681 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1682 type);
1683 return;
1684 }
1685
1686 /* Check if default value has to be used */
1687 if (level >= n_entries ||
1688 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1689 for (i = 0; i < n_entries; i++) {
1690 if (ddi_translations[i].default_index) {
1691 level = i;
1692 break;
1693 }
1694 }
1695 }
1696
b6e08203
ACO		 1697 bxt_ddi_phy_set_signal_level(dev_priv, port,
1698 ddi_translations[level].margin,
1699 ddi_translations[level].scale,
1700 ddi_translations[level].enable,
1701 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1702}
1703
ffe5111e
VS		 1704u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1705{
1706 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1707 int n_entries;
1708
1709 if (encoder->type == INTEL_OUTPUT_EDP)
1710 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1711 else
1712 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1713
1714 if (WARN_ON(n_entries < 1))
1715 n_entries = 1;
1716 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1717 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1718
1719 return index_to_dp_signal_levels[n_entries - 1] &
1720 DP_TRAIN_VOLTAGE_SWING_MASK;
1721}
1722
cf54ca8b
RV		 1723static const struct cnl_ddi_buf_trans *
1724cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1725 u32 voltage, int *n_entries)
1726{
1727 if (voltage == VOLTAGE_INFO_0_85V) {
1728 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1729 return cnl_ddi_translations_hdmi_0_85V;
1730 } else if (voltage == VOLTAGE_INFO_0_95V) {
1731 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1732 return cnl_ddi_translations_hdmi_0_95V;
1733 } else if (voltage == VOLTAGE_INFO_1_05V) {
1734 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1735 return cnl_ddi_translations_hdmi_1_05V;
1736 }
1737 return NULL;
1738}
1739
1740static const struct cnl_ddi_buf_trans *
1741cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1742 u32 voltage, int *n_entries)
1743{
1744 if (voltage == VOLTAGE_INFO_0_85V) {
1745 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1746 return cnl_ddi_translations_dp_0_85V;
1747 } else if (voltage == VOLTAGE_INFO_0_95V) {
1748 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1749 return cnl_ddi_translations_dp_0_95V;
1750 } else if (voltage == VOLTAGE_INFO_1_05V) {
1751 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1752 return cnl_ddi_translations_dp_1_05V;
1753 }
1754 return NULL;
1755}
1756
1757static const struct cnl_ddi_buf_trans *
1758cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1759 u32 voltage, int *n_entries)
1760{
1761 if (dev_priv->vbt.edp.low_vswing) {
1762 if (voltage == VOLTAGE_INFO_0_85V) {
1763 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1764 return cnl_ddi_translations_dp_0_85V;
1765 } else if (voltage == VOLTAGE_INFO_0_95V) {
1766 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1767 return cnl_ddi_translations_edp_0_95V;
1768 } else if (voltage == VOLTAGE_INFO_1_05V) {
1769 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1770 return cnl_ddi_translations_edp_1_05V;
1771 }
1772 return NULL;
1773 } else {
1774 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1775 }
1776}
1777
1778static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1779 u32 level, enum port port, int type)
1780{
1781 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1782 u32 n_entries, val, voltage;
1783 int ln;
1784
1785 /*
1786 * Values for each port type are listed in
1787 * voltage swing programming tables.
1788 * Vccio voltage found in PORT_COMP_DW3.
1789 */
1790 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1791
1792 if (type == INTEL_OUTPUT_HDMI) {
1793 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1794 voltage, &n_entries);
1795 } else if (type == INTEL_OUTPUT_DP) {
1796 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1797 voltage, &n_entries);
1798 } else if (type == INTEL_OUTPUT_EDP) {
1799 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1800 voltage, &n_entries);
1801 }
1802
1803 if (ddi_translations == NULL) {
1804 MISSING_CASE(voltage);
1805 return;
1806 }
1807
1808 if (level >= n_entries) {
1809 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1810 level = n_entries - 1;
1811 }
1812
1813 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1814 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1815 val |= SCALING_MODE_SEL(2);
1816 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1817
1818 /* Program PORT_TX_DW2 */
1819 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1820 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1821 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1822 /* Rcomp scalar is fixed as 0x98 for every table entry */
1823 val |= RCOMP_SCALAR(0x98);
1824 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1825
1826 /* Program PORT_TX_DW4 */
1827 /* We cannot write to GRP. It would overrite individual loadgen */
1828 for (ln = 0; ln < 4; ln++) {
1829 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1830 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1831 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1832 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1833 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1834 }
1835
1836 /* Program PORT_TX_DW5 */
1837 /* All DW5 values are fixed for every table entry */
1838 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1839 val |= RTERM_SELECT(6);
1840 val |= TAP3_DISABLE;
1841 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1842
1843 /* Program PORT_TX_DW7 */
1844 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1845 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1846 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1847}
1848
0091abc3 1849static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1850{
0091abc3
CT		 1851 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853 enum port port = intel_ddi_get_encoder_port(encoder);
1854 int type = encoder->type;
1855 int width = 0;
1856 int rate = 0;
cf54ca8b 1857 u32 val;
0091abc3
CT		 1858 int ln = 0;
1859
1860 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1861 width = intel_dp->lane_count;
1862 rate = intel_dp->link_rate;
1863 } else {
1864 width = 4;
1865 /* Rate is always < than 6GHz for HDMI */
1866 }
cf54ca8b
RV		 1867
1868 /*
1869 * 1. If port type is eDP or DP,
1870 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1871 * else clear to 0b.
1872 */
1873 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1874 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1875 val |= COMMON_KEEPER_EN;
1876 else
1877 val &= ~COMMON_KEEPER_EN;
1878 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1879
1880 /* 2. Program loadgen select */
1881 /*
0091abc3
CT		 1882 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1883 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1884 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1885 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 1886 */
0091abc3
CT		 1887 for (ln = 0; ln <= 3; ln++) {
1888 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1889 val &= ~LOADGEN_SELECT;
1890
1891 if (((rate < 600000) && (width == 4) && (ln >= 1)) ||
1892 ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
1893 val |= LOADGEN_SELECT;
1894 }
1895 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1896 }
cf54ca8b
RV		 1897
1898 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1899 val = I915_READ(CNL_PORT_CL1CM_DW5);
1900 val |= SUS_CLOCK_CONFIG;
1901 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
1902
1903 /* 4. Clear training enable to change swing values */
1904 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1905 val &= ~TX_TRAINING_EN;
1906 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1907
1908 /* 5. Program swing and de-emphasis */
1909 cnl_ddi_vswing_program(dev_priv, level, port, type);
1910
1911 /* 6. Set training enable to trigger update */
1912 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1913 val |= TX_TRAINING_EN;
1914 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1915}
1916
f8896f5d
DW		 1917static uint32_t translate_signal_level(int signal_levels)
1918{
97eeb872 1919 int i;
f8896f5d 1920
97eeb872
VS		 1921 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1922 if (index_to_dp_signal_levels[i] == signal_levels)
1923 return i;
f8896f5d
DW		 1924 }
1925
97eeb872
VS		 1926 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1927 signal_levels);
1928
1929 return 0;
f8896f5d
DW		 1930}
1931
1932uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1933{
1934 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 1935 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 1936 struct intel_encoder *encoder = &dport->base;
1937 uint8_t train_set = intel_dp->train_set[0];
1938 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1939 DP_TRAIN_PRE_EMPHASIS_MASK);
1940 enum port port = dport->port;
1941 uint32_t level;
1942
1943 level = translate_signal_level(signal_levels);
1944
b976dc53 1945 if (IS_GEN9_BC(dev_priv))
a7d8dbc0 1946 skl_ddi_set_iboost(encoder, level);
cc3f90f0 1947 else if (IS_GEN9_LP(dev_priv))
78ab0bae 1948 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
cf54ca8b 1949 else if (IS_CANNONLAKE(dev_priv)) {
0091abc3 1950 cnl_ddi_vswing_sequence(encoder, level);
cf54ca8b
RV		 1951 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
1952 return 0;
1953 }
f8896f5d
DW		 1954 return DDI_BUF_TRANS_SELECT(level);
1955}
1956
d7c530b2
PZ		 1957static void intel_ddi_clk_select(struct intel_encoder *encoder,
1958 struct intel_shared_dpll *pll)
6441ab5f 1959{
e404ba8d
VS		 1960 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1961 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 1962 uint32_t val;
6441ab5f 1963
c856052a
ACO		 1964 if (WARN_ON(!pll))
1965 return;
1966
555e38d2
RV		 1967 if (IS_CANNONLAKE(dev_priv)) {
1968 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
1969 val = I915_READ(DPCLKA_CFGCR0);
1970 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
1971 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 1972
555e38d2
RV		 1973 /*
1974 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
1975 * This step and the step before must be done with separate
1976 * register writes.
1977 */
1978 val = I915_READ(DPCLKA_CFGCR0);
1979 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
1980 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
1981 I915_WRITE(DPCLKA_CFGCR0, val);
1982 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 1983 /* DDI -> PLL mapping */
efa80add
S		 1984 val = I915_READ(DPLL_CTRL2);
1985
1986 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1987 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 1988 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 1989 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1990
1991 I915_WRITE(DPLL_CTRL2, val);
5416d871 1992
e404ba8d 1993 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 1994 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 1995 }
e404ba8d
VS		 1996}
1997
ba88d153
MN		 1998static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
1999 int link_rate, uint32_t lane_count,
2000 struct intel_shared_dpll *pll,
2001 bool link_mst)
e404ba8d 2002{
ba88d153
MN		 2003 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2005 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2006 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
b2ccb822 2007
e081c846
ACO		 2008 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2009
ba88d153
MN		 2010 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2011 link_mst);
2012 if (encoder->type == INTEL_OUTPUT_EDP)
e404ba8d 2013 intel_edp_panel_on(intel_dp);
32bdc400 2014
ba88d153 2015 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2016
2017 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2018
ba88d153
MN		 2019 intel_prepare_dp_ddi_buffers(encoder);
2020 intel_ddi_init_dp_buf_reg(encoder);
2021 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2022 intel_dp_start_link_train(intel_dp);
2023 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2024 intel_dp_stop_link_train(intel_dp);
2025}
901c2daf 2026
ba88d153
MN		 2027static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2028 bool has_hdmi_sink,
ac240288
ML		 2029 const struct intel_crtc_state *crtc_state,
2030 const struct drm_connector_state *conn_state,
ba88d153
MN		 2031 struct intel_shared_dpll *pll)
2032{
2033 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2035 struct drm_encoder *drm_encoder = &encoder->base;
2036 enum port port = intel_ddi_get_encoder_port(encoder);
2037 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2038 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2039
ba88d153
MN		 2040 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2041 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2042
2043 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2044
ba88d153 2045 intel_prepare_hdmi_ddi_buffers(encoder);
b976dc53 2046 if (IS_GEN9_BC(dev_priv))
ba88d153 2047 skl_ddi_set_iboost(encoder, level);
cc3f90f0 2048 else if (IS_GEN9_LP(dev_priv))
ba88d153
MN		 2049 bxt_ddi_vswing_sequence(dev_priv, level, port,
2050 INTEL_OUTPUT_HDMI);
cf54ca8b 2051 else if (IS_CANNONLAKE(dev_priv))
0091abc3 2052 cnl_ddi_vswing_sequence(encoder, level);
8d8bb85e 2053
ba88d153
MN		 2054 intel_hdmi->set_infoframes(drm_encoder,
2055 has_hdmi_sink,
ac240288 2056 crtc_state, conn_state);
ba88d153 2057}
32bdc400 2058
1524e93e 2059static void intel_ddi_pre_enable(struct intel_encoder *encoder,
ba88d153
MN		 2060 struct intel_crtc_state *pipe_config,
2061 struct drm_connector_state *conn_state)
2062{
1524e93e 2063 int type = encoder->type;
30cf6db8 2064
ba88d153 2065 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1524e93e 2066 intel_ddi_pre_enable_dp(encoder,
3dc38eea
ACO		 2067 pipe_config->port_clock,
2068 pipe_config->lane_count,
2069 pipe_config->shared_dpll,
2070 intel_crtc_has_type(pipe_config,
ba88d153
MN		 2071 INTEL_OUTPUT_DP_MST));
2072 }
2073 if (type == INTEL_OUTPUT_HDMI) {
1524e93e 2074 intel_ddi_pre_enable_hdmi(encoder,
ac240288
ML		 2075 pipe_config->has_hdmi_sink,
2076 pipe_config, conn_state,
3dc38eea 2077 pipe_config->shared_dpll);
c19b0669 2078 }
6441ab5f
PZ		 2079}
2080
fd6bbda9
ML		 2081static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2082 struct intel_crtc_state *old_crtc_state,
2083 struct drm_connector_state *old_conn_state)
6441ab5f
PZ		 2084{
2085 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2086 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6441ab5f 2087 enum port port = intel_ddi_get_encoder_port(intel_encoder);
62b69566 2088 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
7618138d 2089 struct intel_dp *intel_dp = NULL;
82a4d9c0 2090 int type = intel_encoder->type;
2886e93f 2091 uint32_t val;
a836bdf9 2092 bool wait = false;
2886e93f 2093
fd6bbda9
ML		 2094 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2095
7618138d
ID		 2096 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2097 intel_dp = enc_to_intel_dp(encoder);
2098 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2099 }
2100
2886e93f
PZ		 2101 val = I915_READ(DDI_BUF_CTL(port));
2102 if (val & DDI_BUF_CTL_ENABLE) {
2103 val &= ~DDI_BUF_CTL_ENABLE;
2104 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2105 wait = true;
2886e93f 2106 }
6441ab5f 2107
a836bdf9
PZ		 2108 val = I915_READ(DP_TP_CTL(port));
2109 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2110 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2111 I915_WRITE(DP_TP_CTL(port), val);
2112
2113 if (wait)
2114 intel_wait_ddi_buf_idle(dev_priv, port);
2115
7618138d 2116 if (intel_dp) {
24f3e092 2117 intel_edp_panel_vdd_on(intel_dp);
4be73780 2118 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2119 }
2120
62b69566
ACO		 2121 if (dig_port)
2122 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2123
555e38d2
RV		 2124 if (IS_CANNONLAKE(dev_priv))
2125 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2126 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2127 else if (IS_GEN9_BC(dev_priv))
efa80add
S		 2128 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2129 DPLL_CTRL2_DDI_CLK_OFF(port)));
66478475 2130 else if (INTEL_GEN(dev_priv) < 9)
efa80add 2131 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 2132
2133 if (type == INTEL_OUTPUT_HDMI) {
2134 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2135
2136 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2137 }
6441ab5f
PZ		 2138}
2139
1524e93e 2140void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
b7076546
ML		 2141 struct intel_crtc_state *old_crtc_state,
2142 struct drm_connector_state *old_conn_state)
2143{
1524e93e 2144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2145 uint32_t val;
2146
2147 /*
2148 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2149 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2150 * step 13 is the correct place for it. Step 18 is where it was
2151 * originally before the BUN.
2152 */
2153 val = I915_READ(FDI_RX_CTL(PIPE_A));
2154 val &= ~FDI_RX_ENABLE;
2155 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2156
1524e93e 2157 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
b7076546
ML		 2158
2159 val = I915_READ(FDI_RX_MISC(PIPE_A));
2160 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2161 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2162 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2163
2164 val = I915_READ(FDI_RX_CTL(PIPE_A));
2165 val &= ~FDI_PCDCLK;
2166 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2167
2168 val = I915_READ(FDI_RX_CTL(PIPE_A));
2169 val &= ~FDI_RX_PLL_ENABLE;
2170 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2171}
2172
fd6bbda9
ML		 2173static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2174 struct intel_crtc_state *pipe_config,
2175 struct drm_connector_state *conn_state)
72662e10 2176{
6547fef8 2177 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2178 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6547fef8
PZ		 2179 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2180 int type = intel_encoder->type;
72662e10 2181
6547fef8 2182 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2183 struct intel_digital_port *intel_dig_port =
2184 enc_to_dig_port(encoder);
15953637
SS		 2185 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2186 bool scrambling = pipe_config->hdmi_scrambling;
2187
2188 intel_hdmi_handle_sink_scrambling(intel_encoder,
2189 conn_state->connector,
2190 clock_ratio, scrambling);
876a8cdf 2191
6547fef8
PZ		 2192 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2193 * are ignored so nothing special needs to be done besides
2194 * enabling the port.
2195 */
876a8cdf 2196 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2197 intel_dig_port->saved_port_bits |
2198 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2199 } else if (type == INTEL_OUTPUT_EDP) {
2200 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2201
66478475 2202 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3ab9c637
ID		 2203 intel_dp_stop_link_train(intel_dp);
2204
b037d58f 2205 intel_edp_backlight_on(pipe_config, conn_state);
0bc12bcb 2206 intel_psr_enable(intel_dp);
85cb48a1 2207 intel_edp_drrs_enable(intel_dp, pipe_config);
6547fef8 2208 }
7b9f35a6 2209
37255d8d 2210 if (pipe_config->has_audio)
bbf35e9d 2211 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
5ab432ef
DV		 2212}
2213
fd6bbda9
ML		 2214static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2215 struct intel_crtc_state *old_crtc_state,
2216 struct drm_connector_state *old_conn_state)
5ab432ef 2217{
d6c50ff8
PZ		 2218 struct drm_encoder *encoder = &intel_encoder->base;
2219 int type = intel_encoder->type;
2220
37255d8d 2221 if (old_crtc_state->has_audio)
69bfe1a9 2222 intel_audio_codec_disable(intel_encoder);
2831d842 2223
15953637
SS		 2224 if (type == INTEL_OUTPUT_HDMI) {
2225 intel_hdmi_handle_sink_scrambling(intel_encoder,
2226 old_conn_state->connector,
2227 false, false);
2228 }
2229
d6c50ff8
PZ		 2230 if (type == INTEL_OUTPUT_EDP) {
2231 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2232
85cb48a1 2233 intel_edp_drrs_disable(intel_dp, old_crtc_state);
0bc12bcb 2234 intel_psr_disable(intel_dp);
b037d58f 2235 intel_edp_backlight_off(old_conn_state);
d6c50ff8 2236 }
72662e10 2237}
79f689aa 2238
fd6bbda9
ML		 2239static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2240 struct intel_crtc_state *pipe_config,
2241 struct drm_connector_state *conn_state)
95a7a2ae 2242{
3dc38eea 2243 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2244
47a6bc61 2245 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2246}
2247
ad64217b 2248void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2249{
ad64217b
ACO		 2250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2251 struct drm_i915_private *dev_priv =
2252 to_i915(intel_dig_port->base.base.dev);
174edf1f 2253 enum port port = intel_dig_port->port;
c19b0669 2254 uint32_t val;
f3e227df 2255 bool wait = false;
c19b0669
PZ		 2256
2257 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2258 val = I915_READ(DDI_BUF_CTL(port));
2259 if (val & DDI_BUF_CTL_ENABLE) {
2260 val &= ~DDI_BUF_CTL_ENABLE;
2261 I915_WRITE(DDI_BUF_CTL(port), val);
2262 wait = true;
2263 }
2264
2265 val = I915_READ(DP_TP_CTL(port));
2266 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2267 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2268 I915_WRITE(DP_TP_CTL(port), val);
2269 POSTING_READ(DP_TP_CTL(port));
2270
2271 if (wait)
2272 intel_wait_ddi_buf_idle(dev_priv, port);
2273 }
2274
0e32b39c 2275 val = DP_TP_CTL_ENABLE |
c19b0669 2276 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2277 if (intel_dp->link_mst)
0e32b39c
DA		 2278 val |= DP_TP_CTL_MODE_MST;
2279 else {
2280 val |= DP_TP_CTL_MODE_SST;
2281 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2282 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2283 }
c19b0669
PZ		 2284 I915_WRITE(DP_TP_CTL(port), val);
2285 POSTING_READ(DP_TP_CTL(port));
2286
2287 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2288 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2289 POSTING_READ(DDI_BUF_CTL(port));
2290
2291 udelay(600);
2292}
00c09d70 2293
9935f7fa
LY		 2294bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2295 struct intel_crtc *intel_crtc)
2296{
2297 u32 temp;
2298
2299 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2300 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2301 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2302 return true;
2303 }
2304 return false;
2305}
2306
6801c18c 2307void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2308 struct intel_crtc_state *pipe_config)
045ac3b5 2309{
fac5e23e 2310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2312 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2313 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2314 u32 temp, flags = 0;
2315
4d1de975
JN		 2316 /* XXX: DSI transcoder paranoia */
2317 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2318 return;
2319
045ac3b5
JB		 2320 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2321 if (temp & TRANS_DDI_PHSYNC)
2322 flags |= DRM_MODE_FLAG_PHSYNC;
2323 else
2324 flags |= DRM_MODE_FLAG_NHSYNC;
2325 if (temp & TRANS_DDI_PVSYNC)
2326 flags |= DRM_MODE_FLAG_PVSYNC;
2327 else
2328 flags |= DRM_MODE_FLAG_NVSYNC;
2329
2d112de7 2330 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2331
2332 switch (temp & TRANS_DDI_BPC_MASK) {
2333 case TRANS_DDI_BPC_6:
2334 pipe_config->pipe_bpp = 18;
2335 break;
2336 case TRANS_DDI_BPC_8:
2337 pipe_config->pipe_bpp = 24;
2338 break;
2339 case TRANS_DDI_BPC_10:
2340 pipe_config->pipe_bpp = 30;
2341 break;
2342 case TRANS_DDI_BPC_12:
2343 pipe_config->pipe_bpp = 36;
2344 break;
2345 default:
2346 break;
2347 }
eb14cb74
VS		 2348
2349 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2350 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2351 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2352 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2353
cda0aaaf 2354 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2355 pipe_config->has_infoframe = true;
15953637
SS		 2356
2357 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2358 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2359 pipe_config->hdmi_scrambling = true;
2360 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2361 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2362 /* fall through */
eb14cb74 2363 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2364 pipe_config->lane_count = 4;
2365 break;
eb14cb74
VS		 2366 case TRANS_DDI_MODE_SELECT_FDI:
2367 break;
2368 case TRANS_DDI_MODE_SELECT_DP_SST:
2369 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2370 pipe_config->lane_count =
2371 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2372 intel_dp_get_m_n(intel_crtc, pipe_config);
2373 break;
2374 default:
2375 break;
2376 }
10214420 2377
9935f7fa
LY		 2378 pipe_config->has_audio =
2379 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2380
6aa23e65
JN		 2381 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2382 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2383 /*
2384 * This is a big fat ugly hack.
2385 *
2386 * Some machines in UEFI boot mode provide us a VBT that has 18
2387 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2388 * unknown we fail to light up. Yet the same BIOS boots up with
2389 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2390 * max, not what it tells us to use.
2391 *
2392 * Note: This will still be broken if the eDP panel is not lit
2393 * up by the BIOS, and thus we can't get the mode at module
2394 * load.
2395 */
2396 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2397 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2398 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2399 }
11578553 2400
22606a18 2401 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2402
cc3f90f0 2403 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2404 pipe_config->lane_lat_optim_mask =
2405 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2406}
2407
5bfe2ac0 2408static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2409 struct intel_crtc_state *pipe_config,
2410 struct drm_connector_state *conn_state)
00c09d70 2411{
fac5e23e 2412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2413 int type = encoder->type;
eccb140b 2414 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2415 int ret;
00c09d70 2416
5bfe2ac0 2417 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2418
eccb140b
DV		 2419 if (port == PORT_A)
2420 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2421
00c09d70 2422 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2423 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2424 else
0a478c27 2425 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2426
cc3f90f0 2427 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2428 pipe_config->lane_lat_optim_mask =
2429 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2430 pipe_config->lane_count);
95a7a2ae
ID		 2431
2432 return ret;
2433
00c09d70
PZ		 2434}
2435
2436static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2437 .reset = intel_dp_encoder_reset,
2438 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2439};
2440
4a28ae58
PZ		 2441static struct intel_connector *
2442intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2443{
2444 struct intel_connector *connector;
2445 enum port port = intel_dig_port->port;
2446
9bdbd0b9 2447 connector = intel_connector_alloc();
4a28ae58
PZ		 2448 if (!connector)
2449 return NULL;
2450
2451 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2452 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2453 kfree(connector);
2454 return NULL;
2455 }
2456
2457 return connector;
2458}
2459
2460static struct intel_connector *
2461intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2462{
2463 struct intel_connector *connector;
2464 enum port port = intel_dig_port->port;
2465
9bdbd0b9 2466 connector = intel_connector_alloc();
4a28ae58
PZ		 2467 if (!connector)
2468 return NULL;
2469
2470 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2471 intel_hdmi_init_connector(intel_dig_port, connector);
2472
2473 return connector;
2474}
2475
c39055b0 2476void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2477{
2478 struct intel_digital_port *intel_dig_port;
2479 struct intel_encoder *intel_encoder;
2480 struct drm_encoder *encoder;
ff662124 2481 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2482 int max_lanes;
2483
2484 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2485 switch (port) {
2486 case PORT_A:
2487 max_lanes = 4;
2488 break;
2489 case PORT_E:
2490 max_lanes = 0;
2491 break;
2492 default:
2493 max_lanes = 4;
2494 break;
2495 }
2496 } else {
2497 switch (port) {
2498 case PORT_A:
2499 max_lanes = 2;
2500 break;
2501 case PORT_E:
2502 max_lanes = 2;
2503 break;
2504 default:
2505 max_lanes = 4;
2506 break;
2507 }
2508 }
311a2094
PZ		 2509
2510 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2511 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2512 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2513
2514 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2515 /*
2516 * Lspcon device needs to be driven with DP connector
2517 * with special detection sequence. So make sure DP
2518 * is initialized before lspcon.
2519 */
2520 init_dp = true;
2521 init_lspcon = true;
2522 init_hdmi = false;
2523 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2524 }
2525
311a2094 2526 if (!init_dp && !init_hdmi) {
500ea70d 2527 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2528 port_name(port));
500ea70d 2529 return;
311a2094 2530 }
00c09d70 2531
b14c5679 2532 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2533 if (!intel_dig_port)
2534 return;
2535
00c09d70
PZ		 2536 intel_encoder = &intel_dig_port->base;
2537 encoder = &intel_encoder->base;
2538
c39055b0 2539 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2540 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2541
5bfe2ac0 2542 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2543 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2544 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2545 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2546 intel_encoder->pre_enable = intel_ddi_pre_enable;
2547 intel_encoder->disable = intel_disable_ddi;
2548 intel_encoder->post_disable = intel_ddi_post_disable;
2549 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2550 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2551 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2552 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2553
2554 intel_dig_port->port = port;
bcf53de4
SM		 2555 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2556 (DDI_BUF_PORT_REVERSAL |
2557 DDI_A_4_LANES);
00c09d70 2558
62b69566
ACO		 2559 switch (port) {
2560 case PORT_A:
2561 intel_dig_port->ddi_io_power_domain =
2562 POWER_DOMAIN_PORT_DDI_A_IO;
2563 break;
2564 case PORT_B:
2565 intel_dig_port->ddi_io_power_domain =
2566 POWER_DOMAIN_PORT_DDI_B_IO;
2567 break;
2568 case PORT_C:
2569 intel_dig_port->ddi_io_power_domain =
2570 POWER_DOMAIN_PORT_DDI_C_IO;
2571 break;
2572 case PORT_D:
2573 intel_dig_port->ddi_io_power_domain =
2574 POWER_DOMAIN_PORT_DDI_D_IO;
2575 break;
2576 case PORT_E:
2577 intel_dig_port->ddi_io_power_domain =
2578 POWER_DOMAIN_PORT_DDI_E_IO;
2579 break;
2580 default:
2581 MISSING_CASE(port);
2582 }
2583
6c566dc9
MR		 2584 /*
2585 * Bspec says that DDI_A_4_LANES is the only supported configuration
2586 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2587 * wasn't lit up at boot. Force this bit on in our internal
2588 * configuration so that we use the proper lane count for our
2589 * calculations.
2590 */
cc3f90f0 2591 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2592 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2593 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2594 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2595 max_lanes = 4;
6c566dc9
MR		 2596 }
2597 }
2598
ed8d60f4
MR		 2599 intel_dig_port->max_lanes = max_lanes;
2600
00c09d70 2601 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2602 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2603 intel_encoder->port = port;
f68d697e 2604 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2605 intel_encoder->cloneable = 0;
00c09d70 2606
f68d697e
CW		 2607 if (init_dp) {
2608 if (!intel_ddi_init_dp_connector(intel_dig_port))
2609 goto err;
13cf5504 2610
f68d697e 2611 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2612 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2613 }
21a8e6a4 2614
311a2094
PZ		 2615 /* In theory we don't need the encoder->type check, but leave it just in
2616 * case we have some really bad VBTs... */
f68d697e
CW		 2617 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2618 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2619 goto err;
21a8e6a4 2620 }
f68d697e 2621
ff662124
SS		 2622 if (init_lspcon) {
2623 if (lspcon_init(intel_dig_port))
2624 /* TODO: handle hdmi info frame part */
2625 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2626 port_name(port));
2627 else
2628 /*
2629 * LSPCON init faied, but DP init was success, so
2630 * lets try to drive as DP++ port.
2631 */
2632 DRM_ERROR("LSPCON init failed on port %c\n",
2633 port_name(port));
2634 }
2635
f68d697e
CW		 2636 return;
2637
2638err:
2639 drm_encoder_cleanup(encoder);
2640 kfree(intel_dig_port);
00c09d70 2641}
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