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drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b
VK		 303struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4
RV		 356struct cnl_ddi_buf_trans {
357 u32 dw2_swing_sel;
358 u32 dw7_n_scalar;
359 u32 dw4_cursor_coeff;
360 u32 dw4_post_cursor_2;
361 u32 dw4_post_cursor_1;
362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
da411a48 547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
da411a48
RV		 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
f8896f5d 565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 566 return skl_u_ddi_translations_edp;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 569 return skl_ddi_translations_edp;
f8896f5d
DW		 570 }
571 }
cd1101cb 572
da411a48 573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 577}
578
579static const struct ddi_buf_trans *
78ab0bae 580skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 581{
78ab0bae 582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 584 return skl_y_ddi_translations_hdmi;
f8896f5d 585 } else {
f8896f5d 586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 587 return skl_ddi_translations_hdmi;
f8896f5d 588 }
f8896f5d
DW		 589}
590
8d8bb85e
VS		 591static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
592{
593 int n_hdmi_entries;
594 int hdmi_level;
595 int hdmi_default_entry;
596
597 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
598
cc3f90f0 599 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 600 return hdmi_level;
601
b976dc53 602 if (IS_GEN9_BC(dev_priv)) {
8d8bb85e
VS		 603 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
604 hdmi_default_entry = 8;
605 } else if (IS_BROADWELL(dev_priv)) {
606 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
607 hdmi_default_entry = 7;
608 } else if (IS_HASWELL(dev_priv)) {
609 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
610 hdmi_default_entry = 6;
611 } else {
612 WARN(1, "ddi translation table missing\n");
613 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
614 hdmi_default_entry = 7;
615 }
616
617 /* Choose a good default if VBT is badly populated */
618 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
619 hdmi_level >= n_hdmi_entries)
620 hdmi_level = hdmi_default_entry;
621
622 return hdmi_level;
623}
624
7d1c42e6
VS		 625static const struct ddi_buf_trans *
626intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
627 int *n_entries)
628{
da411a48 629 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
7d1c42e6
VS		 630 return kbl_get_buf_trans_dp(dev_priv, n_entries);
631 } else if (IS_SKYLAKE(dev_priv)) {
632 return skl_get_buf_trans_dp(dev_priv, n_entries);
633 } else if (IS_BROADWELL(dev_priv)) {
634 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
635 return bdw_ddi_translations_dp;
636 } else if (IS_HASWELL(dev_priv)) {
637 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
638 return hsw_ddi_translations_dp;
639 }
640
641 *n_entries = 0;
642 return NULL;
643}
644
645static const struct ddi_buf_trans *
646intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
647 int *n_entries)
648{
da411a48 649 if (IS_GEN9_BC(dev_priv)) {
7d1c42e6
VS		 650 return skl_get_buf_trans_edp(dev_priv, n_entries);
651 } else if (IS_BROADWELL(dev_priv)) {
652 return bdw_get_buf_trans_edp(dev_priv, n_entries);
653 } else if (IS_HASWELL(dev_priv)) {
654 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
655 return hsw_ddi_translations_dp;
656 }
657
658 *n_entries = 0;
659 return NULL;
660}
661
662static const struct ddi_buf_trans *
663intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
664 int *n_entries)
665{
666 if (IS_BROADWELL(dev_priv)) {
667 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
668 return hsw_ddi_translations_fdi;
669 } else if (IS_HASWELL(dev_priv)) {
670 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
671 return hsw_ddi_translations_fdi;
672 }
673
674 *n_entries = 0;
675 return NULL;
676}
677
e58623cb
AR		 678/*
679 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 680 * values in advance. This function programs the correct values for
681 * DP/eDP/FDI use cases.
45244b87 682 */
d7c530b2 683static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 684{
6a7e4f99 685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 686 u32 iboost_bit = 0;
7d1c42e6 687 int i, n_entries;
32bdc400 688 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 689 const struct ddi_buf_trans *ddi_translations;
e58623cb 690
7d1c42e6
VS		 691 switch (encoder->type) {
692 case INTEL_OUTPUT_EDP:
693 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
694 &n_entries);
695 break;
696 case INTEL_OUTPUT_DP:
697 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
698 &n_entries);
699 break;
700 case INTEL_OUTPUT_ANALOG:
701 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
702 &n_entries);
703 break;
704 default:
705 MISSING_CASE(encoder->type);
706 return;
e58623cb
AR		 707 }
708
b976dc53 709 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 710 /* If we're boosting the current, set bit 31 of trans1 */
711 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
712 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
713
714 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
715 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 716 n_entries > 9))
717 n_entries = 9;
300644c7 718 }
45244b87 719
7d1c42e6 720 for (i = 0; i < n_entries; i++) {
9712e688
VS		 721 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
722 ddi_translations[i].trans1 | iboost_bit);
723 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
724 ddi_translations[i].trans2);
45244b87 725 }
32bdc400
VS		 726}
727
728/*
729 * Starting with Haswell, DDI port buffers must be programmed with correct
730 * values in advance. This function programs the correct values for
731 * HDMI/DVI use cases.
732 */
733static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
734{
735 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
736 u32 iboost_bit = 0;
737 int n_hdmi_entries, hdmi_level;
738 enum port port = intel_ddi_get_encoder_port(encoder);
739 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 740
32bdc400
VS		 741 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
742
b976dc53 743 if (IS_GEN9_BC(dev_priv)) {
32bdc400 744 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 745
32bdc400 746 /* If we're boosting the current, set bit 31 of trans1 */
1edaaa2f 747 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
32bdc400
VS		 748 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
749 } else if (IS_BROADWELL(dev_priv)) {
750 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
751 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
752 } else if (IS_HASWELL(dev_priv)) {
753 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
754 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
755 } else {
756 WARN(1, "ddi translation table missing\n");
757 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
758 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
759 }
760
6acab15a 761 /* Entry 9 is for HDMI: */
ed9c77d2 762 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 763 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 764 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 765 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 766}
767
248138b5
PZ		 768static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
769 enum port port)
770{
f0f59a00 771 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 772 int i;
773
3449ca85 774 for (i = 0; i < 16; i++) {
248138b5
PZ		 775 udelay(1);
776 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
777 return;
778 }
779 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
780}
c82e4d26 781
5f88a9c6 782static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a
ACO		 783{
784 switch (pll->id) {
785 case DPLL_ID_WRPLL1:
786 return PORT_CLK_SEL_WRPLL1;
787 case DPLL_ID_WRPLL2:
788 return PORT_CLK_SEL_WRPLL2;
789 case DPLL_ID_SPLL:
790 return PORT_CLK_SEL_SPLL;
791 case DPLL_ID_LCPLL_810:
792 return PORT_CLK_SEL_LCPLL_810;
793 case DPLL_ID_LCPLL_1350:
794 return PORT_CLK_SEL_LCPLL_1350;
795 case DPLL_ID_LCPLL_2700:
796 return PORT_CLK_SEL_LCPLL_2700;
797 default:
798 MISSING_CASE(pll->id);
799 return PORT_CLK_SEL_NONE;
800 }
801}
802
c82e4d26
ED		 803/* Starting with Haswell, different DDI ports can work in FDI mode for
804 * connection to the PCH-located connectors. For this, it is necessary to train
805 * both the DDI port and PCH receiver for the desired DDI buffer settings.
806 *
807 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
808 * please note that when FDI mode is active on DDI E, it shares 2 lines with
809 * DDI A (which is used for eDP)
810 */
811
dc4a1094
ACO		 812void hsw_fdi_link_train(struct intel_crtc *crtc,
813 const struct intel_crtc_state *crtc_state)
c82e4d26 814{
4cbe4b2b 815 struct drm_device *dev = crtc->base.dev;
fac5e23e 816 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 817 struct intel_encoder *encoder;
c856052a 818 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 819
4cbe4b2b 820 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 821 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 822 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 823 }
824
04945641
PZ		 825 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
826 * mode set "sequence for CRT port" document:
827 * - TP1 to TP2 time with the default value
828 * - FDI delay to 90h
8693a824
DL		 829 *
830 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 831 */
eede3b53 832 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 833 FDI_RX_PWRDN_LANE0_VAL(2) |
834 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
835
836 /* Enable the PCH Receiver FDI PLL */
3e68320e 837 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 838 FDI_RX_PLL_ENABLE |
dc4a1094 839 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 840 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
841 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 842 udelay(220);
843
844 /* Switch from Rawclk to PCDclk */
845 rx_ctl_val |= FDI_PCDCLK;
eede3b53 846 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 847
848 /* Configure Port Clock Select */
dc4a1094 849 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 850 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
851 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 852
853 /* Start the training iterating through available voltages and emphasis,
854 * testing each value twice. */
10122051 855 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 856 /* Configure DP_TP_CTL with auto-training */
857 I915_WRITE(DP_TP_CTL(PORT_E),
858 DP_TP_CTL_FDI_AUTOTRAIN |
859 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
860 DP_TP_CTL_LINK_TRAIN_PAT1 |
861 DP_TP_CTL_ENABLE);
862
876a8cdf
DL		 863 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
864 * DDI E does not support port reversal, the functionality is
865 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
866 * port reversal bit */
c82e4d26 867 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 868 DDI_BUF_CTL_ENABLE |
dc4a1094 869 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 870 DDI_BUF_TRANS_SELECT(i / 2));
04945641 871 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 872
873 udelay(600);
874
04945641 875 /* Program PCH FDI Receiver TU */
eede3b53 876 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 877
878 /* Enable PCH FDI Receiver with auto-training */
879 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 880 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
881 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 882
883 /* Wait for FDI receiver lane calibration */
884 udelay(30);
885
886 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 887 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 888 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 889 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
890 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 891
892 /* Wait for FDI auto training time */
893 udelay(5);
c82e4d26
ED		 894
895 temp = I915_READ(DP_TP_STATUS(PORT_E));
896 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 897 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 898 break;
899 }
c82e4d26 900
a308ccb3
VS		 901 /*
902 * Leave things enabled even if we failed to train FDI.
903 * Results in less fireworks from the state checker.
904 */
905 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
906 DRM_ERROR("FDI link training failed!\n");
907 break;
c82e4d26 908 }
04945641 909
5b421c57
VS		 910 rx_ctl_val &= ~FDI_RX_ENABLE;
911 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
912 POSTING_READ(FDI_RX_CTL(PIPE_A));
913
248138b5
PZ		 914 temp = I915_READ(DDI_BUF_CTL(PORT_E));
915 temp &= ~DDI_BUF_CTL_ENABLE;
916 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
917 POSTING_READ(DDI_BUF_CTL(PORT_E));
918
04945641 919 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 920 temp = I915_READ(DP_TP_CTL(PORT_E));
921 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
922 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
923 I915_WRITE(DP_TP_CTL(PORT_E), temp);
924 POSTING_READ(DP_TP_CTL(PORT_E));
925
926 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 927
04945641 928 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 929 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 930 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
931 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 932 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
933 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 934 }
935
a308ccb3
VS		 936 /* Enable normal pixel sending for FDI */
937 I915_WRITE(DP_TP_CTL(PORT_E),
938 DP_TP_CTL_FDI_AUTOTRAIN |
939 DP_TP_CTL_LINK_TRAIN_NORMAL |
940 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
941 DP_TP_CTL_ENABLE);
c82e4d26 942}
0e72a5b5 943
d7c530b2 944static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 945{
946 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
947 struct intel_digital_port *intel_dig_port =
948 enc_to_dig_port(&encoder->base);
949
950 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 951 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 952 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 953}
954
8d9ddbcb 955static struct intel_encoder *
e9ce1a62 956intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 957{
e9ce1a62 958 struct drm_device *dev = crtc->base.dev;
1524e93e 959 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 960 int num_encoders = 0;
961
1524e93e
SS		 962 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
963 ret = encoder;
8d9ddbcb
PZ		 964 num_encoders++;
965 }
966
967 if (num_encoders != 1)
84f44ce7 968 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 969 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 970
971 BUG_ON(ret == NULL);
972 return ret;
973}
974
44a126ba
PZ		 975/* Finds the only possible encoder associated with the given CRTC. */
976struct intel_encoder *
3165c074 977intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 978{
3165c074
ACO		 979 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
980 struct intel_encoder *ret = NULL;
981 struct drm_atomic_state *state;
da3ced29
ACO		 982 struct drm_connector *connector;
983 struct drm_connector_state *connector_state;
d0737e1d 984 int num_encoders = 0;
3165c074 985 int i;
d0737e1d 986
3165c074
ACO		 987 state = crtc_state->base.state;
988
b77c7a90 989 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 990 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 991 continue;
992
da3ced29 993 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 994 num_encoders++;
d0737e1d
ACO		 995 }
996
997 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
998 pipe_name(crtc->pipe));
999
1000 BUG_ON(ret == NULL);
1001 return ret;
1002}
1003
1c0b85c5 1004#define LC_FREQ 2700
1c0b85c5 1005
f0f59a00
VS		 1006static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1007 i915_reg_t reg)
11578553
JB		 1008{
1009 int refclk = LC_FREQ;
1010 int n, p, r;
1011 u32 wrpll;
1012
1013 wrpll = I915_READ(reg);
114fe488
DV		 1014 switch (wrpll & WRPLL_PLL_REF_MASK) {
1015 case WRPLL_PLL_SSC:
1016 case WRPLL_PLL_NON_SSC:
11578553
JB		 1017 /*
1018 * We could calculate spread here, but our checking
1019 * code only cares about 5% accuracy, and spread is a max of
1020 * 0.5% downspread.
1021 */
1022 refclk = 135;
1023 break;
114fe488 1024 case WRPLL_PLL_LCPLL:
11578553
JB		 1025 refclk = LC_FREQ;
1026 break;
1027 default:
1028 WARN(1, "bad wrpll refclk\n");
1029 return 0;
1030 }
1031
1032 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1033 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1034 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1035
20f0ec16
JB		 1036 /* Convert to KHz, p & r have a fixed point portion */
1037 return (refclk * n * 100) / (p * r);
11578553
JB		 1038}
1039
540e732c
S		 1040static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1041 uint32_t dpll)
1042{
f0f59a00 1043 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1044 uint32_t cfgcr1_val, cfgcr2_val;
1045 uint32_t p0, p1, p2, dco_freq;
1046
923c1241
VS		 1047 cfgcr1_reg = DPLL_CFGCR1(dpll);
1048 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1049
1050 cfgcr1_val = I915_READ(cfgcr1_reg);
1051 cfgcr2_val = I915_READ(cfgcr2_reg);
1052
1053 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1054 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1055
1056 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1057 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1058 else
1059 p1 = 1;
1060
1061
1062 switch (p0) {
1063 case DPLL_CFGCR2_PDIV_1:
1064 p0 = 1;
1065 break;
1066 case DPLL_CFGCR2_PDIV_2:
1067 p0 = 2;
1068 break;
1069 case DPLL_CFGCR2_PDIV_3:
1070 p0 = 3;
1071 break;
1072 case DPLL_CFGCR2_PDIV_7:
1073 p0 = 7;
1074 break;
1075 }
1076
1077 switch (p2) {
1078 case DPLL_CFGCR2_KDIV_5:
1079 p2 = 5;
1080 break;
1081 case DPLL_CFGCR2_KDIV_2:
1082 p2 = 2;
1083 break;
1084 case DPLL_CFGCR2_KDIV_3:
1085 p2 = 3;
1086 break;
1087 case DPLL_CFGCR2_KDIV_1:
1088 p2 = 1;
1089 break;
1090 }
1091
1092 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1093
1094 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1095 1000) / 0x8000;
1096
1097 return dco_freq / (p0 * p1 * p2 * 5);
1098}
1099
a9701a89
RV		 1100static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1101 uint32_t pll_id)
1102{
1103 uint32_t cfgcr0, cfgcr1;
1104 uint32_t p0, p1, p2, dco_freq, ref_clock;
1105
1106 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1107 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1108
1109 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1110 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1111
1112 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1113 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1114 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1115 else
1116 p1 = 1;
1117
1118
1119 switch (p0) {
1120 case DPLL_CFGCR1_PDIV_2:
1121 p0 = 2;
1122 break;
1123 case DPLL_CFGCR1_PDIV_3:
1124 p0 = 3;
1125 break;
1126 case DPLL_CFGCR1_PDIV_5:
1127 p0 = 5;
1128 break;
1129 case DPLL_CFGCR1_PDIV_7:
1130 p0 = 7;
1131 break;
1132 }
1133
1134 switch (p2) {
1135 case DPLL_CFGCR1_KDIV_1:
1136 p2 = 1;
1137 break;
1138 case DPLL_CFGCR1_KDIV_2:
1139 p2 = 2;
1140 break;
1141 case DPLL_CFGCR1_KDIV_4:
1142 p2 = 4;
1143 break;
1144 }
1145
1146 ref_clock = dev_priv->cdclk.hw.ref;
1147
1148 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1149
1150 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1151 DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
1152
1153 return dco_freq / (p0 * p1 * p2 * 5);
1154}
1155
398a017e
VS		 1156static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1157{
1158 int dotclock;
1159
1160 if (pipe_config->has_pch_encoder)
1161 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1162 &pipe_config->fdi_m_n);
37a5650b 1163 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1164 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1165 &pipe_config->dp_m_n);
1166 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1167 dotclock = pipe_config->port_clock * 2 / 3;
1168 else
1169 dotclock = pipe_config->port_clock;
1170
b22ca995
SS		 1171 if (pipe_config->ycbcr420)
1172 dotclock *= 2;
1173
398a017e
VS		 1174 if (pipe_config->pixel_multiplier)
1175 dotclock /= pipe_config->pixel_multiplier;
1176
1177 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1178}
540e732c 1179
a9701a89
RV		 1180static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1181 struct intel_crtc_state *pipe_config)
1182{
1183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1184 int link_clock = 0;
1185 uint32_t cfgcr0, pll_id;
1186
1187 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1188
1189 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1190
1191 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1192 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1193 } else {
1194 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1195
1196 switch (link_clock) {
1197 case DPLL_CFGCR0_LINK_RATE_810:
1198 link_clock = 81000;
1199 break;
1200 case DPLL_CFGCR0_LINK_RATE_1080:
1201 link_clock = 108000;
1202 break;
1203 case DPLL_CFGCR0_LINK_RATE_1350:
1204 link_clock = 135000;
1205 break;
1206 case DPLL_CFGCR0_LINK_RATE_1620:
1207 link_clock = 162000;
1208 break;
1209 case DPLL_CFGCR0_LINK_RATE_2160:
1210 link_clock = 216000;
1211 break;
1212 case DPLL_CFGCR0_LINK_RATE_2700:
1213 link_clock = 270000;
1214 break;
1215 case DPLL_CFGCR0_LINK_RATE_3240:
1216 link_clock = 324000;
1217 break;
1218 case DPLL_CFGCR0_LINK_RATE_4050:
1219 link_clock = 405000;
1220 break;
1221 default:
1222 WARN(1, "Unsupported link rate\n");
1223 break;
1224 }
1225 link_clock *= 2;
1226 }
1227
1228 pipe_config->port_clock = link_clock;
1229
1230 ddi_dotclock_get(pipe_config);
1231}
1232
540e732c 1233static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1234 struct intel_crtc_state *pipe_config)
540e732c 1235{
fac5e23e 1236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1237 int link_clock = 0;
1238 uint32_t dpll_ctl1, dpll;
1239
c856052a 1240 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1241
1242 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1243
1244 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1245 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1246 } else {
71cd8423
DL		 1247 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1248 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1249
1250 switch (link_clock) {
71cd8423 1251 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1252 link_clock = 81000;
1253 break;
71cd8423 1254 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1255 link_clock = 108000;
1256 break;
71cd8423 1257 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1258 link_clock = 135000;
1259 break;
71cd8423 1260 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1261 link_clock = 162000;
1262 break;
71cd8423 1263 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1264 link_clock = 216000;
1265 break;
71cd8423 1266 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1267 link_clock = 270000;
1268 break;
1269 default:
1270 WARN(1, "Unsupported link rate\n");
1271 break;
1272 }
1273 link_clock *= 2;
1274 }
1275
1276 pipe_config->port_clock = link_clock;
1277
398a017e 1278 ddi_dotclock_get(pipe_config);
540e732c
S		 1279}
1280
3d51278a 1281static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1282 struct intel_crtc_state *pipe_config)
11578553 1283{
fac5e23e 1284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1285 int link_clock = 0;
1286 u32 val, pll;
1287
c856052a 1288 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1289 switch (val & PORT_CLK_SEL_MASK) {
1290 case PORT_CLK_SEL_LCPLL_810:
1291 link_clock = 81000;
1292 break;
1293 case PORT_CLK_SEL_LCPLL_1350:
1294 link_clock = 135000;
1295 break;
1296 case PORT_CLK_SEL_LCPLL_2700:
1297 link_clock = 270000;
1298 break;
1299 case PORT_CLK_SEL_WRPLL1:
01403de3 1300 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1301 break;
1302 case PORT_CLK_SEL_WRPLL2:
01403de3 1303 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1304 break;
1305 case PORT_CLK_SEL_SPLL:
1306 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1307 if (pll == SPLL_PLL_FREQ_810MHz)
1308 link_clock = 81000;
1309 else if (pll == SPLL_PLL_FREQ_1350MHz)
1310 link_clock = 135000;
1311 else if (pll == SPLL_PLL_FREQ_2700MHz)
1312 link_clock = 270000;
1313 else {
1314 WARN(1, "bad spll freq\n");
1315 return;
1316 }
1317 break;
1318 default:
1319 WARN(1, "bad port clock sel\n");
1320 return;
1321 }
1322
1323 pipe_config->port_clock = link_clock * 2;
1324
398a017e 1325 ddi_dotclock_get(pipe_config);
11578553
JB		 1326}
1327
977bb38d
S		 1328static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1329 enum intel_dpll_id dpll)
1330{
aa610dcb
ID		 1331 struct intel_shared_dpll *pll;
1332 struct intel_dpll_hw_state *state;
9e2c8475 1333 struct dpll clock;
aa610dcb
ID		 1334
1335 /* For DDI ports we always use a shared PLL. */
1336 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1337 return 0;
1338
1339 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1340 state = &pll->state.hw_state;
aa610dcb
ID		 1341
1342 clock.m1 = 2;
1343 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1344 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1345 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1346 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1347 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1348 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1349
1350 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1351}
1352
1353static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1354 struct intel_crtc_state *pipe_config)
1355{
fac5e23e 1356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1357 enum port port = intel_ddi_get_encoder_port(encoder);
1358 uint32_t dpll = port;
1359
398a017e 1360 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1361
398a017e 1362 ddi_dotclock_get(pipe_config);
977bb38d
S		 1363}
1364
3d51278a 1365void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1366 struct intel_crtc_state *pipe_config)
3d51278a 1367{
0853723b 1368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1369
0853723b 1370 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1371 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1372 else if (IS_GEN9_BC(dev_priv))
22606a18 1373 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1374 else if (IS_GEN9_LP(dev_priv))
977bb38d 1375 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1376 else if (IS_CANNONLAKE(dev_priv))
1377 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1378}
1379
3dc38eea 1380void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1381{
3dc38eea 1382 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1384 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1385 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1386 int type = encoder->type;
dae84799
PZ		 1387 uint32_t temp;
1388
cca0502b 1389 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1390 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1391
c9809791 1392 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1393 switch (crtc_state->pipe_bpp) {
dae84799 1394 case 18:
c9809791 1395 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1396 break;
1397 case 24:
c9809791 1398 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1399 break;
1400 case 30:
c9809791 1401 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1402 break;
1403 case 36:
c9809791 1404 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1405 break;
1406 default:
4e53c2e0 1407 BUG();
dae84799 1408 }
c9809791 1409 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1410 }
1411}
1412
3dc38eea
ACO		 1413void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1414 bool state)
0e32b39c 1415{
3dc38eea 1416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1417 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1418 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1419 uint32_t temp;
1420 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1421 if (state == true)
1422 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1423 else
1424 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1425 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1426}
1427
3dc38eea 1428void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1429{
3dc38eea 1430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1431 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1433 enum pipe pipe = crtc->pipe;
3dc38eea 1434 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1435 enum port port = intel_ddi_get_encoder_port(encoder);
1436 int type = encoder->type;
8d9ddbcb
PZ		 1437 uint32_t temp;
1438
ad80a810
PZ		 1439 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1440 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1441 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1442
3dc38eea 1443 switch (crtc_state->pipe_bpp) {
dfcef252 1444 case 18:
ad80a810 1445 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1446 break;
1447 case 24:
ad80a810 1448 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1449 break;
1450 case 30:
ad80a810 1451 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1452 break;
1453 case 36:
ad80a810 1454 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1455 break;
1456 default:
4e53c2e0 1457 BUG();
dfcef252 1458 }
72662e10 1459
3dc38eea 1460 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1461 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1462 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1463 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1464
e6f0bfc4
PZ		 1465 if (cpu_transcoder == TRANSCODER_EDP) {
1466 switch (pipe) {
1467 case PIPE_A:
c7670b10
PZ		 1468 /* On Haswell, can only use the always-on power well for
1469 * eDP when not using the panel fitter, and when not
1470 * using motion blur mitigation (which we don't
1471 * support). */
772c2a51 1472 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1473 (crtc_state->pch_pfit.enabled ||
1474 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1475 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1476 else
1477 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1478 break;
1479 case PIPE_B:
1480 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1481 break;
1482 case PIPE_C:
1483 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1484 break;
1485 default:
1486 BUG();
1487 break;
1488 }
1489 }
1490
7739c33b 1491 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1492 if (crtc_state->has_hdmi_sink)
ad80a810 1493 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1494 else
ad80a810 1495 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1496
1497 if (crtc_state->hdmi_scrambling)
1498 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1499 if (crtc_state->hdmi_high_tmds_clock_ratio)
1500 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1501 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1502 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1503 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1504 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1505 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1506 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1507 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1508 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1509 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1510 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1511 } else {
84f44ce7 1512 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1513 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1514 }
1515
ad80a810 1516 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1517}
72662e10 1518
ad80a810
PZ		 1519void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1520 enum transcoder cpu_transcoder)
8d9ddbcb 1521{
f0f59a00 1522 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1523 uint32_t val = I915_READ(reg);
1524
0e32b39c 1525 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1526 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1527 I915_WRITE(reg, val);
72662e10
ED		 1528}
1529
bcbc889b
PZ		 1530bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1531{
1532 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1533 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1534 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1535 int type = intel_connector->base.connector_type;
1524e93e 1536 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1537 enum pipe pipe = 0;
1538 enum transcoder cpu_transcoder;
1539 uint32_t tmp;
e27daab4 1540 bool ret;
bcbc889b 1541
79f255a0 1542 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1543 encoder->power_domain))
882244a3
PZ		 1544 return false;
1545
1524e93e 1546 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1547 ret = false;
1548 goto out;
1549 }
bcbc889b
PZ		 1550
1551 if (port == PORT_A)
1552 cpu_transcoder = TRANSCODER_EDP;
1553 else
1a240d4d 1554 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1555
1556 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1557
1558 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1559 case TRANS_DDI_MODE_SELECT_HDMI:
1560 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1561 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1562 break;
bcbc889b
PZ		 1563
1564 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1565 ret = type == DRM_MODE_CONNECTOR_eDP ||
1566 type == DRM_MODE_CONNECTOR_DisplayPort;
1567 break;
1568
0e32b39c
DA		 1569 case TRANS_DDI_MODE_SELECT_DP_MST:
1570 /* if the transcoder is in MST state then
1571 * connector isn't connected */
e27daab4
ID		 1572 ret = false;
1573 break;
bcbc889b
PZ		 1574
1575 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1576 ret = type == DRM_MODE_CONNECTOR_VGA;
1577 break;
bcbc889b
PZ		 1578
1579 default:
e27daab4
ID		 1580 ret = false;
1581 break;
bcbc889b 1582 }
e27daab4
ID		 1583
1584out:
1524e93e 1585 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1586
1587 return ret;
bcbc889b
PZ		 1588}
1589
85234cdc
DV		 1590bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1591 enum pipe *pipe)
1592{
1593 struct drm_device *dev = encoder->base.dev;
fac5e23e 1594 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1595 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1596 u32 tmp;
1597 int i;
e27daab4 1598 bool ret;
85234cdc 1599
79f255a0
ACO		 1600 if (!intel_display_power_get_if_enabled(dev_priv,
1601 encoder->power_domain))
6d129bea
ID		 1602 return false;
1603
e27daab4
ID		 1604 ret = false;
1605
fe43d3f5 1606 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1607
1608 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1609 goto out;
85234cdc 1610
ad80a810
PZ		 1611 if (port == PORT_A) {
1612 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1613
ad80a810
PZ		 1614 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1615 case TRANS_DDI_EDP_INPUT_A_ON:
1616 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1617 *pipe = PIPE_A;
1618 break;
1619 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1620 *pipe = PIPE_B;
1621 break;
1622 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1623 *pipe = PIPE_C;
1624 break;
1625 }
1626
e27daab4 1627 ret = true;
ad80a810 1628
e27daab4
ID		 1629 goto out;
1630 }
0e32b39c 1631
e27daab4
ID		 1632 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1633 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1634
1635 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1636 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1637 TRANS_DDI_MODE_SELECT_DP_MST)
1638 goto out;
1639
1640 *pipe = i;
1641 ret = true;
1642
1643 goto out;
85234cdc
DV		 1644 }
1645 }
1646
84f44ce7 1647 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1648
e27daab4 1649out:
cc3f90f0 1650 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0
ID		 1651 tmp = I915_READ(BXT_PHY_CTL(port));
1652 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1653 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1654 DRM_ERROR("Port %c enabled but PHY powered down? "
1655 "(PHY_CTL %08x)\n", port_name(port), tmp);
1656 }
1657
79f255a0 1658 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1659
1660 return ret;
85234cdc
DV		 1661}
1662
62b69566
ACO		 1663static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1664{
1665 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1666 enum pipe pipe;
1667
1668 if (intel_ddi_get_hw_state(encoder, &pipe))
1669 return BIT_ULL(dig_port->ddi_io_power_domain);
1670
1671 return 0;
1672}
1673
3dc38eea 1674void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1675{
3dc38eea 1676 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1677 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1678 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1679 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1680 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1681
bb523fc0
PZ		 1682 if (cpu_transcoder != TRANSCODER_EDP)
1683 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1684 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1685}
1686
3dc38eea 1687void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1688{
3dc38eea
ACO		 1689 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1690 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1691
bb523fc0
PZ		 1692 if (cpu_transcoder != TRANSCODER_EDP)
1693 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1694 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1695}
1696
a7d8dbc0
VS		 1697static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1698 enum port port, uint8_t iboost)
f8896f5d 1699{
a7d8dbc0
VS		 1700 u32 tmp;
1701
1702 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1703 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1704 if (iboost)
1705 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1706 else
1707 tmp |= BALANCE_LEG_DISABLE(port);
1708 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1709}
1710
1711static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1712{
1713 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1714 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1715 enum port port = intel_dig_port->port;
1716 int type = encoder->type;
f8896f5d
DW		 1717 const struct ddi_buf_trans *ddi_translations;
1718 uint8_t iboost;
75067dde 1719 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1720 int n_entries;
f8896f5d 1721
75067dde
AK		 1722 /* VBT may override standard boost values */
1723 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1724 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1725
cca0502b 1726 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1727 if (dp_iboost) {
1728 iboost = dp_iboost;
1729 } else {
da411a48 1730 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 1731 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1732 &n_entries);
1733 else
1734 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1735 &n_entries);
e4d4c05b 1736 iboost = ddi_translations[level].i_boost;
75067dde 1737 }
f8896f5d 1738 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1739 if (dp_iboost) {
1740 iboost = dp_iboost;
1741 } else {
78ab0bae 1742 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1743
1744 if (WARN_ON(port != PORT_A &&
1745 port != PORT_E && n_entries > 9))
1746 n_entries = 9;
1747
e4d4c05b 1748 iboost = ddi_translations[level].i_boost;
75067dde 1749 }
f8896f5d 1750 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1751 if (hdmi_iboost) {
1752 iboost = hdmi_iboost;
1753 } else {
78ab0bae 1754 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1755 iboost = ddi_translations[level].i_boost;
75067dde 1756 }
f8896f5d
DW		 1757 } else {
1758 return;
1759 }
1760
1761 /* Make sure that the requested I_boost is valid */
1762 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1763 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1764 return;
1765 }
1766
a7d8dbc0 1767 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1768
a7d8dbc0
VS		 1769 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1770 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1771}
1772
78ab0bae
VS		 1773static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1774 u32 level, enum port port, int type)
96fb9f9b 1775{
96fb9f9b
VK		 1776 const struct bxt_ddi_buf_trans *ddi_translations;
1777 u32 n_entries, i;
96fb9f9b 1778
06411f08 1779 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1780 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1781 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1782 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1783 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1784 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1785 ddi_translations = bxt_ddi_translations_dp;
1786 } else if (type == INTEL_OUTPUT_HDMI) {
1787 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1788 ddi_translations = bxt_ddi_translations_hdmi;
1789 } else {
1790 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1791 type);
1792 return;
1793 }
1794
1795 /* Check if default value has to be used */
1796 if (level >= n_entries ||
1797 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1798 for (i = 0; i < n_entries; i++) {
1799 if (ddi_translations[i].default_index) {
1800 level = i;
1801 break;
1802 }
1803 }
1804 }
1805
b6e08203
ACO		 1806 bxt_ddi_phy_set_signal_level(dev_priv, port,
1807 ddi_translations[level].margin,
1808 ddi_translations[level].scale,
1809 ddi_translations[level].enable,
1810 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1811}
1812
ffe5111e
VS		 1813u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1814{
1815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1816 int n_entries;
1817
1818 if (encoder->type == INTEL_OUTPUT_EDP)
1819 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1820 else
1821 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1822
1823 if (WARN_ON(n_entries < 1))
1824 n_entries = 1;
1825 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1826 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1827
1828 return index_to_dp_signal_levels[n_entries - 1] &
1829 DP_TRAIN_VOLTAGE_SWING_MASK;
1830}
1831
cf54ca8b
RV		 1832static const struct cnl_ddi_buf_trans *
1833cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1834 u32 voltage, int *n_entries)
1835{
1836 if (voltage == VOLTAGE_INFO_0_85V) {
1837 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1838 return cnl_ddi_translations_hdmi_0_85V;
1839 } else if (voltage == VOLTAGE_INFO_0_95V) {
1840 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1841 return cnl_ddi_translations_hdmi_0_95V;
1842 } else if (voltage == VOLTAGE_INFO_1_05V) {
1843 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1844 return cnl_ddi_translations_hdmi_1_05V;
1845 }
1846 return NULL;
1847}
1848
1849static const struct cnl_ddi_buf_trans *
1850cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1851 u32 voltage, int *n_entries)
1852{
1853 if (voltage == VOLTAGE_INFO_0_85V) {
1854 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1855 return cnl_ddi_translations_dp_0_85V;
1856 } else if (voltage == VOLTAGE_INFO_0_95V) {
1857 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1858 return cnl_ddi_translations_dp_0_95V;
1859 } else if (voltage == VOLTAGE_INFO_1_05V) {
1860 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1861 return cnl_ddi_translations_dp_1_05V;
1862 }
1863 return NULL;
1864}
1865
1866static const struct cnl_ddi_buf_trans *
1867cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1868 u32 voltage, int *n_entries)
1869{
1870 if (dev_priv->vbt.edp.low_vswing) {
1871 if (voltage == VOLTAGE_INFO_0_85V) {
1872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
50946c89 1873 return cnl_ddi_translations_edp_0_85V;
cf54ca8b
RV		 1874 } else if (voltage == VOLTAGE_INFO_0_95V) {
1875 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1876 return cnl_ddi_translations_edp_0_95V;
1877 } else if (voltage == VOLTAGE_INFO_1_05V) {
1878 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1879 return cnl_ddi_translations_edp_1_05V;
1880 }
1881 return NULL;
1882 } else {
1883 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1884 }
1885}
1886
1887static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1888 u32 level, enum port port, int type)
1889{
1890 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1891 u32 n_entries, val, voltage;
1892 int ln;
1893
1894 /*
1895 * Values for each port type are listed in
1896 * voltage swing programming tables.
1897 * Vccio voltage found in PORT_COMP_DW3.
1898 */
1899 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1900
1901 if (type == INTEL_OUTPUT_HDMI) {
1902 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1903 voltage, &n_entries);
1904 } else if (type == INTEL_OUTPUT_DP) {
1905 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1906 voltage, &n_entries);
1907 } else if (type == INTEL_OUTPUT_EDP) {
1908 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1909 voltage, &n_entries);
1910 }
1911
1912 if (ddi_translations == NULL) {
1913 MISSING_CASE(voltage);
1914 return;
1915 }
1916
1917 if (level >= n_entries) {
1918 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1919 level = n_entries - 1;
1920 }
1921
1922 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1923 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1924 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1925 val |= SCALING_MODE_SEL(2);
1926 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1927
1928 /* Program PORT_TX_DW2 */
1929 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1930 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1931 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1932 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1933 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1934 /* Rcomp scalar is fixed as 0x98 for every table entry */
1935 val |= RCOMP_SCALAR(0x98);
1936 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1937
1938 /* Program PORT_TX_DW4 */
1939 /* We cannot write to GRP. It would overrite individual loadgen */
1940 for (ln = 0; ln < 4; ln++) {
1941 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1942 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1943 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1944 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1945 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1946 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1947 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1948 }
1949
1950 /* Program PORT_TX_DW5 */
1951 /* All DW5 values are fixed for every table entry */
1952 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1953 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1954 val |= RTERM_SELECT(6);
1955 val |= TAP3_DISABLE;
1956 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1957
1958 /* Program PORT_TX_DW7 */
1959 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1960 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1961 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1962 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1963}
1964
0091abc3 1965static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1966{
0091abc3
CT		 1967 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1968 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1969 enum port port = intel_ddi_get_encoder_port(encoder);
1970 int type = encoder->type;
1971 int width = 0;
1972 int rate = 0;
cf54ca8b 1973 u32 val;
0091abc3
CT		 1974 int ln = 0;
1975
1976 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1977 width = intel_dp->lane_count;
1978 rate = intel_dp->link_rate;
61f3e770 1979 } else if (type == INTEL_OUTPUT_HDMI) {
0091abc3
CT		 1980 width = 4;
1981 /* Rate is always < than 6GHz for HDMI */
61f3e770
RV		 1982 } else {
1983 MISSING_CASE(type);
1984 return;
0091abc3 1985 }
cf54ca8b
RV		 1986
1987 /*
1988 * 1. If port type is eDP or DP,
1989 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1990 * else clear to 0b.
1991 */
1992 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1993 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1994 val |= COMMON_KEEPER_EN;
1995 else
1996 val &= ~COMMON_KEEPER_EN;
1997 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1998
1999 /* 2. Program loadgen select */
2000 /*
0091abc3
CT		 2001 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2002 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2003 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2004 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2005 */
0091abc3
CT		 2006 for (ln = 0; ln <= 3; ln++) {
2007 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2008 val &= ~LOADGEN_SELECT;
2009
a8e45a1c
NM		 2010 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2011 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2012 val |= LOADGEN_SELECT;
2013 }
2014 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2015 }
cf54ca8b
RV		 2016
2017 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2018 val = I915_READ(CNL_PORT_CL1CM_DW5);
2019 val |= SUS_CLOCK_CONFIG;
2020 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2021
2022 /* 4. Clear training enable to change swing values */
2023 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2024 val &= ~TX_TRAINING_EN;
2025 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2026
2027 /* 5. Program swing and de-emphasis */
2028 cnl_ddi_vswing_program(dev_priv, level, port, type);
2029
2030 /* 6. Set training enable to trigger update */
2031 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2032 val |= TX_TRAINING_EN;
2033 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2034}
2035
f8896f5d
DW		 2036static uint32_t translate_signal_level(int signal_levels)
2037{
97eeb872 2038 int i;
f8896f5d 2039
97eeb872
VS		 2040 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2041 if (index_to_dp_signal_levels[i] == signal_levels)
2042 return i;
f8896f5d
DW		 2043 }
2044
97eeb872
VS		 2045 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2046 signal_levels);
2047
2048 return 0;
f8896f5d
DW		 2049}
2050
1b6e2fd2
RV		 2051static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2052{
2053 uint8_t train_set = intel_dp->train_set[0];
2054 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2055 DP_TRAIN_PRE_EMPHASIS_MASK);
2056
2057 return translate_signal_level(signal_levels);
2058}
2059
d509af6c 2060u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2061{
2062 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2063 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2064 struct intel_encoder *encoder = &dport->base;
f8896f5d 2065 enum port port = dport->port;
d509af6c
RV		 2066 u32 level = intel_ddi_dp_level(intel_dp);
2067
2068 if (IS_CANNONLAKE(dev_priv))
2069 cnl_ddi_vswing_sequence(encoder, level);
2070 else
2071 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2072
2073 return 0;
2074}
2075
2076uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2077{
2078 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2079 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2080 struct intel_encoder *encoder = &dport->base;
1b6e2fd2 2081 uint32_t level = intel_ddi_dp_level(intel_dp);
f8896f5d 2082
b976dc53 2083 if (IS_GEN9_BC(dev_priv))
d509af6c
RV		 2084 skl_ddi_set_iboost(encoder, level);
2085
f8896f5d
DW		 2086 return DDI_BUF_TRANS_SELECT(level);
2087}
2088
d7c530b2 2089static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2090 const struct intel_shared_dpll *pll)
6441ab5f 2091{
e404ba8d
VS		 2092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2093 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 2094 uint32_t val;
6441ab5f 2095
c856052a
ACO		 2096 if (WARN_ON(!pll))
2097 return;
2098
555e38d2
RV		 2099 if (IS_CANNONLAKE(dev_priv)) {
2100 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2101 val = I915_READ(DPCLKA_CFGCR0);
2102 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2103 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2104
555e38d2
RV		 2105 /*
2106 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2107 * This step and the step before must be done with separate
2108 * register writes.
2109 */
2110 val = I915_READ(DPCLKA_CFGCR0);
2111 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2112 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2113 I915_WRITE(DPCLKA_CFGCR0, val);
2114 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2115 /* DDI -> PLL mapping */
efa80add
S		 2116 val = I915_READ(DPLL_CTRL2);
2117
2118 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2119 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2120 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2121 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2122
2123 I915_WRITE(DPLL_CTRL2, val);
5416d871 2124
e404ba8d 2125 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 2126 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2127 }
e404ba8d
VS		 2128}
2129
ba88d153
MN		 2130static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2131 int link_rate, uint32_t lane_count,
2132 struct intel_shared_dpll *pll,
2133 bool link_mst)
e404ba8d 2134{
ba88d153
MN		 2135 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2136 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2137 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2138 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
381f9570 2139 uint32_t level = intel_ddi_dp_level(intel_dp);
b2ccb822 2140
e081c846
ACO		 2141 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2142
ba88d153
MN		 2143 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2144 link_mst);
2145 if (encoder->type == INTEL_OUTPUT_EDP)
e404ba8d 2146 intel_edp_panel_on(intel_dp);
32bdc400 2147
ba88d153 2148 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2149
2150 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2151
381f9570
RV		 2152 if (IS_CANNONLAKE(dev_priv))
2153 cnl_ddi_vswing_sequence(encoder, level);
2154 else if (IS_GEN9_LP(dev_priv))
2155 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2156 else
2f7460a7
RV		 2157 intel_prepare_dp_ddi_buffers(encoder);
2158
ba88d153
MN		 2159 intel_ddi_init_dp_buf_reg(encoder);
2160 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2161 intel_dp_start_link_train(intel_dp);
2162 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2163 intel_dp_stop_link_train(intel_dp);
2164}
901c2daf 2165
ba88d153 2166static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
b47ef0f7 2167 bool has_infoframe,
ac240288
ML		 2168 const struct intel_crtc_state *crtc_state,
2169 const struct drm_connector_state *conn_state,
5f88a9c6 2170 const struct intel_shared_dpll *pll)
ba88d153 2171{
f99be1b3
VS		 2172 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2173 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ba88d153
MN		 2175 enum port port = intel_ddi_get_encoder_port(encoder);
2176 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2177 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2178
ba88d153
MN		 2179 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2180 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2181
2182 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2183
2f7460a7
RV		 2184 if (IS_CANNONLAKE(dev_priv))
2185 cnl_ddi_vswing_sequence(encoder, level);
cc3f90f0 2186 else if (IS_GEN9_LP(dev_priv))
ba88d153
MN		 2187 bxt_ddi_vswing_sequence(dev_priv, level, port,
2188 INTEL_OUTPUT_HDMI);
2f7460a7
RV		 2189 else
2190 intel_prepare_hdmi_ddi_buffers(encoder);
2191
2192 if (IS_GEN9_BC(dev_priv))
2193 skl_ddi_set_iboost(encoder, level);
8d8bb85e 2194
f99be1b3
VS		 2195 intel_dig_port->set_infoframes(&encoder->base,
2196 has_infoframe,
2197 crtc_state, conn_state);
ba88d153 2198}
32bdc400 2199
1524e93e 2200static void intel_ddi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2201 const struct intel_crtc_state *pipe_config,
2202 const struct drm_connector_state *conn_state)
ba88d153 2203{
1524e93e 2204 int type = encoder->type;
30cf6db8 2205
ba88d153 2206 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1524e93e 2207 intel_ddi_pre_enable_dp(encoder,
3dc38eea
ACO		 2208 pipe_config->port_clock,
2209 pipe_config->lane_count,
2210 pipe_config->shared_dpll,
2211 intel_crtc_has_type(pipe_config,
ba88d153
MN		 2212 INTEL_OUTPUT_DP_MST));
2213 }
2214 if (type == INTEL_OUTPUT_HDMI) {
1524e93e 2215 intel_ddi_pre_enable_hdmi(encoder,
b47ef0f7 2216 pipe_config->has_infoframe,
ac240288 2217 pipe_config, conn_state,
3dc38eea 2218 pipe_config->shared_dpll);
c19b0669 2219 }
6441ab5f
PZ		 2220}
2221
fd6bbda9 2222static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2223 const struct intel_crtc_state *old_crtc_state,
2224 const struct drm_connector_state *old_conn_state)
6441ab5f
PZ		 2225{
2226 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2227 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6441ab5f 2228 enum port port = intel_ddi_get_encoder_port(intel_encoder);
62b69566 2229 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
82a4d9c0 2230 int type = intel_encoder->type;
2886e93f 2231 uint32_t val;
a836bdf9 2232 bool wait = false;
2886e93f 2233
fd6bbda9
ML		 2234 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2235
7618138d 2236 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
c5f93fcf
VS		 2237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2238
7618138d
ID		 2239 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2240 }
2241
2886e93f
PZ		 2242 val = I915_READ(DDI_BUF_CTL(port));
2243 if (val & DDI_BUF_CTL_ENABLE) {
2244 val &= ~DDI_BUF_CTL_ENABLE;
2245 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2246 wait = true;
2886e93f 2247 }
6441ab5f 2248
a836bdf9
PZ		 2249 val = I915_READ(DP_TP_CTL(port));
2250 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2251 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2252 I915_WRITE(DP_TP_CTL(port), val);
2253
2254 if (wait)
2255 intel_wait_ddi_buf_idle(dev_priv, port);
2256
c5f93fcf 2257 if (type == INTEL_OUTPUT_HDMI) {
f99be1b3
VS		 2258 dig_port->set_infoframes(encoder, false,
2259 old_crtc_state, old_conn_state);
c5f93fcf
VS		 2260 }
2261
2262 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2263 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2264
24f3e092 2265 intel_edp_panel_vdd_on(intel_dp);
4be73780 2266 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2267 }
2268
62b69566
ACO		 2269 if (dig_port)
2270 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2271
555e38d2
RV		 2272 if (IS_CANNONLAKE(dev_priv))
2273 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2274 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2275 else if (IS_GEN9_BC(dev_priv))
efa80add
S		 2276 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2277 DPLL_CTRL2_DDI_CLK_OFF(port)));
66478475 2278 else if (INTEL_GEN(dev_priv) < 9)
efa80add 2279 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 2280
2281 if (type == INTEL_OUTPUT_HDMI) {
2282 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2283
2284 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2285 }
6441ab5f
PZ		 2286}
2287
1524e93e 2288void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2289 const struct intel_crtc_state *old_crtc_state,
2290 const struct drm_connector_state *old_conn_state)
b7076546 2291{
1524e93e 2292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2293 uint32_t val;
2294
2295 /*
2296 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2297 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2298 * step 13 is the correct place for it. Step 18 is where it was
2299 * originally before the BUN.
2300 */
2301 val = I915_READ(FDI_RX_CTL(PIPE_A));
2302 val &= ~FDI_RX_ENABLE;
2303 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2304
1524e93e 2305 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
b7076546
ML		 2306
2307 val = I915_READ(FDI_RX_MISC(PIPE_A));
2308 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2309 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2310 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2311
2312 val = I915_READ(FDI_RX_CTL(PIPE_A));
2313 val &= ~FDI_PCDCLK;
2314 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2315
2316 val = I915_READ(FDI_RX_CTL(PIPE_A));
2317 val &= ~FDI_RX_PLL_ENABLE;
2318 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2319}
2320
fd6bbda9 2321static void intel_enable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2322 const struct intel_crtc_state *pipe_config,
2323 const struct drm_connector_state *conn_state)
72662e10 2324{
6547fef8 2325 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2326 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6547fef8
PZ		 2327 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2328 int type = intel_encoder->type;
72662e10 2329
6547fef8 2330 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2331 struct intel_digital_port *intel_dig_port =
2332 enc_to_dig_port(encoder);
15953637
SS		 2333 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2334 bool scrambling = pipe_config->hdmi_scrambling;
2335
2336 intel_hdmi_handle_sink_scrambling(intel_encoder,
2337 conn_state->connector,
2338 clock_ratio, scrambling);
876a8cdf 2339
6547fef8
PZ		 2340 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2341 * are ignored so nothing special needs to be done besides
2342 * enabling the port.
2343 */
876a8cdf 2344 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2345 intel_dig_port->saved_port_bits |
2346 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2347 } else if (type == INTEL_OUTPUT_EDP) {
2348 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2349
66478475 2350 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3ab9c637
ID		 2351 intel_dp_stop_link_train(intel_dp);
2352
b037d58f 2353 intel_edp_backlight_on(pipe_config, conn_state);
d2419ffc 2354 intel_psr_enable(intel_dp, pipe_config);
85cb48a1 2355 intel_edp_drrs_enable(intel_dp, pipe_config);
6547fef8 2356 }
7b9f35a6 2357
37255d8d 2358 if (pipe_config->has_audio)
bbf35e9d 2359 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
5ab432ef
DV		 2360}
2361
fd6bbda9 2362static void intel_disable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2363 const struct intel_crtc_state *old_crtc_state,
2364 const struct drm_connector_state *old_conn_state)
5ab432ef 2365{
d6c50ff8
PZ		 2366 struct drm_encoder *encoder = &intel_encoder->base;
2367 int type = intel_encoder->type;
2368
37255d8d 2369 if (old_crtc_state->has_audio)
69bfe1a9 2370 intel_audio_codec_disable(intel_encoder);
2831d842 2371
15953637
SS		 2372 if (type == INTEL_OUTPUT_HDMI) {
2373 intel_hdmi_handle_sink_scrambling(intel_encoder,
2374 old_conn_state->connector,
2375 false, false);
2376 }
2377
d6c50ff8
PZ		 2378 if (type == INTEL_OUTPUT_EDP) {
2379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2380
85cb48a1 2381 intel_edp_drrs_disable(intel_dp, old_crtc_state);
d2419ffc 2382 intel_psr_disable(intel_dp, old_crtc_state);
b037d58f 2383 intel_edp_backlight_off(old_conn_state);
d6c50ff8 2384 }
72662e10 2385}
79f689aa 2386
fd6bbda9 2387static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2388 const struct intel_crtc_state *pipe_config,
2389 const struct drm_connector_state *conn_state)
95a7a2ae 2390{
3dc38eea 2391 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2392
47a6bc61 2393 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2394}
2395
ad64217b 2396void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2397{
ad64217b
ACO		 2398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2399 struct drm_i915_private *dev_priv =
2400 to_i915(intel_dig_port->base.base.dev);
174edf1f 2401 enum port port = intel_dig_port->port;
c19b0669 2402 uint32_t val;
f3e227df 2403 bool wait = false;
c19b0669
PZ		 2404
2405 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2406 val = I915_READ(DDI_BUF_CTL(port));
2407 if (val & DDI_BUF_CTL_ENABLE) {
2408 val &= ~DDI_BUF_CTL_ENABLE;
2409 I915_WRITE(DDI_BUF_CTL(port), val);
2410 wait = true;
2411 }
2412
2413 val = I915_READ(DP_TP_CTL(port));
2414 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2415 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2416 I915_WRITE(DP_TP_CTL(port), val);
2417 POSTING_READ(DP_TP_CTL(port));
2418
2419 if (wait)
2420 intel_wait_ddi_buf_idle(dev_priv, port);
2421 }
2422
0e32b39c 2423 val = DP_TP_CTL_ENABLE |
c19b0669 2424 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2425 if (intel_dp->link_mst)
0e32b39c
DA		 2426 val |= DP_TP_CTL_MODE_MST;
2427 else {
2428 val |= DP_TP_CTL_MODE_SST;
2429 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2430 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2431 }
c19b0669
PZ		 2432 I915_WRITE(DP_TP_CTL(port), val);
2433 POSTING_READ(DP_TP_CTL(port));
2434
2435 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2436 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2437 POSTING_READ(DDI_BUF_CTL(port));
2438
2439 udelay(600);
2440}
00c09d70 2441
9935f7fa
LY		 2442bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2443 struct intel_crtc *intel_crtc)
2444{
2445 u32 temp;
2446
2447 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2448 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2449 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2450 return true;
2451 }
2452 return false;
2453}
2454
6801c18c 2455void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2456 struct intel_crtc_state *pipe_config)
045ac3b5 2457{
fac5e23e 2458 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2459 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2460 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 2461 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 2462 u32 temp, flags = 0;
2463
4d1de975
JN		 2464 /* XXX: DSI transcoder paranoia */
2465 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2466 return;
2467
045ac3b5
JB		 2468 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2469 if (temp & TRANS_DDI_PHSYNC)
2470 flags |= DRM_MODE_FLAG_PHSYNC;
2471 else
2472 flags |= DRM_MODE_FLAG_NHSYNC;
2473 if (temp & TRANS_DDI_PVSYNC)
2474 flags |= DRM_MODE_FLAG_PVSYNC;
2475 else
2476 flags |= DRM_MODE_FLAG_NVSYNC;
2477
2d112de7 2478 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2479
2480 switch (temp & TRANS_DDI_BPC_MASK) {
2481 case TRANS_DDI_BPC_6:
2482 pipe_config->pipe_bpp = 18;
2483 break;
2484 case TRANS_DDI_BPC_8:
2485 pipe_config->pipe_bpp = 24;
2486 break;
2487 case TRANS_DDI_BPC_10:
2488 pipe_config->pipe_bpp = 30;
2489 break;
2490 case TRANS_DDI_BPC_12:
2491 pipe_config->pipe_bpp = 36;
2492 break;
2493 default:
2494 break;
2495 }
eb14cb74
VS		 2496
2497 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2498 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2499 pipe_config->has_hdmi_sink = true;
f99be1b3 2500 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 2501
f99be1b3 2502 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2503 pipe_config->has_infoframe = true;
15953637
SS		 2504
2505 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2506 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2507 pipe_config->hdmi_scrambling = true;
2508 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2509 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2510 /* fall through */
eb14cb74 2511 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2512 pipe_config->lane_count = 4;
2513 break;
eb14cb74
VS		 2514 case TRANS_DDI_MODE_SELECT_FDI:
2515 break;
2516 case TRANS_DDI_MODE_SELECT_DP_SST:
2517 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2518 pipe_config->lane_count =
2519 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2520 intel_dp_get_m_n(intel_crtc, pipe_config);
2521 break;
2522 default:
2523 break;
2524 }
10214420 2525
9935f7fa
LY		 2526 pipe_config->has_audio =
2527 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2528
6aa23e65
JN		 2529 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2530 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2531 /*
2532 * This is a big fat ugly hack.
2533 *
2534 * Some machines in UEFI boot mode provide us a VBT that has 18
2535 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2536 * unknown we fail to light up. Yet the same BIOS boots up with
2537 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2538 * max, not what it tells us to use.
2539 *
2540 * Note: This will still be broken if the eDP panel is not lit
2541 * up by the BIOS, and thus we can't get the mode at module
2542 * load.
2543 */
2544 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2545 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2546 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2547 }
11578553 2548
22606a18 2549 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2550
cc3f90f0 2551 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2552 pipe_config->lane_lat_optim_mask =
2553 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2554}
2555
5bfe2ac0 2556static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2557 struct intel_crtc_state *pipe_config,
2558 struct drm_connector_state *conn_state)
00c09d70 2559{
fac5e23e 2560 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2561 int type = encoder->type;
eccb140b 2562 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2563 int ret;
00c09d70 2564
5bfe2ac0 2565 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2566
eccb140b
DV		 2567 if (port == PORT_A)
2568 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2569
00c09d70 2570 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2571 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2572 else
0a478c27 2573 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2574
cc3f90f0 2575 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2576 pipe_config->lane_lat_optim_mask =
2577 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2578 pipe_config->lane_count);
95a7a2ae
ID		 2579
2580 return ret;
2581
00c09d70
PZ		 2582}
2583
2584static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2585 .reset = intel_dp_encoder_reset,
2586 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2587};
2588
4a28ae58
PZ		 2589static struct intel_connector *
2590intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2591{
2592 struct intel_connector *connector;
2593 enum port port = intel_dig_port->port;
2594
9bdbd0b9 2595 connector = intel_connector_alloc();
4a28ae58
PZ		 2596 if (!connector)
2597 return NULL;
2598
2599 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2600 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2601 kfree(connector);
2602 return NULL;
2603 }
2604
2605 return connector;
2606}
2607
2608static struct intel_connector *
2609intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2610{
2611 struct intel_connector *connector;
2612 enum port port = intel_dig_port->port;
2613
9bdbd0b9 2614 connector = intel_connector_alloc();
4a28ae58
PZ		 2615 if (!connector)
2616 return NULL;
2617
2618 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2619 intel_hdmi_init_connector(intel_dig_port, connector);
2620
2621 return connector;
2622}
2623
c39055b0 2624void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2625{
2626 struct intel_digital_port *intel_dig_port;
2627 struct intel_encoder *intel_encoder;
2628 struct drm_encoder *encoder;
ff662124 2629 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2630 int max_lanes;
2631
2632 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2633 switch (port) {
2634 case PORT_A:
2635 max_lanes = 4;
2636 break;
2637 case PORT_E:
2638 max_lanes = 0;
2639 break;
2640 default:
2641 max_lanes = 4;
2642 break;
2643 }
2644 } else {
2645 switch (port) {
2646 case PORT_A:
2647 max_lanes = 2;
2648 break;
2649 case PORT_E:
2650 max_lanes = 2;
2651 break;
2652 default:
2653 max_lanes = 4;
2654 break;
2655 }
2656 }
311a2094
PZ		 2657
2658 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2659 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2660 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2661
2662 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2663 /*
2664 * Lspcon device needs to be driven with DP connector
2665 * with special detection sequence. So make sure DP
2666 * is initialized before lspcon.
2667 */
2668 init_dp = true;
2669 init_lspcon = true;
2670 init_hdmi = false;
2671 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2672 }
2673
311a2094 2674 if (!init_dp && !init_hdmi) {
500ea70d 2675 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2676 port_name(port));
500ea70d 2677 return;
311a2094 2678 }
00c09d70 2679
b14c5679 2680 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2681 if (!intel_dig_port)
2682 return;
2683
00c09d70
PZ		 2684 intel_encoder = &intel_dig_port->base;
2685 encoder = &intel_encoder->base;
2686
c39055b0 2687 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2688 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2689
5bfe2ac0 2690 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2691 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2692 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2693 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2694 intel_encoder->pre_enable = intel_ddi_pre_enable;
2695 intel_encoder->disable = intel_disable_ddi;
2696 intel_encoder->post_disable = intel_ddi_post_disable;
2697 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2698 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2699 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2700 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2701
2702 intel_dig_port->port = port;
bcf53de4
SM		 2703 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2704 (DDI_BUF_PORT_REVERSAL |
2705 DDI_A_4_LANES);
00c09d70 2706
62b69566
ACO		 2707 switch (port) {
2708 case PORT_A:
2709 intel_dig_port->ddi_io_power_domain =
2710 POWER_DOMAIN_PORT_DDI_A_IO;
2711 break;
2712 case PORT_B:
2713 intel_dig_port->ddi_io_power_domain =
2714 POWER_DOMAIN_PORT_DDI_B_IO;
2715 break;
2716 case PORT_C:
2717 intel_dig_port->ddi_io_power_domain =
2718 POWER_DOMAIN_PORT_DDI_C_IO;
2719 break;
2720 case PORT_D:
2721 intel_dig_port->ddi_io_power_domain =
2722 POWER_DOMAIN_PORT_DDI_D_IO;
2723 break;
2724 case PORT_E:
2725 intel_dig_port->ddi_io_power_domain =
2726 POWER_DOMAIN_PORT_DDI_E_IO;
2727 break;
2728 default:
2729 MISSING_CASE(port);
2730 }
2731
6c566dc9
MR		 2732 /*
2733 * Bspec says that DDI_A_4_LANES is the only supported configuration
2734 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2735 * wasn't lit up at boot. Force this bit on in our internal
2736 * configuration so that we use the proper lane count for our
2737 * calculations.
2738 */
cc3f90f0 2739 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2740 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2741 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2742 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2743 max_lanes = 4;
6c566dc9
MR		 2744 }
2745 }
2746
ed8d60f4
MR		 2747 intel_dig_port->max_lanes = max_lanes;
2748
00c09d70 2749 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2750 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2751 intel_encoder->port = port;
f68d697e 2752 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2753 intel_encoder->cloneable = 0;
00c09d70 2754
385e4de0
VS		 2755 intel_infoframe_init(intel_dig_port);
2756
f68d697e
CW		 2757 if (init_dp) {
2758 if (!intel_ddi_init_dp_connector(intel_dig_port))
2759 goto err;
13cf5504 2760
f68d697e 2761 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2762 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2763 }
21a8e6a4 2764
311a2094
PZ		 2765 /* In theory we don't need the encoder->type check, but leave it just in
2766 * case we have some really bad VBTs... */
f68d697e
CW		 2767 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2768 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2769 goto err;
21a8e6a4 2770 }
f68d697e 2771
ff662124
SS		 2772 if (init_lspcon) {
2773 if (lspcon_init(intel_dig_port))
2774 /* TODO: handle hdmi info frame part */
2775 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2776 port_name(port));
2777 else
2778 /*
2779 * LSPCON init faied, but DP init was success, so
2780 * lets try to drive as DP++ port.
2781 */
2782 DRM_ERROR("LSPCON init failed on port %c\n",
2783 port_name(port));
2784 }
2785
f68d697e
CW		 2786 return;
2787
2788err:
2789 drm_encoder_cleanup(encoder);
2790 kfree(intel_dig_port);
00c09d70 2791}
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