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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
35 | }; |
36 | ||
97eeb872 VS |
37 | static const u8 index_to_dp_signal_levels[] = { |
38 | [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
39 | [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
40 | [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
41 | [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, | |
42 | [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
43 | [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
44 | [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
45 | [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
46 | [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
47 | [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
48 | }; | |
49 | ||
45244b87 ED |
50 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
51 | * them for both DP and FDI transports, allowing those ports to | |
52 | * automatically adapt to HDMI connections as well | |
53 | */ | |
10122051 | 54 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
55 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
56 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
57 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
58 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
59 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
60 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
61 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
62 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
63 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
64 | }; |
65 | ||
10122051 | 66 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
67 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
68 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
69 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
70 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
71 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
72 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
73 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
74 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
75 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
76 | }; |
77 | ||
10122051 JN |
78 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
79 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
80 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
81 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
82 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
83 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
84 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
85 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
86 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
87 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
88 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
89 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
90 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
91 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
92 | }; |
93 | ||
10122051 | 94 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
95 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
96 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
97 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
98 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
99 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
100 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
101 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
102 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
103 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
104 | }; |
105 | ||
10122051 | 106 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
107 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
108 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
109 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
110 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
111 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
112 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
113 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
114 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
115 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
116 | }; |
117 | ||
10122051 | 118 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
119 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
120 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
121 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
122 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
123 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
124 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
125 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
126 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
127 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
128 | }; |
129 | ||
10122051 JN |
130 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
131 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
132 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
133 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
134 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
135 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
136 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
137 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
138 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
139 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
140 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
141 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
142 | }; |
143 | ||
5f8b2531 | 144 | /* Skylake H and S */ |
7f88e3af | 145 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
146 | { 0x00002016, 0x000000A0, 0x0 }, |
147 | { 0x00005012, 0x0000009B, 0x0 }, | |
148 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
150 | { 0x00002016, 0x0000009B, 0x0 }, |
151 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 152 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 153 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
155 | }; |
156 | ||
f8896f5d DW |
157 | /* Skylake U */ |
158 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 159 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 160 | { 0x00005012, 0x00000088, 0x0 }, |
5ac90567 | 161 | { 0x80007011, 0x000000CD, 0x1 }, |
d7097cff | 162 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 163 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
164 | { 0x80005012, 0x000000C0, 0x1 }, |
165 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 166 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 167 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
168 | }; |
169 | ||
5f8b2531 RV |
170 | /* Skylake Y */ |
171 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
172 | { 0x00000018, 0x000000A2, 0x0 }, |
173 | { 0x00005012, 0x00000088, 0x0 }, | |
5ac90567 | 174 | { 0x80007011, 0x000000CD, 0x3 }, |
d7097cff | 175 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 176 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
177 | { 0x80005012, 0x000000C0, 0x3 }, |
178 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 179 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 180 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
181 | }; |
182 | ||
0fdd4918 RV |
183 | /* Kabylake H and S */ |
184 | static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { | |
185 | { 0x00002016, 0x000000A0, 0x0 }, | |
186 | { 0x00005012, 0x0000009B, 0x0 }, | |
187 | { 0x00007011, 0x00000088, 0x0 }, | |
188 | { 0x80009010, 0x000000C0, 0x1 }, | |
189 | { 0x00002016, 0x0000009B, 0x0 }, | |
190 | { 0x00005012, 0x00000088, 0x0 }, | |
191 | { 0x80007011, 0x000000C0, 0x1 }, | |
192 | { 0x00002016, 0x00000097, 0x0 }, | |
193 | { 0x80005012, 0x000000C0, 0x1 }, | |
194 | }; | |
195 | ||
196 | /* Kabylake U */ | |
197 | static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { | |
198 | { 0x0000201B, 0x000000A1, 0x0 }, | |
199 | { 0x00005012, 0x00000088, 0x0 }, | |
200 | { 0x80007011, 0x000000CD, 0x3 }, | |
201 | { 0x80009010, 0x000000C0, 0x3 }, | |
202 | { 0x0000201B, 0x0000009D, 0x0 }, | |
203 | { 0x80005012, 0x000000C0, 0x3 }, | |
204 | { 0x80007011, 0x000000C0, 0x3 }, | |
205 | { 0x00002016, 0x0000004F, 0x0 }, | |
206 | { 0x80005012, 0x000000C0, 0x3 }, | |
207 | }; | |
208 | ||
209 | /* Kabylake Y */ | |
210 | static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { | |
211 | { 0x00001017, 0x000000A1, 0x0 }, | |
212 | { 0x00005012, 0x00000088, 0x0 }, | |
213 | { 0x80007011, 0x000000CD, 0x3 }, | |
214 | { 0x8000800F, 0x000000C0, 0x3 }, | |
215 | { 0x00001017, 0x0000009D, 0x0 }, | |
216 | { 0x80005012, 0x000000C0, 0x3 }, | |
217 | { 0x80007011, 0x000000C0, 0x3 }, | |
218 | { 0x00001017, 0x0000004C, 0x0 }, | |
219 | { 0x80005012, 0x000000C0, 0x3 }, | |
220 | }; | |
221 | ||
f8896f5d | 222 | /* |
0fdd4918 | 223 | * Skylake/Kabylake H and S |
f8896f5d DW |
224 | * eDP 1.4 low vswing translation parameters |
225 | */ | |
7ad14a29 | 226 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
227 | { 0x00000018, 0x000000A8, 0x0 }, |
228 | { 0x00004013, 0x000000A9, 0x0 }, | |
229 | { 0x00007011, 0x000000A2, 0x0 }, | |
230 | { 0x00009010, 0x0000009C, 0x0 }, | |
231 | { 0x00000018, 0x000000A9, 0x0 }, | |
232 | { 0x00006013, 0x000000A2, 0x0 }, | |
233 | { 0x00007011, 0x000000A6, 0x0 }, | |
234 | { 0x00000018, 0x000000AB, 0x0 }, | |
235 | { 0x00007013, 0x0000009F, 0x0 }, | |
236 | { 0x00000018, 0x000000DF, 0x0 }, | |
237 | }; | |
238 | ||
239 | /* | |
0fdd4918 | 240 | * Skylake/Kabylake U |
f8896f5d DW |
241 | * eDP 1.4 low vswing translation parameters |
242 | */ | |
243 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
244 | { 0x00000018, 0x000000A8, 0x0 }, | |
245 | { 0x00004013, 0x000000A9, 0x0 }, | |
246 | { 0x00007011, 0x000000A2, 0x0 }, | |
247 | { 0x00009010, 0x0000009C, 0x0 }, | |
248 | { 0x00000018, 0x000000A9, 0x0 }, | |
249 | { 0x00006013, 0x000000A2, 0x0 }, | |
250 | { 0x00007011, 0x000000A6, 0x0 }, | |
251 | { 0x00002016, 0x000000AB, 0x0 }, | |
252 | { 0x00005013, 0x0000009F, 0x0 }, | |
253 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
254 | }; |
255 | ||
f8896f5d | 256 | /* |
0fdd4918 | 257 | * Skylake/Kabylake Y |
f8896f5d DW |
258 | * eDP 1.4 low vswing translation parameters |
259 | */ | |
5f8b2531 | 260 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
261 | { 0x00000018, 0x000000A8, 0x0 }, |
262 | { 0x00004013, 0x000000AB, 0x0 }, | |
263 | { 0x00007011, 0x000000A4, 0x0 }, | |
264 | { 0x00009010, 0x000000DF, 0x0 }, | |
265 | { 0x00000018, 0x000000AA, 0x0 }, | |
266 | { 0x00006013, 0x000000A4, 0x0 }, | |
267 | { 0x00007011, 0x0000009D, 0x0 }, | |
268 | { 0x00000018, 0x000000A0, 0x0 }, | |
269 | { 0x00006012, 0x000000DF, 0x0 }, | |
270 | { 0x00000018, 0x0000008A, 0x0 }, | |
271 | }; | |
7ad14a29 | 272 | |
0fdd4918 | 273 | /* Skylake/Kabylake U, H and S */ |
7f88e3af | 274 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
275 | { 0x00000018, 0x000000AC, 0x0 }, |
276 | { 0x00005012, 0x0000009D, 0x0 }, | |
277 | { 0x00007011, 0x00000088, 0x0 }, | |
278 | { 0x00000018, 0x000000A1, 0x0 }, | |
279 | { 0x00000018, 0x00000098, 0x0 }, | |
280 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 281 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 282 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
283 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
284 | { 0x80003015, 0x000000C0, 0x1 }, | |
285 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
286 | }; |
287 | ||
0fdd4918 | 288 | /* Skylake/Kabylake Y */ |
5f8b2531 | 289 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
f8896f5d DW |
290 | { 0x00000018, 0x000000A1, 0x0 }, |
291 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 292 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
293 | { 0x00000018, 0x000000A4, 0x0 }, |
294 | { 0x00000018, 0x0000009D, 0x0 }, | |
295 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 296 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 297 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
298 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
299 | { 0x80003015, 0x000000C0, 0x3 }, | |
300 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
301 | }; |
302 | ||
96fb9f9b VK |
303 | struct bxt_ddi_buf_trans { |
304 | u32 margin; /* swing value */ | |
305 | u32 scale; /* scale value */ | |
306 | u32 enable; /* scale enable */ | |
307 | u32 deemphasis; | |
308 | bool default_index; /* true if the entry represents default value */ | |
309 | }; | |
310 | ||
96fb9f9b VK |
311 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
312 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
313 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
314 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
315 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
316 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
317 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
318 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
319 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
320 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
321 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
f8896f5d | 322 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
96fb9f9b VK |
323 | }; |
324 | ||
d9d7000d SJ |
325 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
326 | /* Idx NT mV diff db */ | |
327 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ | |
328 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ | |
329 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ | |
330 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ | |
331 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ | |
332 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ | |
333 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ | |
334 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ | |
335 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ | |
336 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ | |
337 | }; | |
338 | ||
96fb9f9b VK |
339 | /* BSpec has 2 recommended values - entries 0 and 8. |
340 | * Using the entry with higher vswing. | |
341 | */ | |
342 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
343 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
344 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
345 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
346 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
347 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
348 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
349 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
350 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
351 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
352 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
96fb9f9b VK |
353 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
354 | }; | |
355 | ||
5a5d24dc | 356 | enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) |
fc914639 | 357 | { |
5a5d24dc | 358 | switch (encoder->type) { |
8cd21b7f | 359 | case INTEL_OUTPUT_DP_MST: |
5a5d24dc | 360 | return enc_to_mst(&encoder->base)->primary->port; |
cca0502b | 361 | case INTEL_OUTPUT_DP: |
8cd21b7f JN |
362 | case INTEL_OUTPUT_EDP: |
363 | case INTEL_OUTPUT_HDMI: | |
364 | case INTEL_OUTPUT_UNKNOWN: | |
5a5d24dc | 365 | return enc_to_dig_port(&encoder->base)->port; |
8cd21b7f | 366 | case INTEL_OUTPUT_ANALOG: |
5a5d24dc VS |
367 | return PORT_E; |
368 | default: | |
369 | MISSING_CASE(encoder->type); | |
370 | return PORT_A; | |
fc914639 PZ |
371 | } |
372 | } | |
373 | ||
a930acd9 VS |
374 | static const struct ddi_buf_trans * |
375 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
376 | { | |
377 | if (dev_priv->vbt.edp.low_vswing) { | |
378 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
379 | return bdw_ddi_translations_edp; | |
380 | } else { | |
381 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
382 | return bdw_ddi_translations_dp; | |
383 | } | |
384 | } | |
385 | ||
acee2998 | 386 | static const struct ddi_buf_trans * |
78ab0bae | 387 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 388 | { |
0fdd4918 | 389 | if (IS_SKL_ULX(dev_priv)) { |
5f8b2531 | 390 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 391 | return skl_y_ddi_translations_dp; |
0fdd4918 | 392 | } else if (IS_SKL_ULT(dev_priv)) { |
f8896f5d | 393 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 394 | return skl_u_ddi_translations_dp; |
f8896f5d | 395 | } else { |
f8896f5d | 396 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 397 | return skl_ddi_translations_dp; |
f8896f5d | 398 | } |
f8896f5d DW |
399 | } |
400 | ||
0fdd4918 RV |
401 | static const struct ddi_buf_trans * |
402 | kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
403 | { | |
404 | if (IS_KBL_ULX(dev_priv)) { | |
405 | *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); | |
406 | return kbl_y_ddi_translations_dp; | |
407 | } else if (IS_KBL_ULT(dev_priv)) { | |
408 | *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); | |
409 | return kbl_u_ddi_translations_dp; | |
410 | } else { | |
411 | *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); | |
412 | return kbl_ddi_translations_dp; | |
413 | } | |
414 | } | |
415 | ||
acee2998 | 416 | static const struct ddi_buf_trans * |
78ab0bae | 417 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 418 | { |
06411f08 | 419 | if (dev_priv->vbt.edp.low_vswing) { |
78ab0bae | 420 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 421 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 422 | return skl_y_ddi_translations_edp; |
78ab0bae | 423 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 424 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 425 | return skl_u_ddi_translations_edp; |
f8896f5d | 426 | } else { |
f8896f5d | 427 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 428 | return skl_ddi_translations_edp; |
f8896f5d DW |
429 | } |
430 | } | |
cd1101cb | 431 | |
0fdd4918 RV |
432 | if (IS_KABYLAKE(dev_priv)) |
433 | return kbl_get_buf_trans_dp(dev_priv, n_entries); | |
434 | else | |
435 | return skl_get_buf_trans_dp(dev_priv, n_entries); | |
f8896f5d DW |
436 | } |
437 | ||
438 | static const struct ddi_buf_trans * | |
78ab0bae | 439 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 440 | { |
78ab0bae | 441 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 442 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 443 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 444 | } else { |
f8896f5d | 445 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 446 | return skl_ddi_translations_hdmi; |
f8896f5d | 447 | } |
f8896f5d DW |
448 | } |
449 | ||
8d8bb85e VS |
450 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
451 | { | |
452 | int n_hdmi_entries; | |
453 | int hdmi_level; | |
454 | int hdmi_default_entry; | |
455 | ||
456 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; | |
457 | ||
cc3f90f0 | 458 | if (IS_GEN9_LP(dev_priv)) |
8d8bb85e VS |
459 | return hdmi_level; |
460 | ||
b976dc53 | 461 | if (IS_GEN9_BC(dev_priv)) { |
8d8bb85e VS |
462 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
463 | hdmi_default_entry = 8; | |
464 | } else if (IS_BROADWELL(dev_priv)) { | |
465 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
466 | hdmi_default_entry = 7; | |
467 | } else if (IS_HASWELL(dev_priv)) { | |
468 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
469 | hdmi_default_entry = 6; | |
470 | } else { | |
471 | WARN(1, "ddi translation table missing\n"); | |
472 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
473 | hdmi_default_entry = 7; | |
474 | } | |
475 | ||
476 | /* Choose a good default if VBT is badly populated */ | |
477 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
478 | hdmi_level >= n_hdmi_entries) | |
479 | hdmi_level = hdmi_default_entry; | |
480 | ||
481 | return hdmi_level; | |
482 | } | |
483 | ||
7d1c42e6 VS |
484 | static const struct ddi_buf_trans * |
485 | intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, | |
486 | int *n_entries) | |
487 | { | |
488 | if (IS_KABYLAKE(dev_priv)) { | |
489 | return kbl_get_buf_trans_dp(dev_priv, n_entries); | |
490 | } else if (IS_SKYLAKE(dev_priv)) { | |
491 | return skl_get_buf_trans_dp(dev_priv, n_entries); | |
492 | } else if (IS_BROADWELL(dev_priv)) { | |
493 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
494 | return bdw_ddi_translations_dp; | |
495 | } else if (IS_HASWELL(dev_priv)) { | |
496 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
497 | return hsw_ddi_translations_dp; | |
498 | } | |
499 | ||
500 | *n_entries = 0; | |
501 | return NULL; | |
502 | } | |
503 | ||
504 | static const struct ddi_buf_trans * | |
505 | intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, | |
506 | int *n_entries) | |
507 | { | |
508 | if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) { | |
509 | return skl_get_buf_trans_edp(dev_priv, n_entries); | |
510 | } else if (IS_BROADWELL(dev_priv)) { | |
511 | return bdw_get_buf_trans_edp(dev_priv, n_entries); | |
512 | } else if (IS_HASWELL(dev_priv)) { | |
513 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
514 | return hsw_ddi_translations_dp; | |
515 | } | |
516 | ||
517 | *n_entries = 0; | |
518 | return NULL; | |
519 | } | |
520 | ||
521 | static const struct ddi_buf_trans * | |
522 | intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, | |
523 | int *n_entries) | |
524 | { | |
525 | if (IS_BROADWELL(dev_priv)) { | |
526 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); | |
527 | return hsw_ddi_translations_fdi; | |
528 | } else if (IS_HASWELL(dev_priv)) { | |
529 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); | |
530 | return hsw_ddi_translations_fdi; | |
531 | } | |
532 | ||
533 | *n_entries = 0; | |
534 | return NULL; | |
535 | } | |
536 | ||
e58623cb AR |
537 | /* |
538 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
32bdc400 VS |
539 | * values in advance. This function programs the correct values for |
540 | * DP/eDP/FDI use cases. | |
45244b87 | 541 | */ |
32bdc400 | 542 | void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) |
45244b87 | 543 | { |
6a7e4f99 | 544 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 545 | u32 iboost_bit = 0; |
7d1c42e6 | 546 | int i, n_entries; |
32bdc400 | 547 | enum port port = intel_ddi_get_encoder_port(encoder); |
10122051 | 548 | const struct ddi_buf_trans *ddi_translations; |
e58623cb | 549 | |
cc3f90f0 | 550 | if (IS_GEN9_LP(dev_priv)) |
96fb9f9b | 551 | return; |
6a7e4f99 | 552 | |
7d1c42e6 VS |
553 | switch (encoder->type) { |
554 | case INTEL_OUTPUT_EDP: | |
555 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, | |
556 | &n_entries); | |
557 | break; | |
558 | case INTEL_OUTPUT_DP: | |
559 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, | |
560 | &n_entries); | |
561 | break; | |
562 | case INTEL_OUTPUT_ANALOG: | |
563 | ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, | |
564 | &n_entries); | |
565 | break; | |
566 | default: | |
567 | MISSING_CASE(encoder->type); | |
568 | return; | |
e58623cb AR |
569 | } |
570 | ||
b976dc53 | 571 | if (IS_GEN9_BC(dev_priv)) { |
0a91877c RV |
572 | /* If we're boosting the current, set bit 31 of trans1 */ |
573 | if (dev_priv->vbt.ddi_port_info[port].dp_boost_level) | |
574 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
575 | ||
576 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && | |
577 | port != PORT_A && port != PORT_E && | |
7d1c42e6 VS |
578 | n_entries > 9)) |
579 | n_entries = 9; | |
300644c7 | 580 | } |
45244b87 | 581 | |
7d1c42e6 | 582 | for (i = 0; i < n_entries; i++) { |
9712e688 VS |
583 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
584 | ddi_translations[i].trans1 | iboost_bit); | |
585 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
586 | ddi_translations[i].trans2); | |
45244b87 | 587 | } |
32bdc400 VS |
588 | } |
589 | ||
590 | /* | |
591 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
592 | * values in advance. This function programs the correct values for | |
593 | * HDMI/DVI use cases. | |
594 | */ | |
595 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) | |
596 | { | |
597 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
598 | u32 iboost_bit = 0; | |
599 | int n_hdmi_entries, hdmi_level; | |
600 | enum port port = intel_ddi_get_encoder_port(encoder); | |
601 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
ce4dd49e | 602 | |
cc3f90f0 | 603 | if (IS_GEN9_LP(dev_priv)) |
ce3b7e9b DL |
604 | return; |
605 | ||
32bdc400 VS |
606 | hdmi_level = intel_ddi_hdmi_level(dev_priv, port); |
607 | ||
b976dc53 | 608 | if (IS_GEN9_BC(dev_priv)) { |
32bdc400 | 609 | ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
1edaaa2f | 610 | |
32bdc400 | 611 | /* If we're boosting the current, set bit 31 of trans1 */ |
1edaaa2f | 612 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) |
32bdc400 VS |
613 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
614 | } else if (IS_BROADWELL(dev_priv)) { | |
615 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
616 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
617 | } else if (IS_HASWELL(dev_priv)) { | |
618 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; | |
619 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
620 | } else { | |
621 | WARN(1, "ddi translation table missing\n"); | |
622 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
623 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
624 | } | |
625 | ||
6acab15a | 626 | /* Entry 9 is for HDMI: */ |
ed9c77d2 | 627 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
9712e688 | 628 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
ed9c77d2 | 629 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
9712e688 | 630 | ddi_translations_hdmi[hdmi_level].trans2); |
45244b87 ED |
631 | } |
632 | ||
248138b5 PZ |
633 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
634 | enum port port) | |
635 | { | |
f0f59a00 | 636 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
637 | int i; |
638 | ||
3449ca85 | 639 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
640 | udelay(1); |
641 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
642 | return; | |
643 | } | |
644 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
645 | } | |
c82e4d26 | 646 | |
c856052a ACO |
647 | static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) |
648 | { | |
649 | switch (pll->id) { | |
650 | case DPLL_ID_WRPLL1: | |
651 | return PORT_CLK_SEL_WRPLL1; | |
652 | case DPLL_ID_WRPLL2: | |
653 | return PORT_CLK_SEL_WRPLL2; | |
654 | case DPLL_ID_SPLL: | |
655 | return PORT_CLK_SEL_SPLL; | |
656 | case DPLL_ID_LCPLL_810: | |
657 | return PORT_CLK_SEL_LCPLL_810; | |
658 | case DPLL_ID_LCPLL_1350: | |
659 | return PORT_CLK_SEL_LCPLL_1350; | |
660 | case DPLL_ID_LCPLL_2700: | |
661 | return PORT_CLK_SEL_LCPLL_2700; | |
662 | default: | |
663 | MISSING_CASE(pll->id); | |
664 | return PORT_CLK_SEL_NONE; | |
665 | } | |
666 | } | |
667 | ||
c82e4d26 ED |
668 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
669 | * connection to the PCH-located connectors. For this, it is necessary to train | |
670 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
671 | * | |
672 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
673 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
674 | * DDI A (which is used for eDP) | |
675 | */ | |
676 | ||
677 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
678 | { | |
679 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 680 | struct drm_i915_private *dev_priv = to_i915(dev); |
c82e4d26 | 681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6a7e4f99 | 682 | struct intel_encoder *encoder; |
c856052a | 683 | u32 temp, i, rx_ctl_val, ddi_pll_sel; |
c82e4d26 | 684 | |
6a7e4f99 VS |
685 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
686 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); | |
32bdc400 | 687 | intel_prepare_dp_ddi_buffers(encoder); |
6a7e4f99 VS |
688 | } |
689 | ||
04945641 PZ |
690 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
691 | * mode set "sequence for CRT port" document: | |
692 | * - TP1 to TP2 time with the default value | |
693 | * - FDI delay to 90h | |
8693a824 DL |
694 | * |
695 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 696 | */ |
eede3b53 | 697 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
698 | FDI_RX_PWRDN_LANE0_VAL(2) | |
699 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
700 | ||
701 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 702 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 703 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 704 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
eede3b53 VS |
705 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
706 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
707 | udelay(220); |
708 | ||
709 | /* Switch from Rawclk to PCDclk */ | |
710 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 711 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
712 | |
713 | /* Configure Port Clock Select */ | |
c856052a ACO |
714 | ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll); |
715 | I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); | |
716 | WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
717 | |
718 | /* Start the training iterating through available voltages and emphasis, | |
719 | * testing each value twice. */ | |
10122051 | 720 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
721 | /* Configure DP_TP_CTL with auto-training */ |
722 | I915_WRITE(DP_TP_CTL(PORT_E), | |
723 | DP_TP_CTL_FDI_AUTOTRAIN | | |
724 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
725 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
726 | DP_TP_CTL_ENABLE); | |
727 | ||
876a8cdf DL |
728 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
729 | * DDI E does not support port reversal, the functionality is | |
730 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
731 | * port reversal bit */ | |
c82e4d26 | 732 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 733 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 734 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 735 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 736 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
737 | |
738 | udelay(600); | |
739 | ||
04945641 | 740 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 741 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
742 | |
743 | /* Enable PCH FDI Receiver with auto-training */ | |
744 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
745 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
746 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
747 | |
748 | /* Wait for FDI receiver lane calibration */ | |
749 | udelay(30); | |
750 | ||
751 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 752 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 753 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
754 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
755 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
756 | |
757 | /* Wait for FDI auto training time */ | |
758 | udelay(5); | |
c82e4d26 ED |
759 | |
760 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
761 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 762 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
763 | break; |
764 | } | |
c82e4d26 | 765 | |
a308ccb3 VS |
766 | /* |
767 | * Leave things enabled even if we failed to train FDI. | |
768 | * Results in less fireworks from the state checker. | |
769 | */ | |
770 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
771 | DRM_ERROR("FDI link training failed!\n"); | |
772 | break; | |
c82e4d26 | 773 | } |
04945641 | 774 | |
5b421c57 VS |
775 | rx_ctl_val &= ~FDI_RX_ENABLE; |
776 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); | |
777 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
778 | ||
248138b5 PZ |
779 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
780 | temp &= ~DDI_BUF_CTL_ENABLE; | |
781 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
782 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
783 | ||
04945641 | 784 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
785 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
786 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
787 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
788 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
789 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
790 | ||
791 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 | 792 | |
04945641 | 793 | /* Reset FDI_RX_MISC pwrdn lanes */ |
eede3b53 | 794 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
795 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
796 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
797 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
798 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
799 | } |
800 | ||
a308ccb3 VS |
801 | /* Enable normal pixel sending for FDI */ |
802 | I915_WRITE(DP_TP_CTL(PORT_E), | |
803 | DP_TP_CTL_FDI_AUTOTRAIN | | |
804 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
805 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
806 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 807 | } |
0e72a5b5 | 808 | |
44905a27 DA |
809 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
810 | { | |
811 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
812 | struct intel_digital_port *intel_dig_port = | |
813 | enc_to_dig_port(&encoder->base); | |
814 | ||
815 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 816 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 817 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
818 | } |
819 | ||
8d9ddbcb PZ |
820 | static struct intel_encoder * |
821 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
822 | { | |
823 | struct drm_device *dev = crtc->dev; | |
824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
825 | struct intel_encoder *intel_encoder, *ret = NULL; | |
826 | int num_encoders = 0; | |
827 | ||
828 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
829 | ret = intel_encoder; | |
830 | num_encoders++; | |
831 | } | |
832 | ||
833 | if (num_encoders != 1) | |
84f44ce7 VS |
834 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
835 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
836 | |
837 | BUG_ON(ret == NULL); | |
838 | return ret; | |
839 | } | |
840 | ||
bcddf610 | 841 | struct intel_encoder * |
3165c074 | 842 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 843 | { |
3165c074 ACO |
844 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
845 | struct intel_encoder *ret = NULL; | |
846 | struct drm_atomic_state *state; | |
da3ced29 ACO |
847 | struct drm_connector *connector; |
848 | struct drm_connector_state *connector_state; | |
d0737e1d | 849 | int num_encoders = 0; |
3165c074 | 850 | int i; |
d0737e1d | 851 | |
3165c074 ACO |
852 | state = crtc_state->base.state; |
853 | ||
da3ced29 ACO |
854 | for_each_connector_in_state(state, connector, connector_state, i) { |
855 | if (connector_state->crtc != crtc_state->base.crtc) | |
3165c074 ACO |
856 | continue; |
857 | ||
da3ced29 | 858 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 859 | num_encoders++; |
d0737e1d ACO |
860 | } |
861 | ||
862 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
863 | pipe_name(crtc->pipe)); | |
864 | ||
865 | BUG_ON(ret == NULL); | |
866 | return ret; | |
867 | } | |
868 | ||
1c0b85c5 | 869 | #define LC_FREQ 2700 |
1c0b85c5 | 870 | |
f0f59a00 VS |
871 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
872 | i915_reg_t reg) | |
11578553 JB |
873 | { |
874 | int refclk = LC_FREQ; | |
875 | int n, p, r; | |
876 | u32 wrpll; | |
877 | ||
878 | wrpll = I915_READ(reg); | |
114fe488 DV |
879 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
880 | case WRPLL_PLL_SSC: | |
881 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
882 | /* |
883 | * We could calculate spread here, but our checking | |
884 | * code only cares about 5% accuracy, and spread is a max of | |
885 | * 0.5% downspread. | |
886 | */ | |
887 | refclk = 135; | |
888 | break; | |
114fe488 | 889 | case WRPLL_PLL_LCPLL: |
11578553 JB |
890 | refclk = LC_FREQ; |
891 | break; | |
892 | default: | |
893 | WARN(1, "bad wrpll refclk\n"); | |
894 | return 0; | |
895 | } | |
896 | ||
897 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
898 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
899 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
900 | ||
20f0ec16 JB |
901 | /* Convert to KHz, p & r have a fixed point portion */ |
902 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
903 | } |
904 | ||
540e732c S |
905 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
906 | uint32_t dpll) | |
907 | { | |
f0f59a00 | 908 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
540e732c S |
909 | uint32_t cfgcr1_val, cfgcr2_val; |
910 | uint32_t p0, p1, p2, dco_freq; | |
911 | ||
923c1241 VS |
912 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
913 | cfgcr2_reg = DPLL_CFGCR2(dpll); | |
540e732c S |
914 | |
915 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
916 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
917 | ||
918 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
919 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
920 | ||
921 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
922 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
923 | else | |
924 | p1 = 1; | |
925 | ||
926 | ||
927 | switch (p0) { | |
928 | case DPLL_CFGCR2_PDIV_1: | |
929 | p0 = 1; | |
930 | break; | |
931 | case DPLL_CFGCR2_PDIV_2: | |
932 | p0 = 2; | |
933 | break; | |
934 | case DPLL_CFGCR2_PDIV_3: | |
935 | p0 = 3; | |
936 | break; | |
937 | case DPLL_CFGCR2_PDIV_7: | |
938 | p0 = 7; | |
939 | break; | |
940 | } | |
941 | ||
942 | switch (p2) { | |
943 | case DPLL_CFGCR2_KDIV_5: | |
944 | p2 = 5; | |
945 | break; | |
946 | case DPLL_CFGCR2_KDIV_2: | |
947 | p2 = 2; | |
948 | break; | |
949 | case DPLL_CFGCR2_KDIV_3: | |
950 | p2 = 3; | |
951 | break; | |
952 | case DPLL_CFGCR2_KDIV_1: | |
953 | p2 = 1; | |
954 | break; | |
955 | } | |
956 | ||
957 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
958 | ||
959 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
960 | 1000) / 0x8000; | |
961 | ||
962 | return dco_freq / (p0 * p1 * p2 * 5); | |
963 | } | |
964 | ||
398a017e VS |
965 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
966 | { | |
967 | int dotclock; | |
968 | ||
969 | if (pipe_config->has_pch_encoder) | |
970 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
971 | &pipe_config->fdi_m_n); | |
37a5650b | 972 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
398a017e VS |
973 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
974 | &pipe_config->dp_m_n); | |
975 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) | |
976 | dotclock = pipe_config->port_clock * 2 / 3; | |
977 | else | |
978 | dotclock = pipe_config->port_clock; | |
979 | ||
980 | if (pipe_config->pixel_multiplier) | |
981 | dotclock /= pipe_config->pixel_multiplier; | |
982 | ||
983 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
984 | } | |
540e732c S |
985 | |
986 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 987 | struct intel_crtc_state *pipe_config) |
540e732c | 988 | { |
fac5e23e | 989 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
540e732c S |
990 | int link_clock = 0; |
991 | uint32_t dpll_ctl1, dpll; | |
992 | ||
c856052a | 993 | dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); |
540e732c S |
994 | |
995 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
996 | ||
997 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
998 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
999 | } else { | |
71cd8423 DL |
1000 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
1001 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); | |
540e732c S |
1002 | |
1003 | switch (link_clock) { | |
71cd8423 | 1004 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
1005 | link_clock = 81000; |
1006 | break; | |
71cd8423 | 1007 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
1008 | link_clock = 108000; |
1009 | break; | |
71cd8423 | 1010 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
1011 | link_clock = 135000; |
1012 | break; | |
71cd8423 | 1013 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
1014 | link_clock = 162000; |
1015 | break; | |
71cd8423 | 1016 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
1017 | link_clock = 216000; |
1018 | break; | |
71cd8423 | 1019 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
1020 | link_clock = 270000; |
1021 | break; | |
1022 | default: | |
1023 | WARN(1, "Unsupported link rate\n"); | |
1024 | break; | |
1025 | } | |
1026 | link_clock *= 2; | |
1027 | } | |
1028 | ||
1029 | pipe_config->port_clock = link_clock; | |
1030 | ||
398a017e | 1031 | ddi_dotclock_get(pipe_config); |
540e732c S |
1032 | } |
1033 | ||
3d51278a | 1034 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1035 | struct intel_crtc_state *pipe_config) |
11578553 | 1036 | { |
fac5e23e | 1037 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
11578553 JB |
1038 | int link_clock = 0; |
1039 | u32 val, pll; | |
1040 | ||
c856052a | 1041 | val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); |
11578553 JB |
1042 | switch (val & PORT_CLK_SEL_MASK) { |
1043 | case PORT_CLK_SEL_LCPLL_810: | |
1044 | link_clock = 81000; | |
1045 | break; | |
1046 | case PORT_CLK_SEL_LCPLL_1350: | |
1047 | link_clock = 135000; | |
1048 | break; | |
1049 | case PORT_CLK_SEL_LCPLL_2700: | |
1050 | link_clock = 270000; | |
1051 | break; | |
1052 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 1053 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
1054 | break; |
1055 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 1056 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
1057 | break; |
1058 | case PORT_CLK_SEL_SPLL: | |
1059 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
1060 | if (pll == SPLL_PLL_FREQ_810MHz) | |
1061 | link_clock = 81000; | |
1062 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
1063 | link_clock = 135000; | |
1064 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
1065 | link_clock = 270000; | |
1066 | else { | |
1067 | WARN(1, "bad spll freq\n"); | |
1068 | return; | |
1069 | } | |
1070 | break; | |
1071 | default: | |
1072 | WARN(1, "bad port clock sel\n"); | |
1073 | return; | |
1074 | } | |
1075 | ||
1076 | pipe_config->port_clock = link_clock * 2; | |
1077 | ||
398a017e | 1078 | ddi_dotclock_get(pipe_config); |
11578553 JB |
1079 | } |
1080 | ||
977bb38d S |
1081 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
1082 | enum intel_dpll_id dpll) | |
1083 | { | |
aa610dcb ID |
1084 | struct intel_shared_dpll *pll; |
1085 | struct intel_dpll_hw_state *state; | |
9e2c8475 | 1086 | struct dpll clock; |
aa610dcb ID |
1087 | |
1088 | /* For DDI ports we always use a shared PLL. */ | |
1089 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) | |
1090 | return 0; | |
1091 | ||
1092 | pll = &dev_priv->shared_dplls[dpll]; | |
2c42e535 | 1093 | state = &pll->state.hw_state; |
aa610dcb ID |
1094 | |
1095 | clock.m1 = 2; | |
1096 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; | |
1097 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
1098 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
1099 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
1100 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
1101 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
1102 | ||
1103 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
1104 | } |
1105 | ||
1106 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
1107 | struct intel_crtc_state *pipe_config) | |
1108 | { | |
fac5e23e | 1109 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
977bb38d S |
1110 | enum port port = intel_ddi_get_encoder_port(encoder); |
1111 | uint32_t dpll = port; | |
1112 | ||
398a017e | 1113 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
977bb38d | 1114 | |
398a017e | 1115 | ddi_dotclock_get(pipe_config); |
977bb38d S |
1116 | } |
1117 | ||
3d51278a | 1118 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1119 | struct intel_crtc_state *pipe_config) |
3d51278a | 1120 | { |
0853723b | 1121 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22606a18 | 1122 | |
0853723b | 1123 | if (INTEL_GEN(dev_priv) <= 8) |
22606a18 | 1124 | hsw_ddi_clock_get(encoder, pipe_config); |
b976dc53 | 1125 | else if (IS_GEN9_BC(dev_priv)) |
22606a18 | 1126 | skl_ddi_clock_get(encoder, pipe_config); |
cc3f90f0 | 1127 | else if (IS_GEN9_LP(dev_priv)) |
977bb38d | 1128 | bxt_ddi_clock_get(encoder, pipe_config); |
3d51278a DV |
1129 | } |
1130 | ||
0220ab6e | 1131 | static bool |
d664c0ce | 1132 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 1133 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1134 | struct intel_encoder *intel_encoder) |
6441ab5f | 1135 | { |
daedf20a | 1136 | struct intel_shared_dpll *pll; |
6441ab5f | 1137 | |
9d16da65 ACO |
1138 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, |
1139 | intel_encoder); | |
1140 | if (!pll) | |
1141 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1142 | pipe_name(intel_crtc->pipe)); | |
1143 | ||
1144 | return pll; | |
6441ab5f PZ |
1145 | } |
1146 | ||
82d35437 S |
1147 | static bool |
1148 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1149 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1150 | struct intel_encoder *intel_encoder) |
82d35437 S |
1151 | { |
1152 | struct intel_shared_dpll *pll; | |
82d35437 | 1153 | |
daedf20a | 1154 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
82d35437 S |
1155 | if (pll == NULL) { |
1156 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1157 | pipe_name(intel_crtc->pipe)); | |
1158 | return false; | |
1159 | } | |
1160 | ||
82d35437 S |
1161 | return true; |
1162 | } | |
0220ab6e | 1163 | |
d683f3bc S |
1164 | static bool |
1165 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1166 | struct intel_crtc_state *crtc_state, | |
96f3f1f9 | 1167 | struct intel_encoder *intel_encoder) |
d683f3bc | 1168 | { |
34177c24 | 1169 | return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
d683f3bc S |
1170 | } |
1171 | ||
0220ab6e DL |
1172 | /* |
1173 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1174 | * intel_crtc->ddi_pll_sel. | |
1175 | * | |
1176 | * For private DPLLs, compute_config() should do the selection for us. This | |
1177 | * function should be folded into compute_config() eventually. | |
1178 | */ | |
190f68c5 ACO |
1179 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1180 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1181 | { |
0853723b | 1182 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
d0737e1d | 1183 | struct intel_encoder *intel_encoder = |
3165c074 | 1184 | intel_ddi_get_crtc_new_encoder(crtc_state); |
0220ab6e | 1185 | |
b976dc53 | 1186 | if (IS_GEN9_BC(dev_priv)) |
190f68c5 | 1187 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1188 | intel_encoder); |
cc3f90f0 | 1189 | else if (IS_GEN9_LP(dev_priv)) |
d683f3bc | 1190 | return bxt_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1191 | intel_encoder); |
82d35437 | 1192 | else |
190f68c5 | 1193 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1194 | intel_encoder); |
0220ab6e DL |
1195 | } |
1196 | ||
dae84799 PZ |
1197 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1198 | { | |
fac5e23e | 1199 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
dae84799 PZ |
1200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1201 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1202 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1203 | int type = intel_encoder->type; |
1204 | uint32_t temp; | |
1205 | ||
cca0502b | 1206 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
4d1de975 JN |
1207 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
1208 | ||
c9809791 | 1209 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1210 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1211 | case 18: |
c9809791 | 1212 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1213 | break; |
1214 | case 24: | |
c9809791 | 1215 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1216 | break; |
1217 | case 30: | |
c9809791 | 1218 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1219 | break; |
1220 | case 36: | |
c9809791 | 1221 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1222 | break; |
1223 | default: | |
4e53c2e0 | 1224 | BUG(); |
dae84799 | 1225 | } |
c9809791 | 1226 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1227 | } |
1228 | } | |
1229 | ||
0e32b39c DA |
1230 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1231 | { | |
1232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1233 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 1234 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1235 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1236 | uint32_t temp; |
1237 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1238 | if (state == true) | |
1239 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1240 | else | |
1241 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1242 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1243 | } | |
1244 | ||
8228c251 | 1245 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1246 | { |
1247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1248 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
c7670b10 | 1249 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1250 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d9ddbcb | 1251 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1252 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1253 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1254 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1255 | uint32_t temp; |
1256 | ||
ad80a810 PZ |
1257 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1258 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1259 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1260 | |
6e3c9717 | 1261 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1262 | case 18: |
ad80a810 | 1263 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1264 | break; |
1265 | case 24: | |
ad80a810 | 1266 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1267 | break; |
1268 | case 30: | |
ad80a810 | 1269 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1270 | break; |
1271 | case 36: | |
ad80a810 | 1272 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1273 | break; |
1274 | default: | |
4e53c2e0 | 1275 | BUG(); |
dfcef252 | 1276 | } |
72662e10 | 1277 | |
6e3c9717 | 1278 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1279 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1280 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1281 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1282 | |
e6f0bfc4 PZ |
1283 | if (cpu_transcoder == TRANSCODER_EDP) { |
1284 | switch (pipe) { | |
1285 | case PIPE_A: | |
c7670b10 PZ |
1286 | /* On Haswell, can only use the always-on power well for |
1287 | * eDP when not using the panel fitter, and when not | |
1288 | * using motion blur mitigation (which we don't | |
1289 | * support). */ | |
772c2a51 | 1290 | if (IS_HASWELL(dev_priv) && |
6e3c9717 ACO |
1291 | (intel_crtc->config->pch_pfit.enabled || |
1292 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1293 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1294 | else | |
1295 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1296 | break; |
1297 | case PIPE_B: | |
1298 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1299 | break; | |
1300 | case PIPE_C: | |
1301 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1302 | break; | |
1303 | default: | |
1304 | BUG(); | |
1305 | break; | |
1306 | } | |
1307 | } | |
1308 | ||
7739c33b | 1309 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1310 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1311 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1312 | else |
ad80a810 | 1313 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
7739c33b | 1314 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1315 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1316 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
cca0502b | 1317 | } else if (type == INTEL_OUTPUT_DP || |
7739c33b | 1318 | type == INTEL_OUTPUT_EDP) { |
64ee2fd2 | 1319 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
90a6b7b0 | 1320 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
0e32b39c | 1321 | } else if (type == INTEL_OUTPUT_DP_MST) { |
64ee2fd2 | 1322 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
90a6b7b0 | 1323 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
8d9ddbcb | 1324 | } else { |
84f44ce7 VS |
1325 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1326 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1327 | } |
1328 | ||
ad80a810 | 1329 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1330 | } |
72662e10 | 1331 | |
ad80a810 PZ |
1332 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1333 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1334 | { |
f0f59a00 | 1335 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1336 | uint32_t val = I915_READ(reg); |
1337 | ||
0e32b39c | 1338 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1339 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1340 | I915_WRITE(reg, val); |
72662e10 ED |
1341 | } |
1342 | ||
bcbc889b PZ |
1343 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1344 | { | |
1345 | struct drm_device *dev = intel_connector->base.dev; | |
fac5e23e | 1346 | struct drm_i915_private *dev_priv = to_i915(dev); |
bcbc889b PZ |
1347 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
1348 | int type = intel_connector->base.connector_type; | |
1349 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1350 | enum pipe pipe = 0; | |
1351 | enum transcoder cpu_transcoder; | |
882244a3 | 1352 | enum intel_display_power_domain power_domain; |
bcbc889b | 1353 | uint32_t tmp; |
e27daab4 | 1354 | bool ret; |
bcbc889b | 1355 | |
882244a3 | 1356 | power_domain = intel_display_port_power_domain(intel_encoder); |
e27daab4 | 1357 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1358 | return false; |
1359 | ||
e27daab4 ID |
1360 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1361 | ret = false; | |
1362 | goto out; | |
1363 | } | |
bcbc889b PZ |
1364 | |
1365 | if (port == PORT_A) | |
1366 | cpu_transcoder = TRANSCODER_EDP; | |
1367 | else | |
1a240d4d | 1368 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1369 | |
1370 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1371 | ||
1372 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1373 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1374 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
1375 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1376 | break; | |
bcbc889b PZ |
1377 | |
1378 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
1379 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1380 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
1381 | break; | |
1382 | ||
0e32b39c DA |
1383 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1384 | /* if the transcoder is in MST state then | |
1385 | * connector isn't connected */ | |
e27daab4 ID |
1386 | ret = false; |
1387 | break; | |
bcbc889b PZ |
1388 | |
1389 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
1390 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1391 | break; | |
bcbc889b PZ |
1392 | |
1393 | default: | |
e27daab4 ID |
1394 | ret = false; |
1395 | break; | |
bcbc889b | 1396 | } |
e27daab4 ID |
1397 | |
1398 | out: | |
1399 | intel_display_power_put(dev_priv, power_domain); | |
1400 | ||
1401 | return ret; | |
bcbc889b PZ |
1402 | } |
1403 | ||
85234cdc DV |
1404 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1405 | enum pipe *pipe) | |
1406 | { | |
1407 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1408 | struct drm_i915_private *dev_priv = to_i915(dev); |
fe43d3f5 | 1409 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1410 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1411 | u32 tmp; |
1412 | int i; | |
e27daab4 | 1413 | bool ret; |
85234cdc | 1414 | |
6d129bea | 1415 | power_domain = intel_display_port_power_domain(encoder); |
e27daab4 | 1416 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
1417 | return false; |
1418 | ||
e27daab4 ID |
1419 | ret = false; |
1420 | ||
fe43d3f5 | 1421 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1422 | |
1423 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
e27daab4 | 1424 | goto out; |
85234cdc | 1425 | |
ad80a810 PZ |
1426 | if (port == PORT_A) { |
1427 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1428 | |
ad80a810 PZ |
1429 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1430 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1431 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1432 | *pipe = PIPE_A; | |
1433 | break; | |
1434 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1435 | *pipe = PIPE_B; | |
1436 | break; | |
1437 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1438 | *pipe = PIPE_C; | |
1439 | break; | |
1440 | } | |
1441 | ||
e27daab4 | 1442 | ret = true; |
ad80a810 | 1443 | |
e27daab4 ID |
1444 | goto out; |
1445 | } | |
0e32b39c | 1446 | |
e27daab4 ID |
1447 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
1448 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1449 | ||
1450 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { | |
1451 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == | |
1452 | TRANS_DDI_MODE_SELECT_DP_MST) | |
1453 | goto out; | |
1454 | ||
1455 | *pipe = i; | |
1456 | ret = true; | |
1457 | ||
1458 | goto out; | |
85234cdc DV |
1459 | } |
1460 | } | |
1461 | ||
84f44ce7 | 1462 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1463 | |
e27daab4 | 1464 | out: |
cc3f90f0 | 1465 | if (ret && IS_GEN9_LP(dev_priv)) { |
e93da0a0 ID |
1466 | tmp = I915_READ(BXT_PHY_CTL(port)); |
1467 | if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK | | |
1468 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) | |
1469 | DRM_ERROR("Port %c enabled but PHY powered down? " | |
1470 | "(PHY_CTL %08x)\n", port_name(port), tmp); | |
1471 | } | |
1472 | ||
e27daab4 ID |
1473 | intel_display_power_put(dev_priv, power_domain); |
1474 | ||
1475 | return ret; | |
85234cdc DV |
1476 | } |
1477 | ||
fc914639 PZ |
1478 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1479 | { | |
1480 | struct drm_crtc *crtc = &intel_crtc->base; | |
7d4aefd0 | 1481 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1482 | struct drm_i915_private *dev_priv = to_i915(dev); |
fc914639 PZ |
1483 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1484 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 1485 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1486 | |
bb523fc0 PZ |
1487 | if (cpu_transcoder != TRANSCODER_EDP) |
1488 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1489 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1490 | } |
1491 | ||
1492 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1493 | { | |
fac5e23e | 1494 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
6e3c9717 | 1495 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1496 | |
bb523fc0 PZ |
1497 | if (cpu_transcoder != TRANSCODER_EDP) |
1498 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1499 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1500 | } |
1501 | ||
a7d8dbc0 VS |
1502 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
1503 | enum port port, uint8_t iboost) | |
f8896f5d | 1504 | { |
a7d8dbc0 VS |
1505 | u32 tmp; |
1506 | ||
1507 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
1508 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); | |
1509 | if (iboost) | |
1510 | tmp |= iboost << BALANCE_LEG_SHIFT(port); | |
1511 | else | |
1512 | tmp |= BALANCE_LEG_DISABLE(port); | |
1513 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); | |
1514 | } | |
1515 | ||
1516 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) | |
1517 | { | |
1518 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
1519 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
1520 | enum port port = intel_dig_port->port; | |
1521 | int type = encoder->type; | |
f8896f5d DW |
1522 | const struct ddi_buf_trans *ddi_translations; |
1523 | uint8_t iboost; | |
75067dde | 1524 | uint8_t dp_iboost, hdmi_iboost; |
f8896f5d | 1525 | int n_entries; |
f8896f5d | 1526 | |
75067dde AK |
1527 | /* VBT may override standard boost values */ |
1528 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
1529 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
1530 | ||
cca0502b | 1531 | if (type == INTEL_OUTPUT_DP) { |
75067dde AK |
1532 | if (dp_iboost) { |
1533 | iboost = dp_iboost; | |
1534 | } else { | |
0fdd4918 RV |
1535 | if (IS_KABYLAKE(dev_priv)) |
1536 | ddi_translations = kbl_get_buf_trans_dp(dev_priv, | |
1537 | &n_entries); | |
1538 | else | |
1539 | ddi_translations = skl_get_buf_trans_dp(dev_priv, | |
1540 | &n_entries); | |
e4d4c05b | 1541 | iboost = ddi_translations[level].i_boost; |
75067dde | 1542 | } |
f8896f5d | 1543 | } else if (type == INTEL_OUTPUT_EDP) { |
75067dde AK |
1544 | if (dp_iboost) { |
1545 | iboost = dp_iboost; | |
1546 | } else { | |
78ab0bae | 1547 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
10afa0b6 VS |
1548 | |
1549 | if (WARN_ON(port != PORT_A && | |
1550 | port != PORT_E && n_entries > 9)) | |
1551 | n_entries = 9; | |
1552 | ||
e4d4c05b | 1553 | iboost = ddi_translations[level].i_boost; |
75067dde | 1554 | } |
f8896f5d | 1555 | } else if (type == INTEL_OUTPUT_HDMI) { |
75067dde AK |
1556 | if (hdmi_iboost) { |
1557 | iboost = hdmi_iboost; | |
1558 | } else { | |
78ab0bae | 1559 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
e4d4c05b | 1560 | iboost = ddi_translations[level].i_boost; |
75067dde | 1561 | } |
f8896f5d DW |
1562 | } else { |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | /* Make sure that the requested I_boost is valid */ | |
1567 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
1568 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
1569 | return; | |
1570 | } | |
1571 | ||
a7d8dbc0 | 1572 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
f8896f5d | 1573 | |
a7d8dbc0 VS |
1574 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
1575 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); | |
f8896f5d DW |
1576 | } |
1577 | ||
78ab0bae VS |
1578 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
1579 | u32 level, enum port port, int type) | |
96fb9f9b | 1580 | { |
96fb9f9b VK |
1581 | const struct bxt_ddi_buf_trans *ddi_translations; |
1582 | u32 n_entries, i; | |
96fb9f9b | 1583 | |
06411f08 | 1584 | if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { |
d9d7000d SJ |
1585 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
1586 | ddi_translations = bxt_ddi_translations_edp; | |
cca0502b | 1587 | } else if (type == INTEL_OUTPUT_DP |
d9d7000d | 1588 | || type == INTEL_OUTPUT_EDP) { |
96fb9f9b VK |
1589 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
1590 | ddi_translations = bxt_ddi_translations_dp; | |
1591 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1592 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
1593 | ddi_translations = bxt_ddi_translations_hdmi; | |
1594 | } else { | |
1595 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", | |
1596 | type); | |
1597 | return; | |
1598 | } | |
1599 | ||
1600 | /* Check if default value has to be used */ | |
1601 | if (level >= n_entries || | |
1602 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { | |
1603 | for (i = 0; i < n_entries; i++) { | |
1604 | if (ddi_translations[i].default_index) { | |
1605 | level = i; | |
1606 | break; | |
1607 | } | |
1608 | } | |
1609 | } | |
1610 | ||
b6e08203 ACO |
1611 | bxt_ddi_phy_set_signal_level(dev_priv, port, |
1612 | ddi_translations[level].margin, | |
1613 | ddi_translations[level].scale, | |
1614 | ddi_translations[level].enable, | |
1615 | ddi_translations[level].deemphasis); | |
96fb9f9b VK |
1616 | } |
1617 | ||
ffe5111e VS |
1618 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) |
1619 | { | |
1620 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1621 | int n_entries; | |
1622 | ||
1623 | if (encoder->type == INTEL_OUTPUT_EDP) | |
1624 | intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); | |
1625 | else | |
1626 | intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); | |
1627 | ||
1628 | if (WARN_ON(n_entries < 1)) | |
1629 | n_entries = 1; | |
1630 | if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) | |
1631 | n_entries = ARRAY_SIZE(index_to_dp_signal_levels); | |
1632 | ||
1633 | return index_to_dp_signal_levels[n_entries - 1] & | |
1634 | DP_TRAIN_VOLTAGE_SWING_MASK; | |
1635 | } | |
1636 | ||
f8896f5d DW |
1637 | static uint32_t translate_signal_level(int signal_levels) |
1638 | { | |
97eeb872 | 1639 | int i; |
f8896f5d | 1640 | |
97eeb872 VS |
1641 | for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { |
1642 | if (index_to_dp_signal_levels[i] == signal_levels) | |
1643 | return i; | |
f8896f5d DW |
1644 | } |
1645 | ||
97eeb872 VS |
1646 | WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
1647 | signal_levels); | |
1648 | ||
1649 | return 0; | |
f8896f5d DW |
1650 | } |
1651 | ||
1652 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) | |
1653 | { | |
1654 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 1655 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d DW |
1656 | struct intel_encoder *encoder = &dport->base; |
1657 | uint8_t train_set = intel_dp->train_set[0]; | |
1658 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
1659 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1660 | enum port port = dport->port; | |
1661 | uint32_t level; | |
1662 | ||
1663 | level = translate_signal_level(signal_levels); | |
1664 | ||
b976dc53 | 1665 | if (IS_GEN9_BC(dev_priv)) |
a7d8dbc0 | 1666 | skl_ddi_set_iboost(encoder, level); |
cc3f90f0 | 1667 | else if (IS_GEN9_LP(dev_priv)) |
78ab0bae | 1668 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); |
f8896f5d DW |
1669 | |
1670 | return DDI_BUF_TRANS_SELECT(level); | |
1671 | } | |
1672 | ||
e404ba8d | 1673 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
c856052a | 1674 | struct intel_shared_dpll *pll) |
6441ab5f | 1675 | { |
e404ba8d VS |
1676 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1677 | enum port port = intel_ddi_get_encoder_port(encoder); | |
6441ab5f | 1678 | |
c856052a ACO |
1679 | if (WARN_ON(!pll)) |
1680 | return; | |
1681 | ||
b976dc53 | 1682 | if (IS_GEN9_BC(dev_priv)) { |
efa80add S |
1683 | uint32_t val; |
1684 | ||
5416d871 | 1685 | /* DDI -> PLL mapping */ |
efa80add S |
1686 | val = I915_READ(DPLL_CTRL2); |
1687 | ||
1688 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
1689 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
c856052a | 1690 | val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) | |
efa80add S |
1691 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
1692 | ||
1693 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 1694 | |
e404ba8d | 1695 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
c856052a | 1696 | I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); |
efa80add | 1697 | } |
e404ba8d VS |
1698 | } |
1699 | ||
ba88d153 MN |
1700 | static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, |
1701 | int link_rate, uint32_t lane_count, | |
1702 | struct intel_shared_dpll *pll, | |
1703 | bool link_mst) | |
e404ba8d | 1704 | { |
ba88d153 MN |
1705 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1706 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1707 | enum port port = intel_ddi_get_encoder_port(encoder); | |
b2ccb822 | 1708 | |
ba88d153 MN |
1709 | intel_dp_set_link_params(intel_dp, link_rate, lane_count, |
1710 | link_mst); | |
1711 | if (encoder->type == INTEL_OUTPUT_EDP) | |
e404ba8d | 1712 | intel_edp_panel_on(intel_dp); |
32bdc400 | 1713 | |
ba88d153 MN |
1714 | intel_ddi_clk_select(encoder, pll); |
1715 | intel_prepare_dp_ddi_buffers(encoder); | |
1716 | intel_ddi_init_dp_buf_reg(encoder); | |
1717 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1718 | intel_dp_start_link_train(intel_dp); | |
1719 | if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) | |
1720 | intel_dp_stop_link_train(intel_dp); | |
1721 | } | |
901c2daf | 1722 | |
ba88d153 MN |
1723 | static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, |
1724 | bool has_hdmi_sink, | |
ac240288 ML |
1725 | const struct intel_crtc_state *crtc_state, |
1726 | const struct drm_connector_state *conn_state, | |
ba88d153 MN |
1727 | struct intel_shared_dpll *pll) |
1728 | { | |
1729 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1730 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1731 | struct drm_encoder *drm_encoder = &encoder->base; | |
1732 | enum port port = intel_ddi_get_encoder_port(encoder); | |
1733 | int level = intel_ddi_hdmi_level(dev_priv, port); | |
c19b0669 | 1734 | |
ba88d153 MN |
1735 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1736 | intel_ddi_clk_select(encoder, pll); | |
1737 | intel_prepare_hdmi_ddi_buffers(encoder); | |
b976dc53 | 1738 | if (IS_GEN9_BC(dev_priv)) |
ba88d153 | 1739 | skl_ddi_set_iboost(encoder, level); |
cc3f90f0 | 1740 | else if (IS_GEN9_LP(dev_priv)) |
ba88d153 MN |
1741 | bxt_ddi_vswing_sequence(dev_priv, level, port, |
1742 | INTEL_OUTPUT_HDMI); | |
8d8bb85e | 1743 | |
ba88d153 MN |
1744 | intel_hdmi->set_infoframes(drm_encoder, |
1745 | has_hdmi_sink, | |
ac240288 | 1746 | crtc_state, conn_state); |
ba88d153 | 1747 | } |
32bdc400 | 1748 | |
ba88d153 MN |
1749 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder, |
1750 | struct intel_crtc_state *pipe_config, | |
1751 | struct drm_connector_state *conn_state) | |
1752 | { | |
1753 | struct drm_encoder *encoder = &intel_encoder->base; | |
1754 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
1755 | int type = intel_encoder->type; | |
30cf6db8 | 1756 | |
ba88d153 MN |
1757 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
1758 | intel_ddi_pre_enable_dp(intel_encoder, | |
1759 | crtc->config->port_clock, | |
1760 | crtc->config->lane_count, | |
1761 | crtc->config->shared_dpll, | |
1762 | intel_crtc_has_type(crtc->config, | |
1763 | INTEL_OUTPUT_DP_MST)); | |
1764 | } | |
1765 | if (type == INTEL_OUTPUT_HDMI) { | |
1766 | intel_ddi_pre_enable_hdmi(intel_encoder, | |
ac240288 ML |
1767 | pipe_config->has_hdmi_sink, |
1768 | pipe_config, conn_state, | |
ba88d153 | 1769 | crtc->config->shared_dpll); |
c19b0669 | 1770 | } |
6441ab5f PZ |
1771 | } |
1772 | ||
fd6bbda9 ML |
1773 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, |
1774 | struct intel_crtc_state *old_crtc_state, | |
1775 | struct drm_connector_state *old_conn_state) | |
6441ab5f PZ |
1776 | { |
1777 | struct drm_encoder *encoder = &intel_encoder->base; | |
66478475 | 1778 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6441ab5f | 1779 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1780 | int type = intel_encoder->type; |
2886e93f | 1781 | uint32_t val; |
a836bdf9 | 1782 | bool wait = false; |
2886e93f | 1783 | |
fd6bbda9 ML |
1784 | /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ |
1785 | ||
2886e93f PZ |
1786 | val = I915_READ(DDI_BUF_CTL(port)); |
1787 | if (val & DDI_BUF_CTL_ENABLE) { | |
1788 | val &= ~DDI_BUF_CTL_ENABLE; | |
1789 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1790 | wait = true; |
2886e93f | 1791 | } |
6441ab5f | 1792 | |
a836bdf9 PZ |
1793 | val = I915_READ(DP_TP_CTL(port)); |
1794 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1795 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1796 | I915_WRITE(DP_TP_CTL(port), val); | |
1797 | ||
1798 | if (wait) | |
1799 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1800 | ||
cca0502b | 1801 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1802 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1803 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1804 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1805 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1806 | } |
1807 | ||
b976dc53 | 1808 | if (IS_GEN9_BC(dev_priv)) |
efa80add S |
1809 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
1810 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
66478475 | 1811 | else if (INTEL_GEN(dev_priv) < 9) |
efa80add | 1812 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
b2ccb822 VS |
1813 | |
1814 | if (type == INTEL_OUTPUT_HDMI) { | |
1815 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1816 | ||
1817 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
1818 | } | |
6441ab5f PZ |
1819 | } |
1820 | ||
b7076546 ML |
1821 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
1822 | struct intel_crtc_state *old_crtc_state, | |
1823 | struct drm_connector_state *old_conn_state) | |
1824 | { | |
1825 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); | |
1826 | uint32_t val; | |
1827 | ||
1828 | /* | |
1829 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) | |
1830 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, | |
1831 | * step 13 is the correct place for it. Step 18 is where it was | |
1832 | * originally before the BUN. | |
1833 | */ | |
1834 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1835 | val &= ~FDI_RX_ENABLE; | |
1836 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1837 | ||
1838 | intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state); | |
1839 | ||
1840 | val = I915_READ(FDI_RX_MISC(PIPE_A)); | |
1841 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1842 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1843 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); | |
1844 | ||
1845 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1846 | val &= ~FDI_PCDCLK; | |
1847 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1848 | ||
1849 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1850 | val &= ~FDI_RX_PLL_ENABLE; | |
1851 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1852 | } | |
1853 | ||
fd6bbda9 ML |
1854 | static void intel_enable_ddi(struct intel_encoder *intel_encoder, |
1855 | struct intel_crtc_state *pipe_config, | |
1856 | struct drm_connector_state *conn_state) | |
72662e10 | 1857 | { |
6547fef8 | 1858 | struct drm_encoder *encoder = &intel_encoder->base; |
66478475 | 1859 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6547fef8 PZ |
1860 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1861 | int type = intel_encoder->type; | |
72662e10 | 1862 | |
6547fef8 | 1863 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1864 | struct intel_digital_port *intel_dig_port = |
1865 | enc_to_dig_port(encoder); | |
1866 | ||
6547fef8 PZ |
1867 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1868 | * are ignored so nothing special needs to be done besides | |
1869 | * enabling the port. | |
1870 | */ | |
876a8cdf | 1871 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1872 | intel_dig_port->saved_port_bits | |
1873 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1874 | } else if (type == INTEL_OUTPUT_EDP) { |
1875 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1876 | ||
66478475 | 1877 | if (port == PORT_A && INTEL_GEN(dev_priv) < 9) |
3ab9c637 ID |
1878 | intel_dp_stop_link_train(intel_dp); |
1879 | ||
4be73780 | 1880 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 1881 | intel_psr_enable(intel_dp); |
85cb48a1 | 1882 | intel_edp_drrs_enable(intel_dp, pipe_config); |
6547fef8 | 1883 | } |
7b9f35a6 | 1884 | |
37255d8d | 1885 | if (pipe_config->has_audio) |
bbf35e9d | 1886 | intel_audio_codec_enable(intel_encoder, pipe_config, conn_state); |
5ab432ef DV |
1887 | } |
1888 | ||
fd6bbda9 ML |
1889 | static void intel_disable_ddi(struct intel_encoder *intel_encoder, |
1890 | struct intel_crtc_state *old_crtc_state, | |
1891 | struct drm_connector_state *old_conn_state) | |
5ab432ef | 1892 | { |
d6c50ff8 PZ |
1893 | struct drm_encoder *encoder = &intel_encoder->base; |
1894 | int type = intel_encoder->type; | |
1895 | ||
37255d8d | 1896 | if (old_crtc_state->has_audio) |
69bfe1a9 | 1897 | intel_audio_codec_disable(intel_encoder); |
2831d842 | 1898 | |
d6c50ff8 PZ |
1899 | if (type == INTEL_OUTPUT_EDP) { |
1900 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1901 | ||
85cb48a1 | 1902 | intel_edp_drrs_disable(intel_dp, old_crtc_state); |
0bc12bcb | 1903 | intel_psr_disable(intel_dp); |
4be73780 | 1904 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1905 | } |
72662e10 | 1906 | } |
79f689aa | 1907 | |
fd6bbda9 ML |
1908 | static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, |
1909 | struct intel_crtc_state *pipe_config, | |
1910 | struct drm_connector_state *conn_state) | |
95a7a2ae | 1911 | { |
95a7a2ae | 1912 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
47a6bc61 | 1913 | uint8_t mask = intel_crtc->config->lane_lat_optim_mask; |
95a7a2ae | 1914 | |
47a6bc61 | 1915 | bxt_ddi_phy_set_lane_optim_mask(encoder, mask); |
95a7a2ae ID |
1916 | } |
1917 | ||
ad64217b | 1918 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 1919 | { |
ad64217b ACO |
1920 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1921 | struct drm_i915_private *dev_priv = | |
1922 | to_i915(intel_dig_port->base.base.dev); | |
174edf1f | 1923 | enum port port = intel_dig_port->port; |
c19b0669 | 1924 | uint32_t val; |
f3e227df | 1925 | bool wait = false; |
c19b0669 PZ |
1926 | |
1927 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1928 | val = I915_READ(DDI_BUF_CTL(port)); | |
1929 | if (val & DDI_BUF_CTL_ENABLE) { | |
1930 | val &= ~DDI_BUF_CTL_ENABLE; | |
1931 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1932 | wait = true; | |
1933 | } | |
1934 | ||
1935 | val = I915_READ(DP_TP_CTL(port)); | |
1936 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1937 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1938 | I915_WRITE(DP_TP_CTL(port), val); | |
1939 | POSTING_READ(DP_TP_CTL(port)); | |
1940 | ||
1941 | if (wait) | |
1942 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1943 | } | |
1944 | ||
0e32b39c | 1945 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 1946 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
64ee2fd2 | 1947 | if (intel_dp->link_mst) |
0e32b39c DA |
1948 | val |= DP_TP_CTL_MODE_MST; |
1949 | else { | |
1950 | val |= DP_TP_CTL_MODE_SST; | |
1951 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1952 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1953 | } | |
c19b0669 PZ |
1954 | I915_WRITE(DP_TP_CTL(port), val); |
1955 | POSTING_READ(DP_TP_CTL(port)); | |
1956 | ||
1957 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1958 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1959 | POSTING_READ(DDI_BUF_CTL(port)); | |
1960 | ||
1961 | udelay(600); | |
1962 | } | |
00c09d70 | 1963 | |
9935f7fa LY |
1964 | bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
1965 | struct intel_crtc *intel_crtc) | |
1966 | { | |
1967 | u32 temp; | |
1968 | ||
1969 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { | |
1970 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1971 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) | |
1972 | return true; | |
1973 | } | |
1974 | return false; | |
1975 | } | |
1976 | ||
6801c18c | 1977 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1978 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1979 | { |
fac5e23e | 1980 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 | 1981 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
0cb09a97 | 1982 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 1983 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
1984 | u32 temp, flags = 0; |
1985 | ||
4d1de975 JN |
1986 | /* XXX: DSI transcoder paranoia */ |
1987 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) | |
1988 | return; | |
1989 | ||
045ac3b5 JB |
1990 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1991 | if (temp & TRANS_DDI_PHSYNC) | |
1992 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1993 | else | |
1994 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1995 | if (temp & TRANS_DDI_PVSYNC) | |
1996 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1997 | else | |
1998 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1999 | ||
2d112de7 | 2000 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2001 | |
2002 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2003 | case TRANS_DDI_BPC_6: | |
2004 | pipe_config->pipe_bpp = 18; | |
2005 | break; | |
2006 | case TRANS_DDI_BPC_8: | |
2007 | pipe_config->pipe_bpp = 24; | |
2008 | break; | |
2009 | case TRANS_DDI_BPC_10: | |
2010 | pipe_config->pipe_bpp = 30; | |
2011 | break; | |
2012 | case TRANS_DDI_BPC_12: | |
2013 | pipe_config->pipe_bpp = 36; | |
2014 | break; | |
2015 | default: | |
2016 | break; | |
2017 | } | |
eb14cb74 VS |
2018 | |
2019 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2020 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2021 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
2022 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2023 | ||
cda0aaaf | 2024 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
bbd440fb | 2025 | pipe_config->has_infoframe = true; |
d4d6279a | 2026 | /* fall through */ |
eb14cb74 | 2027 | case TRANS_DDI_MODE_SELECT_DVI: |
d4d6279a ACO |
2028 | pipe_config->lane_count = 4; |
2029 | break; | |
eb14cb74 VS |
2030 | case TRANS_DDI_MODE_SELECT_FDI: |
2031 | break; | |
2032 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2033 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
90a6b7b0 VS |
2034 | pipe_config->lane_count = |
2035 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
2036 | intel_dp_get_m_n(intel_crtc, pipe_config); |
2037 | break; | |
2038 | default: | |
2039 | break; | |
2040 | } | |
10214420 | 2041 | |
9935f7fa LY |
2042 | pipe_config->has_audio = |
2043 | intel_ddi_is_audio_enabled(dev_priv, intel_crtc); | |
9ed109a7 | 2044 | |
6aa23e65 JN |
2045 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
2046 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
10214420 DV |
2047 | /* |
2048 | * This is a big fat ugly hack. | |
2049 | * | |
2050 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2051 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2052 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2053 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2054 | * max, not what it tells us to use. | |
2055 | * | |
2056 | * Note: This will still be broken if the eDP panel is not lit | |
2057 | * up by the BIOS, and thus we can't get the mode at module | |
2058 | * load. | |
2059 | */ | |
2060 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2061 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2062 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
10214420 | 2063 | } |
11578553 | 2064 | |
22606a18 | 2065 | intel_ddi_clock_get(encoder, pipe_config); |
95a7a2ae | 2066 | |
cc3f90f0 | 2067 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae ID |
2068 | pipe_config->lane_lat_optim_mask = |
2069 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); | |
045ac3b5 JB |
2070 | } |
2071 | ||
5bfe2ac0 | 2072 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
2073 | struct intel_crtc_state *pipe_config, |
2074 | struct drm_connector_state *conn_state) | |
00c09d70 | 2075 | { |
fac5e23e | 2076 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5bfe2ac0 | 2077 | int type = encoder->type; |
eccb140b | 2078 | int port = intel_ddi_get_encoder_port(encoder); |
95a7a2ae | 2079 | int ret; |
00c09d70 | 2080 | |
5bfe2ac0 | 2081 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2082 | |
eccb140b DV |
2083 | if (port == PORT_A) |
2084 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2085 | ||
00c09d70 | 2086 | if (type == INTEL_OUTPUT_HDMI) |
0a478c27 | 2087 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
00c09d70 | 2088 | else |
0a478c27 | 2089 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
95a7a2ae | 2090 | |
cc3f90f0 | 2091 | if (IS_GEN9_LP(dev_priv) && ret) |
95a7a2ae ID |
2092 | pipe_config->lane_lat_optim_mask = |
2093 | bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, | |
b284eeda | 2094 | pipe_config->lane_count); |
95a7a2ae ID |
2095 | |
2096 | return ret; | |
2097 | ||
00c09d70 PZ |
2098 | } |
2099 | ||
2100 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
bf93ba67 ID |
2101 | .reset = intel_dp_encoder_reset, |
2102 | .destroy = intel_dp_encoder_destroy, | |
00c09d70 PZ |
2103 | }; |
2104 | ||
4a28ae58 PZ |
2105 | static struct intel_connector * |
2106 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2107 | { | |
2108 | struct intel_connector *connector; | |
2109 | enum port port = intel_dig_port->port; | |
2110 | ||
9bdbd0b9 | 2111 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2112 | if (!connector) |
2113 | return NULL; | |
2114 | ||
2115 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2116 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2117 | kfree(connector); | |
2118 | return NULL; | |
2119 | } | |
2120 | ||
2121 | return connector; | |
2122 | } | |
2123 | ||
2124 | static struct intel_connector * | |
2125 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2126 | { | |
2127 | struct intel_connector *connector; | |
2128 | enum port port = intel_dig_port->port; | |
2129 | ||
9bdbd0b9 | 2130 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2131 | if (!connector) |
2132 | return NULL; | |
2133 | ||
2134 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2135 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2136 | ||
2137 | return connector; | |
2138 | } | |
2139 | ||
c39055b0 | 2140 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) |
00c09d70 PZ |
2141 | { |
2142 | struct intel_digital_port *intel_dig_port; | |
2143 | struct intel_encoder *intel_encoder; | |
2144 | struct drm_encoder *encoder; | |
ff662124 | 2145 | bool init_hdmi, init_dp, init_lspcon = false; |
10e7bec3 VS |
2146 | int max_lanes; |
2147 | ||
2148 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { | |
2149 | switch (port) { | |
2150 | case PORT_A: | |
2151 | max_lanes = 4; | |
2152 | break; | |
2153 | case PORT_E: | |
2154 | max_lanes = 0; | |
2155 | break; | |
2156 | default: | |
2157 | max_lanes = 4; | |
2158 | break; | |
2159 | } | |
2160 | } else { | |
2161 | switch (port) { | |
2162 | case PORT_A: | |
2163 | max_lanes = 2; | |
2164 | break; | |
2165 | case PORT_E: | |
2166 | max_lanes = 2; | |
2167 | break; | |
2168 | default: | |
2169 | max_lanes = 4; | |
2170 | break; | |
2171 | } | |
2172 | } | |
311a2094 PZ |
2173 | |
2174 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2175 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2176 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
ff662124 SS |
2177 | |
2178 | if (intel_bios_is_lspcon_present(dev_priv, port)) { | |
2179 | /* | |
2180 | * Lspcon device needs to be driven with DP connector | |
2181 | * with special detection sequence. So make sure DP | |
2182 | * is initialized before lspcon. | |
2183 | */ | |
2184 | init_dp = true; | |
2185 | init_lspcon = true; | |
2186 | init_hdmi = false; | |
2187 | DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); | |
2188 | } | |
2189 | ||
311a2094 | 2190 | if (!init_dp && !init_hdmi) { |
500ea70d | 2191 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 2192 | port_name(port)); |
500ea70d | 2193 | return; |
311a2094 | 2194 | } |
00c09d70 | 2195 | |
b14c5679 | 2196 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2197 | if (!intel_dig_port) |
2198 | return; | |
2199 | ||
00c09d70 PZ |
2200 | intel_encoder = &intel_dig_port->base; |
2201 | encoder = &intel_encoder->base; | |
2202 | ||
c39055b0 | 2203 | drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, |
580d8ed5 | 2204 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
00c09d70 | 2205 | |
5bfe2ac0 | 2206 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 | 2207 | intel_encoder->enable = intel_enable_ddi; |
cc3f90f0 | 2208 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae | 2209 | intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; |
00c09d70 PZ |
2210 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
2211 | intel_encoder->disable = intel_disable_ddi; | |
2212 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2213 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2214 | intel_encoder->get_config = intel_ddi_get_config; |
bf93ba67 | 2215 | intel_encoder->suspend = intel_dp_encoder_suspend; |
00c09d70 PZ |
2216 | |
2217 | intel_dig_port->port = port; | |
bcf53de4 SM |
2218 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2219 | (DDI_BUF_PORT_REVERSAL | | |
2220 | DDI_A_4_LANES); | |
00c09d70 | 2221 | |
6c566dc9 MR |
2222 | /* |
2223 | * Bspec says that DDI_A_4_LANES is the only supported configuration | |
2224 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP | |
2225 | * wasn't lit up at boot. Force this bit on in our internal | |
2226 | * configuration so that we use the proper lane count for our | |
2227 | * calculations. | |
2228 | */ | |
cc3f90f0 | 2229 | if (IS_GEN9_LP(dev_priv) && port == PORT_A) { |
6c566dc9 MR |
2230 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
2231 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); | |
2232 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; | |
ed8d60f4 | 2233 | max_lanes = 4; |
6c566dc9 MR |
2234 | } |
2235 | } | |
2236 | ||
ed8d60f4 MR |
2237 | intel_dig_port->max_lanes = max_lanes; |
2238 | ||
00c09d70 | 2239 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
03cdc1d4 | 2240 | intel_encoder->port = port; |
f68d697e | 2241 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2242 | intel_encoder->cloneable = 0; |
00c09d70 | 2243 | |
f68d697e CW |
2244 | if (init_dp) { |
2245 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2246 | goto err; | |
13cf5504 | 2247 | |
f68d697e | 2248 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
ca4c3890 | 2249 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
f68d697e | 2250 | } |
21a8e6a4 | 2251 | |
311a2094 PZ |
2252 | /* In theory we don't need the encoder->type check, but leave it just in |
2253 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2254 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2255 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2256 | goto err; | |
21a8e6a4 | 2257 | } |
f68d697e | 2258 | |
ff662124 SS |
2259 | if (init_lspcon) { |
2260 | if (lspcon_init(intel_dig_port)) | |
2261 | /* TODO: handle hdmi info frame part */ | |
2262 | DRM_DEBUG_KMS("LSPCON init success on port %c\n", | |
2263 | port_name(port)); | |
2264 | else | |
2265 | /* | |
2266 | * LSPCON init faied, but DP init was success, so | |
2267 | * lets try to drive as DP++ port. | |
2268 | */ | |
2269 | DRM_ERROR("LSPCON init failed on port %c\n", | |
2270 | port_name(port)); | |
2271 | } | |
2272 | ||
f68d697e CW |
2273 | return; |
2274 | ||
2275 | err: | |
2276 | drm_encoder_cleanup(encoder); | |
2277 | kfree(intel_dig_port); | |
00c09d70 | 2278 | } |