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drm/i915: Write HDR infoframe and send to panel
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
cfda08cd 32#include "intel_combo_phy.h"
ec7f29ff 33#include "intel_connector.h"
fdc24cf3 34#include "intel_ddi.h"
27fec1f9 35#include "intel_dp.h"
e075094f 36#include "intel_dp_link_training.h"
b1ad4c39 37#include "intel_dpio_phy.h"
45244b87 38#include "intel_drv.h"
1dd07e56 39#include "intel_dsi.h"
8834e365 40#include "intel_fifo_underrun.h"
3ce2ea65 41#include "intel_gmbus.h"
408bd917 42#include "intel_hdcp.h"
0550691d 43#include "intel_hdmi.h"
dbeb38d9 44#include "intel_hotplug.h"
f3e18947 45#include "intel_lspcon.h"
44c1220a 46#include "intel_panel.h"
55367a27 47#include "intel_psr.h"
b375d0ef 48#include "intel_vdsc.h"
45244b87 49
10122051
JN		 50struct ddi_buf_trans {
51 u32 trans1; /* balance leg enable, de-emph level */
52 u32 trans2; /* vref sel, vswing */
f8896f5d 53 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 54};
55
97eeb872
VS		 56static const u8 index_to_dp_signal_levels[] = {
57 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
58 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
59 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
60 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
61 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
62 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
63 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
64 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
65 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
66 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
67};
68
45244b87
ED		 69/* HDMI/DVI modes ignore everything but the last 2 items. So we share
70 * them for both DP and FDI transports, allowing those ports to
71 * automatically adapt to HDMI connections as well
72 */
10122051 73static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 74 { 0x00FFFFFF, 0x0006000E, 0x0 },
75 { 0x00D75FFF, 0x0005000A, 0x0 },
76 { 0x00C30FFF, 0x00040006, 0x0 },
77 { 0x80AAAFFF, 0x000B0000, 0x0 },
78 { 0x00FFFFFF, 0x0005000A, 0x0 },
79 { 0x00D75FFF, 0x000C0004, 0x0 },
80 { 0x80C30FFF, 0x000B0000, 0x0 },
81 { 0x00FFFFFF, 0x00040006, 0x0 },
82 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 83};
84
10122051 85static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 86 { 0x00FFFFFF, 0x0007000E, 0x0 },
87 { 0x00D75FFF, 0x000F000A, 0x0 },
88 { 0x00C30FFF, 0x00060006, 0x0 },
89 { 0x00AAAFFF, 0x001E0000, 0x0 },
90 { 0x00FFFFFF, 0x000F000A, 0x0 },
91 { 0x00D75FFF, 0x00160004, 0x0 },
92 { 0x00C30FFF, 0x001E0000, 0x0 },
93 { 0x00FFFFFF, 0x00060006, 0x0 },
94 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 95};
96
10122051
JN		 97static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
98 /* Idx NT mV d T mV d db */
f8896f5d
DW		 99 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
100 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
101 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
102 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
103 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
104 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
105 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
106 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
107 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
108 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
109 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
110 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 111};
112
10122051 113static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 114 { 0x00FFFFFF, 0x00000012, 0x0 },
115 { 0x00EBAFFF, 0x00020011, 0x0 },
116 { 0x00C71FFF, 0x0006000F, 0x0 },
117 { 0x00AAAFFF, 0x000E000A, 0x0 },
118 { 0x00FFFFFF, 0x00020011, 0x0 },
119 { 0x00DB6FFF, 0x0005000F, 0x0 },
120 { 0x00BEEFFF, 0x000A000C, 0x0 },
121 { 0x00FFFFFF, 0x0005000F, 0x0 },
122 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 123};
124
10122051 125static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 126 { 0x00FFFFFF, 0x0007000E, 0x0 },
127 { 0x00D75FFF, 0x000E000A, 0x0 },
128 { 0x00BEFFFF, 0x00140006, 0x0 },
129 { 0x80B2CFFF, 0x001B0002, 0x0 },
130 { 0x00FFFFFF, 0x000E000A, 0x0 },
131 { 0x00DB6FFF, 0x00160005, 0x0 },
132 { 0x80C71FFF, 0x001A0002, 0x0 },
133 { 0x00F7DFFF, 0x00180004, 0x0 },
134 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 135};
136
10122051 137static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 138 { 0x00FFFFFF, 0x0001000E, 0x0 },
139 { 0x00D75FFF, 0x0004000A, 0x0 },
140 { 0x00C30FFF, 0x00070006, 0x0 },
141 { 0x00AAAFFF, 0x000C0000, 0x0 },
142 { 0x00FFFFFF, 0x0004000A, 0x0 },
143 { 0x00D75FFF, 0x00090004, 0x0 },
144 { 0x00C30FFF, 0x000C0000, 0x0 },
145 { 0x00FFFFFF, 0x00070006, 0x0 },
146 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 147};
148
10122051
JN		 149static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
150 /* Idx NT mV d T mV df db */
f8896f5d
DW		 151 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
152 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
153 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
154 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
155 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
156 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
157 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
158 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
159 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
160 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 161};
162
5f8b2531 163/* Skylake H and S */
7f88e3af 164static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 165 { 0x00002016, 0x000000A0, 0x0 },
166 { 0x00005012, 0x0000009B, 0x0 },
167 { 0x00007011, 0x00000088, 0x0 },
d7097cff 168 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 169 { 0x00002016, 0x0000009B, 0x0 },
170 { 0x00005012, 0x00000088, 0x0 },
d7097cff 171 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 172 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 173 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 174};
175
f8896f5d
DW		 176/* Skylake U */
177static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 178 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 179 { 0x00005012, 0x00000088, 0x0 },
5ac90567 180 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 181 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 182 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 183 { 0x80005012, 0x000000C0, 0x1 },
184 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 185 { 0x00002016, 0x00000088, 0x0 },
d7097cff 186 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 187};
188
5f8b2531
RV		 189/* Skylake Y */
190static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 191 { 0x00000018, 0x000000A2, 0x0 },
192 { 0x00005012, 0x00000088, 0x0 },
5ac90567 193 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 194 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 195 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 196 { 0x80005012, 0x000000C0, 0x3 },
197 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 198 { 0x00000018, 0x00000088, 0x0 },
d7097cff 199 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 200};
201
0fdd4918
RV		 202/* Kabylake H and S */
203static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
204 { 0x00002016, 0x000000A0, 0x0 },
205 { 0x00005012, 0x0000009B, 0x0 },
206 { 0x00007011, 0x00000088, 0x0 },
207 { 0x80009010, 0x000000C0, 0x1 },
208 { 0x00002016, 0x0000009B, 0x0 },
209 { 0x00005012, 0x00000088, 0x0 },
210 { 0x80007011, 0x000000C0, 0x1 },
211 { 0x00002016, 0x00000097, 0x0 },
212 { 0x80005012, 0x000000C0, 0x1 },
213};
214
215/* Kabylake U */
216static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
217 { 0x0000201B, 0x000000A1, 0x0 },
218 { 0x00005012, 0x00000088, 0x0 },
219 { 0x80007011, 0x000000CD, 0x3 },
220 { 0x80009010, 0x000000C0, 0x3 },
221 { 0x0000201B, 0x0000009D, 0x0 },
222 { 0x80005012, 0x000000C0, 0x3 },
223 { 0x80007011, 0x000000C0, 0x3 },
224 { 0x00002016, 0x0000004F, 0x0 },
225 { 0x80005012, 0x000000C0, 0x3 },
226};
227
228/* Kabylake Y */
229static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
230 { 0x00001017, 0x000000A1, 0x0 },
231 { 0x00005012, 0x00000088, 0x0 },
232 { 0x80007011, 0x000000CD, 0x3 },
233 { 0x8000800F, 0x000000C0, 0x3 },
234 { 0x00001017, 0x0000009D, 0x0 },
235 { 0x80005012, 0x000000C0, 0x3 },
236 { 0x80007011, 0x000000C0, 0x3 },
237 { 0x00001017, 0x0000004C, 0x0 },
238 { 0x80005012, 0x000000C0, 0x3 },
239};
240
f8896f5d 241/*
0fdd4918 242 * Skylake/Kabylake H and S
f8896f5d
DW		 243 * eDP 1.4 low vswing translation parameters
244 */
7ad14a29 245static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 246 { 0x00000018, 0x000000A8, 0x0 },
247 { 0x00004013, 0x000000A9, 0x0 },
248 { 0x00007011, 0x000000A2, 0x0 },
249 { 0x00009010, 0x0000009C, 0x0 },
250 { 0x00000018, 0x000000A9, 0x0 },
251 { 0x00006013, 0x000000A2, 0x0 },
252 { 0x00007011, 0x000000A6, 0x0 },
253 { 0x00000018, 0x000000AB, 0x0 },
254 { 0x00007013, 0x0000009F, 0x0 },
255 { 0x00000018, 0x000000DF, 0x0 },
256};
257
258/*
0fdd4918 259 * Skylake/Kabylake U
f8896f5d
DW		 260 * eDP 1.4 low vswing translation parameters
261 */
262static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
263 { 0x00000018, 0x000000A8, 0x0 },
264 { 0x00004013, 0x000000A9, 0x0 },
265 { 0x00007011, 0x000000A2, 0x0 },
266 { 0x00009010, 0x0000009C, 0x0 },
267 { 0x00000018, 0x000000A9, 0x0 },
268 { 0x00006013, 0x000000A2, 0x0 },
269 { 0x00007011, 0x000000A6, 0x0 },
270 { 0x00002016, 0x000000AB, 0x0 },
271 { 0x00005013, 0x0000009F, 0x0 },
272 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 273};
274
f8896f5d 275/*
0fdd4918 276 * Skylake/Kabylake Y
f8896f5d
DW		 277 * eDP 1.4 low vswing translation parameters
278 */
5f8b2531 279static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 280 { 0x00000018, 0x000000A8, 0x0 },
281 { 0x00004013, 0x000000AB, 0x0 },
282 { 0x00007011, 0x000000A4, 0x0 },
283 { 0x00009010, 0x000000DF, 0x0 },
284 { 0x00000018, 0x000000AA, 0x0 },
285 { 0x00006013, 0x000000A4, 0x0 },
286 { 0x00007011, 0x0000009D, 0x0 },
287 { 0x00000018, 0x000000A0, 0x0 },
288 { 0x00006012, 0x000000DF, 0x0 },
289 { 0x00000018, 0x0000008A, 0x0 },
290};
7ad14a29 291
0fdd4918 292/* Skylake/Kabylake U, H and S */
7f88e3af 293static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 294 { 0x00000018, 0x000000AC, 0x0 },
295 { 0x00005012, 0x0000009D, 0x0 },
296 { 0x00007011, 0x00000088, 0x0 },
297 { 0x00000018, 0x000000A1, 0x0 },
298 { 0x00000018, 0x00000098, 0x0 },
299 { 0x00004013, 0x00000088, 0x0 },
2e78416e 300 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 301 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 302 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
303 { 0x80003015, 0x000000C0, 0x1 },
304 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 305};
306
0fdd4918 307/* Skylake/Kabylake Y */
5f8b2531 308static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 309 { 0x00000018, 0x000000A1, 0x0 },
310 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 311 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 312 { 0x00000018, 0x000000A4, 0x0 },
313 { 0x00000018, 0x0000009D, 0x0 },
314 { 0x00004013, 0x00000080, 0x0 },
2e78416e 315 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 316 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 317 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
318 { 0x80003015, 0x000000C0, 0x3 },
319 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 320};
321
96fb9f9b 322struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 323 u8 margin; /* swing value */
324 u8 scale; /* scale value */
325 u8 enable; /* scale enable */
326 u8 deemphasis;
96fb9f9b
VK		 327};
328
96fb9f9b
VK		 329static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
330 /* Idx NT mV diff db */
043eaf36
VS		 331 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
332 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
333 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
334 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
335 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
336 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
337 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
338 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
339 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
340 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 341};
342
d9d7000d
SJ		 343static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
344 /* Idx NT mV diff db */
043eaf36
VS		 345 { 26, 0, 0, 128, }, /* 0: 200 0 */
346 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
347 { 48, 0, 0, 96, }, /* 2: 200 4 */
348 { 54, 0, 0, 69, }, /* 3: 200 6 */
349 { 32, 0, 0, 128, }, /* 4: 250 0 */
350 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
351 { 54, 0, 0, 85, }, /* 6: 250 4 */
352 { 43, 0, 0, 128, }, /* 7: 300 0 */
353 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
354 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 355};
356
96fb9f9b
VK		 357/* BSpec has 2 recommended values - entries 0 and 8.
358 * Using the entry with higher vswing.
359 */
360static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
361 /* Idx NT mV diff db */
043eaf36
VS		 362 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
363 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
364 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
365 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
366 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
367 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
368 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
369 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
370 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
371 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 372};
373
83fb7ab4 374struct cnl_ddi_buf_trans {
fb5f4e96
VS		 375 u8 dw2_swing_sel;
376 u8 dw7_n_scalar;
377 u8 dw4_cursor_coeff;
378 u8 dw4_post_cursor_2;
379 u8 dw4_post_cursor_1;
83fb7ab4
RV		 380};
381
382/* Voltage Swing Programming for VccIO 0.85V for DP */
383static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
384 /* NT mV Trans mV db */
385 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
386 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
387 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
388 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
389 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
390 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
391 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
392 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
393 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
394 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
395};
396
397/* Voltage Swing Programming for VccIO 0.85V for HDMI */
398static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
399 /* NT mV Trans mV db */
400 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
401 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
402 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
403 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
404 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
405 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
406 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
407};
408
409/* Voltage Swing Programming for VccIO 0.85V for eDP */
410static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
411 /* NT mV Trans mV db */
412 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
413 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
414 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
415 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
416 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
417 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
418 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
419 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
420 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
421};
422
423/* Voltage Swing Programming for VccIO 0.95V for DP */
424static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
425 /* NT mV Trans mV db */
426 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
427 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
428 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
429 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
430 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
431 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
432 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
433 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
434 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
435 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
436};
437
438/* Voltage Swing Programming for VccIO 0.95V for HDMI */
439static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
440 /* NT mV Trans mV db */
441 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
442 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
443 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
444 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
445 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
446 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
447 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
448 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
449 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
450 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
451 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
452};
453
454/* Voltage Swing Programming for VccIO 0.95V for eDP */
455static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
456 /* NT mV Trans mV db */
457 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
458 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
459 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
460 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
461 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
462 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
463 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
464 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
465 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
466 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
467};
468
469/* Voltage Swing Programming for VccIO 1.05V for DP */
470static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
471 /* NT mV Trans mV db */
472 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
473 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
474 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
475 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
476 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
477 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
478 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
479 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
480 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
481 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
482};
483
484/* Voltage Swing Programming for VccIO 1.05V for HDMI */
485static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
486 /* NT mV Trans mV db */
487 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
488 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
489 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
490 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
491 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
492 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
493 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
494 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
495 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
496 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
497 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
498};
499
500/* Voltage Swing Programming for VccIO 1.05V for eDP */
501static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
502 /* NT mV Trans mV db */
503 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
504 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
505 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
506 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
507 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
508 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
509 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
510 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
511 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
512};
513
b265a2a6
CT		 514/* icl_combo_phy_ddi_translations */
515static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
516 /* NT mV Trans mV db */
517 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
518 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
519 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
520 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
521 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
522 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
523 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
524 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
525 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
526 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 527};
528
b265a2a6
CT		 529static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
530 /* NT mV Trans mV db */
531 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
532 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
533 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
534 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
535 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
536 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
537 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
538 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
539 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
540 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 541};
542
b265a2a6
CT		 543static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
544 /* NT mV Trans mV db */
545 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
546 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
547 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
548 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
549 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
550 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
551 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
552 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
553 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
554 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 555};
556
b265a2a6
CT		 557static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
558 /* NT mV Trans mV db */
559 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
560 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
561 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
562 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
563 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
564 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
565 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 566};
567
cd96bea7
MN		 568struct icl_mg_phy_ddi_buf_trans {
569 u32 cri_txdeemph_override_5_0;
570 u32 cri_txdeemph_override_11_6;
571 u32 cri_txdeemph_override_17_12;
572};
573
574static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
575 /* Voltage swing pre-emphasis */
576 { 0x0, 0x1B, 0x00 }, /* 0 0 */
577 { 0x0, 0x23, 0x08 }, /* 0 1 */
578 { 0x0, 0x2D, 0x12 }, /* 0 2 */
579 { 0x0, 0x00, 0x00 }, /* 0 3 */
580 { 0x0, 0x23, 0x00 }, /* 1 0 */
581 { 0x0, 0x2B, 0x09 }, /* 1 1 */
582 { 0x0, 0x2E, 0x11 }, /* 1 2 */
583 { 0x0, 0x2F, 0x00 }, /* 2 0 */
584 { 0x0, 0x33, 0x0C }, /* 2 1 */
585 { 0x0, 0x00, 0x00 }, /* 3 0 */
586};
587
a930acd9
VS		 588static const struct ddi_buf_trans *
589bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
590{
591 if (dev_priv->vbt.edp.low_vswing) {
592 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
593 return bdw_ddi_translations_edp;
594 } else {
595 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
596 return bdw_ddi_translations_dp;
597 }
598}
599
acee2998 600static const struct ddi_buf_trans *
78ab0bae 601skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 602{
0fdd4918 603 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 604 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 605 return skl_y_ddi_translations_dp;
0fdd4918 606 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 607 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 608 return skl_u_ddi_translations_dp;
f8896f5d 609 } else {
f8896f5d 610 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 611 return skl_ddi_translations_dp;
f8896f5d 612 }
f8896f5d
DW		 613}
614
0fdd4918
RV		 615static const struct ddi_buf_trans *
616kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
617{
dfdaa566 618 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
0fdd4918
RV		 619 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
620 return kbl_y_ddi_translations_dp;
da411a48 621 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 622 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
623 return kbl_u_ddi_translations_dp;
624 } else {
625 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
626 return kbl_ddi_translations_dp;
627 }
628}
629
acee2998 630static const struct ddi_buf_trans *
78ab0bae 631skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 632{
06411f08 633 if (dev_priv->vbt.edp.low_vswing) {
dfdaa566 634 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 635 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 636 return skl_y_ddi_translations_edp;
da411a48
RV		 637 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
638 IS_CFL_ULT(dev_priv)) {
f8896f5d 639 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 640 return skl_u_ddi_translations_edp;
f8896f5d 641 } else {
f8896f5d 642 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 643 return skl_ddi_translations_edp;
f8896f5d
DW		 644 }
645 }
cd1101cb 646
da411a48 647 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 648 return kbl_get_buf_trans_dp(dev_priv, n_entries);
649 else
650 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 651}
652
653static const struct ddi_buf_trans *
78ab0bae 654skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 655{
dfdaa566 656 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 657 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 658 return skl_y_ddi_translations_hdmi;
f8896f5d 659 } else {
f8896f5d 660 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 661 return skl_ddi_translations_hdmi;
f8896f5d 662 }
f8896f5d
DW		 663}
664
edba48fd
VS		 665static int skl_buf_trans_num_entries(enum port port, int n_entries)
666{
667 /* Only DDIA and DDIE can select the 10th register with DP */
668 if (port == PORT_A || port == PORT_E)
669 return min(n_entries, 10);
670 else
671 return min(n_entries, 9);
672}
673
d8fe2c7f
VS		 674static const struct ddi_buf_trans *
675intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 676 enum port port, int *n_entries)
d8fe2c7f
VS		 677{
678 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 679 const struct ddi_buf_trans *ddi_translations =
680 kbl_get_buf_trans_dp(dev_priv, n_entries);
681 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
682 return ddi_translations;
d8fe2c7f 683 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 684 const struct ddi_buf_trans *ddi_translations =
685 skl_get_buf_trans_dp(dev_priv, n_entries);
686 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
687 return ddi_translations;
d8fe2c7f
VS		 688 } else if (IS_BROADWELL(dev_priv)) {
689 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
690 return bdw_ddi_translations_dp;
691 } else if (IS_HASWELL(dev_priv)) {
692 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
693 return hsw_ddi_translations_dp;
694 }
695
696 *n_entries = 0;
697 return NULL;
698}
699
700static const struct ddi_buf_trans *
701intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 702 enum port port, int *n_entries)
d8fe2c7f
VS		 703{
704 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 705 const struct ddi_buf_trans *ddi_translations =
706 skl_get_buf_trans_edp(dev_priv, n_entries);
707 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
708 return ddi_translations;
d8fe2c7f
VS		 709 } else if (IS_BROADWELL(dev_priv)) {
710 return bdw_get_buf_trans_edp(dev_priv, n_entries);
711 } else if (IS_HASWELL(dev_priv)) {
712 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
713 return hsw_ddi_translations_dp;
714 }
715
716 *n_entries = 0;
717 return NULL;
718}
719
720static const struct ddi_buf_trans *
721intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
722 int *n_entries)
723{
724 if (IS_BROADWELL(dev_priv)) {
725 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
726 return bdw_ddi_translations_fdi;
727 } else if (IS_HASWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
729 return hsw_ddi_translations_fdi;
730 }
731
732 *n_entries = 0;
733 return NULL;
734}
735
975786ee
VS		 736static const struct ddi_buf_trans *
737intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
738 int *n_entries)
739{
740 if (IS_GEN9_BC(dev_priv)) {
741 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
742 } else if (IS_BROADWELL(dev_priv)) {
743 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
744 return bdw_ddi_translations_hdmi;
745 } else if (IS_HASWELL(dev_priv)) {
746 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
747 return hsw_ddi_translations_hdmi;
748 }
749
750 *n_entries = 0;
751 return NULL;
752}
753
7d4f37b5
VS		 754static const struct bxt_ddi_buf_trans *
755bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
756{
757 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
758 return bxt_ddi_translations_dp;
759}
760
761static const struct bxt_ddi_buf_trans *
762bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
763{
764 if (dev_priv->vbt.edp.low_vswing) {
765 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
766 return bxt_ddi_translations_edp;
767 }
768
769 return bxt_get_buf_trans_dp(dev_priv, n_entries);
770}
771
772static const struct bxt_ddi_buf_trans *
773bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
774{
775 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
776 return bxt_ddi_translations_hdmi;
777}
778
cf3e0fb4
RV		 779static const struct cnl_ddi_buf_trans *
780cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
781{
782 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
783
784 if (voltage == VOLTAGE_INFO_0_85V) {
785 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
786 return cnl_ddi_translations_hdmi_0_85V;
787 } else if (voltage == VOLTAGE_INFO_0_95V) {
788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
789 return cnl_ddi_translations_hdmi_0_95V;
790 } else if (voltage == VOLTAGE_INFO_1_05V) {
791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
792 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 793 } else {
794 *n_entries = 1; /* shut up gcc */
cf3e0fb4 795 MISSING_CASE(voltage);
83482ca3 796 }
cf3e0fb4
RV		 797 return NULL;
798}
799
800static const struct cnl_ddi_buf_trans *
801cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
802{
803 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
804
805 if (voltage == VOLTAGE_INFO_0_85V) {
806 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
807 return cnl_ddi_translations_dp_0_85V;
808 } else if (voltage == VOLTAGE_INFO_0_95V) {
809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
810 return cnl_ddi_translations_dp_0_95V;
811 } else if (voltage == VOLTAGE_INFO_1_05V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
813 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 814 } else {
815 *n_entries = 1; /* shut up gcc */
cf3e0fb4 816 MISSING_CASE(voltage);
83482ca3 817 }
cf3e0fb4
RV		 818 return NULL;
819}
820
821static const struct cnl_ddi_buf_trans *
822cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
823{
824 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
825
826 if (dev_priv->vbt.edp.low_vswing) {
827 if (voltage == VOLTAGE_INFO_0_85V) {
828 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
829 return cnl_ddi_translations_edp_0_85V;
830 } else if (voltage == VOLTAGE_INFO_0_95V) {
831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
832 return cnl_ddi_translations_edp_0_95V;
833 } else if (voltage == VOLTAGE_INFO_1_05V) {
834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
835 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 836 } else {
837 *n_entries = 1; /* shut up gcc */
cf3e0fb4 838 MISSING_CASE(voltage);
83482ca3 839 }
cf3e0fb4
RV		 840 return NULL;
841 } else {
842 return cnl_get_buf_trans_dp(dev_priv, n_entries);
843 }
844}
845
b265a2a6 846static const struct cnl_ddi_buf_trans *
fb5c8e9d 847icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
b265a2a6 848 int type, int rate, int *n_entries)
fb5c8e9d 849{
b265a2a6
CT		 850 if (type == INTEL_OUTPUT_HDMI) {
851 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
852 return icl_combo_phy_ddi_translations_hdmi;
853 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
855 return icl_combo_phy_ddi_translations_edp_hbr3;
856 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
858 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 859 }
b265a2a6
CT		 860
861 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
862 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 863}
864
8d8bb85e
VS		 865static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
866{
d02ace87 867 int n_entries, level, default_entry;
8d8bb85e 868
d02ace87 869 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 870
2dd24a9c 871 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 872 if (intel_port_is_combophy(dev_priv, port))
b265a2a6
CT		 873 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
874 0, &n_entries);
dccc7228
MN		 875 else
876 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
877 default_entry = n_entries - 1;
878 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 879 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
880 default_entry = n_entries - 1;
043eaf36 881 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 882 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
883 default_entry = n_entries - 1;
bf503556 884 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 885 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
886 default_entry = 8;
8d8bb85e 887 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 888 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
889 default_entry = 7;
8d8bb85e 890 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 891 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
892 default_entry = 6;
8d8bb85e
VS		 893 } else {
894 WARN(1, "ddi translation table missing\n");
975786ee 895 return 0;
8d8bb85e
VS		 896 }
897
898 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 899 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
900 level = default_entry;
8d8bb85e 901
d02ace87 902 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 903 return 0;
d02ace87
VS		 904 if (WARN_ON_ONCE(level >= n_entries))
905 level = n_entries - 1;
21b39d2a 906
d02ace87 907 return level;
8d8bb85e
VS		 908}
909
e58623cb
AR		 910/*
911 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 912 * values in advance. This function programs the correct values for
913 * DP/eDP/FDI use cases.
45244b87 914 */
3a6d84e6
VS		 915static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
916 const struct intel_crtc_state *crtc_state)
45244b87 917{
6a7e4f99 918 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 919 u32 iboost_bit = 0;
7d1c42e6 920 int i, n_entries;
0fce04c8 921 enum port port = encoder->port;
10122051 922 const struct ddi_buf_trans *ddi_translations;
e58623cb 923
3a6d84e6
VS		 924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
925 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
926 &n_entries);
927 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 928 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 929 &n_entries);
3a6d84e6 930 else
edba48fd 931 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 932 &n_entries);
e58623cb 933
edba48fd
VS		 934 /* If we're boosting the current, set bit 31 of trans1 */
935 if (IS_GEN9_BC(dev_priv) &&
936 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
937 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 938
7d1c42e6 939 for (i = 0; i < n_entries; i++) {
9712e688
VS		 940 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
941 ddi_translations[i].trans1 | iboost_bit);
942 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
943 ddi_translations[i].trans2);
45244b87 944 }
32bdc400
VS		 945}
946
947/*
948 * Starting with Haswell, DDI port buffers must be programmed with correct
949 * values in advance. This function programs the correct values for
950 * HDMI/DVI use cases.
951 */
7ea79333 952static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 953 int level)
32bdc400
VS		 954{
955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
956 u32 iboost_bit = 0;
d02ace87 957 int n_entries;
0fce04c8 958 enum port port = encoder->port;
d02ace87 959 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 960
d02ace87 961 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 962
d02ace87 963 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 964 return;
d02ace87
VS		 965 if (WARN_ON_ONCE(level >= n_entries))
966 level = n_entries - 1;
21b39d2a 967
975786ee
VS		 968 /* If we're boosting the current, set bit 31 of trans1 */
969 if (IS_GEN9_BC(dev_priv) &&
970 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
971 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 972
6acab15a 973 /* Entry 9 is for HDMI: */
ed9c77d2 974 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 975 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 976 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 977 ddi_translations[level].trans2);
45244b87
ED		 978}
979
248138b5
PZ		 980static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
981 enum port port)
982{
f0f59a00 983 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 984 int i;
985
3449ca85 986 for (i = 0; i < 16; i++) {
248138b5
PZ		 987 udelay(1);
988 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
989 return;
990 }
991 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
992}
c82e4d26 993
3d0c5005 994static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 995{
0823eb9c 996 switch (pll->info->id) {
c856052a
ACO		 997 case DPLL_ID_WRPLL1:
998 return PORT_CLK_SEL_WRPLL1;
999 case DPLL_ID_WRPLL2:
1000 return PORT_CLK_SEL_WRPLL2;
1001 case DPLL_ID_SPLL:
1002 return PORT_CLK_SEL_SPLL;
1003 case DPLL_ID_LCPLL_810:
1004 return PORT_CLK_SEL_LCPLL_810;
1005 case DPLL_ID_LCPLL_1350:
1006 return PORT_CLK_SEL_LCPLL_1350;
1007 case DPLL_ID_LCPLL_2700:
1008 return PORT_CLK_SEL_LCPLL_2700;
1009 default:
0823eb9c 1010 MISSING_CASE(pll->info->id);
c856052a
ACO		 1011 return PORT_CLK_SEL_NONE;
1012 }
1013}
1014
20fd2ab7 1015static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1016 const struct intel_crtc_state *crtc_state)
c27e917e 1017{
0e5fa646
ML		 1018 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1019 int clock = crtc_state->port_clock;
c27e917e
PZ		 1020 const enum intel_dpll_id id = pll->info->id;
1021
1022 switch (id) {
1023 default:
20fd2ab7
LDM		 1024 /*
1025 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1026 * here, so do warn if this get passed in
1027 */
c27e917e 1028 MISSING_CASE(id);
c27e917e 1029 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1030 case DPLL_ID_ICL_TBTPLL:
1031 switch (clock) {
1032 case 162000:
1033 return DDI_CLK_SEL_TBT_162;
1034 case 270000:
1035 return DDI_CLK_SEL_TBT_270;
1036 case 540000:
1037 return DDI_CLK_SEL_TBT_540;
1038 case 810000:
1039 return DDI_CLK_SEL_TBT_810;
1040 default:
1041 MISSING_CASE(clock);
7a61a6de 1042 return DDI_CLK_SEL_NONE;
1fa11ee2 1043 }
c27e917e
PZ		 1044 case DPLL_ID_ICL_MGPLL1:
1045 case DPLL_ID_ICL_MGPLL2:
1046 case DPLL_ID_ICL_MGPLL3:
1047 case DPLL_ID_ICL_MGPLL4:
1048 return DDI_CLK_SEL_MG;
1049 }
1050}
1051
c82e4d26
ED		 1052/* Starting with Haswell, different DDI ports can work in FDI mode for
1053 * connection to the PCH-located connectors. For this, it is necessary to train
1054 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1055 *
1056 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1057 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1058 * DDI A (which is used for eDP)
1059 */
1060
dc4a1094
ACO		 1061void hsw_fdi_link_train(struct intel_crtc *crtc,
1062 const struct intel_crtc_state *crtc_state)
c82e4d26 1063{
4cbe4b2b 1064 struct drm_device *dev = crtc->base.dev;
fac5e23e 1065 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1066 struct intel_encoder *encoder;
c856052a 1067 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1068
4cbe4b2b 1069 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1070 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1071 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1072 }
1073
04945641
PZ		 1074 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1075 * mode set "sequence for CRT port" document:
1076 * - TP1 to TP2 time with the default value
1077 * - FDI delay to 90h
8693a824
DL		 1078 *
1079 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1080 */
eede3b53 1081 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1082 FDI_RX_PWRDN_LANE0_VAL(2) |
1083 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1084
1085 /* Enable the PCH Receiver FDI PLL */
3e68320e 1086 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1087 FDI_RX_PLL_ENABLE |
dc4a1094 1088 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1089 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1090 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1091 udelay(220);
1092
1093 /* Switch from Rawclk to PCDclk */
1094 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1095 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1096
1097 /* Configure Port Clock Select */
dc4a1094 1098 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1099 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1100 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1101
1102 /* Start the training iterating through available voltages and emphasis,
1103 * testing each value twice. */
10122051 1104 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1105 /* Configure DP_TP_CTL with auto-training */
1106 I915_WRITE(DP_TP_CTL(PORT_E),
1107 DP_TP_CTL_FDI_AUTOTRAIN |
1108 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1109 DP_TP_CTL_LINK_TRAIN_PAT1 |
1110 DP_TP_CTL_ENABLE);
1111
876a8cdf
DL		 1112 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1113 * DDI E does not support port reversal, the functionality is
1114 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1115 * port reversal bit */
c82e4d26 1116 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1117 DDI_BUF_CTL_ENABLE |
dc4a1094 1118 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1119 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1120 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1121
1122 udelay(600);
1123
04945641 1124 /* Program PCH FDI Receiver TU */
eede3b53 1125 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1126
1127 /* Enable PCH FDI Receiver with auto-training */
1128 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1129 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1130 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1131
1132 /* Wait for FDI receiver lane calibration */
1133 udelay(30);
1134
1135 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1136 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1137 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1138 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1139 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1140
1141 /* Wait for FDI auto training time */
1142 udelay(5);
c82e4d26
ED		 1143
1144 temp = I915_READ(DP_TP_STATUS(PORT_E));
1145 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1146 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1147 break;
1148 }
c82e4d26 1149
a308ccb3
VS		 1150 /*
1151 * Leave things enabled even if we failed to train FDI.
1152 * Results in less fireworks from the state checker.
1153 */
1154 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1155 DRM_ERROR("FDI link training failed!\n");
1156 break;
c82e4d26 1157 }
04945641 1158
5b421c57
VS		 1159 rx_ctl_val &= ~FDI_RX_ENABLE;
1160 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1161 POSTING_READ(FDI_RX_CTL(PIPE_A));
1162
248138b5
PZ		 1163 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1164 temp &= ~DDI_BUF_CTL_ENABLE;
1165 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
04945641 1168 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1169 temp = I915_READ(DP_TP_CTL(PORT_E));
1170 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1171 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1172 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1173 POSTING_READ(DP_TP_CTL(PORT_E));
1174
1175 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1176
04945641 1177 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1178 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1179 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1180 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1181 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1182 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1183 }
1184
a308ccb3
VS		 1185 /* Enable normal pixel sending for FDI */
1186 I915_WRITE(DP_TP_CTL(PORT_E),
1187 DP_TP_CTL_FDI_AUTOTRAIN |
1188 DP_TP_CTL_LINK_TRAIN_NORMAL |
1189 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1190 DP_TP_CTL_ENABLE);
c82e4d26 1191}
0e72a5b5 1192
d7c530b2 1193static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1194{
1195 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1196 struct intel_digital_port *intel_dig_port =
1197 enc_to_dig_port(&encoder->base);
1198
1199 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1200 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1201 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1202}
1203
8d9ddbcb 1204static struct intel_encoder *
e9ce1a62 1205intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1206{
e9ce1a62 1207 struct drm_device *dev = crtc->base.dev;
1524e93e 1208 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1209 int num_encoders = 0;
1210
1524e93e
SS		 1211 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1212 ret = encoder;
8d9ddbcb
PZ		 1213 num_encoders++;
1214 }
1215
1216 if (num_encoders != 1)
84f44ce7 1217 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1218 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1219
1220 BUG_ON(ret == NULL);
1221 return ret;
1222}
1223
1c0b85c5 1224#define LC_FREQ 2700
1c0b85c5 1225
f0f59a00
VS		 1226static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1227 i915_reg_t reg)
11578553
JB		 1228{
1229 int refclk = LC_FREQ;
1230 int n, p, r;
1231 u32 wrpll;
1232
1233 wrpll = I915_READ(reg);
114fe488
DV		 1234 switch (wrpll & WRPLL_PLL_REF_MASK) {
1235 case WRPLL_PLL_SSC:
1236 case WRPLL_PLL_NON_SSC:
11578553
JB		 1237 /*
1238 * We could calculate spread here, but our checking
1239 * code only cares about 5% accuracy, and spread is a max of
1240 * 0.5% downspread.
1241 */
1242 refclk = 135;
1243 break;
114fe488 1244 case WRPLL_PLL_LCPLL:
11578553
JB		 1245 refclk = LC_FREQ;
1246 break;
1247 default:
1248 WARN(1, "bad wrpll refclk\n");
1249 return 0;
1250 }
1251
1252 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1253 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1254 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1255
20f0ec16
JB		 1256 /* Convert to KHz, p & r have a fixed point portion */
1257 return (refclk * n * 100) / (p * r);
11578553
JB		 1258}
1259
947f4417 1260static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1261{
3d0c5005 1262 u32 p0, p1, p2, dco_freq;
540e732c 1263
947f4417
LDM		 1264 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1265 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1266
947f4417
LDM		 1267 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1268 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1269 else
1270 p1 = 1;
1271
1272
1273 switch (p0) {
1274 case DPLL_CFGCR2_PDIV_1:
1275 p0 = 1;
1276 break;
1277 case DPLL_CFGCR2_PDIV_2:
1278 p0 = 2;
1279 break;
1280 case DPLL_CFGCR2_PDIV_3:
1281 p0 = 3;
1282 break;
1283 case DPLL_CFGCR2_PDIV_7:
1284 p0 = 7;
1285 break;
1286 }
1287
1288 switch (p2) {
1289 case DPLL_CFGCR2_KDIV_5:
1290 p2 = 5;
1291 break;
1292 case DPLL_CFGCR2_KDIV_2:
1293 p2 = 2;
1294 break;
1295 case DPLL_CFGCR2_KDIV_3:
1296 p2 = 3;
1297 break;
1298 case DPLL_CFGCR2_KDIV_1:
1299 p2 = 1;
1300 break;
1301 }
1302
947f4417
LDM		 1303 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1304 * 24 * 1000;
540e732c 1305
947f4417
LDM		 1306 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1307 * 24 * 1000) / 0x8000;
540e732c 1308
b8449c43
YX		 1309 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1310 return 0;
1311
540e732c
S		 1312 return dco_freq / (p0 * p1 * p2 * 5);
1313}
1314
8327af28 1315int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1316 struct intel_dpll_hw_state *pll_state)
a9701a89 1317{
3d0c5005 1318 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1319
5e65216d
LDM		 1320 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1321 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1322
5e65216d
LDM		 1323 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1324 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1325 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1326 else
1327 p1 = 1;
1328
1329
1330 switch (p0) {
1331 case DPLL_CFGCR1_PDIV_2:
1332 p0 = 2;
1333 break;
1334 case DPLL_CFGCR1_PDIV_3:
1335 p0 = 3;
1336 break;
1337 case DPLL_CFGCR1_PDIV_5:
1338 p0 = 5;
1339 break;
1340 case DPLL_CFGCR1_PDIV_7:
1341 p0 = 7;
1342 break;
1343 }
1344
1345 switch (p2) {
1346 case DPLL_CFGCR1_KDIV_1:
1347 p2 = 1;
1348 break;
1349 case DPLL_CFGCR1_KDIV_2:
1350 p2 = 2;
1351 break;
2ee7fd1e
VS		 1352 case DPLL_CFGCR1_KDIV_3:
1353 p2 = 3;
a9701a89
RV		 1354 break;
1355 }
1356
9f9d594d 1357 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1358
5e65216d
LDM		 1359 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1360 * ref_clock;
a9701a89 1361
5e65216d 1362 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1363 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1364
0e005888
PZ		 1365 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1366 return 0;
1367
a9701a89
RV		 1368 return dco_freq / (p0 * p1 * p2 * 5);
1369}
1370
7b19f544
MN		 1371static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1372 enum port port)
1373{
1374 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1375
1376 switch (val) {
1377 case DDI_CLK_SEL_NONE:
1378 return 0;
1379 case DDI_CLK_SEL_TBT_162:
1380 return 162000;
1381 case DDI_CLK_SEL_TBT_270:
1382 return 270000;
1383 case DDI_CLK_SEL_TBT_540:
1384 return 540000;
1385 case DDI_CLK_SEL_TBT_810:
1386 return 810000;
1387 default:
1388 MISSING_CASE(val);
1389 return 0;
1390 }
1391}
1392
1393static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1394 const struct intel_dpll_hw_state *pll_state)
7b19f544 1395{
02c99d26 1396 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1397 u64 tmp;
1398
02c99d26 1399 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1400
02c99d26
LDM		 1401 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1402 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1403 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1404 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1405 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1406
02c99d26
LDM		 1407 switch (pll_state->mg_clktop2_hsclkctl &
1408 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1409 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1410 div1 = 2;
1411 break;
1412 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1413 div1 = 3;
1414 break;
1415 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1416 div1 = 5;
1417 break;
1418 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1419 div1 = 7;
1420 break;
1421 default:
02c99d26 1422 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1423 return 0;
1424 }
1425
02c99d26
LDM		 1426 div2 = (pll_state->mg_clktop2_hsclkctl &
1427 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1428 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1429
7b19f544
MN		 1430 /* div2 value of 0 is same as 1 means no div */
1431 if (div2 == 0)
1432 div2 = 1;
1433
1434 /*
1435 * Adjust the original formula to delay the division by 2^22 in order to
1436 * minimize possible rounding errors.
1437 */
02c99d26
LDM		 1438 tmp = (u64)m1 * m2_int * ref_clock +
1439 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1440 tmp = div_u64(tmp, 5 * div1 * div2);
1441
1442 return tmp;
1443}
1444
398a017e
VS		 1445static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1446{
1447 int dotclock;
1448
1449 if (pipe_config->has_pch_encoder)
1450 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1451 &pipe_config->fdi_m_n);
37a5650b 1452 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1453 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1454 &pipe_config->dp_m_n);
1455 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1456 dotclock = pipe_config->port_clock * 2 / 3;
1457 else
1458 dotclock = pipe_config->port_clock;
1459
16668f48
GM		 1460 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1461 !intel_crtc_has_dp_encoder(pipe_config))
b22ca995
SS		 1462 dotclock *= 2;
1463
398a017e
VS		 1464 if (pipe_config->pixel_multiplier)
1465 dotclock /= pipe_config->pixel_multiplier;
1466
1467 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1468}
540e732c 1469
51c83cfa
MN		 1470static void icl_ddi_clock_get(struct intel_encoder *encoder,
1471 struct intel_crtc_state *pipe_config)
1472{
1473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1474 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1475 enum port port = encoder->port;
5e65216d 1476 int link_clock;
51c83cfa 1477
176597a1 1478 if (intel_port_is_combophy(dev_priv, port)) {
5e65216d 1479 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1480 } else {
077973c8
LDM		 1481 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1482 pipe_config->shared_dpll);
1483
7b19f544
MN		 1484 if (pll_id == DPLL_ID_ICL_TBTPLL)
1485 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1486 else
02c99d26 1487 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1488 }
1489
1490 pipe_config->port_clock = link_clock;
02c99d26 1491
51c83cfa
MN		 1492 ddi_dotclock_get(pipe_config);
1493}
1494
a9701a89
RV		 1495static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1496 struct intel_crtc_state *pipe_config)
1497{
1498 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1499 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1500 int link_clock;
a9701a89 1501
5e65216d
LDM		 1502 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1503 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1504 } else {
5e65216d 1505 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1506
1507 switch (link_clock) {
1508 case DPLL_CFGCR0_LINK_RATE_810:
1509 link_clock = 81000;
1510 break;
1511 case DPLL_CFGCR0_LINK_RATE_1080:
1512 link_clock = 108000;
1513 break;
1514 case DPLL_CFGCR0_LINK_RATE_1350:
1515 link_clock = 135000;
1516 break;
1517 case DPLL_CFGCR0_LINK_RATE_1620:
1518 link_clock = 162000;
1519 break;
1520 case DPLL_CFGCR0_LINK_RATE_2160:
1521 link_clock = 216000;
1522 break;
1523 case DPLL_CFGCR0_LINK_RATE_2700:
1524 link_clock = 270000;
1525 break;
1526 case DPLL_CFGCR0_LINK_RATE_3240:
1527 link_clock = 324000;
1528 break;
1529 case DPLL_CFGCR0_LINK_RATE_4050:
1530 link_clock = 405000;
1531 break;
1532 default:
1533 WARN(1, "Unsupported link rate\n");
1534 break;
1535 }
1536 link_clock *= 2;
1537 }
1538
1539 pipe_config->port_clock = link_clock;
1540
1541 ddi_dotclock_get(pipe_config);
1542}
1543
540e732c 1544static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1545 struct intel_crtc_state *pipe_config)
540e732c 1546{
947f4417
LDM		 1547 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1548 int link_clock;
540e732c 1549
947f4417
LDM		 1550 /*
1551 * ctrl1 register is already shifted for each pll, just use 0 to get
1552 * the internal shift for each field
1553 */
1554 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1555 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1556 } else {
947f4417
LDM		 1557 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1558 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1559
1560 switch (link_clock) {
71cd8423 1561 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1562 link_clock = 81000;
1563 break;
71cd8423 1564 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1565 link_clock = 108000;
1566 break;
71cd8423 1567 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1568 link_clock = 135000;
1569 break;
71cd8423 1570 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1571 link_clock = 162000;
1572 break;
71cd8423 1573 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1574 link_clock = 216000;
1575 break;
71cd8423 1576 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1577 link_clock = 270000;
1578 break;
1579 default:
1580 WARN(1, "Unsupported link rate\n");
1581 break;
1582 }
1583 link_clock *= 2;
1584 }
1585
1586 pipe_config->port_clock = link_clock;
1587
398a017e 1588 ddi_dotclock_get(pipe_config);
540e732c
S		 1589}
1590
3d51278a 1591static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1592 struct intel_crtc_state *pipe_config)
11578553 1593{
fac5e23e 1594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1595 int link_clock = 0;
1596 u32 val, pll;
1597
c856052a 1598 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1599 switch (val & PORT_CLK_SEL_MASK) {
1600 case PORT_CLK_SEL_LCPLL_810:
1601 link_clock = 81000;
1602 break;
1603 case PORT_CLK_SEL_LCPLL_1350:
1604 link_clock = 135000;
1605 break;
1606 case PORT_CLK_SEL_LCPLL_2700:
1607 link_clock = 270000;
1608 break;
1609 case PORT_CLK_SEL_WRPLL1:
01403de3 1610 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1611 break;
1612 case PORT_CLK_SEL_WRPLL2:
01403de3 1613 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1614 break;
1615 case PORT_CLK_SEL_SPLL:
1616 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1617 if (pll == SPLL_PLL_FREQ_810MHz)
1618 link_clock = 81000;
1619 else if (pll == SPLL_PLL_FREQ_1350MHz)
1620 link_clock = 135000;
1621 else if (pll == SPLL_PLL_FREQ_2700MHz)
1622 link_clock = 270000;
1623 else {
1624 WARN(1, "bad spll freq\n");
1625 return;
1626 }
1627 break;
1628 default:
1629 WARN(1, "bad port clock sel\n");
1630 return;
1631 }
1632
1633 pipe_config->port_clock = link_clock * 2;
1634
398a017e 1635 ddi_dotclock_get(pipe_config);
11578553
JB		 1636}
1637
47c9877e 1638static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1639{
9e2c8475 1640 struct dpll clock;
aa610dcb 1641
aa610dcb 1642 clock.m1 = 2;
47c9877e
LDM		 1643 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1644 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1645 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1646 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1647 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1648 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1649
1650 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1651}
1652
1653static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1654 struct intel_crtc_state *pipe_config)
977bb38d 1655{
47c9877e
LDM		 1656 pipe_config->port_clock =
1657 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1658
398a017e 1659 ddi_dotclock_get(pipe_config);
977bb38d
S		 1660}
1661
35686a44
VS		 1662static void intel_ddi_clock_get(struct intel_encoder *encoder,
1663 struct intel_crtc_state *pipe_config)
3d51278a 1664{
0853723b 1665 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1666
2dd24a9c 1667 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1668 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1669 else if (IS_CANNONLAKE(dev_priv))
1670 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1671 else if (IS_GEN9_LP(dev_priv))
1672 bxt_ddi_clock_get(encoder, pipe_config);
1673 else if (IS_GEN9_BC(dev_priv))
1674 skl_ddi_clock_get(encoder, pipe_config);
1675 else if (INTEL_GEN(dev_priv) <= 8)
1676 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1677}
1678
3dc38eea 1679void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1680{
3dc38eea 1681 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1682 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1683 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1684 u32 temp;
dae84799 1685
5448f53f
VS		 1686 if (!intel_crtc_has_dp_encoder(crtc_state))
1687 return;
4d1de975 1688
5448f53f
VS		 1689 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1690
1691 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1692
1693 if (crtc_state->limited_color_range)
1694 temp |= TRANS_MSA_CEA_RANGE;
1695
5448f53f
VS		 1696 switch (crtc_state->pipe_bpp) {
1697 case 18:
1698 temp |= TRANS_MSA_6_BPC;
1699 break;
1700 case 24:
1701 temp |= TRANS_MSA_8_BPC;
1702 break;
1703 case 30:
1704 temp |= TRANS_MSA_10_BPC;
1705 break;
1706 case 36:
1707 temp |= TRANS_MSA_12_BPC;
1708 break;
1709 default:
1710 MISSING_CASE(crtc_state->pipe_bpp);
1711 break;
dae84799 1712 }
5448f53f 1713
668b6c17
SS		 1714 /*
1715 * As per DP 1.2 spec section 2.3.4.3 while sending
1716 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1717 * colorspace information. The output colorspace encoding is BT601.
1718 */
1719 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1720 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
ec4401d3
GM		 1721 /*
1722 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1723 * of Color Encoding Format and Content Color Gamut] while sending
1724 * YCBCR 420 signals we should program MSA MISC1 fields which
1725 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1726 */
1727 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1728 temp |= TRANS_MSA_USE_VSC_SDP;
5448f53f 1729 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1730}
1731
3dc38eea
ACO		 1732void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1733 bool state)
0e32b39c 1734{
3dc38eea 1735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1736 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1737 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1738 u32 temp;
7e732cac 1739
0e32b39c
DA		 1740 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1741 if (state == true)
1742 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1743 else
1744 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1745 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1746}
1747
3dc38eea 1748void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1749{
3dc38eea 1750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1751 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1753 enum pipe pipe = crtc->pipe;
3dc38eea 1754 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1755 enum port port = encoder->port;
3d0c5005 1756 u32 temp;
8d9ddbcb 1757
ad80a810
PZ		 1758 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1759 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1760 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1761
3dc38eea 1762 switch (crtc_state->pipe_bpp) {
dfcef252 1763 case 18:
ad80a810 1764 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1765 break;
1766 case 24:
ad80a810 1767 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1768 break;
1769 case 30:
ad80a810 1770 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1771 break;
1772 case 36:
ad80a810 1773 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1774 break;
1775 default:
4e53c2e0 1776 BUG();
dfcef252 1777 }
72662e10 1778
3dc38eea 1779 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1780 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1781 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1782 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1783
e6f0bfc4
PZ		 1784 if (cpu_transcoder == TRANSCODER_EDP) {
1785 switch (pipe) {
1786 case PIPE_A:
c7670b10
PZ		 1787 /* On Haswell, can only use the always-on power well for
1788 * eDP when not using the panel fitter, and when not
1789 * using motion blur mitigation (which we don't
1790 * support). */
dc0c0bfe 1791 if (crtc_state->pch_pfit.force_thru)
d6dd9eb1
DV		 1792 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1793 else
1794 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1795 break;
1796 case PIPE_B:
1797 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1798 break;
1799 case PIPE_C:
1800 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1801 break;
1802 default:
1803 BUG();
1804 break;
1805 }
1806 }
1807
742745f1 1808 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1809 if (crtc_state->has_hdmi_sink)
ad80a810 1810 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1811 else
ad80a810 1812 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1813
1814 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1815 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1816 if (crtc_state->hdmi_high_tmds_clock_ratio)
1817 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1818 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1819 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1820 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1821 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1822 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1823 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1824 } else {
742745f1
VS		 1825 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1826 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1827 }
1828
ad80a810 1829 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1830}
72662e10 1831
90c3e219 1832void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1833{
90c3e219
CT		 1834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1836 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1837 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1838 u32 val = I915_READ(reg);
8d9ddbcb 1839
0e32b39c 1840 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1841 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1842 I915_WRITE(reg, val);
90c3e219
CT		 1843
1844 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1845 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1846 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1847 /* Quirk time at 100ms for reliable operation */
1848 msleep(100);
1849 }
72662e10
ED		 1850}
1851
2320175f
SP		 1852int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1853 bool enable)
1854{
1855 struct drm_device *dev = intel_encoder->base.dev;
1856 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1857 intel_wakeref_t wakeref;
2320175f
SP		 1858 enum pipe pipe = 0;
1859 int ret = 0;
3d0c5005 1860 u32 tmp;
2320175f 1861
0e6e0be4
CW		 1862 wakeref = intel_display_power_get_if_enabled(dev_priv,
1863 intel_encoder->power_domain);
1864 if (WARN_ON(!wakeref))
2320175f
SP		 1865 return -ENXIO;
1866
1867 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1868 ret = -EIO;
1869 goto out;
1870 }
1871
1872 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1873 if (enable)
1874 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1875 else
1876 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1877 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1878out:
0e6e0be4 1879 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1880 return ret;
1881}
1882
bcbc889b
PZ		 1883bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1884{
1885 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1886 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1887 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1888 int type = intel_connector->base.connector_type;
0fce04c8 1889 enum port port = encoder->port;
bcbc889b 1890 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1891 intel_wakeref_t wakeref;
1892 enum pipe pipe = 0;
3d0c5005 1893 u32 tmp;
e27daab4 1894 bool ret;
bcbc889b 1895
0e6e0be4
CW		 1896 wakeref = intel_display_power_get_if_enabled(dev_priv,
1897 encoder->power_domain);
1898 if (!wakeref)
882244a3
PZ		 1899 return false;
1900
1524e93e 1901 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1902 ret = false;
1903 goto out;
1904 }
bcbc889b 1905
bc7e3525 1906 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1907 cpu_transcoder = TRANSCODER_EDP;
1908 else
1a240d4d 1909 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1910
1911 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1912
1913 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1914 case TRANS_DDI_MODE_SELECT_HDMI:
1915 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1916 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1917 break;
bcbc889b
PZ		 1918
1919 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1920 ret = type == DRM_MODE_CONNECTOR_eDP ||
1921 type == DRM_MODE_CONNECTOR_DisplayPort;
1922 break;
1923
0e32b39c
DA		 1924 case TRANS_DDI_MODE_SELECT_DP_MST:
1925 /* if the transcoder is in MST state then
1926 * connector isn't connected */
e27daab4
ID		 1927 ret = false;
1928 break;
bcbc889b
PZ		 1929
1930 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1931 ret = type == DRM_MODE_CONNECTOR_VGA;
1932 break;
bcbc889b
PZ		 1933
1934 default:
e27daab4
ID		 1935 ret = false;
1936 break;
bcbc889b 1937 }
e27daab4
ID		 1938
1939out:
0e6e0be4 1940 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 1941
1942 return ret;
bcbc889b
PZ		 1943}
1944
9199c322
ID		 1945static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1946 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 1947{
1948 struct drm_device *dev = encoder->base.dev;
fac5e23e 1949 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1950 enum port port = encoder->port;
0e6e0be4 1951 intel_wakeref_t wakeref;
3657e927 1952 enum pipe p;
85234cdc 1953 u32 tmp;
9199c322
ID		 1954 u8 mst_pipe_mask;
1955
1956 *pipe_mask = 0;
1957 *is_dp_mst = false;
85234cdc 1958
0e6e0be4
CW		 1959 wakeref = intel_display_power_get_if_enabled(dev_priv,
1960 encoder->power_domain);
1961 if (!wakeref)
9199c322 1962 return;
e27daab4 1963
fe43d3f5 1964 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 1965 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1966 goto out;
85234cdc 1967
bc7e3525 1968 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 1969 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1970
ad80a810 1971 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 1972 default:
1973 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1974 /* fallthrough */
ad80a810
PZ		 1975 case TRANS_DDI_EDP_INPUT_A_ON:
1976 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 1977 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 1978 break;
1979 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 1980 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 1981 break;
1982 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 1983 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 1984 break;
1985 }
1986
e27daab4
ID		 1987 goto out;
1988 }
0e32b39c 1989
9199c322 1990 mst_pipe_mask = 0;
3657e927 1991 for_each_pipe(dev_priv, p) {
9199c322 1992 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 1993
1994 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 1995
9199c322
ID		 1996 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1997 continue;
e27daab4 1998
9199c322
ID		 1999 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2000 TRANS_DDI_MODE_SELECT_DP_MST)
2001 mst_pipe_mask |= BIT(p);
e27daab4 2002
9199c322 2003 *pipe_mask |= BIT(p);
85234cdc
DV		 2004 }
2005
9199c322
ID		 2006 if (!*pipe_mask)
2007 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2008 port_name(port));
2009
2010 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2011 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2012 port_name(port), *pipe_mask);
2013 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2014 }
2015
2016 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2017 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2018 port_name(port), *pipe_mask, mst_pipe_mask);
2019 else
2020 *is_dp_mst = mst_pipe_mask;
85234cdc 2021
e27daab4 2022out:
9199c322 2023 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2024 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2025 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2026 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2027 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2028 DRM_ERROR("Port %c enabled but PHY powered down? "
2029 "(PHY_CTL %08x)\n", port_name(port), tmp);
2030 }
2031
0e6e0be4 2032 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2033}
e27daab4 2034
9199c322
ID		 2035bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2036 enum pipe *pipe)
2037{
2038 u8 pipe_mask;
2039 bool is_mst;
2040
2041 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2042
2043 if (is_mst || !pipe_mask)
2044 return false;
2045
2046 *pipe = ffs(pipe_mask) - 1;
2047
2048 return true;
85234cdc
DV		 2049}
2050
52528055 2051static inline enum intel_display_power_domain
bdaa29b6 2052intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2053{
9e3b5ce9 2054 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2055 * DC states enabled at the same time, while for driver initiated AUX
2056 * transfers we need the same AUX IOs to be powered but with DC states
2057 * disabled. Accordingly use the AUX power domain here which leaves DC
2058 * states enabled.
2059 * However, for non-A AUX ports the corresponding non-EDP transcoders
2060 * would have already enabled power well 2 and DC_OFF. This means we can
2061 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2062 * specific AUX_IO reference without powering up any extra wells.
2063 * Note that PSR is enabled only on Port A even though this function
2064 * returns the correct domain for other ports too.
2065 */
563d22a0 2066 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2067 intel_aux_power_domain(dig_port);
52528055
ID		 2068}
2069
3a52fb7e
ID		 2070static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2071 struct intel_crtc_state *crtc_state)
62b69566 2072{
8e4a3ad9 2073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2074 struct intel_digital_port *dig_port;
62b69566 2075
52528055
ID		 2076 /*
2077 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2078 * happen since fake-MST encoders don't set their get_power_domains()
2079 * hook.
52528055
ID		 2080 */
2081 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2082 return;
b79ebe74
ID		 2083
2084 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2085 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2086
8e4a3ad9
ID		 2087 /*
2088 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2089 * ports.
2090 */
2091 if (intel_crtc_has_dp_encoder(crtc_state) ||
2092 intel_port_is_tc(dev_priv, encoder->port))
3a52fb7e
ID		 2093 intel_display_power_get(dev_priv,
2094 intel_ddi_main_link_aux_domain(dig_port));
52528055 2095
a24c62f9
MN		 2096 /*
2097 * VDSC power is needed when DSC is enabled
2098 */
2099 if (crtc_state->dsc_params.compression_enable)
3a52fb7e
ID		 2100 intel_display_power_get(dev_priv,
2101 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2102}
2103
3dc38eea 2104void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2105{
3dc38eea 2106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2108 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2109 enum port port = encoder->port;
3dc38eea 2110 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2111
bb523fc0
PZ		 2112 if (cpu_transcoder != TRANSCODER_EDP)
2113 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2114 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2115}
2116
3dc38eea 2117void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2118{
3dc38eea
ACO		 2119 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2120 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2121
bb523fc0
PZ		 2122 if (cpu_transcoder != TRANSCODER_EDP)
2123 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2124 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2125}
2126
a7d8dbc0 2127static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2128 enum port port, u8 iboost)
f8896f5d 2129{
a7d8dbc0
VS		 2130 u32 tmp;
2131
2132 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2133 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2134 if (iboost)
2135 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2136 else
2137 tmp |= BALANCE_LEG_DISABLE(port);
2138 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2139}
2140
081dfcfa
VS		 2141static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2142 int level, enum intel_output_type type)
a7d8dbc0
VS		 2143{
2144 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2146 enum port port = encoder->port;
3d0c5005 2147 u8 iboost;
f8896f5d 2148
081dfcfa
VS		 2149 if (type == INTEL_OUTPUT_HDMI)
2150 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2151 else
2152 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2153
081dfcfa
VS		 2154 if (iboost == 0) {
2155 const struct ddi_buf_trans *ddi_translations;
2156 int n_entries;
2157
2158 if (type == INTEL_OUTPUT_HDMI)
2159 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2160 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2161 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2162 else
edba48fd 2163 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2164
21b39d2a
VS		 2165 if (WARN_ON_ONCE(!ddi_translations))
2166 return;
2167 if (WARN_ON_ONCE(level >= n_entries))
2168 level = n_entries - 1;
2169
081dfcfa 2170 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2171 }
2172
2173 /* Make sure that the requested I_boost is valid */
2174 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2175 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2176 return;
2177 }
2178
a7d8dbc0 2179 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2180
a7d8dbc0
VS		 2181 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2182 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2183}
2184
7d4f37b5
VS		 2185static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2186 int level, enum intel_output_type type)
96fb9f9b 2187{
7d4f37b5 2188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2189 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2190 enum port port = encoder->port;
043eaf36 2191 int n_entries;
7d4f37b5
VS		 2192
2193 if (type == INTEL_OUTPUT_HDMI)
2194 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2195 else if (type == INTEL_OUTPUT_EDP)
2196 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2197 else
2198 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2199
21b39d2a
VS		 2200 if (WARN_ON_ONCE(!ddi_translations))
2201 return;
2202 if (WARN_ON_ONCE(level >= n_entries))
2203 level = n_entries - 1;
2204
b6e08203
ACO		 2205 bxt_ddi_phy_set_signal_level(dev_priv, port,
2206 ddi_translations[level].margin,
2207 ddi_translations[level].scale,
2208 ddi_translations[level].enable,
2209 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2210}
2211
ffe5111e
VS		 2212u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2213{
2214 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2215 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2216 enum port port = encoder->port;
ffe5111e
VS		 2217 int n_entries;
2218
2dd24a9c 2219 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2220 if (intel_port_is_combophy(dev_priv, port))
36cf89f5 2221 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
b265a2a6 2222 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2223 else
2224 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2225 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2226 if (encoder->type == INTEL_OUTPUT_EDP)
2227 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2228 else
2229 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2230 } else if (IS_GEN9_LP(dev_priv)) {
2231 if (encoder->type == INTEL_OUTPUT_EDP)
2232 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2233 else
2234 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2235 } else {
2236 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2237 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2238 else
edba48fd 2239 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2240 }
ffe5111e
VS		 2241
2242 if (WARN_ON(n_entries < 1))
2243 n_entries = 1;
2244 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2245 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2246
2247 return index_to_dp_signal_levels[n_entries - 1] &
2248 DP_TRAIN_VOLTAGE_SWING_MASK;
2249}
2250
4718a365
VS		 2251/*
2252 * We assume that the full set of pre-emphasis values can be
2253 * used on all DDI platforms. Should that change we need to
2254 * rethink this code.
2255 */
2256u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2257{
2258 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2260 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2262 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2264 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2266 default:
2267 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2268 }
2269}
2270
f3cf4ba4
VS		 2271static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2272 int level, enum intel_output_type type)
cf54ca8b 2273{
f3cf4ba4 2274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2275 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2276 enum port port = encoder->port;
f3cf4ba4
VS		 2277 int n_entries, ln;
2278 u32 val;
cf54ca8b 2279
f3cf4ba4 2280 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2281 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2282 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2283 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2284 else
2285 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2286
21b39d2a 2287 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2288 return;
21b39d2a 2289 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2290 level = n_entries - 1;
cf54ca8b
RV		 2291
2292 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2293 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2294 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2295 val |= SCALING_MODE_SEL(2);
2296 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2297
2298 /* Program PORT_TX_DW2 */
2299 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2300 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2301 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2302 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2303 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2304 /* Rcomp scalar is fixed as 0x98 for every table entry */
2305 val |= RCOMP_SCALAR(0x98);
2306 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2307
20303eb4 2308 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2309 /* We cannot write to GRP. It would overrite individual loadgen */
2310 for (ln = 0; ln < 4; ln++) {
9194e42a 2311 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2312 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2313 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2314 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2315 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2316 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2317 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2318 }
2319
20303eb4 2320 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2321 /* All DW5 values are fixed for every table entry */
2322 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2323 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2324 val |= RTERM_SELECT(6);
2325 val |= TAP3_DISABLE;
2326 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2327
20303eb4 2328 /* Program PORT_TX_DW7 */
cf54ca8b 2329 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2330 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2331 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2332 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2333}
2334
f3cf4ba4
VS		 2335static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2336 int level, enum intel_output_type type)
cf54ca8b 2337{
0091abc3 2338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2339 enum port port = encoder->port;
f3cf4ba4 2340 int width, rate, ln;
cf54ca8b 2341 u32 val;
0091abc3 2342
f3cf4ba4 2343 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2344 width = 4;
f3cf4ba4 2345 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2346 } else {
f3cf4ba4
VS		 2347 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2348
2349 width = intel_dp->lane_count;
2350 rate = intel_dp->link_rate;
0091abc3 2351 }
cf54ca8b
RV		 2352
2353 /*
2354 * 1. If port type is eDP or DP,
2355 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2356 * else clear to 0b.
2357 */
2358 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2359 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2360 val |= COMMON_KEEPER_EN;
2361 else
2362 val &= ~COMMON_KEEPER_EN;
2363 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2364
2365 /* 2. Program loadgen select */
2366 /*
0091abc3
CT		 2367 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2368 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2369 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2370 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2371 */
0091abc3 2372 for (ln = 0; ln <= 3; ln++) {
9194e42a 2373 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2374 val &= ~LOADGEN_SELECT;
2375
a8e45a1c
NM		 2376 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2377 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2378 val |= LOADGEN_SELECT;
2379 }
9194e42a 2380 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2381 }
cf54ca8b
RV		 2382
2383 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2384 val = I915_READ(CNL_PORT_CL1CM_DW5);
2385 val |= SUS_CLOCK_CONFIG;
2386 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2387
2388 /* 4. Clear training enable to change swing values */
2389 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2390 val &= ~TX_TRAINING_EN;
2391 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2392
2393 /* 5. Program swing and de-emphasis */
f3cf4ba4 2394 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2395
2396 /* 6. Set training enable to trigger update */
2397 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2398 val |= TX_TRAINING_EN;
2399 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2400}
2401
fb5c8e9d 2402static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
b265a2a6
CT		 2403 u32 level, enum port port, int type,
2404 int rate)
fb5c8e9d 2405{
b265a2a6 2406 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2407 u32 n_entries, val;
2408 int ln;
2409
2410 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
b265a2a6 2411 rate, &n_entries);
fb5c8e9d
MN		 2412 if (!ddi_translations)
2413 return;
2414
2415 if (level >= n_entries) {
2416 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2417 level = n_entries - 1;
2418 }
2419
b265a2a6 2420 /* Set PORT_TX_DW5 */
fb5c8e9d 2421 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
b265a2a6
CT		 2422 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2423 TAP2_DISABLE | TAP3_DISABLE);
2424 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2425 val |= RTERM_SELECT(0x6);
b265a2a6 2426 val |= TAP3_DISABLE;
fb5c8e9d
MN		 2427 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2428
2429 /* Program PORT_TX_DW2 */
2430 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2431 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2432 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2433 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2434 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2435 /* Program Rcomp scalar for every table entry */
b265a2a6 2436 val |= RCOMP_SCALAR(0x98);
fb5c8e9d
MN		 2437 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2438
2439 /* Program PORT_TX_DW4 */
2440 /* We cannot write to GRP. It would overwrite individual loadgen. */
2441 for (ln = 0; ln <= 3; ln++) {
9194e42a 2442 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2443 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2444 CURSOR_COEFF_MASK);
b265a2a6
CT		 2445 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2446 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2447 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2448 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d 2449 }
b265a2a6
CT		 2450
2451 /* Program PORT_TX_DW7 */
2452 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2453 val &= ~N_SCALAR_MASK;
2454 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2455 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
fb5c8e9d
MN		 2456}
2457
2458static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2459 u32 level,
2460 enum intel_output_type type)
2461{
2462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2463 enum port port = encoder->port;
2464 int width = 0;
2465 int rate = 0;
2466 u32 val;
2467 int ln = 0;
2468
2469 if (type == INTEL_OUTPUT_HDMI) {
2470 width = 4;
2471 /* Rate is always < than 6GHz for HDMI */
2472 } else {
2473 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2474
2475 width = intel_dp->lane_count;
2476 rate = intel_dp->link_rate;
2477 }
2478
2479 /*
2480 * 1. If port type is eDP or DP,
2481 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2482 * else clear to 0b.
2483 */
2484 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2485 if (type == INTEL_OUTPUT_HDMI)
2486 val &= ~COMMON_KEEPER_EN;
2487 else
2488 val |= COMMON_KEEPER_EN;
2489 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2490
2491 /* 2. Program loadgen select */
2492 /*
2493 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2494 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2495 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2496 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2497 */
2498 for (ln = 0; ln <= 3; ln++) {
9194e42a 2499 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2500 val &= ~LOADGEN_SELECT;
2501
2502 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2503 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2504 val |= LOADGEN_SELECT;
2505 }
9194e42a 2506 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d
MN		 2507 }
2508
2509 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2510 val = I915_READ(ICL_PORT_CL_DW5(port));
2511 val |= SUS_CLOCK_CONFIG;
2512 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2513
2514 /* 4. Clear training enable to change swing values */
2515 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2516 val &= ~TX_TRAINING_EN;
2517 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2518
2519 /* 5. Program swing and de-emphasis */
b265a2a6 2520 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
fb5c8e9d
MN		 2521
2522 /* 6. Set training enable to trigger update */
2523 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2524 val |= TX_TRAINING_EN;
2525 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2526}
2527
07685c82
MN		 2528static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2529 int link_clock,
2530 u32 level)
2531{
2532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2533 enum port port = encoder->port;
2534 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2535 u32 n_entries, val;
2536 int ln;
2537
2538 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2539 ddi_translations = icl_mg_phy_ddi_translations;
2540 /* The table does not have values for level 3 and level 9. */
2541 if (level >= n_entries || level == 3 || level == 9) {
2542 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2543 level, n_entries - 2);
2544 level = n_entries - 2;
2545 }
2546
2547 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2548 for (ln = 0; ln < 2; ln++) {
58106b7d 2549 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2550 val &= ~CRI_USE_FS32;
58106b7d 2551 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2552
58106b7d 2553 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2554 val &= ~CRI_USE_FS32;
58106b7d 2555 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2556 }
2557
2558 /* Program MG_TX_SWINGCTRL with values from vswing table */
2559 for (ln = 0; ln < 2; ln++) {
58106b7d 2560 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2561 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2562 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2563 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2564 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2565
58106b7d 2566 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2567 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2568 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2569 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2570 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2571 }
2572
2573 /* Program MG_TX_DRVCTRL with values from vswing table */
2574 for (ln = 0; ln < 2; ln++) {
58106b7d 2575 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2576 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2577 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2578 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2579 ddi_translations[level].cri_txdeemph_override_5_0) |
2580 CRI_TXDEEMPH_OVERRIDE_11_6(
2581 ddi_translations[level].cri_txdeemph_override_11_6) |
2582 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2583 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2584
58106b7d 2585 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2586 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2587 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2588 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2589 ddi_translations[level].cri_txdeemph_override_5_0) |
2590 CRI_TXDEEMPH_OVERRIDE_11_6(
2591 ddi_translations[level].cri_txdeemph_override_11_6) |
2592 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2593 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2594
2595 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2596 }
2597
2598 /*
2599 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2600 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2601 * values from table for which TX1 and TX2 enabled.
2602 */
2603 for (ln = 0; ln < 2; ln++) {
58106b7d 2604 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2605 if (link_clock < 300000)
2606 val |= CFG_LOW_RATE_LKREN_EN;
2607 else
2608 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2609 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2610 }
2611
2612 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2613 for (ln = 0; ln < 2; ln++) {
58106b7d 2614 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2615 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2616 if (link_clock <= 500000) {
2617 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2618 } else {
2619 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2620 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2621 }
58106b7d 2622 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2623
58106b7d 2624 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2625 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2626 if (link_clock <= 500000) {
2627 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2628 } else {
2629 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2630 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2631 }
58106b7d 2632 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2633 }
2634
2635 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2636 for (ln = 0; ln < 2; ln++) {
58106b7d 2637 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2638 val |= CRI_CALCINIT;
58106b7d 2639 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2640
58106b7d 2641 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2642 val |= CRI_CALCINIT;
58106b7d 2643 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2644 }
2645}
2646
2647static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2648 int link_clock,
2649 u32 level,
fb5c8e9d
MN		 2650 enum intel_output_type type)
2651{
176597a1 2652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2653 enum port port = encoder->port;
2654
176597a1 2655 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2656 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2657 else
07685c82 2658 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2659}
2660
3d0c5005 2661static u32 translate_signal_level(int signal_levels)
f8896f5d 2662{
97eeb872 2663 int i;
f8896f5d 2664
97eeb872
VS		 2665 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2666 if (index_to_dp_signal_levels[i] == signal_levels)
2667 return i;
f8896f5d
DW		 2668 }
2669
97eeb872
VS		 2670 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2671 signal_levels);
2672
2673 return 0;
f8896f5d
DW		 2674}
2675
3d0c5005 2676static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2677{
3d0c5005 2678 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2679 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2680 DP_TRAIN_PRE_EMPHASIS_MASK);
2681
2682 return translate_signal_level(signal_levels);
2683}
2684
d509af6c 2685u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2686{
2687 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2688 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2689 struct intel_encoder *encoder = &dport->base;
d02ace87 2690 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2691
2dd24a9c 2692 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2693 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2694 level, encoder->type);
fb5c8e9d 2695 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2696 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2697 else
7d4f37b5 2698 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2699
2700 return 0;
2701}
2702
3d0c5005 2703u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2704{
2705 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2706 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2707 struct intel_encoder *encoder = &dport->base;
d02ace87 2708 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2709
b976dc53 2710 if (IS_GEN9_BC(dev_priv))
081dfcfa 2711 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2712
f8896f5d
DW		 2713 return DDI_BUF_TRANS_SELECT(level);
2714}
2715
bb1c7edc 2716static inline
3d0c5005
JN		 2717u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2718 enum port port)
bb1c7edc
MK		 2719{
2720 if (intel_port_is_combophy(dev_priv, port)) {
2721 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2722 } else if (intel_port_is_tc(dev_priv, port)) {
2723 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2724
2725 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2726 }
2727
2728 return 0;
2729}
2730
3b8c0d5b
JN		 2731static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2732 const struct intel_crtc_state *crtc_state)
c27e917e 2733{
3b8c0d5b 2734 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2735 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3b8c0d5b
JN		 2736 enum port port = encoder->port;
2737 u32 val;
c27e917e 2738
3b8c0d5b 2739 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2740
3b8c0d5b
JN		 2741 val = I915_READ(DPCLKA_CFGCR0_ICL);
2742 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2743
3b8c0d5b
JN		 2744 if (intel_port_is_combophy(dev_priv, port)) {
2745 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2746 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
c27e917e 2747 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
3b8c0d5b 2748 POSTING_READ(DPCLKA_CFGCR0_ICL);
c27e917e 2749 }
3b8c0d5b
JN		 2750
2751 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2752 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2753
2754 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2755}
2756
3b8c0d5b 2757static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2758{
3b8c0d5b
JN		 2759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2760 enum port port = encoder->port;
2761 u32 val;
c27e917e 2762
3b8c0d5b 2763 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2764
3b8c0d5b
JN		 2765 val = I915_READ(DPCLKA_CFGCR0_ICL);
2766 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2767 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
c27e917e 2768
3b8c0d5b 2769 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2770}
2771
70332ac5
ID		 2772void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2773{
2774 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2775 u32 val;
1dd07e56
ID		 2776 enum port port;
2777 u32 port_mask;
2778 bool ddi_clk_needed;
30f5ccfa
ID		 2779
2780 /*
2781 * In case of DP MST, we sanitize the primary encoder only, not the
2782 * virtual ones.
2783 */
2784 if (encoder->type == INTEL_OUTPUT_DP_MST)
2785 return;
2786
30f5ccfa
ID		 2787 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2788 u8 pipe_mask;
2789 bool is_mst;
2790
2791 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2792 /*
2793 * In the unlikely case that BIOS enables DP in MST mode, just
2794 * warn since our MST HW readout is incomplete.
2795 */
2796 if (WARN_ON(is_mst))
2797 return;
2798 }
70332ac5 2799
1dd07e56
ID		 2800 port_mask = BIT(encoder->port);
2801 ddi_clk_needed = encoder->base.crtc;
70332ac5 2802
1dd07e56
ID		 2803 if (encoder->type == INTEL_OUTPUT_DSI) {
2804 struct intel_encoder *other_encoder;
70332ac5 2805
1dd07e56
ID		 2806 port_mask = intel_dsi_encoder_ports(encoder);
2807 /*
2808 * Sanity check that we haven't incorrectly registered another
2809 * encoder using any of the ports of this DSI encoder.
2810 */
2811 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2812 if (other_encoder == encoder)
2813 continue;
2814
2815 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2816 return;
2817 }
2818 /*
942d1cf4
VK		 2819 * For DSI we keep the ddi clocks gated
2820 * except during enable/disable sequence.
1dd07e56 2821 */
942d1cf4 2822 ddi_clk_needed = false;
1dd07e56
ID		 2823 }
2824
2825 val = I915_READ(DPCLKA_CFGCR0_ICL);
2826 for_each_port_masked(port, port_mask) {
2827 bool ddi_clk_ungated = !(val &
2828 icl_dpclka_cfgcr0_clk_off(dev_priv,
2829 port));
2830
2831 if (ddi_clk_needed == ddi_clk_ungated)
2832 continue;
2833
2834 /*
2835 * Punt on the case now where clock is gated, but it would
2836 * be needed by the port. Something else is really broken then.
2837 */
2838 if (WARN_ON(ddi_clk_needed))
2839 continue;
2840
2841 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2842 port_name(port));
2843 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2844 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2845 }
70332ac5
ID		 2846}
2847
d7c530b2 2848static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2849 const struct intel_crtc_state *crtc_state)
6441ab5f 2850{
e404ba8d 2851 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2852 enum port port = encoder->port;
3d0c5005 2853 u32 val;
0e5fa646 2854 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2855
c856052a
ACO		 2856 if (WARN_ON(!pll))
2857 return;
2858
04bf68bb 2859 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2860
2dd24a9c 2861 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2862 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2863 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2864 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c27e917e 2865 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2866 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2867 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2868 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2869 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2870 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2871
555e38d2
RV		 2872 /*
2873 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2874 * This step and the step before must be done with separate
2875 * register writes.
2876 */
2877 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2878 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2879 I915_WRITE(DPCLKA_CFGCR0, val);
2880 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2881 /* DDI -> PLL mapping */
efa80add
S		 2882 val = I915_READ(DPLL_CTRL2);
2883
2884 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2885 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2886 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2887 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2888
2889 I915_WRITE(DPLL_CTRL2, val);
5416d871 2890
c56b89f1 2891 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2892 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2893 }
8edcda12
RV		 2894
2895 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2896}
2897
6b8506d5
VS		 2898static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2899{
2900 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2901 enum port port = encoder->port;
6b8506d5 2902
2dd24a9c 2903 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2904 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2905 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2906 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2907 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2908 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2909 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2910 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2911 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2912 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2913 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2914 }
6b8506d5
VS		 2915}
2916
cb9ff519
ID		 2917static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2918{
2919 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2920 enum port port = dig_port->base.port;
2921 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2922 u32 val;
9c11b121 2923 int ln;
cb9ff519
ID		 2924
2925 if (tc_port == PORT_TC_NONE)
2926 return;
2927
9c11b121
ID		 2928 for (ln = 0; ln < 2; ln++) {
2929 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2930 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2931 MG_DP_MODE_CFG_TRPWR_GATING |
2932 MG_DP_MODE_CFG_CLNPWR_GATING |
2933 MG_DP_MODE_CFG_DIGPWR_GATING |
2934 MG_DP_MODE_CFG_GAONPWR_GATING;
9c11b121 2935 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2936 }
2937
2938 val = I915_READ(MG_MISC_SUS0(tc_port));
2939 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2940 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2941 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2942 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2943 MG_MISC_SUS0_CFG_TRPWR_GATING |
2944 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2945 MG_MISC_SUS0_CFG_DGPWR_GATING;
2946 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2947}
2948
2949static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2950{
2951 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2952 enum port port = dig_port->base.port;
2953 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2954 u32 val;
9c11b121 2955 int ln;
cb9ff519
ID		 2956
2957 if (tc_port == PORT_TC_NONE)
2958 return;
2959
9c11b121
ID		 2960 for (ln = 0; ln < 2; ln++) {
2961 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2962 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2963 MG_DP_MODE_CFG_TRPWR_GATING |
2964 MG_DP_MODE_CFG_CLNPWR_GATING |
2965 MG_DP_MODE_CFG_DIGPWR_GATING |
2966 MG_DP_MODE_CFG_GAONPWR_GATING);
9c11b121 2967 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2968 }
2969
2970 val = I915_READ(MG_MISC_SUS0(tc_port));
2971 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2972 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2973 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2974 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2975 MG_MISC_SUS0_CFG_TRPWR_GATING |
2976 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2977 MG_MISC_SUS0_CFG_DGPWR_GATING);
2978 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2979}
2980
93b662d3
ID		 2981static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2982{
2983 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2984 enum port port = intel_dig_port->base.port;
2985 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2986 u32 ln0, ln1, lane_info;
2987
2988 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2989 return;
2990
37fc7845
JRS		 2991 ln0 = I915_READ(MG_DP_MODE(0, port));
2992 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3
ID		 2993
2994 switch (intel_dig_port->tc_type) {
2995 case TC_PORT_TYPEC:
2996 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2997 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2998
2999 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3000 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3001 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3002
3003 switch (lane_info) {
3004 case 0x1:
3005 case 0x4:
3006 break;
3007 case 0x2:
3008 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3009 break;
3010 case 0x3:
3011 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012 MG_DP_MODE_CFG_DP_X2_MODE;
3013 break;
3014 case 0x8:
3015 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3016 break;
3017 case 0xC:
3018 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3019 MG_DP_MODE_CFG_DP_X2_MODE;
3020 break;
3021 case 0xF:
3022 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3023 MG_DP_MODE_CFG_DP_X2_MODE;
3024 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3025 MG_DP_MODE_CFG_DP_X2_MODE;
3026 break;
3027 default:
3028 MISSING_CASE(lane_info);
3029 }
3030 break;
3031
3032 case TC_PORT_LEGACY:
3033 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3034 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3035 break;
3036
3037 default:
3038 MISSING_CASE(intel_dig_port->tc_type);
3039 return;
3040 }
3041
37fc7845
JRS		 3042 I915_WRITE(MG_DP_MODE(0, port), ln0);
3043 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3044}
3045
a322b975
AS		 3046static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3047 const struct intel_crtc_state *crtc_state)
3048{
3049 if (!crtc_state->fec_enable)
3050 return;
3051
3052 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3053 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3054}
3055
5c44b938
AS		 3056static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3057 const struct intel_crtc_state *crtc_state)
3058{
3059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3060 enum port port = encoder->port;
3061 u32 val;
3062
3063 if (!crtc_state->fec_enable)
3064 return;
3065
3066 val = I915_READ(DP_TP_CTL(port));
3067 val |= DP_TP_CTL_FEC_ENABLE;
3068 I915_WRITE(DP_TP_CTL(port), val);
3069
97a04e0d 3070 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
5c44b938
AS		 3071 DP_TP_STATUS_FEC_ENABLE_LIVE,
3072 DP_TP_STATUS_FEC_ENABLE_LIVE,
3073 1))
3074 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3075}
3076
d6a09cee
AS		 3077static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3078 const struct intel_crtc_state *crtc_state)
3079{
3080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3081 enum port port = encoder->port;
3082 u32 val;
3083
3084 if (!crtc_state->fec_enable)
3085 return;
3086
3087 val = I915_READ(DP_TP_CTL(port));
3088 val &= ~DP_TP_CTL_FEC_ENABLE;
3089 I915_WRITE(DP_TP_CTL(port), val);
3090 POSTING_READ(DP_TP_CTL(port));
3091}
3092
ba88d153 3093static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3094 const struct intel_crtc_state *crtc_state,
3095 const struct drm_connector_state *conn_state)
e404ba8d 3096{
ba88d153
MN		 3097 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3099 enum port port = encoder->port;
62b69566 3100 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3101 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3102 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3103
45e0327e 3104 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3105
45e0327e
VS		 3106 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3107 crtc_state->lane_count, is_mst);
680b71c2
VS		 3108
3109 intel_edp_panel_on(intel_dp);
32bdc400 3110
0e5fa646 3111 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3112
3113 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3114
93b662d3 3115 icl_program_mg_dp_mode(dig_port);
bc334d91 3116 icl_disable_phy_clock_gating(dig_port);
340a44be 3117
2dd24a9c 3118 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3119 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3120 level, encoder->type);
fb5c8e9d 3121 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3122 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3123 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3124 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3125 else
3a6d84e6 3126 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3127
cfda08cd
ID		 3128 if (intel_port_is_combophy(dev_priv, port)) {
3129 bool lane_reversal =
3130 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3131
3132 intel_combo_phy_power_up_lanes(dev_priv, port, false,
3133 crtc_state->lane_count,
3134 lane_reversal);
3135 }
3136
ba88d153 3137 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3138 if (!is_mst)
3139 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3140 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3141 true);
a322b975 3142 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3143 intel_dp_start_link_train(intel_dp);
3144 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3145 intel_dp_stop_link_train(intel_dp);
afb2c443 3146
5c44b938
AS		 3147 intel_ddi_enable_fec(encoder, crtc_state);
3148
bc334d91
PZ		 3149 icl_enable_phy_clock_gating(dig_port);
3150
2b5cf4ef
ID		 3151 if (!is_mst)
3152 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3153
3154 intel_dsc_enable(encoder, crtc_state);
ba88d153 3155}
901c2daf 3156
ba88d153 3157static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3158 const struct intel_crtc_state *crtc_state,
45e0327e 3159 const struct drm_connector_state *conn_state)
ba88d153 3160{
f99be1b3
VS		 3161 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3162 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3163 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3164 enum port port = encoder->port;
ba88d153 3165 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3166 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3167
ba88d153 3168 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3169 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3170
3171 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3172
93b662d3 3173 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3174 icl_disable_phy_clock_gating(dig_port);
3175
2dd24a9c 3176 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3177 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3178 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3179 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3180 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3181 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3182 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3183 else
7ea79333 3184 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3185
cb9ff519
ID		 3186 icl_enable_phy_clock_gating(dig_port);
3187
2f7460a7 3188 if (IS_GEN9_BC(dev_priv))
081dfcfa 3189 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3190
c7373764
ID		 3191 intel_ddi_enable_pipe_clock(crtc_state);
3192
790ea70c 3193 intel_dig_port->set_infoframes(encoder,
45e0327e 3194 crtc_state->has_infoframe,
f99be1b3 3195 crtc_state, conn_state);
ba88d153 3196}
32bdc400 3197
1524e93e 3198static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3199 const struct intel_crtc_state *crtc_state,
5f88a9c6 3200 const struct drm_connector_state *conn_state)
ba88d153 3201{
45e0327e
VS		 3202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3204 enum pipe pipe = crtc->pipe;
30cf6db8 3205
1939ba51
VS		 3206 /*
3207 * When called from DP MST code:
3208 * - conn_state will be NULL
3209 * - encoder will be the main encoder (ie. mst->primary)
3210 * - the main connector associated with this port
3211 * won't be active or linked to a crtc
3212 * - crtc_state will be the state of the first stream to
3213 * be activated on this port, and it may not be the same
3214 * stream that will be deactivated last, but each stream
3215 * should have a state that is identical when it comes to
3216 * the DP link parameteres
3217 */
3218
45e0327e 3219 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3220
3b8c0d5b
JN		 3221 if (INTEL_GEN(dev_priv) >= 11)
3222 icl_map_plls_to_ports(encoder, crtc_state);
3223
364a3fe1
JN		 3224 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3225
06c812d7 3226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3227 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3228 } else {
3229 struct intel_lspcon *lspcon =
3230 enc_to_intel_lspcon(&encoder->base);
3231
45e0327e 3232 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3233 if (lspcon->active) {
3234 struct intel_digital_port *dig_port =
3235 enc_to_dig_port(&encoder->base);
3236
3237 dig_port->set_infoframes(encoder,
3238 crtc_state->has_infoframe,
3239 crtc_state, conn_state);
3240 }
3241 }
6441ab5f
PZ		 3242}
3243
d6a09cee
AS		 3244static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3245 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3246{
3247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3248 enum port port = encoder->port;
e725f645
VS		 3249 bool wait = false;
3250 u32 val;
3251
3252 val = I915_READ(DDI_BUF_CTL(port));
3253 if (val & DDI_BUF_CTL_ENABLE) {
3254 val &= ~DDI_BUF_CTL_ENABLE;
3255 I915_WRITE(DDI_BUF_CTL(port), val);
3256 wait = true;
3257 }
3258
3259 val = I915_READ(DP_TP_CTL(port));
3260 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3261 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3262 I915_WRITE(DP_TP_CTL(port), val);
3263
d6a09cee
AS		 3264 /* Disable FEC in DP Sink */
3265 intel_ddi_disable_fec_state(encoder, crtc_state);
3266
e725f645
VS		 3267 if (wait)
3268 intel_wait_ddi_buf_idle(dev_priv, port);
3269}
3270
f45f3da7
VS		 3271static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3272 const struct intel_crtc_state *old_crtc_state,
3273 const struct drm_connector_state *old_conn_state)
6441ab5f 3274{
f45f3da7
VS		 3275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3276 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3277 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3278 bool is_mst = intel_crtc_has_type(old_crtc_state,
3279 INTEL_OUTPUT_DP_MST);
2886e93f 3280
2b5cf4ef
ID		 3281 if (!is_mst) {
3282 intel_ddi_disable_pipe_clock(old_crtc_state);
3283 /*
3284 * Power down sink before disabling the port, otherwise we end
3285 * up getting interrupts from the sink on detecting link loss.
3286 */
be1c63c8 3287 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3288 }
c5f93fcf 3289
d6a09cee 3290 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3291
f45f3da7
VS		 3292 intel_edp_panel_vdd_on(intel_dp);
3293 intel_edp_panel_off(intel_dp);
a836bdf9 3294
0e6e0be4
CW		 3295 intel_display_power_put_unchecked(dev_priv,
3296 dig_port->ddi_io_power_domain);
c5f93fcf 3297
f45f3da7
VS		 3298 intel_ddi_clk_disable(encoder);
3299}
c5f93fcf 3300
f45f3da7
VS		 3301static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3302 const struct intel_crtc_state *old_crtc_state,
3303 const struct drm_connector_state *old_conn_state)
3304{
3305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3306 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3307 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3308
790ea70c 3309 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3310 old_crtc_state, old_conn_state);
3311
afb2c443
ID		 3312 intel_ddi_disable_pipe_clock(old_crtc_state);
3313
d6a09cee 3314 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3315
0e6e0be4
CW		 3316 intel_display_power_put_unchecked(dev_priv,
3317 dig_port->ddi_io_power_domain);
b2ccb822 3318
f45f3da7
VS		 3319 intel_ddi_clk_disable(encoder);
3320
3321 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3322}
3323
3324static void intel_ddi_post_disable(struct intel_encoder *encoder,
3325 const struct intel_crtc_state *old_crtc_state,
3326 const struct drm_connector_state *old_conn_state)
3327{
3b8c0d5b
JN		 3328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3329
f45f3da7 3330 /*
1939ba51
VS		 3331 * When called from DP MST code:
3332 * - old_conn_state will be NULL
3333 * - encoder will be the main encoder (ie. mst->primary)
3334 * - the main connector associated with this port
3335 * won't be active or linked to a crtc
3336 * - old_crtc_state will be the state of the last stream to
3337 * be deactivated on this port, and it may not be the same
3338 * stream that was activated last, but each stream
3339 * should have a state that is identical when it comes to
3340 * the DP link parameteres
f45f3da7 3341 */
1939ba51
VS		 3342
3343 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3344 intel_ddi_post_disable_hdmi(encoder,
3345 old_crtc_state, old_conn_state);
3346 else
3347 intel_ddi_post_disable_dp(encoder,
3348 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3349
3350 if (INTEL_GEN(dev_priv) >= 11)
3351 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3352}
3353
1524e93e 3354void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3355 const struct intel_crtc_state *old_crtc_state,
3356 const struct drm_connector_state *old_conn_state)
b7076546 3357{
1524e93e 3358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3359 u32 val;
b7076546
ML		 3360
3361 /*
3362 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3363 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3364 * step 13 is the correct place for it. Step 18 is where it was
3365 * originally before the BUN.
3366 */
3367 val = I915_READ(FDI_RX_CTL(PIPE_A));
3368 val &= ~FDI_RX_ENABLE;
3369 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3370
d6a09cee 3371 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3372 intel_ddi_clk_disable(encoder);
b7076546
ML		 3373
3374 val = I915_READ(FDI_RX_MISC(PIPE_A));
3375 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3376 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3377 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3378
3379 val = I915_READ(FDI_RX_CTL(PIPE_A));
3380 val &= ~FDI_PCDCLK;
3381 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3382
3383 val = I915_READ(FDI_RX_CTL(PIPE_A));
3384 val &= ~FDI_RX_PLL_ENABLE;
3385 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3386}
3387
15d05f0e
VS		 3388static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3389 const struct intel_crtc_state *crtc_state,
3390 const struct drm_connector_state *conn_state)
72662e10 3391{
15d05f0e
VS		 3392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3394 enum port port = encoder->port;
72662e10 3395
15d05f0e
VS		 3396 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3397 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3398
15d05f0e
VS		 3399 intel_edp_backlight_on(crtc_state, conn_state);
3400 intel_psr_enable(intel_dp, crtc_state);
3c053a96 3401 intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
15d05f0e 3402 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3403
15d05f0e
VS		 3404 if (crtc_state->has_audio)
3405 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3406}
3407
8f19b401
ID		 3408static i915_reg_t
3409gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3410 enum port port)
3411{
3412 static const i915_reg_t regs[] = {
3413 [PORT_A] = CHICKEN_TRANS_EDP,
3414 [PORT_B] = CHICKEN_TRANS_A,
3415 [PORT_C] = CHICKEN_TRANS_B,
3416 [PORT_D] = CHICKEN_TRANS_C,
3417 [PORT_E] = CHICKEN_TRANS_A,
3418 };
3419
3420 WARN_ON(INTEL_GEN(dev_priv) < 9);
3421
3422 if (WARN_ON(port < PORT_A || port > PORT_E))
3423 port = PORT_A;
3424
3425 return regs[port];
3426}
3427
15d05f0e
VS		 3428static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3429 const struct intel_crtc_state *crtc_state,
3430 const struct drm_connector_state *conn_state)
3431{
3432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3433 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3434 struct drm_connector *connector = conn_state->connector;
0fce04c8 3435 enum port port = encoder->port;
15d05f0e 3436
277ab5ab
VS		 3437 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3438 crtc_state->hdmi_high_tmds_clock_ratio,
3439 crtc_state->hdmi_scrambling))
3440 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3441 connector->base.id, connector->name);
15d05f0e 3442
0519c102
VS		 3443 /* Display WA #1143: skl,kbl,cfl */
3444 if (IS_GEN9_BC(dev_priv)) {
3445 /*
3446 * For some reason these chicken bits have been
3447 * stuffed into a transcoder register, event though
3448 * the bits affect a specific DDI port rather than
3449 * a specific transcoder.
3450 */
8f19b401 3451 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3452 u32 val;
3453
8f19b401 3454 val = I915_READ(reg);
0519c102
VS		 3455
3456 if (port == PORT_E)
3457 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3458 DDIE_TRAINING_OVERRIDE_VALUE;
3459 else
3460 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3461 DDI_TRAINING_OVERRIDE_VALUE;
3462
8f19b401
ID		 3463 I915_WRITE(reg, val);
3464 POSTING_READ(reg);
0519c102
VS		 3465
3466 udelay(1);
3467
3468 if (port == PORT_E)
3469 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3470 DDIE_TRAINING_OVERRIDE_VALUE);
3471 else
3472 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3473 DDI_TRAINING_OVERRIDE_VALUE);
3474
8f19b401 3475 I915_WRITE(reg, val);
0519c102
VS		 3476 }
3477
15d05f0e
VS		 3478 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3479 * are ignored so nothing special needs to be done besides
3480 * enabling the port.
3481 */
3482 I915_WRITE(DDI_BUF_CTL(port),
3483 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3484
15d05f0e
VS		 3485 if (crtc_state->has_audio)
3486 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3487}
3488
3489static void intel_enable_ddi(struct intel_encoder *encoder,
3490 const struct intel_crtc_state *crtc_state,
3491 const struct drm_connector_state *conn_state)
3492{
3493 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3494 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3495 else
3496 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3497
3498 /* Enable hdcp if it's desired */
3499 if (conn_state->content_protection ==
3500 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3501 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3502}
3503
33f083f0
VS		 3504static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3505 const struct intel_crtc_state *old_crtc_state,
3506 const struct drm_connector_state *old_conn_state)
5ab432ef 3507{
33f083f0 3508 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3509
edb2e530
VS		 3510 intel_dp->link_trained = false;
3511
37255d8d 3512 if (old_crtc_state->has_audio)
8ec47de2
VS		 3513 intel_audio_codec_disable(encoder,
3514 old_crtc_state, old_conn_state);
2831d842 3515
33f083f0
VS		 3516 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3517 intel_psr_disable(intel_dp, old_crtc_state);
3518 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3519 /* Disable the decompression in DP Sink */
3520 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3521 false);
33f083f0 3522}
15953637 3523
33f083f0
VS		 3524static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3525 const struct intel_crtc_state *old_crtc_state,
3526 const struct drm_connector_state *old_conn_state)
3527{
277ab5ab
VS		 3528 struct drm_connector *connector = old_conn_state->connector;
3529
33f083f0 3530 if (old_crtc_state->has_audio)
8ec47de2
VS		 3531 intel_audio_codec_disable(encoder,
3532 old_crtc_state, old_conn_state);
d6c50ff8 3533
277ab5ab
VS		 3534 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3535 false, false))
3536 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3537 connector->base.id, connector->name);
33f083f0
VS		 3538}
3539
3540static void intel_disable_ddi(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *old_crtc_state,
3542 const struct drm_connector_state *old_conn_state)
3543{
ee5e5e7a
SP		 3544 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3545
33f083f0
VS		 3546 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3547 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3548 else
3549 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3550}
79f689aa 3551
2ef82327
HG		 3552static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3553 const struct intel_crtc_state *crtc_state,
3554 const struct drm_connector_state *conn_state)
3555{
3556 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3557
5aa2c9ae
VS		 3558 intel_ddi_set_pipe_settings(crtc_state);
3559
23ec9f52 3560 intel_psr_update(intel_dp, crtc_state);
2ef82327 3561 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3562
3563 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3564}
3565
3566static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3567 const struct intel_crtc_state *crtc_state,
3568 const struct drm_connector_state *conn_state)
3569{
3570 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3571 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1
R		 3572
3573 if (conn_state->content_protection ==
3574 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3575 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3576 else if (conn_state->content_protection ==
3577 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3578 intel_hdcp_disable(to_intel_connector(conn_state->connector));
2ef82327
HG		 3579}
3580
03ad7d88
MN		 3581static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3582 const struct intel_crtc_state *pipe_config,
3583 enum port port)
3584{
3585 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3586 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3587 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3588 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3589 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3590
3591 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3592 switch (pipe_config->lane_count) {
3593 case 1:
3594 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3595 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3596 break;
3597 case 2:
3598 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3599 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3600 break;
3601 case 4:
3602 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3603 break;
3604 default:
3605 MISSING_CASE(pipe_config->lane_count);
3606 }
3607 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3608}
3609
bdaa29b6
ID		 3610static void
3611intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3612 const struct intel_crtc_state *crtc_state,
3613 const struct drm_connector_state *conn_state)
03ad7d88 3614{
bdaa29b6 3615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3616 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bdaa29b6
ID		 3617 enum port port = encoder->port;
3618
8e4a3ad9
ID		 3619 if (intel_crtc_has_dp_encoder(crtc_state) ||
3620 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6
ID		 3621 intel_display_power_get(dev_priv,
3622 intel_ddi_main_link_aux_domain(dig_port));
3623
3624 if (IS_GEN9_LP(dev_priv))
3625 bxt_ddi_phy_set_lane_optim_mask(encoder,
3626 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3627
3628 /*
3629 * Program the lane count for static/dynamic connections on Type-C ports.
3630 * Skip this step for TBT.
3631 */
3632 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3633 dig_port->tc_type == TC_PORT_TBT)
3634 return;
3635
bdaa29b6
ID		 3636 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3637}
3638
3639static void
3640intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3641 const struct intel_crtc_state *crtc_state,
3642 const struct drm_connector_state *conn_state)
3643{
3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3645 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3646
3647 if (intel_crtc_has_dp_encoder(crtc_state) ||
3648 intel_port_is_tc(dev_priv, encoder->port))
0e6e0be4
CW		 3649 intel_display_power_put_unchecked(dev_priv,
3650 intel_ddi_main_link_aux_domain(dig_port));
03ad7d88
MN		 3651}
3652
ad64217b 3653void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3654{
ad64217b
ACO		 3655 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3656 struct drm_i915_private *dev_priv =
3657 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3658 enum port port = intel_dig_port->base.port;
3d0c5005 3659 u32 val;
f3e227df 3660 bool wait = false;
c19b0669
PZ		 3661
3662 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3663 val = I915_READ(DDI_BUF_CTL(port));
3664 if (val & DDI_BUF_CTL_ENABLE) {
3665 val &= ~DDI_BUF_CTL_ENABLE;
3666 I915_WRITE(DDI_BUF_CTL(port), val);
3667 wait = true;
3668 }
3669
3670 val = I915_READ(DP_TP_CTL(port));
3671 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3672 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3673 I915_WRITE(DP_TP_CTL(port), val);
3674 POSTING_READ(DP_TP_CTL(port));
3675
3676 if (wait)
3677 intel_wait_ddi_buf_idle(dev_priv, port);
3678 }
3679
0e32b39c 3680 val = DP_TP_CTL_ENABLE |
c19b0669 3681 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3682 if (intel_dp->link_mst)
0e32b39c
DA		 3683 val |= DP_TP_CTL_MODE_MST;
3684 else {
3685 val |= DP_TP_CTL_MODE_SST;
3686 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3687 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3688 }
c19b0669
PZ		 3689 I915_WRITE(DP_TP_CTL(port), val);
3690 POSTING_READ(DP_TP_CTL(port));
3691
3692 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3693 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3694 POSTING_READ(DDI_BUF_CTL(port));
3695
3696 udelay(600);
3697}
00c09d70 3698
2085cc5d
VS		 3699static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3700 enum transcoder cpu_transcoder)
9935f7fa 3701{
2085cc5d
VS		 3702 if (cpu_transcoder == TRANSCODER_EDP)
3703 return false;
9935f7fa 3704
2085cc5d
VS		 3705 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3706 return false;
3707
3708 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3709 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3710}
3711
53e9bf5e
VS		 3712void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3713 struct intel_crtc_state *crtc_state)
3714{
2dd24a9c 3715 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3716 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3717 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3718 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3719}
3720
6801c18c 3721void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3722 struct intel_crtc_state *pipe_config)
045ac3b5 3723{
fac5e23e 3724 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3725 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3726 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3727 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3728 u32 temp, flags = 0;
3729
4d1de975
JN		 3730 /* XXX: DSI transcoder paranoia */
3731 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3732 return;
3733
045ac3b5
JB		 3734 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3735 if (temp & TRANS_DDI_PHSYNC)
3736 flags |= DRM_MODE_FLAG_PHSYNC;
3737 else
3738 flags |= DRM_MODE_FLAG_NHSYNC;
3739 if (temp & TRANS_DDI_PVSYNC)
3740 flags |= DRM_MODE_FLAG_PVSYNC;
3741 else
3742 flags |= DRM_MODE_FLAG_NVSYNC;
3743
2d112de7 3744 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3745
3746 switch (temp & TRANS_DDI_BPC_MASK) {
3747 case TRANS_DDI_BPC_6:
3748 pipe_config->pipe_bpp = 18;
3749 break;
3750 case TRANS_DDI_BPC_8:
3751 pipe_config->pipe_bpp = 24;
3752 break;
3753 case TRANS_DDI_BPC_10:
3754 pipe_config->pipe_bpp = 30;
3755 break;
3756 case TRANS_DDI_BPC_12:
3757 pipe_config->pipe_bpp = 36;
3758 break;
3759 default:
3760 break;
3761 }
eb14cb74
VS		 3762
3763 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3764 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3765 pipe_config->has_hdmi_sink = true;
f99be1b3 3766 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3767
e5e70d4a
VS		 3768 pipe_config->infoframes.enable |=
3769 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3770
3771 if (pipe_config->infoframes.enable)
bbd440fb 3772 pipe_config->has_infoframe = true;
15953637 3773
ab2cb2cb 3774 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 3775 pipe_config->hdmi_scrambling = true;
3776 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3777 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3778 /* fall through */
eb14cb74 3779 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3780 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3781 pipe_config->lane_count = 4;
3782 break;
eb14cb74 3783 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3784 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3785 break;
3786 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3787 if (encoder->type == INTEL_OUTPUT_EDP)
3788 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3789 else
3790 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3791 pipe_config->lane_count =
3792 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3793 intel_dp_get_m_n(intel_crtc, pipe_config);
3794 break;
eb14cb74 3795 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3796 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3797 pipe_config->lane_count =
3798 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3799 intel_dp_get_m_n(intel_crtc, pipe_config);
3800 break;
3801 default:
3802 break;
3803 }
10214420 3804
9935f7fa 3805 pipe_config->has_audio =
2085cc5d 3806 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3807
6aa23e65
JN		 3808 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3809 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3810 /*
3811 * This is a big fat ugly hack.
3812 *
3813 * Some machines in UEFI boot mode provide us a VBT that has 18
3814 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3815 * unknown we fail to light up. Yet the same BIOS boots up with
3816 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3817 * max, not what it tells us to use.
3818 *
3819 * Note: This will still be broken if the eDP panel is not lit
3820 * up by the BIOS, and thus we can't get the mode at module
3821 * load.
3822 */
3823 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3824 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3825 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3826 }
11578553 3827
22606a18 3828 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3829
cc3f90f0 3830 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3831 pipe_config->lane_lat_optim_mask =
3832 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3833
3834 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 3835
3836 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3837
3838 intel_read_infoframe(encoder, pipe_config,
3839 HDMI_INFOFRAME_TYPE_AVI,
3840 &pipe_config->infoframes.avi);
3841 intel_read_infoframe(encoder, pipe_config,
3842 HDMI_INFOFRAME_TYPE_SPD,
3843 &pipe_config->infoframes.spd);
3844 intel_read_infoframe(encoder, pipe_config,
3845 HDMI_INFOFRAME_TYPE_VENDOR,
3846 &pipe_config->infoframes.hdmi);
045ac3b5
JB		 3847}
3848
7e732cac
VS		 3849static enum intel_output_type
3850intel_ddi_compute_output_type(struct intel_encoder *encoder,
3851 struct intel_crtc_state *crtc_state,
3852 struct drm_connector_state *conn_state)
3853{
3854 switch (conn_state->connector->connector_type) {
3855 case DRM_MODE_CONNECTOR_HDMIA:
3856 return INTEL_OUTPUT_HDMI;
3857 case DRM_MODE_CONNECTOR_eDP:
3858 return INTEL_OUTPUT_EDP;
3859 case DRM_MODE_CONNECTOR_DisplayPort:
3860 return INTEL_OUTPUT_DP;
3861 default:
3862 MISSING_CASE(conn_state->connector->connector_type);
3863 return INTEL_OUTPUT_UNUSED;
3864 }
3865}
3866
204474a6
LP		 3867static int intel_ddi_compute_config(struct intel_encoder *encoder,
3868 struct intel_crtc_state *pipe_config,
3869 struct drm_connector_state *conn_state)
00c09d70 3870{
dc0c0bfe 3871 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
fac5e23e 3872 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3873 enum port port = encoder->port;
95a7a2ae 3874 int ret;
00c09d70 3875
bc7e3525 3876 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 3877 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3878
7e732cac 3879 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3880 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3881 else
0a478c27 3882 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
7a412b8f
VS		 3883 if (ret)
3884 return ret;
95a7a2ae 3885
dc0c0bfe
VS		 3886 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3887 pipe_config->cpu_transcoder == TRANSCODER_EDP)
3888 pipe_config->pch_pfit.force_thru =
3889 pipe_config->pch_pfit.enabled ||
3890 pipe_config->crc_enabled;
3891
7a412b8f 3892 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3893 pipe_config->lane_lat_optim_mask =
5161d058 3894 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3895
53e9bf5e
VS		 3896 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3897
7a412b8f 3898 return 0;
00c09d70
PZ		 3899}
3900
f6bff60e
ID		 3901static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3902{
3903 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3904 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3905
3906 intel_dp_encoder_suspend(encoder);
3907
3908 /*
3909 * TODO: disconnect also from USB DP alternate mode once we have a
3910 * way to handle the modeset restore in that mode during resume
3911 * even if the sink has disappeared while being suspended.
3912 */
3913 if (dig_port->tc_legacy_port)
3914 icl_tc_phy_disconnect(i915, dig_port);
3915}
3916
3917static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3918{
3919 struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3920 struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3921
3922 if (intel_port_is_tc(i915, dig_port->base.port))
3923 intel_digital_port_connected(&dig_port->base);
3924
3925 intel_dp_encoder_reset(drm_encoder);
3926}
3927
3928static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3929{
3930 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3931 struct drm_i915_private *i915 = to_i915(encoder->dev);
3932
3933 intel_dp_encoder_flush_work(encoder);
3934
3935 if (intel_port_is_tc(i915, dig_port->base.port))
3936 icl_tc_phy_disconnect(i915, dig_port);
3937
3938 drm_encoder_cleanup(encoder);
3939 kfree(dig_port);
3940}
3941
00c09d70 3942static const struct drm_encoder_funcs intel_ddi_funcs = {
f6bff60e
ID		 3943 .reset = intel_ddi_encoder_reset,
3944 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 3945};
3946
4a28ae58
PZ		 3947static struct intel_connector *
3948intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3949{
3950 struct intel_connector *connector;
8f4f2797 3951 enum port port = intel_dig_port->base.port;
4a28ae58 3952
9bdbd0b9 3953 connector = intel_connector_alloc();
4a28ae58
PZ		 3954 if (!connector)
3955 return NULL;
3956
3957 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3958 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3959 kfree(connector);
3960 return NULL;
3961 }
3962
3963 return connector;
3964}
3965
dba14b27
VS		 3966static int modeset_pipe(struct drm_crtc *crtc,
3967 struct drm_modeset_acquire_ctx *ctx)
3968{
3969 struct drm_atomic_state *state;
3970 struct drm_crtc_state *crtc_state;
3971 int ret;
3972
3973 state = drm_atomic_state_alloc(crtc->dev);
3974 if (!state)
3975 return -ENOMEM;
3976
3977 state->acquire_ctx = ctx;
3978
3979 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3980 if (IS_ERR(crtc_state)) {
3981 ret = PTR_ERR(crtc_state);
3982 goto out;
3983 }
3984
b8fe992a 3985 crtc_state->connectors_changed = true;
dba14b27 3986
dba14b27 3987 ret = drm_atomic_commit(state);
a551cd66 3988out:
dba14b27
VS		 3989 drm_atomic_state_put(state);
3990
3991 return ret;
3992}
3993
3994static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3995 struct drm_modeset_acquire_ctx *ctx)
3996{
3997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3998 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3999 struct intel_connector *connector = hdmi->attached_connector;
4000 struct i2c_adapter *adapter =
4001 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4002 struct drm_connector_state *conn_state;
4003 struct intel_crtc_state *crtc_state;
4004 struct intel_crtc *crtc;
4005 u8 config;
4006 int ret;
4007
4008 if (!connector || connector->base.status != connector_status_connected)
4009 return 0;
4010
4011 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4012 ctx);
4013 if (ret)
4014 return ret;
4015
4016 conn_state = connector->base.state;
4017
4018 crtc = to_intel_crtc(conn_state->crtc);
4019 if (!crtc)
4020 return 0;
4021
4022 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4023 if (ret)
4024 return ret;
4025
4026 crtc_state = to_intel_crtc_state(crtc->base.state);
4027
4028 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4029
4030 if (!crtc_state->base.active)
4031 return 0;
4032
4033 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4034 !crtc_state->hdmi_scrambling)
4035 return 0;
4036
4037 if (conn_state->commit &&
4038 !try_wait_for_completion(&conn_state->commit->hw_done))
4039 return 0;
4040
4041 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4042 if (ret < 0) {
4043 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4044 return 0;
4045 }
4046
4047 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4048 crtc_state->hdmi_high_tmds_clock_ratio &&
4049 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4050 crtc_state->hdmi_scrambling)
4051 return 0;
4052
4053 /*
4054 * HDMI 2.0 says that one should not send scrambled data
4055 * prior to configuring the sink scrambling, and that
4056 * TMDS clock/data transmission should be suspended when
4057 * changing the TMDS clock rate in the sink. So let's
4058 * just do a full modeset here, even though some sinks
4059 * would be perfectly happy if were to just reconfigure
4060 * the SCDC settings on the fly.
4061 */
4062 return modeset_pipe(&crtc->base, ctx);
4063}
4064
4065static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4066 struct intel_connector *connector)
4067{
4068 struct drm_modeset_acquire_ctx ctx;
4069 bool changed;
4070 int ret;
4071
4072 changed = intel_encoder_hotplug(encoder, connector);
4073
4074 drm_modeset_acquire_init(&ctx, 0);
4075
4076 for (;;) {
c85d200e
VS		 4077 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4078 ret = intel_hdmi_reset_link(encoder, &ctx);
4079 else
4080 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4081
4082 if (ret == -EDEADLK) {
4083 drm_modeset_backoff(&ctx);
4084 continue;
4085 }
4086
4087 break;
4088 }
4089
4090 drm_modeset_drop_locks(&ctx);
4091 drm_modeset_acquire_fini(&ctx);
4092 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4093
4094 return changed;
4095}
4096
4a28ae58
PZ		 4097static struct intel_connector *
4098intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4099{
4100 struct intel_connector *connector;
8f4f2797 4101 enum port port = intel_dig_port->base.port;
4a28ae58 4102
9bdbd0b9 4103 connector = intel_connector_alloc();
4a28ae58
PZ		 4104 if (!connector)
4105 return NULL;
4106
4107 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4108 intel_hdmi_init_connector(intel_dig_port, connector);
4109
4110 return connector;
4111}
4112
436009b5
RV		 4113static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4114{
4115 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4116
8f4f2797 4117 if (dport->base.port != PORT_A)
436009b5
RV		 4118 return false;
4119
4120 if (dport->saved_port_bits & DDI_A_4_LANES)
4121 return false;
4122
4123 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4124 * supported configuration
4125 */
4126 if (IS_GEN9_LP(dev_priv))
4127 return true;
4128
4129 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4130 * one who does also have a full A/E split called
4131 * DDI_F what makes DDI_E useless. However for this
4132 * case let's trust VBT info.
4133 */
4134 if (IS_CANNONLAKE(dev_priv) &&
4135 !intel_bios_is_port_present(dev_priv, PORT_E))
4136 return true;
4137
4138 return false;
4139}
4140
3d2011cf
MK		 4141static int
4142intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4143{
4144 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4145 enum port port = intel_dport->base.port;
4146 int max_lanes = 4;
4147
4148 if (INTEL_GEN(dev_priv) >= 11)
4149 return max_lanes;
4150
4151 if (port == PORT_A || port == PORT_E) {
4152 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4153 max_lanes = port == PORT_A ? 4 : 0;
4154 else
4155 /* Both A and E share 2 lanes */
4156 max_lanes = 2;
4157 }
4158
4159 /*
4160 * Some BIOS might fail to set this bit on port A if eDP
4161 * wasn't lit up at boot. Force this bit set when needed
4162 * so we use the proper lane count for our calculations.
4163 */
4164 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4165 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4166 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4167 max_lanes = 4;
4168 }
4169
4170 return max_lanes;
4171}
4172
c39055b0 4173void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4174{
f6bff60e
ID		 4175 struct ddi_vbt_port_info *port_info =
4176 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4177 struct intel_digital_port *intel_dig_port;
4178 struct intel_encoder *intel_encoder;
4179 struct drm_encoder *encoder;
ff662124 4180 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4181 enum pipe pipe;
10e7bec3 4182
f6bff60e
ID		 4183 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4184 init_dp = port_info->supports_dp;
ff662124
SS		 4185
4186 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4187 /*
4188 * Lspcon device needs to be driven with DP connector
4189 * with special detection sequence. So make sure DP
4190 * is initialized before lspcon.
4191 */
4192 init_dp = true;
4193 init_lspcon = true;
4194 init_hdmi = false;
4195 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4196 }
4197
311a2094 4198 if (!init_dp && !init_hdmi) {
500ea70d 4199 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4200 port_name(port));
500ea70d 4201 return;
311a2094 4202 }
00c09d70 4203
b14c5679 4204 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4205 if (!intel_dig_port)
4206 return;
4207
00c09d70
PZ		 4208 intel_encoder = &intel_dig_port->base;
4209 encoder = &intel_encoder->base;
4210
c39055b0 4211 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4212 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4213
c85d200e 4214 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4215 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4216 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4217 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4218 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4219 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4220 intel_encoder->pre_enable = intel_ddi_pre_enable;
4221 intel_encoder->disable = intel_disable_ddi;
4222 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4223 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4224 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4225 intel_encoder->get_config = intel_ddi_get_config;
f6bff60e 4226 intel_encoder->suspend = intel_ddi_encoder_suspend;
62b69566 4227 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4228 intel_encoder->type = INTEL_OUTPUT_DDI;
4229 intel_encoder->power_domain = intel_port_to_power_domain(port);
4230 intel_encoder->port = port;
3d2011cf 4231 intel_encoder->cloneable = 0;
570b16b5
MK		 4232 for_each_pipe(dev_priv, pipe)
4233 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4234
1e6aa7e5
JN		 4235 if (INTEL_GEN(dev_priv) >= 11)
4236 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4237 DDI_BUF_PORT_REVERSAL;
4238 else
4239 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4240 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4241 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4242 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4243 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4244
f6bff60e
ID		 4245 intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4246 !port_info->supports_typec_usb &&
4247 !port_info->supports_tbt;
4248
62b69566
ACO		 4249 switch (port) {
4250 case PORT_A:
4251 intel_dig_port->ddi_io_power_domain =
4252 POWER_DOMAIN_PORT_DDI_A_IO;
4253 break;
4254 case PORT_B:
4255 intel_dig_port->ddi_io_power_domain =
4256 POWER_DOMAIN_PORT_DDI_B_IO;
4257 break;
4258 case PORT_C:
4259 intel_dig_port->ddi_io_power_domain =
4260 POWER_DOMAIN_PORT_DDI_C_IO;
4261 break;
4262 case PORT_D:
4263 intel_dig_port->ddi_io_power_domain =
4264 POWER_DOMAIN_PORT_DDI_D_IO;
4265 break;
4266 case PORT_E:
4267 intel_dig_port->ddi_io_power_domain =
4268 POWER_DOMAIN_PORT_DDI_E_IO;
4269 break;
9787e835
RV		 4270 case PORT_F:
4271 intel_dig_port->ddi_io_power_domain =
4272 POWER_DOMAIN_PORT_DDI_F_IO;
4273 break;
62b69566
ACO		 4274 default:
4275 MISSING_CASE(port);
4276 }
4277
f68d697e
CW		 4278 if (init_dp) {
4279 if (!intel_ddi_init_dp_connector(intel_dig_port))
4280 goto err;
13cf5504 4281
f68d697e 4282 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4283 }
21a8e6a4 4284
311a2094
PZ		 4285 /* In theory we don't need the encoder->type check, but leave it just in
4286 * case we have some really bad VBTs... */
f68d697e
CW		 4287 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4288 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4289 goto err;
21a8e6a4 4290 }
f68d697e 4291
ff662124
SS		 4292 if (init_lspcon) {
4293 if (lspcon_init(intel_dig_port))
4294 /* TODO: handle hdmi info frame part */
4295 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4296 port_name(port));
4297 else
4298 /*
4299 * LSPCON init faied, but DP init was success, so
4300 * lets try to drive as DP++ port.
4301 */
4302 DRM_ERROR("LSPCON init failed on port %c\n",
4303 port_name(port));
4304 }
4305
06c812d7 4306 intel_infoframe_init(intel_dig_port);
f6bff60e
ID		 4307
4308 if (intel_port_is_tc(dev_priv, port))
4309 intel_digital_port_connected(intel_encoder);
4310
f68d697e
CW		 4311 return;
4312
4313err:
4314 drm_encoder_cleanup(encoder);
4315 kfree(intel_dig_port);
00c09d70 4316}
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