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drm/i915: Extract intel_ddi_clk_disable()
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b 303struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 304 u8 margin; /* swing value */
305 u8 scale; /* scale value */
306 u8 enable; /* scale enable */
307 u8 deemphasis;
96fb9f9b
VK		 308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4 356struct cnl_ddi_buf_trans {
fb5f4e96
VS		 357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
83fb7ab4
RV		 362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
da411a48 547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
da411a48
RV		 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
f8896f5d 565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 566 return skl_u_ddi_translations_edp;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 569 return skl_ddi_translations_edp;
f8896f5d
DW		 570 }
571 }
cd1101cb 572
da411a48 573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 577}
578
579static const struct ddi_buf_trans *
78ab0bae 580skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 581{
78ab0bae 582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 584 return skl_y_ddi_translations_hdmi;
f8896f5d 585 } else {
f8896f5d 586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 587 return skl_ddi_translations_hdmi;
f8896f5d 588 }
f8896f5d
DW		 589}
590
cf3e0fb4
RV		 591static const struct cnl_ddi_buf_trans *
592cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
593{
594 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
595
596 if (voltage == VOLTAGE_INFO_0_85V) {
597 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
598 return cnl_ddi_translations_hdmi_0_85V;
599 } else if (voltage == VOLTAGE_INFO_0_95V) {
600 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
601 return cnl_ddi_translations_hdmi_0_95V;
602 } else if (voltage == VOLTAGE_INFO_1_05V) {
603 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
604 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 605 } else {
606 *n_entries = 1; /* shut up gcc */
cf3e0fb4 607 MISSING_CASE(voltage);
83482ca3 608 }
cf3e0fb4
RV		 609 return NULL;
610}
611
612static const struct cnl_ddi_buf_trans *
613cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
614{
615 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
616
617 if (voltage == VOLTAGE_INFO_0_85V) {
618 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
619 return cnl_ddi_translations_dp_0_85V;
620 } else if (voltage == VOLTAGE_INFO_0_95V) {
621 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
622 return cnl_ddi_translations_dp_0_95V;
623 } else if (voltage == VOLTAGE_INFO_1_05V) {
624 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
625 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 626 } else {
627 *n_entries = 1; /* shut up gcc */
cf3e0fb4 628 MISSING_CASE(voltage);
83482ca3 629 }
cf3e0fb4
RV		 630 return NULL;
631}
632
633static const struct cnl_ddi_buf_trans *
634cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
635{
636 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
637
638 if (dev_priv->vbt.edp.low_vswing) {
639 if (voltage == VOLTAGE_INFO_0_85V) {
640 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
641 return cnl_ddi_translations_edp_0_85V;
642 } else if (voltage == VOLTAGE_INFO_0_95V) {
643 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
644 return cnl_ddi_translations_edp_0_95V;
645 } else if (voltage == VOLTAGE_INFO_1_05V) {
646 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
647 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 648 } else {
649 *n_entries = 1; /* shut up gcc */
cf3e0fb4 650 MISSING_CASE(voltage);
83482ca3 651 }
cf3e0fb4
RV		 652 return NULL;
653 } else {
654 return cnl_get_buf_trans_dp(dev_priv, n_entries);
655 }
656}
657
8d8bb85e
VS		 658static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
659{
660 int n_hdmi_entries;
661 int hdmi_level;
662 int hdmi_default_entry;
663
664 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
665
cc3f90f0 666 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 667 return hdmi_level;
668
bf503556
RV		 669 if (IS_CANNONLAKE(dev_priv)) {
670 cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
671 hdmi_default_entry = n_hdmi_entries - 1;
672 } else if (IS_GEN9_BC(dev_priv)) {
8d8bb85e
VS		 673 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
674 hdmi_default_entry = 8;
675 } else if (IS_BROADWELL(dev_priv)) {
676 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
677 hdmi_default_entry = 7;
678 } else if (IS_HASWELL(dev_priv)) {
679 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
680 hdmi_default_entry = 6;
681 } else {
682 WARN(1, "ddi translation table missing\n");
683 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
684 hdmi_default_entry = 7;
685 }
686
687 /* Choose a good default if VBT is badly populated */
688 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
689 hdmi_level >= n_hdmi_entries)
690 hdmi_level = hdmi_default_entry;
691
692 return hdmi_level;
693}
694
7d1c42e6
VS		 695static const struct ddi_buf_trans *
696intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
697 int *n_entries)
698{
da411a48 699 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
7d1c42e6
VS		 700 return kbl_get_buf_trans_dp(dev_priv, n_entries);
701 } else if (IS_SKYLAKE(dev_priv)) {
702 return skl_get_buf_trans_dp(dev_priv, n_entries);
703 } else if (IS_BROADWELL(dev_priv)) {
704 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
705 return bdw_ddi_translations_dp;
706 } else if (IS_HASWELL(dev_priv)) {
707 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
708 return hsw_ddi_translations_dp;
709 }
710
711 *n_entries = 0;
712 return NULL;
713}
714
715static const struct ddi_buf_trans *
716intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
717 int *n_entries)
718{
da411a48 719 if (IS_GEN9_BC(dev_priv)) {
7d1c42e6
VS		 720 return skl_get_buf_trans_edp(dev_priv, n_entries);
721 } else if (IS_BROADWELL(dev_priv)) {
722 return bdw_get_buf_trans_edp(dev_priv, n_entries);
723 } else if (IS_HASWELL(dev_priv)) {
724 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
725 return hsw_ddi_translations_dp;
726 }
727
728 *n_entries = 0;
729 return NULL;
730}
731
732static const struct ddi_buf_trans *
733intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
734 int *n_entries)
735{
736 if (IS_BROADWELL(dev_priv)) {
737 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
738 return hsw_ddi_translations_fdi;
739 } else if (IS_HASWELL(dev_priv)) {
740 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
741 return hsw_ddi_translations_fdi;
742 }
743
744 *n_entries = 0;
745 return NULL;
746}
747
e58623cb
AR		 748/*
749 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 750 * values in advance. This function programs the correct values for
751 * DP/eDP/FDI use cases.
45244b87 752 */
d7c530b2 753static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 754{
6a7e4f99 755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 756 u32 iboost_bit = 0;
7d1c42e6 757 int i, n_entries;
32bdc400 758 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 759 const struct ddi_buf_trans *ddi_translations;
e58623cb 760
7d1c42e6
VS		 761 switch (encoder->type) {
762 case INTEL_OUTPUT_EDP:
763 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
764 &n_entries);
765 break;
766 case INTEL_OUTPUT_DP:
767 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
768 &n_entries);
769 break;
770 case INTEL_OUTPUT_ANALOG:
771 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
772 &n_entries);
773 break;
774 default:
775 MISSING_CASE(encoder->type);
776 return;
e58623cb
AR		 777 }
778
b976dc53 779 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 780 /* If we're boosting the current, set bit 31 of trans1 */
781 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
782 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
783
784 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
785 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 786 n_entries > 9))
787 n_entries = 9;
300644c7 788 }
45244b87 789
7d1c42e6 790 for (i = 0; i < n_entries; i++) {
9712e688
VS		 791 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
792 ddi_translations[i].trans1 | iboost_bit);
793 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
794 ddi_translations[i].trans2);
45244b87 795 }
32bdc400
VS		 796}
797
798/*
799 * Starting with Haswell, DDI port buffers must be programmed with correct
800 * values in advance. This function programs the correct values for
801 * HDMI/DVI use cases.
802 */
803static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
804{
805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
806 u32 iboost_bit = 0;
807 int n_hdmi_entries, hdmi_level;
808 enum port port = intel_ddi_get_encoder_port(encoder);
809 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 810
32bdc400
VS		 811 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
812
b976dc53 813 if (IS_GEN9_BC(dev_priv)) {
32bdc400 814 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 815
32bdc400 816 /* If we're boosting the current, set bit 31 of trans1 */
1edaaa2f 817 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
32bdc400
VS		 818 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
819 } else if (IS_BROADWELL(dev_priv)) {
820 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
821 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
822 } else if (IS_HASWELL(dev_priv)) {
823 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
824 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
825 } else {
826 WARN(1, "ddi translation table missing\n");
827 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
828 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
829 }
830
6acab15a 831 /* Entry 9 is for HDMI: */
ed9c77d2 832 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 833 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 834 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 835 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 836}
837
248138b5
PZ		 838static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
839 enum port port)
840{
f0f59a00 841 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 842 int i;
843
3449ca85 844 for (i = 0; i < 16; i++) {
248138b5
PZ		 845 udelay(1);
846 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
847 return;
848 }
849 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
850}
c82e4d26 851
5f88a9c6 852static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a
ACO		 853{
854 switch (pll->id) {
855 case DPLL_ID_WRPLL1:
856 return PORT_CLK_SEL_WRPLL1;
857 case DPLL_ID_WRPLL2:
858 return PORT_CLK_SEL_WRPLL2;
859 case DPLL_ID_SPLL:
860 return PORT_CLK_SEL_SPLL;
861 case DPLL_ID_LCPLL_810:
862 return PORT_CLK_SEL_LCPLL_810;
863 case DPLL_ID_LCPLL_1350:
864 return PORT_CLK_SEL_LCPLL_1350;
865 case DPLL_ID_LCPLL_2700:
866 return PORT_CLK_SEL_LCPLL_2700;
867 default:
868 MISSING_CASE(pll->id);
869 return PORT_CLK_SEL_NONE;
870 }
871}
872
c82e4d26
ED		 873/* Starting with Haswell, different DDI ports can work in FDI mode for
874 * connection to the PCH-located connectors. For this, it is necessary to train
875 * both the DDI port and PCH receiver for the desired DDI buffer settings.
876 *
877 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
878 * please note that when FDI mode is active on DDI E, it shares 2 lines with
879 * DDI A (which is used for eDP)
880 */
881
dc4a1094
ACO		 882void hsw_fdi_link_train(struct intel_crtc *crtc,
883 const struct intel_crtc_state *crtc_state)
c82e4d26 884{
4cbe4b2b 885 struct drm_device *dev = crtc->base.dev;
fac5e23e 886 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 887 struct intel_encoder *encoder;
c856052a 888 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 889
4cbe4b2b 890 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 891 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 892 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 893 }
894
04945641
PZ		 895 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
896 * mode set "sequence for CRT port" document:
897 * - TP1 to TP2 time with the default value
898 * - FDI delay to 90h
8693a824
DL		 899 *
900 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 901 */
eede3b53 902 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 903 FDI_RX_PWRDN_LANE0_VAL(2) |
904 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
905
906 /* Enable the PCH Receiver FDI PLL */
3e68320e 907 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 908 FDI_RX_PLL_ENABLE |
dc4a1094 909 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 910 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
911 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 912 udelay(220);
913
914 /* Switch from Rawclk to PCDclk */
915 rx_ctl_val |= FDI_PCDCLK;
eede3b53 916 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 917
918 /* Configure Port Clock Select */
dc4a1094 919 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 920 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
921 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 922
923 /* Start the training iterating through available voltages and emphasis,
924 * testing each value twice. */
10122051 925 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 926 /* Configure DP_TP_CTL with auto-training */
927 I915_WRITE(DP_TP_CTL(PORT_E),
928 DP_TP_CTL_FDI_AUTOTRAIN |
929 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
930 DP_TP_CTL_LINK_TRAIN_PAT1 |
931 DP_TP_CTL_ENABLE);
932
876a8cdf
DL		 933 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
934 * DDI E does not support port reversal, the functionality is
935 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
936 * port reversal bit */
c82e4d26 937 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 938 DDI_BUF_CTL_ENABLE |
dc4a1094 939 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 940 DDI_BUF_TRANS_SELECT(i / 2));
04945641 941 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 942
943 udelay(600);
944
04945641 945 /* Program PCH FDI Receiver TU */
eede3b53 946 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 947
948 /* Enable PCH FDI Receiver with auto-training */
949 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 950 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
951 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 952
953 /* Wait for FDI receiver lane calibration */
954 udelay(30);
955
956 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 957 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 958 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 959 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
960 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 961
962 /* Wait for FDI auto training time */
963 udelay(5);
c82e4d26
ED		 964
965 temp = I915_READ(DP_TP_STATUS(PORT_E));
966 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 967 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 968 break;
969 }
c82e4d26 970
a308ccb3
VS		 971 /*
972 * Leave things enabled even if we failed to train FDI.
973 * Results in less fireworks from the state checker.
974 */
975 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
976 DRM_ERROR("FDI link training failed!\n");
977 break;
c82e4d26 978 }
04945641 979
5b421c57
VS		 980 rx_ctl_val &= ~FDI_RX_ENABLE;
981 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
982 POSTING_READ(FDI_RX_CTL(PIPE_A));
983
248138b5
PZ		 984 temp = I915_READ(DDI_BUF_CTL(PORT_E));
985 temp &= ~DDI_BUF_CTL_ENABLE;
986 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
987 POSTING_READ(DDI_BUF_CTL(PORT_E));
988
04945641 989 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 990 temp = I915_READ(DP_TP_CTL(PORT_E));
991 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
992 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
993 I915_WRITE(DP_TP_CTL(PORT_E), temp);
994 POSTING_READ(DP_TP_CTL(PORT_E));
995
996 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 997
04945641 998 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 999 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1000 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1001 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1002 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1003 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1004 }
1005
a308ccb3
VS		 1006 /* Enable normal pixel sending for FDI */
1007 I915_WRITE(DP_TP_CTL(PORT_E),
1008 DP_TP_CTL_FDI_AUTOTRAIN |
1009 DP_TP_CTL_LINK_TRAIN_NORMAL |
1010 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1011 DP_TP_CTL_ENABLE);
c82e4d26 1012}
0e72a5b5 1013
d7c530b2 1014static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1015{
1016 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1017 struct intel_digital_port *intel_dig_port =
1018 enc_to_dig_port(&encoder->base);
1019
1020 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1021 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1022 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1023}
1024
8d9ddbcb 1025static struct intel_encoder *
e9ce1a62 1026intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1027{
e9ce1a62 1028 struct drm_device *dev = crtc->base.dev;
1524e93e 1029 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1030 int num_encoders = 0;
1031
1524e93e
SS		 1032 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1033 ret = encoder;
8d9ddbcb
PZ		 1034 num_encoders++;
1035 }
1036
1037 if (num_encoders != 1)
84f44ce7 1038 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1039 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1040
1041 BUG_ON(ret == NULL);
1042 return ret;
1043}
1044
44a126ba
PZ		 1045/* Finds the only possible encoder associated with the given CRTC. */
1046struct intel_encoder *
3165c074 1047intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 1048{
3165c074
ACO		 1049 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1050 struct intel_encoder *ret = NULL;
1051 struct drm_atomic_state *state;
da3ced29
ACO		 1052 struct drm_connector *connector;
1053 struct drm_connector_state *connector_state;
d0737e1d 1054 int num_encoders = 0;
3165c074 1055 int i;
d0737e1d 1056
3165c074
ACO		 1057 state = crtc_state->base.state;
1058
b77c7a90 1059 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 1060 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 1061 continue;
1062
da3ced29 1063 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 1064 num_encoders++;
d0737e1d
ACO		 1065 }
1066
1067 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1068 pipe_name(crtc->pipe));
1069
1070 BUG_ON(ret == NULL);
1071 return ret;
1072}
1073
1c0b85c5 1074#define LC_FREQ 2700
1c0b85c5 1075
f0f59a00
VS		 1076static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1077 i915_reg_t reg)
11578553
JB		 1078{
1079 int refclk = LC_FREQ;
1080 int n, p, r;
1081 u32 wrpll;
1082
1083 wrpll = I915_READ(reg);
114fe488
DV		 1084 switch (wrpll & WRPLL_PLL_REF_MASK) {
1085 case WRPLL_PLL_SSC:
1086 case WRPLL_PLL_NON_SSC:
11578553
JB		 1087 /*
1088 * We could calculate spread here, but our checking
1089 * code only cares about 5% accuracy, and spread is a max of
1090 * 0.5% downspread.
1091 */
1092 refclk = 135;
1093 break;
114fe488 1094 case WRPLL_PLL_LCPLL:
11578553
JB		 1095 refclk = LC_FREQ;
1096 break;
1097 default:
1098 WARN(1, "bad wrpll refclk\n");
1099 return 0;
1100 }
1101
1102 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1103 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1104 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1105
20f0ec16
JB		 1106 /* Convert to KHz, p & r have a fixed point portion */
1107 return (refclk * n * 100) / (p * r);
11578553
JB		 1108}
1109
540e732c
S		 1110static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1111 uint32_t dpll)
1112{
f0f59a00 1113 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1114 uint32_t cfgcr1_val, cfgcr2_val;
1115 uint32_t p0, p1, p2, dco_freq;
1116
923c1241
VS		 1117 cfgcr1_reg = DPLL_CFGCR1(dpll);
1118 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1119
1120 cfgcr1_val = I915_READ(cfgcr1_reg);
1121 cfgcr2_val = I915_READ(cfgcr2_reg);
1122
1123 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1124 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1125
1126 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1127 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1128 else
1129 p1 = 1;
1130
1131
1132 switch (p0) {
1133 case DPLL_CFGCR2_PDIV_1:
1134 p0 = 1;
1135 break;
1136 case DPLL_CFGCR2_PDIV_2:
1137 p0 = 2;
1138 break;
1139 case DPLL_CFGCR2_PDIV_3:
1140 p0 = 3;
1141 break;
1142 case DPLL_CFGCR2_PDIV_7:
1143 p0 = 7;
1144 break;
1145 }
1146
1147 switch (p2) {
1148 case DPLL_CFGCR2_KDIV_5:
1149 p2 = 5;
1150 break;
1151 case DPLL_CFGCR2_KDIV_2:
1152 p2 = 2;
1153 break;
1154 case DPLL_CFGCR2_KDIV_3:
1155 p2 = 3;
1156 break;
1157 case DPLL_CFGCR2_KDIV_1:
1158 p2 = 1;
1159 break;
1160 }
1161
1162 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1163
1164 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1165 1000) / 0x8000;
1166
1167 return dco_freq / (p0 * p1 * p2 * 5);
1168}
1169
a9701a89
RV		 1170static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1171 uint32_t pll_id)
1172{
1173 uint32_t cfgcr0, cfgcr1;
1174 uint32_t p0, p1, p2, dco_freq, ref_clock;
1175
1176 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1177 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1178
1179 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1180 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1181
1182 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1183 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1184 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1185 else
1186 p1 = 1;
1187
1188
1189 switch (p0) {
1190 case DPLL_CFGCR1_PDIV_2:
1191 p0 = 2;
1192 break;
1193 case DPLL_CFGCR1_PDIV_3:
1194 p0 = 3;
1195 break;
1196 case DPLL_CFGCR1_PDIV_5:
1197 p0 = 5;
1198 break;
1199 case DPLL_CFGCR1_PDIV_7:
1200 p0 = 7;
1201 break;
1202 }
1203
1204 switch (p2) {
1205 case DPLL_CFGCR1_KDIV_1:
1206 p2 = 1;
1207 break;
1208 case DPLL_CFGCR1_KDIV_2:
1209 p2 = 2;
1210 break;
1211 case DPLL_CFGCR1_KDIV_4:
1212 p2 = 4;
1213 break;
1214 }
1215
1216 ref_clock = dev_priv->cdclk.hw.ref;
1217
1218 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1219
1220 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1221 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1222
0e005888
PZ		 1223 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1224 return 0;
1225
a9701a89
RV		 1226 return dco_freq / (p0 * p1 * p2 * 5);
1227}
1228
398a017e
VS		 1229static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1230{
1231 int dotclock;
1232
1233 if (pipe_config->has_pch_encoder)
1234 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1235 &pipe_config->fdi_m_n);
37a5650b 1236 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1237 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1238 &pipe_config->dp_m_n);
1239 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1240 dotclock = pipe_config->port_clock * 2 / 3;
1241 else
1242 dotclock = pipe_config->port_clock;
1243
b22ca995
SS		 1244 if (pipe_config->ycbcr420)
1245 dotclock *= 2;
1246
398a017e
VS		 1247 if (pipe_config->pixel_multiplier)
1248 dotclock /= pipe_config->pixel_multiplier;
1249
1250 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1251}
540e732c 1252
a9701a89
RV		 1253static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1254 struct intel_crtc_state *pipe_config)
1255{
1256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1257 int link_clock = 0;
1258 uint32_t cfgcr0, pll_id;
1259
1260 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1261
1262 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1263
1264 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1265 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1266 } else {
1267 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1268
1269 switch (link_clock) {
1270 case DPLL_CFGCR0_LINK_RATE_810:
1271 link_clock = 81000;
1272 break;
1273 case DPLL_CFGCR0_LINK_RATE_1080:
1274 link_clock = 108000;
1275 break;
1276 case DPLL_CFGCR0_LINK_RATE_1350:
1277 link_clock = 135000;
1278 break;
1279 case DPLL_CFGCR0_LINK_RATE_1620:
1280 link_clock = 162000;
1281 break;
1282 case DPLL_CFGCR0_LINK_RATE_2160:
1283 link_clock = 216000;
1284 break;
1285 case DPLL_CFGCR0_LINK_RATE_2700:
1286 link_clock = 270000;
1287 break;
1288 case DPLL_CFGCR0_LINK_RATE_3240:
1289 link_clock = 324000;
1290 break;
1291 case DPLL_CFGCR0_LINK_RATE_4050:
1292 link_clock = 405000;
1293 break;
1294 default:
1295 WARN(1, "Unsupported link rate\n");
1296 break;
1297 }
1298 link_clock *= 2;
1299 }
1300
1301 pipe_config->port_clock = link_clock;
1302
1303 ddi_dotclock_get(pipe_config);
1304}
1305
540e732c 1306static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1307 struct intel_crtc_state *pipe_config)
540e732c 1308{
fac5e23e 1309 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1310 int link_clock = 0;
1311 uint32_t dpll_ctl1, dpll;
1312
c856052a 1313 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1314
1315 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1316
1317 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1318 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1319 } else {
71cd8423
DL		 1320 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1321 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1322
1323 switch (link_clock) {
71cd8423 1324 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1325 link_clock = 81000;
1326 break;
71cd8423 1327 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1328 link_clock = 108000;
1329 break;
71cd8423 1330 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1331 link_clock = 135000;
1332 break;
71cd8423 1333 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1334 link_clock = 162000;
1335 break;
71cd8423 1336 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1337 link_clock = 216000;
1338 break;
71cd8423 1339 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1340 link_clock = 270000;
1341 break;
1342 default:
1343 WARN(1, "Unsupported link rate\n");
1344 break;
1345 }
1346 link_clock *= 2;
1347 }
1348
1349 pipe_config->port_clock = link_clock;
1350
398a017e 1351 ddi_dotclock_get(pipe_config);
540e732c
S		 1352}
1353
3d51278a 1354static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1355 struct intel_crtc_state *pipe_config)
11578553 1356{
fac5e23e 1357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1358 int link_clock = 0;
1359 u32 val, pll;
1360
c856052a 1361 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1362 switch (val & PORT_CLK_SEL_MASK) {
1363 case PORT_CLK_SEL_LCPLL_810:
1364 link_clock = 81000;
1365 break;
1366 case PORT_CLK_SEL_LCPLL_1350:
1367 link_clock = 135000;
1368 break;
1369 case PORT_CLK_SEL_LCPLL_2700:
1370 link_clock = 270000;
1371 break;
1372 case PORT_CLK_SEL_WRPLL1:
01403de3 1373 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1374 break;
1375 case PORT_CLK_SEL_WRPLL2:
01403de3 1376 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1377 break;
1378 case PORT_CLK_SEL_SPLL:
1379 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1380 if (pll == SPLL_PLL_FREQ_810MHz)
1381 link_clock = 81000;
1382 else if (pll == SPLL_PLL_FREQ_1350MHz)
1383 link_clock = 135000;
1384 else if (pll == SPLL_PLL_FREQ_2700MHz)
1385 link_clock = 270000;
1386 else {
1387 WARN(1, "bad spll freq\n");
1388 return;
1389 }
1390 break;
1391 default:
1392 WARN(1, "bad port clock sel\n");
1393 return;
1394 }
1395
1396 pipe_config->port_clock = link_clock * 2;
1397
398a017e 1398 ddi_dotclock_get(pipe_config);
11578553
JB		 1399}
1400
977bb38d
S		 1401static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1402 enum intel_dpll_id dpll)
1403{
aa610dcb
ID		 1404 struct intel_shared_dpll *pll;
1405 struct intel_dpll_hw_state *state;
9e2c8475 1406 struct dpll clock;
aa610dcb
ID		 1407
1408 /* For DDI ports we always use a shared PLL. */
1409 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1410 return 0;
1411
1412 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1413 state = &pll->state.hw_state;
aa610dcb
ID		 1414
1415 clock.m1 = 2;
1416 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1417 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1418 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1419 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1420 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1421 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1422
1423 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1424}
1425
1426static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1427 struct intel_crtc_state *pipe_config)
1428{
fac5e23e 1429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1430 enum port port = intel_ddi_get_encoder_port(encoder);
1431 uint32_t dpll = port;
1432
398a017e 1433 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1434
398a017e 1435 ddi_dotclock_get(pipe_config);
977bb38d
S		 1436}
1437
3d51278a 1438void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1439 struct intel_crtc_state *pipe_config)
3d51278a 1440{
0853723b 1441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1442
0853723b 1443 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1444 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1445 else if (IS_GEN9_BC(dev_priv))
22606a18 1446 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1447 else if (IS_GEN9_LP(dev_priv))
977bb38d 1448 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1449 else if (IS_CANNONLAKE(dev_priv))
1450 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1451}
1452
3dc38eea 1453void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1454{
3dc38eea 1455 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1457 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1458 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1459 int type = encoder->type;
dae84799
PZ		 1460 uint32_t temp;
1461
cca0502b 1462 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1463 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1464
c9809791 1465 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1466 switch (crtc_state->pipe_bpp) {
dae84799 1467 case 18:
c9809791 1468 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1469 break;
1470 case 24:
c9809791 1471 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1472 break;
1473 case 30:
c9809791 1474 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1475 break;
1476 case 36:
c9809791 1477 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1478 break;
1479 default:
4e53c2e0 1480 BUG();
dae84799 1481 }
c9809791 1482 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1483 }
1484}
1485
3dc38eea
ACO		 1486void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1487 bool state)
0e32b39c 1488{
3dc38eea 1489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1491 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1492 uint32_t temp;
1493 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1494 if (state == true)
1495 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1496 else
1497 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1498 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1499}
1500
3dc38eea 1501void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1502{
3dc38eea 1503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1504 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1506 enum pipe pipe = crtc->pipe;
3dc38eea 1507 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1508 enum port port = intel_ddi_get_encoder_port(encoder);
1509 int type = encoder->type;
8d9ddbcb
PZ		 1510 uint32_t temp;
1511
ad80a810
PZ		 1512 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1513 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1514 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1515
3dc38eea 1516 switch (crtc_state->pipe_bpp) {
dfcef252 1517 case 18:
ad80a810 1518 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1519 break;
1520 case 24:
ad80a810 1521 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1522 break;
1523 case 30:
ad80a810 1524 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1525 break;
1526 case 36:
ad80a810 1527 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1528 break;
1529 default:
4e53c2e0 1530 BUG();
dfcef252 1531 }
72662e10 1532
3dc38eea 1533 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1534 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1535 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1536 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1537
e6f0bfc4
PZ		 1538 if (cpu_transcoder == TRANSCODER_EDP) {
1539 switch (pipe) {
1540 case PIPE_A:
c7670b10
PZ		 1541 /* On Haswell, can only use the always-on power well for
1542 * eDP when not using the panel fitter, and when not
1543 * using motion blur mitigation (which we don't
1544 * support). */
772c2a51 1545 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1546 (crtc_state->pch_pfit.enabled ||
1547 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1548 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1549 else
1550 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1551 break;
1552 case PIPE_B:
1553 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1554 break;
1555 case PIPE_C:
1556 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1557 break;
1558 default:
1559 BUG();
1560 break;
1561 }
1562 }
1563
7739c33b 1564 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1565 if (crtc_state->has_hdmi_sink)
ad80a810 1566 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1567 else
ad80a810 1568 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1569
1570 if (crtc_state->hdmi_scrambling)
1571 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1572 if (crtc_state->hdmi_high_tmds_clock_ratio)
1573 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1574 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1575 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1576 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1577 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1578 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1579 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1580 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1581 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1582 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1584 } else {
84f44ce7 1585 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1586 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1587 }
1588
ad80a810 1589 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1590}
72662e10 1591
ad80a810
PZ		 1592void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1593 enum transcoder cpu_transcoder)
8d9ddbcb 1594{
f0f59a00 1595 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1596 uint32_t val = I915_READ(reg);
1597
0e32b39c 1598 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1599 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1600 I915_WRITE(reg, val);
72662e10
ED		 1601}
1602
bcbc889b
PZ		 1603bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1604{
1605 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1606 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1607 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1608 int type = intel_connector->base.connector_type;
1524e93e 1609 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1610 enum pipe pipe = 0;
1611 enum transcoder cpu_transcoder;
1612 uint32_t tmp;
e27daab4 1613 bool ret;
bcbc889b 1614
79f255a0 1615 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1616 encoder->power_domain))
882244a3
PZ		 1617 return false;
1618
1524e93e 1619 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1620 ret = false;
1621 goto out;
1622 }
bcbc889b
PZ		 1623
1624 if (port == PORT_A)
1625 cpu_transcoder = TRANSCODER_EDP;
1626 else
1a240d4d 1627 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1628
1629 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1630
1631 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1632 case TRANS_DDI_MODE_SELECT_HDMI:
1633 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1634 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1635 break;
bcbc889b
PZ		 1636
1637 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1638 ret = type == DRM_MODE_CONNECTOR_eDP ||
1639 type == DRM_MODE_CONNECTOR_DisplayPort;
1640 break;
1641
0e32b39c
DA		 1642 case TRANS_DDI_MODE_SELECT_DP_MST:
1643 /* if the transcoder is in MST state then
1644 * connector isn't connected */
e27daab4
ID		 1645 ret = false;
1646 break;
bcbc889b
PZ		 1647
1648 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1649 ret = type == DRM_MODE_CONNECTOR_VGA;
1650 break;
bcbc889b
PZ		 1651
1652 default:
e27daab4
ID		 1653 ret = false;
1654 break;
bcbc889b 1655 }
e27daab4
ID		 1656
1657out:
1524e93e 1658 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1659
1660 return ret;
bcbc889b
PZ		 1661}
1662
85234cdc
DV		 1663bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1664 enum pipe *pipe)
1665{
1666 struct drm_device *dev = encoder->base.dev;
fac5e23e 1667 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1668 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1669 u32 tmp;
1670 int i;
e27daab4 1671 bool ret;
85234cdc 1672
79f255a0
ACO		 1673 if (!intel_display_power_get_if_enabled(dev_priv,
1674 encoder->power_domain))
6d129bea
ID		 1675 return false;
1676
e27daab4
ID		 1677 ret = false;
1678
fe43d3f5 1679 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1680
1681 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1682 goto out;
85234cdc 1683
ad80a810
PZ		 1684 if (port == PORT_A) {
1685 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1686
ad80a810
PZ		 1687 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1688 case TRANS_DDI_EDP_INPUT_A_ON:
1689 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1690 *pipe = PIPE_A;
1691 break;
1692 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1693 *pipe = PIPE_B;
1694 break;
1695 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1696 *pipe = PIPE_C;
1697 break;
1698 }
1699
e27daab4 1700 ret = true;
ad80a810 1701
e27daab4
ID		 1702 goto out;
1703 }
0e32b39c 1704
e27daab4
ID		 1705 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1706 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1707
1708 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1709 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1710 TRANS_DDI_MODE_SELECT_DP_MST)
1711 goto out;
1712
1713 *pipe = i;
1714 ret = true;
1715
1716 goto out;
85234cdc
DV		 1717 }
1718 }
1719
84f44ce7 1720 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1721
e27daab4 1722out:
cc3f90f0 1723 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0 1724 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 1725 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1726 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 1727 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1728 DRM_ERROR("Port %c enabled but PHY powered down? "
1729 "(PHY_CTL %08x)\n", port_name(port), tmp);
1730 }
1731
79f255a0 1732 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1733
1734 return ret;
85234cdc
DV		 1735}
1736
62b69566
ACO		 1737static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1738{
1739 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1740 enum pipe pipe;
1741
1742 if (intel_ddi_get_hw_state(encoder, &pipe))
1743 return BIT_ULL(dig_port->ddi_io_power_domain);
1744
1745 return 0;
1746}
1747
3dc38eea 1748void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1749{
3dc38eea 1750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1752 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1753 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1754 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1755
bb523fc0
PZ		 1756 if (cpu_transcoder != TRANSCODER_EDP)
1757 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1758 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1759}
1760
3dc38eea 1761void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1762{
3dc38eea
ACO		 1763 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1764 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1765
bb523fc0
PZ		 1766 if (cpu_transcoder != TRANSCODER_EDP)
1767 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1768 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1769}
1770
a7d8dbc0
VS		 1771static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1772 enum port port, uint8_t iboost)
f8896f5d 1773{
a7d8dbc0
VS		 1774 u32 tmp;
1775
1776 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1777 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1778 if (iboost)
1779 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1780 else
1781 tmp |= BALANCE_LEG_DISABLE(port);
1782 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1783}
1784
1785static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1786{
1787 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1788 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1789 enum port port = intel_dig_port->port;
1790 int type = encoder->type;
f8896f5d
DW		 1791 const struct ddi_buf_trans *ddi_translations;
1792 uint8_t iboost;
75067dde 1793 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1794 int n_entries;
f8896f5d 1795
75067dde
AK		 1796 /* VBT may override standard boost values */
1797 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1798 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1799
cca0502b 1800 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1801 if (dp_iboost) {
1802 iboost = dp_iboost;
1803 } else {
da411a48 1804 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 1805 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1806 &n_entries);
1807 else
1808 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1809 &n_entries);
e4d4c05b 1810 iboost = ddi_translations[level].i_boost;
75067dde 1811 }
f8896f5d 1812 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1813 if (dp_iboost) {
1814 iboost = dp_iboost;
1815 } else {
78ab0bae 1816 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1817
1818 if (WARN_ON(port != PORT_A &&
1819 port != PORT_E && n_entries > 9))
1820 n_entries = 9;
1821
e4d4c05b 1822 iboost = ddi_translations[level].i_boost;
75067dde 1823 }
f8896f5d 1824 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1825 if (hdmi_iboost) {
1826 iboost = hdmi_iboost;
1827 } else {
78ab0bae 1828 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1829 iboost = ddi_translations[level].i_boost;
75067dde 1830 }
f8896f5d
DW		 1831 } else {
1832 return;
1833 }
1834
1835 /* Make sure that the requested I_boost is valid */
1836 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1837 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1838 return;
1839 }
1840
a7d8dbc0 1841 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1842
a7d8dbc0
VS		 1843 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1844 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1845}
1846
78ab0bae
VS		 1847static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1848 u32 level, enum port port, int type)
96fb9f9b 1849{
96fb9f9b
VK		 1850 const struct bxt_ddi_buf_trans *ddi_translations;
1851 u32 n_entries, i;
96fb9f9b 1852
06411f08 1853 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1854 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1855 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1856 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1857 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1858 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1859 ddi_translations = bxt_ddi_translations_dp;
1860 } else if (type == INTEL_OUTPUT_HDMI) {
1861 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1862 ddi_translations = bxt_ddi_translations_hdmi;
1863 } else {
1864 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1865 type);
1866 return;
1867 }
1868
1869 /* Check if default value has to be used */
1870 if (level >= n_entries ||
1871 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1872 for (i = 0; i < n_entries; i++) {
1873 if (ddi_translations[i].default_index) {
1874 level = i;
1875 break;
1876 }
1877 }
1878 }
1879
b6e08203
ACO		 1880 bxt_ddi_phy_set_signal_level(dev_priv, port,
1881 ddi_translations[level].margin,
1882 ddi_translations[level].scale,
1883 ddi_translations[level].enable,
1884 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1885}
1886
ffe5111e
VS		 1887u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1888{
1889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1890 int n_entries;
1891
5fcf34b1
RV		 1892 if (IS_CANNONLAKE(dev_priv)) {
1893 if (encoder->type == INTEL_OUTPUT_EDP)
1894 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1895 else
1896 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1897 } else {
1898 if (encoder->type == INTEL_OUTPUT_EDP)
1899 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1900 else
1901 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1902 }
ffe5111e
VS		 1903
1904 if (WARN_ON(n_entries < 1))
1905 n_entries = 1;
1906 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1907 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1908
1909 return index_to_dp_signal_levels[n_entries - 1] &
1910 DP_TRAIN_VOLTAGE_SWING_MASK;
1911}
1912
cf54ca8b
RV		 1913static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1914 u32 level, enum port port, int type)
1915{
1916 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
cc9cabfd 1917 u32 n_entries, val;
cf54ca8b
RV		 1918 int ln;
1919
cf54ca8b 1920 if (type == INTEL_OUTPUT_HDMI) {
cc9cabfd 1921 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
cf54ca8b 1922 } else if (type == INTEL_OUTPUT_DP) {
cc9cabfd 1923 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 1924 } else if (type == INTEL_OUTPUT_EDP) {
cc9cabfd 1925 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
cf54ca8b
RV		 1926 }
1927
cc9cabfd 1928 if (WARN_ON(ddi_translations == NULL))
cf54ca8b 1929 return;
cf54ca8b
RV		 1930
1931 if (level >= n_entries) {
1932 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1933 level = n_entries - 1;
1934 }
1935
1936 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1937 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1938 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1939 val |= SCALING_MODE_SEL(2);
1940 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1941
1942 /* Program PORT_TX_DW2 */
1943 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1944 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1945 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1946 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1947 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1948 /* Rcomp scalar is fixed as 0x98 for every table entry */
1949 val |= RCOMP_SCALAR(0x98);
1950 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1951
20303eb4 1952 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 1953 /* We cannot write to GRP. It would overrite individual loadgen */
1954 for (ln = 0; ln < 4; ln++) {
1955 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1956 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1957 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1958 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1959 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1960 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1961 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1962 }
1963
20303eb4 1964 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 1965 /* All DW5 values are fixed for every table entry */
1966 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1967 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1968 val |= RTERM_SELECT(6);
1969 val |= TAP3_DISABLE;
1970 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1971
20303eb4 1972 /* Program PORT_TX_DW7 */
cf54ca8b 1973 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1974 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1975 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1976 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1977}
1978
0091abc3 1979static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1980{
0091abc3
CT		 1981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1982 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1983 enum port port = intel_ddi_get_encoder_port(encoder);
1984 int type = encoder->type;
1985 int width = 0;
1986 int rate = 0;
cf54ca8b 1987 u32 val;
0091abc3
CT		 1988 int ln = 0;
1989
1990 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1991 width = intel_dp->lane_count;
1992 rate = intel_dp->link_rate;
61f3e770 1993 } else if (type == INTEL_OUTPUT_HDMI) {
0091abc3
CT		 1994 width = 4;
1995 /* Rate is always < than 6GHz for HDMI */
61f3e770
RV		 1996 } else {
1997 MISSING_CASE(type);
1998 return;
0091abc3 1999 }
cf54ca8b
RV		 2000
2001 /*
2002 * 1. If port type is eDP or DP,
2003 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2004 * else clear to 0b.
2005 */
2006 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2007 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
2008 val |= COMMON_KEEPER_EN;
2009 else
2010 val &= ~COMMON_KEEPER_EN;
2011 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2012
2013 /* 2. Program loadgen select */
2014 /*
0091abc3
CT		 2015 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2016 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2017 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2018 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2019 */
0091abc3
CT		 2020 for (ln = 0; ln <= 3; ln++) {
2021 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2022 val &= ~LOADGEN_SELECT;
2023
a8e45a1c
NM		 2024 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2025 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2026 val |= LOADGEN_SELECT;
2027 }
2028 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2029 }
cf54ca8b
RV		 2030
2031 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2032 val = I915_READ(CNL_PORT_CL1CM_DW5);
2033 val |= SUS_CLOCK_CONFIG;
2034 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2035
2036 /* 4. Clear training enable to change swing values */
2037 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2038 val &= ~TX_TRAINING_EN;
2039 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2040
2041 /* 5. Program swing and de-emphasis */
2042 cnl_ddi_vswing_program(dev_priv, level, port, type);
2043
2044 /* 6. Set training enable to trigger update */
2045 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2046 val |= TX_TRAINING_EN;
2047 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2048}
2049
f8896f5d
DW		 2050static uint32_t translate_signal_level(int signal_levels)
2051{
97eeb872 2052 int i;
f8896f5d 2053
97eeb872
VS		 2054 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2055 if (index_to_dp_signal_levels[i] == signal_levels)
2056 return i;
f8896f5d
DW		 2057 }
2058
97eeb872
VS		 2059 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2060 signal_levels);
2061
2062 return 0;
f8896f5d
DW		 2063}
2064
1b6e2fd2
RV		 2065static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2066{
2067 uint8_t train_set = intel_dp->train_set[0];
2068 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2069 DP_TRAIN_PRE_EMPHASIS_MASK);
2070
2071 return translate_signal_level(signal_levels);
2072}
2073
d509af6c 2074u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2075{
2076 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2077 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2078 struct intel_encoder *encoder = &dport->base;
f8896f5d 2079 enum port port = dport->port;
d509af6c
RV		 2080 u32 level = intel_ddi_dp_level(intel_dp);
2081
2082 if (IS_CANNONLAKE(dev_priv))
2083 cnl_ddi_vswing_sequence(encoder, level);
2084 else
2085 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2086
2087 return 0;
2088}
2089
2090uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2091{
2092 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2093 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2094 struct intel_encoder *encoder = &dport->base;
1b6e2fd2 2095 uint32_t level = intel_ddi_dp_level(intel_dp);
f8896f5d 2096
b976dc53 2097 if (IS_GEN9_BC(dev_priv))
d509af6c
RV		 2098 skl_ddi_set_iboost(encoder, level);
2099
f8896f5d
DW		 2100 return DDI_BUF_TRANS_SELECT(level);
2101}
2102
d7c530b2 2103static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2104 const struct intel_shared_dpll *pll)
6441ab5f 2105{
e404ba8d
VS		 2106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2107 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 2108 uint32_t val;
6441ab5f 2109
c856052a
ACO		 2110 if (WARN_ON(!pll))
2111 return;
2112
555e38d2
RV		 2113 if (IS_CANNONLAKE(dev_priv)) {
2114 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2115 val = I915_READ(DPCLKA_CFGCR0);
2116 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2117 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2118
555e38d2
RV		 2119 /*
2120 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2121 * This step and the step before must be done with separate
2122 * register writes.
2123 */
2124 val = I915_READ(DPCLKA_CFGCR0);
2125 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2126 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2127 I915_WRITE(DPCLKA_CFGCR0, val);
2128 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2129 /* DDI -> PLL mapping */
efa80add
S		 2130 val = I915_READ(DPLL_CTRL2);
2131
2132 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2133 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2134 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2135 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2136
2137 I915_WRITE(DPLL_CTRL2, val);
5416d871 2138
e404ba8d 2139 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 2140 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2141 }
e404ba8d
VS		 2142}
2143
6b8506d5
VS		 2144static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2145{
2146 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2147 enum port port = intel_ddi_get_encoder_port(encoder);
2148
2149 if (IS_CANNONLAKE(dev_priv))
2150 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2151 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2152 else if (IS_GEN9_BC(dev_priv))
2153 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2154 DPLL_CTRL2_DDI_CLK_OFF(port));
2155 else if (INTEL_GEN(dev_priv) < 9)
2156 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2157}
2158
ba88d153
MN		 2159static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2160 int link_rate, uint32_t lane_count,
2161 struct intel_shared_dpll *pll,
2162 bool link_mst)
e404ba8d 2163{
ba88d153
MN		 2164 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2166 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2167 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
381f9570 2168 uint32_t level = intel_ddi_dp_level(intel_dp);
b2ccb822 2169
e081c846
ACO		 2170 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2171
ba88d153
MN		 2172 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2173 link_mst);
2174 if (encoder->type == INTEL_OUTPUT_EDP)
e404ba8d 2175 intel_edp_panel_on(intel_dp);
32bdc400 2176
ba88d153 2177 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2178
2179 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2180
381f9570
RV		 2181 if (IS_CANNONLAKE(dev_priv))
2182 cnl_ddi_vswing_sequence(encoder, level);
2183 else if (IS_GEN9_LP(dev_priv))
2184 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2185 else
2f7460a7
RV		 2186 intel_prepare_dp_ddi_buffers(encoder);
2187
ba88d153 2188 intel_ddi_init_dp_buf_reg(encoder);
5ea2355a
DP		 2189 if (!link_mst)
2190 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
ba88d153
MN		 2191 intel_dp_start_link_train(intel_dp);
2192 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2193 intel_dp_stop_link_train(intel_dp);
2194}
901c2daf 2195
ba88d153 2196static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
b47ef0f7 2197 bool has_infoframe,
ac240288
ML		 2198 const struct intel_crtc_state *crtc_state,
2199 const struct drm_connector_state *conn_state,
5f88a9c6 2200 const struct intel_shared_dpll *pll)
ba88d153 2201{
f99be1b3
VS		 2202 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2203 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ba88d153
MN		 2205 enum port port = intel_ddi_get_encoder_port(encoder);
2206 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2207 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2208
ba88d153
MN		 2209 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2210 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2211
2212 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2213
2f7460a7
RV		 2214 if (IS_CANNONLAKE(dev_priv))
2215 cnl_ddi_vswing_sequence(encoder, level);
cc3f90f0 2216 else if (IS_GEN9_LP(dev_priv))
ba88d153
MN		 2217 bxt_ddi_vswing_sequence(dev_priv, level, port,
2218 INTEL_OUTPUT_HDMI);
2f7460a7
RV		 2219 else
2220 intel_prepare_hdmi_ddi_buffers(encoder);
2221
2222 if (IS_GEN9_BC(dev_priv))
2223 skl_ddi_set_iboost(encoder, level);
8d8bb85e 2224
f99be1b3
VS		 2225 intel_dig_port->set_infoframes(&encoder->base,
2226 has_infoframe,
2227 crtc_state, conn_state);
ba88d153 2228}
32bdc400 2229
1524e93e 2230static void intel_ddi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2231 const struct intel_crtc_state *pipe_config,
2232 const struct drm_connector_state *conn_state)
ba88d153 2233{
364a3fe1
JN		 2234 struct drm_crtc *crtc = pipe_config->base.crtc;
2235 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237 int pipe = intel_crtc->pipe;
1524e93e 2238 int type = encoder->type;
30cf6db8 2239
364a3fe1
JN		 2240 WARN_ON(intel_crtc->config->has_pch_encoder);
2241
2242 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2243
ba88d153 2244 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1524e93e 2245 intel_ddi_pre_enable_dp(encoder,
3dc38eea
ACO		 2246 pipe_config->port_clock,
2247 pipe_config->lane_count,
2248 pipe_config->shared_dpll,
2249 intel_crtc_has_type(pipe_config,
ba88d153
MN		 2250 INTEL_OUTPUT_DP_MST));
2251 }
2252 if (type == INTEL_OUTPUT_HDMI) {
1524e93e 2253 intel_ddi_pre_enable_hdmi(encoder,
b47ef0f7 2254 pipe_config->has_infoframe,
ac240288 2255 pipe_config, conn_state,
3dc38eea 2256 pipe_config->shared_dpll);
c19b0669 2257 }
6441ab5f
PZ		 2258}
2259
fd6bbda9 2260static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2261 const struct intel_crtc_state *old_crtc_state,
2262 const struct drm_connector_state *old_conn_state)
6441ab5f
PZ		 2263{
2264 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2265 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6441ab5f 2266 enum port port = intel_ddi_get_encoder_port(intel_encoder);
62b69566 2267 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
82a4d9c0 2268 int type = intel_encoder->type;
2886e93f 2269 uint32_t val;
a836bdf9 2270 bool wait = false;
2886e93f 2271
7618138d 2272 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
5ea2355a
DP		 2273 /*
2274 * old_crtc_state and old_conn_state are NULL when called from
2275 * DP_MST. The main connector associated with this port is never
2276 * bound to a crtc for MST.
2277 */
2278 bool is_mst = !old_crtc_state;
c5f93fcf
VS		 2279 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2280
5ea2355a
DP		 2281 /*
2282 * Power down sink before disabling the port, otherwise we end
2283 * up getting interrupts from the sink on detecting link loss.
2284 */
2285 if (!is_mst)
2286 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
7618138d
ID		 2287 }
2288
2886e93f
PZ		 2289 val = I915_READ(DDI_BUF_CTL(port));
2290 if (val & DDI_BUF_CTL_ENABLE) {
2291 val &= ~DDI_BUF_CTL_ENABLE;
2292 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2293 wait = true;
2886e93f 2294 }
6441ab5f 2295
a836bdf9
PZ		 2296 val = I915_READ(DP_TP_CTL(port));
2297 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2298 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2299 I915_WRITE(DP_TP_CTL(port), val);
2300
2301 if (wait)
2302 intel_wait_ddi_buf_idle(dev_priv, port);
2303
c5f93fcf 2304 if (type == INTEL_OUTPUT_HDMI) {
f99be1b3
VS		 2305 dig_port->set_infoframes(encoder, false,
2306 old_crtc_state, old_conn_state);
c5f93fcf
VS		 2307 }
2308
2309 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2310 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2311
24f3e092 2312 intel_edp_panel_vdd_on(intel_dp);
4be73780 2313 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2314 }
2315
62b69566
ACO		 2316 if (dig_port)
2317 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2318
6b8506d5 2319 intel_ddi_clk_disable(intel_encoder);
b2ccb822
VS		 2320
2321 if (type == INTEL_OUTPUT_HDMI) {
2322 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2323
2324 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2325 }
6441ab5f
PZ		 2326}
2327
1524e93e 2328void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2329 const struct intel_crtc_state *old_crtc_state,
2330 const struct drm_connector_state *old_conn_state)
b7076546 2331{
1524e93e 2332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2333 uint32_t val;
2334
2335 /*
2336 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2337 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2338 * step 13 is the correct place for it. Step 18 is where it was
2339 * originally before the BUN.
2340 */
2341 val = I915_READ(FDI_RX_CTL(PIPE_A));
2342 val &= ~FDI_RX_ENABLE;
2343 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2344
1524e93e 2345 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
b7076546
ML		 2346
2347 val = I915_READ(FDI_RX_MISC(PIPE_A));
2348 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2349 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2350 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2351
2352 val = I915_READ(FDI_RX_CTL(PIPE_A));
2353 val &= ~FDI_PCDCLK;
2354 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2355
2356 val = I915_READ(FDI_RX_CTL(PIPE_A));
2357 val &= ~FDI_RX_PLL_ENABLE;
2358 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2359}
2360
fd6bbda9 2361static void intel_enable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2362 const struct intel_crtc_state *pipe_config,
2363 const struct drm_connector_state *conn_state)
72662e10 2364{
6547fef8 2365 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2366 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6547fef8
PZ		 2367 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2368 int type = intel_encoder->type;
72662e10 2369
6547fef8 2370 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2371 struct intel_digital_port *intel_dig_port =
2372 enc_to_dig_port(encoder);
15953637
SS		 2373 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2374 bool scrambling = pipe_config->hdmi_scrambling;
2375
2376 intel_hdmi_handle_sink_scrambling(intel_encoder,
2377 conn_state->connector,
2378 clock_ratio, scrambling);
876a8cdf 2379
6547fef8
PZ		 2380 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2381 * are ignored so nothing special needs to be done besides
2382 * enabling the port.
2383 */
876a8cdf 2384 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2385 intel_dig_port->saved_port_bits |
2386 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2387 } else if (type == INTEL_OUTPUT_EDP) {
2388 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2389
66478475 2390 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3ab9c637
ID		 2391 intel_dp_stop_link_train(intel_dp);
2392
b037d58f 2393 intel_edp_backlight_on(pipe_config, conn_state);
d2419ffc 2394 intel_psr_enable(intel_dp, pipe_config);
85cb48a1 2395 intel_edp_drrs_enable(intel_dp, pipe_config);
6547fef8 2396 }
7b9f35a6 2397
37255d8d 2398 if (pipe_config->has_audio)
bbf35e9d 2399 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
5ab432ef
DV		 2400}
2401
fd6bbda9 2402static void intel_disable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2403 const struct intel_crtc_state *old_crtc_state,
2404 const struct drm_connector_state *old_conn_state)
5ab432ef 2405{
d6c50ff8
PZ		 2406 struct drm_encoder *encoder = &intel_encoder->base;
2407 int type = intel_encoder->type;
2408
37255d8d 2409 if (old_crtc_state->has_audio)
69bfe1a9 2410 intel_audio_codec_disable(intel_encoder);
2831d842 2411
15953637
SS		 2412 if (type == INTEL_OUTPUT_HDMI) {
2413 intel_hdmi_handle_sink_scrambling(intel_encoder,
2414 old_conn_state->connector,
2415 false, false);
2416 }
2417
d6c50ff8
PZ		 2418 if (type == INTEL_OUTPUT_EDP) {
2419 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2420
85cb48a1 2421 intel_edp_drrs_disable(intel_dp, old_crtc_state);
d2419ffc 2422 intel_psr_disable(intel_dp, old_crtc_state);
b037d58f 2423 intel_edp_backlight_off(old_conn_state);
d6c50ff8 2424 }
72662e10 2425}
79f689aa 2426
fd6bbda9 2427static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2428 const struct intel_crtc_state *pipe_config,
2429 const struct drm_connector_state *conn_state)
95a7a2ae 2430{
3dc38eea 2431 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2432
47a6bc61 2433 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2434}
2435
ad64217b 2436void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2437{
ad64217b
ACO		 2438 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2439 struct drm_i915_private *dev_priv =
2440 to_i915(intel_dig_port->base.base.dev);
174edf1f 2441 enum port port = intel_dig_port->port;
c19b0669 2442 uint32_t val;
f3e227df 2443 bool wait = false;
c19b0669
PZ		 2444
2445 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2446 val = I915_READ(DDI_BUF_CTL(port));
2447 if (val & DDI_BUF_CTL_ENABLE) {
2448 val &= ~DDI_BUF_CTL_ENABLE;
2449 I915_WRITE(DDI_BUF_CTL(port), val);
2450 wait = true;
2451 }
2452
2453 val = I915_READ(DP_TP_CTL(port));
2454 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2455 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2456 I915_WRITE(DP_TP_CTL(port), val);
2457 POSTING_READ(DP_TP_CTL(port));
2458
2459 if (wait)
2460 intel_wait_ddi_buf_idle(dev_priv, port);
2461 }
2462
0e32b39c 2463 val = DP_TP_CTL_ENABLE |
c19b0669 2464 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2465 if (intel_dp->link_mst)
0e32b39c
DA		 2466 val |= DP_TP_CTL_MODE_MST;
2467 else {
2468 val |= DP_TP_CTL_MODE_SST;
2469 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2470 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2471 }
c19b0669
PZ		 2472 I915_WRITE(DP_TP_CTL(port), val);
2473 POSTING_READ(DP_TP_CTL(port));
2474
2475 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2476 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2477 POSTING_READ(DDI_BUF_CTL(port));
2478
2479 udelay(600);
2480}
00c09d70 2481
9935f7fa
LY		 2482bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2483 struct intel_crtc *intel_crtc)
2484{
2485 u32 temp;
2486
2487 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2488 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2489 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2490 return true;
2491 }
2492 return false;
2493}
2494
6801c18c 2495void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2496 struct intel_crtc_state *pipe_config)
045ac3b5 2497{
fac5e23e 2498 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2499 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2500 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 2501 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 2502 u32 temp, flags = 0;
2503
4d1de975
JN		 2504 /* XXX: DSI transcoder paranoia */
2505 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2506 return;
2507
045ac3b5
JB		 2508 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2509 if (temp & TRANS_DDI_PHSYNC)
2510 flags |= DRM_MODE_FLAG_PHSYNC;
2511 else
2512 flags |= DRM_MODE_FLAG_NHSYNC;
2513 if (temp & TRANS_DDI_PVSYNC)
2514 flags |= DRM_MODE_FLAG_PVSYNC;
2515 else
2516 flags |= DRM_MODE_FLAG_NVSYNC;
2517
2d112de7 2518 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2519
2520 switch (temp & TRANS_DDI_BPC_MASK) {
2521 case TRANS_DDI_BPC_6:
2522 pipe_config->pipe_bpp = 18;
2523 break;
2524 case TRANS_DDI_BPC_8:
2525 pipe_config->pipe_bpp = 24;
2526 break;
2527 case TRANS_DDI_BPC_10:
2528 pipe_config->pipe_bpp = 30;
2529 break;
2530 case TRANS_DDI_BPC_12:
2531 pipe_config->pipe_bpp = 36;
2532 break;
2533 default:
2534 break;
2535 }
eb14cb74
VS		 2536
2537 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2538 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2539 pipe_config->has_hdmi_sink = true;
f99be1b3 2540 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 2541
f99be1b3 2542 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2543 pipe_config->has_infoframe = true;
15953637
SS		 2544
2545 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2546 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2547 pipe_config->hdmi_scrambling = true;
2548 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2549 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2550 /* fall through */
eb14cb74 2551 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2552 pipe_config->lane_count = 4;
2553 break;
eb14cb74
VS		 2554 case TRANS_DDI_MODE_SELECT_FDI:
2555 break;
2556 case TRANS_DDI_MODE_SELECT_DP_SST:
2557 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2558 pipe_config->lane_count =
2559 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2560 intel_dp_get_m_n(intel_crtc, pipe_config);
2561 break;
2562 default:
2563 break;
2564 }
10214420 2565
9935f7fa
LY		 2566 pipe_config->has_audio =
2567 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2568
6aa23e65
JN		 2569 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2570 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2571 /*
2572 * This is a big fat ugly hack.
2573 *
2574 * Some machines in UEFI boot mode provide us a VBT that has 18
2575 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2576 * unknown we fail to light up. Yet the same BIOS boots up with
2577 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2578 * max, not what it tells us to use.
2579 *
2580 * Note: This will still be broken if the eDP panel is not lit
2581 * up by the BIOS, and thus we can't get the mode at module
2582 * load.
2583 */
2584 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2585 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2586 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2587 }
11578553 2588
22606a18 2589 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2590
cc3f90f0 2591 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2592 pipe_config->lane_lat_optim_mask =
2593 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2594}
2595
5bfe2ac0 2596static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2597 struct intel_crtc_state *pipe_config,
2598 struct drm_connector_state *conn_state)
00c09d70 2599{
fac5e23e 2600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2601 int type = encoder->type;
eccb140b 2602 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2603 int ret;
00c09d70 2604
5bfe2ac0 2605 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2606
eccb140b
DV		 2607 if (port == PORT_A)
2608 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2609
00c09d70 2610 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2611 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2612 else
0a478c27 2613 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2614
cc3f90f0 2615 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2616 pipe_config->lane_lat_optim_mask =
2617 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2618 pipe_config->lane_count);
95a7a2ae
ID		 2619
2620 return ret;
2621
00c09d70
PZ		 2622}
2623
2624static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2625 .reset = intel_dp_encoder_reset,
2626 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2627};
2628
4a28ae58
PZ		 2629static struct intel_connector *
2630intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2631{
2632 struct intel_connector *connector;
2633 enum port port = intel_dig_port->port;
2634
9bdbd0b9 2635 connector = intel_connector_alloc();
4a28ae58
PZ		 2636 if (!connector)
2637 return NULL;
2638
2639 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2640 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2641 kfree(connector);
2642 return NULL;
2643 }
2644
2645 return connector;
2646}
2647
2648static struct intel_connector *
2649intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2650{
2651 struct intel_connector *connector;
2652 enum port port = intel_dig_port->port;
2653
9bdbd0b9 2654 connector = intel_connector_alloc();
4a28ae58
PZ		 2655 if (!connector)
2656 return NULL;
2657
2658 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2659 intel_hdmi_init_connector(intel_dig_port, connector);
2660
2661 return connector;
2662}
2663
c39055b0 2664void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2665{
2666 struct intel_digital_port *intel_dig_port;
2667 struct intel_encoder *intel_encoder;
2668 struct drm_encoder *encoder;
ff662124 2669 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2670 int max_lanes;
2671
2672 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2673 switch (port) {
2674 case PORT_A:
2675 max_lanes = 4;
2676 break;
2677 case PORT_E:
2678 max_lanes = 0;
2679 break;
2680 default:
2681 max_lanes = 4;
2682 break;
2683 }
2684 } else {
2685 switch (port) {
2686 case PORT_A:
2687 max_lanes = 2;
2688 break;
2689 case PORT_E:
2690 max_lanes = 2;
2691 break;
2692 default:
2693 max_lanes = 4;
2694 break;
2695 }
2696 }
311a2094
PZ		 2697
2698 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2699 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2700 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2701
2702 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2703 /*
2704 * Lspcon device needs to be driven with DP connector
2705 * with special detection sequence. So make sure DP
2706 * is initialized before lspcon.
2707 */
2708 init_dp = true;
2709 init_lspcon = true;
2710 init_hdmi = false;
2711 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2712 }
2713
311a2094 2714 if (!init_dp && !init_hdmi) {
500ea70d 2715 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2716 port_name(port));
500ea70d 2717 return;
311a2094 2718 }
00c09d70 2719
b14c5679 2720 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2721 if (!intel_dig_port)
2722 return;
2723
00c09d70
PZ		 2724 intel_encoder = &intel_dig_port->base;
2725 encoder = &intel_encoder->base;
2726
c39055b0 2727 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2728 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2729
5bfe2ac0 2730 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2731 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2732 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2733 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2734 intel_encoder->pre_enable = intel_ddi_pre_enable;
2735 intel_encoder->disable = intel_disable_ddi;
2736 intel_encoder->post_disable = intel_ddi_post_disable;
2737 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2738 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2739 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2740 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2741
2742 intel_dig_port->port = port;
bcf53de4
SM		 2743 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2744 (DDI_BUF_PORT_REVERSAL |
2745 DDI_A_4_LANES);
00c09d70 2746
62b69566
ACO		 2747 switch (port) {
2748 case PORT_A:
2749 intel_dig_port->ddi_io_power_domain =
2750 POWER_DOMAIN_PORT_DDI_A_IO;
2751 break;
2752 case PORT_B:
2753 intel_dig_port->ddi_io_power_domain =
2754 POWER_DOMAIN_PORT_DDI_B_IO;
2755 break;
2756 case PORT_C:
2757 intel_dig_port->ddi_io_power_domain =
2758 POWER_DOMAIN_PORT_DDI_C_IO;
2759 break;
2760 case PORT_D:
2761 intel_dig_port->ddi_io_power_domain =
2762 POWER_DOMAIN_PORT_DDI_D_IO;
2763 break;
2764 case PORT_E:
2765 intel_dig_port->ddi_io_power_domain =
2766 POWER_DOMAIN_PORT_DDI_E_IO;
2767 break;
2768 default:
2769 MISSING_CASE(port);
2770 }
2771
6c566dc9
MR		 2772 /*
2773 * Bspec says that DDI_A_4_LANES is the only supported configuration
2774 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2775 * wasn't lit up at boot. Force this bit on in our internal
2776 * configuration so that we use the proper lane count for our
2777 * calculations.
2778 */
cc3f90f0 2779 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2780 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2781 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2782 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2783 max_lanes = 4;
6c566dc9
MR		 2784 }
2785 }
2786
ed8d60f4
MR		 2787 intel_dig_port->max_lanes = max_lanes;
2788
00c09d70 2789 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2790 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2791 intel_encoder->port = port;
f68d697e 2792 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2793 intel_encoder->cloneable = 0;
00c09d70 2794
385e4de0
VS		 2795 intel_infoframe_init(intel_dig_port);
2796
f68d697e
CW		 2797 if (init_dp) {
2798 if (!intel_ddi_init_dp_connector(intel_dig_port))
2799 goto err;
13cf5504 2800
f68d697e 2801 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2802 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2803 }
21a8e6a4 2804
311a2094
PZ		 2805 /* In theory we don't need the encoder->type check, but leave it just in
2806 * case we have some really bad VBTs... */
f68d697e
CW		 2807 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2808 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2809 goto err;
21a8e6a4 2810 }
f68d697e 2811
ff662124
SS		 2812 if (init_lspcon) {
2813 if (lspcon_init(intel_dig_port))
2814 /* TODO: handle hdmi info frame part */
2815 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2816 port_name(port));
2817 else
2818 /*
2819 * LSPCON init faied, but DP init was success, so
2820 * lets try to drive as DP++ port.
2821 */
2822 DRM_ERROR("LSPCON init failed on port %c\n",
2823 port_name(port));
2824 }
2825
f68d697e
CW		 2826 return;
2827
2828err:
2829 drm_encoder_cleanup(encoder);
2830 kfree(intel_dig_port);
00c09d70 2831}
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