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drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b 303struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 304 u8 margin; /* swing value */
305 u8 scale; /* scale value */
306 u8 enable; /* scale enable */
307 u8 deemphasis;
96fb9f9b
VK		 308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4 356struct cnl_ddi_buf_trans {
fb5f4e96
VS		 357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
83fb7ab4
RV		 362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
da411a48 547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
da411a48
RV		 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
f8896f5d 565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 566 return skl_u_ddi_translations_edp;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 569 return skl_ddi_translations_edp;
f8896f5d
DW		 570 }
571 }
cd1101cb 572
da411a48 573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 577}
578
579static const struct ddi_buf_trans *
78ab0bae 580skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 581{
78ab0bae 582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 584 return skl_y_ddi_translations_hdmi;
f8896f5d 585 } else {
f8896f5d 586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 587 return skl_ddi_translations_hdmi;
f8896f5d 588 }
f8896f5d
DW		 589}
590
d8fe2c7f
VS		 591static const struct ddi_buf_trans *
592intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
593 int *n_entries)
594{
595 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
596 return kbl_get_buf_trans_dp(dev_priv, n_entries);
597 } else if (IS_SKYLAKE(dev_priv)) {
598 return skl_get_buf_trans_dp(dev_priv, n_entries);
599 } else if (IS_BROADWELL(dev_priv)) {
600 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
601 return bdw_ddi_translations_dp;
602 } else if (IS_HASWELL(dev_priv)) {
603 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
604 return hsw_ddi_translations_dp;
605 }
606
607 *n_entries = 0;
608 return NULL;
609}
610
611static const struct ddi_buf_trans *
612intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
613 int *n_entries)
614{
615 if (IS_GEN9_BC(dev_priv)) {
616 return skl_get_buf_trans_edp(dev_priv, n_entries);
617 } else if (IS_BROADWELL(dev_priv)) {
618 return bdw_get_buf_trans_edp(dev_priv, n_entries);
619 } else if (IS_HASWELL(dev_priv)) {
620 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
621 return hsw_ddi_translations_dp;
622 }
623
624 *n_entries = 0;
625 return NULL;
626}
627
628static const struct ddi_buf_trans *
629intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
630 int *n_entries)
631{
632 if (IS_BROADWELL(dev_priv)) {
633 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
634 return bdw_ddi_translations_fdi;
635 } else if (IS_HASWELL(dev_priv)) {
636 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
637 return hsw_ddi_translations_fdi;
638 }
639
640 *n_entries = 0;
641 return NULL;
642}
643
975786ee
VS		 644static const struct ddi_buf_trans *
645intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
646 int *n_entries)
647{
648 if (IS_GEN9_BC(dev_priv)) {
649 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
650 } else if (IS_BROADWELL(dev_priv)) {
651 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
652 return bdw_ddi_translations_hdmi;
653 } else if (IS_HASWELL(dev_priv)) {
654 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
655 return hsw_ddi_translations_hdmi;
656 }
657
658 *n_entries = 0;
659 return NULL;
660}
661
7d4f37b5
VS		 662static const struct bxt_ddi_buf_trans *
663bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
664{
665 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
666 return bxt_ddi_translations_dp;
667}
668
669static const struct bxt_ddi_buf_trans *
670bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
671{
672 if (dev_priv->vbt.edp.low_vswing) {
673 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
674 return bxt_ddi_translations_edp;
675 }
676
677 return bxt_get_buf_trans_dp(dev_priv, n_entries);
678}
679
680static const struct bxt_ddi_buf_trans *
681bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
682{
683 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
684 return bxt_ddi_translations_hdmi;
685}
686
cf3e0fb4
RV		 687static const struct cnl_ddi_buf_trans *
688cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
689{
690 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
691
692 if (voltage == VOLTAGE_INFO_0_85V) {
693 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
694 return cnl_ddi_translations_hdmi_0_85V;
695 } else if (voltage == VOLTAGE_INFO_0_95V) {
696 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
697 return cnl_ddi_translations_hdmi_0_95V;
698 } else if (voltage == VOLTAGE_INFO_1_05V) {
699 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
700 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 701 } else {
702 *n_entries = 1; /* shut up gcc */
cf3e0fb4 703 MISSING_CASE(voltage);
83482ca3 704 }
cf3e0fb4
RV		 705 return NULL;
706}
707
708static const struct cnl_ddi_buf_trans *
709cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
710{
711 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
712
713 if (voltage == VOLTAGE_INFO_0_85V) {
714 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
715 return cnl_ddi_translations_dp_0_85V;
716 } else if (voltage == VOLTAGE_INFO_0_95V) {
717 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
718 return cnl_ddi_translations_dp_0_95V;
719 } else if (voltage == VOLTAGE_INFO_1_05V) {
720 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
721 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 722 } else {
723 *n_entries = 1; /* shut up gcc */
cf3e0fb4 724 MISSING_CASE(voltage);
83482ca3 725 }
cf3e0fb4
RV		 726 return NULL;
727}
728
729static const struct cnl_ddi_buf_trans *
730cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
731{
732 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
733
734 if (dev_priv->vbt.edp.low_vswing) {
735 if (voltage == VOLTAGE_INFO_0_85V) {
736 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
737 return cnl_ddi_translations_edp_0_85V;
738 } else if (voltage == VOLTAGE_INFO_0_95V) {
739 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
740 return cnl_ddi_translations_edp_0_95V;
741 } else if (voltage == VOLTAGE_INFO_1_05V) {
742 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
743 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 744 } else {
745 *n_entries = 1; /* shut up gcc */
cf3e0fb4 746 MISSING_CASE(voltage);
83482ca3 747 }
cf3e0fb4
RV		 748 return NULL;
749 } else {
750 return cnl_get_buf_trans_dp(dev_priv, n_entries);
751 }
752}
753
8d8bb85e
VS		 754static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
755{
756 int n_hdmi_entries;
757 int hdmi_level;
758 int hdmi_default_entry;
759
760 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
761
cc3f90f0 762 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 763 return hdmi_level;
764
bf503556
RV		 765 if (IS_CANNONLAKE(dev_priv)) {
766 cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
767 hdmi_default_entry = n_hdmi_entries - 1;
768 } else if (IS_GEN9_BC(dev_priv)) {
975786ee 769 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
8d8bb85e
VS		 770 hdmi_default_entry = 8;
771 } else if (IS_BROADWELL(dev_priv)) {
975786ee 772 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
8d8bb85e
VS		 773 hdmi_default_entry = 7;
774 } else if (IS_HASWELL(dev_priv)) {
975786ee 775 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
8d8bb85e
VS		 776 hdmi_default_entry = 6;
777 } else {
778 WARN(1, "ddi translation table missing\n");
975786ee 779 return 0;
8d8bb85e
VS		 780 }
781
782 /* Choose a good default if VBT is badly populated */
783 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
784 hdmi_level >= n_hdmi_entries)
785 hdmi_level = hdmi_default_entry;
786
787 return hdmi_level;
788}
789
e58623cb
AR		 790/*
791 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 792 * values in advance. This function programs the correct values for
793 * DP/eDP/FDI use cases.
45244b87 794 */
d7c530b2 795static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 796{
6a7e4f99 797 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 798 u32 iboost_bit = 0;
7d1c42e6 799 int i, n_entries;
32bdc400 800 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 801 const struct ddi_buf_trans *ddi_translations;
e58623cb 802
7d1c42e6
VS		 803 switch (encoder->type) {
804 case INTEL_OUTPUT_EDP:
805 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
806 &n_entries);
807 break;
808 case INTEL_OUTPUT_DP:
809 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
810 &n_entries);
811 break;
812 case INTEL_OUTPUT_ANALOG:
813 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
814 &n_entries);
815 break;
816 default:
817 MISSING_CASE(encoder->type);
818 return;
e58623cb
AR		 819 }
820
b976dc53 821 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 822 /* If we're boosting the current, set bit 31 of trans1 */
823 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
824 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
825
826 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
827 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 828 n_entries > 9))
829 n_entries = 9;
300644c7 830 }
45244b87 831
7d1c42e6 832 for (i = 0; i < n_entries; i++) {
9712e688
VS		 833 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
834 ddi_translations[i].trans1 | iboost_bit);
835 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
836 ddi_translations[i].trans2);
45244b87 837 }
32bdc400
VS		 838}
839
840/*
841 * Starting with Haswell, DDI port buffers must be programmed with correct
842 * values in advance. This function programs the correct values for
843 * HDMI/DVI use cases.
844 */
7ea79333
VS		 845static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
846 int hdmi_level)
32bdc400
VS		 847{
848 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
849 u32 iboost_bit = 0;
7ea79333 850 int n_hdmi_entries;
32bdc400
VS		 851 enum port port = intel_ddi_get_encoder_port(encoder);
852 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 853
975786ee 854 ddi_translations_hdmi = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 855
975786ee
VS		 856 /* If we're boosting the current, set bit 31 of trans1 */
857 if (IS_GEN9_BC(dev_priv) &&
858 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
859 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 860
6acab15a 861 /* Entry 9 is for HDMI: */
ed9c77d2 862 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 863 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 864 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 865 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 866}
867
248138b5
PZ		 868static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
869 enum port port)
870{
f0f59a00 871 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 872 int i;
873
3449ca85 874 for (i = 0; i < 16; i++) {
248138b5
PZ		 875 udelay(1);
876 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
877 return;
878 }
879 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
880}
c82e4d26 881
5f88a9c6 882static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a
ACO		 883{
884 switch (pll->id) {
885 case DPLL_ID_WRPLL1:
886 return PORT_CLK_SEL_WRPLL1;
887 case DPLL_ID_WRPLL2:
888 return PORT_CLK_SEL_WRPLL2;
889 case DPLL_ID_SPLL:
890 return PORT_CLK_SEL_SPLL;
891 case DPLL_ID_LCPLL_810:
892 return PORT_CLK_SEL_LCPLL_810;
893 case DPLL_ID_LCPLL_1350:
894 return PORT_CLK_SEL_LCPLL_1350;
895 case DPLL_ID_LCPLL_2700:
896 return PORT_CLK_SEL_LCPLL_2700;
897 default:
898 MISSING_CASE(pll->id);
899 return PORT_CLK_SEL_NONE;
900 }
901}
902
c82e4d26
ED		 903/* Starting with Haswell, different DDI ports can work in FDI mode for
904 * connection to the PCH-located connectors. For this, it is necessary to train
905 * both the DDI port and PCH receiver for the desired DDI buffer settings.
906 *
907 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
908 * please note that when FDI mode is active on DDI E, it shares 2 lines with
909 * DDI A (which is used for eDP)
910 */
911
dc4a1094
ACO		 912void hsw_fdi_link_train(struct intel_crtc *crtc,
913 const struct intel_crtc_state *crtc_state)
c82e4d26 914{
4cbe4b2b 915 struct drm_device *dev = crtc->base.dev;
fac5e23e 916 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 917 struct intel_encoder *encoder;
c856052a 918 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 919
4cbe4b2b 920 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 921 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 922 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 923 }
924
04945641
PZ		 925 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
926 * mode set "sequence for CRT port" document:
927 * - TP1 to TP2 time with the default value
928 * - FDI delay to 90h
8693a824
DL		 929 *
930 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 931 */
eede3b53 932 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 933 FDI_RX_PWRDN_LANE0_VAL(2) |
934 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
935
936 /* Enable the PCH Receiver FDI PLL */
3e68320e 937 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 938 FDI_RX_PLL_ENABLE |
dc4a1094 939 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 940 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
941 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 942 udelay(220);
943
944 /* Switch from Rawclk to PCDclk */
945 rx_ctl_val |= FDI_PCDCLK;
eede3b53 946 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 947
948 /* Configure Port Clock Select */
dc4a1094 949 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 950 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
951 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 952
953 /* Start the training iterating through available voltages and emphasis,
954 * testing each value twice. */
10122051 955 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 956 /* Configure DP_TP_CTL with auto-training */
957 I915_WRITE(DP_TP_CTL(PORT_E),
958 DP_TP_CTL_FDI_AUTOTRAIN |
959 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
960 DP_TP_CTL_LINK_TRAIN_PAT1 |
961 DP_TP_CTL_ENABLE);
962
876a8cdf
DL		 963 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
964 * DDI E does not support port reversal, the functionality is
965 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
966 * port reversal bit */
c82e4d26 967 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 968 DDI_BUF_CTL_ENABLE |
dc4a1094 969 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 970 DDI_BUF_TRANS_SELECT(i / 2));
04945641 971 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 972
973 udelay(600);
974
04945641 975 /* Program PCH FDI Receiver TU */
eede3b53 976 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 977
978 /* Enable PCH FDI Receiver with auto-training */
979 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 980 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
981 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 982
983 /* Wait for FDI receiver lane calibration */
984 udelay(30);
985
986 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 987 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 988 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 989 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
990 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 991
992 /* Wait for FDI auto training time */
993 udelay(5);
c82e4d26
ED		 994
995 temp = I915_READ(DP_TP_STATUS(PORT_E));
996 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 997 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 998 break;
999 }
c82e4d26 1000
a308ccb3
VS		 1001 /*
1002 * Leave things enabled even if we failed to train FDI.
1003 * Results in less fireworks from the state checker.
1004 */
1005 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1006 DRM_ERROR("FDI link training failed!\n");
1007 break;
c82e4d26 1008 }
04945641 1009
5b421c57
VS		 1010 rx_ctl_val &= ~FDI_RX_ENABLE;
1011 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1012 POSTING_READ(FDI_RX_CTL(PIPE_A));
1013
248138b5
PZ		 1014 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1015 temp &= ~DDI_BUF_CTL_ENABLE;
1016 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1017 POSTING_READ(DDI_BUF_CTL(PORT_E));
1018
04945641 1019 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1020 temp = I915_READ(DP_TP_CTL(PORT_E));
1021 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1022 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1023 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1024 POSTING_READ(DP_TP_CTL(PORT_E));
1025
1026 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1027
04945641 1028 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1029 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1030 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1031 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1032 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1033 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1034 }
1035
a308ccb3
VS		 1036 /* Enable normal pixel sending for FDI */
1037 I915_WRITE(DP_TP_CTL(PORT_E),
1038 DP_TP_CTL_FDI_AUTOTRAIN |
1039 DP_TP_CTL_LINK_TRAIN_NORMAL |
1040 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1041 DP_TP_CTL_ENABLE);
c82e4d26 1042}
0e72a5b5 1043
d7c530b2 1044static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1045{
1046 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1047 struct intel_digital_port *intel_dig_port =
1048 enc_to_dig_port(&encoder->base);
1049
1050 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1051 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1052 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1053}
1054
8d9ddbcb 1055static struct intel_encoder *
e9ce1a62 1056intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1057{
e9ce1a62 1058 struct drm_device *dev = crtc->base.dev;
1524e93e 1059 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1060 int num_encoders = 0;
1061
1524e93e
SS		 1062 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1063 ret = encoder;
8d9ddbcb
PZ		 1064 num_encoders++;
1065 }
1066
1067 if (num_encoders != 1)
84f44ce7 1068 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1069 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1070
1071 BUG_ON(ret == NULL);
1072 return ret;
1073}
1074
44a126ba
PZ		 1075/* Finds the only possible encoder associated with the given CRTC. */
1076struct intel_encoder *
3165c074 1077intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 1078{
3165c074
ACO		 1079 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1080 struct intel_encoder *ret = NULL;
1081 struct drm_atomic_state *state;
da3ced29
ACO		 1082 struct drm_connector *connector;
1083 struct drm_connector_state *connector_state;
d0737e1d 1084 int num_encoders = 0;
3165c074 1085 int i;
d0737e1d 1086
3165c074
ACO		 1087 state = crtc_state->base.state;
1088
b77c7a90 1089 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 1090 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 1091 continue;
1092
da3ced29 1093 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 1094 num_encoders++;
d0737e1d
ACO		 1095 }
1096
1097 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1098 pipe_name(crtc->pipe));
1099
1100 BUG_ON(ret == NULL);
1101 return ret;
1102}
1103
1c0b85c5 1104#define LC_FREQ 2700
1c0b85c5 1105
f0f59a00
VS		 1106static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1107 i915_reg_t reg)
11578553
JB		 1108{
1109 int refclk = LC_FREQ;
1110 int n, p, r;
1111 u32 wrpll;
1112
1113 wrpll = I915_READ(reg);
114fe488
DV		 1114 switch (wrpll & WRPLL_PLL_REF_MASK) {
1115 case WRPLL_PLL_SSC:
1116 case WRPLL_PLL_NON_SSC:
11578553
JB		 1117 /*
1118 * We could calculate spread here, but our checking
1119 * code only cares about 5% accuracy, and spread is a max of
1120 * 0.5% downspread.
1121 */
1122 refclk = 135;
1123 break;
114fe488 1124 case WRPLL_PLL_LCPLL:
11578553
JB		 1125 refclk = LC_FREQ;
1126 break;
1127 default:
1128 WARN(1, "bad wrpll refclk\n");
1129 return 0;
1130 }
1131
1132 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1133 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1134 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1135
20f0ec16
JB		 1136 /* Convert to KHz, p & r have a fixed point portion */
1137 return (refclk * n * 100) / (p * r);
11578553
JB		 1138}
1139
540e732c
S		 1140static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1141 uint32_t dpll)
1142{
f0f59a00 1143 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1144 uint32_t cfgcr1_val, cfgcr2_val;
1145 uint32_t p0, p1, p2, dco_freq;
1146
923c1241
VS		 1147 cfgcr1_reg = DPLL_CFGCR1(dpll);
1148 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1149
1150 cfgcr1_val = I915_READ(cfgcr1_reg);
1151 cfgcr2_val = I915_READ(cfgcr2_reg);
1152
1153 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1154 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1155
1156 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1157 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1158 else
1159 p1 = 1;
1160
1161
1162 switch (p0) {
1163 case DPLL_CFGCR2_PDIV_1:
1164 p0 = 1;
1165 break;
1166 case DPLL_CFGCR2_PDIV_2:
1167 p0 = 2;
1168 break;
1169 case DPLL_CFGCR2_PDIV_3:
1170 p0 = 3;
1171 break;
1172 case DPLL_CFGCR2_PDIV_7:
1173 p0 = 7;
1174 break;
1175 }
1176
1177 switch (p2) {
1178 case DPLL_CFGCR2_KDIV_5:
1179 p2 = 5;
1180 break;
1181 case DPLL_CFGCR2_KDIV_2:
1182 p2 = 2;
1183 break;
1184 case DPLL_CFGCR2_KDIV_3:
1185 p2 = 3;
1186 break;
1187 case DPLL_CFGCR2_KDIV_1:
1188 p2 = 1;
1189 break;
1190 }
1191
1192 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1193
1194 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1195 1000) / 0x8000;
1196
1197 return dco_freq / (p0 * p1 * p2 * 5);
1198}
1199
a9701a89
RV		 1200static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1201 uint32_t pll_id)
1202{
1203 uint32_t cfgcr0, cfgcr1;
1204 uint32_t p0, p1, p2, dco_freq, ref_clock;
1205
1206 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1207 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1208
1209 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1210 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1211
1212 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1213 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1214 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1215 else
1216 p1 = 1;
1217
1218
1219 switch (p0) {
1220 case DPLL_CFGCR1_PDIV_2:
1221 p0 = 2;
1222 break;
1223 case DPLL_CFGCR1_PDIV_3:
1224 p0 = 3;
1225 break;
1226 case DPLL_CFGCR1_PDIV_5:
1227 p0 = 5;
1228 break;
1229 case DPLL_CFGCR1_PDIV_7:
1230 p0 = 7;
1231 break;
1232 }
1233
1234 switch (p2) {
1235 case DPLL_CFGCR1_KDIV_1:
1236 p2 = 1;
1237 break;
1238 case DPLL_CFGCR1_KDIV_2:
1239 p2 = 2;
1240 break;
1241 case DPLL_CFGCR1_KDIV_4:
1242 p2 = 4;
1243 break;
1244 }
1245
1246 ref_clock = dev_priv->cdclk.hw.ref;
1247
1248 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1249
1250 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1251 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1252
0e005888
PZ		 1253 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1254 return 0;
1255
a9701a89
RV		 1256 return dco_freq / (p0 * p1 * p2 * 5);
1257}
1258
398a017e
VS		 1259static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1260{
1261 int dotclock;
1262
1263 if (pipe_config->has_pch_encoder)
1264 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1265 &pipe_config->fdi_m_n);
37a5650b 1266 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1267 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1268 &pipe_config->dp_m_n);
1269 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1270 dotclock = pipe_config->port_clock * 2 / 3;
1271 else
1272 dotclock = pipe_config->port_clock;
1273
b22ca995
SS		 1274 if (pipe_config->ycbcr420)
1275 dotclock *= 2;
1276
398a017e
VS		 1277 if (pipe_config->pixel_multiplier)
1278 dotclock /= pipe_config->pixel_multiplier;
1279
1280 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1281}
540e732c 1282
a9701a89
RV		 1283static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1284 struct intel_crtc_state *pipe_config)
1285{
1286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1287 int link_clock = 0;
1288 uint32_t cfgcr0, pll_id;
1289
1290 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1291
1292 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1293
1294 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1295 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1296 } else {
1297 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1298
1299 switch (link_clock) {
1300 case DPLL_CFGCR0_LINK_RATE_810:
1301 link_clock = 81000;
1302 break;
1303 case DPLL_CFGCR0_LINK_RATE_1080:
1304 link_clock = 108000;
1305 break;
1306 case DPLL_CFGCR0_LINK_RATE_1350:
1307 link_clock = 135000;
1308 break;
1309 case DPLL_CFGCR0_LINK_RATE_1620:
1310 link_clock = 162000;
1311 break;
1312 case DPLL_CFGCR0_LINK_RATE_2160:
1313 link_clock = 216000;
1314 break;
1315 case DPLL_CFGCR0_LINK_RATE_2700:
1316 link_clock = 270000;
1317 break;
1318 case DPLL_CFGCR0_LINK_RATE_3240:
1319 link_clock = 324000;
1320 break;
1321 case DPLL_CFGCR0_LINK_RATE_4050:
1322 link_clock = 405000;
1323 break;
1324 default:
1325 WARN(1, "Unsupported link rate\n");
1326 break;
1327 }
1328 link_clock *= 2;
1329 }
1330
1331 pipe_config->port_clock = link_clock;
1332
1333 ddi_dotclock_get(pipe_config);
1334}
1335
540e732c 1336static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1337 struct intel_crtc_state *pipe_config)
540e732c 1338{
fac5e23e 1339 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1340 int link_clock = 0;
1341 uint32_t dpll_ctl1, dpll;
1342
c856052a 1343 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1344
1345 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1346
1347 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1348 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1349 } else {
71cd8423
DL		 1350 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1351 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1352
1353 switch (link_clock) {
71cd8423 1354 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1355 link_clock = 81000;
1356 break;
71cd8423 1357 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1358 link_clock = 108000;
1359 break;
71cd8423 1360 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1361 link_clock = 135000;
1362 break;
71cd8423 1363 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1364 link_clock = 162000;
1365 break;
71cd8423 1366 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1367 link_clock = 216000;
1368 break;
71cd8423 1369 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1370 link_clock = 270000;
1371 break;
1372 default:
1373 WARN(1, "Unsupported link rate\n");
1374 break;
1375 }
1376 link_clock *= 2;
1377 }
1378
1379 pipe_config->port_clock = link_clock;
1380
398a017e 1381 ddi_dotclock_get(pipe_config);
540e732c
S		 1382}
1383
3d51278a 1384static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1385 struct intel_crtc_state *pipe_config)
11578553 1386{
fac5e23e 1387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1388 int link_clock = 0;
1389 u32 val, pll;
1390
c856052a 1391 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1392 switch (val & PORT_CLK_SEL_MASK) {
1393 case PORT_CLK_SEL_LCPLL_810:
1394 link_clock = 81000;
1395 break;
1396 case PORT_CLK_SEL_LCPLL_1350:
1397 link_clock = 135000;
1398 break;
1399 case PORT_CLK_SEL_LCPLL_2700:
1400 link_clock = 270000;
1401 break;
1402 case PORT_CLK_SEL_WRPLL1:
01403de3 1403 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1404 break;
1405 case PORT_CLK_SEL_WRPLL2:
01403de3 1406 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1407 break;
1408 case PORT_CLK_SEL_SPLL:
1409 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1410 if (pll == SPLL_PLL_FREQ_810MHz)
1411 link_clock = 81000;
1412 else if (pll == SPLL_PLL_FREQ_1350MHz)
1413 link_clock = 135000;
1414 else if (pll == SPLL_PLL_FREQ_2700MHz)
1415 link_clock = 270000;
1416 else {
1417 WARN(1, "bad spll freq\n");
1418 return;
1419 }
1420 break;
1421 default:
1422 WARN(1, "bad port clock sel\n");
1423 return;
1424 }
1425
1426 pipe_config->port_clock = link_clock * 2;
1427
398a017e 1428 ddi_dotclock_get(pipe_config);
11578553
JB		 1429}
1430
977bb38d
S		 1431static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1432 enum intel_dpll_id dpll)
1433{
aa610dcb
ID		 1434 struct intel_shared_dpll *pll;
1435 struct intel_dpll_hw_state *state;
9e2c8475 1436 struct dpll clock;
aa610dcb
ID		 1437
1438 /* For DDI ports we always use a shared PLL. */
1439 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1440 return 0;
1441
1442 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1443 state = &pll->state.hw_state;
aa610dcb
ID		 1444
1445 clock.m1 = 2;
1446 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1447 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1448 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1449 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1450 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1451 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1452
1453 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1454}
1455
1456static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1457 struct intel_crtc_state *pipe_config)
1458{
fac5e23e 1459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1460 enum port port = intel_ddi_get_encoder_port(encoder);
1461 uint32_t dpll = port;
1462
398a017e 1463 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1464
398a017e 1465 ddi_dotclock_get(pipe_config);
977bb38d
S		 1466}
1467
3d51278a 1468void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1469 struct intel_crtc_state *pipe_config)
3d51278a 1470{
0853723b 1471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1472
0853723b 1473 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1474 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1475 else if (IS_GEN9_BC(dev_priv))
22606a18 1476 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1477 else if (IS_GEN9_LP(dev_priv))
977bb38d 1478 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1479 else if (IS_CANNONLAKE(dev_priv))
1480 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1481}
1482
3dc38eea 1483void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1484{
3dc38eea 1485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1487 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1488 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1489 int type = encoder->type;
dae84799
PZ		 1490 uint32_t temp;
1491
cca0502b 1492 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1493 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1494
c9809791 1495 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1496 switch (crtc_state->pipe_bpp) {
dae84799 1497 case 18:
c9809791 1498 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1499 break;
1500 case 24:
c9809791 1501 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1502 break;
1503 case 30:
c9809791 1504 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1505 break;
1506 case 36:
c9809791 1507 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1508 break;
1509 default:
4e53c2e0 1510 BUG();
dae84799 1511 }
c9809791 1512 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1513 }
1514}
1515
3dc38eea
ACO		 1516void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1517 bool state)
0e32b39c 1518{
3dc38eea 1519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1521 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1522 uint32_t temp;
1523 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1524 if (state == true)
1525 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1526 else
1527 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1528 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1529}
1530
3dc38eea 1531void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1532{
3dc38eea 1533 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1534 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536 enum pipe pipe = crtc->pipe;
3dc38eea 1537 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1538 enum port port = intel_ddi_get_encoder_port(encoder);
1539 int type = encoder->type;
8d9ddbcb
PZ		 1540 uint32_t temp;
1541
ad80a810
PZ		 1542 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1543 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1544 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1545
3dc38eea 1546 switch (crtc_state->pipe_bpp) {
dfcef252 1547 case 18:
ad80a810 1548 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1549 break;
1550 case 24:
ad80a810 1551 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1552 break;
1553 case 30:
ad80a810 1554 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1555 break;
1556 case 36:
ad80a810 1557 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1558 break;
1559 default:
4e53c2e0 1560 BUG();
dfcef252 1561 }
72662e10 1562
3dc38eea 1563 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1564 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1565 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1566 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1567
e6f0bfc4
PZ		 1568 if (cpu_transcoder == TRANSCODER_EDP) {
1569 switch (pipe) {
1570 case PIPE_A:
c7670b10
PZ		 1571 /* On Haswell, can only use the always-on power well for
1572 * eDP when not using the panel fitter, and when not
1573 * using motion blur mitigation (which we don't
1574 * support). */
772c2a51 1575 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1576 (crtc_state->pch_pfit.enabled ||
1577 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1578 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1579 else
1580 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1581 break;
1582 case PIPE_B:
1583 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1584 break;
1585 case PIPE_C:
1586 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1587 break;
1588 default:
1589 BUG();
1590 break;
1591 }
1592 }
1593
7739c33b 1594 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1595 if (crtc_state->has_hdmi_sink)
ad80a810 1596 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1597 else
ad80a810 1598 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1599
1600 if (crtc_state->hdmi_scrambling)
1601 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1602 if (crtc_state->hdmi_high_tmds_clock_ratio)
1603 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1604 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1605 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1606 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1607 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1608 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1609 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1610 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1611 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1612 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1613 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1614 } else {
84f44ce7 1615 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1616 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1617 }
1618
ad80a810 1619 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1620}
72662e10 1621
ad80a810
PZ		 1622void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1623 enum transcoder cpu_transcoder)
8d9ddbcb 1624{
f0f59a00 1625 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1626 uint32_t val = I915_READ(reg);
1627
0e32b39c 1628 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1629 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1630 I915_WRITE(reg, val);
72662e10
ED		 1631}
1632
bcbc889b
PZ		 1633bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1634{
1635 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1636 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1637 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1638 int type = intel_connector->base.connector_type;
1524e93e 1639 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1640 enum pipe pipe = 0;
1641 enum transcoder cpu_transcoder;
1642 uint32_t tmp;
e27daab4 1643 bool ret;
bcbc889b 1644
79f255a0 1645 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1646 encoder->power_domain))
882244a3
PZ		 1647 return false;
1648
1524e93e 1649 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1650 ret = false;
1651 goto out;
1652 }
bcbc889b
PZ		 1653
1654 if (port == PORT_A)
1655 cpu_transcoder = TRANSCODER_EDP;
1656 else
1a240d4d 1657 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1658
1659 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1660
1661 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1662 case TRANS_DDI_MODE_SELECT_HDMI:
1663 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1664 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1665 break;
bcbc889b
PZ		 1666
1667 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1668 ret = type == DRM_MODE_CONNECTOR_eDP ||
1669 type == DRM_MODE_CONNECTOR_DisplayPort;
1670 break;
1671
0e32b39c
DA		 1672 case TRANS_DDI_MODE_SELECT_DP_MST:
1673 /* if the transcoder is in MST state then
1674 * connector isn't connected */
e27daab4
ID		 1675 ret = false;
1676 break;
bcbc889b
PZ		 1677
1678 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1679 ret = type == DRM_MODE_CONNECTOR_VGA;
1680 break;
bcbc889b
PZ		 1681
1682 default:
e27daab4
ID		 1683 ret = false;
1684 break;
bcbc889b 1685 }
e27daab4
ID		 1686
1687out:
1524e93e 1688 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1689
1690 return ret;
bcbc889b
PZ		 1691}
1692
85234cdc
DV		 1693bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1694 enum pipe *pipe)
1695{
1696 struct drm_device *dev = encoder->base.dev;
fac5e23e 1697 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1698 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1699 u32 tmp;
1700 int i;
e27daab4 1701 bool ret;
85234cdc 1702
79f255a0
ACO		 1703 if (!intel_display_power_get_if_enabled(dev_priv,
1704 encoder->power_domain))
6d129bea
ID		 1705 return false;
1706
e27daab4
ID		 1707 ret = false;
1708
fe43d3f5 1709 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1710
1711 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1712 goto out;
85234cdc 1713
ad80a810
PZ		 1714 if (port == PORT_A) {
1715 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1716
ad80a810
PZ		 1717 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1718 case TRANS_DDI_EDP_INPUT_A_ON:
1719 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1720 *pipe = PIPE_A;
1721 break;
1722 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1723 *pipe = PIPE_B;
1724 break;
1725 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1726 *pipe = PIPE_C;
1727 break;
1728 }
1729
e27daab4 1730 ret = true;
ad80a810 1731
e27daab4
ID		 1732 goto out;
1733 }
0e32b39c 1734
e27daab4
ID		 1735 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1736 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1737
1738 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1739 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1740 TRANS_DDI_MODE_SELECT_DP_MST)
1741 goto out;
1742
1743 *pipe = i;
1744 ret = true;
1745
1746 goto out;
85234cdc
DV		 1747 }
1748 }
1749
84f44ce7 1750 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1751
e27daab4 1752out:
cc3f90f0 1753 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0 1754 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 1755 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1756 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 1757 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1758 DRM_ERROR("Port %c enabled but PHY powered down? "
1759 "(PHY_CTL %08x)\n", port_name(port), tmp);
1760 }
1761
79f255a0 1762 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1763
1764 return ret;
85234cdc
DV		 1765}
1766
62b69566
ACO		 1767static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1768{
1769 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1770 enum pipe pipe;
1771
1772 if (intel_ddi_get_hw_state(encoder, &pipe))
1773 return BIT_ULL(dig_port->ddi_io_power_domain);
1774
1775 return 0;
1776}
1777
3dc38eea 1778void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1779{
3dc38eea 1780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1781 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1782 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1783 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1784 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1785
bb523fc0
PZ		 1786 if (cpu_transcoder != TRANSCODER_EDP)
1787 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1788 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1789}
1790
3dc38eea 1791void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1792{
3dc38eea
ACO		 1793 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1794 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1795
bb523fc0
PZ		 1796 if (cpu_transcoder != TRANSCODER_EDP)
1797 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1798 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1799}
1800
a7d8dbc0
VS		 1801static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1802 enum port port, uint8_t iboost)
f8896f5d 1803{
a7d8dbc0
VS		 1804 u32 tmp;
1805
1806 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1807 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1808 if (iboost)
1809 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1810 else
1811 tmp |= BALANCE_LEG_DISABLE(port);
1812 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1813}
1814
081dfcfa
VS		 1815static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1816 int level, enum intel_output_type type)
a7d8dbc0
VS		 1817{
1818 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1819 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1820 enum port port = intel_dig_port->port;
f8896f5d 1821 uint8_t iboost;
f8896f5d 1822
081dfcfa
VS		 1823 if (type == INTEL_OUTPUT_HDMI)
1824 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1825 else
1826 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 1827
081dfcfa
VS		 1828 if (iboost == 0) {
1829 const struct ddi_buf_trans *ddi_translations;
1830 int n_entries;
1831
1832 if (type == INTEL_OUTPUT_HDMI)
1833 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1834 else if (type == INTEL_OUTPUT_EDP)
d8fe2c7f 1835 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
081dfcfa
VS		 1836 else
1837 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
10afa0b6 1838
081dfcfa
VS		 1839 if (WARN_ON(type != INTEL_OUTPUT_HDMI &&
1840 port != PORT_A &&
1841 port != PORT_E && n_entries > 9))
1842 n_entries = 9;
10afa0b6 1843
081dfcfa 1844 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 1845 }
1846
1847 /* Make sure that the requested I_boost is valid */
1848 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1849 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1850 return;
1851 }
1852
a7d8dbc0 1853 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1854
a7d8dbc0
VS		 1855 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1856 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1857}
1858
7d4f37b5
VS		 1859static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1860 int level, enum intel_output_type type)
96fb9f9b 1861{
7d4f37b5 1862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 1863 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5
VS		 1864 enum port port = encoder->port;
1865 int n_entries, i;
1866
1867 if (type == INTEL_OUTPUT_HDMI)
1868 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1869 else if (type == INTEL_OUTPUT_EDP)
1870 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1871 else
1872 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b
VK		 1873
1874 /* Check if default value has to be used */
1875 if (level >= n_entries ||
1876 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1877 for (i = 0; i < n_entries; i++) {
1878 if (ddi_translations[i].default_index) {
1879 level = i;
1880 break;
1881 }
1882 }
1883 }
1884
b6e08203
ACO		 1885 bxt_ddi_phy_set_signal_level(dev_priv, port,
1886 ddi_translations[level].margin,
1887 ddi_translations[level].scale,
1888 ddi_translations[level].enable,
1889 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1890}
1891
ffe5111e
VS		 1892u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1893{
1894 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1895 int n_entries;
1896
5fcf34b1
RV		 1897 if (IS_CANNONLAKE(dev_priv)) {
1898 if (encoder->type == INTEL_OUTPUT_EDP)
1899 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1900 else
1901 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 1902 } else if (IS_GEN9_LP(dev_priv)) {
1903 if (encoder->type == INTEL_OUTPUT_EDP)
1904 bxt_get_buf_trans_edp(dev_priv, &n_entries);
1905 else
1906 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 1907 } else {
1908 if (encoder->type == INTEL_OUTPUT_EDP)
1909 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1910 else
1911 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1912 }
ffe5111e
VS		 1913
1914 if (WARN_ON(n_entries < 1))
1915 n_entries = 1;
1916 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1917 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1918
1919 return index_to_dp_signal_levels[n_entries - 1] &
1920 DP_TRAIN_VOLTAGE_SWING_MASK;
1921}
1922
cf54ca8b
RV		 1923static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1924 u32 level, enum port port, int type)
1925{
1926 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
cc9cabfd 1927 u32 n_entries, val;
cf54ca8b
RV		 1928 int ln;
1929
cf54ca8b 1930 if (type == INTEL_OUTPUT_HDMI) {
cc9cabfd 1931 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
cf54ca8b 1932 } else if (type == INTEL_OUTPUT_DP) {
cc9cabfd 1933 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 1934 } else if (type == INTEL_OUTPUT_EDP) {
cc9cabfd 1935 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
cf54ca8b
RV		 1936 }
1937
cc9cabfd 1938 if (WARN_ON(ddi_translations == NULL))
cf54ca8b 1939 return;
cf54ca8b
RV		 1940
1941 if (level >= n_entries) {
1942 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1943 level = n_entries - 1;
1944 }
1945
1946 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1947 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1948 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1949 val |= SCALING_MODE_SEL(2);
1950 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1951
1952 /* Program PORT_TX_DW2 */
1953 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1954 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1955 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1956 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1957 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1958 /* Rcomp scalar is fixed as 0x98 for every table entry */
1959 val |= RCOMP_SCALAR(0x98);
1960 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1961
20303eb4 1962 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 1963 /* We cannot write to GRP. It would overrite individual loadgen */
1964 for (ln = 0; ln < 4; ln++) {
1965 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1966 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1967 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1968 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1969 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1970 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1971 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1972 }
1973
20303eb4 1974 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 1975 /* All DW5 values are fixed for every table entry */
1976 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1977 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1978 val |= RTERM_SELECT(6);
1979 val |= TAP3_DISABLE;
1980 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1981
20303eb4 1982 /* Program PORT_TX_DW7 */
cf54ca8b 1983 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1984 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1985 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1986 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1987}
1988
0091abc3 1989static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1990{
0091abc3
CT		 1991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1992 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1993 enum port port = intel_ddi_get_encoder_port(encoder);
1994 int type = encoder->type;
1995 int width = 0;
1996 int rate = 0;
cf54ca8b 1997 u32 val;
0091abc3
CT		 1998 int ln = 0;
1999
2000 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
2001 width = intel_dp->lane_count;
2002 rate = intel_dp->link_rate;
61f3e770 2003 } else if (type == INTEL_OUTPUT_HDMI) {
0091abc3
CT		 2004 width = 4;
2005 /* Rate is always < than 6GHz for HDMI */
61f3e770
RV		 2006 } else {
2007 MISSING_CASE(type);
2008 return;
0091abc3 2009 }
cf54ca8b
RV		 2010
2011 /*
2012 * 1. If port type is eDP or DP,
2013 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2014 * else clear to 0b.
2015 */
2016 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2017 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
2018 val |= COMMON_KEEPER_EN;
2019 else
2020 val &= ~COMMON_KEEPER_EN;
2021 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2022
2023 /* 2. Program loadgen select */
2024 /*
0091abc3
CT		 2025 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2026 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2027 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2028 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2029 */
0091abc3
CT		 2030 for (ln = 0; ln <= 3; ln++) {
2031 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2032 val &= ~LOADGEN_SELECT;
2033
a8e45a1c
NM		 2034 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2035 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2036 val |= LOADGEN_SELECT;
2037 }
2038 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2039 }
cf54ca8b
RV		 2040
2041 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2042 val = I915_READ(CNL_PORT_CL1CM_DW5);
2043 val |= SUS_CLOCK_CONFIG;
2044 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2045
2046 /* 4. Clear training enable to change swing values */
2047 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2048 val &= ~TX_TRAINING_EN;
2049 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2050
2051 /* 5. Program swing and de-emphasis */
2052 cnl_ddi_vswing_program(dev_priv, level, port, type);
2053
2054 /* 6. Set training enable to trigger update */
2055 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2056 val |= TX_TRAINING_EN;
2057 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2058}
2059
f8896f5d
DW		 2060static uint32_t translate_signal_level(int signal_levels)
2061{
97eeb872 2062 int i;
f8896f5d 2063
97eeb872
VS		 2064 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2065 if (index_to_dp_signal_levels[i] == signal_levels)
2066 return i;
f8896f5d
DW		 2067 }
2068
97eeb872
VS		 2069 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2070 signal_levels);
2071
2072 return 0;
f8896f5d
DW		 2073}
2074
1b6e2fd2
RV		 2075static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2076{
2077 uint8_t train_set = intel_dp->train_set[0];
2078 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2079 DP_TRAIN_PRE_EMPHASIS_MASK);
2080
2081 return translate_signal_level(signal_levels);
2082}
2083
d509af6c 2084u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2085{
2086 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2087 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2088 struct intel_encoder *encoder = &dport->base;
d509af6c
RV		 2089 u32 level = intel_ddi_dp_level(intel_dp);
2090
2091 if (IS_CANNONLAKE(dev_priv))
2092 cnl_ddi_vswing_sequence(encoder, level);
2093 else
7d4f37b5 2094 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2095
2096 return 0;
2097}
2098
2099uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2100{
2101 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2102 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2103 struct intel_encoder *encoder = &dport->base;
1b6e2fd2 2104 uint32_t level = intel_ddi_dp_level(intel_dp);
f8896f5d 2105
b976dc53 2106 if (IS_GEN9_BC(dev_priv))
081dfcfa 2107 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2108
f8896f5d
DW		 2109 return DDI_BUF_TRANS_SELECT(level);
2110}
2111
d7c530b2 2112static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2113 const struct intel_shared_dpll *pll)
6441ab5f 2114{
e404ba8d
VS		 2115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2116 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 2117 uint32_t val;
6441ab5f 2118
c856052a
ACO		 2119 if (WARN_ON(!pll))
2120 return;
2121
555e38d2
RV		 2122 if (IS_CANNONLAKE(dev_priv)) {
2123 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2124 val = I915_READ(DPCLKA_CFGCR0);
2125 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2126 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2127
555e38d2
RV		 2128 /*
2129 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2130 * This step and the step before must be done with separate
2131 * register writes.
2132 */
2133 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2134 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2135 I915_WRITE(DPCLKA_CFGCR0, val);
2136 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2137 /* DDI -> PLL mapping */
efa80add
S		 2138 val = I915_READ(DPLL_CTRL2);
2139
2140 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2141 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2142 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2143 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2144
2145 I915_WRITE(DPLL_CTRL2, val);
5416d871 2146
e404ba8d 2147 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 2148 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2149 }
e404ba8d
VS		 2150}
2151
6b8506d5
VS		 2152static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2153{
2154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2155 enum port port = intel_ddi_get_encoder_port(encoder);
2156
2157 if (IS_CANNONLAKE(dev_priv))
2158 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2159 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2160 else if (IS_GEN9_BC(dev_priv))
2161 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2162 DPLL_CTRL2_DDI_CLK_OFF(port));
2163 else if (INTEL_GEN(dev_priv) < 9)
2164 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2165}
2166
ba88d153 2167static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 2168 const struct intel_crtc_state *crtc_state,
2169 const struct drm_connector_state *conn_state)
e404ba8d 2170{
ba88d153
MN		 2171 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2173 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2174 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 2175 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
381f9570 2176 uint32_t level = intel_ddi_dp_level(intel_dp);
b2ccb822 2177
45e0327e 2178 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 2179
45e0327e
VS		 2180 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2181 crtc_state->lane_count, is_mst);
680b71c2
VS		 2182
2183 intel_edp_panel_on(intel_dp);
32bdc400 2184
45e0327e 2185 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2186
2187 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2188
381f9570
RV		 2189 if (IS_CANNONLAKE(dev_priv))
2190 cnl_ddi_vswing_sequence(encoder, level);
2191 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2192 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 2193 else
2f7460a7
RV		 2194 intel_prepare_dp_ddi_buffers(encoder);
2195
ba88d153 2196 intel_ddi_init_dp_buf_reg(encoder);
45e0327e 2197 if (!is_mst)
5ea2355a 2198 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
ba88d153
MN		 2199 intel_dp_start_link_train(intel_dp);
2200 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2201 intel_dp_stop_link_train(intel_dp);
2202}
901c2daf 2203
ba88d153 2204static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 2205 const struct intel_crtc_state *crtc_state,
45e0327e 2206 const struct drm_connector_state *conn_state)
ba88d153 2207{
f99be1b3
VS		 2208 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2209 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ba88d153
MN		 2211 enum port port = intel_ddi_get_encoder_port(encoder);
2212 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2213 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2214
ba88d153 2215 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
45e0327e 2216 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2217
2218 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2219
2f7460a7
RV		 2220 if (IS_CANNONLAKE(dev_priv))
2221 cnl_ddi_vswing_sequence(encoder, level);
cc3f90f0 2222 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2223 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 2224 else
7ea79333 2225 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7
RV		 2226
2227 if (IS_GEN9_BC(dev_priv))
081dfcfa 2228 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 2229
f99be1b3 2230 intel_dig_port->set_infoframes(&encoder->base,
45e0327e 2231 crtc_state->has_infoframe,
f99be1b3 2232 crtc_state, conn_state);
ba88d153 2233}
32bdc400 2234
1524e93e 2235static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 2236 const struct intel_crtc_state *crtc_state,
5f88a9c6 2237 const struct drm_connector_state *conn_state)
ba88d153 2238{
45e0327e
VS		 2239 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2241 enum pipe pipe = crtc->pipe;
30cf6db8 2242
45e0327e 2243 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1
JN		 2244
2245 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2246
45e0327e
VS		 2247 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2248 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2249 else
2250 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
6441ab5f
PZ		 2251}
2252
e725f645
VS		 2253static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2254{
2255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2256 enum port port = intel_ddi_get_encoder_port(encoder);
2257 bool wait = false;
2258 u32 val;
2259
2260 val = I915_READ(DDI_BUF_CTL(port));
2261 if (val & DDI_BUF_CTL_ENABLE) {
2262 val &= ~DDI_BUF_CTL_ENABLE;
2263 I915_WRITE(DDI_BUF_CTL(port), val);
2264 wait = true;
2265 }
2266
2267 val = I915_READ(DP_TP_CTL(port));
2268 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2269 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2270 I915_WRITE(DP_TP_CTL(port), val);
2271
2272 if (wait)
2273 intel_wait_ddi_buf_idle(dev_priv, port);
2274}
2275
f45f3da7
VS		 2276static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2277 const struct intel_crtc_state *old_crtc_state,
2278 const struct drm_connector_state *old_conn_state)
6441ab5f 2279{
f45f3da7
VS		 2280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2281 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2282 struct intel_dp *intel_dp = &dig_port->dp;
2283 /*
2284 * old_crtc_state and old_conn_state are NULL when called from
2285 * DP_MST. The main connector associated with this port is never
2286 * bound to a crtc for MST.
2287 */
2288 bool is_mst = !old_crtc_state;
2886e93f 2289
f45f3da7
VS		 2290 /*
2291 * Power down sink before disabling the port, otherwise we end
2292 * up getting interrupts from the sink on detecting link loss.
2293 */
2294 if (!is_mst)
2295 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
c5f93fcf 2296
f45f3da7 2297 intel_disable_ddi_buf(encoder);
7618138d 2298
f45f3da7
VS		 2299 intel_edp_panel_vdd_on(intel_dp);
2300 intel_edp_panel_off(intel_dp);
a836bdf9 2301
f45f3da7 2302 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
c5f93fcf 2303
f45f3da7
VS		 2304 intel_ddi_clk_disable(encoder);
2305}
c5f93fcf 2306
f45f3da7
VS		 2307static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2308 const struct intel_crtc_state *old_crtc_state,
2309 const struct drm_connector_state *old_conn_state)
2310{
2311 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2312 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2313 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 2314
f45f3da7 2315 intel_disable_ddi_buf(encoder);
62b69566 2316
f45f3da7
VS		 2317 dig_port->set_infoframes(&encoder->base, false,
2318 old_crtc_state, old_conn_state);
b2ccb822 2319
f45f3da7 2320 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
b2ccb822 2321
f45f3da7
VS		 2322 intel_ddi_clk_disable(encoder);
2323
2324 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2325}
2326
2327static void intel_ddi_post_disable(struct intel_encoder *encoder,
2328 const struct intel_crtc_state *old_crtc_state,
2329 const struct drm_connector_state *old_conn_state)
2330{
2331 /*
2332 * old_crtc_state and old_conn_state are NULL when called from
2333 * DP_MST. The main connector associated with this port is never
2334 * bound to a crtc for MST.
2335 */
2336 if (old_crtc_state &&
2337 intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2338 intel_ddi_post_disable_hdmi(encoder,
2339 old_crtc_state, old_conn_state);
2340 else
2341 intel_ddi_post_disable_dp(encoder,
2342 old_crtc_state, old_conn_state);
6441ab5f
PZ		 2343}
2344
1524e93e 2345void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2346 const struct intel_crtc_state *old_crtc_state,
2347 const struct drm_connector_state *old_conn_state)
b7076546 2348{
1524e93e 2349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2350 uint32_t val;
2351
2352 /*
2353 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2354 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2355 * step 13 is the correct place for it. Step 18 is where it was
2356 * originally before the BUN.
2357 */
2358 val = I915_READ(FDI_RX_CTL(PIPE_A));
2359 val &= ~FDI_RX_ENABLE;
2360 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2361
fb0bd3bd
VS		 2362 intel_disable_ddi_buf(encoder);
2363 intel_ddi_clk_disable(encoder);
b7076546
ML		 2364
2365 val = I915_READ(FDI_RX_MISC(PIPE_A));
2366 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2367 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2368 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2369
2370 val = I915_READ(FDI_RX_CTL(PIPE_A));
2371 val &= ~FDI_PCDCLK;
2372 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2373
2374 val = I915_READ(FDI_RX_CTL(PIPE_A));
2375 val &= ~FDI_RX_PLL_ENABLE;
2376 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2377}
2378
15d05f0e
VS		 2379static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2380 const struct intel_crtc_state *crtc_state,
2381 const struct drm_connector_state *conn_state)
72662e10 2382{
15d05f0e
VS		 2383 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2384 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2385 enum port port = intel_ddi_get_encoder_port(encoder);
72662e10 2386
15d05f0e
VS		 2387 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2388 intel_dp_stop_link_train(intel_dp);
d6c50ff8 2389
15d05f0e
VS		 2390 intel_edp_backlight_on(crtc_state, conn_state);
2391 intel_psr_enable(intel_dp, crtc_state);
2392 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 2393
15d05f0e
VS		 2394 if (crtc_state->has_audio)
2395 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2396}
2397
2398static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2399 const struct intel_crtc_state *crtc_state,
2400 const struct drm_connector_state *conn_state)
2401{
2402 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2403 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2404 enum port port = intel_ddi_get_encoder_port(encoder);
2405
2406 intel_hdmi_handle_sink_scrambling(encoder,
2407 conn_state->connector,
2408 crtc_state->hdmi_high_tmds_clock_ratio,
2409 crtc_state->hdmi_scrambling);
2410
2411 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2412 * are ignored so nothing special needs to be done besides
2413 * enabling the port.
2414 */
2415 I915_WRITE(DDI_BUF_CTL(port),
2416 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 2417
15d05f0e
VS		 2418 if (crtc_state->has_audio)
2419 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2420}
2421
2422static void intel_enable_ddi(struct intel_encoder *encoder,
2423 const struct intel_crtc_state *crtc_state,
2424 const struct drm_connector_state *conn_state)
2425{
2426 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2427 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2428 else
2429 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
5ab432ef
DV		 2430}
2431
33f083f0
VS		 2432static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2433 const struct intel_crtc_state *old_crtc_state,
2434 const struct drm_connector_state *old_conn_state)
5ab432ef 2435{
33f083f0 2436 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 2437
37255d8d 2438 if (old_crtc_state->has_audio)
33f083f0 2439 intel_audio_codec_disable(encoder);
2831d842 2440
33f083f0
VS		 2441 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2442 intel_psr_disable(intel_dp, old_crtc_state);
2443 intel_edp_backlight_off(old_conn_state);
2444}
15953637 2445
33f083f0
VS		 2446static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2447 const struct intel_crtc_state *old_crtc_state,
2448 const struct drm_connector_state *old_conn_state)
2449{
2450 if (old_crtc_state->has_audio)
2451 intel_audio_codec_disable(encoder);
d6c50ff8 2452
33f083f0
VS		 2453 intel_hdmi_handle_sink_scrambling(encoder,
2454 old_conn_state->connector,
2455 false, false);
2456}
2457
2458static void intel_disable_ddi(struct intel_encoder *encoder,
2459 const struct intel_crtc_state *old_crtc_state,
2460 const struct drm_connector_state *old_conn_state)
2461{
2462 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2463 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2464 else
2465 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 2466}
79f689aa 2467
fd6bbda9 2468static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2469 const struct intel_crtc_state *pipe_config,
2470 const struct drm_connector_state *conn_state)
95a7a2ae 2471{
3dc38eea 2472 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2473
47a6bc61 2474 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2475}
2476
ad64217b 2477void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2478{
ad64217b
ACO		 2479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480 struct drm_i915_private *dev_priv =
2481 to_i915(intel_dig_port->base.base.dev);
174edf1f 2482 enum port port = intel_dig_port->port;
c19b0669 2483 uint32_t val;
f3e227df 2484 bool wait = false;
c19b0669
PZ		 2485
2486 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2487 val = I915_READ(DDI_BUF_CTL(port));
2488 if (val & DDI_BUF_CTL_ENABLE) {
2489 val &= ~DDI_BUF_CTL_ENABLE;
2490 I915_WRITE(DDI_BUF_CTL(port), val);
2491 wait = true;
2492 }
2493
2494 val = I915_READ(DP_TP_CTL(port));
2495 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2496 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2497 I915_WRITE(DP_TP_CTL(port), val);
2498 POSTING_READ(DP_TP_CTL(port));
2499
2500 if (wait)
2501 intel_wait_ddi_buf_idle(dev_priv, port);
2502 }
2503
0e32b39c 2504 val = DP_TP_CTL_ENABLE |
c19b0669 2505 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2506 if (intel_dp->link_mst)
0e32b39c
DA		 2507 val |= DP_TP_CTL_MODE_MST;
2508 else {
2509 val |= DP_TP_CTL_MODE_SST;
2510 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2511 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2512 }
c19b0669
PZ		 2513 I915_WRITE(DP_TP_CTL(port), val);
2514 POSTING_READ(DP_TP_CTL(port));
2515
2516 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2517 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2518 POSTING_READ(DDI_BUF_CTL(port));
2519
2520 udelay(600);
2521}
00c09d70 2522
9935f7fa
LY		 2523bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2524 struct intel_crtc *intel_crtc)
2525{
2526 u32 temp;
2527
2528 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2529 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2530 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2531 return true;
2532 }
2533 return false;
2534}
2535
6801c18c 2536void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2537 struct intel_crtc_state *pipe_config)
045ac3b5 2538{
fac5e23e 2539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2540 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2541 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 2542 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 2543 u32 temp, flags = 0;
2544
4d1de975
JN		 2545 /* XXX: DSI transcoder paranoia */
2546 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2547 return;
2548
045ac3b5
JB		 2549 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2550 if (temp & TRANS_DDI_PHSYNC)
2551 flags |= DRM_MODE_FLAG_PHSYNC;
2552 else
2553 flags |= DRM_MODE_FLAG_NHSYNC;
2554 if (temp & TRANS_DDI_PVSYNC)
2555 flags |= DRM_MODE_FLAG_PVSYNC;
2556 else
2557 flags |= DRM_MODE_FLAG_NVSYNC;
2558
2d112de7 2559 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2560
2561 switch (temp & TRANS_DDI_BPC_MASK) {
2562 case TRANS_DDI_BPC_6:
2563 pipe_config->pipe_bpp = 18;
2564 break;
2565 case TRANS_DDI_BPC_8:
2566 pipe_config->pipe_bpp = 24;
2567 break;
2568 case TRANS_DDI_BPC_10:
2569 pipe_config->pipe_bpp = 30;
2570 break;
2571 case TRANS_DDI_BPC_12:
2572 pipe_config->pipe_bpp = 36;
2573 break;
2574 default:
2575 break;
2576 }
eb14cb74
VS		 2577
2578 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2579 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2580 pipe_config->has_hdmi_sink = true;
f99be1b3 2581 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 2582
f99be1b3 2583 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2584 pipe_config->has_infoframe = true;
15953637
SS		 2585
2586 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2587 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2588 pipe_config->hdmi_scrambling = true;
2589 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2590 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2591 /* fall through */
eb14cb74 2592 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2593 pipe_config->lane_count = 4;
2594 break;
eb14cb74
VS		 2595 case TRANS_DDI_MODE_SELECT_FDI:
2596 break;
2597 case TRANS_DDI_MODE_SELECT_DP_SST:
2598 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2599 pipe_config->lane_count =
2600 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2601 intel_dp_get_m_n(intel_crtc, pipe_config);
2602 break;
2603 default:
2604 break;
2605 }
10214420 2606
9935f7fa
LY		 2607 pipe_config->has_audio =
2608 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2609
6aa23e65
JN		 2610 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2611 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2612 /*
2613 * This is a big fat ugly hack.
2614 *
2615 * Some machines in UEFI boot mode provide us a VBT that has 18
2616 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2617 * unknown we fail to light up. Yet the same BIOS boots up with
2618 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2619 * max, not what it tells us to use.
2620 *
2621 * Note: This will still be broken if the eDP panel is not lit
2622 * up by the BIOS, and thus we can't get the mode at module
2623 * load.
2624 */
2625 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2626 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2627 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2628 }
11578553 2629
22606a18 2630 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2631
cc3f90f0 2632 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2633 pipe_config->lane_lat_optim_mask =
2634 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2635}
2636
5bfe2ac0 2637static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2638 struct intel_crtc_state *pipe_config,
2639 struct drm_connector_state *conn_state)
00c09d70 2640{
fac5e23e 2641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2642 int type = encoder->type;
eccb140b 2643 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2644 int ret;
00c09d70 2645
5bfe2ac0 2646 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2647
eccb140b
DV		 2648 if (port == PORT_A)
2649 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2650
00c09d70 2651 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2652 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2653 else
0a478c27 2654 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2655
cc3f90f0 2656 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2657 pipe_config->lane_lat_optim_mask =
2658 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2659 pipe_config->lane_count);
95a7a2ae
ID		 2660
2661 return ret;
2662
00c09d70
PZ		 2663}
2664
2665static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2666 .reset = intel_dp_encoder_reset,
2667 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2668};
2669
4a28ae58
PZ		 2670static struct intel_connector *
2671intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2672{
2673 struct intel_connector *connector;
2674 enum port port = intel_dig_port->port;
2675
9bdbd0b9 2676 connector = intel_connector_alloc();
4a28ae58
PZ		 2677 if (!connector)
2678 return NULL;
2679
2680 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2681 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2682 kfree(connector);
2683 return NULL;
2684 }
2685
2686 return connector;
2687}
2688
2689static struct intel_connector *
2690intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2691{
2692 struct intel_connector *connector;
2693 enum port port = intel_dig_port->port;
2694
9bdbd0b9 2695 connector = intel_connector_alloc();
4a28ae58
PZ		 2696 if (!connector)
2697 return NULL;
2698
2699 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2700 intel_hdmi_init_connector(intel_dig_port, connector);
2701
2702 return connector;
2703}
2704
c39055b0 2705void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2706{
2707 struct intel_digital_port *intel_dig_port;
2708 struct intel_encoder *intel_encoder;
2709 struct drm_encoder *encoder;
ff662124 2710 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2711 int max_lanes;
2712
2713 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2714 switch (port) {
2715 case PORT_A:
2716 max_lanes = 4;
2717 break;
2718 case PORT_E:
2719 max_lanes = 0;
2720 break;
2721 default:
2722 max_lanes = 4;
2723 break;
2724 }
2725 } else {
2726 switch (port) {
2727 case PORT_A:
2728 max_lanes = 2;
2729 break;
2730 case PORT_E:
2731 max_lanes = 2;
2732 break;
2733 default:
2734 max_lanes = 4;
2735 break;
2736 }
2737 }
311a2094
PZ		 2738
2739 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2740 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2741 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2742
2743 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2744 /*
2745 * Lspcon device needs to be driven with DP connector
2746 * with special detection sequence. So make sure DP
2747 * is initialized before lspcon.
2748 */
2749 init_dp = true;
2750 init_lspcon = true;
2751 init_hdmi = false;
2752 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2753 }
2754
311a2094 2755 if (!init_dp && !init_hdmi) {
500ea70d 2756 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2757 port_name(port));
500ea70d 2758 return;
311a2094 2759 }
00c09d70 2760
b14c5679 2761 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2762 if (!intel_dig_port)
2763 return;
2764
00c09d70
PZ		 2765 intel_encoder = &intel_dig_port->base;
2766 encoder = &intel_encoder->base;
2767
c39055b0 2768 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2769 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2770
5bfe2ac0 2771 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2772 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2773 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2774 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2775 intel_encoder->pre_enable = intel_ddi_pre_enable;
2776 intel_encoder->disable = intel_disable_ddi;
2777 intel_encoder->post_disable = intel_ddi_post_disable;
2778 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2779 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2780 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2781 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2782
2783 intel_dig_port->port = port;
bcf53de4
SM		 2784 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2785 (DDI_BUF_PORT_REVERSAL |
2786 DDI_A_4_LANES);
00c09d70 2787
62b69566
ACO		 2788 switch (port) {
2789 case PORT_A:
2790 intel_dig_port->ddi_io_power_domain =
2791 POWER_DOMAIN_PORT_DDI_A_IO;
2792 break;
2793 case PORT_B:
2794 intel_dig_port->ddi_io_power_domain =
2795 POWER_DOMAIN_PORT_DDI_B_IO;
2796 break;
2797 case PORT_C:
2798 intel_dig_port->ddi_io_power_domain =
2799 POWER_DOMAIN_PORT_DDI_C_IO;
2800 break;
2801 case PORT_D:
2802 intel_dig_port->ddi_io_power_domain =
2803 POWER_DOMAIN_PORT_DDI_D_IO;
2804 break;
2805 case PORT_E:
2806 intel_dig_port->ddi_io_power_domain =
2807 POWER_DOMAIN_PORT_DDI_E_IO;
2808 break;
2809 default:
2810 MISSING_CASE(port);
2811 }
2812
6c566dc9
MR		 2813 /*
2814 * Bspec says that DDI_A_4_LANES is the only supported configuration
2815 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2816 * wasn't lit up at boot. Force this bit on in our internal
2817 * configuration so that we use the proper lane count for our
2818 * calculations.
2819 */
cc3f90f0 2820 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2821 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2822 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2823 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2824 max_lanes = 4;
6c566dc9
MR		 2825 }
2826 }
2827
ed8d60f4
MR		 2828 intel_dig_port->max_lanes = max_lanes;
2829
00c09d70 2830 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2831 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2832 intel_encoder->port = port;
f68d697e 2833 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2834 intel_encoder->cloneable = 0;
00c09d70 2835
385e4de0
VS		 2836 intel_infoframe_init(intel_dig_port);
2837
f68d697e
CW		 2838 if (init_dp) {
2839 if (!intel_ddi_init_dp_connector(intel_dig_port))
2840 goto err;
13cf5504 2841
f68d697e 2842 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2843 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2844 }
21a8e6a4 2845
311a2094
PZ		 2846 /* In theory we don't need the encoder->type check, but leave it just in
2847 * case we have some really bad VBTs... */
f68d697e
CW		 2848 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2849 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2850 goto err;
21a8e6a4 2851 }
f68d697e 2852
ff662124
SS		 2853 if (init_lspcon) {
2854 if (lspcon_init(intel_dig_port))
2855 /* TODO: handle hdmi info frame part */
2856 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2857 port_name(port));
2858 else
2859 /*
2860 * LSPCON init faied, but DP init was success, so
2861 * lets try to drive as DP++ port.
2862 */
2863 DRM_ERROR("LSPCON init failed on port %c\n",
2864 port_name(port));
2865 }
2866
f68d697e
CW		 2867 return;
2868
2869err:
2870 drm_encoder_cleanup(encoder);
2871 kfree(intel_dig_port);
00c09d70 2872}
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