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drm/i915: extract intel_fifo_underrun.h from intel_drv.h
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
ec7f29ff 32#include "intel_connector.h"
fdc24cf3 33#include "intel_ddi.h"
27fec1f9 34#include "intel_dp.h"
45244b87 35#include "intel_drv.h"
1dd07e56 36#include "intel_dsi.h"
8834e365 37#include "intel_fifo_underrun.h"
408bd917 38#include "intel_hdcp.h"
0550691d 39#include "intel_hdmi.h"
f3e18947 40#include "intel_lspcon.h"
44c1220a 41#include "intel_panel.h"
55367a27 42#include "intel_psr.h"
45244b87 43
10122051
JN		 44struct ddi_buf_trans {
45 u32 trans1; /* balance leg enable, de-emph level */
46 u32 trans2; /* vref sel, vswing */
f8896f5d 47 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 48};
49
97eeb872
VS		 50static const u8 index_to_dp_signal_levels[] = {
51 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
52 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
53 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
54 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
55 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
56 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
57 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
58 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
59 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
60 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
61};
62
45244b87
ED		 63/* HDMI/DVI modes ignore everything but the last 2 items. So we share
64 * them for both DP and FDI transports, allowing those ports to
65 * automatically adapt to HDMI connections as well
66 */
10122051 67static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 68 { 0x00FFFFFF, 0x0006000E, 0x0 },
69 { 0x00D75FFF, 0x0005000A, 0x0 },
70 { 0x00C30FFF, 0x00040006, 0x0 },
71 { 0x80AAAFFF, 0x000B0000, 0x0 },
72 { 0x00FFFFFF, 0x0005000A, 0x0 },
73 { 0x00D75FFF, 0x000C0004, 0x0 },
74 { 0x80C30FFF, 0x000B0000, 0x0 },
75 { 0x00FFFFFF, 0x00040006, 0x0 },
76 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 77};
78
10122051 79static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0007000E, 0x0 },
81 { 0x00D75FFF, 0x000F000A, 0x0 },
82 { 0x00C30FFF, 0x00060006, 0x0 },
83 { 0x00AAAFFF, 0x001E0000, 0x0 },
84 { 0x00FFFFFF, 0x000F000A, 0x0 },
85 { 0x00D75FFF, 0x00160004, 0x0 },
86 { 0x00C30FFF, 0x001E0000, 0x0 },
87 { 0x00FFFFFF, 0x00060006, 0x0 },
88 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 89};
90
10122051
JN		 91static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
92 /* Idx NT mV d T mV d db */
f8896f5d
DW		 93 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
94 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
95 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
96 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
97 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
98 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
99 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
100 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
101 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
102 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
103 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
104 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 105};
106
10122051 107static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 108 { 0x00FFFFFF, 0x00000012, 0x0 },
109 { 0x00EBAFFF, 0x00020011, 0x0 },
110 { 0x00C71FFF, 0x0006000F, 0x0 },
111 { 0x00AAAFFF, 0x000E000A, 0x0 },
112 { 0x00FFFFFF, 0x00020011, 0x0 },
113 { 0x00DB6FFF, 0x0005000F, 0x0 },
114 { 0x00BEEFFF, 0x000A000C, 0x0 },
115 { 0x00FFFFFF, 0x0005000F, 0x0 },
116 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 117};
118
10122051 119static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 120 { 0x00FFFFFF, 0x0007000E, 0x0 },
121 { 0x00D75FFF, 0x000E000A, 0x0 },
122 { 0x00BEFFFF, 0x00140006, 0x0 },
123 { 0x80B2CFFF, 0x001B0002, 0x0 },
124 { 0x00FFFFFF, 0x000E000A, 0x0 },
125 { 0x00DB6FFF, 0x00160005, 0x0 },
126 { 0x80C71FFF, 0x001A0002, 0x0 },
127 { 0x00F7DFFF, 0x00180004, 0x0 },
128 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 129};
130
10122051 131static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0001000E, 0x0 },
133 { 0x00D75FFF, 0x0004000A, 0x0 },
134 { 0x00C30FFF, 0x00070006, 0x0 },
135 { 0x00AAAFFF, 0x000C0000, 0x0 },
136 { 0x00FFFFFF, 0x0004000A, 0x0 },
137 { 0x00D75FFF, 0x00090004, 0x0 },
138 { 0x00C30FFF, 0x000C0000, 0x0 },
139 { 0x00FFFFFF, 0x00070006, 0x0 },
140 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 141};
142
10122051
JN		 143static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
144 /* Idx NT mV d T mV df db */
f8896f5d
DW		 145 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
146 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
147 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
148 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
149 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
150 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
151 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
152 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
153 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
154 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 155};
156
5f8b2531 157/* Skylake H and S */
7f88e3af 158static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00002016, 0x000000A0, 0x0 },
160 { 0x00005012, 0x0000009B, 0x0 },
161 { 0x00007011, 0x00000088, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 163 { 0x00002016, 0x0000009B, 0x0 },
164 { 0x00005012, 0x00000088, 0x0 },
d7097cff 165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 168};
169
f8896f5d
DW		 170/* Skylake U */
171static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 172 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 176 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x1 },
178 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 179 { 0x00002016, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 181};
182
5f8b2531
RV		 183/* Skylake Y */
184static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 185 { 0x00000018, 0x000000A2, 0x0 },
186 { 0x00005012, 0x00000088, 0x0 },
5ac90567 187 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 188 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 189 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 190 { 0x80005012, 0x000000C0, 0x3 },
191 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 192 { 0x00000018, 0x00000088, 0x0 },
d7097cff 193 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 194};
195
0fdd4918
RV		 196/* Kabylake H and S */
197static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
198 { 0x00002016, 0x000000A0, 0x0 },
199 { 0x00005012, 0x0000009B, 0x0 },
200 { 0x00007011, 0x00000088, 0x0 },
201 { 0x80009010, 0x000000C0, 0x1 },
202 { 0x00002016, 0x0000009B, 0x0 },
203 { 0x00005012, 0x00000088, 0x0 },
204 { 0x80007011, 0x000000C0, 0x1 },
205 { 0x00002016, 0x00000097, 0x0 },
206 { 0x80005012, 0x000000C0, 0x1 },
207};
208
209/* Kabylake U */
210static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
211 { 0x0000201B, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x80009010, 0x000000C0, 0x3 },
215 { 0x0000201B, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00002016, 0x0000004F, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
222/* Kabylake Y */
223static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
224 { 0x00001017, 0x000000A1, 0x0 },
225 { 0x00005012, 0x00000088, 0x0 },
226 { 0x80007011, 0x000000CD, 0x3 },
227 { 0x8000800F, 0x000000C0, 0x3 },
228 { 0x00001017, 0x0000009D, 0x0 },
229 { 0x80005012, 0x000000C0, 0x3 },
230 { 0x80007011, 0x000000C0, 0x3 },
231 { 0x00001017, 0x0000004C, 0x0 },
232 { 0x80005012, 0x000000C0, 0x3 },
233};
234
f8896f5d 235/*
0fdd4918 236 * Skylake/Kabylake H and S
f8896f5d
DW		 237 * eDP 1.4 low vswing translation parameters
238 */
7ad14a29 239static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 240 { 0x00000018, 0x000000A8, 0x0 },
241 { 0x00004013, 0x000000A9, 0x0 },
242 { 0x00007011, 0x000000A2, 0x0 },
243 { 0x00009010, 0x0000009C, 0x0 },
244 { 0x00000018, 0x000000A9, 0x0 },
245 { 0x00006013, 0x000000A2, 0x0 },
246 { 0x00007011, 0x000000A6, 0x0 },
247 { 0x00000018, 0x000000AB, 0x0 },
248 { 0x00007013, 0x0000009F, 0x0 },
249 { 0x00000018, 0x000000DF, 0x0 },
250};
251
252/*
0fdd4918 253 * Skylake/Kabylake U
f8896f5d
DW		 254 * eDP 1.4 low vswing translation parameters
255 */
256static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
257 { 0x00000018, 0x000000A8, 0x0 },
258 { 0x00004013, 0x000000A9, 0x0 },
259 { 0x00007011, 0x000000A2, 0x0 },
260 { 0x00009010, 0x0000009C, 0x0 },
261 { 0x00000018, 0x000000A9, 0x0 },
262 { 0x00006013, 0x000000A2, 0x0 },
263 { 0x00007011, 0x000000A6, 0x0 },
264 { 0x00002016, 0x000000AB, 0x0 },
265 { 0x00005013, 0x0000009F, 0x0 },
266 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 267};
268
f8896f5d 269/*
0fdd4918 270 * Skylake/Kabylake Y
f8896f5d
DW		 271 * eDP 1.4 low vswing translation parameters
272 */
5f8b2531 273static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 274 { 0x00000018, 0x000000A8, 0x0 },
275 { 0x00004013, 0x000000AB, 0x0 },
276 { 0x00007011, 0x000000A4, 0x0 },
277 { 0x00009010, 0x000000DF, 0x0 },
278 { 0x00000018, 0x000000AA, 0x0 },
279 { 0x00006013, 0x000000A4, 0x0 },
280 { 0x00007011, 0x0000009D, 0x0 },
281 { 0x00000018, 0x000000A0, 0x0 },
282 { 0x00006012, 0x000000DF, 0x0 },
283 { 0x00000018, 0x0000008A, 0x0 },
284};
7ad14a29 285
0fdd4918 286/* Skylake/Kabylake U, H and S */
7f88e3af 287static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 288 { 0x00000018, 0x000000AC, 0x0 },
289 { 0x00005012, 0x0000009D, 0x0 },
290 { 0x00007011, 0x00000088, 0x0 },
291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00000018, 0x00000098, 0x0 },
293 { 0x00004013, 0x00000088, 0x0 },
2e78416e 294 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 295 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 296 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
297 { 0x80003015, 0x000000C0, 0x1 },
298 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 299};
300
0fdd4918 301/* Skylake/Kabylake Y */
5f8b2531 302static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 303 { 0x00000018, 0x000000A1, 0x0 },
304 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 305 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 306 { 0x00000018, 0x000000A4, 0x0 },
307 { 0x00000018, 0x0000009D, 0x0 },
308 { 0x00004013, 0x00000080, 0x0 },
2e78416e 309 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 310 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 311 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
312 { 0x80003015, 0x000000C0, 0x3 },
313 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 314};
315
96fb9f9b 316struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 317 u8 margin; /* swing value */
318 u8 scale; /* scale value */
319 u8 enable; /* scale enable */
320 u8 deemphasis;
96fb9f9b
VK		 321};
322
96fb9f9b
VK		 323static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
324 /* Idx NT mV diff db */
043eaf36
VS		 325 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
326 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
327 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
328 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
329 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
330 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
331 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
332 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
333 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
334 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 335};
336
d9d7000d
SJ		 337static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
338 /* Idx NT mV diff db */
043eaf36
VS		 339 { 26, 0, 0, 128, }, /* 0: 200 0 */
340 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
341 { 48, 0, 0, 96, }, /* 2: 200 4 */
342 { 54, 0, 0, 69, }, /* 3: 200 6 */
343 { 32, 0, 0, 128, }, /* 4: 250 0 */
344 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
345 { 54, 0, 0, 85, }, /* 6: 250 4 */
346 { 43, 0, 0, 128, }, /* 7: 300 0 */
347 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
348 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 349};
350
96fb9f9b
VK		 351/* BSpec has 2 recommended values - entries 0 and 8.
352 * Using the entry with higher vswing.
353 */
354static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
355 /* Idx NT mV diff db */
043eaf36
VS		 356 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
357 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
358 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
359 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
360 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
361 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
362 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
363 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
364 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
365 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 366};
367
83fb7ab4 368struct cnl_ddi_buf_trans {
fb5f4e96
VS		 369 u8 dw2_swing_sel;
370 u8 dw7_n_scalar;
371 u8 dw4_cursor_coeff;
372 u8 dw4_post_cursor_2;
373 u8 dw4_post_cursor_1;
83fb7ab4
RV		 374};
375
376/* Voltage Swing Programming for VccIO 0.85V for DP */
377static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
378 /* NT mV Trans mV db */
379 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
380 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
381 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
382 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
383 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
384 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
385 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
386 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
387 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
388 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for HDMI */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
395 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
396 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
397 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
398 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
399 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
400 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
401};
402
403/* Voltage Swing Programming for VccIO 0.85V for eDP */
404static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
405 /* NT mV Trans mV db */
406 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
407 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
408 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
409 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
410 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
411 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
412 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
413 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
414 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
415};
416
417/* Voltage Swing Programming for VccIO 0.95V for DP */
418static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
419 /* NT mV Trans mV db */
420 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
421 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
422 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
423 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
424 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
425 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
426 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
427 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
428 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
429 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
430};
431
432/* Voltage Swing Programming for VccIO 0.95V for HDMI */
433static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
434 /* NT mV Trans mV db */
435 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
436 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
437 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
438 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
439 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
440 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
441 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
442 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
443 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
444 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
445 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
446};
447
448/* Voltage Swing Programming for VccIO 0.95V for eDP */
449static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
450 /* NT mV Trans mV db */
451 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
452 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
453 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
454 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
455 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
456 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
457 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
458 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
459 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
460 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
461};
462
463/* Voltage Swing Programming for VccIO 1.05V for DP */
464static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
465 /* NT mV Trans mV db */
466 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
467 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
468 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
469 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
470 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
471 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
472 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
473 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
474 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
475 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
476};
477
478/* Voltage Swing Programming for VccIO 1.05V for HDMI */
479static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
480 /* NT mV Trans mV db */
481 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
482 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
483 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
484 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
485 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
486 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
487 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
488 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
489 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
490 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
491 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
492};
493
494/* Voltage Swing Programming for VccIO 1.05V for eDP */
495static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
496 /* NT mV Trans mV db */
497 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
498 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
499 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
500 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
501 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
502 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
503 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
504 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
505 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
506};
507
b265a2a6
CT		 508/* icl_combo_phy_ddi_translations */
509static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
510 /* NT mV Trans mV db */
511 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
512 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
513 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
514 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
515 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
516 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
517 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
518 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
519 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
520 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 521};
522
b265a2a6
CT		 523static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
524 /* NT mV Trans mV db */
525 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
526 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
527 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
528 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
529 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
530 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
531 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
532 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
533 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
534 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 535};
536
b265a2a6
CT		 537static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
538 /* NT mV Trans mV db */
539 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
540 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
541 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
542 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
543 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
544 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
545 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
546 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
547 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
548 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 549};
550
b265a2a6
CT		 551static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
552 /* NT mV Trans mV db */
553 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
554 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
555 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
556 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
557 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
558 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
559 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 560};
561
cd96bea7
MN		 562struct icl_mg_phy_ddi_buf_trans {
563 u32 cri_txdeemph_override_5_0;
564 u32 cri_txdeemph_override_11_6;
565 u32 cri_txdeemph_override_17_12;
566};
567
568static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
569 /* Voltage swing pre-emphasis */
570 { 0x0, 0x1B, 0x00 }, /* 0 0 */
571 { 0x0, 0x23, 0x08 }, /* 0 1 */
572 { 0x0, 0x2D, 0x12 }, /* 0 2 */
573 { 0x0, 0x00, 0x00 }, /* 0 3 */
574 { 0x0, 0x23, 0x00 }, /* 1 0 */
575 { 0x0, 0x2B, 0x09 }, /* 1 1 */
576 { 0x0, 0x2E, 0x11 }, /* 1 2 */
577 { 0x0, 0x2F, 0x00 }, /* 2 0 */
578 { 0x0, 0x33, 0x0C }, /* 2 1 */
579 { 0x0, 0x00, 0x00 }, /* 3 0 */
580};
581
a930acd9
VS		 582static const struct ddi_buf_trans *
583bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
584{
585 if (dev_priv->vbt.edp.low_vswing) {
586 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
587 return bdw_ddi_translations_edp;
588 } else {
589 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
590 return bdw_ddi_translations_dp;
591 }
592}
593
acee2998 594static const struct ddi_buf_trans *
78ab0bae 595skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 596{
0fdd4918 597 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 598 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 599 return skl_y_ddi_translations_dp;
0fdd4918 600 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 601 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 602 return skl_u_ddi_translations_dp;
f8896f5d 603 } else {
f8896f5d 604 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 605 return skl_ddi_translations_dp;
f8896f5d 606 }
f8896f5d
DW		 607}
608
0fdd4918
RV		 609static const struct ddi_buf_trans *
610kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
611{
dfdaa566 612 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
0fdd4918
RV		 613 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
614 return kbl_y_ddi_translations_dp;
da411a48 615 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 616 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
617 return kbl_u_ddi_translations_dp;
618 } else {
619 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
620 return kbl_ddi_translations_dp;
621 }
622}
623
acee2998 624static const struct ddi_buf_trans *
78ab0bae 625skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 626{
06411f08 627 if (dev_priv->vbt.edp.low_vswing) {
dfdaa566 628 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 629 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 630 return skl_y_ddi_translations_edp;
da411a48
RV		 631 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
632 IS_CFL_ULT(dev_priv)) {
f8896f5d 633 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 634 return skl_u_ddi_translations_edp;
f8896f5d 635 } else {
f8896f5d 636 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 637 return skl_ddi_translations_edp;
f8896f5d
DW		 638 }
639 }
cd1101cb 640
da411a48 641 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 642 return kbl_get_buf_trans_dp(dev_priv, n_entries);
643 else
644 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 645}
646
647static const struct ddi_buf_trans *
78ab0bae 648skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 649{
dfdaa566 650 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 651 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 652 return skl_y_ddi_translations_hdmi;
f8896f5d 653 } else {
f8896f5d 654 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 655 return skl_ddi_translations_hdmi;
f8896f5d 656 }
f8896f5d
DW		 657}
658
edba48fd
VS		 659static int skl_buf_trans_num_entries(enum port port, int n_entries)
660{
661 /* Only DDIA and DDIE can select the 10th register with DP */
662 if (port == PORT_A || port == PORT_E)
663 return min(n_entries, 10);
664 else
665 return min(n_entries, 9);
666}
667
d8fe2c7f
VS		 668static const struct ddi_buf_trans *
669intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 670 enum port port, int *n_entries)
d8fe2c7f
VS		 671{
672 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 673 const struct ddi_buf_trans *ddi_translations =
674 kbl_get_buf_trans_dp(dev_priv, n_entries);
675 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
676 return ddi_translations;
d8fe2c7f 677 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 678 const struct ddi_buf_trans *ddi_translations =
679 skl_get_buf_trans_dp(dev_priv, n_entries);
680 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
681 return ddi_translations;
d8fe2c7f
VS		 682 } else if (IS_BROADWELL(dev_priv)) {
683 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
684 return bdw_ddi_translations_dp;
685 } else if (IS_HASWELL(dev_priv)) {
686 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
687 return hsw_ddi_translations_dp;
688 }
689
690 *n_entries = 0;
691 return NULL;
692}
693
694static const struct ddi_buf_trans *
695intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 696 enum port port, int *n_entries)
d8fe2c7f
VS		 697{
698 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 699 const struct ddi_buf_trans *ddi_translations =
700 skl_get_buf_trans_edp(dev_priv, n_entries);
701 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
702 return ddi_translations;
d8fe2c7f
VS		 703 } else if (IS_BROADWELL(dev_priv)) {
704 return bdw_get_buf_trans_edp(dev_priv, n_entries);
705 } else if (IS_HASWELL(dev_priv)) {
706 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
707 return hsw_ddi_translations_dp;
708 }
709
710 *n_entries = 0;
711 return NULL;
712}
713
714static const struct ddi_buf_trans *
715intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
716 int *n_entries)
717{
718 if (IS_BROADWELL(dev_priv)) {
719 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
720 return bdw_ddi_translations_fdi;
721 } else if (IS_HASWELL(dev_priv)) {
722 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
723 return hsw_ddi_translations_fdi;
724 }
725
726 *n_entries = 0;
727 return NULL;
728}
729
975786ee
VS		 730static const struct ddi_buf_trans *
731intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
732 int *n_entries)
733{
734 if (IS_GEN9_BC(dev_priv)) {
735 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
736 } else if (IS_BROADWELL(dev_priv)) {
737 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
738 return bdw_ddi_translations_hdmi;
739 } else if (IS_HASWELL(dev_priv)) {
740 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
741 return hsw_ddi_translations_hdmi;
742 }
743
744 *n_entries = 0;
745 return NULL;
746}
747
7d4f37b5
VS		 748static const struct bxt_ddi_buf_trans *
749bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
750{
751 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
752 return bxt_ddi_translations_dp;
753}
754
755static const struct bxt_ddi_buf_trans *
756bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
757{
758 if (dev_priv->vbt.edp.low_vswing) {
759 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
760 return bxt_ddi_translations_edp;
761 }
762
763 return bxt_get_buf_trans_dp(dev_priv, n_entries);
764}
765
766static const struct bxt_ddi_buf_trans *
767bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
768{
769 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
770 return bxt_ddi_translations_hdmi;
771}
772
cf3e0fb4
RV		 773static const struct cnl_ddi_buf_trans *
774cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
775{
776 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
777
778 if (voltage == VOLTAGE_INFO_0_85V) {
779 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
780 return cnl_ddi_translations_hdmi_0_85V;
781 } else if (voltage == VOLTAGE_INFO_0_95V) {
782 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
783 return cnl_ddi_translations_hdmi_0_95V;
784 } else if (voltage == VOLTAGE_INFO_1_05V) {
785 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
786 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 787 } else {
788 *n_entries = 1; /* shut up gcc */
cf3e0fb4 789 MISSING_CASE(voltage);
83482ca3 790 }
cf3e0fb4
RV		 791 return NULL;
792}
793
794static const struct cnl_ddi_buf_trans *
795cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
796{
797 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
798
799 if (voltage == VOLTAGE_INFO_0_85V) {
800 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
801 return cnl_ddi_translations_dp_0_85V;
802 } else if (voltage == VOLTAGE_INFO_0_95V) {
803 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
804 return cnl_ddi_translations_dp_0_95V;
805 } else if (voltage == VOLTAGE_INFO_1_05V) {
806 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
807 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 808 } else {
809 *n_entries = 1; /* shut up gcc */
cf3e0fb4 810 MISSING_CASE(voltage);
83482ca3 811 }
cf3e0fb4
RV		 812 return NULL;
813}
814
815static const struct cnl_ddi_buf_trans *
816cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
817{
818 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
819
820 if (dev_priv->vbt.edp.low_vswing) {
821 if (voltage == VOLTAGE_INFO_0_85V) {
822 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
823 return cnl_ddi_translations_edp_0_85V;
824 } else if (voltage == VOLTAGE_INFO_0_95V) {
825 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
826 return cnl_ddi_translations_edp_0_95V;
827 } else if (voltage == VOLTAGE_INFO_1_05V) {
828 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
829 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 830 } else {
831 *n_entries = 1; /* shut up gcc */
cf3e0fb4 832 MISSING_CASE(voltage);
83482ca3 833 }
cf3e0fb4
RV		 834 return NULL;
835 } else {
836 return cnl_get_buf_trans_dp(dev_priv, n_entries);
837 }
838}
839
b265a2a6 840static const struct cnl_ddi_buf_trans *
fb5c8e9d 841icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
b265a2a6 842 int type, int rate, int *n_entries)
fb5c8e9d 843{
b265a2a6
CT		 844 if (type == INTEL_OUTPUT_HDMI) {
845 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
846 return icl_combo_phy_ddi_translations_hdmi;
847 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
848 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
849 return icl_combo_phy_ddi_translations_edp_hbr3;
850 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
851 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
852 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 853 }
b265a2a6
CT		 854
855 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
856 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 857}
858
8d8bb85e
VS		 859static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
860{
d02ace87 861 int n_entries, level, default_entry;
8d8bb85e 862
d02ace87 863 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 864
2dd24a9c 865 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 866 if (intel_port_is_combophy(dev_priv, port))
b265a2a6
CT		 867 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
868 0, &n_entries);
dccc7228
MN		 869 else
870 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
871 default_entry = n_entries - 1;
872 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 873 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
874 default_entry = n_entries - 1;
043eaf36 875 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 876 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
877 default_entry = n_entries - 1;
bf503556 878 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 879 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
880 default_entry = 8;
8d8bb85e 881 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 882 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
883 default_entry = 7;
8d8bb85e 884 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 885 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
886 default_entry = 6;
8d8bb85e
VS		 887 } else {
888 WARN(1, "ddi translation table missing\n");
975786ee 889 return 0;
8d8bb85e
VS		 890 }
891
892 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 893 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
894 level = default_entry;
8d8bb85e 895
d02ace87 896 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 897 return 0;
d02ace87
VS		 898 if (WARN_ON_ONCE(level >= n_entries))
899 level = n_entries - 1;
21b39d2a 900
d02ace87 901 return level;
8d8bb85e
VS		 902}
903
e58623cb
AR		 904/*
905 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 906 * values in advance. This function programs the correct values for
907 * DP/eDP/FDI use cases.
45244b87 908 */
3a6d84e6
VS		 909static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
910 const struct intel_crtc_state *crtc_state)
45244b87 911{
6a7e4f99 912 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 913 u32 iboost_bit = 0;
7d1c42e6 914 int i, n_entries;
0fce04c8 915 enum port port = encoder->port;
10122051 916 const struct ddi_buf_trans *ddi_translations;
e58623cb 917
3a6d84e6
VS		 918 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
919 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
920 &n_entries);
921 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 922 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 923 &n_entries);
3a6d84e6 924 else
edba48fd 925 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 926 &n_entries);
e58623cb 927
edba48fd
VS		 928 /* If we're boosting the current, set bit 31 of trans1 */
929 if (IS_GEN9_BC(dev_priv) &&
930 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
931 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 932
7d1c42e6 933 for (i = 0; i < n_entries; i++) {
9712e688
VS		 934 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
935 ddi_translations[i].trans1 | iboost_bit);
936 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
937 ddi_translations[i].trans2);
45244b87 938 }
32bdc400
VS		 939}
940
941/*
942 * Starting with Haswell, DDI port buffers must be programmed with correct
943 * values in advance. This function programs the correct values for
944 * HDMI/DVI use cases.
945 */
7ea79333 946static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 947 int level)
32bdc400
VS		 948{
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
950 u32 iboost_bit = 0;
d02ace87 951 int n_entries;
0fce04c8 952 enum port port = encoder->port;
d02ace87 953 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 954
d02ace87 955 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 956
d02ace87 957 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 958 return;
d02ace87
VS		 959 if (WARN_ON_ONCE(level >= n_entries))
960 level = n_entries - 1;
21b39d2a 961
975786ee
VS		 962 /* If we're boosting the current, set bit 31 of trans1 */
963 if (IS_GEN9_BC(dev_priv) &&
964 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
965 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 966
6acab15a 967 /* Entry 9 is for HDMI: */
ed9c77d2 968 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 969 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 970 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 971 ddi_translations[level].trans2);
45244b87
ED		 972}
973
248138b5
PZ		 974static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
975 enum port port)
976{
f0f59a00 977 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 978 int i;
979
3449ca85 980 for (i = 0; i < 16; i++) {
248138b5
PZ		 981 udelay(1);
982 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
983 return;
984 }
985 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
986}
c82e4d26 987
3d0c5005 988static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 989{
0823eb9c 990 switch (pll->info->id) {
c856052a
ACO		 991 case DPLL_ID_WRPLL1:
992 return PORT_CLK_SEL_WRPLL1;
993 case DPLL_ID_WRPLL2:
994 return PORT_CLK_SEL_WRPLL2;
995 case DPLL_ID_SPLL:
996 return PORT_CLK_SEL_SPLL;
997 case DPLL_ID_LCPLL_810:
998 return PORT_CLK_SEL_LCPLL_810;
999 case DPLL_ID_LCPLL_1350:
1000 return PORT_CLK_SEL_LCPLL_1350;
1001 case DPLL_ID_LCPLL_2700:
1002 return PORT_CLK_SEL_LCPLL_2700;
1003 default:
0823eb9c 1004 MISSING_CASE(pll->info->id);
c856052a
ACO		 1005 return PORT_CLK_SEL_NONE;
1006 }
1007}
1008
20fd2ab7 1009static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1010 const struct intel_crtc_state *crtc_state)
c27e917e 1011{
0e5fa646
ML		 1012 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1013 int clock = crtc_state->port_clock;
c27e917e
PZ		 1014 const enum intel_dpll_id id = pll->info->id;
1015
1016 switch (id) {
1017 default:
20fd2ab7
LDM		 1018 /*
1019 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1020 * here, so do warn if this get passed in
1021 */
c27e917e 1022 MISSING_CASE(id);
c27e917e 1023 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1024 case DPLL_ID_ICL_TBTPLL:
1025 switch (clock) {
1026 case 162000:
1027 return DDI_CLK_SEL_TBT_162;
1028 case 270000:
1029 return DDI_CLK_SEL_TBT_270;
1030 case 540000:
1031 return DDI_CLK_SEL_TBT_540;
1032 case 810000:
1033 return DDI_CLK_SEL_TBT_810;
1034 default:
1035 MISSING_CASE(clock);
7a61a6de 1036 return DDI_CLK_SEL_NONE;
1fa11ee2 1037 }
c27e917e
PZ		 1038 case DPLL_ID_ICL_MGPLL1:
1039 case DPLL_ID_ICL_MGPLL2:
1040 case DPLL_ID_ICL_MGPLL3:
1041 case DPLL_ID_ICL_MGPLL4:
1042 return DDI_CLK_SEL_MG;
1043 }
1044}
1045
c82e4d26
ED		 1046/* Starting with Haswell, different DDI ports can work in FDI mode for
1047 * connection to the PCH-located connectors. For this, it is necessary to train
1048 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1049 *
1050 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1051 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1052 * DDI A (which is used for eDP)
1053 */
1054
dc4a1094
ACO		 1055void hsw_fdi_link_train(struct intel_crtc *crtc,
1056 const struct intel_crtc_state *crtc_state)
c82e4d26 1057{
4cbe4b2b 1058 struct drm_device *dev = crtc->base.dev;
fac5e23e 1059 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1060 struct intel_encoder *encoder;
c856052a 1061 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1062
4cbe4b2b 1063 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1064 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1065 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1066 }
1067
04945641
PZ		 1068 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1069 * mode set "sequence for CRT port" document:
1070 * - TP1 to TP2 time with the default value
1071 * - FDI delay to 90h
8693a824
DL		 1072 *
1073 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1074 */
eede3b53 1075 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1076 FDI_RX_PWRDN_LANE0_VAL(2) |
1077 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1078
1079 /* Enable the PCH Receiver FDI PLL */
3e68320e 1080 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1081 FDI_RX_PLL_ENABLE |
dc4a1094 1082 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1083 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1084 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1085 udelay(220);
1086
1087 /* Switch from Rawclk to PCDclk */
1088 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1089 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1090
1091 /* Configure Port Clock Select */
dc4a1094 1092 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1093 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1094 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1095
1096 /* Start the training iterating through available voltages and emphasis,
1097 * testing each value twice. */
10122051 1098 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1099 /* Configure DP_TP_CTL with auto-training */
1100 I915_WRITE(DP_TP_CTL(PORT_E),
1101 DP_TP_CTL_FDI_AUTOTRAIN |
1102 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1103 DP_TP_CTL_LINK_TRAIN_PAT1 |
1104 DP_TP_CTL_ENABLE);
1105
876a8cdf
DL		 1106 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1107 * DDI E does not support port reversal, the functionality is
1108 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1109 * port reversal bit */
c82e4d26 1110 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1111 DDI_BUF_CTL_ENABLE |
dc4a1094 1112 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1113 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1114 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1115
1116 udelay(600);
1117
04945641 1118 /* Program PCH FDI Receiver TU */
eede3b53 1119 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1120
1121 /* Enable PCH FDI Receiver with auto-training */
1122 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1123 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1124 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1125
1126 /* Wait for FDI receiver lane calibration */
1127 udelay(30);
1128
1129 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1130 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1131 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1132 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1133 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1134
1135 /* Wait for FDI auto training time */
1136 udelay(5);
c82e4d26
ED		 1137
1138 temp = I915_READ(DP_TP_STATUS(PORT_E));
1139 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1140 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1141 break;
1142 }
c82e4d26 1143
a308ccb3
VS		 1144 /*
1145 * Leave things enabled even if we failed to train FDI.
1146 * Results in less fireworks from the state checker.
1147 */
1148 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1149 DRM_ERROR("FDI link training failed!\n");
1150 break;
c82e4d26 1151 }
04945641 1152
5b421c57
VS		 1153 rx_ctl_val &= ~FDI_RX_ENABLE;
1154 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1155 POSTING_READ(FDI_RX_CTL(PIPE_A));
1156
248138b5
PZ		 1157 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1158 temp &= ~DDI_BUF_CTL_ENABLE;
1159 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1160 POSTING_READ(DDI_BUF_CTL(PORT_E));
1161
04945641 1162 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1163 temp = I915_READ(DP_TP_CTL(PORT_E));
1164 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1165 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1166 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1167 POSTING_READ(DP_TP_CTL(PORT_E));
1168
1169 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1170
04945641 1171 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1172 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1173 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1174 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1175 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1176 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1177 }
1178
a308ccb3
VS		 1179 /* Enable normal pixel sending for FDI */
1180 I915_WRITE(DP_TP_CTL(PORT_E),
1181 DP_TP_CTL_FDI_AUTOTRAIN |
1182 DP_TP_CTL_LINK_TRAIN_NORMAL |
1183 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1184 DP_TP_CTL_ENABLE);
c82e4d26 1185}
0e72a5b5 1186
d7c530b2 1187static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1188{
1189 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1190 struct intel_digital_port *intel_dig_port =
1191 enc_to_dig_port(&encoder->base);
1192
1193 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1194 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1195 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1196}
1197
8d9ddbcb 1198static struct intel_encoder *
e9ce1a62 1199intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1200{
e9ce1a62 1201 struct drm_device *dev = crtc->base.dev;
1524e93e 1202 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1203 int num_encoders = 0;
1204
1524e93e
SS		 1205 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1206 ret = encoder;
8d9ddbcb
PZ		 1207 num_encoders++;
1208 }
1209
1210 if (num_encoders != 1)
84f44ce7 1211 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1212 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1213
1214 BUG_ON(ret == NULL);
1215 return ret;
1216}
1217
1c0b85c5 1218#define LC_FREQ 2700
1c0b85c5 1219
f0f59a00
VS		 1220static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1221 i915_reg_t reg)
11578553
JB		 1222{
1223 int refclk = LC_FREQ;
1224 int n, p, r;
1225 u32 wrpll;
1226
1227 wrpll = I915_READ(reg);
114fe488
DV		 1228 switch (wrpll & WRPLL_PLL_REF_MASK) {
1229 case WRPLL_PLL_SSC:
1230 case WRPLL_PLL_NON_SSC:
11578553
JB		 1231 /*
1232 * We could calculate spread here, but our checking
1233 * code only cares about 5% accuracy, and spread is a max of
1234 * 0.5% downspread.
1235 */
1236 refclk = 135;
1237 break;
114fe488 1238 case WRPLL_PLL_LCPLL:
11578553
JB		 1239 refclk = LC_FREQ;
1240 break;
1241 default:
1242 WARN(1, "bad wrpll refclk\n");
1243 return 0;
1244 }
1245
1246 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1247 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1248 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1249
20f0ec16
JB		 1250 /* Convert to KHz, p & r have a fixed point portion */
1251 return (refclk * n * 100) / (p * r);
11578553
JB		 1252}
1253
947f4417 1254static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1255{
3d0c5005 1256 u32 p0, p1, p2, dco_freq;
540e732c 1257
947f4417
LDM		 1258 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1259 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1260
947f4417
LDM		 1261 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1262 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1263 else
1264 p1 = 1;
1265
1266
1267 switch (p0) {
1268 case DPLL_CFGCR2_PDIV_1:
1269 p0 = 1;
1270 break;
1271 case DPLL_CFGCR2_PDIV_2:
1272 p0 = 2;
1273 break;
1274 case DPLL_CFGCR2_PDIV_3:
1275 p0 = 3;
1276 break;
1277 case DPLL_CFGCR2_PDIV_7:
1278 p0 = 7;
1279 break;
1280 }
1281
1282 switch (p2) {
1283 case DPLL_CFGCR2_KDIV_5:
1284 p2 = 5;
1285 break;
1286 case DPLL_CFGCR2_KDIV_2:
1287 p2 = 2;
1288 break;
1289 case DPLL_CFGCR2_KDIV_3:
1290 p2 = 3;
1291 break;
1292 case DPLL_CFGCR2_KDIV_1:
1293 p2 = 1;
1294 break;
1295 }
1296
947f4417
LDM		 1297 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1298 * 24 * 1000;
540e732c 1299
947f4417
LDM		 1300 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1301 * 24 * 1000) / 0x8000;
540e732c 1302
b8449c43
YX		 1303 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1304 return 0;
1305
540e732c
S		 1306 return dco_freq / (p0 * p1 * p2 * 5);
1307}
1308
8327af28 1309int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1310 struct intel_dpll_hw_state *pll_state)
a9701a89 1311{
3d0c5005 1312 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1313
5e65216d
LDM		 1314 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1315 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1316
5e65216d
LDM		 1317 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1318 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1319 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1320 else
1321 p1 = 1;
1322
1323
1324 switch (p0) {
1325 case DPLL_CFGCR1_PDIV_2:
1326 p0 = 2;
1327 break;
1328 case DPLL_CFGCR1_PDIV_3:
1329 p0 = 3;
1330 break;
1331 case DPLL_CFGCR1_PDIV_5:
1332 p0 = 5;
1333 break;
1334 case DPLL_CFGCR1_PDIV_7:
1335 p0 = 7;
1336 break;
1337 }
1338
1339 switch (p2) {
1340 case DPLL_CFGCR1_KDIV_1:
1341 p2 = 1;
1342 break;
1343 case DPLL_CFGCR1_KDIV_2:
1344 p2 = 2;
1345 break;
2ee7fd1e
VS		 1346 case DPLL_CFGCR1_KDIV_3:
1347 p2 = 3;
a9701a89
RV		 1348 break;
1349 }
1350
9f9d594d 1351 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1352
5e65216d
LDM		 1353 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1354 * ref_clock;
a9701a89 1355
5e65216d 1356 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1357 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1358
0e005888
PZ		 1359 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1360 return 0;
1361
a9701a89
RV		 1362 return dco_freq / (p0 * p1 * p2 * 5);
1363}
1364
7b19f544
MN		 1365static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1366 enum port port)
1367{
1368 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1369
1370 switch (val) {
1371 case DDI_CLK_SEL_NONE:
1372 return 0;
1373 case DDI_CLK_SEL_TBT_162:
1374 return 162000;
1375 case DDI_CLK_SEL_TBT_270:
1376 return 270000;
1377 case DDI_CLK_SEL_TBT_540:
1378 return 540000;
1379 case DDI_CLK_SEL_TBT_810:
1380 return 810000;
1381 default:
1382 MISSING_CASE(val);
1383 return 0;
1384 }
1385}
1386
1387static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1388 const struct intel_dpll_hw_state *pll_state)
7b19f544 1389{
02c99d26 1390 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1391 u64 tmp;
1392
02c99d26 1393 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1394
02c99d26
LDM		 1395 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1396 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1397 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1398 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1399 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1400
02c99d26
LDM		 1401 switch (pll_state->mg_clktop2_hsclkctl &
1402 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1403 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1404 div1 = 2;
1405 break;
1406 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1407 div1 = 3;
1408 break;
1409 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1410 div1 = 5;
1411 break;
1412 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1413 div1 = 7;
1414 break;
1415 default:
02c99d26 1416 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1417 return 0;
1418 }
1419
02c99d26
LDM		 1420 div2 = (pll_state->mg_clktop2_hsclkctl &
1421 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1422 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1423
7b19f544
MN		 1424 /* div2 value of 0 is same as 1 means no div */
1425 if (div2 == 0)
1426 div2 = 1;
1427
1428 /*
1429 * Adjust the original formula to delay the division by 2^22 in order to
1430 * minimize possible rounding errors.
1431 */
02c99d26
LDM		 1432 tmp = (u64)m1 * m2_int * ref_clock +
1433 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1434 tmp = div_u64(tmp, 5 * div1 * div2);
1435
1436 return tmp;
1437}
1438
398a017e
VS		 1439static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1440{
1441 int dotclock;
1442
1443 if (pipe_config->has_pch_encoder)
1444 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1445 &pipe_config->fdi_m_n);
37a5650b 1446 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1447 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1448 &pipe_config->dp_m_n);
1449 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1450 dotclock = pipe_config->port_clock * 2 / 3;
1451 else
1452 dotclock = pipe_config->port_clock;
1453
33b7f3ee 1454 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
b22ca995
SS		 1455 dotclock *= 2;
1456
398a017e
VS		 1457 if (pipe_config->pixel_multiplier)
1458 dotclock /= pipe_config->pixel_multiplier;
1459
1460 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1461}
540e732c 1462
51c83cfa
MN		 1463static void icl_ddi_clock_get(struct intel_encoder *encoder,
1464 struct intel_crtc_state *pipe_config)
1465{
1466 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1467 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1468 enum port port = encoder->port;
5e65216d 1469 int link_clock;
51c83cfa 1470
176597a1 1471 if (intel_port_is_combophy(dev_priv, port)) {
5e65216d 1472 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1473 } else {
077973c8
LDM		 1474 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1475 pipe_config->shared_dpll);
1476
7b19f544
MN		 1477 if (pll_id == DPLL_ID_ICL_TBTPLL)
1478 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1479 else
02c99d26 1480 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1481 }
1482
1483 pipe_config->port_clock = link_clock;
02c99d26 1484
51c83cfa
MN		 1485 ddi_dotclock_get(pipe_config);
1486}
1487
a9701a89
RV		 1488static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1489 struct intel_crtc_state *pipe_config)
1490{
1491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1492 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1493 int link_clock;
a9701a89 1494
5e65216d
LDM		 1495 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1496 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1497 } else {
5e65216d 1498 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1499
1500 switch (link_clock) {
1501 case DPLL_CFGCR0_LINK_RATE_810:
1502 link_clock = 81000;
1503 break;
1504 case DPLL_CFGCR0_LINK_RATE_1080:
1505 link_clock = 108000;
1506 break;
1507 case DPLL_CFGCR0_LINK_RATE_1350:
1508 link_clock = 135000;
1509 break;
1510 case DPLL_CFGCR0_LINK_RATE_1620:
1511 link_clock = 162000;
1512 break;
1513 case DPLL_CFGCR0_LINK_RATE_2160:
1514 link_clock = 216000;
1515 break;
1516 case DPLL_CFGCR0_LINK_RATE_2700:
1517 link_clock = 270000;
1518 break;
1519 case DPLL_CFGCR0_LINK_RATE_3240:
1520 link_clock = 324000;
1521 break;
1522 case DPLL_CFGCR0_LINK_RATE_4050:
1523 link_clock = 405000;
1524 break;
1525 default:
1526 WARN(1, "Unsupported link rate\n");
1527 break;
1528 }
1529 link_clock *= 2;
1530 }
1531
1532 pipe_config->port_clock = link_clock;
1533
1534 ddi_dotclock_get(pipe_config);
1535}
1536
540e732c 1537static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1538 struct intel_crtc_state *pipe_config)
540e732c 1539{
947f4417
LDM		 1540 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1541 int link_clock;
540e732c 1542
947f4417
LDM		 1543 /*
1544 * ctrl1 register is already shifted for each pll, just use 0 to get
1545 * the internal shift for each field
1546 */
1547 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1548 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1549 } else {
947f4417
LDM		 1550 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1551 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1552
1553 switch (link_clock) {
71cd8423 1554 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1555 link_clock = 81000;
1556 break;
71cd8423 1557 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1558 link_clock = 108000;
1559 break;
71cd8423 1560 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1561 link_clock = 135000;
1562 break;
71cd8423 1563 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1564 link_clock = 162000;
1565 break;
71cd8423 1566 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1567 link_clock = 216000;
1568 break;
71cd8423 1569 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1570 link_clock = 270000;
1571 break;
1572 default:
1573 WARN(1, "Unsupported link rate\n");
1574 break;
1575 }
1576 link_clock *= 2;
1577 }
1578
1579 pipe_config->port_clock = link_clock;
1580
398a017e 1581 ddi_dotclock_get(pipe_config);
540e732c
S		 1582}
1583
3d51278a 1584static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1585 struct intel_crtc_state *pipe_config)
11578553 1586{
fac5e23e 1587 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1588 int link_clock = 0;
1589 u32 val, pll;
1590
c856052a 1591 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1592 switch (val & PORT_CLK_SEL_MASK) {
1593 case PORT_CLK_SEL_LCPLL_810:
1594 link_clock = 81000;
1595 break;
1596 case PORT_CLK_SEL_LCPLL_1350:
1597 link_clock = 135000;
1598 break;
1599 case PORT_CLK_SEL_LCPLL_2700:
1600 link_clock = 270000;
1601 break;
1602 case PORT_CLK_SEL_WRPLL1:
01403de3 1603 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1604 break;
1605 case PORT_CLK_SEL_WRPLL2:
01403de3 1606 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1607 break;
1608 case PORT_CLK_SEL_SPLL:
1609 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1610 if (pll == SPLL_PLL_FREQ_810MHz)
1611 link_clock = 81000;
1612 else if (pll == SPLL_PLL_FREQ_1350MHz)
1613 link_clock = 135000;
1614 else if (pll == SPLL_PLL_FREQ_2700MHz)
1615 link_clock = 270000;
1616 else {
1617 WARN(1, "bad spll freq\n");
1618 return;
1619 }
1620 break;
1621 default:
1622 WARN(1, "bad port clock sel\n");
1623 return;
1624 }
1625
1626 pipe_config->port_clock = link_clock * 2;
1627
398a017e 1628 ddi_dotclock_get(pipe_config);
11578553
JB		 1629}
1630
47c9877e 1631static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1632{
9e2c8475 1633 struct dpll clock;
aa610dcb 1634
aa610dcb 1635 clock.m1 = 2;
47c9877e
LDM		 1636 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1637 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1638 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1639 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1640 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1641 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1642
1643 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1644}
1645
1646static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1647 struct intel_crtc_state *pipe_config)
977bb38d 1648{
47c9877e
LDM		 1649 pipe_config->port_clock =
1650 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1651
398a017e 1652 ddi_dotclock_get(pipe_config);
977bb38d
S		 1653}
1654
35686a44
VS		 1655static void intel_ddi_clock_get(struct intel_encoder *encoder,
1656 struct intel_crtc_state *pipe_config)
3d51278a 1657{
0853723b 1658 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1659
2dd24a9c 1660 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1661 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1662 else if (IS_CANNONLAKE(dev_priv))
1663 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1664 else if (IS_GEN9_LP(dev_priv))
1665 bxt_ddi_clock_get(encoder, pipe_config);
1666 else if (IS_GEN9_BC(dev_priv))
1667 skl_ddi_clock_get(encoder, pipe_config);
1668 else if (INTEL_GEN(dev_priv) <= 8)
1669 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1670}
1671
3dc38eea 1672void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1673{
3dc38eea 1674 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1675 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1676 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1677 u32 temp;
dae84799 1678
5448f53f
VS		 1679 if (!intel_crtc_has_dp_encoder(crtc_state))
1680 return;
4d1de975 1681
5448f53f
VS		 1682 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1683
1684 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1685
1686 if (crtc_state->limited_color_range)
1687 temp |= TRANS_MSA_CEA_RANGE;
1688
5448f53f
VS		 1689 switch (crtc_state->pipe_bpp) {
1690 case 18:
1691 temp |= TRANS_MSA_6_BPC;
1692 break;
1693 case 24:
1694 temp |= TRANS_MSA_8_BPC;
1695 break;
1696 case 30:
1697 temp |= TRANS_MSA_10_BPC;
1698 break;
1699 case 36:
1700 temp |= TRANS_MSA_12_BPC;
1701 break;
1702 default:
1703 MISSING_CASE(crtc_state->pipe_bpp);
1704 break;
dae84799 1705 }
5448f53f 1706
668b6c17
SS		 1707 /*
1708 * As per DP 1.2 spec section 2.3.4.3 while sending
1709 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1710 * colorspace information. The output colorspace encoding is BT601.
1711 */
1712 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1713 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
5448f53f 1714 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1715}
1716
3dc38eea
ACO		 1717void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1718 bool state)
0e32b39c 1719{
3dc38eea 1720 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1721 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1722 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1723 u32 temp;
7e732cac 1724
0e32b39c
DA		 1725 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1726 if (state == true)
1727 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1728 else
1729 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1730 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1731}
1732
3dc38eea 1733void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1734{
3dc38eea 1735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1736 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1738 enum pipe pipe = crtc->pipe;
3dc38eea 1739 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1740 enum port port = encoder->port;
3d0c5005 1741 u32 temp;
8d9ddbcb 1742
ad80a810
PZ		 1743 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1744 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1745 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1746
3dc38eea 1747 switch (crtc_state->pipe_bpp) {
dfcef252 1748 case 18:
ad80a810 1749 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1750 break;
1751 case 24:
ad80a810 1752 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1753 break;
1754 case 30:
ad80a810 1755 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1756 break;
1757 case 36:
ad80a810 1758 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1759 break;
1760 default:
4e53c2e0 1761 BUG();
dfcef252 1762 }
72662e10 1763
3dc38eea 1764 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1765 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1766 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1767 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1768
e6f0bfc4
PZ		 1769 if (cpu_transcoder == TRANSCODER_EDP) {
1770 switch (pipe) {
1771 case PIPE_A:
c7670b10
PZ		 1772 /* On Haswell, can only use the always-on power well for
1773 * eDP when not using the panel fitter, and when not
1774 * using motion blur mitigation (which we don't
1775 * support). */
772c2a51 1776 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1777 (crtc_state->pch_pfit.enabled ||
1778 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1779 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1780 else
1781 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1782 break;
1783 case PIPE_B:
1784 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1785 break;
1786 case PIPE_C:
1787 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1788 break;
1789 default:
1790 BUG();
1791 break;
1792 }
1793 }
1794
742745f1 1795 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1796 if (crtc_state->has_hdmi_sink)
ad80a810 1797 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1798 else
ad80a810 1799 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1800
1801 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1802 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1803 if (crtc_state->hdmi_high_tmds_clock_ratio)
1804 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1805 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1806 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1807 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1808 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1809 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1810 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1811 } else {
742745f1
VS		 1812 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1813 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1814 }
1815
ad80a810 1816 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1817}
72662e10 1818
90c3e219 1819void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1820{
90c3e219
CT		 1821 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1824 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1825 u32 val = I915_READ(reg);
8d9ddbcb 1826
0e32b39c 1827 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1828 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1829 I915_WRITE(reg, val);
90c3e219
CT		 1830
1831 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1832 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1833 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1834 /* Quirk time at 100ms for reliable operation */
1835 msleep(100);
1836 }
72662e10
ED		 1837}
1838
2320175f
SP		 1839int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1840 bool enable)
1841{
1842 struct drm_device *dev = intel_encoder->base.dev;
1843 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1844 intel_wakeref_t wakeref;
2320175f
SP		 1845 enum pipe pipe = 0;
1846 int ret = 0;
3d0c5005 1847 u32 tmp;
2320175f 1848
0e6e0be4
CW		 1849 wakeref = intel_display_power_get_if_enabled(dev_priv,
1850 intel_encoder->power_domain);
1851 if (WARN_ON(!wakeref))
2320175f
SP		 1852 return -ENXIO;
1853
1854 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1855 ret = -EIO;
1856 goto out;
1857 }
1858
1859 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1860 if (enable)
1861 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1862 else
1863 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1864 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1865out:
0e6e0be4 1866 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1867 return ret;
1868}
1869
bcbc889b
PZ		 1870bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1871{
1872 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1873 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1874 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1875 int type = intel_connector->base.connector_type;
0fce04c8 1876 enum port port = encoder->port;
bcbc889b 1877 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1878 intel_wakeref_t wakeref;
1879 enum pipe pipe = 0;
3d0c5005 1880 u32 tmp;
e27daab4 1881 bool ret;
bcbc889b 1882
0e6e0be4
CW		 1883 wakeref = intel_display_power_get_if_enabled(dev_priv,
1884 encoder->power_domain);
1885 if (!wakeref)
882244a3
PZ		 1886 return false;
1887
1524e93e 1888 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1889 ret = false;
1890 goto out;
1891 }
bcbc889b 1892
bc7e3525 1893 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1894 cpu_transcoder = TRANSCODER_EDP;
1895 else
1a240d4d 1896 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1897
1898 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1899
1900 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1901 case TRANS_DDI_MODE_SELECT_HDMI:
1902 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1903 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1904 break;
bcbc889b
PZ		 1905
1906 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1907 ret = type == DRM_MODE_CONNECTOR_eDP ||
1908 type == DRM_MODE_CONNECTOR_DisplayPort;
1909 break;
1910
0e32b39c
DA		 1911 case TRANS_DDI_MODE_SELECT_DP_MST:
1912 /* if the transcoder is in MST state then
1913 * connector isn't connected */
e27daab4
ID		 1914 ret = false;
1915 break;
bcbc889b
PZ		 1916
1917 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1918 ret = type == DRM_MODE_CONNECTOR_VGA;
1919 break;
bcbc889b
PZ		 1920
1921 default:
e27daab4
ID		 1922 ret = false;
1923 break;
bcbc889b 1924 }
e27daab4
ID		 1925
1926out:
0e6e0be4 1927 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 1928
1929 return ret;
bcbc889b
PZ		 1930}
1931
9199c322
ID		 1932static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1933 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 1934{
1935 struct drm_device *dev = encoder->base.dev;
fac5e23e 1936 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1937 enum port port = encoder->port;
0e6e0be4 1938 intel_wakeref_t wakeref;
3657e927 1939 enum pipe p;
85234cdc 1940 u32 tmp;
9199c322
ID		 1941 u8 mst_pipe_mask;
1942
1943 *pipe_mask = 0;
1944 *is_dp_mst = false;
85234cdc 1945
0e6e0be4
CW		 1946 wakeref = intel_display_power_get_if_enabled(dev_priv,
1947 encoder->power_domain);
1948 if (!wakeref)
9199c322 1949 return;
e27daab4 1950
fe43d3f5 1951 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 1952 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1953 goto out;
85234cdc 1954
bc7e3525 1955 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 1956 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1957
ad80a810 1958 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 1959 default:
1960 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1961 /* fallthrough */
ad80a810
PZ		 1962 case TRANS_DDI_EDP_INPUT_A_ON:
1963 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 1964 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 1965 break;
1966 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 1967 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 1968 break;
1969 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 1970 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 1971 break;
1972 }
1973
e27daab4
ID		 1974 goto out;
1975 }
0e32b39c 1976
9199c322 1977 mst_pipe_mask = 0;
3657e927 1978 for_each_pipe(dev_priv, p) {
9199c322 1979 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 1980
1981 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 1982
9199c322
ID		 1983 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1984 continue;
e27daab4 1985
9199c322
ID		 1986 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1987 TRANS_DDI_MODE_SELECT_DP_MST)
1988 mst_pipe_mask |= BIT(p);
e27daab4 1989
9199c322 1990 *pipe_mask |= BIT(p);
85234cdc
DV		 1991 }
1992
9199c322
ID		 1993 if (!*pipe_mask)
1994 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
1995 port_name(port));
1996
1997 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1998 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
1999 port_name(port), *pipe_mask);
2000 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2001 }
2002
2003 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2004 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2005 port_name(port), *pipe_mask, mst_pipe_mask);
2006 else
2007 *is_dp_mst = mst_pipe_mask;
85234cdc 2008
e27daab4 2009out:
9199c322 2010 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2011 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2012 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2013 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2014 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2015 DRM_ERROR("Port %c enabled but PHY powered down? "
2016 "(PHY_CTL %08x)\n", port_name(port), tmp);
2017 }
2018
0e6e0be4 2019 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2020}
e27daab4 2021
9199c322
ID		 2022bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2023 enum pipe *pipe)
2024{
2025 u8 pipe_mask;
2026 bool is_mst;
2027
2028 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2029
2030 if (is_mst || !pipe_mask)
2031 return false;
2032
2033 *pipe = ffs(pipe_mask) - 1;
2034
2035 return true;
85234cdc
DV		 2036}
2037
52528055 2038static inline enum intel_display_power_domain
bdaa29b6 2039intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2040{
9e3b5ce9 2041 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2042 * DC states enabled at the same time, while for driver initiated AUX
2043 * transfers we need the same AUX IOs to be powered but with DC states
2044 * disabled. Accordingly use the AUX power domain here which leaves DC
2045 * states enabled.
2046 * However, for non-A AUX ports the corresponding non-EDP transcoders
2047 * would have already enabled power well 2 and DC_OFF. This means we can
2048 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2049 * specific AUX_IO reference without powering up any extra wells.
2050 * Note that PSR is enabled only on Port A even though this function
2051 * returns the correct domain for other ports too.
2052 */
563d22a0 2053 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2054 intel_aux_power_domain(dig_port);
52528055
ID		 2055}
2056
3a52fb7e
ID		 2057static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2058 struct intel_crtc_state *crtc_state)
62b69566 2059{
8e4a3ad9 2060 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2061 struct intel_digital_port *dig_port;
62b69566 2062
52528055
ID		 2063 /*
2064 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2065 * happen since fake-MST encoders don't set their get_power_domains()
2066 * hook.
52528055
ID		 2067 */
2068 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2069 return;
b79ebe74
ID		 2070
2071 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2072 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2073
8e4a3ad9
ID		 2074 /*
2075 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2076 * ports.
2077 */
2078 if (intel_crtc_has_dp_encoder(crtc_state) ||
2079 intel_port_is_tc(dev_priv, encoder->port))
3a52fb7e
ID		 2080 intel_display_power_get(dev_priv,
2081 intel_ddi_main_link_aux_domain(dig_port));
52528055 2082
a24c62f9
MN		 2083 /*
2084 * VDSC power is needed when DSC is enabled
2085 */
2086 if (crtc_state->dsc_params.compression_enable)
3a52fb7e
ID		 2087 intel_display_power_get(dev_priv,
2088 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2089}
2090
3dc38eea 2091void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2092{
3dc38eea 2093 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2094 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2095 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2096 enum port port = encoder->port;
3dc38eea 2097 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2098
bb523fc0
PZ		 2099 if (cpu_transcoder != TRANSCODER_EDP)
2100 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2101 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2102}
2103
3dc38eea 2104void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2105{
3dc38eea
ACO		 2106 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2107 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2108
bb523fc0
PZ		 2109 if (cpu_transcoder != TRANSCODER_EDP)
2110 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2111 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2112}
2113
a7d8dbc0 2114static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2115 enum port port, u8 iboost)
f8896f5d 2116{
a7d8dbc0
VS		 2117 u32 tmp;
2118
2119 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2120 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2121 if (iboost)
2122 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2123 else
2124 tmp |= BALANCE_LEG_DISABLE(port);
2125 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2126}
2127
081dfcfa
VS		 2128static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2129 int level, enum intel_output_type type)
a7d8dbc0
VS		 2130{
2131 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2132 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2133 enum port port = encoder->port;
3d0c5005 2134 u8 iboost;
f8896f5d 2135
081dfcfa
VS		 2136 if (type == INTEL_OUTPUT_HDMI)
2137 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2138 else
2139 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2140
081dfcfa
VS		 2141 if (iboost == 0) {
2142 const struct ddi_buf_trans *ddi_translations;
2143 int n_entries;
2144
2145 if (type == INTEL_OUTPUT_HDMI)
2146 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2147 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2148 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2149 else
edba48fd 2150 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2151
21b39d2a
VS		 2152 if (WARN_ON_ONCE(!ddi_translations))
2153 return;
2154 if (WARN_ON_ONCE(level >= n_entries))
2155 level = n_entries - 1;
2156
081dfcfa 2157 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2158 }
2159
2160 /* Make sure that the requested I_boost is valid */
2161 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2162 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2163 return;
2164 }
2165
a7d8dbc0 2166 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2167
a7d8dbc0
VS		 2168 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2169 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2170}
2171
7d4f37b5
VS		 2172static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2173 int level, enum intel_output_type type)
96fb9f9b 2174{
7d4f37b5 2175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2176 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2177 enum port port = encoder->port;
043eaf36 2178 int n_entries;
7d4f37b5
VS		 2179
2180 if (type == INTEL_OUTPUT_HDMI)
2181 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2182 else if (type == INTEL_OUTPUT_EDP)
2183 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2184 else
2185 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2186
21b39d2a
VS		 2187 if (WARN_ON_ONCE(!ddi_translations))
2188 return;
2189 if (WARN_ON_ONCE(level >= n_entries))
2190 level = n_entries - 1;
2191
b6e08203
ACO		 2192 bxt_ddi_phy_set_signal_level(dev_priv, port,
2193 ddi_translations[level].margin,
2194 ddi_translations[level].scale,
2195 ddi_translations[level].enable,
2196 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2197}
2198
ffe5111e
VS		 2199u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2200{
2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2202 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2203 enum port port = encoder->port;
ffe5111e
VS		 2204 int n_entries;
2205
2dd24a9c 2206 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2207 if (intel_port_is_combophy(dev_priv, port))
36cf89f5 2208 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
b265a2a6 2209 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2210 else
2211 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2212 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2213 if (encoder->type == INTEL_OUTPUT_EDP)
2214 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2215 else
2216 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2217 } else if (IS_GEN9_LP(dev_priv)) {
2218 if (encoder->type == INTEL_OUTPUT_EDP)
2219 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2220 else
2221 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2222 } else {
2223 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2224 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2225 else
edba48fd 2226 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2227 }
ffe5111e
VS		 2228
2229 if (WARN_ON(n_entries < 1))
2230 n_entries = 1;
2231 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2232 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2233
2234 return index_to_dp_signal_levels[n_entries - 1] &
2235 DP_TRAIN_VOLTAGE_SWING_MASK;
2236}
2237
4718a365
VS		 2238/*
2239 * We assume that the full set of pre-emphasis values can be
2240 * used on all DDI platforms. Should that change we need to
2241 * rethink this code.
2242 */
2243u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2244{
2245 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2247 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2249 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2251 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2253 default:
2254 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2255 }
2256}
2257
f3cf4ba4
VS		 2258static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2259 int level, enum intel_output_type type)
cf54ca8b 2260{
f3cf4ba4 2261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2262 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2263 enum port port = encoder->port;
f3cf4ba4
VS		 2264 int n_entries, ln;
2265 u32 val;
cf54ca8b 2266
f3cf4ba4 2267 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2268 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2269 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2270 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2271 else
2272 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2273
21b39d2a 2274 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2275 return;
21b39d2a 2276 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2277 level = n_entries - 1;
cf54ca8b
RV		 2278
2279 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2280 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2281 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2282 val |= SCALING_MODE_SEL(2);
2283 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2284
2285 /* Program PORT_TX_DW2 */
2286 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2287 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2288 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2289 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2290 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2291 /* Rcomp scalar is fixed as 0x98 for every table entry */
2292 val |= RCOMP_SCALAR(0x98);
2293 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2294
20303eb4 2295 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2296 /* We cannot write to GRP. It would overrite individual loadgen */
2297 for (ln = 0; ln < 4; ln++) {
9194e42a 2298 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2299 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2300 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2301 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2302 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2303 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2304 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2305 }
2306
20303eb4 2307 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2308 /* All DW5 values are fixed for every table entry */
2309 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2310 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2311 val |= RTERM_SELECT(6);
2312 val |= TAP3_DISABLE;
2313 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2314
20303eb4 2315 /* Program PORT_TX_DW7 */
cf54ca8b 2316 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2317 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2318 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2319 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2320}
2321
f3cf4ba4
VS		 2322static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2323 int level, enum intel_output_type type)
cf54ca8b 2324{
0091abc3 2325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2326 enum port port = encoder->port;
f3cf4ba4 2327 int width, rate, ln;
cf54ca8b 2328 u32 val;
0091abc3 2329
f3cf4ba4 2330 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2331 width = 4;
f3cf4ba4 2332 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2333 } else {
f3cf4ba4
VS		 2334 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2335
2336 width = intel_dp->lane_count;
2337 rate = intel_dp->link_rate;
0091abc3 2338 }
cf54ca8b
RV		 2339
2340 /*
2341 * 1. If port type is eDP or DP,
2342 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2343 * else clear to 0b.
2344 */
2345 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2346 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2347 val |= COMMON_KEEPER_EN;
2348 else
2349 val &= ~COMMON_KEEPER_EN;
2350 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2351
2352 /* 2. Program loadgen select */
2353 /*
0091abc3
CT		 2354 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2355 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2356 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2357 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2358 */
0091abc3 2359 for (ln = 0; ln <= 3; ln++) {
9194e42a 2360 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2361 val &= ~LOADGEN_SELECT;
2362
a8e45a1c
NM		 2363 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2364 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2365 val |= LOADGEN_SELECT;
2366 }
9194e42a 2367 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2368 }
cf54ca8b
RV		 2369
2370 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2371 val = I915_READ(CNL_PORT_CL1CM_DW5);
2372 val |= SUS_CLOCK_CONFIG;
2373 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2374
2375 /* 4. Clear training enable to change swing values */
2376 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2377 val &= ~TX_TRAINING_EN;
2378 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2379
2380 /* 5. Program swing and de-emphasis */
f3cf4ba4 2381 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2382
2383 /* 6. Set training enable to trigger update */
2384 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2385 val |= TX_TRAINING_EN;
2386 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2387}
2388
fb5c8e9d 2389static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
b265a2a6
CT		 2390 u32 level, enum port port, int type,
2391 int rate)
fb5c8e9d 2392{
b265a2a6 2393 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2394 u32 n_entries, val;
2395 int ln;
2396
2397 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
b265a2a6 2398 rate, &n_entries);
fb5c8e9d
MN		 2399 if (!ddi_translations)
2400 return;
2401
2402 if (level >= n_entries) {
2403 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2404 level = n_entries - 1;
2405 }
2406
b265a2a6 2407 /* Set PORT_TX_DW5 */
fb5c8e9d 2408 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
b265a2a6
CT		 2409 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2410 TAP2_DISABLE | TAP3_DISABLE);
2411 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2412 val |= RTERM_SELECT(0x6);
b265a2a6 2413 val |= TAP3_DISABLE;
fb5c8e9d
MN		 2414 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2415
2416 /* Program PORT_TX_DW2 */
2417 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2418 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2419 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2420 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2421 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2422 /* Program Rcomp scalar for every table entry */
b265a2a6 2423 val |= RCOMP_SCALAR(0x98);
fb5c8e9d
MN		 2424 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2425
2426 /* Program PORT_TX_DW4 */
2427 /* We cannot write to GRP. It would overwrite individual loadgen. */
2428 for (ln = 0; ln <= 3; ln++) {
9194e42a 2429 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2430 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2431 CURSOR_COEFF_MASK);
b265a2a6
CT		 2432 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2433 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2434 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2435 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d 2436 }
b265a2a6
CT		 2437
2438 /* Program PORT_TX_DW7 */
2439 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2440 val &= ~N_SCALAR_MASK;
2441 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2442 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
fb5c8e9d
MN		 2443}
2444
2445static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2446 u32 level,
2447 enum intel_output_type type)
2448{
2449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2450 enum port port = encoder->port;
2451 int width = 0;
2452 int rate = 0;
2453 u32 val;
2454 int ln = 0;
2455
2456 if (type == INTEL_OUTPUT_HDMI) {
2457 width = 4;
2458 /* Rate is always < than 6GHz for HDMI */
2459 } else {
2460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461
2462 width = intel_dp->lane_count;
2463 rate = intel_dp->link_rate;
2464 }
2465
2466 /*
2467 * 1. If port type is eDP or DP,
2468 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2469 * else clear to 0b.
2470 */
2471 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2472 if (type == INTEL_OUTPUT_HDMI)
2473 val &= ~COMMON_KEEPER_EN;
2474 else
2475 val |= COMMON_KEEPER_EN;
2476 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2477
2478 /* 2. Program loadgen select */
2479 /*
2480 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2481 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2482 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2483 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2484 */
2485 for (ln = 0; ln <= 3; ln++) {
9194e42a 2486 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2487 val &= ~LOADGEN_SELECT;
2488
2489 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2490 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2491 val |= LOADGEN_SELECT;
2492 }
9194e42a 2493 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d
MN		 2494 }
2495
2496 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2497 val = I915_READ(ICL_PORT_CL_DW5(port));
2498 val |= SUS_CLOCK_CONFIG;
2499 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2500
2501 /* 4. Clear training enable to change swing values */
2502 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2503 val &= ~TX_TRAINING_EN;
2504 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2505
2506 /* 5. Program swing and de-emphasis */
b265a2a6 2507 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
fb5c8e9d
MN		 2508
2509 /* 6. Set training enable to trigger update */
2510 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2511 val |= TX_TRAINING_EN;
2512 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2513}
2514
07685c82
MN		 2515static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2516 int link_clock,
2517 u32 level)
2518{
2519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2520 enum port port = encoder->port;
2521 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2522 u32 n_entries, val;
2523 int ln;
2524
2525 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2526 ddi_translations = icl_mg_phy_ddi_translations;
2527 /* The table does not have values for level 3 and level 9. */
2528 if (level >= n_entries || level == 3 || level == 9) {
2529 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2530 level, n_entries - 2);
2531 level = n_entries - 2;
2532 }
2533
2534 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2535 for (ln = 0; ln < 2; ln++) {
58106b7d 2536 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2537 val &= ~CRI_USE_FS32;
58106b7d 2538 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2539
58106b7d 2540 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2541 val &= ~CRI_USE_FS32;
58106b7d 2542 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2543 }
2544
2545 /* Program MG_TX_SWINGCTRL with values from vswing table */
2546 for (ln = 0; ln < 2; ln++) {
58106b7d 2547 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2548 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2549 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2550 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2551 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2552
58106b7d 2553 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2554 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2555 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2556 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2557 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2558 }
2559
2560 /* Program MG_TX_DRVCTRL with values from vswing table */
2561 for (ln = 0; ln < 2; ln++) {
58106b7d 2562 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2563 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2564 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2565 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2566 ddi_translations[level].cri_txdeemph_override_5_0) |
2567 CRI_TXDEEMPH_OVERRIDE_11_6(
2568 ddi_translations[level].cri_txdeemph_override_11_6) |
2569 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2570 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2571
58106b7d 2572 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2573 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2574 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2575 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2576 ddi_translations[level].cri_txdeemph_override_5_0) |
2577 CRI_TXDEEMPH_OVERRIDE_11_6(
2578 ddi_translations[level].cri_txdeemph_override_11_6) |
2579 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2580 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2581
2582 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2583 }
2584
2585 /*
2586 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2587 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2588 * values from table for which TX1 and TX2 enabled.
2589 */
2590 for (ln = 0; ln < 2; ln++) {
58106b7d 2591 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2592 if (link_clock < 300000)
2593 val |= CFG_LOW_RATE_LKREN_EN;
2594 else
2595 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2596 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2597 }
2598
2599 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2600 for (ln = 0; ln < 2; ln++) {
58106b7d 2601 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2602 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2603 if (link_clock <= 500000) {
2604 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2605 } else {
2606 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2607 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2608 }
58106b7d 2609 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2610
58106b7d 2611 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2612 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2613 if (link_clock <= 500000) {
2614 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2615 } else {
2616 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2617 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2618 }
58106b7d 2619 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2620 }
2621
2622 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2623 for (ln = 0; ln < 2; ln++) {
58106b7d 2624 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2625 val |= CRI_CALCINIT;
58106b7d 2626 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2627
58106b7d 2628 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2629 val |= CRI_CALCINIT;
58106b7d 2630 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2631 }
2632}
2633
2634static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2635 int link_clock,
2636 u32 level,
fb5c8e9d
MN		 2637 enum intel_output_type type)
2638{
176597a1 2639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2640 enum port port = encoder->port;
2641
176597a1 2642 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2643 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2644 else
07685c82 2645 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2646}
2647
3d0c5005 2648static u32 translate_signal_level(int signal_levels)
f8896f5d 2649{
97eeb872 2650 int i;
f8896f5d 2651
97eeb872
VS		 2652 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2653 if (index_to_dp_signal_levels[i] == signal_levels)
2654 return i;
f8896f5d
DW		 2655 }
2656
97eeb872
VS		 2657 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2658 signal_levels);
2659
2660 return 0;
f8896f5d
DW		 2661}
2662
3d0c5005 2663static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2664{
3d0c5005 2665 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2666 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2667 DP_TRAIN_PRE_EMPHASIS_MASK);
2668
2669 return translate_signal_level(signal_levels);
2670}
2671
d509af6c 2672u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2673{
2674 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2675 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2676 struct intel_encoder *encoder = &dport->base;
d02ace87 2677 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2678
2dd24a9c 2679 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2680 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2681 level, encoder->type);
fb5c8e9d 2682 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2683 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2684 else
7d4f37b5 2685 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2686
2687 return 0;
2688}
2689
3d0c5005 2690u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2691{
2692 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2693 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2694 struct intel_encoder *encoder = &dport->base;
d02ace87 2695 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2696
b976dc53 2697 if (IS_GEN9_BC(dev_priv))
081dfcfa 2698 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2699
f8896f5d
DW		 2700 return DDI_BUF_TRANS_SELECT(level);
2701}
2702
bb1c7edc 2703static inline
3d0c5005
JN		 2704u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2705 enum port port)
bb1c7edc
MK		 2706{
2707 if (intel_port_is_combophy(dev_priv, port)) {
2708 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2709 } else if (intel_port_is_tc(dev_priv, port)) {
2710 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2711
2712 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2713 }
2714
2715 return 0;
2716}
2717
3b8c0d5b
JN		 2718static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2719 const struct intel_crtc_state *crtc_state)
c27e917e 2720{
3b8c0d5b 2721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2722 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3b8c0d5b
JN		 2723 enum port port = encoder->port;
2724 u32 val;
c27e917e 2725
3b8c0d5b 2726 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2727
3b8c0d5b
JN		 2728 val = I915_READ(DPCLKA_CFGCR0_ICL);
2729 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2730
3b8c0d5b
JN		 2731 if (intel_port_is_combophy(dev_priv, port)) {
2732 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2733 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
c27e917e 2734 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
3b8c0d5b 2735 POSTING_READ(DPCLKA_CFGCR0_ICL);
c27e917e 2736 }
3b8c0d5b
JN		 2737
2738 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2739 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2740
2741 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2742}
2743
3b8c0d5b 2744static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2745{
3b8c0d5b
JN		 2746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2747 enum port port = encoder->port;
2748 u32 val;
c27e917e 2749
3b8c0d5b 2750 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2751
3b8c0d5b
JN		 2752 val = I915_READ(DPCLKA_CFGCR0_ICL);
2753 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2754 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
c27e917e 2755
3b8c0d5b 2756 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2757}
2758
70332ac5
ID		 2759void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2760{
2761 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2762 u32 val;
1dd07e56
ID		 2763 enum port port;
2764 u32 port_mask;
2765 bool ddi_clk_needed;
30f5ccfa
ID		 2766
2767 /*
2768 * In case of DP MST, we sanitize the primary encoder only, not the
2769 * virtual ones.
2770 */
2771 if (encoder->type == INTEL_OUTPUT_DP_MST)
2772 return;
2773
30f5ccfa
ID		 2774 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2775 u8 pipe_mask;
2776 bool is_mst;
2777
2778 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2779 /*
2780 * In the unlikely case that BIOS enables DP in MST mode, just
2781 * warn since our MST HW readout is incomplete.
2782 */
2783 if (WARN_ON(is_mst))
2784 return;
2785 }
70332ac5 2786
1dd07e56
ID		 2787 port_mask = BIT(encoder->port);
2788 ddi_clk_needed = encoder->base.crtc;
70332ac5 2789
1dd07e56
ID		 2790 if (encoder->type == INTEL_OUTPUT_DSI) {
2791 struct intel_encoder *other_encoder;
70332ac5 2792
1dd07e56
ID		 2793 port_mask = intel_dsi_encoder_ports(encoder);
2794 /*
2795 * Sanity check that we haven't incorrectly registered another
2796 * encoder using any of the ports of this DSI encoder.
2797 */
2798 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2799 if (other_encoder == encoder)
2800 continue;
2801
2802 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2803 return;
2804 }
2805 /*
942d1cf4
VK		 2806 * For DSI we keep the ddi clocks gated
2807 * except during enable/disable sequence.
1dd07e56 2808 */
942d1cf4 2809 ddi_clk_needed = false;
1dd07e56
ID		 2810 }
2811
2812 val = I915_READ(DPCLKA_CFGCR0_ICL);
2813 for_each_port_masked(port, port_mask) {
2814 bool ddi_clk_ungated = !(val &
2815 icl_dpclka_cfgcr0_clk_off(dev_priv,
2816 port));
2817
2818 if (ddi_clk_needed == ddi_clk_ungated)
2819 continue;
2820
2821 /*
2822 * Punt on the case now where clock is gated, but it would
2823 * be needed by the port. Something else is really broken then.
2824 */
2825 if (WARN_ON(ddi_clk_needed))
2826 continue;
2827
2828 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2829 port_name(port));
2830 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2831 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2832 }
70332ac5
ID		 2833}
2834
d7c530b2 2835static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2836 const struct intel_crtc_state *crtc_state)
6441ab5f 2837{
e404ba8d 2838 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2839 enum port port = encoder->port;
3d0c5005 2840 u32 val;
0e5fa646 2841 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2842
c856052a
ACO		 2843 if (WARN_ON(!pll))
2844 return;
2845
04bf68bb 2846 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2847
2dd24a9c 2848 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2849 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2850 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2851 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c27e917e 2852 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2853 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2854 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2855 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2856 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2857 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2858
555e38d2
RV		 2859 /*
2860 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2861 * This step and the step before must be done with separate
2862 * register writes.
2863 */
2864 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2865 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2866 I915_WRITE(DPCLKA_CFGCR0, val);
2867 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2868 /* DDI -> PLL mapping */
efa80add
S		 2869 val = I915_READ(DPLL_CTRL2);
2870
2871 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2872 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2873 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2874 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2875
2876 I915_WRITE(DPLL_CTRL2, val);
5416d871 2877
c56b89f1 2878 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2879 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2880 }
8edcda12
RV		 2881
2882 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2883}
2884
6b8506d5
VS		 2885static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2886{
2887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2888 enum port port = encoder->port;
6b8506d5 2889
2dd24a9c 2890 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2891 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2892 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2893 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2894 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2895 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2896 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2897 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2898 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2899 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2900 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2901 }
6b8506d5
VS		 2902}
2903
cb9ff519
ID		 2904static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2905{
2906 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2907 enum port port = dig_port->base.port;
2908 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2909 u32 val;
9c11b121 2910 int ln;
cb9ff519
ID		 2911
2912 if (tc_port == PORT_TC_NONE)
2913 return;
2914
9c11b121
ID		 2915 for (ln = 0; ln < 2; ln++) {
2916 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2917 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2918 MG_DP_MODE_CFG_TRPWR_GATING |
2919 MG_DP_MODE_CFG_CLNPWR_GATING |
2920 MG_DP_MODE_CFG_DIGPWR_GATING |
2921 MG_DP_MODE_CFG_GAONPWR_GATING;
9c11b121 2922 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2923 }
2924
2925 val = I915_READ(MG_MISC_SUS0(tc_port));
2926 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2927 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2928 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2929 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2930 MG_MISC_SUS0_CFG_TRPWR_GATING |
2931 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2932 MG_MISC_SUS0_CFG_DGPWR_GATING;
2933 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2934}
2935
2936static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2937{
2938 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2939 enum port port = dig_port->base.port;
2940 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2941 u32 val;
9c11b121 2942 int ln;
cb9ff519
ID		 2943
2944 if (tc_port == PORT_TC_NONE)
2945 return;
2946
9c11b121
ID		 2947 for (ln = 0; ln < 2; ln++) {
2948 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2949 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2950 MG_DP_MODE_CFG_TRPWR_GATING |
2951 MG_DP_MODE_CFG_CLNPWR_GATING |
2952 MG_DP_MODE_CFG_DIGPWR_GATING |
2953 MG_DP_MODE_CFG_GAONPWR_GATING);
9c11b121 2954 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2955 }
2956
2957 val = I915_READ(MG_MISC_SUS0(tc_port));
2958 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2959 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2960 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2961 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2962 MG_MISC_SUS0_CFG_TRPWR_GATING |
2963 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2964 MG_MISC_SUS0_CFG_DGPWR_GATING);
2965 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2966}
2967
93b662d3
ID		 2968static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2969{
2970 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2971 enum port port = intel_dig_port->base.port;
2972 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2973 u32 ln0, ln1, lane_info;
2974
2975 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2976 return;
2977
37fc7845
JRS		 2978 ln0 = I915_READ(MG_DP_MODE(0, port));
2979 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3
ID		 2980
2981 switch (intel_dig_port->tc_type) {
2982 case TC_PORT_TYPEC:
2983 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2984 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2985
2986 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2987 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2988 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2989
2990 switch (lane_info) {
2991 case 0x1:
2992 case 0x4:
2993 break;
2994 case 0x2:
2995 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2996 break;
2997 case 0x3:
2998 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
2999 MG_DP_MODE_CFG_DP_X2_MODE;
3000 break;
3001 case 0x8:
3002 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3003 break;
3004 case 0xC:
3005 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3006 MG_DP_MODE_CFG_DP_X2_MODE;
3007 break;
3008 case 0xF:
3009 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3010 MG_DP_MODE_CFG_DP_X2_MODE;
3011 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012 MG_DP_MODE_CFG_DP_X2_MODE;
3013 break;
3014 default:
3015 MISSING_CASE(lane_info);
3016 }
3017 break;
3018
3019 case TC_PORT_LEGACY:
3020 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3021 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3022 break;
3023
3024 default:
3025 MISSING_CASE(intel_dig_port->tc_type);
3026 return;
3027 }
3028
37fc7845
JRS		 3029 I915_WRITE(MG_DP_MODE(0, port), ln0);
3030 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3031}
3032
a322b975
AS		 3033static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3034 const struct intel_crtc_state *crtc_state)
3035{
3036 if (!crtc_state->fec_enable)
3037 return;
3038
3039 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3040 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3041}
3042
5c44b938
AS		 3043static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3044 const struct intel_crtc_state *crtc_state)
3045{
3046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3047 enum port port = encoder->port;
3048 u32 val;
3049
3050 if (!crtc_state->fec_enable)
3051 return;
3052
3053 val = I915_READ(DP_TP_CTL(port));
3054 val |= DP_TP_CTL_FEC_ENABLE;
3055 I915_WRITE(DP_TP_CTL(port), val);
3056
97a04e0d 3057 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
5c44b938
AS		 3058 DP_TP_STATUS_FEC_ENABLE_LIVE,
3059 DP_TP_STATUS_FEC_ENABLE_LIVE,
3060 1))
3061 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3062}
3063
d6a09cee
AS		 3064static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3065 const struct intel_crtc_state *crtc_state)
3066{
3067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3068 enum port port = encoder->port;
3069 u32 val;
3070
3071 if (!crtc_state->fec_enable)
3072 return;
3073
3074 val = I915_READ(DP_TP_CTL(port));
3075 val &= ~DP_TP_CTL_FEC_ENABLE;
3076 I915_WRITE(DP_TP_CTL(port), val);
3077 POSTING_READ(DP_TP_CTL(port));
3078}
3079
ba88d153 3080static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3081 const struct intel_crtc_state *crtc_state,
3082 const struct drm_connector_state *conn_state)
e404ba8d 3083{
ba88d153
MN		 3084 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3085 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3086 enum port port = encoder->port;
62b69566 3087 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3088 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3089 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3090
45e0327e 3091 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3092
45e0327e
VS		 3093 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3094 crtc_state->lane_count, is_mst);
680b71c2
VS		 3095
3096 intel_edp_panel_on(intel_dp);
32bdc400 3097
0e5fa646 3098 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3099
3100 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3101
93b662d3 3102 icl_program_mg_dp_mode(dig_port);
bc334d91 3103 icl_disable_phy_clock_gating(dig_port);
340a44be 3104
2dd24a9c 3105 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3106 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3107 level, encoder->type);
fb5c8e9d 3108 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3109 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3110 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3111 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3112 else
3a6d84e6 3113 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3114
ba88d153 3115 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3116 if (!is_mst)
3117 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3118 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3119 true);
a322b975 3120 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3121 intel_dp_start_link_train(intel_dp);
3122 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3123 intel_dp_stop_link_train(intel_dp);
afb2c443 3124
5c44b938
AS		 3125 intel_ddi_enable_fec(encoder, crtc_state);
3126
bc334d91
PZ		 3127 icl_enable_phy_clock_gating(dig_port);
3128
2b5cf4ef
ID		 3129 if (!is_mst)
3130 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3131
3132 intel_dsc_enable(encoder, crtc_state);
ba88d153 3133}
901c2daf 3134
ba88d153 3135static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3136 const struct intel_crtc_state *crtc_state,
45e0327e 3137 const struct drm_connector_state *conn_state)
ba88d153 3138{
f99be1b3
VS		 3139 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3140 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3142 enum port port = encoder->port;
ba88d153 3143 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3144 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3145
ba88d153 3146 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3147 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3148
3149 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3150
93b662d3 3151 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3152 icl_disable_phy_clock_gating(dig_port);
3153
2dd24a9c 3154 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3155 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3156 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3157 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3158 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3159 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3160 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3161 else
7ea79333 3162 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3163
cb9ff519
ID		 3164 icl_enable_phy_clock_gating(dig_port);
3165
2f7460a7 3166 if (IS_GEN9_BC(dev_priv))
081dfcfa 3167 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3168
c7373764
ID		 3169 intel_ddi_enable_pipe_clock(crtc_state);
3170
790ea70c 3171 intel_dig_port->set_infoframes(encoder,
45e0327e 3172 crtc_state->has_infoframe,
f99be1b3 3173 crtc_state, conn_state);
ba88d153 3174}
32bdc400 3175
1524e93e 3176static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3177 const struct intel_crtc_state *crtc_state,
5f88a9c6 3178 const struct drm_connector_state *conn_state)
ba88d153 3179{
45e0327e
VS		 3180 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3182 enum pipe pipe = crtc->pipe;
30cf6db8 3183
1939ba51
VS		 3184 /*
3185 * When called from DP MST code:
3186 * - conn_state will be NULL
3187 * - encoder will be the main encoder (ie. mst->primary)
3188 * - the main connector associated with this port
3189 * won't be active or linked to a crtc
3190 * - crtc_state will be the state of the first stream to
3191 * be activated on this port, and it may not be the same
3192 * stream that will be deactivated last, but each stream
3193 * should have a state that is identical when it comes to
3194 * the DP link parameteres
3195 */
3196
45e0327e 3197 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3198
3b8c0d5b
JN		 3199 if (INTEL_GEN(dev_priv) >= 11)
3200 icl_map_plls_to_ports(encoder, crtc_state);
3201
364a3fe1
JN		 3202 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3203
06c812d7 3204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3205 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3206 } else {
3207 struct intel_lspcon *lspcon =
3208 enc_to_intel_lspcon(&encoder->base);
3209
45e0327e 3210 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3211 if (lspcon->active) {
3212 struct intel_digital_port *dig_port =
3213 enc_to_dig_port(&encoder->base);
3214
3215 dig_port->set_infoframes(encoder,
3216 crtc_state->has_infoframe,
3217 crtc_state, conn_state);
3218 }
3219 }
6441ab5f
PZ		 3220}
3221
d6a09cee
AS		 3222static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3223 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3224{
3225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3226 enum port port = encoder->port;
e725f645
VS		 3227 bool wait = false;
3228 u32 val;
3229
3230 val = I915_READ(DDI_BUF_CTL(port));
3231 if (val & DDI_BUF_CTL_ENABLE) {
3232 val &= ~DDI_BUF_CTL_ENABLE;
3233 I915_WRITE(DDI_BUF_CTL(port), val);
3234 wait = true;
3235 }
3236
3237 val = I915_READ(DP_TP_CTL(port));
3238 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3239 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3240 I915_WRITE(DP_TP_CTL(port), val);
3241
d6a09cee
AS		 3242 /* Disable FEC in DP Sink */
3243 intel_ddi_disable_fec_state(encoder, crtc_state);
3244
e725f645
VS		 3245 if (wait)
3246 intel_wait_ddi_buf_idle(dev_priv, port);
3247}
3248
f45f3da7
VS		 3249static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3250 const struct intel_crtc_state *old_crtc_state,
3251 const struct drm_connector_state *old_conn_state)
6441ab5f 3252{
f45f3da7
VS		 3253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3254 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3255 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3256 bool is_mst = intel_crtc_has_type(old_crtc_state,
3257 INTEL_OUTPUT_DP_MST);
2886e93f 3258
2b5cf4ef
ID		 3259 if (!is_mst) {
3260 intel_ddi_disable_pipe_clock(old_crtc_state);
3261 /*
3262 * Power down sink before disabling the port, otherwise we end
3263 * up getting interrupts from the sink on detecting link loss.
3264 */
be1c63c8 3265 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3266 }
c5f93fcf 3267
d6a09cee 3268 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3269
f45f3da7
VS		 3270 intel_edp_panel_vdd_on(intel_dp);
3271 intel_edp_panel_off(intel_dp);
a836bdf9 3272
0e6e0be4
CW		 3273 intel_display_power_put_unchecked(dev_priv,
3274 dig_port->ddi_io_power_domain);
c5f93fcf 3275
f45f3da7
VS		 3276 intel_ddi_clk_disable(encoder);
3277}
c5f93fcf 3278
f45f3da7
VS		 3279static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3280 const struct intel_crtc_state *old_crtc_state,
3281 const struct drm_connector_state *old_conn_state)
3282{
3283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3284 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3285 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3286
790ea70c 3287 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3288 old_crtc_state, old_conn_state);
3289
afb2c443
ID		 3290 intel_ddi_disable_pipe_clock(old_crtc_state);
3291
d6a09cee 3292 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3293
0e6e0be4
CW		 3294 intel_display_power_put_unchecked(dev_priv,
3295 dig_port->ddi_io_power_domain);
b2ccb822 3296
f45f3da7
VS		 3297 intel_ddi_clk_disable(encoder);
3298
3299 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3300}
3301
3302static void intel_ddi_post_disable(struct intel_encoder *encoder,
3303 const struct intel_crtc_state *old_crtc_state,
3304 const struct drm_connector_state *old_conn_state)
3305{
3b8c0d5b
JN		 3306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3307
f45f3da7 3308 /*
1939ba51
VS		 3309 * When called from DP MST code:
3310 * - old_conn_state will be NULL
3311 * - encoder will be the main encoder (ie. mst->primary)
3312 * - the main connector associated with this port
3313 * won't be active or linked to a crtc
3314 * - old_crtc_state will be the state of the last stream to
3315 * be deactivated on this port, and it may not be the same
3316 * stream that was activated last, but each stream
3317 * should have a state that is identical when it comes to
3318 * the DP link parameteres
f45f3da7 3319 */
1939ba51
VS		 3320
3321 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3322 intel_ddi_post_disable_hdmi(encoder,
3323 old_crtc_state, old_conn_state);
3324 else
3325 intel_ddi_post_disable_dp(encoder,
3326 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3327
3328 if (INTEL_GEN(dev_priv) >= 11)
3329 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3330}
3331
1524e93e 3332void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3333 const struct intel_crtc_state *old_crtc_state,
3334 const struct drm_connector_state *old_conn_state)
b7076546 3335{
1524e93e 3336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3337 u32 val;
b7076546
ML		 3338
3339 /*
3340 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3341 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3342 * step 13 is the correct place for it. Step 18 is where it was
3343 * originally before the BUN.
3344 */
3345 val = I915_READ(FDI_RX_CTL(PIPE_A));
3346 val &= ~FDI_RX_ENABLE;
3347 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3348
d6a09cee 3349 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3350 intel_ddi_clk_disable(encoder);
b7076546
ML		 3351
3352 val = I915_READ(FDI_RX_MISC(PIPE_A));
3353 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3354 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3355 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3356
3357 val = I915_READ(FDI_RX_CTL(PIPE_A));
3358 val &= ~FDI_PCDCLK;
3359 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3360
3361 val = I915_READ(FDI_RX_CTL(PIPE_A));
3362 val &= ~FDI_RX_PLL_ENABLE;
3363 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3364}
3365
15d05f0e
VS		 3366static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3367 const struct intel_crtc_state *crtc_state,
3368 const struct drm_connector_state *conn_state)
72662e10 3369{
15d05f0e
VS		 3370 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3371 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3372 enum port port = encoder->port;
72662e10 3373
15d05f0e
VS		 3374 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3375 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3376
15d05f0e
VS		 3377 intel_edp_backlight_on(crtc_state, conn_state);
3378 intel_psr_enable(intel_dp, crtc_state);
3379 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3380
15d05f0e
VS		 3381 if (crtc_state->has_audio)
3382 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3383}
3384
8f19b401
ID		 3385static i915_reg_t
3386gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3387 enum port port)
3388{
3389 static const i915_reg_t regs[] = {
3390 [PORT_A] = CHICKEN_TRANS_EDP,
3391 [PORT_B] = CHICKEN_TRANS_A,
3392 [PORT_C] = CHICKEN_TRANS_B,
3393 [PORT_D] = CHICKEN_TRANS_C,
3394 [PORT_E] = CHICKEN_TRANS_A,
3395 };
3396
3397 WARN_ON(INTEL_GEN(dev_priv) < 9);
3398
3399 if (WARN_ON(port < PORT_A || port > PORT_E))
3400 port = PORT_A;
3401
3402 return regs[port];
3403}
3404
15d05f0e
VS		 3405static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3406 const struct intel_crtc_state *crtc_state,
3407 const struct drm_connector_state *conn_state)
3408{
3409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3410 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3411 struct drm_connector *connector = conn_state->connector;
0fce04c8 3412 enum port port = encoder->port;
15d05f0e 3413
277ab5ab
VS		 3414 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3415 crtc_state->hdmi_high_tmds_clock_ratio,
3416 crtc_state->hdmi_scrambling))
3417 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3418 connector->base.id, connector->name);
15d05f0e 3419
0519c102
VS		 3420 /* Display WA #1143: skl,kbl,cfl */
3421 if (IS_GEN9_BC(dev_priv)) {
3422 /*
3423 * For some reason these chicken bits have been
3424 * stuffed into a transcoder register, event though
3425 * the bits affect a specific DDI port rather than
3426 * a specific transcoder.
3427 */
8f19b401 3428 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3429 u32 val;
3430
8f19b401 3431 val = I915_READ(reg);
0519c102
VS		 3432
3433 if (port == PORT_E)
3434 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3435 DDIE_TRAINING_OVERRIDE_VALUE;
3436 else
3437 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3438 DDI_TRAINING_OVERRIDE_VALUE;
3439
8f19b401
ID		 3440 I915_WRITE(reg, val);
3441 POSTING_READ(reg);
0519c102
VS		 3442
3443 udelay(1);
3444
3445 if (port == PORT_E)
3446 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3447 DDIE_TRAINING_OVERRIDE_VALUE);
3448 else
3449 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3450 DDI_TRAINING_OVERRIDE_VALUE);
3451
8f19b401 3452 I915_WRITE(reg, val);
0519c102
VS		 3453 }
3454
15d05f0e
VS		 3455 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3456 * are ignored so nothing special needs to be done besides
3457 * enabling the port.
3458 */
3459 I915_WRITE(DDI_BUF_CTL(port),
3460 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3461
15d05f0e
VS		 3462 if (crtc_state->has_audio)
3463 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3464}
3465
3466static void intel_enable_ddi(struct intel_encoder *encoder,
3467 const struct intel_crtc_state *crtc_state,
3468 const struct drm_connector_state *conn_state)
3469{
3470 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3471 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3472 else
3473 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3474
3475 /* Enable hdcp if it's desired */
3476 if (conn_state->content_protection ==
3477 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3478 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3479}
3480
33f083f0
VS		 3481static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3482 const struct intel_crtc_state *old_crtc_state,
3483 const struct drm_connector_state *old_conn_state)
5ab432ef 3484{
33f083f0 3485 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3486
edb2e530
VS		 3487 intel_dp->link_trained = false;
3488
37255d8d 3489 if (old_crtc_state->has_audio)
8ec47de2
VS		 3490 intel_audio_codec_disable(encoder,
3491 old_crtc_state, old_conn_state);
2831d842 3492
33f083f0
VS		 3493 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3494 intel_psr_disable(intel_dp, old_crtc_state);
3495 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3496 /* Disable the decompression in DP Sink */
3497 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3498 false);
33f083f0 3499}
15953637 3500
33f083f0
VS		 3501static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3502 const struct intel_crtc_state *old_crtc_state,
3503 const struct drm_connector_state *old_conn_state)
3504{
277ab5ab
VS		 3505 struct drm_connector *connector = old_conn_state->connector;
3506
33f083f0 3507 if (old_crtc_state->has_audio)
8ec47de2
VS		 3508 intel_audio_codec_disable(encoder,
3509 old_crtc_state, old_conn_state);
d6c50ff8 3510
277ab5ab
VS		 3511 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3512 false, false))
3513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3514 connector->base.id, connector->name);
33f083f0
VS		 3515}
3516
3517static void intel_disable_ddi(struct intel_encoder *encoder,
3518 const struct intel_crtc_state *old_crtc_state,
3519 const struct drm_connector_state *old_conn_state)
3520{
ee5e5e7a
SP		 3521 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3522
33f083f0
VS		 3523 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3524 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3525 else
3526 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3527}
79f689aa 3528
2ef82327
HG		 3529static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3530 const struct intel_crtc_state *crtc_state,
3531 const struct drm_connector_state *conn_state)
3532{
3533 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3534
5aa2c9ae
VS		 3535 intel_ddi_set_pipe_settings(crtc_state);
3536
23ec9f52 3537 intel_psr_update(intel_dp, crtc_state);
2ef82327 3538 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3539
3540 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3541}
3542
3543static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3544 const struct intel_crtc_state *crtc_state,
3545 const struct drm_connector_state *conn_state)
3546{
3547 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3548 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1
R		 3549
3550 if (conn_state->content_protection ==
3551 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3552 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3553 else if (conn_state->content_protection ==
3554 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3555 intel_hdcp_disable(to_intel_connector(conn_state->connector));
2ef82327
HG		 3556}
3557
03ad7d88
MN		 3558static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3559 const struct intel_crtc_state *pipe_config,
3560 enum port port)
3561{
3562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3563 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3564 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3565 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3566 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3567
3568 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3569 switch (pipe_config->lane_count) {
3570 case 1:
3571 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3572 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3573 break;
3574 case 2:
3575 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3576 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3577 break;
3578 case 4:
3579 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3580 break;
3581 default:
3582 MISSING_CASE(pipe_config->lane_count);
3583 }
3584 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3585}
3586
bdaa29b6
ID		 3587static void
3588intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3589 const struct intel_crtc_state *crtc_state,
3590 const struct drm_connector_state *conn_state)
03ad7d88 3591{
bdaa29b6 3592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3593 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bdaa29b6
ID		 3594 enum port port = encoder->port;
3595
8e4a3ad9
ID		 3596 if (intel_crtc_has_dp_encoder(crtc_state) ||
3597 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6
ID		 3598 intel_display_power_get(dev_priv,
3599 intel_ddi_main_link_aux_domain(dig_port));
3600
3601 if (IS_GEN9_LP(dev_priv))
3602 bxt_ddi_phy_set_lane_optim_mask(encoder,
3603 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3604
3605 /*
3606 * Program the lane count for static/dynamic connections on Type-C ports.
3607 * Skip this step for TBT.
3608 */
3609 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3610 dig_port->tc_type == TC_PORT_TBT)
3611 return;
3612
bdaa29b6
ID		 3613 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3614}
3615
3616static void
3617intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3618 const struct intel_crtc_state *crtc_state,
3619 const struct drm_connector_state *conn_state)
3620{
3621 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3622 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3623
3624 if (intel_crtc_has_dp_encoder(crtc_state) ||
3625 intel_port_is_tc(dev_priv, encoder->port))
0e6e0be4
CW		 3626 intel_display_power_put_unchecked(dev_priv,
3627 intel_ddi_main_link_aux_domain(dig_port));
03ad7d88
MN		 3628}
3629
ad64217b 3630void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3631{
ad64217b
ACO		 3632 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3633 struct drm_i915_private *dev_priv =
3634 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3635 enum port port = intel_dig_port->base.port;
3d0c5005 3636 u32 val;
f3e227df 3637 bool wait = false;
c19b0669
PZ		 3638
3639 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3640 val = I915_READ(DDI_BUF_CTL(port));
3641 if (val & DDI_BUF_CTL_ENABLE) {
3642 val &= ~DDI_BUF_CTL_ENABLE;
3643 I915_WRITE(DDI_BUF_CTL(port), val);
3644 wait = true;
3645 }
3646
3647 val = I915_READ(DP_TP_CTL(port));
3648 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3649 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3650 I915_WRITE(DP_TP_CTL(port), val);
3651 POSTING_READ(DP_TP_CTL(port));
3652
3653 if (wait)
3654 intel_wait_ddi_buf_idle(dev_priv, port);
3655 }
3656
0e32b39c 3657 val = DP_TP_CTL_ENABLE |
c19b0669 3658 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3659 if (intel_dp->link_mst)
0e32b39c
DA		 3660 val |= DP_TP_CTL_MODE_MST;
3661 else {
3662 val |= DP_TP_CTL_MODE_SST;
3663 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3664 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3665 }
c19b0669
PZ		 3666 I915_WRITE(DP_TP_CTL(port), val);
3667 POSTING_READ(DP_TP_CTL(port));
3668
3669 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3670 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3671 POSTING_READ(DDI_BUF_CTL(port));
3672
3673 udelay(600);
3674}
00c09d70 3675
2085cc5d
VS		 3676static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3677 enum transcoder cpu_transcoder)
9935f7fa 3678{
2085cc5d
VS		 3679 if (cpu_transcoder == TRANSCODER_EDP)
3680 return false;
9935f7fa 3681
2085cc5d
VS		 3682 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3683 return false;
3684
3685 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3686 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3687}
3688
53e9bf5e
VS		 3689void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3690 struct intel_crtc_state *crtc_state)
3691{
2dd24a9c 3692 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3693 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3694 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3695 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3696}
3697
6801c18c 3698void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3699 struct intel_crtc_state *pipe_config)
045ac3b5 3700{
fac5e23e 3701 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3702 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3703 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3704 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3705 u32 temp, flags = 0;
3706
4d1de975
JN		 3707 /* XXX: DSI transcoder paranoia */
3708 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3709 return;
3710
045ac3b5
JB		 3711 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3712 if (temp & TRANS_DDI_PHSYNC)
3713 flags |= DRM_MODE_FLAG_PHSYNC;
3714 else
3715 flags |= DRM_MODE_FLAG_NHSYNC;
3716 if (temp & TRANS_DDI_PVSYNC)
3717 flags |= DRM_MODE_FLAG_PVSYNC;
3718 else
3719 flags |= DRM_MODE_FLAG_NVSYNC;
3720
2d112de7 3721 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3722
3723 switch (temp & TRANS_DDI_BPC_MASK) {
3724 case TRANS_DDI_BPC_6:
3725 pipe_config->pipe_bpp = 18;
3726 break;
3727 case TRANS_DDI_BPC_8:
3728 pipe_config->pipe_bpp = 24;
3729 break;
3730 case TRANS_DDI_BPC_10:
3731 pipe_config->pipe_bpp = 30;
3732 break;
3733 case TRANS_DDI_BPC_12:
3734 pipe_config->pipe_bpp = 36;
3735 break;
3736 default:
3737 break;
3738 }
eb14cb74
VS		 3739
3740 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3741 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3742 pipe_config->has_hdmi_sink = true;
f99be1b3 3743 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3744
e5e70d4a
VS		 3745 pipe_config->infoframes.enable |=
3746 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3747
3748 if (pipe_config->infoframes.enable)
bbd440fb 3749 pipe_config->has_infoframe = true;
15953637 3750
ab2cb2cb 3751 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 3752 pipe_config->hdmi_scrambling = true;
3753 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3754 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3755 /* fall through */
eb14cb74 3756 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3757 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3758 pipe_config->lane_count = 4;
3759 break;
eb14cb74 3760 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3761 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3762 break;
3763 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3764 if (encoder->type == INTEL_OUTPUT_EDP)
3765 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3766 else
3767 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3768 pipe_config->lane_count =
3769 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3770 intel_dp_get_m_n(intel_crtc, pipe_config);
3771 break;
eb14cb74 3772 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3773 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3774 pipe_config->lane_count =
3775 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3776 intel_dp_get_m_n(intel_crtc, pipe_config);
3777 break;
3778 default:
3779 break;
3780 }
10214420 3781
9935f7fa 3782 pipe_config->has_audio =
2085cc5d 3783 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3784
6aa23e65
JN		 3785 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3786 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3787 /*
3788 * This is a big fat ugly hack.
3789 *
3790 * Some machines in UEFI boot mode provide us a VBT that has 18
3791 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3792 * unknown we fail to light up. Yet the same BIOS boots up with
3793 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3794 * max, not what it tells us to use.
3795 *
3796 * Note: This will still be broken if the eDP panel is not lit
3797 * up by the BIOS, and thus we can't get the mode at module
3798 * load.
3799 */
3800 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3801 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3802 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3803 }
11578553 3804
22606a18 3805 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3806
cc3f90f0 3807 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3808 pipe_config->lane_lat_optim_mask =
3809 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3810
3811 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 3812
3813 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3814
3815 intel_read_infoframe(encoder, pipe_config,
3816 HDMI_INFOFRAME_TYPE_AVI,
3817 &pipe_config->infoframes.avi);
3818 intel_read_infoframe(encoder, pipe_config,
3819 HDMI_INFOFRAME_TYPE_SPD,
3820 &pipe_config->infoframes.spd);
3821 intel_read_infoframe(encoder, pipe_config,
3822 HDMI_INFOFRAME_TYPE_VENDOR,
3823 &pipe_config->infoframes.hdmi);
045ac3b5
JB		 3824}
3825
7e732cac
VS		 3826static enum intel_output_type
3827intel_ddi_compute_output_type(struct intel_encoder *encoder,
3828 struct intel_crtc_state *crtc_state,
3829 struct drm_connector_state *conn_state)
3830{
3831 switch (conn_state->connector->connector_type) {
3832 case DRM_MODE_CONNECTOR_HDMIA:
3833 return INTEL_OUTPUT_HDMI;
3834 case DRM_MODE_CONNECTOR_eDP:
3835 return INTEL_OUTPUT_EDP;
3836 case DRM_MODE_CONNECTOR_DisplayPort:
3837 return INTEL_OUTPUT_DP;
3838 default:
3839 MISSING_CASE(conn_state->connector->connector_type);
3840 return INTEL_OUTPUT_UNUSED;
3841 }
3842}
3843
204474a6
LP		 3844static int intel_ddi_compute_config(struct intel_encoder *encoder,
3845 struct intel_crtc_state *pipe_config,
3846 struct drm_connector_state *conn_state)
00c09d70 3847{
fac5e23e 3848 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3849 enum port port = encoder->port;
95a7a2ae 3850 int ret;
00c09d70 3851
bc7e3525 3852 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 3853 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3854
7e732cac 3855 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3856 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3857 else
0a478c27 3858 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
7a412b8f
VS		 3859 if (ret)
3860 return ret;
95a7a2ae 3861
7a412b8f 3862 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3863 pipe_config->lane_lat_optim_mask =
5161d058 3864 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3865
53e9bf5e
VS		 3866 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3867
7a412b8f 3868 return 0;
95a7a2ae 3869
00c09d70
PZ		 3870}
3871
f6bff60e
ID		 3872static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3873{
3874 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3875 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3876
3877 intel_dp_encoder_suspend(encoder);
3878
3879 /*
3880 * TODO: disconnect also from USB DP alternate mode once we have a
3881 * way to handle the modeset restore in that mode during resume
3882 * even if the sink has disappeared while being suspended.
3883 */
3884 if (dig_port->tc_legacy_port)
3885 icl_tc_phy_disconnect(i915, dig_port);
3886}
3887
3888static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3889{
3890 struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3891 struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3892
3893 if (intel_port_is_tc(i915, dig_port->base.port))
3894 intel_digital_port_connected(&dig_port->base);
3895
3896 intel_dp_encoder_reset(drm_encoder);
3897}
3898
3899static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3900{
3901 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3902 struct drm_i915_private *i915 = to_i915(encoder->dev);
3903
3904 intel_dp_encoder_flush_work(encoder);
3905
3906 if (intel_port_is_tc(i915, dig_port->base.port))
3907 icl_tc_phy_disconnect(i915, dig_port);
3908
3909 drm_encoder_cleanup(encoder);
3910 kfree(dig_port);
3911}
3912
00c09d70 3913static const struct drm_encoder_funcs intel_ddi_funcs = {
f6bff60e
ID		 3914 .reset = intel_ddi_encoder_reset,
3915 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 3916};
3917
4a28ae58
PZ		 3918static struct intel_connector *
3919intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3920{
3921 struct intel_connector *connector;
8f4f2797 3922 enum port port = intel_dig_port->base.port;
4a28ae58 3923
9bdbd0b9 3924 connector = intel_connector_alloc();
4a28ae58
PZ		 3925 if (!connector)
3926 return NULL;
3927
3928 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3929 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3930 kfree(connector);
3931 return NULL;
3932 }
3933
3934 return connector;
3935}
3936
dba14b27
VS		 3937static int modeset_pipe(struct drm_crtc *crtc,
3938 struct drm_modeset_acquire_ctx *ctx)
3939{
3940 struct drm_atomic_state *state;
3941 struct drm_crtc_state *crtc_state;
3942 int ret;
3943
3944 state = drm_atomic_state_alloc(crtc->dev);
3945 if (!state)
3946 return -ENOMEM;
3947
3948 state->acquire_ctx = ctx;
3949
3950 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3951 if (IS_ERR(crtc_state)) {
3952 ret = PTR_ERR(crtc_state);
3953 goto out;
3954 }
3955
b8fe992a 3956 crtc_state->connectors_changed = true;
dba14b27 3957
dba14b27 3958 ret = drm_atomic_commit(state);
a551cd66 3959out:
dba14b27
VS		 3960 drm_atomic_state_put(state);
3961
3962 return ret;
3963}
3964
3965static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3966 struct drm_modeset_acquire_ctx *ctx)
3967{
3968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3969 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3970 struct intel_connector *connector = hdmi->attached_connector;
3971 struct i2c_adapter *adapter =
3972 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3973 struct drm_connector_state *conn_state;
3974 struct intel_crtc_state *crtc_state;
3975 struct intel_crtc *crtc;
3976 u8 config;
3977 int ret;
3978
3979 if (!connector || connector->base.status != connector_status_connected)
3980 return 0;
3981
3982 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3983 ctx);
3984 if (ret)
3985 return ret;
3986
3987 conn_state = connector->base.state;
3988
3989 crtc = to_intel_crtc(conn_state->crtc);
3990 if (!crtc)
3991 return 0;
3992
3993 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3994 if (ret)
3995 return ret;
3996
3997 crtc_state = to_intel_crtc_state(crtc->base.state);
3998
3999 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4000
4001 if (!crtc_state->base.active)
4002 return 0;
4003
4004 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4005 !crtc_state->hdmi_scrambling)
4006 return 0;
4007
4008 if (conn_state->commit &&
4009 !try_wait_for_completion(&conn_state->commit->hw_done))
4010 return 0;
4011
4012 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4013 if (ret < 0) {
4014 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4015 return 0;
4016 }
4017
4018 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4019 crtc_state->hdmi_high_tmds_clock_ratio &&
4020 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4021 crtc_state->hdmi_scrambling)
4022 return 0;
4023
4024 /*
4025 * HDMI 2.0 says that one should not send scrambled data
4026 * prior to configuring the sink scrambling, and that
4027 * TMDS clock/data transmission should be suspended when
4028 * changing the TMDS clock rate in the sink. So let's
4029 * just do a full modeset here, even though some sinks
4030 * would be perfectly happy if were to just reconfigure
4031 * the SCDC settings on the fly.
4032 */
4033 return modeset_pipe(&crtc->base, ctx);
4034}
4035
4036static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4037 struct intel_connector *connector)
4038{
4039 struct drm_modeset_acquire_ctx ctx;
4040 bool changed;
4041 int ret;
4042
4043 changed = intel_encoder_hotplug(encoder, connector);
4044
4045 drm_modeset_acquire_init(&ctx, 0);
4046
4047 for (;;) {
c85d200e
VS		 4048 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4049 ret = intel_hdmi_reset_link(encoder, &ctx);
4050 else
4051 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4052
4053 if (ret == -EDEADLK) {
4054 drm_modeset_backoff(&ctx);
4055 continue;
4056 }
4057
4058 break;
4059 }
4060
4061 drm_modeset_drop_locks(&ctx);
4062 drm_modeset_acquire_fini(&ctx);
4063 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4064
4065 return changed;
4066}
4067
4a28ae58
PZ		 4068static struct intel_connector *
4069intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4070{
4071 struct intel_connector *connector;
8f4f2797 4072 enum port port = intel_dig_port->base.port;
4a28ae58 4073
9bdbd0b9 4074 connector = intel_connector_alloc();
4a28ae58
PZ		 4075 if (!connector)
4076 return NULL;
4077
4078 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4079 intel_hdmi_init_connector(intel_dig_port, connector);
4080
4081 return connector;
4082}
4083
436009b5
RV		 4084static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4085{
4086 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4087
8f4f2797 4088 if (dport->base.port != PORT_A)
436009b5
RV		 4089 return false;
4090
4091 if (dport->saved_port_bits & DDI_A_4_LANES)
4092 return false;
4093
4094 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4095 * supported configuration
4096 */
4097 if (IS_GEN9_LP(dev_priv))
4098 return true;
4099
4100 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4101 * one who does also have a full A/E split called
4102 * DDI_F what makes DDI_E useless. However for this
4103 * case let's trust VBT info.
4104 */
4105 if (IS_CANNONLAKE(dev_priv) &&
4106 !intel_bios_is_port_present(dev_priv, PORT_E))
4107 return true;
4108
4109 return false;
4110}
4111
3d2011cf
MK		 4112static int
4113intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4114{
4115 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4116 enum port port = intel_dport->base.port;
4117 int max_lanes = 4;
4118
4119 if (INTEL_GEN(dev_priv) >= 11)
4120 return max_lanes;
4121
4122 if (port == PORT_A || port == PORT_E) {
4123 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4124 max_lanes = port == PORT_A ? 4 : 0;
4125 else
4126 /* Both A and E share 2 lanes */
4127 max_lanes = 2;
4128 }
4129
4130 /*
4131 * Some BIOS might fail to set this bit on port A if eDP
4132 * wasn't lit up at boot. Force this bit set when needed
4133 * so we use the proper lane count for our calculations.
4134 */
4135 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4136 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4137 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4138 max_lanes = 4;
4139 }
4140
4141 return max_lanes;
4142}
4143
c39055b0 4144void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4145{
f6bff60e
ID		 4146 struct ddi_vbt_port_info *port_info =
4147 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4148 struct intel_digital_port *intel_dig_port;
4149 struct intel_encoder *intel_encoder;
4150 struct drm_encoder *encoder;
ff662124 4151 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4152 enum pipe pipe;
10e7bec3 4153
f6bff60e
ID		 4154 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4155 init_dp = port_info->supports_dp;
ff662124
SS		 4156
4157 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4158 /*
4159 * Lspcon device needs to be driven with DP connector
4160 * with special detection sequence. So make sure DP
4161 * is initialized before lspcon.
4162 */
4163 init_dp = true;
4164 init_lspcon = true;
4165 init_hdmi = false;
4166 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4167 }
4168
311a2094 4169 if (!init_dp && !init_hdmi) {
500ea70d 4170 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4171 port_name(port));
500ea70d 4172 return;
311a2094 4173 }
00c09d70 4174
b14c5679 4175 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4176 if (!intel_dig_port)
4177 return;
4178
00c09d70
PZ		 4179 intel_encoder = &intel_dig_port->base;
4180 encoder = &intel_encoder->base;
4181
c39055b0 4182 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4183 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4184
c85d200e 4185 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4186 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4187 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4188 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4189 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4190 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4191 intel_encoder->pre_enable = intel_ddi_pre_enable;
4192 intel_encoder->disable = intel_disable_ddi;
4193 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4194 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4195 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4196 intel_encoder->get_config = intel_ddi_get_config;
f6bff60e 4197 intel_encoder->suspend = intel_ddi_encoder_suspend;
62b69566 4198 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4199 intel_encoder->type = INTEL_OUTPUT_DDI;
4200 intel_encoder->power_domain = intel_port_to_power_domain(port);
4201 intel_encoder->port = port;
3d2011cf 4202 intel_encoder->cloneable = 0;
570b16b5
MK		 4203 for_each_pipe(dev_priv, pipe)
4204 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4205
1e6aa7e5
JN		 4206 if (INTEL_GEN(dev_priv) >= 11)
4207 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4208 DDI_BUF_PORT_REVERSAL;
4209 else
4210 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4211 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4212 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4213 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4214 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4215
f6bff60e
ID		 4216 intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4217 !port_info->supports_typec_usb &&
4218 !port_info->supports_tbt;
4219
62b69566
ACO		 4220 switch (port) {
4221 case PORT_A:
4222 intel_dig_port->ddi_io_power_domain =
4223 POWER_DOMAIN_PORT_DDI_A_IO;
4224 break;
4225 case PORT_B:
4226 intel_dig_port->ddi_io_power_domain =
4227 POWER_DOMAIN_PORT_DDI_B_IO;
4228 break;
4229 case PORT_C:
4230 intel_dig_port->ddi_io_power_domain =
4231 POWER_DOMAIN_PORT_DDI_C_IO;
4232 break;
4233 case PORT_D:
4234 intel_dig_port->ddi_io_power_domain =
4235 POWER_DOMAIN_PORT_DDI_D_IO;
4236 break;
4237 case PORT_E:
4238 intel_dig_port->ddi_io_power_domain =
4239 POWER_DOMAIN_PORT_DDI_E_IO;
4240 break;
9787e835
RV		 4241 case PORT_F:
4242 intel_dig_port->ddi_io_power_domain =
4243 POWER_DOMAIN_PORT_DDI_F_IO;
4244 break;
62b69566
ACO		 4245 default:
4246 MISSING_CASE(port);
4247 }
4248
f68d697e
CW		 4249 if (init_dp) {
4250 if (!intel_ddi_init_dp_connector(intel_dig_port))
4251 goto err;
13cf5504 4252
f68d697e 4253 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4254 }
21a8e6a4 4255
311a2094
PZ		 4256 /* In theory we don't need the encoder->type check, but leave it just in
4257 * case we have some really bad VBTs... */
f68d697e
CW		 4258 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4259 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4260 goto err;
21a8e6a4 4261 }
f68d697e 4262
ff662124
SS		 4263 if (init_lspcon) {
4264 if (lspcon_init(intel_dig_port))
4265 /* TODO: handle hdmi info frame part */
4266 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4267 port_name(port));
4268 else
4269 /*
4270 * LSPCON init faied, but DP init was success, so
4271 * lets try to drive as DP++ port.
4272 */
4273 DRM_ERROR("LSPCON init failed on port %c\n",
4274 port_name(port));
4275 }
4276
06c812d7 4277 intel_infoframe_init(intel_dig_port);
f6bff60e
ID		 4278
4279 if (intel_port_is_tc(dev_priv, port))
4280 intel_digital_port_connected(intel_encoder);
4281
f68d697e
CW		 4282 return;
4283
4284err:
4285 drm_encoder_cleanup(encoder);
4286 kfree(intel_dig_port);
00c09d70 4287}
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