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drm/i915/cdclk: have only one init/uninit function
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
ec7f29ff 32#include "intel_connector.h"
fdc24cf3 33#include "intel_ddi.h"
27fec1f9 34#include "intel_dp.h"
45244b87 35#include "intel_drv.h"
1dd07e56 36#include "intel_dsi.h"
408bd917 37#include "intel_hdcp.h"
0550691d 38#include "intel_hdmi.h"
f3e18947 39#include "intel_lspcon.h"
44c1220a 40#include "intel_panel.h"
55367a27 41#include "intel_psr.h"
45244b87 42
10122051
JN		 43struct ddi_buf_trans {
44 u32 trans1; /* balance leg enable, de-emph level */
45 u32 trans2; /* vref sel, vswing */
f8896f5d 46 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 47};
48
97eeb872
VS		 49static const u8 index_to_dp_signal_levels[] = {
50 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
51 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
52 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
53 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
54 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
55 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
56 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
57 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
58 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
59 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
60};
61
45244b87
ED		 62/* HDMI/DVI modes ignore everything but the last 2 items. So we share
63 * them for both DP and FDI transports, allowing those ports to
64 * automatically adapt to HDMI connections as well
65 */
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },
68 { 0x00D75FFF, 0x0005000A, 0x0 },
69 { 0x00C30FFF, 0x00040006, 0x0 },
70 { 0x80AAAFFF, 0x000B0000, 0x0 },
71 { 0x00FFFFFF, 0x0005000A, 0x0 },
72 { 0x00D75FFF, 0x000C0004, 0x0 },
73 { 0x80C30FFF, 0x000B0000, 0x0 },
74 { 0x00FFFFFF, 0x00040006, 0x0 },
75 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 76};
77
10122051 78static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 79 { 0x00FFFFFF, 0x0007000E, 0x0 },
80 { 0x00D75FFF, 0x000F000A, 0x0 },
81 { 0x00C30FFF, 0x00060006, 0x0 },
82 { 0x00AAAFFF, 0x001E0000, 0x0 },
83 { 0x00FFFFFF, 0x000F000A, 0x0 },
84 { 0x00D75FFF, 0x00160004, 0x0 },
85 { 0x00C30FFF, 0x001E0000, 0x0 },
86 { 0x00FFFFFF, 0x00060006, 0x0 },
87 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 88};
89
10122051
JN		 90static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
91 /* Idx NT mV d T mV d db */
f8896f5d
DW		 92 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
93 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
94 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
95 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
96 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
97 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
98 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
99 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
100 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
101 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
102 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
103 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x00000012, 0x0 },
108 { 0x00EBAFFF, 0x00020011, 0x0 },
109 { 0x00C71FFF, 0x0006000F, 0x0 },
110 { 0x00AAAFFF, 0x000E000A, 0x0 },
111 { 0x00FFFFFF, 0x00020011, 0x0 },
112 { 0x00DB6FFF, 0x0005000F, 0x0 },
113 { 0x00BEEFFF, 0x000A000C, 0x0 },
114 { 0x00FFFFFF, 0x0005000F, 0x0 },
115 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },
120 { 0x00D75FFF, 0x000E000A, 0x0 },
121 { 0x00BEFFFF, 0x00140006, 0x0 },
122 { 0x80B2CFFF, 0x001B0002, 0x0 },
123 { 0x00FFFFFF, 0x000E000A, 0x0 },
124 { 0x00DB6FFF, 0x00160005, 0x0 },
125 { 0x80C71FFF, 0x001A0002, 0x0 },
126 { 0x00F7DFFF, 0x00180004, 0x0 },
127 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 128};
129
10122051 130static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 131 { 0x00FFFFFF, 0x0001000E, 0x0 },
132 { 0x00D75FFF, 0x0004000A, 0x0 },
133 { 0x00C30FFF, 0x00070006, 0x0 },
134 { 0x00AAAFFF, 0x000C0000, 0x0 },
135 { 0x00FFFFFF, 0x0004000A, 0x0 },
136 { 0x00D75FFF, 0x00090004, 0x0 },
137 { 0x00C30FFF, 0x000C0000, 0x0 },
138 { 0x00FFFFFF, 0x00070006, 0x0 },
139 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 140};
141
10122051
JN		 142static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
143 /* Idx NT mV d T mV df db */
f8896f5d
DW		 144 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
145 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
146 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
147 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
148 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
149 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
150 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
151 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
152 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
153 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 154};
155
5f8b2531 156/* Skylake H and S */
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 158 { 0x00002016, 0x000000A0, 0x0 },
159 { 0x00005012, 0x0000009B, 0x0 },
160 { 0x00007011, 0x00000088, 0x0 },
d7097cff 161 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 162 { 0x00002016, 0x0000009B, 0x0 },
163 { 0x00005012, 0x00000088, 0x0 },
d7097cff 164 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 165 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 166 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 167};
168
f8896f5d
DW		 169/* Skylake U */
170static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 171 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 172 { 0x00005012, 0x00000088, 0x0 },
5ac90567 173 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 174 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 175 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 176 { 0x80005012, 0x000000C0, 0x1 },
177 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 178 { 0x00002016, 0x00000088, 0x0 },
d7097cff 179 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 180};
181
5f8b2531
RV		 182/* Skylake Y */
183static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 184 { 0x00000018, 0x000000A2, 0x0 },
185 { 0x00005012, 0x00000088, 0x0 },
5ac90567 186 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 187 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 188 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 189 { 0x80005012, 0x000000C0, 0x3 },
190 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 191 { 0x00000018, 0x00000088, 0x0 },
d7097cff 192 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 193};
194
0fdd4918
RV		 195/* Kabylake H and S */
196static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
197 { 0x00002016, 0x000000A0, 0x0 },
198 { 0x00005012, 0x0000009B, 0x0 },
199 { 0x00007011, 0x00000088, 0x0 },
200 { 0x80009010, 0x000000C0, 0x1 },
201 { 0x00002016, 0x0000009B, 0x0 },
202 { 0x00005012, 0x00000088, 0x0 },
203 { 0x80007011, 0x000000C0, 0x1 },
204 { 0x00002016, 0x00000097, 0x0 },
205 { 0x80005012, 0x000000C0, 0x1 },
206};
207
208/* Kabylake U */
209static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
210 { 0x0000201B, 0x000000A1, 0x0 },
211 { 0x00005012, 0x00000088, 0x0 },
212 { 0x80007011, 0x000000CD, 0x3 },
213 { 0x80009010, 0x000000C0, 0x3 },
214 { 0x0000201B, 0x0000009D, 0x0 },
215 { 0x80005012, 0x000000C0, 0x3 },
216 { 0x80007011, 0x000000C0, 0x3 },
217 { 0x00002016, 0x0000004F, 0x0 },
218 { 0x80005012, 0x000000C0, 0x3 },
219};
220
221/* Kabylake Y */
222static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
223 { 0x00001017, 0x000000A1, 0x0 },
224 { 0x00005012, 0x00000088, 0x0 },
225 { 0x80007011, 0x000000CD, 0x3 },
226 { 0x8000800F, 0x000000C0, 0x3 },
227 { 0x00001017, 0x0000009D, 0x0 },
228 { 0x80005012, 0x000000C0, 0x3 },
229 { 0x80007011, 0x000000C0, 0x3 },
230 { 0x00001017, 0x0000004C, 0x0 },
231 { 0x80005012, 0x000000C0, 0x3 },
232};
233
f8896f5d 234/*
0fdd4918 235 * Skylake/Kabylake H and S
f8896f5d
DW		 236 * eDP 1.4 low vswing translation parameters
237 */
7ad14a29 238static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 239 { 0x00000018, 0x000000A8, 0x0 },
240 { 0x00004013, 0x000000A9, 0x0 },
241 { 0x00007011, 0x000000A2, 0x0 },
242 { 0x00009010, 0x0000009C, 0x0 },
243 { 0x00000018, 0x000000A9, 0x0 },
244 { 0x00006013, 0x000000A2, 0x0 },
245 { 0x00007011, 0x000000A6, 0x0 },
246 { 0x00000018, 0x000000AB, 0x0 },
247 { 0x00007013, 0x0000009F, 0x0 },
248 { 0x00000018, 0x000000DF, 0x0 },
249};
250
251/*
0fdd4918 252 * Skylake/Kabylake U
f8896f5d
DW		 253 * eDP 1.4 low vswing translation parameters
254 */
255static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
256 { 0x00000018, 0x000000A8, 0x0 },
257 { 0x00004013, 0x000000A9, 0x0 },
258 { 0x00007011, 0x000000A2, 0x0 },
259 { 0x00009010, 0x0000009C, 0x0 },
260 { 0x00000018, 0x000000A9, 0x0 },
261 { 0x00006013, 0x000000A2, 0x0 },
262 { 0x00007011, 0x000000A6, 0x0 },
263 { 0x00002016, 0x000000AB, 0x0 },
264 { 0x00005013, 0x0000009F, 0x0 },
265 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 266};
267
f8896f5d 268/*
0fdd4918 269 * Skylake/Kabylake Y
f8896f5d
DW		 270 * eDP 1.4 low vswing translation parameters
271 */
5f8b2531 272static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 273 { 0x00000018, 0x000000A8, 0x0 },
274 { 0x00004013, 0x000000AB, 0x0 },
275 { 0x00007011, 0x000000A4, 0x0 },
276 { 0x00009010, 0x000000DF, 0x0 },
277 { 0x00000018, 0x000000AA, 0x0 },
278 { 0x00006013, 0x000000A4, 0x0 },
279 { 0x00007011, 0x0000009D, 0x0 },
280 { 0x00000018, 0x000000A0, 0x0 },
281 { 0x00006012, 0x000000DF, 0x0 },
282 { 0x00000018, 0x0000008A, 0x0 },
283};
7ad14a29 284
0fdd4918 285/* Skylake/Kabylake U, H and S */
7f88e3af 286static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 287 { 0x00000018, 0x000000AC, 0x0 },
288 { 0x00005012, 0x0000009D, 0x0 },
289 { 0x00007011, 0x00000088, 0x0 },
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00000018, 0x00000098, 0x0 },
292 { 0x00004013, 0x00000088, 0x0 },
2e78416e 293 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 294 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 295 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
296 { 0x80003015, 0x000000C0, 0x1 },
297 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 298};
299
0fdd4918 300/* Skylake/Kabylake Y */
5f8b2531 301static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 302 { 0x00000018, 0x000000A1, 0x0 },
303 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 304 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 305 { 0x00000018, 0x000000A4, 0x0 },
306 { 0x00000018, 0x0000009D, 0x0 },
307 { 0x00004013, 0x00000080, 0x0 },
2e78416e 308 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 309 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 310 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
311 { 0x80003015, 0x000000C0, 0x3 },
312 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 313};
314
96fb9f9b 315struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 316 u8 margin; /* swing value */
317 u8 scale; /* scale value */
318 u8 enable; /* scale enable */
319 u8 deemphasis;
96fb9f9b
VK		 320};
321
96fb9f9b
VK		 322static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
323 /* Idx NT mV diff db */
043eaf36
VS		 324 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
325 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
326 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
327 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
328 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
329 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
330 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
331 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
332 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
333 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 334};
335
d9d7000d
SJ		 336static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
337 /* Idx NT mV diff db */
043eaf36
VS		 338 { 26, 0, 0, 128, }, /* 0: 200 0 */
339 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
340 { 48, 0, 0, 96, }, /* 2: 200 4 */
341 { 54, 0, 0, 69, }, /* 3: 200 6 */
342 { 32, 0, 0, 128, }, /* 4: 250 0 */
343 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
344 { 54, 0, 0, 85, }, /* 6: 250 4 */
345 { 43, 0, 0, 128, }, /* 7: 300 0 */
346 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
347 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 348};
349
96fb9f9b
VK		 350/* BSpec has 2 recommended values - entries 0 and 8.
351 * Using the entry with higher vswing.
352 */
353static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
354 /* Idx NT mV diff db */
043eaf36
VS		 355 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
356 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
357 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
358 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
359 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
360 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
361 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
362 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
363 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
364 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 365};
366
83fb7ab4 367struct cnl_ddi_buf_trans {
fb5f4e96
VS		 368 u8 dw2_swing_sel;
369 u8 dw7_n_scalar;
370 u8 dw4_cursor_coeff;
371 u8 dw4_post_cursor_2;
372 u8 dw4_post_cursor_1;
83fb7ab4
RV		 373};
374
375/* Voltage Swing Programming for VccIO 0.85V for DP */
376static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
377 /* NT mV Trans mV db */
378 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
379 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
380 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
381 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
382 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
383 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
384 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
385 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
386 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
387 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
388};
389
390/* Voltage Swing Programming for VccIO 0.85V for HDMI */
391static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
394 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
395 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
396 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
397 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
398 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
399 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
400};
401
402/* Voltage Swing Programming for VccIO 0.85V for eDP */
403static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
404 /* NT mV Trans mV db */
405 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
406 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
407 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
408 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
409 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
410 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
411 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
412 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
413 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
414};
415
416/* Voltage Swing Programming for VccIO 0.95V for DP */
417static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
418 /* NT mV Trans mV db */
419 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
420 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
421 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
422 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
423 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
424 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
425 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
426 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
427 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
428 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
429};
430
431/* Voltage Swing Programming for VccIO 0.95V for HDMI */
432static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
433 /* NT mV Trans mV db */
434 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
435 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
436 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
437 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
438 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
439 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
440 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
441 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
442 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
443 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
444 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
445};
446
447/* Voltage Swing Programming for VccIO 0.95V for eDP */
448static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
449 /* NT mV Trans mV db */
450 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
451 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
452 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
453 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
454 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
455 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
456 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
457 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
458 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
459 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
460};
461
462/* Voltage Swing Programming for VccIO 1.05V for DP */
463static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
464 /* NT mV Trans mV db */
465 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
466 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
467 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
468 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
469 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
470 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
471 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
472 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
473 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
474 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
475};
476
477/* Voltage Swing Programming for VccIO 1.05V for HDMI */
478static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
479 /* NT mV Trans mV db */
480 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
481 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
482 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
483 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
484 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
485 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
486 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
487 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
488 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
489 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
490 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
491};
492
493/* Voltage Swing Programming for VccIO 1.05V for eDP */
494static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
495 /* NT mV Trans mV db */
496 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
497 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
498 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
499 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
500 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
501 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
502 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
503 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
504 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
505};
506
b265a2a6
CT		 507/* icl_combo_phy_ddi_translations */
508static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
509 /* NT mV Trans mV db */
510 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
511 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
512 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
513 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
514 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
515 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
516 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
517 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
518 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
519 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 520};
521
b265a2a6
CT		 522static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
523 /* NT mV Trans mV db */
524 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
525 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
526 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
527 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
528 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
529 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
530 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
531 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
532 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
533 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 534};
535
b265a2a6
CT		 536static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
537 /* NT mV Trans mV db */
538 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
539 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
540 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
541 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
542 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
543 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
544 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
545 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
546 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
547 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 548};
549
b265a2a6
CT		 550static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
551 /* NT mV Trans mV db */
552 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
553 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
554 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
555 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
556 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
558 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 559};
560
cd96bea7
MN		 561struct icl_mg_phy_ddi_buf_trans {
562 u32 cri_txdeemph_override_5_0;
563 u32 cri_txdeemph_override_11_6;
564 u32 cri_txdeemph_override_17_12;
565};
566
567static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
568 /* Voltage swing pre-emphasis */
569 { 0x0, 0x1B, 0x00 }, /* 0 0 */
570 { 0x0, 0x23, 0x08 }, /* 0 1 */
571 { 0x0, 0x2D, 0x12 }, /* 0 2 */
572 { 0x0, 0x00, 0x00 }, /* 0 3 */
573 { 0x0, 0x23, 0x00 }, /* 1 0 */
574 { 0x0, 0x2B, 0x09 }, /* 1 1 */
575 { 0x0, 0x2E, 0x11 }, /* 1 2 */
576 { 0x0, 0x2F, 0x00 }, /* 2 0 */
577 { 0x0, 0x33, 0x0C }, /* 2 1 */
578 { 0x0, 0x00, 0x00 }, /* 3 0 */
579};
580
a930acd9
VS		 581static const struct ddi_buf_trans *
582bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
583{
584 if (dev_priv->vbt.edp.low_vswing) {
585 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
586 return bdw_ddi_translations_edp;
587 } else {
588 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
589 return bdw_ddi_translations_dp;
590 }
591}
592
acee2998 593static const struct ddi_buf_trans *
78ab0bae 594skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 595{
0fdd4918 596 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 597 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 598 return skl_y_ddi_translations_dp;
0fdd4918 599 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 600 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 601 return skl_u_ddi_translations_dp;
f8896f5d 602 } else {
f8896f5d 603 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 604 return skl_ddi_translations_dp;
f8896f5d 605 }
f8896f5d
DW		 606}
607
0fdd4918
RV		 608static const struct ddi_buf_trans *
609kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
610{
dfdaa566 611 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
0fdd4918
RV		 612 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
613 return kbl_y_ddi_translations_dp;
da411a48 614 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 615 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
616 return kbl_u_ddi_translations_dp;
617 } else {
618 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
619 return kbl_ddi_translations_dp;
620 }
621}
622
acee2998 623static const struct ddi_buf_trans *
78ab0bae 624skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 625{
06411f08 626 if (dev_priv->vbt.edp.low_vswing) {
dfdaa566 627 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 628 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 629 return skl_y_ddi_translations_edp;
da411a48
RV		 630 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
631 IS_CFL_ULT(dev_priv)) {
f8896f5d 632 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 633 return skl_u_ddi_translations_edp;
f8896f5d 634 } else {
f8896f5d 635 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 636 return skl_ddi_translations_edp;
f8896f5d
DW		 637 }
638 }
cd1101cb 639
da411a48 640 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 641 return kbl_get_buf_trans_dp(dev_priv, n_entries);
642 else
643 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 644}
645
646static const struct ddi_buf_trans *
78ab0bae 647skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 648{
dfdaa566 649 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 650 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 651 return skl_y_ddi_translations_hdmi;
f8896f5d 652 } else {
f8896f5d 653 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 654 return skl_ddi_translations_hdmi;
f8896f5d 655 }
f8896f5d
DW		 656}
657
edba48fd
VS		 658static int skl_buf_trans_num_entries(enum port port, int n_entries)
659{
660 /* Only DDIA and DDIE can select the 10th register with DP */
661 if (port == PORT_A || port == PORT_E)
662 return min(n_entries, 10);
663 else
664 return min(n_entries, 9);
665}
666
d8fe2c7f
VS		 667static const struct ddi_buf_trans *
668intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 669 enum port port, int *n_entries)
d8fe2c7f
VS		 670{
671 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 672 const struct ddi_buf_trans *ddi_translations =
673 kbl_get_buf_trans_dp(dev_priv, n_entries);
674 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
675 return ddi_translations;
d8fe2c7f 676 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 677 const struct ddi_buf_trans *ddi_translations =
678 skl_get_buf_trans_dp(dev_priv, n_entries);
679 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
680 return ddi_translations;
d8fe2c7f
VS		 681 } else if (IS_BROADWELL(dev_priv)) {
682 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
683 return bdw_ddi_translations_dp;
684 } else if (IS_HASWELL(dev_priv)) {
685 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
686 return hsw_ddi_translations_dp;
687 }
688
689 *n_entries = 0;
690 return NULL;
691}
692
693static const struct ddi_buf_trans *
694intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 695 enum port port, int *n_entries)
d8fe2c7f
VS		 696{
697 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 698 const struct ddi_buf_trans *ddi_translations =
699 skl_get_buf_trans_edp(dev_priv, n_entries);
700 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
701 return ddi_translations;
d8fe2c7f
VS		 702 } else if (IS_BROADWELL(dev_priv)) {
703 return bdw_get_buf_trans_edp(dev_priv, n_entries);
704 } else if (IS_HASWELL(dev_priv)) {
705 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
706 return hsw_ddi_translations_dp;
707 }
708
709 *n_entries = 0;
710 return NULL;
711}
712
713static const struct ddi_buf_trans *
714intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
715 int *n_entries)
716{
717 if (IS_BROADWELL(dev_priv)) {
718 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
719 return bdw_ddi_translations_fdi;
720 } else if (IS_HASWELL(dev_priv)) {
721 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
722 return hsw_ddi_translations_fdi;
723 }
724
725 *n_entries = 0;
726 return NULL;
727}
728
975786ee
VS		 729static const struct ddi_buf_trans *
730intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
731 int *n_entries)
732{
733 if (IS_GEN9_BC(dev_priv)) {
734 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
735 } else if (IS_BROADWELL(dev_priv)) {
736 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
737 return bdw_ddi_translations_hdmi;
738 } else if (IS_HASWELL(dev_priv)) {
739 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
740 return hsw_ddi_translations_hdmi;
741 }
742
743 *n_entries = 0;
744 return NULL;
745}
746
7d4f37b5
VS		 747static const struct bxt_ddi_buf_trans *
748bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
749{
750 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
751 return bxt_ddi_translations_dp;
752}
753
754static const struct bxt_ddi_buf_trans *
755bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
756{
757 if (dev_priv->vbt.edp.low_vswing) {
758 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
759 return bxt_ddi_translations_edp;
760 }
761
762 return bxt_get_buf_trans_dp(dev_priv, n_entries);
763}
764
765static const struct bxt_ddi_buf_trans *
766bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
767{
768 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
769 return bxt_ddi_translations_hdmi;
770}
771
cf3e0fb4
RV		 772static const struct cnl_ddi_buf_trans *
773cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
774{
775 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
776
777 if (voltage == VOLTAGE_INFO_0_85V) {
778 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
779 return cnl_ddi_translations_hdmi_0_85V;
780 } else if (voltage == VOLTAGE_INFO_0_95V) {
781 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
782 return cnl_ddi_translations_hdmi_0_95V;
783 } else if (voltage == VOLTAGE_INFO_1_05V) {
784 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
785 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 786 } else {
787 *n_entries = 1; /* shut up gcc */
cf3e0fb4 788 MISSING_CASE(voltage);
83482ca3 789 }
cf3e0fb4
RV		 790 return NULL;
791}
792
793static const struct cnl_ddi_buf_trans *
794cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
795{
796 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
797
798 if (voltage == VOLTAGE_INFO_0_85V) {
799 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
800 return cnl_ddi_translations_dp_0_85V;
801 } else if (voltage == VOLTAGE_INFO_0_95V) {
802 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
803 return cnl_ddi_translations_dp_0_95V;
804 } else if (voltage == VOLTAGE_INFO_1_05V) {
805 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
806 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 807 } else {
808 *n_entries = 1; /* shut up gcc */
cf3e0fb4 809 MISSING_CASE(voltage);
83482ca3 810 }
cf3e0fb4
RV		 811 return NULL;
812}
813
814static const struct cnl_ddi_buf_trans *
815cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
816{
817 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
818
819 if (dev_priv->vbt.edp.low_vswing) {
820 if (voltage == VOLTAGE_INFO_0_85V) {
821 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
822 return cnl_ddi_translations_edp_0_85V;
823 } else if (voltage == VOLTAGE_INFO_0_95V) {
824 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
825 return cnl_ddi_translations_edp_0_95V;
826 } else if (voltage == VOLTAGE_INFO_1_05V) {
827 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
828 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 829 } else {
830 *n_entries = 1; /* shut up gcc */
cf3e0fb4 831 MISSING_CASE(voltage);
83482ca3 832 }
cf3e0fb4
RV		 833 return NULL;
834 } else {
835 return cnl_get_buf_trans_dp(dev_priv, n_entries);
836 }
837}
838
b265a2a6 839static const struct cnl_ddi_buf_trans *
fb5c8e9d 840icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
b265a2a6 841 int type, int rate, int *n_entries)
fb5c8e9d 842{
b265a2a6
CT		 843 if (type == INTEL_OUTPUT_HDMI) {
844 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
845 return icl_combo_phy_ddi_translations_hdmi;
846 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
847 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
848 return icl_combo_phy_ddi_translations_edp_hbr3;
849 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
850 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
851 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 852 }
b265a2a6
CT		 853
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
855 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 856}
857
8d8bb85e
VS		 858static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
859{
d02ace87 860 int n_entries, level, default_entry;
8d8bb85e 861
d02ace87 862 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 863
2dd24a9c 864 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 865 if (intel_port_is_combophy(dev_priv, port))
b265a2a6
CT		 866 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
867 0, &n_entries);
dccc7228
MN		 868 else
869 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
870 default_entry = n_entries - 1;
871 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 872 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
873 default_entry = n_entries - 1;
043eaf36 874 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 875 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
876 default_entry = n_entries - 1;
bf503556 877 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 878 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
879 default_entry = 8;
8d8bb85e 880 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 881 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
882 default_entry = 7;
8d8bb85e 883 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 884 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
885 default_entry = 6;
8d8bb85e
VS		 886 } else {
887 WARN(1, "ddi translation table missing\n");
975786ee 888 return 0;
8d8bb85e
VS		 889 }
890
891 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 892 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
893 level = default_entry;
8d8bb85e 894
d02ace87 895 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 896 return 0;
d02ace87
VS		 897 if (WARN_ON_ONCE(level >= n_entries))
898 level = n_entries - 1;
21b39d2a 899
d02ace87 900 return level;
8d8bb85e
VS		 901}
902
e58623cb
AR		 903/*
904 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 905 * values in advance. This function programs the correct values for
906 * DP/eDP/FDI use cases.
45244b87 907 */
3a6d84e6
VS		 908static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
909 const struct intel_crtc_state *crtc_state)
45244b87 910{
6a7e4f99 911 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 912 u32 iboost_bit = 0;
7d1c42e6 913 int i, n_entries;
0fce04c8 914 enum port port = encoder->port;
10122051 915 const struct ddi_buf_trans *ddi_translations;
e58623cb 916
3a6d84e6
VS		 917 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
918 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
919 &n_entries);
920 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 921 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 922 &n_entries);
3a6d84e6 923 else
edba48fd 924 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 925 &n_entries);
e58623cb 926
edba48fd
VS		 927 /* If we're boosting the current, set bit 31 of trans1 */
928 if (IS_GEN9_BC(dev_priv) &&
929 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
930 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 931
7d1c42e6 932 for (i = 0; i < n_entries; i++) {
9712e688
VS		 933 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
934 ddi_translations[i].trans1 | iboost_bit);
935 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
936 ddi_translations[i].trans2);
45244b87 937 }
32bdc400
VS		 938}
939
940/*
941 * Starting with Haswell, DDI port buffers must be programmed with correct
942 * values in advance. This function programs the correct values for
943 * HDMI/DVI use cases.
944 */
7ea79333 945static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 946 int level)
32bdc400
VS		 947{
948 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
949 u32 iboost_bit = 0;
d02ace87 950 int n_entries;
0fce04c8 951 enum port port = encoder->port;
d02ace87 952 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 953
d02ace87 954 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 955
d02ace87 956 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 957 return;
d02ace87
VS		 958 if (WARN_ON_ONCE(level >= n_entries))
959 level = n_entries - 1;
21b39d2a 960
975786ee
VS		 961 /* If we're boosting the current, set bit 31 of trans1 */
962 if (IS_GEN9_BC(dev_priv) &&
963 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
964 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 965
6acab15a 966 /* Entry 9 is for HDMI: */
ed9c77d2 967 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 968 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 969 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 970 ddi_translations[level].trans2);
45244b87
ED		 971}
972
248138b5
PZ		 973static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
974 enum port port)
975{
f0f59a00 976 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 977 int i;
978
3449ca85 979 for (i = 0; i < 16; i++) {
248138b5
PZ		 980 udelay(1);
981 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
982 return;
983 }
984 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
985}
c82e4d26 986
3d0c5005 987static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 988{
0823eb9c 989 switch (pll->info->id) {
c856052a
ACO		 990 case DPLL_ID_WRPLL1:
991 return PORT_CLK_SEL_WRPLL1;
992 case DPLL_ID_WRPLL2:
993 return PORT_CLK_SEL_WRPLL2;
994 case DPLL_ID_SPLL:
995 return PORT_CLK_SEL_SPLL;
996 case DPLL_ID_LCPLL_810:
997 return PORT_CLK_SEL_LCPLL_810;
998 case DPLL_ID_LCPLL_1350:
999 return PORT_CLK_SEL_LCPLL_1350;
1000 case DPLL_ID_LCPLL_2700:
1001 return PORT_CLK_SEL_LCPLL_2700;
1002 default:
0823eb9c 1003 MISSING_CASE(pll->info->id);
c856052a
ACO		 1004 return PORT_CLK_SEL_NONE;
1005 }
1006}
1007
20fd2ab7 1008static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1009 const struct intel_crtc_state *crtc_state)
c27e917e 1010{
0e5fa646
ML		 1011 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1012 int clock = crtc_state->port_clock;
c27e917e
PZ		 1013 const enum intel_dpll_id id = pll->info->id;
1014
1015 switch (id) {
1016 default:
20fd2ab7
LDM		 1017 /*
1018 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1019 * here, so do warn if this get passed in
1020 */
c27e917e 1021 MISSING_CASE(id);
c27e917e 1022 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1023 case DPLL_ID_ICL_TBTPLL:
1024 switch (clock) {
1025 case 162000:
1026 return DDI_CLK_SEL_TBT_162;
1027 case 270000:
1028 return DDI_CLK_SEL_TBT_270;
1029 case 540000:
1030 return DDI_CLK_SEL_TBT_540;
1031 case 810000:
1032 return DDI_CLK_SEL_TBT_810;
1033 default:
1034 MISSING_CASE(clock);
7a61a6de 1035 return DDI_CLK_SEL_NONE;
1fa11ee2 1036 }
c27e917e
PZ		 1037 case DPLL_ID_ICL_MGPLL1:
1038 case DPLL_ID_ICL_MGPLL2:
1039 case DPLL_ID_ICL_MGPLL3:
1040 case DPLL_ID_ICL_MGPLL4:
1041 return DDI_CLK_SEL_MG;
1042 }
1043}
1044
c82e4d26
ED		 1045/* Starting with Haswell, different DDI ports can work in FDI mode for
1046 * connection to the PCH-located connectors. For this, it is necessary to train
1047 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1048 *
1049 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1050 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1051 * DDI A (which is used for eDP)
1052 */
1053
dc4a1094
ACO		 1054void hsw_fdi_link_train(struct intel_crtc *crtc,
1055 const struct intel_crtc_state *crtc_state)
c82e4d26 1056{
4cbe4b2b 1057 struct drm_device *dev = crtc->base.dev;
fac5e23e 1058 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1059 struct intel_encoder *encoder;
c856052a 1060 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1061
4cbe4b2b 1062 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1063 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1064 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1065 }
1066
04945641
PZ		 1067 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1068 * mode set "sequence for CRT port" document:
1069 * - TP1 to TP2 time with the default value
1070 * - FDI delay to 90h
8693a824
DL		 1071 *
1072 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1073 */
eede3b53 1074 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1075 FDI_RX_PWRDN_LANE0_VAL(2) |
1076 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1077
1078 /* Enable the PCH Receiver FDI PLL */
3e68320e 1079 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1080 FDI_RX_PLL_ENABLE |
dc4a1094 1081 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1082 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1083 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1084 udelay(220);
1085
1086 /* Switch from Rawclk to PCDclk */
1087 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1088 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1089
1090 /* Configure Port Clock Select */
dc4a1094 1091 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1092 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1093 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1094
1095 /* Start the training iterating through available voltages and emphasis,
1096 * testing each value twice. */
10122051 1097 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1098 /* Configure DP_TP_CTL with auto-training */
1099 I915_WRITE(DP_TP_CTL(PORT_E),
1100 DP_TP_CTL_FDI_AUTOTRAIN |
1101 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1102 DP_TP_CTL_LINK_TRAIN_PAT1 |
1103 DP_TP_CTL_ENABLE);
1104
876a8cdf
DL		 1105 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1106 * DDI E does not support port reversal, the functionality is
1107 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1108 * port reversal bit */
c82e4d26 1109 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1110 DDI_BUF_CTL_ENABLE |
dc4a1094 1111 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1112 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1113 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1114
1115 udelay(600);
1116
04945641 1117 /* Program PCH FDI Receiver TU */
eede3b53 1118 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1119
1120 /* Enable PCH FDI Receiver with auto-training */
1121 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1122 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1123 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1124
1125 /* Wait for FDI receiver lane calibration */
1126 udelay(30);
1127
1128 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1129 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1130 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1131 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1132 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1133
1134 /* Wait for FDI auto training time */
1135 udelay(5);
c82e4d26
ED		 1136
1137 temp = I915_READ(DP_TP_STATUS(PORT_E));
1138 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1139 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1140 break;
1141 }
c82e4d26 1142
a308ccb3
VS		 1143 /*
1144 * Leave things enabled even if we failed to train FDI.
1145 * Results in less fireworks from the state checker.
1146 */
1147 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1148 DRM_ERROR("FDI link training failed!\n");
1149 break;
c82e4d26 1150 }
04945641 1151
5b421c57
VS		 1152 rx_ctl_val &= ~FDI_RX_ENABLE;
1153 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1154 POSTING_READ(FDI_RX_CTL(PIPE_A));
1155
248138b5
PZ		 1156 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1157 temp &= ~DDI_BUF_CTL_ENABLE;
1158 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1159 POSTING_READ(DDI_BUF_CTL(PORT_E));
1160
04945641 1161 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1162 temp = I915_READ(DP_TP_CTL(PORT_E));
1163 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1164 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1165 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1166 POSTING_READ(DP_TP_CTL(PORT_E));
1167
1168 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1169
04945641 1170 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1171 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1172 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1173 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1174 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1175 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1176 }
1177
a308ccb3
VS		 1178 /* Enable normal pixel sending for FDI */
1179 I915_WRITE(DP_TP_CTL(PORT_E),
1180 DP_TP_CTL_FDI_AUTOTRAIN |
1181 DP_TP_CTL_LINK_TRAIN_NORMAL |
1182 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1183 DP_TP_CTL_ENABLE);
c82e4d26 1184}
0e72a5b5 1185
d7c530b2 1186static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1187{
1188 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1189 struct intel_digital_port *intel_dig_port =
1190 enc_to_dig_port(&encoder->base);
1191
1192 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1193 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1194 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1195}
1196
8d9ddbcb 1197static struct intel_encoder *
e9ce1a62 1198intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1199{
e9ce1a62 1200 struct drm_device *dev = crtc->base.dev;
1524e93e 1201 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1202 int num_encoders = 0;
1203
1524e93e
SS		 1204 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1205 ret = encoder;
8d9ddbcb
PZ		 1206 num_encoders++;
1207 }
1208
1209 if (num_encoders != 1)
84f44ce7 1210 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1211 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1212
1213 BUG_ON(ret == NULL);
1214 return ret;
1215}
1216
1c0b85c5 1217#define LC_FREQ 2700
1c0b85c5 1218
f0f59a00
VS		 1219static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1220 i915_reg_t reg)
11578553
JB		 1221{
1222 int refclk = LC_FREQ;
1223 int n, p, r;
1224 u32 wrpll;
1225
1226 wrpll = I915_READ(reg);
114fe488
DV		 1227 switch (wrpll & WRPLL_PLL_REF_MASK) {
1228 case WRPLL_PLL_SSC:
1229 case WRPLL_PLL_NON_SSC:
11578553
JB		 1230 /*
1231 * We could calculate spread here, but our checking
1232 * code only cares about 5% accuracy, and spread is a max of
1233 * 0.5% downspread.
1234 */
1235 refclk = 135;
1236 break;
114fe488 1237 case WRPLL_PLL_LCPLL:
11578553
JB		 1238 refclk = LC_FREQ;
1239 break;
1240 default:
1241 WARN(1, "bad wrpll refclk\n");
1242 return 0;
1243 }
1244
1245 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1246 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1247 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1248
20f0ec16
JB		 1249 /* Convert to KHz, p & r have a fixed point portion */
1250 return (refclk * n * 100) / (p * r);
11578553
JB		 1251}
1252
947f4417 1253static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1254{
3d0c5005 1255 u32 p0, p1, p2, dco_freq;
540e732c 1256
947f4417
LDM		 1257 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1258 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1259
947f4417
LDM		 1260 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1261 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1262 else
1263 p1 = 1;
1264
1265
1266 switch (p0) {
1267 case DPLL_CFGCR2_PDIV_1:
1268 p0 = 1;
1269 break;
1270 case DPLL_CFGCR2_PDIV_2:
1271 p0 = 2;
1272 break;
1273 case DPLL_CFGCR2_PDIV_3:
1274 p0 = 3;
1275 break;
1276 case DPLL_CFGCR2_PDIV_7:
1277 p0 = 7;
1278 break;
1279 }
1280
1281 switch (p2) {
1282 case DPLL_CFGCR2_KDIV_5:
1283 p2 = 5;
1284 break;
1285 case DPLL_CFGCR2_KDIV_2:
1286 p2 = 2;
1287 break;
1288 case DPLL_CFGCR2_KDIV_3:
1289 p2 = 3;
1290 break;
1291 case DPLL_CFGCR2_KDIV_1:
1292 p2 = 1;
1293 break;
1294 }
1295
947f4417
LDM		 1296 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1297 * 24 * 1000;
540e732c 1298
947f4417
LDM		 1299 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1300 * 24 * 1000) / 0x8000;
540e732c 1301
b8449c43
YX		 1302 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1303 return 0;
1304
540e732c
S		 1305 return dco_freq / (p0 * p1 * p2 * 5);
1306}
1307
8327af28 1308int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1309 struct intel_dpll_hw_state *pll_state)
a9701a89 1310{
3d0c5005 1311 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1312
5e65216d
LDM		 1313 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1314 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1315
5e65216d
LDM		 1316 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1317 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1318 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1319 else
1320 p1 = 1;
1321
1322
1323 switch (p0) {
1324 case DPLL_CFGCR1_PDIV_2:
1325 p0 = 2;
1326 break;
1327 case DPLL_CFGCR1_PDIV_3:
1328 p0 = 3;
1329 break;
1330 case DPLL_CFGCR1_PDIV_5:
1331 p0 = 5;
1332 break;
1333 case DPLL_CFGCR1_PDIV_7:
1334 p0 = 7;
1335 break;
1336 }
1337
1338 switch (p2) {
1339 case DPLL_CFGCR1_KDIV_1:
1340 p2 = 1;
1341 break;
1342 case DPLL_CFGCR1_KDIV_2:
1343 p2 = 2;
1344 break;
2ee7fd1e
VS		 1345 case DPLL_CFGCR1_KDIV_3:
1346 p2 = 3;
a9701a89
RV		 1347 break;
1348 }
1349
9f9d594d 1350 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1351
5e65216d
LDM		 1352 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1353 * ref_clock;
a9701a89 1354
5e65216d 1355 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1356 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1357
0e005888
PZ		 1358 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1359 return 0;
1360
a9701a89
RV		 1361 return dco_freq / (p0 * p1 * p2 * 5);
1362}
1363
7b19f544
MN		 1364static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1365 enum port port)
1366{
1367 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1368
1369 switch (val) {
1370 case DDI_CLK_SEL_NONE:
1371 return 0;
1372 case DDI_CLK_SEL_TBT_162:
1373 return 162000;
1374 case DDI_CLK_SEL_TBT_270:
1375 return 270000;
1376 case DDI_CLK_SEL_TBT_540:
1377 return 540000;
1378 case DDI_CLK_SEL_TBT_810:
1379 return 810000;
1380 default:
1381 MISSING_CASE(val);
1382 return 0;
1383 }
1384}
1385
1386static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1387 const struct intel_dpll_hw_state *pll_state)
7b19f544 1388{
02c99d26 1389 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1390 u64 tmp;
1391
02c99d26 1392 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1393
02c99d26
LDM		 1394 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1395 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1396 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1397 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1398 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1399
02c99d26
LDM		 1400 switch (pll_state->mg_clktop2_hsclkctl &
1401 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1402 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1403 div1 = 2;
1404 break;
1405 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1406 div1 = 3;
1407 break;
1408 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1409 div1 = 5;
1410 break;
1411 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1412 div1 = 7;
1413 break;
1414 default:
02c99d26 1415 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1416 return 0;
1417 }
1418
02c99d26
LDM		 1419 div2 = (pll_state->mg_clktop2_hsclkctl &
1420 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1421 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1422
7b19f544
MN		 1423 /* div2 value of 0 is same as 1 means no div */
1424 if (div2 == 0)
1425 div2 = 1;
1426
1427 /*
1428 * Adjust the original formula to delay the division by 2^22 in order to
1429 * minimize possible rounding errors.
1430 */
02c99d26
LDM		 1431 tmp = (u64)m1 * m2_int * ref_clock +
1432 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1433 tmp = div_u64(tmp, 5 * div1 * div2);
1434
1435 return tmp;
1436}
1437
398a017e
VS		 1438static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1439{
1440 int dotclock;
1441
1442 if (pipe_config->has_pch_encoder)
1443 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1444 &pipe_config->fdi_m_n);
37a5650b 1445 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1446 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1447 &pipe_config->dp_m_n);
1448 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1449 dotclock = pipe_config->port_clock * 2 / 3;
1450 else
1451 dotclock = pipe_config->port_clock;
1452
33b7f3ee 1453 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
b22ca995
SS		 1454 dotclock *= 2;
1455
398a017e
VS		 1456 if (pipe_config->pixel_multiplier)
1457 dotclock /= pipe_config->pixel_multiplier;
1458
1459 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1460}
540e732c 1461
51c83cfa
MN		 1462static void icl_ddi_clock_get(struct intel_encoder *encoder,
1463 struct intel_crtc_state *pipe_config)
1464{
1465 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1466 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1467 enum port port = encoder->port;
5e65216d 1468 int link_clock;
51c83cfa 1469
176597a1 1470 if (intel_port_is_combophy(dev_priv, port)) {
5e65216d 1471 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1472 } else {
077973c8
LDM		 1473 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1474 pipe_config->shared_dpll);
1475
7b19f544
MN		 1476 if (pll_id == DPLL_ID_ICL_TBTPLL)
1477 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1478 else
02c99d26 1479 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1480 }
1481
1482 pipe_config->port_clock = link_clock;
02c99d26 1483
51c83cfa
MN		 1484 ddi_dotclock_get(pipe_config);
1485}
1486
a9701a89
RV		 1487static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1488 struct intel_crtc_state *pipe_config)
1489{
1490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1491 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1492 int link_clock;
a9701a89 1493
5e65216d
LDM		 1494 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1495 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1496 } else {
5e65216d 1497 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1498
1499 switch (link_clock) {
1500 case DPLL_CFGCR0_LINK_RATE_810:
1501 link_clock = 81000;
1502 break;
1503 case DPLL_CFGCR0_LINK_RATE_1080:
1504 link_clock = 108000;
1505 break;
1506 case DPLL_CFGCR0_LINK_RATE_1350:
1507 link_clock = 135000;
1508 break;
1509 case DPLL_CFGCR0_LINK_RATE_1620:
1510 link_clock = 162000;
1511 break;
1512 case DPLL_CFGCR0_LINK_RATE_2160:
1513 link_clock = 216000;
1514 break;
1515 case DPLL_CFGCR0_LINK_RATE_2700:
1516 link_clock = 270000;
1517 break;
1518 case DPLL_CFGCR0_LINK_RATE_3240:
1519 link_clock = 324000;
1520 break;
1521 case DPLL_CFGCR0_LINK_RATE_4050:
1522 link_clock = 405000;
1523 break;
1524 default:
1525 WARN(1, "Unsupported link rate\n");
1526 break;
1527 }
1528 link_clock *= 2;
1529 }
1530
1531 pipe_config->port_clock = link_clock;
1532
1533 ddi_dotclock_get(pipe_config);
1534}
1535
540e732c 1536static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1537 struct intel_crtc_state *pipe_config)
540e732c 1538{
947f4417
LDM		 1539 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1540 int link_clock;
540e732c 1541
947f4417
LDM		 1542 /*
1543 * ctrl1 register is already shifted for each pll, just use 0 to get
1544 * the internal shift for each field
1545 */
1546 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1547 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1548 } else {
947f4417
LDM		 1549 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1550 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1551
1552 switch (link_clock) {
71cd8423 1553 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1554 link_clock = 81000;
1555 break;
71cd8423 1556 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1557 link_clock = 108000;
1558 break;
71cd8423 1559 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1560 link_clock = 135000;
1561 break;
71cd8423 1562 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1563 link_clock = 162000;
1564 break;
71cd8423 1565 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1566 link_clock = 216000;
1567 break;
71cd8423 1568 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1569 link_clock = 270000;
1570 break;
1571 default:
1572 WARN(1, "Unsupported link rate\n");
1573 break;
1574 }
1575 link_clock *= 2;
1576 }
1577
1578 pipe_config->port_clock = link_clock;
1579
398a017e 1580 ddi_dotclock_get(pipe_config);
540e732c
S		 1581}
1582
3d51278a 1583static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1584 struct intel_crtc_state *pipe_config)
11578553 1585{
fac5e23e 1586 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1587 int link_clock = 0;
1588 u32 val, pll;
1589
c856052a 1590 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1591 switch (val & PORT_CLK_SEL_MASK) {
1592 case PORT_CLK_SEL_LCPLL_810:
1593 link_clock = 81000;
1594 break;
1595 case PORT_CLK_SEL_LCPLL_1350:
1596 link_clock = 135000;
1597 break;
1598 case PORT_CLK_SEL_LCPLL_2700:
1599 link_clock = 270000;
1600 break;
1601 case PORT_CLK_SEL_WRPLL1:
01403de3 1602 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1603 break;
1604 case PORT_CLK_SEL_WRPLL2:
01403de3 1605 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1606 break;
1607 case PORT_CLK_SEL_SPLL:
1608 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1609 if (pll == SPLL_PLL_FREQ_810MHz)
1610 link_clock = 81000;
1611 else if (pll == SPLL_PLL_FREQ_1350MHz)
1612 link_clock = 135000;
1613 else if (pll == SPLL_PLL_FREQ_2700MHz)
1614 link_clock = 270000;
1615 else {
1616 WARN(1, "bad spll freq\n");
1617 return;
1618 }
1619 break;
1620 default:
1621 WARN(1, "bad port clock sel\n");
1622 return;
1623 }
1624
1625 pipe_config->port_clock = link_clock * 2;
1626
398a017e 1627 ddi_dotclock_get(pipe_config);
11578553
JB		 1628}
1629
47c9877e 1630static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1631{
9e2c8475 1632 struct dpll clock;
aa610dcb 1633
aa610dcb 1634 clock.m1 = 2;
47c9877e
LDM		 1635 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1636 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1637 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1638 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1639 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1640 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1641
1642 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1643}
1644
1645static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1646 struct intel_crtc_state *pipe_config)
977bb38d 1647{
47c9877e
LDM		 1648 pipe_config->port_clock =
1649 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1650
398a017e 1651 ddi_dotclock_get(pipe_config);
977bb38d
S		 1652}
1653
35686a44
VS		 1654static void intel_ddi_clock_get(struct intel_encoder *encoder,
1655 struct intel_crtc_state *pipe_config)
3d51278a 1656{
0853723b 1657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1658
2dd24a9c 1659 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1660 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1661 else if (IS_CANNONLAKE(dev_priv))
1662 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1663 else if (IS_GEN9_LP(dev_priv))
1664 bxt_ddi_clock_get(encoder, pipe_config);
1665 else if (IS_GEN9_BC(dev_priv))
1666 skl_ddi_clock_get(encoder, pipe_config);
1667 else if (INTEL_GEN(dev_priv) <= 8)
1668 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1669}
1670
3dc38eea 1671void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1672{
3dc38eea 1673 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1674 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1675 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1676 u32 temp;
dae84799 1677
5448f53f
VS		 1678 if (!intel_crtc_has_dp_encoder(crtc_state))
1679 return;
4d1de975 1680
5448f53f
VS		 1681 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1682
1683 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1684
1685 if (crtc_state->limited_color_range)
1686 temp |= TRANS_MSA_CEA_RANGE;
1687
5448f53f
VS		 1688 switch (crtc_state->pipe_bpp) {
1689 case 18:
1690 temp |= TRANS_MSA_6_BPC;
1691 break;
1692 case 24:
1693 temp |= TRANS_MSA_8_BPC;
1694 break;
1695 case 30:
1696 temp |= TRANS_MSA_10_BPC;
1697 break;
1698 case 36:
1699 temp |= TRANS_MSA_12_BPC;
1700 break;
1701 default:
1702 MISSING_CASE(crtc_state->pipe_bpp);
1703 break;
dae84799 1704 }
5448f53f 1705
668b6c17
SS		 1706 /*
1707 * As per DP 1.2 spec section 2.3.4.3 while sending
1708 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1709 * colorspace information. The output colorspace encoding is BT601.
1710 */
1711 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1712 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
5448f53f 1713 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1714}
1715
3dc38eea
ACO		 1716void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1717 bool state)
0e32b39c 1718{
3dc38eea 1719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1721 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1722 u32 temp;
7e732cac 1723
0e32b39c
DA		 1724 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1725 if (state == true)
1726 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1727 else
1728 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1729 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1730}
1731
3dc38eea 1732void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1733{
3dc38eea 1734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1735 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1736 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1737 enum pipe pipe = crtc->pipe;
3dc38eea 1738 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1739 enum port port = encoder->port;
3d0c5005 1740 u32 temp;
8d9ddbcb 1741
ad80a810
PZ		 1742 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1743 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1744 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1745
3dc38eea 1746 switch (crtc_state->pipe_bpp) {
dfcef252 1747 case 18:
ad80a810 1748 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1749 break;
1750 case 24:
ad80a810 1751 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1752 break;
1753 case 30:
ad80a810 1754 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1755 break;
1756 case 36:
ad80a810 1757 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1758 break;
1759 default:
4e53c2e0 1760 BUG();
dfcef252 1761 }
72662e10 1762
3dc38eea 1763 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1764 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1765 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1766 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1767
e6f0bfc4
PZ		 1768 if (cpu_transcoder == TRANSCODER_EDP) {
1769 switch (pipe) {
1770 case PIPE_A:
c7670b10
PZ		 1771 /* On Haswell, can only use the always-on power well for
1772 * eDP when not using the panel fitter, and when not
1773 * using motion blur mitigation (which we don't
1774 * support). */
772c2a51 1775 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1776 (crtc_state->pch_pfit.enabled ||
1777 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1778 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1779 else
1780 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1781 break;
1782 case PIPE_B:
1783 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1784 break;
1785 case PIPE_C:
1786 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1787 break;
1788 default:
1789 BUG();
1790 break;
1791 }
1792 }
1793
742745f1 1794 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1795 if (crtc_state->has_hdmi_sink)
ad80a810 1796 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1797 else
ad80a810 1798 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1799
1800 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1801 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1802 if (crtc_state->hdmi_high_tmds_clock_ratio)
1803 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1804 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1805 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1806 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1807 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1808 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1809 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1810 } else {
742745f1
VS		 1811 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1812 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1813 }
1814
ad80a810 1815 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1816}
72662e10 1817
90c3e219 1818void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1819{
90c3e219
CT		 1820 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1821 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1822 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1823 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1824 u32 val = I915_READ(reg);
8d9ddbcb 1825
0e32b39c 1826 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1827 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1828 I915_WRITE(reg, val);
90c3e219
CT		 1829
1830 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1831 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1832 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1833 /* Quirk time at 100ms for reliable operation */
1834 msleep(100);
1835 }
72662e10
ED		 1836}
1837
2320175f
SP		 1838int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1839 bool enable)
1840{
1841 struct drm_device *dev = intel_encoder->base.dev;
1842 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1843 intel_wakeref_t wakeref;
2320175f
SP		 1844 enum pipe pipe = 0;
1845 int ret = 0;
3d0c5005 1846 u32 tmp;
2320175f 1847
0e6e0be4
CW		 1848 wakeref = intel_display_power_get_if_enabled(dev_priv,
1849 intel_encoder->power_domain);
1850 if (WARN_ON(!wakeref))
2320175f
SP		 1851 return -ENXIO;
1852
1853 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1854 ret = -EIO;
1855 goto out;
1856 }
1857
1858 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1859 if (enable)
1860 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1861 else
1862 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1863 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1864out:
0e6e0be4 1865 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1866 return ret;
1867}
1868
bcbc889b
PZ		 1869bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1870{
1871 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1872 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1873 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1874 int type = intel_connector->base.connector_type;
0fce04c8 1875 enum port port = encoder->port;
bcbc889b 1876 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1877 intel_wakeref_t wakeref;
1878 enum pipe pipe = 0;
3d0c5005 1879 u32 tmp;
e27daab4 1880 bool ret;
bcbc889b 1881
0e6e0be4
CW		 1882 wakeref = intel_display_power_get_if_enabled(dev_priv,
1883 encoder->power_domain);
1884 if (!wakeref)
882244a3
PZ		 1885 return false;
1886
1524e93e 1887 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1888 ret = false;
1889 goto out;
1890 }
bcbc889b 1891
bc7e3525 1892 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1893 cpu_transcoder = TRANSCODER_EDP;
1894 else
1a240d4d 1895 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1896
1897 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1898
1899 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1900 case TRANS_DDI_MODE_SELECT_HDMI:
1901 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1902 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1903 break;
bcbc889b
PZ		 1904
1905 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1906 ret = type == DRM_MODE_CONNECTOR_eDP ||
1907 type == DRM_MODE_CONNECTOR_DisplayPort;
1908 break;
1909
0e32b39c
DA		 1910 case TRANS_DDI_MODE_SELECT_DP_MST:
1911 /* if the transcoder is in MST state then
1912 * connector isn't connected */
e27daab4
ID		 1913 ret = false;
1914 break;
bcbc889b
PZ		 1915
1916 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1917 ret = type == DRM_MODE_CONNECTOR_VGA;
1918 break;
bcbc889b
PZ		 1919
1920 default:
e27daab4
ID		 1921 ret = false;
1922 break;
bcbc889b 1923 }
e27daab4
ID		 1924
1925out:
0e6e0be4 1926 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 1927
1928 return ret;
bcbc889b
PZ		 1929}
1930
9199c322
ID		 1931static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1932 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 1933{
1934 struct drm_device *dev = encoder->base.dev;
fac5e23e 1935 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1936 enum port port = encoder->port;
0e6e0be4 1937 intel_wakeref_t wakeref;
3657e927 1938 enum pipe p;
85234cdc 1939 u32 tmp;
9199c322
ID		 1940 u8 mst_pipe_mask;
1941
1942 *pipe_mask = 0;
1943 *is_dp_mst = false;
85234cdc 1944
0e6e0be4
CW		 1945 wakeref = intel_display_power_get_if_enabled(dev_priv,
1946 encoder->power_domain);
1947 if (!wakeref)
9199c322 1948 return;
e27daab4 1949
fe43d3f5 1950 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 1951 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1952 goto out;
85234cdc 1953
bc7e3525 1954 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 1955 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1956
ad80a810 1957 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 1958 default:
1959 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1960 /* fallthrough */
ad80a810
PZ		 1961 case TRANS_DDI_EDP_INPUT_A_ON:
1962 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 1963 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 1964 break;
1965 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 1966 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 1967 break;
1968 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 1969 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 1970 break;
1971 }
1972
e27daab4
ID		 1973 goto out;
1974 }
0e32b39c 1975
9199c322 1976 mst_pipe_mask = 0;
3657e927 1977 for_each_pipe(dev_priv, p) {
9199c322 1978 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 1979
1980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 1981
9199c322
ID		 1982 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1983 continue;
e27daab4 1984
9199c322
ID		 1985 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1986 TRANS_DDI_MODE_SELECT_DP_MST)
1987 mst_pipe_mask |= BIT(p);
e27daab4 1988
9199c322 1989 *pipe_mask |= BIT(p);
85234cdc
DV		 1990 }
1991
9199c322
ID		 1992 if (!*pipe_mask)
1993 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
1994 port_name(port));
1995
1996 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1997 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
1998 port_name(port), *pipe_mask);
1999 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2000 }
2001
2002 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2003 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2004 port_name(port), *pipe_mask, mst_pipe_mask);
2005 else
2006 *is_dp_mst = mst_pipe_mask;
85234cdc 2007
e27daab4 2008out:
9199c322 2009 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2010 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2011 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2012 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2013 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2014 DRM_ERROR("Port %c enabled but PHY powered down? "
2015 "(PHY_CTL %08x)\n", port_name(port), tmp);
2016 }
2017
0e6e0be4 2018 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2019}
e27daab4 2020
9199c322
ID		 2021bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2022 enum pipe *pipe)
2023{
2024 u8 pipe_mask;
2025 bool is_mst;
2026
2027 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2028
2029 if (is_mst || !pipe_mask)
2030 return false;
2031
2032 *pipe = ffs(pipe_mask) - 1;
2033
2034 return true;
85234cdc
DV		 2035}
2036
52528055 2037static inline enum intel_display_power_domain
bdaa29b6 2038intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2039{
9e3b5ce9 2040 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2041 * DC states enabled at the same time, while for driver initiated AUX
2042 * transfers we need the same AUX IOs to be powered but with DC states
2043 * disabled. Accordingly use the AUX power domain here which leaves DC
2044 * states enabled.
2045 * However, for non-A AUX ports the corresponding non-EDP transcoders
2046 * would have already enabled power well 2 and DC_OFF. This means we can
2047 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2048 * specific AUX_IO reference without powering up any extra wells.
2049 * Note that PSR is enabled only on Port A even though this function
2050 * returns the correct domain for other ports too.
2051 */
563d22a0 2052 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2053 intel_aux_power_domain(dig_port);
52528055
ID		 2054}
2055
2056static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2057 struct intel_crtc_state *crtc_state)
62b69566 2058{
8e4a3ad9 2059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2060 struct intel_digital_port *dig_port;
52528055 2061 u64 domains;
62b69566 2062
52528055
ID		 2063 /*
2064 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2065 * happen since fake-MST encoders don't set their get_power_domains()
2066 * hook.
52528055
ID		 2067 */
2068 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
b79ebe74
ID		 2069 return 0;
2070
2071 dig_port = enc_to_dig_port(&encoder->base);
2072 domains = BIT_ULL(dig_port->ddi_io_power_domain);
52528055 2073
8e4a3ad9
ID		 2074 /*
2075 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2076 * ports.
2077 */
2078 if (intel_crtc_has_dp_encoder(crtc_state) ||
2079 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6 2080 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
52528055 2081
a24c62f9
MN		 2082 /*
2083 * VDSC power is needed when DSC is enabled
2084 */
2085 if (crtc_state->dsc_params.compression_enable)
2086 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2087
52528055 2088 return domains;
62b69566
ACO		 2089}
2090
3dc38eea 2091void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2092{
3dc38eea 2093 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2094 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2095 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2096 enum port port = encoder->port;
3dc38eea 2097 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2098
bb523fc0
PZ		 2099 if (cpu_transcoder != TRANSCODER_EDP)
2100 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2101 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2102}
2103
3dc38eea 2104void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2105{
3dc38eea
ACO		 2106 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2107 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2108
bb523fc0
PZ		 2109 if (cpu_transcoder != TRANSCODER_EDP)
2110 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2111 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2112}
2113
a7d8dbc0 2114static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2115 enum port port, u8 iboost)
f8896f5d 2116{
a7d8dbc0
VS		 2117 u32 tmp;
2118
2119 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2120 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2121 if (iboost)
2122 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2123 else
2124 tmp |= BALANCE_LEG_DISABLE(port);
2125 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2126}
2127
081dfcfa
VS		 2128static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2129 int level, enum intel_output_type type)
a7d8dbc0
VS		 2130{
2131 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2132 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2133 enum port port = encoder->port;
3d0c5005 2134 u8 iboost;
f8896f5d 2135
081dfcfa
VS		 2136 if (type == INTEL_OUTPUT_HDMI)
2137 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2138 else
2139 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2140
081dfcfa
VS		 2141 if (iboost == 0) {
2142 const struct ddi_buf_trans *ddi_translations;
2143 int n_entries;
2144
2145 if (type == INTEL_OUTPUT_HDMI)
2146 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2147 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2148 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2149 else
edba48fd 2150 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2151
21b39d2a
VS		 2152 if (WARN_ON_ONCE(!ddi_translations))
2153 return;
2154 if (WARN_ON_ONCE(level >= n_entries))
2155 level = n_entries - 1;
2156
081dfcfa 2157 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2158 }
2159
2160 /* Make sure that the requested I_boost is valid */
2161 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2162 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2163 return;
2164 }
2165
a7d8dbc0 2166 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2167
a7d8dbc0
VS		 2168 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2169 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2170}
2171
7d4f37b5
VS		 2172static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2173 int level, enum intel_output_type type)
96fb9f9b 2174{
7d4f37b5 2175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2176 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2177 enum port port = encoder->port;
043eaf36 2178 int n_entries;
7d4f37b5
VS		 2179
2180 if (type == INTEL_OUTPUT_HDMI)
2181 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2182 else if (type == INTEL_OUTPUT_EDP)
2183 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2184 else
2185 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2186
21b39d2a
VS		 2187 if (WARN_ON_ONCE(!ddi_translations))
2188 return;
2189 if (WARN_ON_ONCE(level >= n_entries))
2190 level = n_entries - 1;
2191
b6e08203
ACO		 2192 bxt_ddi_phy_set_signal_level(dev_priv, port,
2193 ddi_translations[level].margin,
2194 ddi_translations[level].scale,
2195 ddi_translations[level].enable,
2196 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2197}
2198
ffe5111e
VS		 2199u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2200{
2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2202 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2203 enum port port = encoder->port;
ffe5111e
VS		 2204 int n_entries;
2205
2dd24a9c 2206 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2207 if (intel_port_is_combophy(dev_priv, port))
36cf89f5 2208 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
b265a2a6 2209 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2210 else
2211 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2212 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2213 if (encoder->type == INTEL_OUTPUT_EDP)
2214 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2215 else
2216 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2217 } else if (IS_GEN9_LP(dev_priv)) {
2218 if (encoder->type == INTEL_OUTPUT_EDP)
2219 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2220 else
2221 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2222 } else {
2223 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2224 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2225 else
edba48fd 2226 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2227 }
ffe5111e
VS		 2228
2229 if (WARN_ON(n_entries < 1))
2230 n_entries = 1;
2231 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2232 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2233
2234 return index_to_dp_signal_levels[n_entries - 1] &
2235 DP_TRAIN_VOLTAGE_SWING_MASK;
2236}
2237
4718a365
VS		 2238/*
2239 * We assume that the full set of pre-emphasis values can be
2240 * used on all DDI platforms. Should that change we need to
2241 * rethink this code.
2242 */
2243u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2244{
2245 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2247 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2249 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2251 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2253 default:
2254 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2255 }
2256}
2257
f3cf4ba4
VS		 2258static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2259 int level, enum intel_output_type type)
cf54ca8b 2260{
f3cf4ba4 2261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2262 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2263 enum port port = encoder->port;
f3cf4ba4
VS		 2264 int n_entries, ln;
2265 u32 val;
cf54ca8b 2266
f3cf4ba4 2267 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2268 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2269 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2270 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2271 else
2272 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2273
21b39d2a 2274 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2275 return;
21b39d2a 2276 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2277 level = n_entries - 1;
cf54ca8b
RV		 2278
2279 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2280 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2281 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2282 val |= SCALING_MODE_SEL(2);
2283 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2284
2285 /* Program PORT_TX_DW2 */
2286 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2287 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2288 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2289 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2290 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2291 /* Rcomp scalar is fixed as 0x98 for every table entry */
2292 val |= RCOMP_SCALAR(0x98);
2293 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2294
20303eb4 2295 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2296 /* We cannot write to GRP. It would overrite individual loadgen */
2297 for (ln = 0; ln < 4; ln++) {
9194e42a 2298 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2299 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2300 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2301 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2302 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2303 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2304 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2305 }
2306
20303eb4 2307 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2308 /* All DW5 values are fixed for every table entry */
2309 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2310 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2311 val |= RTERM_SELECT(6);
2312 val |= TAP3_DISABLE;
2313 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2314
20303eb4 2315 /* Program PORT_TX_DW7 */
cf54ca8b 2316 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2317 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2318 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2319 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2320}
2321
f3cf4ba4
VS		 2322static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2323 int level, enum intel_output_type type)
cf54ca8b 2324{
0091abc3 2325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2326 enum port port = encoder->port;
f3cf4ba4 2327 int width, rate, ln;
cf54ca8b 2328 u32 val;
0091abc3 2329
f3cf4ba4 2330 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2331 width = 4;
f3cf4ba4 2332 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2333 } else {
f3cf4ba4
VS		 2334 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2335
2336 width = intel_dp->lane_count;
2337 rate = intel_dp->link_rate;
0091abc3 2338 }
cf54ca8b
RV		 2339
2340 /*
2341 * 1. If port type is eDP or DP,
2342 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2343 * else clear to 0b.
2344 */
2345 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2346 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2347 val |= COMMON_KEEPER_EN;
2348 else
2349 val &= ~COMMON_KEEPER_EN;
2350 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2351
2352 /* 2. Program loadgen select */
2353 /*
0091abc3
CT		 2354 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2355 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2356 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2357 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2358 */
0091abc3 2359 for (ln = 0; ln <= 3; ln++) {
9194e42a 2360 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2361 val &= ~LOADGEN_SELECT;
2362
a8e45a1c
NM		 2363 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2364 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2365 val |= LOADGEN_SELECT;
2366 }
9194e42a 2367 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2368 }
cf54ca8b
RV		 2369
2370 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2371 val = I915_READ(CNL_PORT_CL1CM_DW5);
2372 val |= SUS_CLOCK_CONFIG;
2373 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2374
2375 /* 4. Clear training enable to change swing values */
2376 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2377 val &= ~TX_TRAINING_EN;
2378 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2379
2380 /* 5. Program swing and de-emphasis */
f3cf4ba4 2381 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2382
2383 /* 6. Set training enable to trigger update */
2384 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2385 val |= TX_TRAINING_EN;
2386 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2387}
2388
fb5c8e9d 2389static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
b265a2a6
CT		 2390 u32 level, enum port port, int type,
2391 int rate)
fb5c8e9d 2392{
b265a2a6 2393 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2394 u32 n_entries, val;
2395 int ln;
2396
2397 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
b265a2a6 2398 rate, &n_entries);
fb5c8e9d
MN		 2399 if (!ddi_translations)
2400 return;
2401
2402 if (level >= n_entries) {
2403 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2404 level = n_entries - 1;
2405 }
2406
b265a2a6 2407 /* Set PORT_TX_DW5 */
fb5c8e9d 2408 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
b265a2a6
CT		 2409 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2410 TAP2_DISABLE | TAP3_DISABLE);
2411 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2412 val |= RTERM_SELECT(0x6);
b265a2a6 2413 val |= TAP3_DISABLE;
fb5c8e9d
MN		 2414 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2415
2416 /* Program PORT_TX_DW2 */
2417 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2418 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2419 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2420 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2421 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2422 /* Program Rcomp scalar for every table entry */
b265a2a6 2423 val |= RCOMP_SCALAR(0x98);
fb5c8e9d
MN		 2424 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2425
2426 /* Program PORT_TX_DW4 */
2427 /* We cannot write to GRP. It would overwrite individual loadgen. */
2428 for (ln = 0; ln <= 3; ln++) {
9194e42a 2429 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2430 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2431 CURSOR_COEFF_MASK);
b265a2a6
CT		 2432 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2433 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2434 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2435 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d 2436 }
b265a2a6
CT		 2437
2438 /* Program PORT_TX_DW7 */
2439 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2440 val &= ~N_SCALAR_MASK;
2441 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2442 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
fb5c8e9d
MN		 2443}
2444
2445static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2446 u32 level,
2447 enum intel_output_type type)
2448{
2449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2450 enum port port = encoder->port;
2451 int width = 0;
2452 int rate = 0;
2453 u32 val;
2454 int ln = 0;
2455
2456 if (type == INTEL_OUTPUT_HDMI) {
2457 width = 4;
2458 /* Rate is always < than 6GHz for HDMI */
2459 } else {
2460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461
2462 width = intel_dp->lane_count;
2463 rate = intel_dp->link_rate;
2464 }
2465
2466 /*
2467 * 1. If port type is eDP or DP,
2468 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2469 * else clear to 0b.
2470 */
2471 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2472 if (type == INTEL_OUTPUT_HDMI)
2473 val &= ~COMMON_KEEPER_EN;
2474 else
2475 val |= COMMON_KEEPER_EN;
2476 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2477
2478 /* 2. Program loadgen select */
2479 /*
2480 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2481 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2482 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2483 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2484 */
2485 for (ln = 0; ln <= 3; ln++) {
9194e42a 2486 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2487 val &= ~LOADGEN_SELECT;
2488
2489 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2490 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2491 val |= LOADGEN_SELECT;
2492 }
9194e42a 2493 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d
MN		 2494 }
2495
2496 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2497 val = I915_READ(ICL_PORT_CL_DW5(port));
2498 val |= SUS_CLOCK_CONFIG;
2499 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2500
2501 /* 4. Clear training enable to change swing values */
2502 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2503 val &= ~TX_TRAINING_EN;
2504 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2505
2506 /* 5. Program swing and de-emphasis */
b265a2a6 2507 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
fb5c8e9d
MN		 2508
2509 /* 6. Set training enable to trigger update */
2510 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2511 val |= TX_TRAINING_EN;
2512 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2513}
2514
07685c82
MN		 2515static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2516 int link_clock,
2517 u32 level)
2518{
2519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2520 enum port port = encoder->port;
2521 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2522 u32 n_entries, val;
2523 int ln;
2524
2525 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2526 ddi_translations = icl_mg_phy_ddi_translations;
2527 /* The table does not have values for level 3 and level 9. */
2528 if (level >= n_entries || level == 3 || level == 9) {
2529 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2530 level, n_entries - 2);
2531 level = n_entries - 2;
2532 }
2533
2534 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2535 for (ln = 0; ln < 2; ln++) {
58106b7d 2536 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2537 val &= ~CRI_USE_FS32;
58106b7d 2538 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2539
58106b7d 2540 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2541 val &= ~CRI_USE_FS32;
58106b7d 2542 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2543 }
2544
2545 /* Program MG_TX_SWINGCTRL with values from vswing table */
2546 for (ln = 0; ln < 2; ln++) {
58106b7d 2547 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2548 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2549 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2550 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2551 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2552
58106b7d 2553 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2554 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2555 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2556 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2557 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2558 }
2559
2560 /* Program MG_TX_DRVCTRL with values from vswing table */
2561 for (ln = 0; ln < 2; ln++) {
58106b7d 2562 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2563 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2564 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2565 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2566 ddi_translations[level].cri_txdeemph_override_5_0) |
2567 CRI_TXDEEMPH_OVERRIDE_11_6(
2568 ddi_translations[level].cri_txdeemph_override_11_6) |
2569 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2570 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2571
58106b7d 2572 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2573 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2574 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2575 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2576 ddi_translations[level].cri_txdeemph_override_5_0) |
2577 CRI_TXDEEMPH_OVERRIDE_11_6(
2578 ddi_translations[level].cri_txdeemph_override_11_6) |
2579 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2580 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2581
2582 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2583 }
2584
2585 /*
2586 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2587 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2588 * values from table for which TX1 and TX2 enabled.
2589 */
2590 for (ln = 0; ln < 2; ln++) {
58106b7d 2591 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2592 if (link_clock < 300000)
2593 val |= CFG_LOW_RATE_LKREN_EN;
2594 else
2595 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2596 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2597 }
2598
2599 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2600 for (ln = 0; ln < 2; ln++) {
58106b7d 2601 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2602 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2603 if (link_clock <= 500000) {
2604 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2605 } else {
2606 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2607 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2608 }
58106b7d 2609 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2610
58106b7d 2611 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2612 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2613 if (link_clock <= 500000) {
2614 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2615 } else {
2616 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2617 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2618 }
58106b7d 2619 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2620 }
2621
2622 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2623 for (ln = 0; ln < 2; ln++) {
58106b7d 2624 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2625 val |= CRI_CALCINIT;
58106b7d 2626 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2627
58106b7d 2628 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2629 val |= CRI_CALCINIT;
58106b7d 2630 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2631 }
2632}
2633
2634static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2635 int link_clock,
2636 u32 level,
fb5c8e9d
MN		 2637 enum intel_output_type type)
2638{
176597a1 2639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2640 enum port port = encoder->port;
2641
176597a1 2642 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2643 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2644 else
07685c82 2645 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2646}
2647
3d0c5005 2648static u32 translate_signal_level(int signal_levels)
f8896f5d 2649{
97eeb872 2650 int i;
f8896f5d 2651
97eeb872
VS		 2652 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2653 if (index_to_dp_signal_levels[i] == signal_levels)
2654 return i;
f8896f5d
DW		 2655 }
2656
97eeb872
VS		 2657 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2658 signal_levels);
2659
2660 return 0;
f8896f5d
DW		 2661}
2662
3d0c5005 2663static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2664{
3d0c5005 2665 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2666 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2667 DP_TRAIN_PRE_EMPHASIS_MASK);
2668
2669 return translate_signal_level(signal_levels);
2670}
2671
d509af6c 2672u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2673{
2674 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2675 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2676 struct intel_encoder *encoder = &dport->base;
d02ace87 2677 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2678
2dd24a9c 2679 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2680 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2681 level, encoder->type);
fb5c8e9d 2682 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2683 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2684 else
7d4f37b5 2685 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2686
2687 return 0;
2688}
2689
3d0c5005 2690u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2691{
2692 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2693 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2694 struct intel_encoder *encoder = &dport->base;
d02ace87 2695 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2696
b976dc53 2697 if (IS_GEN9_BC(dev_priv))
081dfcfa 2698 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2699
f8896f5d
DW		 2700 return DDI_BUF_TRANS_SELECT(level);
2701}
2702
bb1c7edc 2703static inline
3d0c5005
JN		 2704u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2705 enum port port)
bb1c7edc
MK		 2706{
2707 if (intel_port_is_combophy(dev_priv, port)) {
2708 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2709 } else if (intel_port_is_tc(dev_priv, port)) {
2710 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2711
2712 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2713 }
2714
2715 return 0;
2716}
2717
3b8c0d5b
JN		 2718static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2719 const struct intel_crtc_state *crtc_state)
c27e917e 2720{
3b8c0d5b 2721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2722 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3b8c0d5b
JN		 2723 enum port port = encoder->port;
2724 u32 val;
c27e917e 2725
3b8c0d5b 2726 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2727
3b8c0d5b
JN		 2728 val = I915_READ(DPCLKA_CFGCR0_ICL);
2729 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2730
3b8c0d5b
JN		 2731 if (intel_port_is_combophy(dev_priv, port)) {
2732 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2733 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
c27e917e 2734 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
3b8c0d5b 2735 POSTING_READ(DPCLKA_CFGCR0_ICL);
c27e917e 2736 }
3b8c0d5b
JN		 2737
2738 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2739 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2740
2741 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2742}
2743
3b8c0d5b 2744static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2745{
3b8c0d5b
JN		 2746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2747 enum port port = encoder->port;
2748 u32 val;
c27e917e 2749
3b8c0d5b 2750 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2751
3b8c0d5b
JN		 2752 val = I915_READ(DPCLKA_CFGCR0_ICL);
2753 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2754 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
c27e917e 2755
3b8c0d5b 2756 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2757}
2758
70332ac5
ID		 2759void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2760{
2761 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2762 u32 val;
1dd07e56
ID		 2763 enum port port;
2764 u32 port_mask;
2765 bool ddi_clk_needed;
30f5ccfa
ID		 2766
2767 /*
2768 * In case of DP MST, we sanitize the primary encoder only, not the
2769 * virtual ones.
2770 */
2771 if (encoder->type == INTEL_OUTPUT_DP_MST)
2772 return;
2773
30f5ccfa
ID		 2774 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2775 u8 pipe_mask;
2776 bool is_mst;
2777
2778 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2779 /*
2780 * In the unlikely case that BIOS enables DP in MST mode, just
2781 * warn since our MST HW readout is incomplete.
2782 */
2783 if (WARN_ON(is_mst))
2784 return;
2785 }
70332ac5 2786
1dd07e56
ID		 2787 port_mask = BIT(encoder->port);
2788 ddi_clk_needed = encoder->base.crtc;
70332ac5 2789
1dd07e56
ID		 2790 if (encoder->type == INTEL_OUTPUT_DSI) {
2791 struct intel_encoder *other_encoder;
70332ac5 2792
1dd07e56
ID		 2793 port_mask = intel_dsi_encoder_ports(encoder);
2794 /*
2795 * Sanity check that we haven't incorrectly registered another
2796 * encoder using any of the ports of this DSI encoder.
2797 */
2798 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2799 if (other_encoder == encoder)
2800 continue;
2801
2802 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2803 return;
2804 }
2805 /*
2806 * DSI ports should have their DDI clock ungated when disabled
2807 * and gated when enabled.
2808 */
2809 ddi_clk_needed = !encoder->base.crtc;
2810 }
2811
2812 val = I915_READ(DPCLKA_CFGCR0_ICL);
2813 for_each_port_masked(port, port_mask) {
2814 bool ddi_clk_ungated = !(val &
2815 icl_dpclka_cfgcr0_clk_off(dev_priv,
2816 port));
2817
2818 if (ddi_clk_needed == ddi_clk_ungated)
2819 continue;
2820
2821 /*
2822 * Punt on the case now where clock is gated, but it would
2823 * be needed by the port. Something else is really broken then.
2824 */
2825 if (WARN_ON(ddi_clk_needed))
2826 continue;
2827
2828 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2829 port_name(port));
2830 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2831 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2832 }
70332ac5
ID		 2833}
2834
d7c530b2 2835static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2836 const struct intel_crtc_state *crtc_state)
6441ab5f 2837{
e404ba8d 2838 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2839 enum port port = encoder->port;
3d0c5005 2840 u32 val;
0e5fa646 2841 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2842
c856052a
ACO		 2843 if (WARN_ON(!pll))
2844 return;
2845
04bf68bb 2846 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2847
2dd24a9c 2848 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2849 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2850 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2851 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c27e917e 2852 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2853 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2854 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2855 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2856 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2857 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2858
555e38d2
RV		 2859 /*
2860 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2861 * This step and the step before must be done with separate
2862 * register writes.
2863 */
2864 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2865 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2866 I915_WRITE(DPCLKA_CFGCR0, val);
2867 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2868 /* DDI -> PLL mapping */
efa80add
S		 2869 val = I915_READ(DPLL_CTRL2);
2870
2871 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2872 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2873 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2874 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2875
2876 I915_WRITE(DPLL_CTRL2, val);
5416d871 2877
c56b89f1 2878 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2879 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2880 }
8edcda12
RV		 2881
2882 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2883}
2884
6b8506d5
VS		 2885static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2886{
2887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2888 enum port port = encoder->port;
6b8506d5 2889
2dd24a9c 2890 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2891 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2892 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2893 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2894 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2895 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2896 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2897 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2898 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2899 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2900 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2901 }
6b8506d5
VS		 2902}
2903
cb9ff519
ID		 2904static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2905{
2906 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2907 enum port port = dig_port->base.port;
2908 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
37fc7845 2909 i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
cb9ff519
ID		 2910 u32 val;
2911 int i;
2912
2913 if (tc_port == PORT_TC_NONE)
2914 return;
2915
2916 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2917 val = I915_READ(mg_regs[i]);
2918 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2919 MG_DP_MODE_CFG_TRPWR_GATING |
2920 MG_DP_MODE_CFG_CLNPWR_GATING |
2921 MG_DP_MODE_CFG_DIGPWR_GATING |
2922 MG_DP_MODE_CFG_GAONPWR_GATING;
2923 I915_WRITE(mg_regs[i], val);
2924 }
2925
2926 val = I915_READ(MG_MISC_SUS0(tc_port));
2927 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2928 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2929 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2930 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2931 MG_MISC_SUS0_CFG_TRPWR_GATING |
2932 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2933 MG_MISC_SUS0_CFG_DGPWR_GATING;
2934 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2935}
2936
2937static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2938{
2939 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2940 enum port port = dig_port->base.port;
2941 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2942 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2943 u32 val;
2944 int i;
2945
2946 if (tc_port == PORT_TC_NONE)
2947 return;
2948
2949 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2950 val = I915_READ(mg_regs[i]);
2951 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2952 MG_DP_MODE_CFG_TRPWR_GATING |
2953 MG_DP_MODE_CFG_CLNPWR_GATING |
2954 MG_DP_MODE_CFG_DIGPWR_GATING |
2955 MG_DP_MODE_CFG_GAONPWR_GATING);
2956 I915_WRITE(mg_regs[i], val);
2957 }
2958
2959 val = I915_READ(MG_MISC_SUS0(tc_port));
2960 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2961 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2962 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2963 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2964 MG_MISC_SUS0_CFG_TRPWR_GATING |
2965 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2966 MG_MISC_SUS0_CFG_DGPWR_GATING);
2967 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2968}
2969
93b662d3
ID		 2970static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2971{
2972 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2973 enum port port = intel_dig_port->base.port;
2974 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2975 u32 ln0, ln1, lane_info;
2976
2977 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2978 return;
2979
37fc7845
JRS		 2980 ln0 = I915_READ(MG_DP_MODE(0, port));
2981 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3
ID		 2982
2983 switch (intel_dig_port->tc_type) {
2984 case TC_PORT_TYPEC:
2985 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2986 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2987
2988 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2989 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2990 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2991
2992 switch (lane_info) {
2993 case 0x1:
2994 case 0x4:
2995 break;
2996 case 0x2:
2997 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2998 break;
2999 case 0x3:
3000 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3001 MG_DP_MODE_CFG_DP_X2_MODE;
3002 break;
3003 case 0x8:
3004 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3005 break;
3006 case 0xC:
3007 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3008 MG_DP_MODE_CFG_DP_X2_MODE;
3009 break;
3010 case 0xF:
3011 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012 MG_DP_MODE_CFG_DP_X2_MODE;
3013 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3014 MG_DP_MODE_CFG_DP_X2_MODE;
3015 break;
3016 default:
3017 MISSING_CASE(lane_info);
3018 }
3019 break;
3020
3021 case TC_PORT_LEGACY:
3022 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3023 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3024 break;
3025
3026 default:
3027 MISSING_CASE(intel_dig_port->tc_type);
3028 return;
3029 }
3030
37fc7845
JRS		 3031 I915_WRITE(MG_DP_MODE(0, port), ln0);
3032 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3033}
3034
a322b975
AS		 3035static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3036 const struct intel_crtc_state *crtc_state)
3037{
3038 if (!crtc_state->fec_enable)
3039 return;
3040
3041 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3042 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3043}
3044
5c44b938
AS		 3045static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3046 const struct intel_crtc_state *crtc_state)
3047{
3048 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3049 enum port port = encoder->port;
3050 u32 val;
3051
3052 if (!crtc_state->fec_enable)
3053 return;
3054
3055 val = I915_READ(DP_TP_CTL(port));
3056 val |= DP_TP_CTL_FEC_ENABLE;
3057 I915_WRITE(DP_TP_CTL(port), val);
3058
97a04e0d 3059 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
5c44b938
AS		 3060 DP_TP_STATUS_FEC_ENABLE_LIVE,
3061 DP_TP_STATUS_FEC_ENABLE_LIVE,
3062 1))
3063 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3064}
3065
d6a09cee
AS		 3066static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3067 const struct intel_crtc_state *crtc_state)
3068{
3069 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3070 enum port port = encoder->port;
3071 u32 val;
3072
3073 if (!crtc_state->fec_enable)
3074 return;
3075
3076 val = I915_READ(DP_TP_CTL(port));
3077 val &= ~DP_TP_CTL_FEC_ENABLE;
3078 I915_WRITE(DP_TP_CTL(port), val);
3079 POSTING_READ(DP_TP_CTL(port));
3080}
3081
ba88d153 3082static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3083 const struct intel_crtc_state *crtc_state,
3084 const struct drm_connector_state *conn_state)
e404ba8d 3085{
ba88d153
MN		 3086 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3088 enum port port = encoder->port;
62b69566 3089 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3090 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3091 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3092
45e0327e 3093 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3094
45e0327e
VS		 3095 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3096 crtc_state->lane_count, is_mst);
680b71c2
VS		 3097
3098 intel_edp_panel_on(intel_dp);
32bdc400 3099
0e5fa646 3100 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3101
3102 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3103
93b662d3 3104 icl_program_mg_dp_mode(dig_port);
bc334d91 3105 icl_disable_phy_clock_gating(dig_port);
340a44be 3106
2dd24a9c 3107 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3108 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3109 level, encoder->type);
fb5c8e9d 3110 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3111 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3112 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3113 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3114 else
3a6d84e6 3115 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3116
ba88d153 3117 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3118 if (!is_mst)
3119 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3120 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3121 true);
a322b975 3122 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3123 intel_dp_start_link_train(intel_dp);
3124 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3125 intel_dp_stop_link_train(intel_dp);
afb2c443 3126
5c44b938
AS		 3127 intel_ddi_enable_fec(encoder, crtc_state);
3128
bc334d91
PZ		 3129 icl_enable_phy_clock_gating(dig_port);
3130
2b5cf4ef
ID		 3131 if (!is_mst)
3132 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3133
3134 intel_dsc_enable(encoder, crtc_state);
ba88d153 3135}
901c2daf 3136
ba88d153 3137static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3138 const struct intel_crtc_state *crtc_state,
45e0327e 3139 const struct drm_connector_state *conn_state)
ba88d153 3140{
f99be1b3
VS		 3141 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3142 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3144 enum port port = encoder->port;
ba88d153 3145 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3146 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3147
ba88d153 3148 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3149 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3150
3151 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3152
93b662d3 3153 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3154 icl_disable_phy_clock_gating(dig_port);
3155
2dd24a9c 3156 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3157 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3158 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3159 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3160 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3161 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3162 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3163 else
7ea79333 3164 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3165
cb9ff519
ID		 3166 icl_enable_phy_clock_gating(dig_port);
3167
2f7460a7 3168 if (IS_GEN9_BC(dev_priv))
081dfcfa 3169 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3170
c7373764
ID		 3171 intel_ddi_enable_pipe_clock(crtc_state);
3172
790ea70c 3173 intel_dig_port->set_infoframes(encoder,
45e0327e 3174 crtc_state->has_infoframe,
f99be1b3 3175 crtc_state, conn_state);
ba88d153 3176}
32bdc400 3177
1524e93e 3178static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3179 const struct intel_crtc_state *crtc_state,
5f88a9c6 3180 const struct drm_connector_state *conn_state)
ba88d153 3181{
45e0327e
VS		 3182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3184 enum pipe pipe = crtc->pipe;
30cf6db8 3185
1939ba51
VS		 3186 /*
3187 * When called from DP MST code:
3188 * - conn_state will be NULL
3189 * - encoder will be the main encoder (ie. mst->primary)
3190 * - the main connector associated with this port
3191 * won't be active or linked to a crtc
3192 * - crtc_state will be the state of the first stream to
3193 * be activated on this port, and it may not be the same
3194 * stream that will be deactivated last, but each stream
3195 * should have a state that is identical when it comes to
3196 * the DP link parameteres
3197 */
3198
45e0327e 3199 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3200
3b8c0d5b
JN		 3201 if (INTEL_GEN(dev_priv) >= 11)
3202 icl_map_plls_to_ports(encoder, crtc_state);
3203
364a3fe1
JN		 3204 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3205
06c812d7 3206 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3207 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3208 } else {
3209 struct intel_lspcon *lspcon =
3210 enc_to_intel_lspcon(&encoder->base);
3211
45e0327e 3212 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3213 if (lspcon->active) {
3214 struct intel_digital_port *dig_port =
3215 enc_to_dig_port(&encoder->base);
3216
3217 dig_port->set_infoframes(encoder,
3218 crtc_state->has_infoframe,
3219 crtc_state, conn_state);
3220 }
3221 }
6441ab5f
PZ		 3222}
3223
d6a09cee
AS		 3224static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3225 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3226{
3227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3228 enum port port = encoder->port;
e725f645
VS		 3229 bool wait = false;
3230 u32 val;
3231
3232 val = I915_READ(DDI_BUF_CTL(port));
3233 if (val & DDI_BUF_CTL_ENABLE) {
3234 val &= ~DDI_BUF_CTL_ENABLE;
3235 I915_WRITE(DDI_BUF_CTL(port), val);
3236 wait = true;
3237 }
3238
3239 val = I915_READ(DP_TP_CTL(port));
3240 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3241 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3242 I915_WRITE(DP_TP_CTL(port), val);
3243
d6a09cee
AS		 3244 /* Disable FEC in DP Sink */
3245 intel_ddi_disable_fec_state(encoder, crtc_state);
3246
e725f645
VS		 3247 if (wait)
3248 intel_wait_ddi_buf_idle(dev_priv, port);
3249}
3250
f45f3da7
VS		 3251static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3252 const struct intel_crtc_state *old_crtc_state,
3253 const struct drm_connector_state *old_conn_state)
6441ab5f 3254{
f45f3da7
VS		 3255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3256 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3257 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3258 bool is_mst = intel_crtc_has_type(old_crtc_state,
3259 INTEL_OUTPUT_DP_MST);
2886e93f 3260
2b5cf4ef
ID		 3261 if (!is_mst) {
3262 intel_ddi_disable_pipe_clock(old_crtc_state);
3263 /*
3264 * Power down sink before disabling the port, otherwise we end
3265 * up getting interrupts from the sink on detecting link loss.
3266 */
be1c63c8 3267 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3268 }
c5f93fcf 3269
d6a09cee 3270 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3271
f45f3da7
VS		 3272 intel_edp_panel_vdd_on(intel_dp);
3273 intel_edp_panel_off(intel_dp);
a836bdf9 3274
0e6e0be4
CW		 3275 intel_display_power_put_unchecked(dev_priv,
3276 dig_port->ddi_io_power_domain);
c5f93fcf 3277
f45f3da7
VS		 3278 intel_ddi_clk_disable(encoder);
3279}
c5f93fcf 3280
f45f3da7
VS		 3281static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3282 const struct intel_crtc_state *old_crtc_state,
3283 const struct drm_connector_state *old_conn_state)
3284{
3285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3286 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3287 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3288
790ea70c 3289 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3290 old_crtc_state, old_conn_state);
3291
afb2c443
ID		 3292 intel_ddi_disable_pipe_clock(old_crtc_state);
3293
d6a09cee 3294 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3295
0e6e0be4
CW		 3296 intel_display_power_put_unchecked(dev_priv,
3297 dig_port->ddi_io_power_domain);
b2ccb822 3298
f45f3da7
VS		 3299 intel_ddi_clk_disable(encoder);
3300
3301 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3302}
3303
3304static void intel_ddi_post_disable(struct intel_encoder *encoder,
3305 const struct intel_crtc_state *old_crtc_state,
3306 const struct drm_connector_state *old_conn_state)
3307{
3b8c0d5b
JN		 3308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3309
f45f3da7 3310 /*
1939ba51
VS		 3311 * When called from DP MST code:
3312 * - old_conn_state will be NULL
3313 * - encoder will be the main encoder (ie. mst->primary)
3314 * - the main connector associated with this port
3315 * won't be active or linked to a crtc
3316 * - old_crtc_state will be the state of the last stream to
3317 * be deactivated on this port, and it may not be the same
3318 * stream that was activated last, but each stream
3319 * should have a state that is identical when it comes to
3320 * the DP link parameteres
f45f3da7 3321 */
1939ba51
VS		 3322
3323 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3324 intel_ddi_post_disable_hdmi(encoder,
3325 old_crtc_state, old_conn_state);
3326 else
3327 intel_ddi_post_disable_dp(encoder,
3328 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3329
3330 if (INTEL_GEN(dev_priv) >= 11)
3331 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3332}
3333
1524e93e 3334void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3335 const struct intel_crtc_state *old_crtc_state,
3336 const struct drm_connector_state *old_conn_state)
b7076546 3337{
1524e93e 3338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3339 u32 val;
b7076546
ML		 3340
3341 /*
3342 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3343 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3344 * step 13 is the correct place for it. Step 18 is where it was
3345 * originally before the BUN.
3346 */
3347 val = I915_READ(FDI_RX_CTL(PIPE_A));
3348 val &= ~FDI_RX_ENABLE;
3349 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3350
d6a09cee 3351 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3352 intel_ddi_clk_disable(encoder);
b7076546
ML		 3353
3354 val = I915_READ(FDI_RX_MISC(PIPE_A));
3355 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3356 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3357 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3358
3359 val = I915_READ(FDI_RX_CTL(PIPE_A));
3360 val &= ~FDI_PCDCLK;
3361 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3362
3363 val = I915_READ(FDI_RX_CTL(PIPE_A));
3364 val &= ~FDI_RX_PLL_ENABLE;
3365 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3366}
3367
15d05f0e
VS		 3368static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3369 const struct intel_crtc_state *crtc_state,
3370 const struct drm_connector_state *conn_state)
72662e10 3371{
15d05f0e
VS		 3372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3373 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3374 enum port port = encoder->port;
72662e10 3375
15d05f0e
VS		 3376 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3377 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3378
15d05f0e
VS		 3379 intel_edp_backlight_on(crtc_state, conn_state);
3380 intel_psr_enable(intel_dp, crtc_state);
3381 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3382
15d05f0e
VS		 3383 if (crtc_state->has_audio)
3384 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3385}
3386
8f19b401
ID		 3387static i915_reg_t
3388gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3389 enum port port)
3390{
3391 static const i915_reg_t regs[] = {
3392 [PORT_A] = CHICKEN_TRANS_EDP,
3393 [PORT_B] = CHICKEN_TRANS_A,
3394 [PORT_C] = CHICKEN_TRANS_B,
3395 [PORT_D] = CHICKEN_TRANS_C,
3396 [PORT_E] = CHICKEN_TRANS_A,
3397 };
3398
3399 WARN_ON(INTEL_GEN(dev_priv) < 9);
3400
3401 if (WARN_ON(port < PORT_A || port > PORT_E))
3402 port = PORT_A;
3403
3404 return regs[port];
3405}
3406
15d05f0e
VS		 3407static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3408 const struct intel_crtc_state *crtc_state,
3409 const struct drm_connector_state *conn_state)
3410{
3411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3412 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3413 struct drm_connector *connector = conn_state->connector;
0fce04c8 3414 enum port port = encoder->port;
15d05f0e 3415
277ab5ab
VS		 3416 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3417 crtc_state->hdmi_high_tmds_clock_ratio,
3418 crtc_state->hdmi_scrambling))
3419 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3420 connector->base.id, connector->name);
15d05f0e 3421
0519c102
VS		 3422 /* Display WA #1143: skl,kbl,cfl */
3423 if (IS_GEN9_BC(dev_priv)) {
3424 /*
3425 * For some reason these chicken bits have been
3426 * stuffed into a transcoder register, event though
3427 * the bits affect a specific DDI port rather than
3428 * a specific transcoder.
3429 */
8f19b401 3430 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3431 u32 val;
3432
8f19b401 3433 val = I915_READ(reg);
0519c102
VS		 3434
3435 if (port == PORT_E)
3436 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3437 DDIE_TRAINING_OVERRIDE_VALUE;
3438 else
3439 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3440 DDI_TRAINING_OVERRIDE_VALUE;
3441
8f19b401
ID		 3442 I915_WRITE(reg, val);
3443 POSTING_READ(reg);
0519c102
VS		 3444
3445 udelay(1);
3446
3447 if (port == PORT_E)
3448 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3449 DDIE_TRAINING_OVERRIDE_VALUE);
3450 else
3451 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3452 DDI_TRAINING_OVERRIDE_VALUE);
3453
8f19b401 3454 I915_WRITE(reg, val);
0519c102
VS		 3455 }
3456
15d05f0e
VS		 3457 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3458 * are ignored so nothing special needs to be done besides
3459 * enabling the port.
3460 */
3461 I915_WRITE(DDI_BUF_CTL(port),
3462 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3463
15d05f0e
VS		 3464 if (crtc_state->has_audio)
3465 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3466}
3467
3468static void intel_enable_ddi(struct intel_encoder *encoder,
3469 const struct intel_crtc_state *crtc_state,
3470 const struct drm_connector_state *conn_state)
3471{
3472 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3473 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3474 else
3475 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3476
3477 /* Enable hdcp if it's desired */
3478 if (conn_state->content_protection ==
3479 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3480 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3481}
3482
33f083f0
VS		 3483static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3484 const struct intel_crtc_state *old_crtc_state,
3485 const struct drm_connector_state *old_conn_state)
5ab432ef 3486{
33f083f0 3487 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3488
edb2e530
VS		 3489 intel_dp->link_trained = false;
3490
37255d8d 3491 if (old_crtc_state->has_audio)
8ec47de2
VS		 3492 intel_audio_codec_disable(encoder,
3493 old_crtc_state, old_conn_state);
2831d842 3494
33f083f0
VS		 3495 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3496 intel_psr_disable(intel_dp, old_crtc_state);
3497 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3498 /* Disable the decompression in DP Sink */
3499 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3500 false);
33f083f0 3501}
15953637 3502
33f083f0
VS		 3503static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3504 const struct intel_crtc_state *old_crtc_state,
3505 const struct drm_connector_state *old_conn_state)
3506{
277ab5ab
VS		 3507 struct drm_connector *connector = old_conn_state->connector;
3508
33f083f0 3509 if (old_crtc_state->has_audio)
8ec47de2
VS		 3510 intel_audio_codec_disable(encoder,
3511 old_crtc_state, old_conn_state);
d6c50ff8 3512
277ab5ab
VS		 3513 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3514 false, false))
3515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3516 connector->base.id, connector->name);
33f083f0
VS		 3517}
3518
3519static void intel_disable_ddi(struct intel_encoder *encoder,
3520 const struct intel_crtc_state *old_crtc_state,
3521 const struct drm_connector_state *old_conn_state)
3522{
ee5e5e7a
SP		 3523 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3524
33f083f0
VS		 3525 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3526 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3527 else
3528 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3529}
79f689aa 3530
2ef82327
HG		 3531static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3532 const struct intel_crtc_state *crtc_state,
3533 const struct drm_connector_state *conn_state)
3534{
3535 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3536
5aa2c9ae
VS		 3537 intel_ddi_set_pipe_settings(crtc_state);
3538
23ec9f52 3539 intel_psr_update(intel_dp, crtc_state);
2ef82327 3540 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3541
3542 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3543}
3544
3545static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3546 const struct intel_crtc_state *crtc_state,
3547 const struct drm_connector_state *conn_state)
3548{
3549 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3550 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1
R		 3551
3552 if (conn_state->content_protection ==
3553 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3554 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3555 else if (conn_state->content_protection ==
3556 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3557 intel_hdcp_disable(to_intel_connector(conn_state->connector));
2ef82327
HG		 3558}
3559
03ad7d88
MN		 3560static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3561 const struct intel_crtc_state *pipe_config,
3562 enum port port)
3563{
3564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3565 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3566 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3567 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3568 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3569
3570 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3571 switch (pipe_config->lane_count) {
3572 case 1:
3573 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3574 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3575 break;
3576 case 2:
3577 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3578 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3579 break;
3580 case 4:
3581 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3582 break;
3583 default:
3584 MISSING_CASE(pipe_config->lane_count);
3585 }
3586 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3587}
3588
bdaa29b6
ID		 3589static void
3590intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3591 const struct intel_crtc_state *crtc_state,
3592 const struct drm_connector_state *conn_state)
03ad7d88 3593{
bdaa29b6 3594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3595 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bdaa29b6
ID		 3596 enum port port = encoder->port;
3597
8e4a3ad9
ID		 3598 if (intel_crtc_has_dp_encoder(crtc_state) ||
3599 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6
ID		 3600 intel_display_power_get(dev_priv,
3601 intel_ddi_main_link_aux_domain(dig_port));
3602
3603 if (IS_GEN9_LP(dev_priv))
3604 bxt_ddi_phy_set_lane_optim_mask(encoder,
3605 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3606
3607 /*
3608 * Program the lane count for static/dynamic connections on Type-C ports.
3609 * Skip this step for TBT.
3610 */
3611 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3612 dig_port->tc_type == TC_PORT_TBT)
3613 return;
3614
bdaa29b6
ID		 3615 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3616}
3617
3618static void
3619intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3620 const struct intel_crtc_state *crtc_state,
3621 const struct drm_connector_state *conn_state)
3622{
3623 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3624 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3625
3626 if (intel_crtc_has_dp_encoder(crtc_state) ||
3627 intel_port_is_tc(dev_priv, encoder->port))
0e6e0be4
CW		 3628 intel_display_power_put_unchecked(dev_priv,
3629 intel_ddi_main_link_aux_domain(dig_port));
03ad7d88
MN		 3630}
3631
ad64217b 3632void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3633{
ad64217b
ACO		 3634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3635 struct drm_i915_private *dev_priv =
3636 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3637 enum port port = intel_dig_port->base.port;
3d0c5005 3638 u32 val;
f3e227df 3639 bool wait = false;
c19b0669
PZ		 3640
3641 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3642 val = I915_READ(DDI_BUF_CTL(port));
3643 if (val & DDI_BUF_CTL_ENABLE) {
3644 val &= ~DDI_BUF_CTL_ENABLE;
3645 I915_WRITE(DDI_BUF_CTL(port), val);
3646 wait = true;
3647 }
3648
3649 val = I915_READ(DP_TP_CTL(port));
3650 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3651 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3652 I915_WRITE(DP_TP_CTL(port), val);
3653 POSTING_READ(DP_TP_CTL(port));
3654
3655 if (wait)
3656 intel_wait_ddi_buf_idle(dev_priv, port);
3657 }
3658
0e32b39c 3659 val = DP_TP_CTL_ENABLE |
c19b0669 3660 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3661 if (intel_dp->link_mst)
0e32b39c
DA		 3662 val |= DP_TP_CTL_MODE_MST;
3663 else {
3664 val |= DP_TP_CTL_MODE_SST;
3665 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3666 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3667 }
c19b0669
PZ		 3668 I915_WRITE(DP_TP_CTL(port), val);
3669 POSTING_READ(DP_TP_CTL(port));
3670
3671 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3672 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3673 POSTING_READ(DDI_BUF_CTL(port));
3674
3675 udelay(600);
3676}
00c09d70 3677
2085cc5d
VS		 3678static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3679 enum transcoder cpu_transcoder)
9935f7fa 3680{
2085cc5d
VS		 3681 if (cpu_transcoder == TRANSCODER_EDP)
3682 return false;
9935f7fa 3683
2085cc5d
VS		 3684 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3685 return false;
3686
3687 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3688 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3689}
3690
53e9bf5e
VS		 3691void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3692 struct intel_crtc_state *crtc_state)
3693{
2dd24a9c 3694 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3695 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3696 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3697 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3698}
3699
6801c18c 3700void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3701 struct intel_crtc_state *pipe_config)
045ac3b5 3702{
fac5e23e 3703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3704 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3705 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3706 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3707 u32 temp, flags = 0;
3708
4d1de975
JN		 3709 /* XXX: DSI transcoder paranoia */
3710 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3711 return;
3712
045ac3b5
JB		 3713 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3714 if (temp & TRANS_DDI_PHSYNC)
3715 flags |= DRM_MODE_FLAG_PHSYNC;
3716 else
3717 flags |= DRM_MODE_FLAG_NHSYNC;
3718 if (temp & TRANS_DDI_PVSYNC)
3719 flags |= DRM_MODE_FLAG_PVSYNC;
3720 else
3721 flags |= DRM_MODE_FLAG_NVSYNC;
3722
2d112de7 3723 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3724
3725 switch (temp & TRANS_DDI_BPC_MASK) {
3726 case TRANS_DDI_BPC_6:
3727 pipe_config->pipe_bpp = 18;
3728 break;
3729 case TRANS_DDI_BPC_8:
3730 pipe_config->pipe_bpp = 24;
3731 break;
3732 case TRANS_DDI_BPC_10:
3733 pipe_config->pipe_bpp = 30;
3734 break;
3735 case TRANS_DDI_BPC_12:
3736 pipe_config->pipe_bpp = 36;
3737 break;
3738 default:
3739 break;
3740 }
eb14cb74
VS		 3741
3742 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3743 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3744 pipe_config->has_hdmi_sink = true;
f99be1b3 3745 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3746
e5e70d4a
VS		 3747 pipe_config->infoframes.enable |=
3748 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3749
3750 if (pipe_config->infoframes.enable)
bbd440fb 3751 pipe_config->has_infoframe = true;
15953637 3752
ab2cb2cb 3753 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 3754 pipe_config->hdmi_scrambling = true;
3755 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3756 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3757 /* fall through */
eb14cb74 3758 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3759 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3760 pipe_config->lane_count = 4;
3761 break;
eb14cb74 3762 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3763 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3764 break;
3765 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3766 if (encoder->type == INTEL_OUTPUT_EDP)
3767 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3768 else
3769 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3770 pipe_config->lane_count =
3771 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3772 intel_dp_get_m_n(intel_crtc, pipe_config);
3773 break;
eb14cb74 3774 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3775 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3776 pipe_config->lane_count =
3777 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3778 intel_dp_get_m_n(intel_crtc, pipe_config);
3779 break;
3780 default:
3781 break;
3782 }
10214420 3783
9935f7fa 3784 pipe_config->has_audio =
2085cc5d 3785 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3786
6aa23e65
JN		 3787 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3788 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3789 /*
3790 * This is a big fat ugly hack.
3791 *
3792 * Some machines in UEFI boot mode provide us a VBT that has 18
3793 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3794 * unknown we fail to light up. Yet the same BIOS boots up with
3795 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3796 * max, not what it tells us to use.
3797 *
3798 * Note: This will still be broken if the eDP panel is not lit
3799 * up by the BIOS, and thus we can't get the mode at module
3800 * load.
3801 */
3802 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3803 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3804 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3805 }
11578553 3806
22606a18 3807 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3808
cc3f90f0 3809 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3810 pipe_config->lane_lat_optim_mask =
3811 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3812
3813 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 3814
3815 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3816
3817 intel_read_infoframe(encoder, pipe_config,
3818 HDMI_INFOFRAME_TYPE_AVI,
3819 &pipe_config->infoframes.avi);
3820 intel_read_infoframe(encoder, pipe_config,
3821 HDMI_INFOFRAME_TYPE_SPD,
3822 &pipe_config->infoframes.spd);
3823 intel_read_infoframe(encoder, pipe_config,
3824 HDMI_INFOFRAME_TYPE_VENDOR,
3825 &pipe_config->infoframes.hdmi);
045ac3b5
JB		 3826}
3827
7e732cac
VS		 3828static enum intel_output_type
3829intel_ddi_compute_output_type(struct intel_encoder *encoder,
3830 struct intel_crtc_state *crtc_state,
3831 struct drm_connector_state *conn_state)
3832{
3833 switch (conn_state->connector->connector_type) {
3834 case DRM_MODE_CONNECTOR_HDMIA:
3835 return INTEL_OUTPUT_HDMI;
3836 case DRM_MODE_CONNECTOR_eDP:
3837 return INTEL_OUTPUT_EDP;
3838 case DRM_MODE_CONNECTOR_DisplayPort:
3839 return INTEL_OUTPUT_DP;
3840 default:
3841 MISSING_CASE(conn_state->connector->connector_type);
3842 return INTEL_OUTPUT_UNUSED;
3843 }
3844}
3845
204474a6
LP		 3846static int intel_ddi_compute_config(struct intel_encoder *encoder,
3847 struct intel_crtc_state *pipe_config,
3848 struct drm_connector_state *conn_state)
00c09d70 3849{
fac5e23e 3850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3851 enum port port = encoder->port;
95a7a2ae 3852 int ret;
00c09d70 3853
bc7e3525 3854 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 3855 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3856
7e732cac 3857 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3858 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3859 else
0a478c27 3860 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 3861
cc3f90f0 3862 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae 3863 pipe_config->lane_lat_optim_mask =
5161d058 3864 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3865
53e9bf5e
VS		 3866 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3867
95a7a2ae
ID		 3868 return ret;
3869
00c09d70
PZ		 3870}
3871
f6bff60e
ID		 3872static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3873{
3874 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3875 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3876
3877 intel_dp_encoder_suspend(encoder);
3878
3879 /*
3880 * TODO: disconnect also from USB DP alternate mode once we have a
3881 * way to handle the modeset restore in that mode during resume
3882 * even if the sink has disappeared while being suspended.
3883 */
3884 if (dig_port->tc_legacy_port)
3885 icl_tc_phy_disconnect(i915, dig_port);
3886}
3887
3888static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3889{
3890 struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3891 struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3892
3893 if (intel_port_is_tc(i915, dig_port->base.port))
3894 intel_digital_port_connected(&dig_port->base);
3895
3896 intel_dp_encoder_reset(drm_encoder);
3897}
3898
3899static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3900{
3901 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3902 struct drm_i915_private *i915 = to_i915(encoder->dev);
3903
3904 intel_dp_encoder_flush_work(encoder);
3905
3906 if (intel_port_is_tc(i915, dig_port->base.port))
3907 icl_tc_phy_disconnect(i915, dig_port);
3908
3909 drm_encoder_cleanup(encoder);
3910 kfree(dig_port);
3911}
3912
00c09d70 3913static const struct drm_encoder_funcs intel_ddi_funcs = {
f6bff60e
ID		 3914 .reset = intel_ddi_encoder_reset,
3915 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 3916};
3917
4a28ae58
PZ		 3918static struct intel_connector *
3919intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3920{
3921 struct intel_connector *connector;
8f4f2797 3922 enum port port = intel_dig_port->base.port;
4a28ae58 3923
9bdbd0b9 3924 connector = intel_connector_alloc();
4a28ae58
PZ		 3925 if (!connector)
3926 return NULL;
3927
3928 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3929 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3930 kfree(connector);
3931 return NULL;
3932 }
3933
3934 return connector;
3935}
3936
dba14b27
VS		 3937static int modeset_pipe(struct drm_crtc *crtc,
3938 struct drm_modeset_acquire_ctx *ctx)
3939{
3940 struct drm_atomic_state *state;
3941 struct drm_crtc_state *crtc_state;
3942 int ret;
3943
3944 state = drm_atomic_state_alloc(crtc->dev);
3945 if (!state)
3946 return -ENOMEM;
3947
3948 state->acquire_ctx = ctx;
3949
3950 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3951 if (IS_ERR(crtc_state)) {
3952 ret = PTR_ERR(crtc_state);
3953 goto out;
3954 }
3955
b8fe992a 3956 crtc_state->connectors_changed = true;
dba14b27 3957
dba14b27 3958 ret = drm_atomic_commit(state);
a551cd66 3959out:
dba14b27
VS		 3960 drm_atomic_state_put(state);
3961
3962 return ret;
3963}
3964
3965static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3966 struct drm_modeset_acquire_ctx *ctx)
3967{
3968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3969 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3970 struct intel_connector *connector = hdmi->attached_connector;
3971 struct i2c_adapter *adapter =
3972 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3973 struct drm_connector_state *conn_state;
3974 struct intel_crtc_state *crtc_state;
3975 struct intel_crtc *crtc;
3976 u8 config;
3977 int ret;
3978
3979 if (!connector || connector->base.status != connector_status_connected)
3980 return 0;
3981
3982 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3983 ctx);
3984 if (ret)
3985 return ret;
3986
3987 conn_state = connector->base.state;
3988
3989 crtc = to_intel_crtc(conn_state->crtc);
3990 if (!crtc)
3991 return 0;
3992
3993 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3994 if (ret)
3995 return ret;
3996
3997 crtc_state = to_intel_crtc_state(crtc->base.state);
3998
3999 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4000
4001 if (!crtc_state->base.active)
4002 return 0;
4003
4004 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4005 !crtc_state->hdmi_scrambling)
4006 return 0;
4007
4008 if (conn_state->commit &&
4009 !try_wait_for_completion(&conn_state->commit->hw_done))
4010 return 0;
4011
4012 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4013 if (ret < 0) {
4014 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4015 return 0;
4016 }
4017
4018 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4019 crtc_state->hdmi_high_tmds_clock_ratio &&
4020 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4021 crtc_state->hdmi_scrambling)
4022 return 0;
4023
4024 /*
4025 * HDMI 2.0 says that one should not send scrambled data
4026 * prior to configuring the sink scrambling, and that
4027 * TMDS clock/data transmission should be suspended when
4028 * changing the TMDS clock rate in the sink. So let's
4029 * just do a full modeset here, even though some sinks
4030 * would be perfectly happy if were to just reconfigure
4031 * the SCDC settings on the fly.
4032 */
4033 return modeset_pipe(&crtc->base, ctx);
4034}
4035
4036static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4037 struct intel_connector *connector)
4038{
4039 struct drm_modeset_acquire_ctx ctx;
4040 bool changed;
4041 int ret;
4042
4043 changed = intel_encoder_hotplug(encoder, connector);
4044
4045 drm_modeset_acquire_init(&ctx, 0);
4046
4047 for (;;) {
c85d200e
VS		 4048 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4049 ret = intel_hdmi_reset_link(encoder, &ctx);
4050 else
4051 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4052
4053 if (ret == -EDEADLK) {
4054 drm_modeset_backoff(&ctx);
4055 continue;
4056 }
4057
4058 break;
4059 }
4060
4061 drm_modeset_drop_locks(&ctx);
4062 drm_modeset_acquire_fini(&ctx);
4063 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4064
4065 return changed;
4066}
4067
4a28ae58
PZ		 4068static struct intel_connector *
4069intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4070{
4071 struct intel_connector *connector;
8f4f2797 4072 enum port port = intel_dig_port->base.port;
4a28ae58 4073
9bdbd0b9 4074 connector = intel_connector_alloc();
4a28ae58
PZ		 4075 if (!connector)
4076 return NULL;
4077
4078 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4079 intel_hdmi_init_connector(intel_dig_port, connector);
4080
4081 return connector;
4082}
4083
436009b5
RV		 4084static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4085{
4086 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4087
8f4f2797 4088 if (dport->base.port != PORT_A)
436009b5
RV		 4089 return false;
4090
4091 if (dport->saved_port_bits & DDI_A_4_LANES)
4092 return false;
4093
4094 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4095 * supported configuration
4096 */
4097 if (IS_GEN9_LP(dev_priv))
4098 return true;
4099
4100 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4101 * one who does also have a full A/E split called
4102 * DDI_F what makes DDI_E useless. However for this
4103 * case let's trust VBT info.
4104 */
4105 if (IS_CANNONLAKE(dev_priv) &&
4106 !intel_bios_is_port_present(dev_priv, PORT_E))
4107 return true;
4108
4109 return false;
4110}
4111
3d2011cf
MK		 4112static int
4113intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4114{
4115 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4116 enum port port = intel_dport->base.port;
4117 int max_lanes = 4;
4118
4119 if (INTEL_GEN(dev_priv) >= 11)
4120 return max_lanes;
4121
4122 if (port == PORT_A || port == PORT_E) {
4123 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4124 max_lanes = port == PORT_A ? 4 : 0;
4125 else
4126 /* Both A and E share 2 lanes */
4127 max_lanes = 2;
4128 }
4129
4130 /*
4131 * Some BIOS might fail to set this bit on port A if eDP
4132 * wasn't lit up at boot. Force this bit set when needed
4133 * so we use the proper lane count for our calculations.
4134 */
4135 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4136 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4137 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4138 max_lanes = 4;
4139 }
4140
4141 return max_lanes;
4142}
4143
c39055b0 4144void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4145{
f6bff60e
ID		 4146 struct ddi_vbt_port_info *port_info =
4147 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4148 struct intel_digital_port *intel_dig_port;
4149 struct intel_encoder *intel_encoder;
4150 struct drm_encoder *encoder;
ff662124 4151 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4152 enum pipe pipe;
10e7bec3 4153
f6bff60e
ID		 4154 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4155 init_dp = port_info->supports_dp;
ff662124
SS		 4156
4157 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4158 /*
4159 * Lspcon device needs to be driven with DP connector
4160 * with special detection sequence. So make sure DP
4161 * is initialized before lspcon.
4162 */
4163 init_dp = true;
4164 init_lspcon = true;
4165 init_hdmi = false;
4166 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4167 }
4168
311a2094 4169 if (!init_dp && !init_hdmi) {
500ea70d 4170 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4171 port_name(port));
500ea70d 4172 return;
311a2094 4173 }
00c09d70 4174
b14c5679 4175 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4176 if (!intel_dig_port)
4177 return;
4178
00c09d70
PZ		 4179 intel_encoder = &intel_dig_port->base;
4180 encoder = &intel_encoder->base;
4181
c39055b0 4182 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4183 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4184
c85d200e 4185 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4186 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4187 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4188 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4189 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4190 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4191 intel_encoder->pre_enable = intel_ddi_pre_enable;
4192 intel_encoder->disable = intel_disable_ddi;
4193 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4194 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4195 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4196 intel_encoder->get_config = intel_ddi_get_config;
f6bff60e 4197 intel_encoder->suspend = intel_ddi_encoder_suspend;
62b69566 4198 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4199 intel_encoder->type = INTEL_OUTPUT_DDI;
4200 intel_encoder->power_domain = intel_port_to_power_domain(port);
4201 intel_encoder->port = port;
3d2011cf 4202 intel_encoder->cloneable = 0;
570b16b5
MK		 4203 for_each_pipe(dev_priv, pipe)
4204 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4205
1e6aa7e5
JN		 4206 if (INTEL_GEN(dev_priv) >= 11)
4207 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4208 DDI_BUF_PORT_REVERSAL;
4209 else
4210 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4211 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4212 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4213 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4214 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4215
f6bff60e
ID		 4216 intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4217 !port_info->supports_typec_usb &&
4218 !port_info->supports_tbt;
4219
62b69566
ACO		 4220 switch (port) {
4221 case PORT_A:
4222 intel_dig_port->ddi_io_power_domain =
4223 POWER_DOMAIN_PORT_DDI_A_IO;
4224 break;
4225 case PORT_B:
4226 intel_dig_port->ddi_io_power_domain =
4227 POWER_DOMAIN_PORT_DDI_B_IO;
4228 break;
4229 case PORT_C:
4230 intel_dig_port->ddi_io_power_domain =
4231 POWER_DOMAIN_PORT_DDI_C_IO;
4232 break;
4233 case PORT_D:
4234 intel_dig_port->ddi_io_power_domain =
4235 POWER_DOMAIN_PORT_DDI_D_IO;
4236 break;
4237 case PORT_E:
4238 intel_dig_port->ddi_io_power_domain =
4239 POWER_DOMAIN_PORT_DDI_E_IO;
4240 break;
9787e835
RV		 4241 case PORT_F:
4242 intel_dig_port->ddi_io_power_domain =
4243 POWER_DOMAIN_PORT_DDI_F_IO;
4244 break;
62b69566
ACO		 4245 default:
4246 MISSING_CASE(port);
4247 }
4248
f68d697e
CW		 4249 if (init_dp) {
4250 if (!intel_ddi_init_dp_connector(intel_dig_port))
4251 goto err;
13cf5504 4252
f68d697e 4253 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4254 }
21a8e6a4 4255
311a2094
PZ		 4256 /* In theory we don't need the encoder->type check, but leave it just in
4257 * case we have some really bad VBTs... */
f68d697e
CW		 4258 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4259 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4260 goto err;
21a8e6a4 4261 }
f68d697e 4262
ff662124
SS		 4263 if (init_lspcon) {
4264 if (lspcon_init(intel_dig_port))
4265 /* TODO: handle hdmi info frame part */
4266 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4267 port_name(port));
4268 else
4269 /*
4270 * LSPCON init faied, but DP init was success, so
4271 * lets try to drive as DP++ port.
4272 */
4273 DRM_ERROR("LSPCON init failed on port %c\n",
4274 port_name(port));
4275 }
4276
06c812d7 4277 intel_infoframe_init(intel_dig_port);
f6bff60e
ID		 4278
4279 if (intel_port_is_tc(dev_priv, port))
4280 intel_digital_port_connected(intel_encoder);
4281
f68d697e
CW		 4282 return;
4283
4284err:
4285 drm_encoder_cleanup(encoder);
4286 kfree(intel_dig_port);
00c09d70 4287}
Ubuntu Hirsute Linux kernel mirror