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Merge tag 'drm-for-v4.13' into drm-intel-next-queued
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b
VK		 303struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4
RV		 356struct cnl_ddi_buf_trans {
357 u32 dw2_swing_sel;
358 u32 dw7_n_scalar;
359 u32 dw4_cursor_coeff;
360 u32 dw4_post_cursor_2;
361 u32 dw4_post_cursor_1;
362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
da411a48 547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
da411a48
RV		 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
f8896f5d 565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 566 return skl_u_ddi_translations_edp;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 569 return skl_ddi_translations_edp;
f8896f5d
DW		 570 }
571 }
cd1101cb 572
da411a48 573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 577}
578
579static const struct ddi_buf_trans *
78ab0bae 580skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 581{
78ab0bae 582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 584 return skl_y_ddi_translations_hdmi;
f8896f5d 585 } else {
f8896f5d 586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 587 return skl_ddi_translations_hdmi;
f8896f5d 588 }
f8896f5d
DW		 589}
590
8d8bb85e
VS		 591static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
592{
593 int n_hdmi_entries;
594 int hdmi_level;
595 int hdmi_default_entry;
596
597 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
598
cc3f90f0 599 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 600 return hdmi_level;
601
b976dc53 602 if (IS_GEN9_BC(dev_priv)) {
8d8bb85e
VS		 603 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
604 hdmi_default_entry = 8;
605 } else if (IS_BROADWELL(dev_priv)) {
606 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
607 hdmi_default_entry = 7;
608 } else if (IS_HASWELL(dev_priv)) {
609 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
610 hdmi_default_entry = 6;
611 } else {
612 WARN(1, "ddi translation table missing\n");
613 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
614 hdmi_default_entry = 7;
615 }
616
617 /* Choose a good default if VBT is badly populated */
618 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
619 hdmi_level >= n_hdmi_entries)
620 hdmi_level = hdmi_default_entry;
621
622 return hdmi_level;
623}
624
7d1c42e6
VS		 625static const struct ddi_buf_trans *
626intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
627 int *n_entries)
628{
da411a48 629 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
7d1c42e6
VS		 630 return kbl_get_buf_trans_dp(dev_priv, n_entries);
631 } else if (IS_SKYLAKE(dev_priv)) {
632 return skl_get_buf_trans_dp(dev_priv, n_entries);
633 } else if (IS_BROADWELL(dev_priv)) {
634 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
635 return bdw_ddi_translations_dp;
636 } else if (IS_HASWELL(dev_priv)) {
637 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
638 return hsw_ddi_translations_dp;
639 }
640
641 *n_entries = 0;
642 return NULL;
643}
644
645static const struct ddi_buf_trans *
646intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
647 int *n_entries)
648{
da411a48 649 if (IS_GEN9_BC(dev_priv)) {
7d1c42e6
VS		 650 return skl_get_buf_trans_edp(dev_priv, n_entries);
651 } else if (IS_BROADWELL(dev_priv)) {
652 return bdw_get_buf_trans_edp(dev_priv, n_entries);
653 } else if (IS_HASWELL(dev_priv)) {
654 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
655 return hsw_ddi_translations_dp;
656 }
657
658 *n_entries = 0;
659 return NULL;
660}
661
662static const struct ddi_buf_trans *
663intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
664 int *n_entries)
665{
666 if (IS_BROADWELL(dev_priv)) {
667 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
668 return hsw_ddi_translations_fdi;
669 } else if (IS_HASWELL(dev_priv)) {
670 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
671 return hsw_ddi_translations_fdi;
672 }
673
674 *n_entries = 0;
675 return NULL;
676}
677
e58623cb
AR		 678/*
679 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 680 * values in advance. This function programs the correct values for
681 * DP/eDP/FDI use cases.
45244b87 682 */
d7c530b2 683static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 684{
6a7e4f99 685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 686 u32 iboost_bit = 0;
7d1c42e6 687 int i, n_entries;
32bdc400 688 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 689 const struct ddi_buf_trans *ddi_translations;
e58623cb 690
cc3f90f0 691 if (IS_GEN9_LP(dev_priv))
96fb9f9b 692 return;
6a7e4f99 693
7d1c42e6
VS		 694 switch (encoder->type) {
695 case INTEL_OUTPUT_EDP:
696 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
697 &n_entries);
698 break;
699 case INTEL_OUTPUT_DP:
700 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
701 &n_entries);
702 break;
703 case INTEL_OUTPUT_ANALOG:
704 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
705 &n_entries);
706 break;
707 default:
708 MISSING_CASE(encoder->type);
709 return;
e58623cb
AR		 710 }
711
b976dc53 712 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 713 /* If we're boosting the current, set bit 31 of trans1 */
714 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
715 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
716
717 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
718 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 719 n_entries > 9))
720 n_entries = 9;
300644c7 721 }
45244b87 722
7d1c42e6 723 for (i = 0; i < n_entries; i++) {
9712e688
VS		 724 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
725 ddi_translations[i].trans1 | iboost_bit);
726 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
727 ddi_translations[i].trans2);
45244b87 728 }
32bdc400
VS		 729}
730
731/*
732 * Starting with Haswell, DDI port buffers must be programmed with correct
733 * values in advance. This function programs the correct values for
734 * HDMI/DVI use cases.
735 */
736static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
737{
738 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
739 u32 iboost_bit = 0;
740 int n_hdmi_entries, hdmi_level;
741 enum port port = intel_ddi_get_encoder_port(encoder);
742 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 743
cc3f90f0 744 if (IS_GEN9_LP(dev_priv))
ce3b7e9b
DL		 745 return;
746
32bdc400
VS		 747 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
748
b976dc53 749 if (IS_GEN9_BC(dev_priv)) {
32bdc400 750 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 751
32bdc400 752 /* If we're boosting the current, set bit 31 of trans1 */
1edaaa2f 753 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
32bdc400
VS		 754 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
755 } else if (IS_BROADWELL(dev_priv)) {
756 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
757 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
758 } else if (IS_HASWELL(dev_priv)) {
759 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
760 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
761 } else {
762 WARN(1, "ddi translation table missing\n");
763 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
764 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
765 }
766
6acab15a 767 /* Entry 9 is for HDMI: */
ed9c77d2 768 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 769 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 770 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 771 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 772}
773
248138b5
PZ		 774static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
775 enum port port)
776{
f0f59a00 777 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 778 int i;
779
3449ca85 780 for (i = 0; i < 16; i++) {
248138b5
PZ		 781 udelay(1);
782 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
783 return;
784 }
785 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
786}
c82e4d26 787
c856052a
ACO		 788static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
789{
790 switch (pll->id) {
791 case DPLL_ID_WRPLL1:
792 return PORT_CLK_SEL_WRPLL1;
793 case DPLL_ID_WRPLL2:
794 return PORT_CLK_SEL_WRPLL2;
795 case DPLL_ID_SPLL:
796 return PORT_CLK_SEL_SPLL;
797 case DPLL_ID_LCPLL_810:
798 return PORT_CLK_SEL_LCPLL_810;
799 case DPLL_ID_LCPLL_1350:
800 return PORT_CLK_SEL_LCPLL_1350;
801 case DPLL_ID_LCPLL_2700:
802 return PORT_CLK_SEL_LCPLL_2700;
803 default:
804 MISSING_CASE(pll->id);
805 return PORT_CLK_SEL_NONE;
806 }
807}
808
c82e4d26
ED		 809/* Starting with Haswell, different DDI ports can work in FDI mode for
810 * connection to the PCH-located connectors. For this, it is necessary to train
811 * both the DDI port and PCH receiver for the desired DDI buffer settings.
812 *
813 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
814 * please note that when FDI mode is active on DDI E, it shares 2 lines with
815 * DDI A (which is used for eDP)
816 */
817
dc4a1094
ACO		 818void hsw_fdi_link_train(struct intel_crtc *crtc,
819 const struct intel_crtc_state *crtc_state)
c82e4d26 820{
4cbe4b2b 821 struct drm_device *dev = crtc->base.dev;
fac5e23e 822 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 823 struct intel_encoder *encoder;
c856052a 824 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 825
4cbe4b2b 826 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 827 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 828 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 829 }
830
04945641
PZ		 831 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
832 * mode set "sequence for CRT port" document:
833 * - TP1 to TP2 time with the default value
834 * - FDI delay to 90h
8693a824
DL		 835 *
836 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 837 */
eede3b53 838 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 839 FDI_RX_PWRDN_LANE0_VAL(2) |
840 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
841
842 /* Enable the PCH Receiver FDI PLL */
3e68320e 843 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 844 FDI_RX_PLL_ENABLE |
dc4a1094 845 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 846 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
847 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 848 udelay(220);
849
850 /* Switch from Rawclk to PCDclk */
851 rx_ctl_val |= FDI_PCDCLK;
eede3b53 852 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 853
854 /* Configure Port Clock Select */
dc4a1094 855 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 856 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
857 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 858
859 /* Start the training iterating through available voltages and emphasis,
860 * testing each value twice. */
10122051 861 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 862 /* Configure DP_TP_CTL with auto-training */
863 I915_WRITE(DP_TP_CTL(PORT_E),
864 DP_TP_CTL_FDI_AUTOTRAIN |
865 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
866 DP_TP_CTL_LINK_TRAIN_PAT1 |
867 DP_TP_CTL_ENABLE);
868
876a8cdf
DL		 869 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
870 * DDI E does not support port reversal, the functionality is
871 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
872 * port reversal bit */
c82e4d26 873 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 874 DDI_BUF_CTL_ENABLE |
dc4a1094 875 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 876 DDI_BUF_TRANS_SELECT(i / 2));
04945641 877 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 878
879 udelay(600);
880
04945641 881 /* Program PCH FDI Receiver TU */
eede3b53 882 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 883
884 /* Enable PCH FDI Receiver with auto-training */
885 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 886 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
887 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 888
889 /* Wait for FDI receiver lane calibration */
890 udelay(30);
891
892 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 893 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 894 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 895 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
896 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 897
898 /* Wait for FDI auto training time */
899 udelay(5);
c82e4d26
ED		 900
901 temp = I915_READ(DP_TP_STATUS(PORT_E));
902 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 903 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 904 break;
905 }
c82e4d26 906
a308ccb3
VS		 907 /*
908 * Leave things enabled even if we failed to train FDI.
909 * Results in less fireworks from the state checker.
910 */
911 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
912 DRM_ERROR("FDI link training failed!\n");
913 break;
c82e4d26 914 }
04945641 915
5b421c57
VS		 916 rx_ctl_val &= ~FDI_RX_ENABLE;
917 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
918 POSTING_READ(FDI_RX_CTL(PIPE_A));
919
248138b5
PZ		 920 temp = I915_READ(DDI_BUF_CTL(PORT_E));
921 temp &= ~DDI_BUF_CTL_ENABLE;
922 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
923 POSTING_READ(DDI_BUF_CTL(PORT_E));
924
04945641 925 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 926 temp = I915_READ(DP_TP_CTL(PORT_E));
927 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
928 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
929 I915_WRITE(DP_TP_CTL(PORT_E), temp);
930 POSTING_READ(DP_TP_CTL(PORT_E));
931
932 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 933
04945641 934 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 935 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 936 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
937 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 938 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
939 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 940 }
941
a308ccb3
VS		 942 /* Enable normal pixel sending for FDI */
943 I915_WRITE(DP_TP_CTL(PORT_E),
944 DP_TP_CTL_FDI_AUTOTRAIN |
945 DP_TP_CTL_LINK_TRAIN_NORMAL |
946 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
947 DP_TP_CTL_ENABLE);
c82e4d26 948}
0e72a5b5 949
d7c530b2 950static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 951{
952 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
953 struct intel_digital_port *intel_dig_port =
954 enc_to_dig_port(&encoder->base);
955
956 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 957 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 958 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 959}
960
8d9ddbcb 961static struct intel_encoder *
e9ce1a62 962intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 963{
e9ce1a62 964 struct drm_device *dev = crtc->base.dev;
1524e93e 965 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 966 int num_encoders = 0;
967
1524e93e
SS		 968 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
969 ret = encoder;
8d9ddbcb
PZ		 970 num_encoders++;
971 }
972
973 if (num_encoders != 1)
84f44ce7 974 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 975 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 976
977 BUG_ON(ret == NULL);
978 return ret;
979}
980
44a126ba
PZ		 981/* Finds the only possible encoder associated with the given CRTC. */
982struct intel_encoder *
3165c074 983intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 984{
3165c074
ACO		 985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986 struct intel_encoder *ret = NULL;
987 struct drm_atomic_state *state;
da3ced29
ACO		 988 struct drm_connector *connector;
989 struct drm_connector_state *connector_state;
d0737e1d 990 int num_encoders = 0;
3165c074 991 int i;
d0737e1d 992
3165c074
ACO		 993 state = crtc_state->base.state;
994
b77c7a90 995 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 996 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 997 continue;
998
da3ced29 999 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 1000 num_encoders++;
d0737e1d
ACO		 1001 }
1002
1003 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1004 pipe_name(crtc->pipe));
1005
1006 BUG_ON(ret == NULL);
1007 return ret;
1008}
1009
1c0b85c5 1010#define LC_FREQ 2700
1c0b85c5 1011
f0f59a00
VS		 1012static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1013 i915_reg_t reg)
11578553
JB		 1014{
1015 int refclk = LC_FREQ;
1016 int n, p, r;
1017 u32 wrpll;
1018
1019 wrpll = I915_READ(reg);
114fe488
DV		 1020 switch (wrpll & WRPLL_PLL_REF_MASK) {
1021 case WRPLL_PLL_SSC:
1022 case WRPLL_PLL_NON_SSC:
11578553
JB		 1023 /*
1024 * We could calculate spread here, but our checking
1025 * code only cares about 5% accuracy, and spread is a max of
1026 * 0.5% downspread.
1027 */
1028 refclk = 135;
1029 break;
114fe488 1030 case WRPLL_PLL_LCPLL:
11578553
JB		 1031 refclk = LC_FREQ;
1032 break;
1033 default:
1034 WARN(1, "bad wrpll refclk\n");
1035 return 0;
1036 }
1037
1038 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1039 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1040 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1041
20f0ec16
JB		 1042 /* Convert to KHz, p & r have a fixed point portion */
1043 return (refclk * n * 100) / (p * r);
11578553
JB		 1044}
1045
540e732c
S		 1046static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1047 uint32_t dpll)
1048{
f0f59a00 1049 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1050 uint32_t cfgcr1_val, cfgcr2_val;
1051 uint32_t p0, p1, p2, dco_freq;
1052
923c1241
VS		 1053 cfgcr1_reg = DPLL_CFGCR1(dpll);
1054 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1055
1056 cfgcr1_val = I915_READ(cfgcr1_reg);
1057 cfgcr2_val = I915_READ(cfgcr2_reg);
1058
1059 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1060 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1061
1062 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1063 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1064 else
1065 p1 = 1;
1066
1067
1068 switch (p0) {
1069 case DPLL_CFGCR2_PDIV_1:
1070 p0 = 1;
1071 break;
1072 case DPLL_CFGCR2_PDIV_2:
1073 p0 = 2;
1074 break;
1075 case DPLL_CFGCR2_PDIV_3:
1076 p0 = 3;
1077 break;
1078 case DPLL_CFGCR2_PDIV_7:
1079 p0 = 7;
1080 break;
1081 }
1082
1083 switch (p2) {
1084 case DPLL_CFGCR2_KDIV_5:
1085 p2 = 5;
1086 break;
1087 case DPLL_CFGCR2_KDIV_2:
1088 p2 = 2;
1089 break;
1090 case DPLL_CFGCR2_KDIV_3:
1091 p2 = 3;
1092 break;
1093 case DPLL_CFGCR2_KDIV_1:
1094 p2 = 1;
1095 break;
1096 }
1097
1098 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1099
1100 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1101 1000) / 0x8000;
1102
1103 return dco_freq / (p0 * p1 * p2 * 5);
1104}
1105
a9701a89
RV		 1106static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1107 uint32_t pll_id)
1108{
1109 uint32_t cfgcr0, cfgcr1;
1110 uint32_t p0, p1, p2, dco_freq, ref_clock;
1111
1112 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1113 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1114
1115 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1116 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1117
1118 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1119 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1120 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1121 else
1122 p1 = 1;
1123
1124
1125 switch (p0) {
1126 case DPLL_CFGCR1_PDIV_2:
1127 p0 = 2;
1128 break;
1129 case DPLL_CFGCR1_PDIV_3:
1130 p0 = 3;
1131 break;
1132 case DPLL_CFGCR1_PDIV_5:
1133 p0 = 5;
1134 break;
1135 case DPLL_CFGCR1_PDIV_7:
1136 p0 = 7;
1137 break;
1138 }
1139
1140 switch (p2) {
1141 case DPLL_CFGCR1_KDIV_1:
1142 p2 = 1;
1143 break;
1144 case DPLL_CFGCR1_KDIV_2:
1145 p2 = 2;
1146 break;
1147 case DPLL_CFGCR1_KDIV_4:
1148 p2 = 4;
1149 break;
1150 }
1151
1152 ref_clock = dev_priv->cdclk.hw.ref;
1153
1154 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1155
1156 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1157 DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
1158
1159 return dco_freq / (p0 * p1 * p2 * 5);
1160}
1161
398a017e
VS		 1162static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1163{
1164 int dotclock;
1165
1166 if (pipe_config->has_pch_encoder)
1167 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1168 &pipe_config->fdi_m_n);
37a5650b 1169 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1170 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1171 &pipe_config->dp_m_n);
1172 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1173 dotclock = pipe_config->port_clock * 2 / 3;
1174 else
1175 dotclock = pipe_config->port_clock;
1176
1177 if (pipe_config->pixel_multiplier)
1178 dotclock /= pipe_config->pixel_multiplier;
1179
1180 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1181}
540e732c 1182
a9701a89
RV		 1183static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1184 struct intel_crtc_state *pipe_config)
1185{
1186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1187 int link_clock = 0;
1188 uint32_t cfgcr0, pll_id;
1189
1190 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1191
1192 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1193
1194 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1195 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1196 } else {
1197 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1198
1199 switch (link_clock) {
1200 case DPLL_CFGCR0_LINK_RATE_810:
1201 link_clock = 81000;
1202 break;
1203 case DPLL_CFGCR0_LINK_RATE_1080:
1204 link_clock = 108000;
1205 break;
1206 case DPLL_CFGCR0_LINK_RATE_1350:
1207 link_clock = 135000;
1208 break;
1209 case DPLL_CFGCR0_LINK_RATE_1620:
1210 link_clock = 162000;
1211 break;
1212 case DPLL_CFGCR0_LINK_RATE_2160:
1213 link_clock = 216000;
1214 break;
1215 case DPLL_CFGCR0_LINK_RATE_2700:
1216 link_clock = 270000;
1217 break;
1218 case DPLL_CFGCR0_LINK_RATE_3240:
1219 link_clock = 324000;
1220 break;
1221 case DPLL_CFGCR0_LINK_RATE_4050:
1222 link_clock = 405000;
1223 break;
1224 default:
1225 WARN(1, "Unsupported link rate\n");
1226 break;
1227 }
1228 link_clock *= 2;
1229 }
1230
1231 pipe_config->port_clock = link_clock;
1232
1233 ddi_dotclock_get(pipe_config);
1234}
1235
540e732c 1236static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1237 struct intel_crtc_state *pipe_config)
540e732c 1238{
fac5e23e 1239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1240 int link_clock = 0;
1241 uint32_t dpll_ctl1, dpll;
1242
c856052a 1243 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1244
1245 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1246
1247 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1248 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1249 } else {
71cd8423
DL		 1250 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1251 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1252
1253 switch (link_clock) {
71cd8423 1254 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1255 link_clock = 81000;
1256 break;
71cd8423 1257 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1258 link_clock = 108000;
1259 break;
71cd8423 1260 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1261 link_clock = 135000;
1262 break;
71cd8423 1263 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1264 link_clock = 162000;
1265 break;
71cd8423 1266 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1267 link_clock = 216000;
1268 break;
71cd8423 1269 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1270 link_clock = 270000;
1271 break;
1272 default:
1273 WARN(1, "Unsupported link rate\n");
1274 break;
1275 }
1276 link_clock *= 2;
1277 }
1278
1279 pipe_config->port_clock = link_clock;
1280
398a017e 1281 ddi_dotclock_get(pipe_config);
540e732c
S		 1282}
1283
3d51278a 1284static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1285 struct intel_crtc_state *pipe_config)
11578553 1286{
fac5e23e 1287 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1288 int link_clock = 0;
1289 u32 val, pll;
1290
c856052a 1291 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1292 switch (val & PORT_CLK_SEL_MASK) {
1293 case PORT_CLK_SEL_LCPLL_810:
1294 link_clock = 81000;
1295 break;
1296 case PORT_CLK_SEL_LCPLL_1350:
1297 link_clock = 135000;
1298 break;
1299 case PORT_CLK_SEL_LCPLL_2700:
1300 link_clock = 270000;
1301 break;
1302 case PORT_CLK_SEL_WRPLL1:
01403de3 1303 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1304 break;
1305 case PORT_CLK_SEL_WRPLL2:
01403de3 1306 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1307 break;
1308 case PORT_CLK_SEL_SPLL:
1309 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1310 if (pll == SPLL_PLL_FREQ_810MHz)
1311 link_clock = 81000;
1312 else if (pll == SPLL_PLL_FREQ_1350MHz)
1313 link_clock = 135000;
1314 else if (pll == SPLL_PLL_FREQ_2700MHz)
1315 link_clock = 270000;
1316 else {
1317 WARN(1, "bad spll freq\n");
1318 return;
1319 }
1320 break;
1321 default:
1322 WARN(1, "bad port clock sel\n");
1323 return;
1324 }
1325
1326 pipe_config->port_clock = link_clock * 2;
1327
398a017e 1328 ddi_dotclock_get(pipe_config);
11578553
JB		 1329}
1330
977bb38d
S		 1331static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1332 enum intel_dpll_id dpll)
1333{
aa610dcb
ID		 1334 struct intel_shared_dpll *pll;
1335 struct intel_dpll_hw_state *state;
9e2c8475 1336 struct dpll clock;
aa610dcb
ID		 1337
1338 /* For DDI ports we always use a shared PLL. */
1339 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1340 return 0;
1341
1342 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1343 state = &pll->state.hw_state;
aa610dcb
ID		 1344
1345 clock.m1 = 2;
1346 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1347 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1348 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1349 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1350 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1351 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1352
1353 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1354}
1355
1356static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1357 struct intel_crtc_state *pipe_config)
1358{
fac5e23e 1359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1360 enum port port = intel_ddi_get_encoder_port(encoder);
1361 uint32_t dpll = port;
1362
398a017e 1363 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1364
398a017e 1365 ddi_dotclock_get(pipe_config);
977bb38d
S		 1366}
1367
3d51278a 1368void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1369 struct intel_crtc_state *pipe_config)
3d51278a 1370{
0853723b 1371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1372
0853723b 1373 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1374 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1375 else if (IS_GEN9_BC(dev_priv))
22606a18 1376 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1377 else if (IS_GEN9_LP(dev_priv))
977bb38d 1378 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1379 else if (IS_CANNONLAKE(dev_priv))
1380 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1381}
1382
3dc38eea 1383void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1384{
3dc38eea 1385 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1386 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1387 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1388 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1389 int type = encoder->type;
dae84799
PZ		 1390 uint32_t temp;
1391
cca0502b 1392 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1393 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1394
c9809791 1395 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1396 switch (crtc_state->pipe_bpp) {
dae84799 1397 case 18:
c9809791 1398 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1399 break;
1400 case 24:
c9809791 1401 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1402 break;
1403 case 30:
c9809791 1404 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1405 break;
1406 case 36:
c9809791 1407 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1408 break;
1409 default:
4e53c2e0 1410 BUG();
dae84799 1411 }
c9809791 1412 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1413 }
1414}
1415
3dc38eea
ACO		 1416void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1417 bool state)
0e32b39c 1418{
3dc38eea 1419 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1421 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1422 uint32_t temp;
1423 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1424 if (state == true)
1425 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1426 else
1427 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1428 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1429}
1430
3dc38eea 1431void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1432{
3dc38eea 1433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1434 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
3dc38eea 1437 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1438 enum port port = intel_ddi_get_encoder_port(encoder);
1439 int type = encoder->type;
8d9ddbcb
PZ		 1440 uint32_t temp;
1441
ad80a810
PZ		 1442 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1443 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1444 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1445
3dc38eea 1446 switch (crtc_state->pipe_bpp) {
dfcef252 1447 case 18:
ad80a810 1448 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1449 break;
1450 case 24:
ad80a810 1451 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1452 break;
1453 case 30:
ad80a810 1454 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1455 break;
1456 case 36:
ad80a810 1457 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1458 break;
1459 default:
4e53c2e0 1460 BUG();
dfcef252 1461 }
72662e10 1462
3dc38eea 1463 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1464 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1465 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1466 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1467
e6f0bfc4
PZ		 1468 if (cpu_transcoder == TRANSCODER_EDP) {
1469 switch (pipe) {
1470 case PIPE_A:
c7670b10
PZ		 1471 /* On Haswell, can only use the always-on power well for
1472 * eDP when not using the panel fitter, and when not
1473 * using motion blur mitigation (which we don't
1474 * support). */
772c2a51 1475 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1476 (crtc_state->pch_pfit.enabled ||
1477 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1478 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1479 else
1480 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1481 break;
1482 case PIPE_B:
1483 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1484 break;
1485 case PIPE_C:
1486 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1487 break;
1488 default:
1489 BUG();
1490 break;
1491 }
1492 }
1493
7739c33b 1494 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1495 if (crtc_state->has_hdmi_sink)
ad80a810 1496 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1497 else
ad80a810 1498 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1499
1500 if (crtc_state->hdmi_scrambling)
1501 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1502 if (crtc_state->hdmi_high_tmds_clock_ratio)
1503 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1504 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1505 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1506 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1507 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1508 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1509 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1510 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1511 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1512 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1513 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1514 } else {
84f44ce7 1515 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1516 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1517 }
1518
ad80a810 1519 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1520}
72662e10 1521
ad80a810
PZ		 1522void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1523 enum transcoder cpu_transcoder)
8d9ddbcb 1524{
f0f59a00 1525 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1526 uint32_t val = I915_READ(reg);
1527
0e32b39c 1528 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1529 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1530 I915_WRITE(reg, val);
72662e10
ED		 1531}
1532
bcbc889b
PZ		 1533bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1534{
1535 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1536 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1537 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1538 int type = intel_connector->base.connector_type;
1524e93e 1539 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1540 enum pipe pipe = 0;
1541 enum transcoder cpu_transcoder;
1542 uint32_t tmp;
e27daab4 1543 bool ret;
bcbc889b 1544
79f255a0 1545 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1546 encoder->power_domain))
882244a3
PZ		 1547 return false;
1548
1524e93e 1549 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1550 ret = false;
1551 goto out;
1552 }
bcbc889b
PZ		 1553
1554 if (port == PORT_A)
1555 cpu_transcoder = TRANSCODER_EDP;
1556 else
1a240d4d 1557 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1558
1559 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1560
1561 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1562 case TRANS_DDI_MODE_SELECT_HDMI:
1563 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1564 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1565 break;
bcbc889b
PZ		 1566
1567 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1568 ret = type == DRM_MODE_CONNECTOR_eDP ||
1569 type == DRM_MODE_CONNECTOR_DisplayPort;
1570 break;
1571
0e32b39c
DA		 1572 case TRANS_DDI_MODE_SELECT_DP_MST:
1573 /* if the transcoder is in MST state then
1574 * connector isn't connected */
e27daab4
ID		 1575 ret = false;
1576 break;
bcbc889b
PZ		 1577
1578 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1579 ret = type == DRM_MODE_CONNECTOR_VGA;
1580 break;
bcbc889b
PZ		 1581
1582 default:
e27daab4
ID		 1583 ret = false;
1584 break;
bcbc889b 1585 }
e27daab4
ID		 1586
1587out:
1524e93e 1588 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1589
1590 return ret;
bcbc889b
PZ		 1591}
1592
85234cdc
DV		 1593bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1594 enum pipe *pipe)
1595{
1596 struct drm_device *dev = encoder->base.dev;
fac5e23e 1597 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1598 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1599 u32 tmp;
1600 int i;
e27daab4 1601 bool ret;
85234cdc 1602
79f255a0
ACO		 1603 if (!intel_display_power_get_if_enabled(dev_priv,
1604 encoder->power_domain))
6d129bea
ID		 1605 return false;
1606
e27daab4
ID		 1607 ret = false;
1608
fe43d3f5 1609 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1610
1611 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1612 goto out;
85234cdc 1613
ad80a810
PZ		 1614 if (port == PORT_A) {
1615 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1616
ad80a810
PZ		 1617 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1618 case TRANS_DDI_EDP_INPUT_A_ON:
1619 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1620 *pipe = PIPE_A;
1621 break;
1622 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1623 *pipe = PIPE_B;
1624 break;
1625 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1626 *pipe = PIPE_C;
1627 break;
1628 }
1629
e27daab4 1630 ret = true;
ad80a810 1631
e27daab4
ID		 1632 goto out;
1633 }
0e32b39c 1634
e27daab4
ID		 1635 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1636 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1637
1638 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1639 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1640 TRANS_DDI_MODE_SELECT_DP_MST)
1641 goto out;
1642
1643 *pipe = i;
1644 ret = true;
1645
1646 goto out;
85234cdc
DV		 1647 }
1648 }
1649
84f44ce7 1650 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1651
e27daab4 1652out:
cc3f90f0 1653 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0
ID		 1654 tmp = I915_READ(BXT_PHY_CTL(port));
1655 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1656 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1657 DRM_ERROR("Port %c enabled but PHY powered down? "
1658 "(PHY_CTL %08x)\n", port_name(port), tmp);
1659 }
1660
79f255a0 1661 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1662
1663 return ret;
85234cdc
DV		 1664}
1665
62b69566
ACO		 1666static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1667{
1668 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1669 enum pipe pipe;
1670
1671 if (intel_ddi_get_hw_state(encoder, &pipe))
1672 return BIT_ULL(dig_port->ddi_io_power_domain);
1673
1674 return 0;
1675}
1676
3dc38eea 1677void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1678{
3dc38eea 1679 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1681 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1682 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1683 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1684
bb523fc0
PZ		 1685 if (cpu_transcoder != TRANSCODER_EDP)
1686 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1687 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1688}
1689
3dc38eea 1690void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1691{
3dc38eea
ACO		 1692 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1693 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1694
bb523fc0
PZ		 1695 if (cpu_transcoder != TRANSCODER_EDP)
1696 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1697 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1698}
1699
a7d8dbc0
VS		 1700static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1701 enum port port, uint8_t iboost)
f8896f5d 1702{
a7d8dbc0
VS		 1703 u32 tmp;
1704
1705 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1706 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1707 if (iboost)
1708 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1709 else
1710 tmp |= BALANCE_LEG_DISABLE(port);
1711 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1712}
1713
1714static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1715{
1716 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1717 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1718 enum port port = intel_dig_port->port;
1719 int type = encoder->type;
f8896f5d
DW		 1720 const struct ddi_buf_trans *ddi_translations;
1721 uint8_t iboost;
75067dde 1722 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1723 int n_entries;
f8896f5d 1724
75067dde
AK		 1725 /* VBT may override standard boost values */
1726 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1727 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1728
cca0502b 1729 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1730 if (dp_iboost) {
1731 iboost = dp_iboost;
1732 } else {
da411a48 1733 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 1734 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1735 &n_entries);
1736 else
1737 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1738 &n_entries);
e4d4c05b 1739 iboost = ddi_translations[level].i_boost;
75067dde 1740 }
f8896f5d 1741 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1742 if (dp_iboost) {
1743 iboost = dp_iboost;
1744 } else {
78ab0bae 1745 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1746
1747 if (WARN_ON(port != PORT_A &&
1748 port != PORT_E && n_entries > 9))
1749 n_entries = 9;
1750
e4d4c05b 1751 iboost = ddi_translations[level].i_boost;
75067dde 1752 }
f8896f5d 1753 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1754 if (hdmi_iboost) {
1755 iboost = hdmi_iboost;
1756 } else {
78ab0bae 1757 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1758 iboost = ddi_translations[level].i_boost;
75067dde 1759 }
f8896f5d
DW		 1760 } else {
1761 return;
1762 }
1763
1764 /* Make sure that the requested I_boost is valid */
1765 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1766 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1767 return;
1768 }
1769
a7d8dbc0 1770 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1771
a7d8dbc0
VS		 1772 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1773 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1774}
1775
78ab0bae
VS		 1776static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1777 u32 level, enum port port, int type)
96fb9f9b 1778{
96fb9f9b
VK		 1779 const struct bxt_ddi_buf_trans *ddi_translations;
1780 u32 n_entries, i;
96fb9f9b 1781
06411f08 1782 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1783 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1784 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1785 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1786 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1787 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1788 ddi_translations = bxt_ddi_translations_dp;
1789 } else if (type == INTEL_OUTPUT_HDMI) {
1790 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1791 ddi_translations = bxt_ddi_translations_hdmi;
1792 } else {
1793 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1794 type);
1795 return;
1796 }
1797
1798 /* Check if default value has to be used */
1799 if (level >= n_entries ||
1800 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1801 for (i = 0; i < n_entries; i++) {
1802 if (ddi_translations[i].default_index) {
1803 level = i;
1804 break;
1805 }
1806 }
1807 }
1808
b6e08203
ACO		 1809 bxt_ddi_phy_set_signal_level(dev_priv, port,
1810 ddi_translations[level].margin,
1811 ddi_translations[level].scale,
1812 ddi_translations[level].enable,
1813 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1814}
1815
ffe5111e
VS		 1816u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1817{
1818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1819 int n_entries;
1820
1821 if (encoder->type == INTEL_OUTPUT_EDP)
1822 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1823 else
1824 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1825
1826 if (WARN_ON(n_entries < 1))
1827 n_entries = 1;
1828 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1829 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1830
1831 return index_to_dp_signal_levels[n_entries - 1] &
1832 DP_TRAIN_VOLTAGE_SWING_MASK;
1833}
1834
cf54ca8b
RV		 1835static const struct cnl_ddi_buf_trans *
1836cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1837 u32 voltage, int *n_entries)
1838{
1839 if (voltage == VOLTAGE_INFO_0_85V) {
1840 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1841 return cnl_ddi_translations_hdmi_0_85V;
1842 } else if (voltage == VOLTAGE_INFO_0_95V) {
1843 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1844 return cnl_ddi_translations_hdmi_0_95V;
1845 } else if (voltage == VOLTAGE_INFO_1_05V) {
1846 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1847 return cnl_ddi_translations_hdmi_1_05V;
1848 }
1849 return NULL;
1850}
1851
1852static const struct cnl_ddi_buf_trans *
1853cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1854 u32 voltage, int *n_entries)
1855{
1856 if (voltage == VOLTAGE_INFO_0_85V) {
1857 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1858 return cnl_ddi_translations_dp_0_85V;
1859 } else if (voltage == VOLTAGE_INFO_0_95V) {
1860 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1861 return cnl_ddi_translations_dp_0_95V;
1862 } else if (voltage == VOLTAGE_INFO_1_05V) {
1863 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1864 return cnl_ddi_translations_dp_1_05V;
1865 }
1866 return NULL;
1867}
1868
1869static const struct cnl_ddi_buf_trans *
1870cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1871 u32 voltage, int *n_entries)
1872{
1873 if (dev_priv->vbt.edp.low_vswing) {
1874 if (voltage == VOLTAGE_INFO_0_85V) {
1875 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1876 return cnl_ddi_translations_dp_0_85V;
1877 } else if (voltage == VOLTAGE_INFO_0_95V) {
1878 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1879 return cnl_ddi_translations_edp_0_95V;
1880 } else if (voltage == VOLTAGE_INFO_1_05V) {
1881 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1882 return cnl_ddi_translations_edp_1_05V;
1883 }
1884 return NULL;
1885 } else {
1886 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1887 }
1888}
1889
1890static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1891 u32 level, enum port port, int type)
1892{
1893 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1894 u32 n_entries, val, voltage;
1895 int ln;
1896
1897 /*
1898 * Values for each port type are listed in
1899 * voltage swing programming tables.
1900 * Vccio voltage found in PORT_COMP_DW3.
1901 */
1902 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1903
1904 if (type == INTEL_OUTPUT_HDMI) {
1905 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1906 voltage, &n_entries);
1907 } else if (type == INTEL_OUTPUT_DP) {
1908 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1909 voltage, &n_entries);
1910 } else if (type == INTEL_OUTPUT_EDP) {
1911 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1912 voltage, &n_entries);
1913 }
1914
1915 if (ddi_translations == NULL) {
1916 MISSING_CASE(voltage);
1917 return;
1918 }
1919
1920 if (level >= n_entries) {
1921 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1922 level = n_entries - 1;
1923 }
1924
1925 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1926 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1927 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1928 val |= SCALING_MODE_SEL(2);
1929 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1930
1931 /* Program PORT_TX_DW2 */
1932 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1933 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1934 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1935 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1936 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1937 /* Rcomp scalar is fixed as 0x98 for every table entry */
1938 val |= RCOMP_SCALAR(0x98);
1939 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1940
1941 /* Program PORT_TX_DW4 */
1942 /* We cannot write to GRP. It would overrite individual loadgen */
1943 for (ln = 0; ln < 4; ln++) {
1944 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1945 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1946 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1947 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1948 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1949 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1950 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1951 }
1952
1953 /* Program PORT_TX_DW5 */
1954 /* All DW5 values are fixed for every table entry */
1955 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1956 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1957 val |= RTERM_SELECT(6);
1958 val |= TAP3_DISABLE;
1959 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1960
1961 /* Program PORT_TX_DW7 */
1962 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1963 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1964 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1965 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1966}
1967
0091abc3 1968static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1969{
0091abc3
CT		 1970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1971 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1972 enum port port = intel_ddi_get_encoder_port(encoder);
1973 int type = encoder->type;
1974 int width = 0;
1975 int rate = 0;
cf54ca8b 1976 u32 val;
0091abc3
CT		 1977 int ln = 0;
1978
1979 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1980 width = intel_dp->lane_count;
1981 rate = intel_dp->link_rate;
1982 } else {
1983 width = 4;
1984 /* Rate is always < than 6GHz for HDMI */
1985 }
cf54ca8b
RV		 1986
1987 /*
1988 * 1. If port type is eDP or DP,
1989 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1990 * else clear to 0b.
1991 */
1992 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1993 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1994 val |= COMMON_KEEPER_EN;
1995 else
1996 val &= ~COMMON_KEEPER_EN;
1997 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1998
1999 /* 2. Program loadgen select */
2000 /*
0091abc3
CT		 2001 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2002 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2003 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2004 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2005 */
0091abc3
CT		 2006 for (ln = 0; ln <= 3; ln++) {
2007 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2008 val &= ~LOADGEN_SELECT;
2009
2010 if (((rate < 600000) && (width == 4) && (ln >= 1)) ||
2011 ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
2012 val |= LOADGEN_SELECT;
2013 }
2014 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2015 }
cf54ca8b
RV		 2016
2017 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2018 val = I915_READ(CNL_PORT_CL1CM_DW5);
2019 val |= SUS_CLOCK_CONFIG;
2020 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2021
2022 /* 4. Clear training enable to change swing values */
2023 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2024 val &= ~TX_TRAINING_EN;
2025 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2026
2027 /* 5. Program swing and de-emphasis */
2028 cnl_ddi_vswing_program(dev_priv, level, port, type);
2029
2030 /* 6. Set training enable to trigger update */
2031 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2032 val |= TX_TRAINING_EN;
2033 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2034}
2035
f8896f5d
DW		 2036static uint32_t translate_signal_level(int signal_levels)
2037{
97eeb872 2038 int i;
f8896f5d 2039
97eeb872
VS		 2040 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2041 if (index_to_dp_signal_levels[i] == signal_levels)
2042 return i;
f8896f5d
DW		 2043 }
2044
97eeb872
VS		 2045 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2046 signal_levels);
2047
2048 return 0;
f8896f5d
DW		 2049}
2050
2051uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2052{
2053 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2054 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 2055 struct intel_encoder *encoder = &dport->base;
2056 uint8_t train_set = intel_dp->train_set[0];
2057 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2058 DP_TRAIN_PRE_EMPHASIS_MASK);
2059 enum port port = dport->port;
2060 uint32_t level;
2061
2062 level = translate_signal_level(signal_levels);
2063
b976dc53 2064 if (IS_GEN9_BC(dev_priv))
a7d8dbc0 2065 skl_ddi_set_iboost(encoder, level);
cc3f90f0 2066 else if (IS_GEN9_LP(dev_priv))
78ab0bae 2067 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
cf54ca8b 2068 else if (IS_CANNONLAKE(dev_priv)) {
0091abc3 2069 cnl_ddi_vswing_sequence(encoder, level);
cf54ca8b
RV		 2070 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
2071 return 0;
2072 }
f8896f5d
DW		 2073 return DDI_BUF_TRANS_SELECT(level);
2074}
2075
d7c530b2
PZ		 2076static void intel_ddi_clk_select(struct intel_encoder *encoder,
2077 struct intel_shared_dpll *pll)
6441ab5f 2078{
e404ba8d
VS		 2079 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2080 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 2081 uint32_t val;
6441ab5f 2082
c856052a
ACO		 2083 if (WARN_ON(!pll))
2084 return;
2085
555e38d2
RV		 2086 if (IS_CANNONLAKE(dev_priv)) {
2087 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2088 val = I915_READ(DPCLKA_CFGCR0);
2089 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2090 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2091
555e38d2
RV		 2092 /*
2093 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2094 * This step and the step before must be done with separate
2095 * register writes.
2096 */
2097 val = I915_READ(DPCLKA_CFGCR0);
2098 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2099 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2100 I915_WRITE(DPCLKA_CFGCR0, val);
2101 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2102 /* DDI -> PLL mapping */
efa80add
S		 2103 val = I915_READ(DPLL_CTRL2);
2104
2105 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2106 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2107 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2108 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2109
2110 I915_WRITE(DPLL_CTRL2, val);
5416d871 2111
e404ba8d 2112 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 2113 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2114 }
e404ba8d
VS		 2115}
2116
ba88d153
MN		 2117static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2118 int link_rate, uint32_t lane_count,
2119 struct intel_shared_dpll *pll,
2120 bool link_mst)
e404ba8d 2121{
ba88d153
MN		 2122 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2124 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2125 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
b2ccb822 2126
e081c846
ACO		 2127 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2128
ba88d153
MN		 2129 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2130 link_mst);
2131 if (encoder->type == INTEL_OUTPUT_EDP)
e404ba8d 2132 intel_edp_panel_on(intel_dp);
32bdc400 2133
ba88d153 2134 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2135
2136 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2137
ba88d153
MN		 2138 intel_prepare_dp_ddi_buffers(encoder);
2139 intel_ddi_init_dp_buf_reg(encoder);
2140 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2141 intel_dp_start_link_train(intel_dp);
2142 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2143 intel_dp_stop_link_train(intel_dp);
2144}
901c2daf 2145
ba88d153
MN		 2146static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2147 bool has_hdmi_sink,
ac240288
ML		 2148 const struct intel_crtc_state *crtc_state,
2149 const struct drm_connector_state *conn_state,
ba88d153
MN		 2150 struct intel_shared_dpll *pll)
2151{
2152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2154 struct drm_encoder *drm_encoder = &encoder->base;
2155 enum port port = intel_ddi_get_encoder_port(encoder);
2156 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2157 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2158
ba88d153
MN		 2159 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2160 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2161
2162 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2163
ba88d153 2164 intel_prepare_hdmi_ddi_buffers(encoder);
b976dc53 2165 if (IS_GEN9_BC(dev_priv))
ba88d153 2166 skl_ddi_set_iboost(encoder, level);
cc3f90f0 2167 else if (IS_GEN9_LP(dev_priv))
ba88d153
MN		 2168 bxt_ddi_vswing_sequence(dev_priv, level, port,
2169 INTEL_OUTPUT_HDMI);
cf54ca8b 2170 else if (IS_CANNONLAKE(dev_priv))
0091abc3 2171 cnl_ddi_vswing_sequence(encoder, level);
8d8bb85e 2172
ba88d153
MN		 2173 intel_hdmi->set_infoframes(drm_encoder,
2174 has_hdmi_sink,
ac240288 2175 crtc_state, conn_state);
ba88d153 2176}
32bdc400 2177
1524e93e 2178static void intel_ddi_pre_enable(struct intel_encoder *encoder,
ba88d153
MN		 2179 struct intel_crtc_state *pipe_config,
2180 struct drm_connector_state *conn_state)
2181{
1524e93e 2182 int type = encoder->type;
30cf6db8 2183
ba88d153 2184 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1524e93e 2185 intel_ddi_pre_enable_dp(encoder,
3dc38eea
ACO		 2186 pipe_config->port_clock,
2187 pipe_config->lane_count,
2188 pipe_config->shared_dpll,
2189 intel_crtc_has_type(pipe_config,
ba88d153
MN		 2190 INTEL_OUTPUT_DP_MST));
2191 }
2192 if (type == INTEL_OUTPUT_HDMI) {
1524e93e 2193 intel_ddi_pre_enable_hdmi(encoder,
ac240288
ML		 2194 pipe_config->has_hdmi_sink,
2195 pipe_config, conn_state,
3dc38eea 2196 pipe_config->shared_dpll);
c19b0669 2197 }
6441ab5f
PZ		 2198}
2199
fd6bbda9
ML		 2200static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2201 struct intel_crtc_state *old_crtc_state,
2202 struct drm_connector_state *old_conn_state)
6441ab5f
PZ		 2203{
2204 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2205 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6441ab5f 2206 enum port port = intel_ddi_get_encoder_port(intel_encoder);
62b69566 2207 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
7618138d 2208 struct intel_dp *intel_dp = NULL;
82a4d9c0 2209 int type = intel_encoder->type;
2886e93f 2210 uint32_t val;
a836bdf9 2211 bool wait = false;
2886e93f 2212
fd6bbda9
ML		 2213 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2214
7618138d
ID		 2215 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2216 intel_dp = enc_to_intel_dp(encoder);
2217 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2218 }
2219
2886e93f
PZ		 2220 val = I915_READ(DDI_BUF_CTL(port));
2221 if (val & DDI_BUF_CTL_ENABLE) {
2222 val &= ~DDI_BUF_CTL_ENABLE;
2223 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2224 wait = true;
2886e93f 2225 }
6441ab5f 2226
a836bdf9
PZ		 2227 val = I915_READ(DP_TP_CTL(port));
2228 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2229 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2230 I915_WRITE(DP_TP_CTL(port), val);
2231
2232 if (wait)
2233 intel_wait_ddi_buf_idle(dev_priv, port);
2234
7618138d 2235 if (intel_dp) {
24f3e092 2236 intel_edp_panel_vdd_on(intel_dp);
4be73780 2237 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2238 }
2239
62b69566
ACO		 2240 if (dig_port)
2241 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2242
555e38d2
RV		 2243 if (IS_CANNONLAKE(dev_priv))
2244 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2245 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2246 else if (IS_GEN9_BC(dev_priv))
efa80add
S		 2247 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2248 DPLL_CTRL2_DDI_CLK_OFF(port)));
66478475 2249 else if (INTEL_GEN(dev_priv) < 9)
efa80add 2250 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 2251
2252 if (type == INTEL_OUTPUT_HDMI) {
2253 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2254
2255 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2256 }
6441ab5f
PZ		 2257}
2258
1524e93e 2259void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
b7076546
ML		 2260 struct intel_crtc_state *old_crtc_state,
2261 struct drm_connector_state *old_conn_state)
2262{
1524e93e 2263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2264 uint32_t val;
2265
2266 /*
2267 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2268 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2269 * step 13 is the correct place for it. Step 18 is where it was
2270 * originally before the BUN.
2271 */
2272 val = I915_READ(FDI_RX_CTL(PIPE_A));
2273 val &= ~FDI_RX_ENABLE;
2274 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2275
1524e93e 2276 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
b7076546
ML		 2277
2278 val = I915_READ(FDI_RX_MISC(PIPE_A));
2279 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2280 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2281 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2282
2283 val = I915_READ(FDI_RX_CTL(PIPE_A));
2284 val &= ~FDI_PCDCLK;
2285 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2286
2287 val = I915_READ(FDI_RX_CTL(PIPE_A));
2288 val &= ~FDI_RX_PLL_ENABLE;
2289 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2290}
2291
fd6bbda9
ML		 2292static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2293 struct intel_crtc_state *pipe_config,
2294 struct drm_connector_state *conn_state)
72662e10 2295{
6547fef8 2296 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2297 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6547fef8
PZ		 2298 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2299 int type = intel_encoder->type;
72662e10 2300
6547fef8 2301 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2302 struct intel_digital_port *intel_dig_port =
2303 enc_to_dig_port(encoder);
15953637
SS		 2304 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2305 bool scrambling = pipe_config->hdmi_scrambling;
2306
2307 intel_hdmi_handle_sink_scrambling(intel_encoder,
2308 conn_state->connector,
2309 clock_ratio, scrambling);
876a8cdf 2310
6547fef8
PZ		 2311 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2312 * are ignored so nothing special needs to be done besides
2313 * enabling the port.
2314 */
876a8cdf 2315 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2316 intel_dig_port->saved_port_bits |
2317 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2318 } else if (type == INTEL_OUTPUT_EDP) {
2319 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2320
66478475 2321 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3ab9c637
ID		 2322 intel_dp_stop_link_train(intel_dp);
2323
b037d58f 2324 intel_edp_backlight_on(pipe_config, conn_state);
0bc12bcb 2325 intel_psr_enable(intel_dp);
85cb48a1 2326 intel_edp_drrs_enable(intel_dp, pipe_config);
6547fef8 2327 }
7b9f35a6 2328
37255d8d 2329 if (pipe_config->has_audio)
bbf35e9d 2330 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
5ab432ef
DV		 2331}
2332
fd6bbda9
ML		 2333static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2334 struct intel_crtc_state *old_crtc_state,
2335 struct drm_connector_state *old_conn_state)
5ab432ef 2336{
d6c50ff8
PZ		 2337 struct drm_encoder *encoder = &intel_encoder->base;
2338 int type = intel_encoder->type;
2339
37255d8d 2340 if (old_crtc_state->has_audio)
69bfe1a9 2341 intel_audio_codec_disable(intel_encoder);
2831d842 2342
15953637
SS		 2343 if (type == INTEL_OUTPUT_HDMI) {
2344 intel_hdmi_handle_sink_scrambling(intel_encoder,
2345 old_conn_state->connector,
2346 false, false);
2347 }
2348
d6c50ff8
PZ		 2349 if (type == INTEL_OUTPUT_EDP) {
2350 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2351
85cb48a1 2352 intel_edp_drrs_disable(intel_dp, old_crtc_state);
0bc12bcb 2353 intel_psr_disable(intel_dp);
b037d58f 2354 intel_edp_backlight_off(old_conn_state);
d6c50ff8 2355 }
72662e10 2356}
79f689aa 2357
fd6bbda9
ML		 2358static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2359 struct intel_crtc_state *pipe_config,
2360 struct drm_connector_state *conn_state)
95a7a2ae 2361{
3dc38eea 2362 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2363
47a6bc61 2364 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2365}
2366
ad64217b 2367void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2368{
ad64217b
ACO		 2369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2370 struct drm_i915_private *dev_priv =
2371 to_i915(intel_dig_port->base.base.dev);
174edf1f 2372 enum port port = intel_dig_port->port;
c19b0669 2373 uint32_t val;
f3e227df 2374 bool wait = false;
c19b0669
PZ		 2375
2376 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2377 val = I915_READ(DDI_BUF_CTL(port));
2378 if (val & DDI_BUF_CTL_ENABLE) {
2379 val &= ~DDI_BUF_CTL_ENABLE;
2380 I915_WRITE(DDI_BUF_CTL(port), val);
2381 wait = true;
2382 }
2383
2384 val = I915_READ(DP_TP_CTL(port));
2385 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2386 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2387 I915_WRITE(DP_TP_CTL(port), val);
2388 POSTING_READ(DP_TP_CTL(port));
2389
2390 if (wait)
2391 intel_wait_ddi_buf_idle(dev_priv, port);
2392 }
2393
0e32b39c 2394 val = DP_TP_CTL_ENABLE |
c19b0669 2395 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2396 if (intel_dp->link_mst)
0e32b39c
DA		 2397 val |= DP_TP_CTL_MODE_MST;
2398 else {
2399 val |= DP_TP_CTL_MODE_SST;
2400 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2401 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2402 }
c19b0669
PZ		 2403 I915_WRITE(DP_TP_CTL(port), val);
2404 POSTING_READ(DP_TP_CTL(port));
2405
2406 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2407 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2408 POSTING_READ(DDI_BUF_CTL(port));
2409
2410 udelay(600);
2411}
00c09d70 2412
9935f7fa
LY		 2413bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2414 struct intel_crtc *intel_crtc)
2415{
2416 u32 temp;
2417
2418 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2419 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2420 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2421 return true;
2422 }
2423 return false;
2424}
2425
6801c18c 2426void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2427 struct intel_crtc_state *pipe_config)
045ac3b5 2428{
fac5e23e 2429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2430 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2431 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2432 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2433 u32 temp, flags = 0;
2434
4d1de975
JN		 2435 /* XXX: DSI transcoder paranoia */
2436 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2437 return;
2438
045ac3b5
JB		 2439 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2440 if (temp & TRANS_DDI_PHSYNC)
2441 flags |= DRM_MODE_FLAG_PHSYNC;
2442 else
2443 flags |= DRM_MODE_FLAG_NHSYNC;
2444 if (temp & TRANS_DDI_PVSYNC)
2445 flags |= DRM_MODE_FLAG_PVSYNC;
2446 else
2447 flags |= DRM_MODE_FLAG_NVSYNC;
2448
2d112de7 2449 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2450
2451 switch (temp & TRANS_DDI_BPC_MASK) {
2452 case TRANS_DDI_BPC_6:
2453 pipe_config->pipe_bpp = 18;
2454 break;
2455 case TRANS_DDI_BPC_8:
2456 pipe_config->pipe_bpp = 24;
2457 break;
2458 case TRANS_DDI_BPC_10:
2459 pipe_config->pipe_bpp = 30;
2460 break;
2461 case TRANS_DDI_BPC_12:
2462 pipe_config->pipe_bpp = 36;
2463 break;
2464 default:
2465 break;
2466 }
eb14cb74
VS		 2467
2468 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2469 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2470 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2471 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2472
cda0aaaf 2473 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2474 pipe_config->has_infoframe = true;
15953637
SS		 2475
2476 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2477 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2478 pipe_config->hdmi_scrambling = true;
2479 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2480 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2481 /* fall through */
eb14cb74 2482 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2483 pipe_config->lane_count = 4;
2484 break;
eb14cb74
VS		 2485 case TRANS_DDI_MODE_SELECT_FDI:
2486 break;
2487 case TRANS_DDI_MODE_SELECT_DP_SST:
2488 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2489 pipe_config->lane_count =
2490 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2491 intel_dp_get_m_n(intel_crtc, pipe_config);
2492 break;
2493 default:
2494 break;
2495 }
10214420 2496
9935f7fa
LY		 2497 pipe_config->has_audio =
2498 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2499
6aa23e65
JN		 2500 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2501 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2502 /*
2503 * This is a big fat ugly hack.
2504 *
2505 * Some machines in UEFI boot mode provide us a VBT that has 18
2506 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2507 * unknown we fail to light up. Yet the same BIOS boots up with
2508 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2509 * max, not what it tells us to use.
2510 *
2511 * Note: This will still be broken if the eDP panel is not lit
2512 * up by the BIOS, and thus we can't get the mode at module
2513 * load.
2514 */
2515 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2516 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2517 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2518 }
11578553 2519
22606a18 2520 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2521
cc3f90f0 2522 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2523 pipe_config->lane_lat_optim_mask =
2524 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2525}
2526
5bfe2ac0 2527static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2528 struct intel_crtc_state *pipe_config,
2529 struct drm_connector_state *conn_state)
00c09d70 2530{
fac5e23e 2531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2532 int type = encoder->type;
eccb140b 2533 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2534 int ret;
00c09d70 2535
5bfe2ac0 2536 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2537
eccb140b
DV		 2538 if (port == PORT_A)
2539 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2540
00c09d70 2541 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2542 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2543 else
0a478c27 2544 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2545
cc3f90f0 2546 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2547 pipe_config->lane_lat_optim_mask =
2548 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2549 pipe_config->lane_count);
95a7a2ae
ID		 2550
2551 return ret;
2552
00c09d70
PZ		 2553}
2554
2555static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2556 .reset = intel_dp_encoder_reset,
2557 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2558};
2559
4a28ae58
PZ		 2560static struct intel_connector *
2561intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2562{
2563 struct intel_connector *connector;
2564 enum port port = intel_dig_port->port;
2565
9bdbd0b9 2566 connector = intel_connector_alloc();
4a28ae58
PZ		 2567 if (!connector)
2568 return NULL;
2569
2570 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2571 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2572 kfree(connector);
2573 return NULL;
2574 }
2575
2576 return connector;
2577}
2578
2579static struct intel_connector *
2580intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2581{
2582 struct intel_connector *connector;
2583 enum port port = intel_dig_port->port;
2584
9bdbd0b9 2585 connector = intel_connector_alloc();
4a28ae58
PZ		 2586 if (!connector)
2587 return NULL;
2588
2589 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2590 intel_hdmi_init_connector(intel_dig_port, connector);
2591
2592 return connector;
2593}
2594
c39055b0 2595void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2596{
2597 struct intel_digital_port *intel_dig_port;
2598 struct intel_encoder *intel_encoder;
2599 struct drm_encoder *encoder;
ff662124 2600 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2601 int max_lanes;
2602
2603 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2604 switch (port) {
2605 case PORT_A:
2606 max_lanes = 4;
2607 break;
2608 case PORT_E:
2609 max_lanes = 0;
2610 break;
2611 default:
2612 max_lanes = 4;
2613 break;
2614 }
2615 } else {
2616 switch (port) {
2617 case PORT_A:
2618 max_lanes = 2;
2619 break;
2620 case PORT_E:
2621 max_lanes = 2;
2622 break;
2623 default:
2624 max_lanes = 4;
2625 break;
2626 }
2627 }
311a2094
PZ		 2628
2629 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2630 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2631 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2632
2633 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2634 /*
2635 * Lspcon device needs to be driven with DP connector
2636 * with special detection sequence. So make sure DP
2637 * is initialized before lspcon.
2638 */
2639 init_dp = true;
2640 init_lspcon = true;
2641 init_hdmi = false;
2642 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2643 }
2644
311a2094 2645 if (!init_dp && !init_hdmi) {
500ea70d 2646 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2647 port_name(port));
500ea70d 2648 return;
311a2094 2649 }
00c09d70 2650
b14c5679 2651 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2652 if (!intel_dig_port)
2653 return;
2654
00c09d70
PZ		 2655 intel_encoder = &intel_dig_port->base;
2656 encoder = &intel_encoder->base;
2657
c39055b0 2658 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2659 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2660
5bfe2ac0 2661 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2662 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2663 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2664 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2665 intel_encoder->pre_enable = intel_ddi_pre_enable;
2666 intel_encoder->disable = intel_disable_ddi;
2667 intel_encoder->post_disable = intel_ddi_post_disable;
2668 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2669 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2670 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2671 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2672
2673 intel_dig_port->port = port;
bcf53de4
SM		 2674 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2675 (DDI_BUF_PORT_REVERSAL |
2676 DDI_A_4_LANES);
00c09d70 2677
62b69566
ACO		 2678 switch (port) {
2679 case PORT_A:
2680 intel_dig_port->ddi_io_power_domain =
2681 POWER_DOMAIN_PORT_DDI_A_IO;
2682 break;
2683 case PORT_B:
2684 intel_dig_port->ddi_io_power_domain =
2685 POWER_DOMAIN_PORT_DDI_B_IO;
2686 break;
2687 case PORT_C:
2688 intel_dig_port->ddi_io_power_domain =
2689 POWER_DOMAIN_PORT_DDI_C_IO;
2690 break;
2691 case PORT_D:
2692 intel_dig_port->ddi_io_power_domain =
2693 POWER_DOMAIN_PORT_DDI_D_IO;
2694 break;
2695 case PORT_E:
2696 intel_dig_port->ddi_io_power_domain =
2697 POWER_DOMAIN_PORT_DDI_E_IO;
2698 break;
2699 default:
2700 MISSING_CASE(port);
2701 }
2702
6c566dc9
MR		 2703 /*
2704 * Bspec says that DDI_A_4_LANES is the only supported configuration
2705 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2706 * wasn't lit up at boot. Force this bit on in our internal
2707 * configuration so that we use the proper lane count for our
2708 * calculations.
2709 */
cc3f90f0 2710 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2711 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2712 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2713 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2714 max_lanes = 4;
6c566dc9
MR		 2715 }
2716 }
2717
ed8d60f4
MR		 2718 intel_dig_port->max_lanes = max_lanes;
2719
00c09d70 2720 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2721 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2722 intel_encoder->port = port;
f68d697e 2723 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2724 intel_encoder->cloneable = 0;
00c09d70 2725
f68d697e
CW		 2726 if (init_dp) {
2727 if (!intel_ddi_init_dp_connector(intel_dig_port))
2728 goto err;
13cf5504 2729
f68d697e 2730 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2731 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2732 }
21a8e6a4 2733
311a2094
PZ		 2734 /* In theory we don't need the encoder->type check, but leave it just in
2735 * case we have some really bad VBTs... */
f68d697e
CW		 2736 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2737 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2738 goto err;
21a8e6a4 2739 }
f68d697e 2740
ff662124
SS		 2741 if (init_lspcon) {
2742 if (lspcon_init(intel_dig_port))
2743 /* TODO: handle hdmi info frame part */
2744 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2745 port_name(port));
2746 else
2747 /*
2748 * LSPCON init faied, but DP init was success, so
2749 * lets try to drive as DP++ port.
2750 */
2751 DRM_ERROR("LSPCON init failed on port %c\n",
2752 port_name(port));
2753 }
2754
f68d697e
CW		 2755 return;
2756
2757err:
2758 drm_encoder_cleanup(encoder);
2759 kfree(intel_dig_port);
00c09d70 2760}
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