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drm/i915: Move bxt_ddi_vswing_sequence() call into intel_ddi_pre_enable() for HDMI
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
a1e6ad66
ID		 304static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
305 struct intel_digital_port **dig_port,
306 enum port *port)
fc914639 307{
0bdee30e 308 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 309
8cd21b7f
JN		 310 switch (intel_encoder->type) {
311 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 312 *dig_port = enc_to_mst(encoder)->primary;
313 *port = (*dig_port)->port;
8cd21b7f 314 break;
183aec16
CW		 315 default:
316 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
317 /* fallthrough and treat as unknown */
cca0502b 318 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f 328 break;
fc914639
PZ		 329 }
330}
331
a1e6ad66
ID		 332enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
333{
334 struct intel_digital_port *dig_port;
335 enum port port;
336
337 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
338
339 return port;
340}
341
acee2998 342static const struct ddi_buf_trans *
78ab0bae 343skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 344{
78ab0bae 345 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 346 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 347 return skl_y_ddi_translations_dp;
78ab0bae 348 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 349 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 350 return skl_u_ddi_translations_dp;
f8896f5d 351 } else {
f8896f5d 352 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 353 return skl_ddi_translations_dp;
f8896f5d 354 }
f8896f5d
DW		 355}
356
acee2998 357static const struct ddi_buf_trans *
78ab0bae 358skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 359{
06411f08 360 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 361 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 362 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 363 return skl_y_ddi_translations_edp;
78ab0bae 364 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 365 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 366 return skl_u_ddi_translations_edp;
f8896f5d 367 } else {
f8896f5d 368 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 369 return skl_ddi_translations_edp;
f8896f5d
DW		 370 }
371 }
cd1101cb 372
78ab0bae 373 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 374}
375
376static const struct ddi_buf_trans *
78ab0bae 377skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 378{
78ab0bae 379 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 380 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 381 return skl_y_ddi_translations_hdmi;
f8896f5d 382 } else {
f8896f5d 383 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 384 return skl_ddi_translations_hdmi;
f8896f5d 385 }
f8896f5d
DW		 386}
387
8d8bb85e
VS		 388static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
389{
390 int n_hdmi_entries;
391 int hdmi_level;
392 int hdmi_default_entry;
393
394 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
395
396 if (IS_BROXTON(dev_priv))
397 return hdmi_level;
398
399 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
400 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
401 hdmi_default_entry = 8;
402 } else if (IS_BROADWELL(dev_priv)) {
403 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
404 hdmi_default_entry = 7;
405 } else if (IS_HASWELL(dev_priv)) {
406 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
407 hdmi_default_entry = 6;
408 } else {
409 WARN(1, "ddi translation table missing\n");
410 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
411 hdmi_default_entry = 7;
412 }
413
414 /* Choose a good default if VBT is badly populated */
415 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
416 hdmi_level >= n_hdmi_entries)
417 hdmi_level = hdmi_default_entry;
418
419 return hdmi_level;
420}
421
e58623cb
AR		 422/*
423 * Starting with Haswell, DDI port buffers must be programmed with correct
424 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 425 * but the HDMI/DVI fields are shared among those. So we program the DDI
426 * in either FDI or DP modes only, as HDMI connections will work with both
427 * of those
428 */
6a7e4f99 429void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
45244b87 430{
6a7e4f99 431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 432 u32 iboost_bit = 0;
8d8bb85e 433 int i, n_hdmi_entries, n_dp_entries, n_edp_entries,
7ad14a29 434 size;
6a7e4f99
VS		 435 int hdmi_level;
436 enum port port;
10122051
JN		 437 const struct ddi_buf_trans *ddi_translations_fdi;
438 const struct ddi_buf_trans *ddi_translations_dp;
439 const struct ddi_buf_trans *ddi_translations_edp;
440 const struct ddi_buf_trans *ddi_translations_hdmi;
441 const struct ddi_buf_trans *ddi_translations;
e58623cb 442
6a7e4f99 443 port = intel_ddi_get_encoder_port(encoder);
8d8bb85e 444 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
6a7e4f99 445
9f332437 446 if (IS_BROXTON(dev_priv))
96fb9f9b 447 return;
6a7e4f99
VS		 448
449 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 450 ddi_translations_fdi = NULL;
f8896f5d 451 ddi_translations_dp =
78ab0bae 452 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 453 ddi_translations_edp =
78ab0bae 454 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 455 ddi_translations_hdmi =
78ab0bae 456 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
75067dde
AK		 457 /* If we're boosting the current, set bit 31 of trans1 */
458 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
459 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
c110ae6c 460 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
10afa0b6 461
ceccad59
VS		 462 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
463 port != PORT_A && port != PORT_E &&
464 n_edp_entries > 9))
10afa0b6 465 n_edp_entries = 9;
78ab0bae 466 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 467 ddi_translations_fdi = bdw_ddi_translations_fdi;
468 ddi_translations_dp = bdw_ddi_translations_dp;
00983519
MK		 469
470 if (dev_priv->vbt.edp.low_vswing) {
471 ddi_translations_edp = bdw_ddi_translations_edp;
472 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
473 } else {
474 ddi_translations_edp = bdw_ddi_translations_dp;
475 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
476 }
477
a26aa8ba 478 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
00983519 479
7ad14a29 480 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 481 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
78ab0bae 482 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 483 ddi_translations_fdi = hsw_ddi_translations_fdi;
484 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 485 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 486 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 487 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 488 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
e58623cb
AR		 489 } else {
490 WARN(1, "ddi translation table missing\n");
300644c7 491 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 492 ddi_translations_fdi = bdw_ddi_translations_fdi;
493 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 494 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 495 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
496 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 497 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
e58623cb
AR		 498 }
499
6a7e4f99
VS		 500 switch (encoder->type) {
501 case INTEL_OUTPUT_EDP:
300644c7 502 ddi_translations = ddi_translations_edp;
7ad14a29 503 size = n_edp_entries;
300644c7 504 break;
cca0502b 505 case INTEL_OUTPUT_DP:
6a7e4f99 506 case INTEL_OUTPUT_HDMI:
300644c7 507 ddi_translations = ddi_translations_dp;
7ad14a29 508 size = n_dp_entries;
300644c7 509 break;
6a7e4f99
VS		 510 case INTEL_OUTPUT_ANALOG:
511 ddi_translations = ddi_translations_fdi;
7ad14a29 512 size = n_dp_entries;
300644c7
PZ		 513 break;
514 default:
515 BUG();
516 }
45244b87 517
9712e688
VS		 518 for (i = 0; i < size; i++) {
519 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
520 ddi_translations[i].trans1 | iboost_bit);
521 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
522 ddi_translations[i].trans2);
45244b87 523 }
ce4dd49e 524
6a7e4f99 525 if (encoder->type != INTEL_OUTPUT_HDMI)
ce3b7e9b
DL		 526 return;
527
6acab15a 528 /* Entry 9 is for HDMI: */
9712e688
VS		 529 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
530 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
531 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
532 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 533}
534
248138b5
PZ		 535static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
536 enum port port)
537{
f0f59a00 538 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 539 int i;
540
3449ca85 541 for (i = 0; i < 16; i++) {
248138b5
PZ		 542 udelay(1);
543 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
544 return;
545 }
546 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
547}
c82e4d26
ED		 548
549/* Starting with Haswell, different DDI ports can work in FDI mode for
550 * connection to the PCH-located connectors. For this, it is necessary to train
551 * both the DDI port and PCH receiver for the desired DDI buffer settings.
552 *
553 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
554 * please note that when FDI mode is active on DDI E, it shares 2 lines with
555 * DDI A (which is used for eDP)
556 */
557
558void hsw_fdi_link_train(struct drm_crtc *crtc)
559{
560 struct drm_device *dev = crtc->dev;
fac5e23e 561 struct drm_i915_private *dev_priv = to_i915(dev);
c82e4d26 562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6a7e4f99 563 struct intel_encoder *encoder;
04945641 564 u32 temp, i, rx_ctl_val;
c82e4d26 565
6a7e4f99
VS		 566 for_each_encoder_on_crtc(dev, crtc, encoder) {
567 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
568 intel_prepare_ddi_buffer(encoder);
569 }
570
04945641
PZ		 571 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
572 * mode set "sequence for CRT port" document:
573 * - TP1 to TP2 time with the default value
574 * - FDI delay to 90h
8693a824
DL		 575 *
576 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 577 */
eede3b53 578 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 579 FDI_RX_PWRDN_LANE0_VAL(2) |
580 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
581
582 /* Enable the PCH Receiver FDI PLL */
3e68320e 583 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 584 FDI_RX_PLL_ENABLE |
6e3c9717 585 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 586 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
587 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 588 udelay(220);
589
590 /* Switch from Rawclk to PCDclk */
591 rx_ctl_val |= FDI_PCDCLK;
eede3b53 592 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 593
594 /* Configure Port Clock Select */
6e3c9717
ACO		 595 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
596 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 597
598 /* Start the training iterating through available voltages and emphasis,
599 * testing each value twice. */
10122051 600 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 601 /* Configure DP_TP_CTL with auto-training */
602 I915_WRITE(DP_TP_CTL(PORT_E),
603 DP_TP_CTL_FDI_AUTOTRAIN |
604 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
605 DP_TP_CTL_LINK_TRAIN_PAT1 |
606 DP_TP_CTL_ENABLE);
607
876a8cdf
DL		 608 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
609 * DDI E does not support port reversal, the functionality is
610 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
611 * port reversal bit */
c82e4d26 612 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 613 DDI_BUF_CTL_ENABLE |
6e3c9717 614 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 615 DDI_BUF_TRANS_SELECT(i / 2));
04945641 616 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 617
618 udelay(600);
619
04945641 620 /* Program PCH FDI Receiver TU */
eede3b53 621 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 622
623 /* Enable PCH FDI Receiver with auto-training */
624 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 625 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
626 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 627
628 /* Wait for FDI receiver lane calibration */
629 udelay(30);
630
631 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 632 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 633 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 634 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
635 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 636
637 /* Wait for FDI auto training time */
638 udelay(5);
c82e4d26
ED		 639
640 temp = I915_READ(DP_TP_STATUS(PORT_E));
641 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 642 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 643 break;
644 }
c82e4d26 645
a308ccb3
VS		 646 /*
647 * Leave things enabled even if we failed to train FDI.
648 * Results in less fireworks from the state checker.
649 */
650 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
651 DRM_ERROR("FDI link training failed!\n");
652 break;
c82e4d26 653 }
04945641 654
5b421c57
VS		 655 rx_ctl_val &= ~FDI_RX_ENABLE;
656 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
657 POSTING_READ(FDI_RX_CTL(PIPE_A));
658
248138b5
PZ		 659 temp = I915_READ(DDI_BUF_CTL(PORT_E));
660 temp &= ~DDI_BUF_CTL_ENABLE;
661 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
662 POSTING_READ(DDI_BUF_CTL(PORT_E));
663
04945641 664 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 665 temp = I915_READ(DP_TP_CTL(PORT_E));
666 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
667 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
668 I915_WRITE(DP_TP_CTL(PORT_E), temp);
669 POSTING_READ(DP_TP_CTL(PORT_E));
670
671 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 672
04945641 673 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 674 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 675 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
676 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
678 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 679 }
680
a308ccb3
VS		 681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
c82e4d26 687}
0e72a5b5 688
44905a27
DA		 689void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
690{
691 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
692 struct intel_digital_port *intel_dig_port =
693 enc_to_dig_port(&encoder->base);
694
695 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 696 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 697 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 698}
699
8d9ddbcb
PZ		 700static struct intel_encoder *
701intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
702{
703 struct drm_device *dev = crtc->dev;
704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
705 struct intel_encoder *intel_encoder, *ret = NULL;
706 int num_encoders = 0;
707
708 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
709 ret = intel_encoder;
710 num_encoders++;
711 }
712
713 if (num_encoders != 1)
84f44ce7
VS		 714 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
715 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 716
717 BUG_ON(ret == NULL);
718 return ret;
719}
720
bcddf610 721struct intel_encoder *
3165c074 722intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 723{
3165c074
ACO		 724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
725 struct intel_encoder *ret = NULL;
726 struct drm_atomic_state *state;
da3ced29
ACO		 727 struct drm_connector *connector;
728 struct drm_connector_state *connector_state;
d0737e1d 729 int num_encoders = 0;
3165c074 730 int i;
d0737e1d 731
3165c074
ACO		 732 state = crtc_state->base.state;
733
da3ced29
ACO		 734 for_each_connector_in_state(state, connector, connector_state, i) {
735 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 736 continue;
737
da3ced29 738 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 739 num_encoders++;
d0737e1d
ACO		 740 }
741
742 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
743 pipe_name(crtc->pipe));
744
745 BUG_ON(ret == NULL);
746 return ret;
747}
748
1c0b85c5 749#define LC_FREQ 2700
1c0b85c5 750
f0f59a00
VS		 751static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
752 i915_reg_t reg)
11578553
JB		 753{
754 int refclk = LC_FREQ;
755 int n, p, r;
756 u32 wrpll;
757
758 wrpll = I915_READ(reg);
114fe488
DV		 759 switch (wrpll & WRPLL_PLL_REF_MASK) {
760 case WRPLL_PLL_SSC:
761 case WRPLL_PLL_NON_SSC:
11578553
JB		 762 /*
763 * We could calculate spread here, but our checking
764 * code only cares about 5% accuracy, and spread is a max of
765 * 0.5% downspread.
766 */
767 refclk = 135;
768 break;
114fe488 769 case WRPLL_PLL_LCPLL:
11578553
JB		 770 refclk = LC_FREQ;
771 break;
772 default:
773 WARN(1, "bad wrpll refclk\n");
774 return 0;
775 }
776
777 r = wrpll & WRPLL_DIVIDER_REF_MASK;
778 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
779 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
780
20f0ec16
JB		 781 /* Convert to KHz, p & r have a fixed point portion */
782 return (refclk * n * 100) / (p * r);
11578553
JB		 783}
784
540e732c
S		 785static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
786 uint32_t dpll)
787{
f0f59a00 788 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 789 uint32_t cfgcr1_val, cfgcr2_val;
790 uint32_t p0, p1, p2, dco_freq;
791
923c1241
VS		 792 cfgcr1_reg = DPLL_CFGCR1(dpll);
793 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 794
795 cfgcr1_val = I915_READ(cfgcr1_reg);
796 cfgcr2_val = I915_READ(cfgcr2_reg);
797
798 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
799 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
800
801 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
802 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
803 else
804 p1 = 1;
805
806
807 switch (p0) {
808 case DPLL_CFGCR2_PDIV_1:
809 p0 = 1;
810 break;
811 case DPLL_CFGCR2_PDIV_2:
812 p0 = 2;
813 break;
814 case DPLL_CFGCR2_PDIV_3:
815 p0 = 3;
816 break;
817 case DPLL_CFGCR2_PDIV_7:
818 p0 = 7;
819 break;
820 }
821
822 switch (p2) {
823 case DPLL_CFGCR2_KDIV_5:
824 p2 = 5;
825 break;
826 case DPLL_CFGCR2_KDIV_2:
827 p2 = 2;
828 break;
829 case DPLL_CFGCR2_KDIV_3:
830 p2 = 3;
831 break;
832 case DPLL_CFGCR2_KDIV_1:
833 p2 = 1;
834 break;
835 }
836
837 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
838
839 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
840 1000) / 0x8000;
841
842 return dco_freq / (p0 * p1 * p2 * 5);
843}
844
398a017e
VS		 845static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
846{
847 int dotclock;
848
849 if (pipe_config->has_pch_encoder)
850 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
851 &pipe_config->fdi_m_n);
37a5650b 852 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 853 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
854 &pipe_config->dp_m_n);
855 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
856 dotclock = pipe_config->port_clock * 2 / 3;
857 else
858 dotclock = pipe_config->port_clock;
859
860 if (pipe_config->pixel_multiplier)
861 dotclock /= pipe_config->pixel_multiplier;
862
863 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
864}
540e732c
S		 865
866static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 867 struct intel_crtc_state *pipe_config)
540e732c 868{
fac5e23e 869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 870 int link_clock = 0;
871 uint32_t dpll_ctl1, dpll;
872
134ffa44 873 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 874
875 dpll_ctl1 = I915_READ(DPLL_CTRL1);
876
877 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
878 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
879 } else {
71cd8423
DL		 880 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
881 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 882
883 switch (link_clock) {
71cd8423 884 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 885 link_clock = 81000;
886 break;
71cd8423 887 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 888 link_clock = 108000;
889 break;
71cd8423 890 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 891 link_clock = 135000;
892 break;
71cd8423 893 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 894 link_clock = 162000;
895 break;
71cd8423 896 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 897 link_clock = 216000;
898 break;
71cd8423 899 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 900 link_clock = 270000;
901 break;
902 default:
903 WARN(1, "Unsupported link rate\n");
904 break;
905 }
906 link_clock *= 2;
907 }
908
909 pipe_config->port_clock = link_clock;
910
398a017e 911 ddi_dotclock_get(pipe_config);
540e732c
S		 912}
913
3d51278a 914static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 915 struct intel_crtc_state *pipe_config)
11578553 916{
fac5e23e 917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 918 int link_clock = 0;
919 u32 val, pll;
920
26804afd 921 val = pipe_config->ddi_pll_sel;
11578553
JB		 922 switch (val & PORT_CLK_SEL_MASK) {
923 case PORT_CLK_SEL_LCPLL_810:
924 link_clock = 81000;
925 break;
926 case PORT_CLK_SEL_LCPLL_1350:
927 link_clock = 135000;
928 break;
929 case PORT_CLK_SEL_LCPLL_2700:
930 link_clock = 270000;
931 break;
932 case PORT_CLK_SEL_WRPLL1:
01403de3 933 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 934 break;
935 case PORT_CLK_SEL_WRPLL2:
01403de3 936 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 937 break;
938 case PORT_CLK_SEL_SPLL:
939 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
940 if (pll == SPLL_PLL_FREQ_810MHz)
941 link_clock = 81000;
942 else if (pll == SPLL_PLL_FREQ_1350MHz)
943 link_clock = 135000;
944 else if (pll == SPLL_PLL_FREQ_2700MHz)
945 link_clock = 270000;
946 else {
947 WARN(1, "bad spll freq\n");
948 return;
949 }
950 break;
951 default:
952 WARN(1, "bad port clock sel\n");
953 return;
954 }
955
956 pipe_config->port_clock = link_clock * 2;
957
398a017e 958 ddi_dotclock_get(pipe_config);
11578553
JB		 959}
960
977bb38d
S		 961static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
962 enum intel_dpll_id dpll)
963{
aa610dcb
ID		 964 struct intel_shared_dpll *pll;
965 struct intel_dpll_hw_state *state;
9e2c8475 966 struct dpll clock;
aa610dcb
ID		 967
968 /* For DDI ports we always use a shared PLL. */
969 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
970 return 0;
971
972 pll = &dev_priv->shared_dplls[dpll];
973 state = &pll->config.hw_state;
974
975 clock.m1 = 2;
976 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
977 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
978 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
979 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
980 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
981 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
982
983 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 984}
985
986static void bxt_ddi_clock_get(struct intel_encoder *encoder,
987 struct intel_crtc_state *pipe_config)
988{
fac5e23e 989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 990 enum port port = intel_ddi_get_encoder_port(encoder);
991 uint32_t dpll = port;
992
398a017e 993 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 994
398a017e 995 ddi_dotclock_get(pipe_config);
977bb38d
S		 996}
997
3d51278a 998void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 999 struct intel_crtc_state *pipe_config)
3d51278a 1000{
22606a18
DL		 1001 struct drm_device *dev = encoder->base.dev;
1002
1003 if (INTEL_INFO(dev)->gen <= 8)
1004 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1005 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1006 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1007 else if (IS_BROXTON(dev))
1008 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1009}
1010
0220ab6e 1011static bool
d664c0ce 1012hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1013 struct intel_crtc_state *crtc_state,
96f3f1f9 1014 struct intel_encoder *intel_encoder)
6441ab5f 1015{
daedf20a 1016 struct intel_shared_dpll *pll;
6441ab5f 1017
9d16da65
ACO		 1018 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1019 intel_encoder);
1020 if (!pll)
1021 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022 pipe_name(intel_crtc->pipe));
1023
1024 return pll;
6441ab5f
PZ		 1025}
1026
82d35437
S		 1027static bool
1028skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1029 struct intel_crtc_state *crtc_state,
96f3f1f9 1030 struct intel_encoder *intel_encoder)
82d35437
S		 1031{
1032 struct intel_shared_dpll *pll;
82d35437 1033
daedf20a 1034 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
82d35437
S		 1035 if (pll == NULL) {
1036 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1037 pipe_name(intel_crtc->pipe));
1038 return false;
1039 }
1040
82d35437
S		 1041 return true;
1042}
0220ab6e 1043
d683f3bc
S		 1044static bool
1045bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1046 struct intel_crtc_state *crtc_state,
96f3f1f9 1047 struct intel_encoder *intel_encoder)
d683f3bc 1048{
34177c24 1049 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
d683f3bc
S		 1050}
1051
0220ab6e
DL		 1052/*
1053 * Tries to find a *shared* PLL for the CRTC and store it in
1054 * intel_crtc->ddi_pll_sel.
1055 *
1056 * For private DPLLs, compute_config() should do the selection for us. This
1057 * function should be folded into compute_config() eventually.
1058 */
190f68c5
ACO		 1059bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1060 struct intel_crtc_state *crtc_state)
0220ab6e 1061{
82d35437 1062 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1063 struct intel_encoder *intel_encoder =
3165c074 1064 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1065
ef11bdb3 1066 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1067 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1068 intel_encoder);
d683f3bc
S		 1069 else if (IS_BROXTON(dev))
1070 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1071 intel_encoder);
82d35437 1072 else
190f68c5 1073 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1074 intel_encoder);
0220ab6e
DL		 1075}
1076
dae84799
PZ		 1077void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1078{
fac5e23e 1079 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
dae84799
PZ		 1080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1081 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1082 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1083 int type = intel_encoder->type;
1084 uint32_t temp;
1085
cca0502b 1086 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1087 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1088
c9809791 1089 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1090 switch (intel_crtc->config->pipe_bpp) {
dae84799 1091 case 18:
c9809791 1092 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1093 break;
1094 case 24:
c9809791 1095 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1096 break;
1097 case 30:
c9809791 1098 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1099 break;
1100 case 36:
c9809791 1101 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1102 break;
1103 default:
4e53c2e0 1104 BUG();
dae84799 1105 }
c9809791 1106 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1107 }
1108}
1109
0e32b39c
DA		 1110void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1111{
1112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113 struct drm_device *dev = crtc->dev;
fac5e23e 1114 struct drm_i915_private *dev_priv = to_i915(dev);
6e3c9717 1115 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1116 uint32_t temp;
1117 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1118 if (state == true)
1119 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1120 else
1121 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1122 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1123}
1124
8228c251 1125void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1126{
1127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1128 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1129 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10 1130 struct drm_device *dev = crtc->dev;
fac5e23e 1131 struct drm_i915_private *dev_priv = to_i915(dev);
8d9ddbcb 1132 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1133 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1134 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1135 int type = intel_encoder->type;
8d9ddbcb
PZ		 1136 uint32_t temp;
1137
ad80a810
PZ		 1138 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1139 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1140 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1141
6e3c9717 1142 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1143 case 18:
ad80a810 1144 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1145 break;
1146 case 24:
ad80a810 1147 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1148 break;
1149 case 30:
ad80a810 1150 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1151 break;
1152 case 36:
ad80a810 1153 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1154 break;
1155 default:
4e53c2e0 1156 BUG();
dfcef252 1157 }
72662e10 1158
6e3c9717 1159 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1160 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1161 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1162 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1163
e6f0bfc4
PZ		 1164 if (cpu_transcoder == TRANSCODER_EDP) {
1165 switch (pipe) {
1166 case PIPE_A:
c7670b10
PZ		 1167 /* On Haswell, can only use the always-on power well for
1168 * eDP when not using the panel fitter, and when not
1169 * using motion blur mitigation (which we don't
1170 * support). */
fabf6e51 1171 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1172 (intel_crtc->config->pch_pfit.enabled ||
1173 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1174 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1175 else
1176 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1177 break;
1178 case PIPE_B:
1179 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1180 break;
1181 case PIPE_C:
1182 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1183 break;
1184 default:
1185 BUG();
1186 break;
1187 }
1188 }
1189
7739c33b 1190 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1191 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1192 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1193 else
ad80a810 1194 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1195
7739c33b 1196 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1197 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1198 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b 1199
cca0502b 1200 } else if (type == INTEL_OUTPUT_DP ||
7739c33b
PZ		 1201 type == INTEL_OUTPUT_EDP) {
1202 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1203
0e32b39c
DA		 1204 if (intel_dp->is_mst) {
1205 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1206 } else
1207 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1208
90a6b7b0 1209 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1210 } else if (type == INTEL_OUTPUT_DP_MST) {
1211 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1212
1213 if (intel_dp->is_mst) {
1214 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1215 } else
1216 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1217
90a6b7b0 1218 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1219 } else {
84f44ce7
VS		 1220 WARN(1, "Invalid encoder type %d for pipe %c\n",
1221 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1222 }
1223
ad80a810 1224 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1225}
72662e10 1226
ad80a810
PZ		 1227void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1228 enum transcoder cpu_transcoder)
8d9ddbcb 1229{
f0f59a00 1230 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1231 uint32_t val = I915_READ(reg);
1232
0e32b39c 1233 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1234 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1235 I915_WRITE(reg, val);
72662e10
ED		 1236}
1237
bcbc889b
PZ		 1238bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1239{
1240 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1241 struct drm_i915_private *dev_priv = to_i915(dev);
bcbc889b
PZ		 1242 struct intel_encoder *intel_encoder = intel_connector->encoder;
1243 int type = intel_connector->base.connector_type;
1244 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1245 enum pipe pipe = 0;
1246 enum transcoder cpu_transcoder;
882244a3 1247 enum intel_display_power_domain power_domain;
bcbc889b 1248 uint32_t tmp;
e27daab4 1249 bool ret;
bcbc889b 1250
882244a3 1251 power_domain = intel_display_port_power_domain(intel_encoder);
e27daab4 1252 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1253 return false;
1254
e27daab4
ID		 1255 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1256 ret = false;
1257 goto out;
1258 }
bcbc889b
PZ		 1259
1260 if (port == PORT_A)
1261 cpu_transcoder = TRANSCODER_EDP;
1262 else
1a240d4d 1263 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1264
1265 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1266
1267 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1268 case TRANS_DDI_MODE_SELECT_HDMI:
1269 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1270 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1271 break;
bcbc889b
PZ		 1272
1273 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1274 ret = type == DRM_MODE_CONNECTOR_eDP ||
1275 type == DRM_MODE_CONNECTOR_DisplayPort;
1276 break;
1277
0e32b39c
DA		 1278 case TRANS_DDI_MODE_SELECT_DP_MST:
1279 /* if the transcoder is in MST state then
1280 * connector isn't connected */
e27daab4
ID		 1281 ret = false;
1282 break;
bcbc889b
PZ		 1283
1284 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1285 ret = type == DRM_MODE_CONNECTOR_VGA;
1286 break;
bcbc889b
PZ		 1287
1288 default:
e27daab4
ID		 1289 ret = false;
1290 break;
bcbc889b 1291 }
e27daab4
ID		 1292
1293out:
1294 intel_display_power_put(dev_priv, power_domain);
1295
1296 return ret;
bcbc889b
PZ		 1297}
1298
85234cdc
DV		 1299bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
1301{
1302 struct drm_device *dev = encoder->base.dev;
fac5e23e 1303 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1304 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1305 enum intel_display_power_domain power_domain;
85234cdc
DV		 1306 u32 tmp;
1307 int i;
e27daab4 1308 bool ret;
85234cdc 1309
6d129bea 1310 power_domain = intel_display_port_power_domain(encoder);
e27daab4 1311 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 1312 return false;
1313
e27daab4
ID		 1314 ret = false;
1315
fe43d3f5 1316 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1317
1318 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1319 goto out;
85234cdc 1320
ad80a810
PZ		 1321 if (port == PORT_A) {
1322 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1323
ad80a810
PZ		 1324 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1325 case TRANS_DDI_EDP_INPUT_A_ON:
1326 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1327 *pipe = PIPE_A;
1328 break;
1329 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1330 *pipe = PIPE_B;
1331 break;
1332 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1333 *pipe = PIPE_C;
1334 break;
1335 }
1336
e27daab4 1337 ret = true;
ad80a810 1338
e27daab4
ID		 1339 goto out;
1340 }
0e32b39c 1341
e27daab4
ID		 1342 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1343 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1344
1345 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1346 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1347 TRANS_DDI_MODE_SELECT_DP_MST)
1348 goto out;
1349
1350 *pipe = i;
1351 ret = true;
1352
1353 goto out;
85234cdc
DV		 1354 }
1355 }
1356
84f44ce7 1357 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1358
e27daab4 1359out:
e93da0a0
ID		 1360 if (ret && IS_BROXTON(dev_priv)) {
1361 tmp = I915_READ(BXT_PHY_CTL(port));
1362 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1363 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1364 DRM_ERROR("Port %c enabled but PHY powered down? "
1365 "(PHY_CTL %08x)\n", port_name(port), tmp);
1366 }
1367
e27daab4
ID		 1368 intel_display_power_put(dev_priv, power_domain);
1369
1370 return ret;
85234cdc
DV		 1371}
1372
fc914639
PZ		 1373void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1374{
1375 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0 1376 struct drm_device *dev = crtc->dev;
fac5e23e 1377 struct drm_i915_private *dev_priv = to_i915(dev);
fc914639
PZ		 1378 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1379 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1380 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1381
bb523fc0
PZ		 1382 if (cpu_transcoder != TRANSCODER_EDP)
1383 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1384 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1385}
1386
1387void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1388{
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6e3c9717 1390 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1391
bb523fc0
PZ		 1392 if (cpu_transcoder != TRANSCODER_EDP)
1393 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1394 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1395}
1396
a7d8dbc0
VS		 1397static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1398 enum port port, uint8_t iboost)
f8896f5d 1399{
a7d8dbc0
VS		 1400 u32 tmp;
1401
1402 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1403 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1404 if (iboost)
1405 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1406 else
1407 tmp |= BALANCE_LEG_DISABLE(port);
1408 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1409}
1410
1411static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1412{
1413 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1414 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1415 enum port port = intel_dig_port->port;
1416 int type = encoder->type;
f8896f5d
DW		 1417 const struct ddi_buf_trans *ddi_translations;
1418 uint8_t iboost;
75067dde 1419 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1420 int n_entries;
f8896f5d 1421
75067dde
AK		 1422 /* VBT may override standard boost values */
1423 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1424 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1425
cca0502b 1426 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1427 if (dp_iboost) {
1428 iboost = dp_iboost;
1429 } else {
78ab0bae 1430 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 1431 iboost = ddi_translations[level].i_boost;
75067dde 1432 }
f8896f5d 1433 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1434 if (dp_iboost) {
1435 iboost = dp_iboost;
1436 } else {
78ab0bae 1437 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1438
1439 if (WARN_ON(port != PORT_A &&
1440 port != PORT_E && n_entries > 9))
1441 n_entries = 9;
1442
e4d4c05b 1443 iboost = ddi_translations[level].i_boost;
75067dde 1444 }
f8896f5d 1445 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1446 if (hdmi_iboost) {
1447 iboost = hdmi_iboost;
1448 } else {
78ab0bae 1449 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1450 iboost = ddi_translations[level].i_boost;
75067dde 1451 }
f8896f5d
DW		 1452 } else {
1453 return;
1454 }
1455
1456 /* Make sure that the requested I_boost is valid */
1457 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1458 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1459 return;
1460 }
1461
a7d8dbc0 1462 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1463
a7d8dbc0
VS		 1464 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1465 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1466}
1467
78ab0bae
VS		 1468static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1469 u32 level, enum port port, int type)
96fb9f9b 1470{
96fb9f9b
VK		 1471 const struct bxt_ddi_buf_trans *ddi_translations;
1472 u32 n_entries, i;
1473 uint32_t val;
1474
06411f08 1475 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1476 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1477 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1478 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1479 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1480 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1481 ddi_translations = bxt_ddi_translations_dp;
1482 } else if (type == INTEL_OUTPUT_HDMI) {
1483 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1484 ddi_translations = bxt_ddi_translations_hdmi;
1485 } else {
1486 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1487 type);
1488 return;
1489 }
1490
1491 /* Check if default value has to be used */
1492 if (level >= n_entries ||
1493 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1494 for (i = 0; i < n_entries; i++) {
1495 if (ddi_translations[i].default_index) {
1496 level = i;
1497 break;
1498 }
1499 }
1500 }
1501
1502 /*
1503 * While we write to the group register to program all lanes at once we
1504 * can read only lane registers and we pick lanes 0/1 for that.
1505 */
1506 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1507 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1508 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1509
1510 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1511 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1512 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1513 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1514 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1515
1516 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 1517 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 1518 if (ddi_translations[level].enable)
9c58a049
SJ		 1519 val |= SCALE_DCOMP_METHOD;
1520
1521 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1522 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1523
96fb9f9b
VK		 1524 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1525
1526 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1527 val &= ~DE_EMPHASIS;
1528 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1529 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1530
1531 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1532 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1533 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1534}
1535
f8896f5d
DW		 1536static uint32_t translate_signal_level(int signal_levels)
1537{
1538 uint32_t level;
1539
1540 switch (signal_levels) {
1541 default:
1542 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1543 signal_levels);
1544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1545 level = 0;
1546 break;
1547 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1548 level = 1;
1549 break;
1550 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1551 level = 2;
1552 break;
1553 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1554 level = 3;
1555 break;
1556
1557 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1558 level = 4;
1559 break;
1560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1561 level = 5;
1562 break;
1563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1564 level = 6;
1565 break;
1566
1567 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1568 level = 7;
1569 break;
1570 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1571 level = 8;
1572 break;
1573
1574 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1575 level = 9;
1576 break;
1577 }
1578
1579 return level;
1580}
1581
1582uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1583{
1584 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 1585 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 1586 struct intel_encoder *encoder = &dport->base;
1587 uint8_t train_set = intel_dp->train_set[0];
1588 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1589 DP_TRAIN_PRE_EMPHASIS_MASK);
1590 enum port port = dport->port;
1591 uint32_t level;
1592
1593 level = translate_signal_level(signal_levels);
1594
78ab0bae 1595 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
a7d8dbc0 1596 skl_ddi_set_iboost(encoder, level);
78ab0bae
VS		 1597 else if (IS_BROXTON(dev_priv))
1598 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 1599
1600 return DDI_BUF_TRANS_SELECT(level);
1601}
1602
e404ba8d
VS		 1603void intel_ddi_clk_select(struct intel_encoder *encoder,
1604 const struct intel_crtc_state *pipe_config)
6441ab5f 1605{
e404ba8d
VS		 1606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1607 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 1608
e404ba8d
VS		 1609 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1610 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 1611 uint32_t val;
1612
5416d871 1613 /* DDI -> PLL mapping */
efa80add
S		 1614 val = I915_READ(DPLL_CTRL2);
1615
1616 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1617 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1618 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1619 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1620
1621 I915_WRITE(DPLL_CTRL2, val);
5416d871 1622
e404ba8d
VS		 1623 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1624 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1625 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 1626 }
e404ba8d
VS		 1627}
1628
1629static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1630{
1631 struct drm_encoder *encoder = &intel_encoder->base;
6a7e4f99 1632 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
e404ba8d
VS		 1633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1634 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1635 int type = intel_encoder->type;
6a7e4f99 1636
b2ccb822
VS		 1637 if (type == INTEL_OUTPUT_HDMI) {
1638 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1639
1640 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1641 }
1642
6a7e4f99 1643 intel_prepare_ddi_buffer(intel_encoder);
e404ba8d
VS		 1644
1645 if (type == INTEL_OUTPUT_EDP) {
1646 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1647 intel_edp_panel_on(intel_dp);
1648 }
1649
1650 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 1651
cca0502b 1652 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
c19b0669 1653 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1654
901c2daf
VS		 1655 intel_dp_set_link_params(intel_dp, crtc->config);
1656
44905a27 1657 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1658
1659 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1660 intel_dp_start_link_train(intel_dp);
6a7e4f99 1661 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
3ab9c637 1662 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1663 } else if (type == INTEL_OUTPUT_HDMI) {
1664 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
8d8bb85e
VS		 1665 int level = intel_ddi_hdmi_level(dev_priv, port);
1666
1667 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1668 skl_ddi_set_iboost(intel_encoder, level);
9f332437
VS		 1669 else if (IS_BROXTON(dev_priv))
1670 bxt_ddi_vswing_sequence(dev_priv, level, port,
1671 INTEL_OUTPUT_HDMI);
30cf6db8
DV		 1672
1673 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1674 crtc->config->has_hdmi_sink,
1675 &crtc->config->base.adjusted_mode);
c19b0669 1676 }
6441ab5f
PZ		 1677}
1678
00c09d70 1679static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1680{
1681 struct drm_encoder *encoder = &intel_encoder->base;
efa80add 1682 struct drm_device *dev = encoder->dev;
fac5e23e 1683 struct drm_i915_private *dev_priv = to_i915(dev);
6441ab5f 1684 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1685 int type = intel_encoder->type;
2886e93f 1686 uint32_t val;
a836bdf9 1687 bool wait = false;
2886e93f
PZ		 1688
1689 val = I915_READ(DDI_BUF_CTL(port));
1690 if (val & DDI_BUF_CTL_ENABLE) {
1691 val &= ~DDI_BUF_CTL_ENABLE;
1692 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1693 wait = true;
2886e93f 1694 }
6441ab5f 1695
a836bdf9
PZ		 1696 val = I915_READ(DP_TP_CTL(port));
1697 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1698 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1699 I915_WRITE(DP_TP_CTL(port), val);
1700
1701 if (wait)
1702 intel_wait_ddi_buf_idle(dev_priv, port);
1703
cca0502b 1704 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1705 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1706 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1707 intel_edp_panel_vdd_on(intel_dp);
4be73780 1708 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1709 }
1710
ef11bdb3 1711 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 1712 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1713 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1714 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1715 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 1716
1717 if (type == INTEL_OUTPUT_HDMI) {
1718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1719
1720 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1721 }
6441ab5f
PZ		 1722}
1723
00c09d70 1724static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1725{
6547fef8 1726 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1727 struct drm_crtc *crtc = encoder->crtc;
1728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1729 struct drm_device *dev = encoder->dev;
fac5e23e 1730 struct drm_i915_private *dev_priv = to_i915(dev);
6547fef8
PZ		 1731 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1732 int type = intel_encoder->type;
72662e10 1733
6547fef8 1734 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1735 struct intel_digital_port *intel_dig_port =
1736 enc_to_dig_port(encoder);
1737
6547fef8
PZ		 1738 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1739 * are ignored so nothing special needs to be done besides
1740 * enabling the port.
1741 */
876a8cdf 1742 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1743 intel_dig_port->saved_port_bits |
1744 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1745 } else if (type == INTEL_OUTPUT_EDP) {
1746 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1747
23f08d83 1748 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1749 intel_dp_stop_link_train(intel_dp);
1750
4be73780 1751 intel_edp_backlight_on(intel_dp);
0bc12bcb 1752 intel_psr_enable(intel_dp);
c395578e 1753 intel_edp_drrs_enable(intel_dp);
6547fef8 1754 }
7b9f35a6 1755
6e3c9717 1756 if (intel_crtc->config->has_audio) {
d45a0bf5 1757 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1758 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1759 }
5ab432ef
DV		 1760}
1761
00c09d70 1762static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1763{
d6c50ff8 1764 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1765 struct drm_crtc *crtc = encoder->crtc;
1766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1767 int type = intel_encoder->type;
7b9f35a6 1768 struct drm_device *dev = encoder->dev;
fac5e23e 1769 struct drm_i915_private *dev_priv = to_i915(dev);
d6c50ff8 1770
6e3c9717 1771 if (intel_crtc->config->has_audio) {
69bfe1a9 1772 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1773 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1774 }
2831d842 1775
d6c50ff8
PZ		 1776 if (type == INTEL_OUTPUT_EDP) {
1777 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1778
c395578e 1779 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1780 intel_psr_disable(intel_dp);
4be73780 1781 intel_edp_backlight_off(intel_dp);
d6c50ff8 1782 }
72662e10 1783}
79f689aa 1784
9c8d0b8e
ID		 1785bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1786 enum dpio_phy phy)
bd480061 1787{
e93da0a0
ID		 1788 enum port port;
1789
bd480061
ID		 1790 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1791 return false;
1792
1793 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1794 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1795 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1796 phy);
1797
1798 return false;
1799 }
1800
1801 if (phy == DPIO_PHY1 &&
1802 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1803 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1804
1805 return false;
1806 }
1807
1808 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1809 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1810 phy);
1811
1812 return false;
1813 }
1814
e93da0a0
ID		 1815 for_each_port_masked(port,
1816 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1817 BIT(PORT_A)) {
1818 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1819
1820 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1821 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1822 "for port %c powered down "
1823 "(PHY_CTL %08x)\n",
1824 phy, port_name(port), tmp);
1825
1826 return false;
1827 }
1828 }
1829
bd480061
ID		 1830 return true;
1831}
1832
324513c0 1833static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
adc7f04b
ID		 1834{
1835 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1836
1837 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1838}
1839
324513c0
ID		 1840static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1841 enum dpio_phy phy)
01a01ef2 1842{
058fee93
CW		 1843 if (intel_wait_for_register(dev_priv,
1844 BXT_PORT_REF_DW3(phy),
1845 GRC_DONE, GRC_DONE,
1846 10))
01a01ef2
ID		 1847 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1848}
1849
9c8d0b8e 1850void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
5c6706e5 1851{
95a7a2ae 1852 u32 val;
5c6706e5 1853
9c8d0b8e 1854 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
adc7f04b 1855 /* Still read out the GRC value for state verification */
67856d4d 1856 if (phy == DPIO_PHY0)
324513c0 1857 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
bd480061 1858
9c8d0b8e 1859 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
47baf2a5
ID		 1860 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1861 "won't reprogram it\n", phy);
1862
1863 return;
1864 }
bd480061 1865
47baf2a5
ID		 1866 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1867 "force reprogramming it\n", phy);
47baf2a5 1868 }
bd480061 1869
5c6706e5
VK		 1870 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1871 val |= GT_DISPLAY_POWER_ON(phy);
1872 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1873
b61e7996
VK		 1874 /*
1875 * The PHY registers start out inaccessible and respond to reads with
1876 * all 1s. Eventually they become accessible as they power up, then
1877 * the reserved bit will give the default 0. Poll on the reserved bit
1878 * becoming 0 to find when the PHY is accessible.
1879 * HW team confirmed that the time to reach phypowergood status is
1880 * anywhere between 50 us and 100us.
1881 */
1882 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1883 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
5c6706e5 1884 DRM_ERROR("timeout during PHY%d power on\n", phy);
b61e7996 1885 }
5c6706e5 1886
5c6706e5
VK		 1887 /* Program PLL Rcomp code offset */
1888 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1889 val &= ~IREF0RC_OFFSET_MASK;
1890 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1891 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1892
1893 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1894 val &= ~IREF1RC_OFFSET_MASK;
1895 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1896 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1897
1898 /* Program power gating */
1899 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1900 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1901 SUS_CLK_CONFIG;
1902 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1903
1904 if (phy == DPIO_PHY0) {
1905 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1906 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1907 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1908 }
1909
1910 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1911 val &= ~OCL2_LDOFUSE_PWR_DIS;
1912 /*
1913 * On PHY1 disable power on the second channel, since no port is
1914 * connected there. On PHY0 both channels have a port, so leave it
1915 * enabled.
1916 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1917 * power down the second channel on PHY0 as well.
28ca6931
ID		 1918 *
1919 * FIXME: Clarify programming of the following, the register is
1920 * read-only with bit 6 fixed at 0 at least in stepping A.
5c6706e5
VK		 1921 */
1922 if (phy == DPIO_PHY1)
1923 val |= OCL2_LDOFUSE_PWR_DIS;
1924 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1925
1926 if (phy == DPIO_PHY0) {
1927 uint32_t grc_code;
1928 /*
1929 * PHY0 isn't connected to an RCOMP resistor so copy over
1930 * the corresponding calibrated value from PHY1, and disable
1931 * the automatic calibration on PHY0.
1932 */
324513c0 1933 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
5c6706e5
VK		 1934 grc_code = val << GRC_CODE_FAST_SHIFT |
1935 val << GRC_CODE_SLOW_SHIFT |
1936 val;
1937 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1938
1939 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1940 val |= GRC_DIS | GRC_RDY_OVRD;
1941 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1942 }
1943
1944 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1945 val |= COMMON_RESET_DIS;
1946 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
e4c49e0f
ID		 1947
1948 if (phy == DPIO_PHY1)
324513c0 1949 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
5c6706e5
VK		 1950}
1951
9c8d0b8e 1952void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
5c6706e5
VK		 1953{
1954 uint32_t val;
1955
1956 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1957 val &= ~COMMON_RESET_DIS;
1958 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
d7d33fd8
ID		 1959
1960 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1961 val &= ~GT_DISPLAY_POWER_ON(phy);
1962 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
5c6706e5
VK		 1963}
1964
adc7f04b
ID		 1965static bool __printf(6, 7)
1966__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1967 i915_reg_t reg, u32 mask, u32 expected,
1968 const char *reg_fmt, ...)
1969{
1970 struct va_format vaf;
1971 va_list args;
1972 u32 val;
1973
1974 val = I915_READ(reg);
1975 if ((val & mask) == expected)
1976 return true;
1977
1978 va_start(args, reg_fmt);
1979 vaf.fmt = reg_fmt;
1980 vaf.va = &args;
1981
1982 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1983 "current %08x, expected %08x (mask %08x)\n",
1984 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1985 mask);
1986
1987 va_end(args);
1988
1989 return false;
1990}
1991
9c8d0b8e
ID		 1992bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1993 enum dpio_phy phy)
adc7f04b 1994{
adc7f04b
ID		 1995 uint32_t mask;
1996 bool ok;
1997
1998#define _CHK(reg, mask, exp, fmt, ...) \
1999 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
2000 ## __VA_ARGS__)
2001
9c8d0b8e 2002 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
adc7f04b
ID		 2003 return false;
2004
2005 ok = true;
2006
adc7f04b
ID		 2007 /* PLL Rcomp code offset */
2008 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2009 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2010 "BXT_PORT_CL1CM_DW9(%d)", phy);
2011 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2012 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2013 "BXT_PORT_CL1CM_DW10(%d)", phy);
2014
2015 /* Power gating */
2016 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2017 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2018 "BXT_PORT_CL1CM_DW28(%d)", phy);
2019
2020 if (phy == DPIO_PHY0)
2021 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2022 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2023 "BXT_PORT_CL2CM_DW6_BC");
2024
2025 /*
2026 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2027 * at least on stepping A this bit is read-only and fixed at 0.
2028 */
2029
2030 if (phy == DPIO_PHY0) {
2031 u32 grc_code = dev_priv->bxt_phy_grc;
2032
2033 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2034 grc_code << GRC_CODE_SLOW_SHIFT |
2035 grc_code;
2036 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2037 GRC_CODE_NOM_MASK;
2038 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2039 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2040
2041 mask = GRC_DIS | GRC_RDY_OVRD;
2042 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2043 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2044 }
2045
2046 return ok;
2047#undef _CHK
2048}
2049
95a7a2ae
ID		 2050static uint8_t
2051bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2052 struct intel_crtc_state *pipe_config)
2053{
2054 switch (pipe_config->lane_count) {
2055 case 1:
2056 return 0;
2057 case 2:
2058 return BIT(2) | BIT(0);
2059 case 4:
2060 return BIT(3) | BIT(2) | BIT(0);
2061 default:
2062 MISSING_CASE(pipe_config->lane_count);
2063
2064 return 0;
2065 }
2066}
2067
2068static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2069{
2070 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2071 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2072 enum port port = dport->port;
2073 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2074 int lane;
2075
2076 for (lane = 0; lane < 4; lane++) {
2077 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2078
2079 /*
2080 * Note that on CHV this flag is called UPAR, but has
2081 * the same function.
2082 */
2083 val &= ~LATENCY_OPTIM;
2084 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2085 val |= LATENCY_OPTIM;
2086
2087 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2088 }
2089}
2090
2091static uint8_t
2092bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2093{
2094 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2095 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2096 enum port port = dport->port;
2097 int lane;
2098 uint8_t mask;
2099
2100 mask = 0;
2101 for (lane = 0; lane < 4; lane++) {
2102 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2103
2104 if (val & LATENCY_OPTIM)
2105 mask |= BIT(lane);
2106 }
2107
2108 return mask;
2109}
2110
ad64217b 2111void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2112{
ad64217b
ACO		 2113 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2114 struct drm_i915_private *dev_priv =
2115 to_i915(intel_dig_port->base.base.dev);
174edf1f 2116 enum port port = intel_dig_port->port;
c19b0669 2117 uint32_t val;
f3e227df 2118 bool wait = false;
c19b0669
PZ		 2119
2120 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2121 val = I915_READ(DDI_BUF_CTL(port));
2122 if (val & DDI_BUF_CTL_ENABLE) {
2123 val &= ~DDI_BUF_CTL_ENABLE;
2124 I915_WRITE(DDI_BUF_CTL(port), val);
2125 wait = true;
2126 }
2127
2128 val = I915_READ(DP_TP_CTL(port));
2129 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2130 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2131 I915_WRITE(DP_TP_CTL(port), val);
2132 POSTING_READ(DP_TP_CTL(port));
2133
2134 if (wait)
2135 intel_wait_ddi_buf_idle(dev_priv, port);
2136 }
2137
0e32b39c 2138 val = DP_TP_CTL_ENABLE |
c19b0669 2139 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2140 if (intel_dp->is_mst)
2141 val |= DP_TP_CTL_MODE_MST;
2142 else {
2143 val |= DP_TP_CTL_MODE_SST;
2144 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2145 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2146 }
c19b0669
PZ		 2147 I915_WRITE(DP_TP_CTL(port), val);
2148 POSTING_READ(DP_TP_CTL(port));
2149
2150 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2151 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2152 POSTING_READ(DDI_BUF_CTL(port));
2153
2154 udelay(600);
2155}
00c09d70 2156
1ad960f2
PZ		 2157void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2158{
fac5e23e 2159 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1ad960f2
PZ		 2160 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2161 uint32_t val;
2162
5b421c57
VS		 2163 /*
2164 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2165 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2166 * step 13 is the correct place for it. Step 18 is where it was
2167 * originally before the BUN.
2168 */
eede3b53 2169 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2170 val &= ~FDI_RX_ENABLE;
eede3b53 2171 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2172
5b421c57
VS		 2173 intel_ddi_post_disable(intel_encoder);
2174
eede3b53 2175 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 2176 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2177 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 2178 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 2179
eede3b53 2180 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2181 val &= ~FDI_PCDCLK;
eede3b53 2182 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2183
eede3b53 2184 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2185 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 2186 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 2187}
2188
6801c18c 2189void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2190 struct intel_crtc_state *pipe_config)
045ac3b5 2191{
fac5e23e 2192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2193 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2194 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2195 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2196 u32 temp, flags = 0;
2197
4d1de975
JN		 2198 /* XXX: DSI transcoder paranoia */
2199 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2200 return;
2201
045ac3b5
JB		 2202 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2203 if (temp & TRANS_DDI_PHSYNC)
2204 flags |= DRM_MODE_FLAG_PHSYNC;
2205 else
2206 flags |= DRM_MODE_FLAG_NHSYNC;
2207 if (temp & TRANS_DDI_PVSYNC)
2208 flags |= DRM_MODE_FLAG_PVSYNC;
2209 else
2210 flags |= DRM_MODE_FLAG_NVSYNC;
2211
2d112de7 2212 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2213
2214 switch (temp & TRANS_DDI_BPC_MASK) {
2215 case TRANS_DDI_BPC_6:
2216 pipe_config->pipe_bpp = 18;
2217 break;
2218 case TRANS_DDI_BPC_8:
2219 pipe_config->pipe_bpp = 24;
2220 break;
2221 case TRANS_DDI_BPC_10:
2222 pipe_config->pipe_bpp = 30;
2223 break;
2224 case TRANS_DDI_BPC_12:
2225 pipe_config->pipe_bpp = 36;
2226 break;
2227 default:
2228 break;
2229 }
eb14cb74
VS		 2230
2231 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2232 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2233 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2234 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2235
cda0aaaf 2236 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2237 pipe_config->has_infoframe = true;
d4d6279a 2238 /* fall through */
eb14cb74 2239 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2240 pipe_config->lane_count = 4;
2241 break;
eb14cb74
VS		 2242 case TRANS_DDI_MODE_SELECT_FDI:
2243 break;
2244 case TRANS_DDI_MODE_SELECT_DP_SST:
2245 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2246 pipe_config->lane_count =
2247 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2248 intel_dp_get_m_n(intel_crtc, pipe_config);
2249 break;
2250 default:
2251 break;
2252 }
10214420 2253
5a8f97ea
L		 2254 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2255 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2256 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2257 pipe_config->has_audio = true;
2258 }
9ed109a7 2259
6aa23e65
JN		 2260 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2261 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2262 /*
2263 * This is a big fat ugly hack.
2264 *
2265 * Some machines in UEFI boot mode provide us a VBT that has 18
2266 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2267 * unknown we fail to light up. Yet the same BIOS boots up with
2268 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2269 * max, not what it tells us to use.
2270 *
2271 * Note: This will still be broken if the eDP panel is not lit
2272 * up by the BIOS, and thus we can't get the mode at module
2273 * load.
2274 */
2275 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2276 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2277 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2278 }
11578553 2279
22606a18 2280 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae
ID		 2281
2282 if (IS_BROXTON(dev_priv))
2283 pipe_config->lane_lat_optim_mask =
2284 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2285}
2286
5bfe2ac0 2287static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2288 struct intel_crtc_state *pipe_config)
00c09d70 2289{
fac5e23e 2290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2291 int type = encoder->type;
eccb140b 2292 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2293 int ret;
00c09d70 2294
5bfe2ac0 2295 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2296
eccb140b
DV		 2297 if (port == PORT_A)
2298 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2299
00c09d70 2300 if (type == INTEL_OUTPUT_HDMI)
95a7a2ae 2301 ret = intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2302 else
95a7a2ae
ID		 2303 ret = intel_dp_compute_config(encoder, pipe_config);
2304
2305 if (IS_BROXTON(dev_priv) && ret)
2306 pipe_config->lane_lat_optim_mask =
2307 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2308 pipe_config);
2309
2310 return ret;
2311
00c09d70
PZ		 2312}
2313
2314static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2315 .reset = intel_dp_encoder_reset,
2316 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2317};
2318
4a28ae58
PZ		 2319static struct intel_connector *
2320intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2321{
2322 struct intel_connector *connector;
2323 enum port port = intel_dig_port->port;
2324
9bdbd0b9 2325 connector = intel_connector_alloc();
4a28ae58
PZ		 2326 if (!connector)
2327 return NULL;
2328
2329 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2330 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2331 kfree(connector);
2332 return NULL;
2333 }
2334
2335 return connector;
2336}
2337
2338static struct intel_connector *
2339intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2340{
2341 struct intel_connector *connector;
2342 enum port port = intel_dig_port->port;
2343
9bdbd0b9 2344 connector = intel_connector_alloc();
4a28ae58
PZ		 2345 if (!connector)
2346 return NULL;
2347
2348 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2349 intel_hdmi_init_connector(intel_dig_port, connector);
2350
2351 return connector;
2352}
2353
00c09d70
PZ		 2354void intel_ddi_init(struct drm_device *dev, enum port port)
2355{
fac5e23e 2356 struct drm_i915_private *dev_priv = to_i915(dev);
00c09d70
PZ		 2357 struct intel_digital_port *intel_dig_port;
2358 struct intel_encoder *intel_encoder;
2359 struct drm_encoder *encoder;
311a2094 2360 bool init_hdmi, init_dp;
10e7bec3
VS		 2361 int max_lanes;
2362
2363 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2364 switch (port) {
2365 case PORT_A:
2366 max_lanes = 4;
2367 break;
2368 case PORT_E:
2369 max_lanes = 0;
2370 break;
2371 default:
2372 max_lanes = 4;
2373 break;
2374 }
2375 } else {
2376 switch (port) {
2377 case PORT_A:
2378 max_lanes = 2;
2379 break;
2380 case PORT_E:
2381 max_lanes = 2;
2382 break;
2383 default:
2384 max_lanes = 4;
2385 break;
2386 }
2387 }
311a2094
PZ		 2388
2389 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2390 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2391 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2392 if (!init_dp && !init_hdmi) {
500ea70d 2393 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2394 port_name(port));
500ea70d 2395 return;
311a2094 2396 }
00c09d70 2397
b14c5679 2398 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2399 if (!intel_dig_port)
2400 return;
2401
00c09d70
PZ		 2402 intel_encoder = &intel_dig_port->base;
2403 encoder = &intel_encoder->base;
2404
2405 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
580d8ed5 2406 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2407
5bfe2ac0 2408 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2409 intel_encoder->enable = intel_enable_ddi;
95a7a2ae
ID		 2410 if (IS_BROXTON(dev_priv))
2411 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2412 intel_encoder->pre_enable = intel_ddi_pre_enable;
2413 intel_encoder->disable = intel_disable_ddi;
2414 intel_encoder->post_disable = intel_ddi_post_disable;
2415 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2416 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2417 intel_encoder->suspend = intel_dp_encoder_suspend;
00c09d70
PZ		 2418
2419 intel_dig_port->port = port;
bcf53de4
SM		 2420 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2421 (DDI_BUF_PORT_REVERSAL |
2422 DDI_A_4_LANES);
00c09d70 2423
6c566dc9
MR		 2424 /*
2425 * Bspec says that DDI_A_4_LANES is the only supported configuration
2426 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2427 * wasn't lit up at boot. Force this bit on in our internal
2428 * configuration so that we use the proper lane count for our
2429 * calculations.
2430 */
2431 if (IS_BROXTON(dev) && port == PORT_A) {
2432 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2433 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2434 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2435 max_lanes = 4;
6c566dc9
MR		 2436 }
2437 }
2438
ed8d60f4
MR		 2439 intel_dig_port->max_lanes = max_lanes;
2440
00c09d70 2441 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2442 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2443 intel_encoder->cloneable = 0;
00c09d70 2444
f68d697e
CW		 2445 if (init_dp) {
2446 if (!intel_ddi_init_dp_connector(intel_dig_port))
2447 goto err;
13cf5504 2448
f68d697e 2449 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 2450 /*
2451 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2452 * interrupts to check the external panel connection.
2453 */
e87a005d 2454 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 2455 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2456 else
2457 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2458 }
21a8e6a4 2459
311a2094
PZ		 2460 /* In theory we don't need the encoder->type check, but leave it just in
2461 * case we have some really bad VBTs... */
f68d697e
CW		 2462 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2463 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2464 goto err;
21a8e6a4 2465 }
f68d697e
CW		 2466
2467 return;
2468
2469err:
2470 drm_encoder_cleanup(encoder);
2471 kfree(intel_dig_port);
00c09d70 2472}
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