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drm/i915: factor out ddi_get_encoder_port
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
b403745c
DL		 259static void intel_prepare_ddi_buffers(struct drm_device *dev,
260 struct intel_digital_port *intel_dig_port)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
b403745c 264 int port = intel_dig_port->port;
7ff44670 265 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 266 size;
6acab15a 267 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 268 const struct ddi_buf_trans *ddi_translations_fdi;
269 const struct ddi_buf_trans *ddi_translations_dp;
270 const struct ddi_buf_trans *ddi_translations_edp;
271 const struct ddi_buf_trans *ddi_translations_hdmi;
272 const struct ddi_buf_trans *ddi_translations;
e58623cb 273
96fb9f9b
VK		 274 if (IS_BROXTON(dev)) {
275 if (!intel_dig_port_supports_hdmi(intel_dig_port))
276 return;
277
278 /* Vswing programming for HDMI */
279 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
280 INTEL_OUTPUT_HDMI);
281 return;
282 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 283 ddi_translations_fdi = NULL;
284 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29
SJ		 285 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
286 if (dev_priv->vbt.edp_low_vswing) {
287 ddi_translations_edp = skl_ddi_translations_edp;
288 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
289 } else {
290 ddi_translations_edp = skl_ddi_translations_dp;
291 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
292 }
293
7f88e3af
DL		 294 ddi_translations_hdmi = skl_ddi_translations_hdmi;
295 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 296 hdmi_default_entry = 7;
7f88e3af 297 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 298 ddi_translations_fdi = bdw_ddi_translations_fdi;
299 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 300 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 301 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 302 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
303 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 304 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 305 hdmi_default_entry = 7;
e58623cb
AR		 306 } else if (IS_HASWELL(dev)) {
307 ddi_translations_fdi = hsw_ddi_translations_fdi;
308 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 309 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 310 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 311 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 312 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 313 hdmi_default_entry = 6;
e58623cb
AR		 314 } else {
315 WARN(1, "ddi translation table missing\n");
300644c7 316 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 317 ddi_translations_fdi = bdw_ddi_translations_fdi;
318 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 319 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 320 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
321 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 322 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 323 hdmi_default_entry = 7;
e58623cb
AR		 324 }
325
300644c7
PZ		 326 switch (port) {
327 case PORT_A:
328 ddi_translations = ddi_translations_edp;
7ad14a29 329 size = n_edp_entries;
300644c7
PZ		 330 break;
331 case PORT_B:
332 case PORT_C:
300644c7 333 ddi_translations = ddi_translations_dp;
7ad14a29 334 size = n_dp_entries;
300644c7 335 break;
77d8d009 336 case PORT_D:
7ad14a29 337 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 338 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 339 size = n_edp_entries;
340 } else {
77d8d009 341 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 342 size = n_dp_entries;
343 }
77d8d009 344 break;
300644c7 345 case PORT_E:
7f88e3af
DL		 346 if (ddi_translations_fdi)
347 ddi_translations = ddi_translations_fdi;
348 else
349 ddi_translations = ddi_translations_dp;
7ad14a29 350 size = n_dp_entries;
300644c7
PZ		 351 break;
352 default:
353 BUG();
354 }
45244b87 355
7ad14a29 356 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 357 I915_WRITE(reg, ddi_translations[i].trans1);
358 reg += 4;
359 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 360 reg += 4;
361 }
ce4dd49e 362
ce3b7e9b
DL		 363 if (!intel_dig_port_supports_hdmi(intel_dig_port))
364 return;
365
ce4dd49e
DL		 366 /* Choose a good default if VBT is badly populated */
367 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
368 hdmi_level >= n_hdmi_entries)
7ff44670 369 hdmi_level = hdmi_default_entry;
ce4dd49e 370
6acab15a 371 /* Entry 9 is for HDMI: */
10122051
JN		 372 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
373 reg += 4;
374 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
375 reg += 4;
45244b87
ED		 376}
377
378/* Program DDI buffers translations for DP. By default, program ports A-D in DP
379 * mode and port E for FDI.
380 */
381void intel_prepare_ddi(struct drm_device *dev)
382{
b403745c
DL		 383 struct intel_digital_port *intel_dig_port;
384 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 385
0d536cb4
PZ		 386 if (!HAS_DDI(dev))
387 return;
45244b87 388
b403745c
DL		 389 for_each_digital_port(dev, intel_dig_port) {
390 if (visited[intel_dig_port->port])
391 continue;
392
393 intel_prepare_ddi_buffers(dev, intel_dig_port);
394 visited[intel_dig_port->port] = true;
395 }
45244b87 396}
c82e4d26 397
248138b5
PZ		 398static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
399 enum port port)
400{
401 uint32_t reg = DDI_BUF_CTL(port);
402 int i;
403
3449ca85 404 for (i = 0; i < 16; i++) {
248138b5
PZ		 405 udelay(1);
406 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
407 return;
408 }
409 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
410}
c82e4d26
ED		 411
412/* Starting with Haswell, different DDI ports can work in FDI mode for
413 * connection to the PCH-located connectors. For this, it is necessary to train
414 * both the DDI port and PCH receiver for the desired DDI buffer settings.
415 *
416 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
417 * please note that when FDI mode is active on DDI E, it shares 2 lines with
418 * DDI A (which is used for eDP)
419 */
420
421void hsw_fdi_link_train(struct drm_crtc *crtc)
422{
423 struct drm_device *dev = crtc->dev;
424 struct drm_i915_private *dev_priv = dev->dev_private;
425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 426 u32 temp, i, rx_ctl_val;
c82e4d26 427
04945641
PZ		 428 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
429 * mode set "sequence for CRT port" document:
430 * - TP1 to TP2 time with the default value
431 * - FDI delay to 90h
8693a824
DL		 432 *
433 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 434 */
435 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
436 FDI_RX_PWRDN_LANE0_VAL(2) |
437 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
438
439 /* Enable the PCH Receiver FDI PLL */
3e68320e 440 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 441 FDI_RX_PLL_ENABLE |
6e3c9717 442 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 443 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
444 POSTING_READ(_FDI_RXA_CTL);
445 udelay(220);
446
447 /* Switch from Rawclk to PCDclk */
448 rx_ctl_val |= FDI_PCDCLK;
449 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
450
451 /* Configure Port Clock Select */
6e3c9717
ACO		 452 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
453 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 454
455 /* Start the training iterating through available voltages and emphasis,
456 * testing each value twice. */
10122051 457 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 458 /* Configure DP_TP_CTL with auto-training */
459 I915_WRITE(DP_TP_CTL(PORT_E),
460 DP_TP_CTL_FDI_AUTOTRAIN |
461 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
462 DP_TP_CTL_LINK_TRAIN_PAT1 |
463 DP_TP_CTL_ENABLE);
464
876a8cdf
DL		 465 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
466 * DDI E does not support port reversal, the functionality is
467 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
468 * port reversal bit */
c82e4d26 469 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 470 DDI_BUF_CTL_ENABLE |
6e3c9717 471 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 472 DDI_BUF_TRANS_SELECT(i / 2));
04945641 473 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 474
475 udelay(600);
476
04945641
PZ		 477 /* Program PCH FDI Receiver TU */
478 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
479
480 /* Enable PCH FDI Receiver with auto-training */
481 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
482 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
483 POSTING_READ(_FDI_RXA_CTL);
484
485 /* Wait for FDI receiver lane calibration */
486 udelay(30);
487
488 /* Unset FDI_RX_MISC pwrdn lanes */
489 temp = I915_READ(_FDI_RXA_MISC);
490 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
491 I915_WRITE(_FDI_RXA_MISC, temp);
492 POSTING_READ(_FDI_RXA_MISC);
493
494 /* Wait for FDI auto training time */
495 udelay(5);
c82e4d26
ED		 496
497 temp = I915_READ(DP_TP_STATUS(PORT_E));
498 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 499 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 500
501 /* Enable normal pixel sending for FDI */
502 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 503 DP_TP_CTL_FDI_AUTOTRAIN |
504 DP_TP_CTL_LINK_TRAIN_NORMAL |
505 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
506 DP_TP_CTL_ENABLE);
c82e4d26 507
04945641 508 return;
c82e4d26 509 }
04945641 510
248138b5
PZ		 511 temp = I915_READ(DDI_BUF_CTL(PORT_E));
512 temp &= ~DDI_BUF_CTL_ENABLE;
513 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
514 POSTING_READ(DDI_BUF_CTL(PORT_E));
515
04945641 516 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 517 temp = I915_READ(DP_TP_CTL(PORT_E));
518 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
519 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
520 I915_WRITE(DP_TP_CTL(PORT_E), temp);
521 POSTING_READ(DP_TP_CTL(PORT_E));
522
523 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 524
525 rx_ctl_val &= ~FDI_RX_ENABLE;
526 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 527 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 528
529 /* Reset FDI_RX_MISC pwrdn lanes */
530 temp = I915_READ(_FDI_RXA_MISC);
531 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
532 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
533 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 534 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 535 }
536
04945641 537 DRM_ERROR("FDI link training failed!\n");
c82e4d26 538}
0e72a5b5 539
44905a27
DA		 540void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
541{
542 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
543 struct intel_digital_port *intel_dig_port =
544 enc_to_dig_port(&encoder->base);
545
546 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 547 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 548 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
549
550}
551
8d9ddbcb
PZ		 552static struct intel_encoder *
553intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
554{
555 struct drm_device *dev = crtc->dev;
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
557 struct intel_encoder *intel_encoder, *ret = NULL;
558 int num_encoders = 0;
559
560 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
561 ret = intel_encoder;
562 num_encoders++;
563 }
564
565 if (num_encoders != 1)
84f44ce7
VS		 566 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
567 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 568
569 BUG_ON(ret == NULL);
570 return ret;
571}
572
bcddf610 573struct intel_encoder *
3165c074 574intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 575{
3165c074
ACO		 576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
577 struct intel_encoder *ret = NULL;
578 struct drm_atomic_state *state;
d0737e1d 579 int num_encoders = 0;
3165c074 580 int i;
d0737e1d 581
3165c074
ACO		 582 state = crtc_state->base.state;
583
584 for (i = 0; i < state->num_connector; i++) {
585 if (!state->connectors[i] ||
586 state->connector_states[i]->crtc != crtc_state->base.crtc)
587 continue;
588
589 ret = to_intel_encoder(state->connector_states[i]->best_encoder);
590 num_encoders++;
d0737e1d
ACO		 591 }
592
593 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
594 pipe_name(crtc->pipe));
595
596 BUG_ON(ret == NULL);
597 return ret;
598}
599
1c0b85c5 600#define LC_FREQ 2700
27893390 601#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 602
603#define P_MIN 2
604#define P_MAX 64
605#define P_INC 2
606
607/* Constraints for PLL good behavior */
608#define REF_MIN 48
609#define REF_MAX 400
610#define VCO_MIN 2400
611#define VCO_MAX 4800
612
27893390
DL		 613#define abs_diff(a, b) ({ \
614 typeof(a) __a = (a); \
615 typeof(b) __b = (b); \
616 (void) (&__a == &__b); \
617 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 618
619struct wrpll_rnp {
620 unsigned p, n2, r2;
621};
622
623static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 624{
1c0b85c5
DL		 625 unsigned budget;
626
627 switch (clock) {
628 case 25175000:
629 case 25200000:
630 case 27000000:
631 case 27027000:
632 case 37762500:
633 case 37800000:
634 case 40500000:
635 case 40541000:
636 case 54000000:
637 case 54054000:
638 case 59341000:
639 case 59400000:
640 case 72000000:
641 case 74176000:
642 case 74250000:
643 case 81000000:
644 case 81081000:
645 case 89012000:
646 case 89100000:
647 case 108000000:
648 case 108108000:
649 case 111264000:
650 case 111375000:
651 case 148352000:
652 case 148500000:
653 case 162000000:
654 case 162162000:
655 case 222525000:
656 case 222750000:
657 case 296703000:
658 case 297000000:
659 budget = 0;
660 break;
661 case 233500000:
662 case 245250000:
663 case 247750000:
664 case 253250000:
665 case 298000000:
666 budget = 1500;
667 break;
668 case 169128000:
669 case 169500000:
670 case 179500000:
671 case 202000000:
672 budget = 2000;
673 break;
674 case 256250000:
675 case 262500000:
676 case 270000000:
677 case 272500000:
678 case 273750000:
679 case 280750000:
680 case 281250000:
681 case 286000000:
682 case 291750000:
683 budget = 4000;
684 break;
685 case 267250000:
686 case 268500000:
687 budget = 5000;
688 break;
689 default:
690 budget = 1000;
691 break;
692 }
6441ab5f 693
1c0b85c5
DL		 694 return budget;
695}
696
697static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
698 unsigned r2, unsigned n2, unsigned p,
699 struct wrpll_rnp *best)
700{
701 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 702
1c0b85c5
DL		 703 /* No best (r,n,p) yet */
704 if (best->p == 0) {
705 best->p = p;
706 best->n2 = n2;
707 best->r2 = r2;
708 return;
709 }
6441ab5f 710
1c0b85c5
DL		 711 /*
712 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
713 * freq2k.
714 *
715 * delta = 1e6 *
716 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
717 * freq2k;
718 *
719 * and we would like delta <= budget.
720 *
721 * If the discrepancy is above the PPM-based budget, always prefer to
722 * improve upon the previous solution. However, if you're within the
723 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
724 */
725 a = freq2k * budget * p * r2;
726 b = freq2k * budget * best->p * best->r2;
27893390
DL		 727 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
728 diff_best = abs_diff(freq2k * best->p * best->r2,
729 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 730 c = 1000000 * diff;
731 d = 1000000 * diff_best;
732
733 if (a < c && b < d) {
734 /* If both are above the budget, pick the closer */
735 if (best->p * best->r2 * diff < p * r2 * diff_best) {
736 best->p = p;
737 best->n2 = n2;
738 best->r2 = r2;
739 }
740 } else if (a >= c && b < d) {
741 /* If A is below the threshold but B is above it? Update. */
742 best->p = p;
743 best->n2 = n2;
744 best->r2 = r2;
745 } else if (a >= c && b >= d) {
746 /* Both are below the limit, so pick the higher n2/(r2*r2) */
747 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
748 best->p = p;
749 best->n2 = n2;
750 best->r2 = r2;
751 }
752 }
753 /* Otherwise a < c && b >= d, do nothing */
754}
755
11578553
JB		 756static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
757 int reg)
758{
759 int refclk = LC_FREQ;
760 int n, p, r;
761 u32 wrpll;
762
763 wrpll = I915_READ(reg);
114fe488
DV		 764 switch (wrpll & WRPLL_PLL_REF_MASK) {
765 case WRPLL_PLL_SSC:
766 case WRPLL_PLL_NON_SSC:
11578553
JB		 767 /*
768 * We could calculate spread here, but our checking
769 * code only cares about 5% accuracy, and spread is a max of
770 * 0.5% downspread.
771 */
772 refclk = 135;
773 break;
114fe488 774 case WRPLL_PLL_LCPLL:
11578553
JB		 775 refclk = LC_FREQ;
776 break;
777 default:
778 WARN(1, "bad wrpll refclk\n");
779 return 0;
780 }
781
782 r = wrpll & WRPLL_DIVIDER_REF_MASK;
783 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
784 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
785
20f0ec16
JB		 786 /* Convert to KHz, p & r have a fixed point portion */
787 return (refclk * n * 100) / (p * r);
11578553
JB		 788}
789
540e732c
S		 790static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
791 uint32_t dpll)
792{
793 uint32_t cfgcr1_reg, cfgcr2_reg;
794 uint32_t cfgcr1_val, cfgcr2_val;
795 uint32_t p0, p1, p2, dco_freq;
796
797 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
798 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
799
800 cfgcr1_val = I915_READ(cfgcr1_reg);
801 cfgcr2_val = I915_READ(cfgcr2_reg);
802
803 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
804 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
805
806 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
807 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
808 else
809 p1 = 1;
810
811
812 switch (p0) {
813 case DPLL_CFGCR2_PDIV_1:
814 p0 = 1;
815 break;
816 case DPLL_CFGCR2_PDIV_2:
817 p0 = 2;
818 break;
819 case DPLL_CFGCR2_PDIV_3:
820 p0 = 3;
821 break;
822 case DPLL_CFGCR2_PDIV_7:
823 p0 = 7;
824 break;
825 }
826
827 switch (p2) {
828 case DPLL_CFGCR2_KDIV_5:
829 p2 = 5;
830 break;
831 case DPLL_CFGCR2_KDIV_2:
832 p2 = 2;
833 break;
834 case DPLL_CFGCR2_KDIV_3:
835 p2 = 3;
836 break;
837 case DPLL_CFGCR2_KDIV_1:
838 p2 = 1;
839 break;
840 }
841
842 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
843
844 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
845 1000) / 0x8000;
846
847 return dco_freq / (p0 * p1 * p2 * 5);
848}
849
850
851static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 852 struct intel_crtc_state *pipe_config)
540e732c
S		 853{
854 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 855 int link_clock = 0;
856 uint32_t dpll_ctl1, dpll;
857
134ffa44 858 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 859
860 dpll_ctl1 = I915_READ(DPLL_CTRL1);
861
862 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
863 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
864 } else {
865 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
866 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
867
868 switch (link_clock) {
869 case DPLL_CRTL1_LINK_RATE_810:
870 link_clock = 81000;
871 break;
a8f3ef61
SJ		 872 case DPLL_CRTL1_LINK_RATE_1080:
873 link_clock = 108000;
874 break;
540e732c
S		 875 case DPLL_CRTL1_LINK_RATE_1350:
876 link_clock = 135000;
877 break;
a8f3ef61
SJ		 878 case DPLL_CRTL1_LINK_RATE_1620:
879 link_clock = 162000;
880 break;
881 case DPLL_CRTL1_LINK_RATE_2160:
882 link_clock = 216000;
883 break;
540e732c
S		 884 case DPLL_CRTL1_LINK_RATE_2700:
885 link_clock = 270000;
886 break;
887 default:
888 WARN(1, "Unsupported link rate\n");
889 break;
890 }
891 link_clock *= 2;
892 }
893
894 pipe_config->port_clock = link_clock;
895
896 if (pipe_config->has_dp_encoder)
2d112de7 897 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 898 intel_dotclock_calculate(pipe_config->port_clock,
899 &pipe_config->dp_m_n);
900 else
2d112de7 901 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 902}
903
3d51278a 904static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 905 struct intel_crtc_state *pipe_config)
11578553
JB		 906{
907 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 908 int link_clock = 0;
909 u32 val, pll;
910
26804afd 911 val = pipe_config->ddi_pll_sel;
11578553
JB		 912 switch (val & PORT_CLK_SEL_MASK) {
913 case PORT_CLK_SEL_LCPLL_810:
914 link_clock = 81000;
915 break;
916 case PORT_CLK_SEL_LCPLL_1350:
917 link_clock = 135000;
918 break;
919 case PORT_CLK_SEL_LCPLL_2700:
920 link_clock = 270000;
921 break;
922 case PORT_CLK_SEL_WRPLL1:
923 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
924 break;
925 case PORT_CLK_SEL_WRPLL2:
926 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
927 break;
928 case PORT_CLK_SEL_SPLL:
929 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
930 if (pll == SPLL_PLL_FREQ_810MHz)
931 link_clock = 81000;
932 else if (pll == SPLL_PLL_FREQ_1350MHz)
933 link_clock = 135000;
934 else if (pll == SPLL_PLL_FREQ_2700MHz)
935 link_clock = 270000;
936 else {
937 WARN(1, "bad spll freq\n");
938 return;
939 }
940 break;
941 default:
942 WARN(1, "bad port clock sel\n");
943 return;
944 }
945
946 pipe_config->port_clock = link_clock * 2;
947
948 if (pipe_config->has_pch_encoder)
2d112de7 949 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 950 intel_dotclock_calculate(pipe_config->port_clock,
951 &pipe_config->fdi_m_n);
952 else if (pipe_config->has_dp_encoder)
2d112de7 953 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 954 intel_dotclock_calculate(pipe_config->port_clock,
955 &pipe_config->dp_m_n);
956 else
2d112de7 957 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 958}
959
977bb38d
S		 960static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
961 enum intel_dpll_id dpll)
962{
963 /* FIXME formula not available in bspec */
964 return 0;
965}
966
967static void bxt_ddi_clock_get(struct intel_encoder *encoder,
968 struct intel_crtc_state *pipe_config)
969{
970 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
971 enum port port = intel_ddi_get_encoder_port(encoder);
972 uint32_t dpll = port;
973
974 pipe_config->port_clock =
975 bxt_calc_pll_link(dev_priv, dpll);
976
977 if (pipe_config->has_dp_encoder)
978 pipe_config->base.adjusted_mode.crtc_clock =
979 intel_dotclock_calculate(pipe_config->port_clock,
980 &pipe_config->dp_m_n);
981 else
982 pipe_config->base.adjusted_mode.crtc_clock =
983 pipe_config->port_clock;
984}
985
3d51278a 986void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 987 struct intel_crtc_state *pipe_config)
3d51278a 988{
22606a18
DL		 989 struct drm_device *dev = encoder->base.dev;
990
991 if (INTEL_INFO(dev)->gen <= 8)
992 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 993 else if (IS_SKYLAKE(dev))
22606a18 994 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 995 else if (IS_BROXTON(dev))
996 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 997}
998
1c0b85c5 999static void
d664c0ce
DL		 1000hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1001 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1002{
1003 uint64_t freq2k;
1004 unsigned p, n2, r2;
1005 struct wrpll_rnp best = { 0, 0, 0 };
1006 unsigned budget;
1007
1008 freq2k = clock / 100;
1009
1010 budget = wrpll_get_budget_for_freq(clock);
1011
1012 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1013 * and directly pass the LC PLL to it. */
1014 if (freq2k == 5400000) {
1015 *n2_out = 2;
1016 *p_out = 1;
1017 *r2_out = 2;
1018 return;
1019 }
1020
1021 /*
1022 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1023 * the WR PLL.
1024 *
1025 * We want R so that REF_MIN <= Ref <= REF_MAX.
1026 * Injecting R2 = 2 * R gives:
1027 * REF_MAX * r2 > LC_FREQ * 2 and
1028 * REF_MIN * r2 < LC_FREQ * 2
1029 *
1030 * Which means the desired boundaries for r2 are:
1031 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1032 *
1033 */
1034 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1035 r2 <= LC_FREQ * 2 / REF_MIN;
1036 r2++) {
1037
1038 /*
1039 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1040 *
1041 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1042 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1043 * VCO_MAX * r2 > n2 * LC_FREQ and
1044 * VCO_MIN * r2 < n2 * LC_FREQ)
1045 *
1046 * Which means the desired boundaries for n2 are:
1047 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1048 */
1049 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1050 n2 <= VCO_MAX * r2 / LC_FREQ;
1051 n2++) {
1052
1053 for (p = P_MIN; p <= P_MAX; p += P_INC)
1054 wrpll_update_rnp(freq2k, budget,
1055 r2, n2, p, &best);
1056 }
1057 }
6441ab5f 1058
1c0b85c5
DL		 1059 *n2_out = best.n2;
1060 *p_out = best.p;
1061 *r2_out = best.r2;
6441ab5f
PZ		 1062}
1063
0220ab6e 1064static bool
d664c0ce 1065hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1066 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1067 struct intel_encoder *intel_encoder,
1068 int clock)
6441ab5f 1069{
d664c0ce 1070 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1071 struct intel_shared_dpll *pll;
716c2e55 1072 uint32_t val;
1c0b85c5 1073 unsigned p, n2, r2;
6441ab5f 1074
d664c0ce 1075 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1076
114fe488 1077 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1078 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1079 WRPLL_DIVIDER_POST(p);
1080
190f68c5 1081 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1082
190f68c5 1083 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1084 if (pll == NULL) {
1085 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1086 pipe_name(intel_crtc->pipe));
1087 return false;
0694001b 1088 }
d452c5b6 1089
190f68c5 1090 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1091 }
1092
6441ab5f
PZ		 1093 return true;
1094}
1095
82d35437
S		 1096struct skl_wrpll_params {
1097 uint32_t dco_fraction;
1098 uint32_t dco_integer;
1099 uint32_t qdiv_ratio;
1100 uint32_t qdiv_mode;
1101 uint32_t kdiv;
1102 uint32_t pdiv;
1103 uint32_t central_freq;
1104};
1105
1106static void
1107skl_ddi_calculate_wrpll(int clock /* in Hz */,
1108 struct skl_wrpll_params *wrpll_params)
1109{
1110 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1111 uint64_t dco_central_freq[3] = {8400000000ULL,
1112 9000000000ULL,
1113 9600000000ULL};
82d35437
S		 1114 uint32_t min_dco_deviation = 400;
1115 uint32_t min_dco_index = 3;
1116 uint32_t P0[4] = {1, 2, 3, 7};
1117 uint32_t P2[4] = {1, 2, 3, 5};
1118 bool found = false;
1119 uint32_t candidate_p = 0;
1120 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1121 uint32_t candidate_p2[3] = {0};
1122 uint32_t dco_central_freq_deviation[3];
1123 uint32_t i, P1, k, dco_count;
1124 bool retry_with_odd = false;
1125 uint64_t dco_freq;
1126
1127 /* Determine P0, P1 or P2 */
1128 for (dco_count = 0; dco_count < 3; dco_count++) {
1129 found = false;
1130 candidate_p =
1131 div64_u64(dco_central_freq[dco_count], afe_clock);
1132 if (retry_with_odd == false)
1133 candidate_p = (candidate_p % 2 == 0 ?
1134 candidate_p : candidate_p + 1);
1135
1136 for (P1 = 1; P1 < candidate_p; P1++) {
1137 for (i = 0; i < 4; i++) {
1138 if (!(P0[i] != 1 || P1 == 1))
1139 continue;
1140
1141 for (k = 0; k < 4; k++) {
1142 if (P1 != 1 && P2[k] != 2)
1143 continue;
1144
1145 if (candidate_p == P0[i] * P1 * P2[k]) {
1146 /* Found possible P0, P1, P2 */
1147 found = true;
1148 candidate_p0[dco_count] = P0[i];
1149 candidate_p1[dco_count] = P1;
1150 candidate_p2[dco_count] = P2[k];
1151 goto found;
1152 }
1153
1154 }
1155 }
1156 }
1157
1158found:
1159 if (found) {
1160 dco_central_freq_deviation[dco_count] =
1161 div64_u64(10000 *
1162 abs_diff((candidate_p * afe_clock),
1163 dco_central_freq[dco_count]),
1164 dco_central_freq[dco_count]);
1165
1166 if (dco_central_freq_deviation[dco_count] <
1167 min_dco_deviation) {
1168 min_dco_deviation =
1169 dco_central_freq_deviation[dco_count];
1170 min_dco_index = dco_count;
1171 }
1172 }
1173
1174 if (min_dco_index > 2 && dco_count == 2) {
1175 retry_with_odd = true;
1176 dco_count = 0;
1177 }
1178 }
1179
1180 if (min_dco_index > 2) {
1181 WARN(1, "No valid values found for the given pixel clock\n");
1182 } else {
1183 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1184
1185 switch (dco_central_freq[min_dco_index]) {
21318cce 1186 case 9600000000ULL:
82d35437
S		 1187 wrpll_params->central_freq = 0;
1188 break;
21318cce 1189 case 9000000000ULL:
82d35437
S		 1190 wrpll_params->central_freq = 1;
1191 break;
21318cce 1192 case 8400000000ULL:
82d35437
S		 1193 wrpll_params->central_freq = 3;
1194 }
1195
1196 switch (candidate_p0[min_dco_index]) {
1197 case 1:
1198 wrpll_params->pdiv = 0;
1199 break;
1200 case 2:
1201 wrpll_params->pdiv = 1;
1202 break;
1203 case 3:
1204 wrpll_params->pdiv = 2;
1205 break;
1206 case 7:
1207 wrpll_params->pdiv = 4;
1208 break;
1209 default:
1210 WARN(1, "Incorrect PDiv\n");
1211 }
1212
1213 switch (candidate_p2[min_dco_index]) {
1214 case 5:
1215 wrpll_params->kdiv = 0;
1216 break;
1217 case 2:
1218 wrpll_params->kdiv = 1;
1219 break;
1220 case 3:
1221 wrpll_params->kdiv = 2;
1222 break;
1223 case 1:
1224 wrpll_params->kdiv = 3;
1225 break;
1226 default:
1227 WARN(1, "Incorrect KDiv\n");
1228 }
1229
1230 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1231 wrpll_params->qdiv_mode =
1232 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1233
1234 dco_freq = candidate_p0[min_dco_index] *
1235 candidate_p1[min_dco_index] *
1236 candidate_p2[min_dco_index] * afe_clock;
1237
1238 /*
1239 * Intermediate values are in Hz.
1240 * Divide by MHz to match bsepc
1241 */
1242 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1243 wrpll_params->dco_fraction =
1244 div_u64(((div_u64(dco_freq, 24) -
1245 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1246
1247 }
1248}
1249
1250
1251static bool
1252skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1253 struct intel_crtc_state *crtc_state,
82d35437
S		 1254 struct intel_encoder *intel_encoder,
1255 int clock)
1256{
1257 struct intel_shared_dpll *pll;
1258 uint32_t ctrl1, cfgcr1, cfgcr2;
1259
1260 /*
1261 * See comment in intel_dpll_hw_state to understand why we always use 0
1262 * as the DPLL id in this function.
1263 */
1264
1265 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1266
1267 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1268 struct skl_wrpll_params wrpll_params = { 0, };
1269
1270 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1271
1272 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1273
1274 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1275 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1276 wrpll_params.dco_integer;
1277
1278 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1279 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1280 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1281 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1282 wrpll_params.central_freq;
1283 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1284 struct drm_encoder *encoder = &intel_encoder->base;
1285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1286
1287 switch (intel_dp->link_bw) {
1288 case DP_LINK_BW_1_62:
1289 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1290 break;
1291 case DP_LINK_BW_2_7:
1292 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1293 break;
1294 case DP_LINK_BW_5_4:
1295 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1296 break;
1297 }
1298
1299 cfgcr1 = cfgcr2 = 0;
1300 } else /* eDP */
1301 return true;
1302
190f68c5
ACO		 1303 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1304 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1305 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1306
190f68c5 1307 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1308 if (pll == NULL) {
1309 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1310 pipe_name(intel_crtc->pipe));
1311 return false;
1312 }
1313
1314 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1315 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1316
1317 return true;
1318}
0220ab6e 1319
d683f3bc
S		 1320/* bxt clock parameters */
1321struct bxt_clk_div {
1322 uint32_t p1;
1323 uint32_t p2;
1324 uint32_t m2_int;
1325 uint32_t m2_frac;
1326 bool m2_frac_en;
1327 uint32_t n;
1328 uint32_t prop_coef;
1329 uint32_t int_coef;
1330 uint32_t gain_ctl;
1331 uint32_t targ_cnt;
1332 uint32_t lanestagger;
1333};
1334
1335/* pre-calculated values for DP linkrates */
1336static struct bxt_clk_div bxt_dp_clk_val[7] = {
1337 /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1338 /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
1339 /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
1340 /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1341 /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
1342 /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1343 /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
1344};
1345
1346static bool
1347bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1348 struct intel_crtc_state *crtc_state,
1349 struct intel_encoder *intel_encoder,
1350 int clock)
1351{
1352 struct intel_shared_dpll *pll;
1353 struct bxt_clk_div clk_div = {0};
1354
1355 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1356 intel_clock_t best_clock;
1357
1358 /* Calculate HDMI div */
1359 /*
1360 * FIXME: tie the following calculation into
1361 * i9xx_crtc_compute_clock
1362 */
1363 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1364 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1365 clock, pipe_name(intel_crtc->pipe));
1366 return false;
1367 }
1368
1369 clk_div.p1 = best_clock.p1;
1370 clk_div.p2 = best_clock.p2;
1371 WARN_ON(best_clock.m1 != 2);
1372 clk_div.n = best_clock.n;
1373 clk_div.m2_int = best_clock.m2 >> 22;
1374 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1375 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1376
1377 /* FIXME: set coef, gain, targcnt based on freq band */
1378 clk_div.prop_coef = 5;
1379 clk_div.int_coef = 11;
1380 clk_div.gain_ctl = 2;
1381 clk_div.targ_cnt = 9;
1382 if (clock > 270000)
1383 clk_div.lanestagger = 0x18;
1384 else if (clock > 135000)
1385 clk_div.lanestagger = 0x0d;
1386 else if (clock > 67000)
1387 clk_div.lanestagger = 0x07;
1388 else if (clock > 33000)
1389 clk_div.lanestagger = 0x04;
1390 else
1391 clk_div.lanestagger = 0x02;
1392 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1393 intel_encoder->type == INTEL_OUTPUT_EDP) {
1394 struct drm_encoder *encoder = &intel_encoder->base;
1395 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1396
1397 switch (intel_dp->link_bw) {
1398 case DP_LINK_BW_1_62:
1399 clk_div = bxt_dp_clk_val[0];
1400 break;
1401 case DP_LINK_BW_2_7:
1402 clk_div = bxt_dp_clk_val[1];
1403 break;
1404 case DP_LINK_BW_5_4:
1405 clk_div = bxt_dp_clk_val[2];
1406 break;
1407 default:
1408 clk_div = bxt_dp_clk_val[0];
1409 DRM_ERROR("Unknown link rate\n");
1410 }
1411 }
1412
1413 crtc_state->dpll_hw_state.ebb0 =
1414 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1415 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1416 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1417 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1418
1419 if (clk_div.m2_frac_en)
1420 crtc_state->dpll_hw_state.pll3 =
1421 PORT_PLL_M2_FRAC_ENABLE;
1422
1423 crtc_state->dpll_hw_state.pll6 =
1424 clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
1425 crtc_state->dpll_hw_state.pll6 |=
1426 PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
1427
1428 crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
1429
1430 crtc_state->dpll_hw_state.pcsdw12 =
1431 LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
1432
1433 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1434 if (pll == NULL) {
1435 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1436 pipe_name(intel_crtc->pipe));
1437 return false;
1438 }
1439
1440 /* shared DPLL id 0 is DPLL A */
1441 crtc_state->ddi_pll_sel = pll->id;
1442
1443 return true;
1444}
1445
0220ab6e
DL		 1446/*
1447 * Tries to find a *shared* PLL for the CRTC and store it in
1448 * intel_crtc->ddi_pll_sel.
1449 *
1450 * For private DPLLs, compute_config() should do the selection for us. This
1451 * function should be folded into compute_config() eventually.
1452 */
190f68c5
ACO		 1453bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1454 struct intel_crtc_state *crtc_state)
0220ab6e 1455{
82d35437 1456 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1457 struct intel_encoder *intel_encoder =
3165c074 1458 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1459 int clock = crtc_state->port_clock;
0220ab6e 1460
82d35437 1461 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1462 return skl_ddi_pll_select(intel_crtc, crtc_state,
1463 intel_encoder, clock);
d683f3bc
S		 1464 else if (IS_BROXTON(dev))
1465 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1466 intel_encoder, clock);
82d35437 1467 else
190f68c5
ACO		 1468 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1469 intel_encoder, clock);
0220ab6e
DL		 1470}
1471
dae84799
PZ		 1472void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1473{
1474 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1476 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1477 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1478 int type = intel_encoder->type;
1479 uint32_t temp;
1480
0e32b39c 1481 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1482 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1483 switch (intel_crtc->config->pipe_bpp) {
dae84799 1484 case 18:
c9809791 1485 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1486 break;
1487 case 24:
c9809791 1488 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1489 break;
1490 case 30:
c9809791 1491 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1492 break;
1493 case 36:
c9809791 1494 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1495 break;
1496 default:
4e53c2e0 1497 BUG();
dae84799 1498 }
c9809791 1499 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1500 }
1501}
1502
0e32b39c
DA		 1503void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1504{
1505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1506 struct drm_device *dev = crtc->dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1508 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1509 uint32_t temp;
1510 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1511 if (state == true)
1512 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1513 else
1514 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1515 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1516}
1517
8228c251 1518void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1519{
1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1522 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1523 struct drm_device *dev = crtc->dev;
1524 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1525 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1526 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1527 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1528 int type = intel_encoder->type;
8d9ddbcb
PZ		 1529 uint32_t temp;
1530
ad80a810
PZ		 1531 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1532 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1533 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1534
6e3c9717 1535 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1536 case 18:
ad80a810 1537 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1538 break;
1539 case 24:
ad80a810 1540 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1541 break;
1542 case 30:
ad80a810 1543 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1544 break;
1545 case 36:
ad80a810 1546 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1547 break;
1548 default:
4e53c2e0 1549 BUG();
dfcef252 1550 }
72662e10 1551
6e3c9717 1552 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1553 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1554 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1555 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1556
e6f0bfc4
PZ		 1557 if (cpu_transcoder == TRANSCODER_EDP) {
1558 switch (pipe) {
1559 case PIPE_A:
c7670b10
PZ		 1560 /* On Haswell, can only use the always-on power well for
1561 * eDP when not using the panel fitter, and when not
1562 * using motion blur mitigation (which we don't
1563 * support). */
fabf6e51 1564 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1565 (intel_crtc->config->pch_pfit.enabled ||
1566 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1567 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1568 else
1569 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1570 break;
1571 case PIPE_B:
1572 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1573 break;
1574 case PIPE_C:
1575 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1576 break;
1577 default:
1578 BUG();
1579 break;
1580 }
1581 }
1582
7739c33b 1583 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1584 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1585 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1586 else
ad80a810 1587 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1588
7739c33b 1589 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1590 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1591 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1592
1593 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1594 type == INTEL_OUTPUT_EDP) {
1595 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1596
0e32b39c
DA		 1597 if (intel_dp->is_mst) {
1598 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1599 } else
1600 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1601
1602 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1603 } else if (type == INTEL_OUTPUT_DP_MST) {
1604 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1605
1606 if (intel_dp->is_mst) {
1607 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1608 } else
1609 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1610
17aa6be9 1611 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1612 } else {
84f44ce7
VS		 1613 WARN(1, "Invalid encoder type %d for pipe %c\n",
1614 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1615 }
1616
ad80a810 1617 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1618}
72662e10 1619
ad80a810
PZ		 1620void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1621 enum transcoder cpu_transcoder)
8d9ddbcb 1622{
ad80a810 1623 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1624 uint32_t val = I915_READ(reg);
1625
0e32b39c 1626 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1627 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1628 I915_WRITE(reg, val);
72662e10
ED		 1629}
1630
bcbc889b
PZ		 1631bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1632{
1633 struct drm_device *dev = intel_connector->base.dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 struct intel_encoder *intel_encoder = intel_connector->encoder;
1636 int type = intel_connector->base.connector_type;
1637 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1638 enum pipe pipe = 0;
1639 enum transcoder cpu_transcoder;
882244a3 1640 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1641 uint32_t tmp;
1642
882244a3 1643 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1644 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1645 return false;
1646
bcbc889b
PZ		 1647 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1648 return false;
1649
1650 if (port == PORT_A)
1651 cpu_transcoder = TRANSCODER_EDP;
1652 else
1a240d4d 1653 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1654
1655 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1656
1657 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1658 case TRANS_DDI_MODE_SELECT_HDMI:
1659 case TRANS_DDI_MODE_SELECT_DVI:
1660 return (type == DRM_MODE_CONNECTOR_HDMIA);
1661
1662 case TRANS_DDI_MODE_SELECT_DP_SST:
1663 if (type == DRM_MODE_CONNECTOR_eDP)
1664 return true;
bcbc889b 1665 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1666 case TRANS_DDI_MODE_SELECT_DP_MST:
1667 /* if the transcoder is in MST state then
1668 * connector isn't connected */
1669 return false;
bcbc889b
PZ		 1670
1671 case TRANS_DDI_MODE_SELECT_FDI:
1672 return (type == DRM_MODE_CONNECTOR_VGA);
1673
1674 default:
1675 return false;
1676 }
1677}
1678
85234cdc
DV		 1679bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1680 enum pipe *pipe)
1681{
1682 struct drm_device *dev = encoder->base.dev;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1684 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1685 enum intel_display_power_domain power_domain;
85234cdc
DV		 1686 u32 tmp;
1687 int i;
1688
6d129bea 1689 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1690 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1691 return false;
1692
fe43d3f5 1693 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1694
1695 if (!(tmp & DDI_BUF_CTL_ENABLE))
1696 return false;
1697
ad80a810
PZ		 1698 if (port == PORT_A) {
1699 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1700
ad80a810
PZ		 1701 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1702 case TRANS_DDI_EDP_INPUT_A_ON:
1703 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1704 *pipe = PIPE_A;
1705 break;
1706 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1707 *pipe = PIPE_B;
1708 break;
1709 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1710 *pipe = PIPE_C;
1711 break;
1712 }
1713
1714 return true;
1715 } else {
1716 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1717 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1718
1719 if ((tmp & TRANS_DDI_PORT_MASK)
1720 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1721 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1722 return false;
1723
ad80a810
PZ		 1724 *pipe = i;
1725 return true;
1726 }
85234cdc
DV		 1727 }
1728 }
1729
84f44ce7 1730 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1731
22f9fe50 1732 return false;
85234cdc
DV		 1733}
1734
fc914639
PZ		 1735void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1736{
1737 struct drm_crtc *crtc = &intel_crtc->base;
1738 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1739 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1740 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1741 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1742
bb523fc0
PZ		 1743 if (cpu_transcoder != TRANSCODER_EDP)
1744 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1745 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1746}
1747
1748void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1749{
1750 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1751 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1752
bb523fc0
PZ		 1753 if (cpu_transcoder != TRANSCODER_EDP)
1754 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1755 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1756}
1757
96fb9f9b
VK		 1758void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1759 enum port port, int type)
1760{
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 const struct bxt_ddi_buf_trans *ddi_translations;
1763 u32 n_entries, i;
1764 uint32_t val;
1765
1766 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1767 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1768 ddi_translations = bxt_ddi_translations_dp;
1769 } else if (type == INTEL_OUTPUT_HDMI) {
1770 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1771 ddi_translations = bxt_ddi_translations_hdmi;
1772 } else {
1773 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1774 type);
1775 return;
1776 }
1777
1778 /* Check if default value has to be used */
1779 if (level >= n_entries ||
1780 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1781 for (i = 0; i < n_entries; i++) {
1782 if (ddi_translations[i].default_index) {
1783 level = i;
1784 break;
1785 }
1786 }
1787 }
1788
1789 /*
1790 * While we write to the group register to program all lanes at once we
1791 * can read only lane registers and we pick lanes 0/1 for that.
1792 */
1793 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1794 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1795 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1796
1797 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1798 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1799 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1800 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1801 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1802
1803 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1804 val &= ~UNIQE_TRANGE_EN_METHOD;
1805 if (ddi_translations[level].enable)
1806 val |= UNIQE_TRANGE_EN_METHOD;
1807 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1808
1809 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1810 val &= ~DE_EMPHASIS;
1811 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1812 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1813
1814 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1815 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1816 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1817}
1818
00c09d70 1819static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1820{
c19b0669 1821 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1822 struct drm_device *dev = encoder->dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1824 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1825 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1826 int type = intel_encoder->type;
96fb9f9b 1827 int hdmi_level;
6441ab5f 1828
82a4d9c0
PZ		 1829 if (type == INTEL_OUTPUT_EDP) {
1830 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1831 intel_edp_panel_on(intel_dp);
82a4d9c0 1832 }
6441ab5f 1833
efa80add 1834 if (IS_SKYLAKE(dev)) {
6e3c9717 1835 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1836 uint32_t val;
1837
5416d871
DL		 1838 /*
1839 * DPLL0 is used for eDP and is the only "private" DPLL (as
1840 * opposed to shared) on SKL
1841 */
1842 if (type == INTEL_OUTPUT_EDP) {
1843 WARN_ON(dpll != SKL_DPLL0);
1844
1845 val = I915_READ(DPLL_CTRL1);
1846
1847 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1848 DPLL_CTRL1_SSC(dpll) |
1849 DPLL_CRTL1_LINK_RATE_MASK(dpll));
6e3c9717 1850 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1851
1852 I915_WRITE(DPLL_CTRL1, val);
1853 POSTING_READ(DPLL_CTRL1);
1854 }
1855
1856 /* DDI -> PLL mapping */
efa80add
S		 1857 val = I915_READ(DPLL_CTRL2);
1858
1859 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1860 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1861 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1862 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1863
1864 I915_WRITE(DPLL_CTRL2, val);
5416d871 1865
1ab23380 1866 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1867 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1868 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1869 }
c19b0669 1870
82a4d9c0 1871 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1872 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1873
44905a27 1874 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1875
1876 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1877 intel_dp_start_link_train(intel_dp);
1878 intel_dp_complete_link_train(intel_dp);
23f08d83 1879 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1880 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1881 } else if (type == INTEL_OUTPUT_HDMI) {
1882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1883
96fb9f9b
VK		 1884 if (IS_BROXTON(dev)) {
1885 hdmi_level = dev_priv->vbt.
1886 ddi_port_info[port].hdmi_level_shift;
1887 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1888 INTEL_OUTPUT_HDMI);
1889 }
30cf6db8 1890 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1891 crtc->config->has_hdmi_sink,
1892 &crtc->config->base.adjusted_mode);
c19b0669 1893 }
6441ab5f
PZ		 1894}
1895
00c09d70 1896static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1897{
1898 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1899 struct drm_device *dev = encoder->dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1901 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1902 int type = intel_encoder->type;
2886e93f 1903 uint32_t val;
a836bdf9 1904 bool wait = false;
2886e93f
PZ		 1905
1906 val = I915_READ(DDI_BUF_CTL(port));
1907 if (val & DDI_BUF_CTL_ENABLE) {
1908 val &= ~DDI_BUF_CTL_ENABLE;
1909 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1910 wait = true;
2886e93f 1911 }
6441ab5f 1912
a836bdf9
PZ		 1913 val = I915_READ(DP_TP_CTL(port));
1914 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1915 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1916 I915_WRITE(DP_TP_CTL(port), val);
1917
1918 if (wait)
1919 intel_wait_ddi_buf_idle(dev_priv, port);
1920
76bb80ed 1921 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1922 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1923 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1924 intel_edp_panel_vdd_on(intel_dp);
4be73780 1925 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1926 }
1927
efa80add
S		 1928 if (IS_SKYLAKE(dev))
1929 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1930 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1931 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1932 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1933}
1934
00c09d70 1935static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1936{
6547fef8 1937 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1938 struct drm_crtc *crtc = encoder->crtc;
1939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1940 struct drm_device *dev = encoder->dev;
72662e10 1941 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1942 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1943 int type = intel_encoder->type;
72662e10 1944
6547fef8 1945 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1946 struct intel_digital_port *intel_dig_port =
1947 enc_to_dig_port(encoder);
1948
6547fef8
PZ		 1949 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1950 * are ignored so nothing special needs to be done besides
1951 * enabling the port.
1952 */
876a8cdf 1953 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1954 intel_dig_port->saved_port_bits |
1955 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1956 } else if (type == INTEL_OUTPUT_EDP) {
1957 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1958
23f08d83 1959 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1960 intel_dp_stop_link_train(intel_dp);
1961
4be73780 1962 intel_edp_backlight_on(intel_dp);
0bc12bcb 1963 intel_psr_enable(intel_dp);
c395578e 1964 intel_edp_drrs_enable(intel_dp);
6547fef8 1965 }
7b9f35a6 1966
6e3c9717 1967 if (intel_crtc->config->has_audio) {
d45a0bf5 1968 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1969 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1970 }
5ab432ef
DV		 1971}
1972
00c09d70 1973static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1974{
d6c50ff8 1975 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1976 struct drm_crtc *crtc = encoder->crtc;
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1978 int type = intel_encoder->type;
7b9f35a6
WX		 1979 struct drm_device *dev = encoder->dev;
1980 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1981
6e3c9717 1982 if (intel_crtc->config->has_audio) {
69bfe1a9 1983 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1984 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1985 }
2831d842 1986
d6c50ff8
PZ		 1987 if (type == INTEL_OUTPUT_EDP) {
1988 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1989
c395578e 1990 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1991 intel_psr_disable(intel_dp);
4be73780 1992 intel_edp_backlight_off(intel_dp);
d6c50ff8 1993 }
72662e10 1994}
79f689aa 1995
e0b01be4
DV		 1996static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1997 struct intel_shared_dpll *pll)
1998{
3e369b76 1999 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2000 POSTING_READ(WRPLL_CTL(pll->id));
2001 udelay(20);
2002}
2003
12030431
DV		 2004static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2005 struct intel_shared_dpll *pll)
2006{
2007 uint32_t val;
2008
2009 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2010 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2011 POSTING_READ(WRPLL_CTL(pll->id));
2012}
2013
d452c5b6
DV		 2014static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2015 struct intel_shared_dpll *pll,
2016 struct intel_dpll_hw_state *hw_state)
2017{
2018 uint32_t val;
2019
f458ebbc 2020 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2021 return false;
2022
2023 val = I915_READ(WRPLL_CTL(pll->id));
2024 hw_state->wrpll = val;
2025
2026 return val & WRPLL_PLL_ENABLE;
2027}
2028
ca1381b5 2029static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2030 "WRPLL 1",
2031 "WRPLL 2",
2032};
2033
143b307c 2034static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2035{
9cd86933
DV		 2036 int i;
2037
716c2e55 2038 dev_priv->num_shared_dpll = 2;
9cd86933 2039
716c2e55 2040 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2041 dev_priv->shared_dplls[i].id = i;
2042 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2043 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2044 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2045 dev_priv->shared_dplls[i].get_hw_state =
2046 hsw_ddi_pll_get_hw_state;
9cd86933 2047 }
143b307c
DL		 2048}
2049
d1a2dc78
S		 2050static const char * const skl_ddi_pll_names[] = {
2051 "DPLL 1",
2052 "DPLL 2",
2053 "DPLL 3",
2054};
2055
2056struct skl_dpll_regs {
2057 u32 ctl, cfgcr1, cfgcr2;
2058};
2059
2060/* this array is indexed by the *shared* pll id */
2061static const struct skl_dpll_regs skl_dpll_regs[3] = {
2062 {
2063 /* DPLL 1 */
2064 .ctl = LCPLL2_CTL,
2065 .cfgcr1 = DPLL1_CFGCR1,
2066 .cfgcr2 = DPLL1_CFGCR2,
2067 },
2068 {
2069 /* DPLL 2 */
2070 .ctl = WRPLL_CTL1,
2071 .cfgcr1 = DPLL2_CFGCR1,
2072 .cfgcr2 = DPLL2_CFGCR2,
2073 },
2074 {
2075 /* DPLL 3 */
2076 .ctl = WRPLL_CTL2,
2077 .cfgcr1 = DPLL3_CFGCR1,
2078 .cfgcr2 = DPLL3_CFGCR2,
2079 },
2080};
2081
2082static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2083 struct intel_shared_dpll *pll)
2084{
2085 uint32_t val;
2086 unsigned int dpll;
2087 const struct skl_dpll_regs *regs = skl_dpll_regs;
2088
2089 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2090 dpll = pll->id + 1;
2091
2092 val = I915_READ(DPLL_CTRL1);
2093
2094 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2095 DPLL_CRTL1_LINK_RATE_MASK(dpll));
2096 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2097
2098 I915_WRITE(DPLL_CTRL1, val);
2099 POSTING_READ(DPLL_CTRL1);
2100
2101 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2102 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2103 POSTING_READ(regs[pll->id].cfgcr1);
2104 POSTING_READ(regs[pll->id].cfgcr2);
2105
2106 /* the enable bit is always bit 31 */
2107 I915_WRITE(regs[pll->id].ctl,
2108 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2109
2110 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2111 DRM_ERROR("DPLL %d not locked\n", dpll);
2112}
2113
2114static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2115 struct intel_shared_dpll *pll)
2116{
2117 const struct skl_dpll_regs *regs = skl_dpll_regs;
2118
2119 /* the enable bit is always bit 31 */
2120 I915_WRITE(regs[pll->id].ctl,
2121 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2122 POSTING_READ(regs[pll->id].ctl);
2123}
2124
2125static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2126 struct intel_shared_dpll *pll,
2127 struct intel_dpll_hw_state *hw_state)
2128{
2129 uint32_t val;
2130 unsigned int dpll;
2131 const struct skl_dpll_regs *regs = skl_dpll_regs;
2132
2133 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2134 return false;
2135
2136 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2137 dpll = pll->id + 1;
2138
2139 val = I915_READ(regs[pll->id].ctl);
2140 if (!(val & LCPLL_PLL_ENABLE))
2141 return false;
2142
2143 val = I915_READ(DPLL_CTRL1);
2144 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2145
2146 /* avoid reading back stale values if HDMI mode is not enabled */
2147 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2148 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2149 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2150 }
2151
2152 return true;
2153}
2154
2155static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2156{
2157 int i;
2158
2159 dev_priv->num_shared_dpll = 3;
2160
2161 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2162 dev_priv->shared_dplls[i].id = i;
2163 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2164 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2165 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2166 dev_priv->shared_dplls[i].get_hw_state =
2167 skl_ddi_pll_get_hw_state;
2168 }
2169}
2170
5c6706e5
VK		 2171static void broxton_phy_init(struct drm_i915_private *dev_priv,
2172 enum dpio_phy phy)
2173{
2174 enum port port;
2175 uint32_t val;
2176
2177 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2178 val |= GT_DISPLAY_POWER_ON(phy);
2179 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2180
2181 /* Considering 10ms timeout until BSpec is updated */
2182 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2183 DRM_ERROR("timeout during PHY%d power on\n", phy);
2184
2185 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2186 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2187 int lane;
2188
2189 for (lane = 0; lane < 4; lane++) {
2190 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2191 /*
2192 * Note that on CHV this flag is called UPAR, but has
2193 * the same function.
2194 */
2195 val &= ~LATENCY_OPTIM;
2196 if (lane != 1)
2197 val |= LATENCY_OPTIM;
2198
2199 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2200 }
2201 }
2202
2203 /* Program PLL Rcomp code offset */
2204 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2205 val &= ~IREF0RC_OFFSET_MASK;
2206 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2207 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2208
2209 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2210 val &= ~IREF1RC_OFFSET_MASK;
2211 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2212 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2213
2214 /* Program power gating */
2215 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2216 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2217 SUS_CLK_CONFIG;
2218 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2219
2220 if (phy == DPIO_PHY0) {
2221 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2222 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2223 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2224 }
2225
2226 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2227 val &= ~OCL2_LDOFUSE_PWR_DIS;
2228 /*
2229 * On PHY1 disable power on the second channel, since no port is
2230 * connected there. On PHY0 both channels have a port, so leave it
2231 * enabled.
2232 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2233 * power down the second channel on PHY0 as well.
2234 */
2235 if (phy == DPIO_PHY1)
2236 val |= OCL2_LDOFUSE_PWR_DIS;
2237 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2238
2239 if (phy == DPIO_PHY0) {
2240 uint32_t grc_code;
2241 /*
2242 * PHY0 isn't connected to an RCOMP resistor so copy over
2243 * the corresponding calibrated value from PHY1, and disable
2244 * the automatic calibration on PHY0.
2245 */
2246 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2247 10))
2248 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2249
2250 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2251 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2252 grc_code = val << GRC_CODE_FAST_SHIFT |
2253 val << GRC_CODE_SLOW_SHIFT |
2254 val;
2255 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2256
2257 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2258 val |= GRC_DIS | GRC_RDY_OVRD;
2259 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2260 }
2261
2262 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2263 val |= COMMON_RESET_DIS;
2264 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2265}
2266
2267void broxton_ddi_phy_init(struct drm_device *dev)
2268{
2269 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2270 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2271 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2272}
2273
2274static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2275 enum dpio_phy phy)
2276{
2277 uint32_t val;
2278
2279 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2280 val &= ~COMMON_RESET_DIS;
2281 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2282}
2283
2284void broxton_ddi_phy_uninit(struct drm_device *dev)
2285{
2286 struct drm_i915_private *dev_priv = dev->dev_private;
2287
2288 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2289 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2290
2291 /* FIXME: do this in broxton_phy_uninit per phy */
2292 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2293}
2294
dfb82408
S		 2295static const char * const bxt_ddi_pll_names[] = {
2296 "PORT PLL A",
2297 "PORT PLL B",
2298 "PORT PLL C",
2299};
2300
2301static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2302 struct intel_shared_dpll *pll)
2303{
2304 uint32_t temp;
2305 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2306
2307 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2308 temp &= ~PORT_PLL_REF_SEL;
2309 /* Non-SSC reference */
2310 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2311
2312 /* Disable 10 bit clock */
2313 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2314 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2315 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2316
2317 /* Write P1 & P2 */
2318 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2319 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2320 temp |= pll->config.hw_state.ebb0;
2321 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2322
2323 /* Write M2 integer */
2324 temp = I915_READ(BXT_PORT_PLL(port, 0));
2325 temp &= ~PORT_PLL_M2_MASK;
2326 temp |= pll->config.hw_state.pll0;
2327 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2328
2329 /* Write N */
2330 temp = I915_READ(BXT_PORT_PLL(port, 1));
2331 temp &= ~PORT_PLL_N_MASK;
2332 temp |= pll->config.hw_state.pll1;
2333 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2334
2335 /* Write M2 fraction */
2336 temp = I915_READ(BXT_PORT_PLL(port, 2));
2337 temp &= ~PORT_PLL_M2_FRAC_MASK;
2338 temp |= pll->config.hw_state.pll2;
2339 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2340
2341 /* Write M2 fraction enable */
2342 temp = I915_READ(BXT_PORT_PLL(port, 3));
2343 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2344 temp |= pll->config.hw_state.pll3;
2345 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2346
2347 /* Write coeff */
2348 temp = I915_READ(BXT_PORT_PLL(port, 6));
2349 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2350 temp &= ~PORT_PLL_INT_COEFF_MASK;
2351 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2352 temp |= pll->config.hw_state.pll6;
2353 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2354
2355 /* Write calibration val */
2356 temp = I915_READ(BXT_PORT_PLL(port, 8));
2357 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2358 temp |= pll->config.hw_state.pll8;
2359 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2360
2361 /*
2362 * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
2363 * specification update.
2364 */
2365
2366 /* Recalibrate with new settings */
2367 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2368 temp |= PORT_PLL_RECALIBRATE;
2369 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2370 /* Enable 10 bit clock */
2371 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2372 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2373
2374 /* Enable PLL */
2375 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2376 temp |= PORT_PLL_ENABLE;
2377 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2378 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2379
2380 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2381 PORT_PLL_LOCK), 200))
2382 DRM_ERROR("PLL %d not locked\n", port);
2383
2384 /*
2385 * While we write to the group register to program all lanes at once we
2386 * can read only lane registers and we pick lanes 0/1 for that.
2387 */
2388 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2389 temp &= ~LANE_STAGGER_MASK;
2390 temp &= ~LANESTAGGER_STRAP_OVRD;
2391 temp |= pll->config.hw_state.pcsdw12;
2392 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2393}
2394
2395static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2396 struct intel_shared_dpll *pll)
2397{
2398 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2399 uint32_t temp;
2400
2401 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2402 temp &= ~PORT_PLL_ENABLE;
2403 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2404 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2405}
2406
2407static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2408 struct intel_shared_dpll *pll,
2409 struct intel_dpll_hw_state *hw_state)
2410{
2411 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2412 uint32_t val;
2413
2414 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2415 return false;
2416
2417 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2418 if (!(val & PORT_PLL_ENABLE))
2419 return false;
2420
2421 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2422 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2423 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2424 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2425 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2426 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2427 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2428 /*
2429 * While we write to the group register to program all lanes at once we
2430 * can read only lane registers. We configure all lanes the same way, so
2431 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2432 */
2433 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2434 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2435 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2436 hw_state->pcsdw12,
2437 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2438
2439 return true;
2440}
2441
2442static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2443{
2444 int i;
2445
2446 dev_priv->num_shared_dpll = 3;
2447
2448 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2449 dev_priv->shared_dplls[i].id = i;
2450 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2451 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2452 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2453 dev_priv->shared_dplls[i].get_hw_state =
2454 bxt_ddi_pll_get_hw_state;
2455 }
2456}
2457
143b307c
DL		 2458void intel_ddi_pll_init(struct drm_device *dev)
2459{
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 uint32_t val = I915_READ(LCPLL_CTL);
2462
d1a2dc78
S		 2463 if (IS_SKYLAKE(dev))
2464 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2465 else if (IS_BROXTON(dev))
2466 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2467 else
2468 hsw_shared_dplls_init(dev_priv);
79f689aa 2469
b2b877ff 2470 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1652d19e 2471 dev_priv->display.get_display_clock_speed(dev));
79f689aa 2472
121643c2
S		 2473 if (IS_SKYLAKE(dev)) {
2474 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2475 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 2476 } else if (IS_BROXTON(dev)) {
2477 broxton_init_cdclk(dev);
5c6706e5 2478 broxton_ddi_phy_init(dev);
121643c2
S		 2479 } else {
2480 /*
2481 * The LCPLL register should be turned on by the BIOS. For now
2482 * let's just check its state and print errors in case
2483 * something is wrong. Don't even try to turn it on.
2484 */
2485
2486 if (val & LCPLL_CD_SOURCE_FCLK)
2487 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2488
121643c2
S		 2489 if (val & LCPLL_PLL_DISABLE)
2490 DRM_ERROR("LCPLL is disabled\n");
2491 }
79f689aa 2492}
c19b0669
PZ		 2493
2494void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2495{
174edf1f
PZ		 2496 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2497 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2498 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2499 enum port port = intel_dig_port->port;
c19b0669 2500 uint32_t val;
f3e227df 2501 bool wait = false;
c19b0669
PZ		 2502
2503 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2504 val = I915_READ(DDI_BUF_CTL(port));
2505 if (val & DDI_BUF_CTL_ENABLE) {
2506 val &= ~DDI_BUF_CTL_ENABLE;
2507 I915_WRITE(DDI_BUF_CTL(port), val);
2508 wait = true;
2509 }
2510
2511 val = I915_READ(DP_TP_CTL(port));
2512 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2513 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2514 I915_WRITE(DP_TP_CTL(port), val);
2515 POSTING_READ(DP_TP_CTL(port));
2516
2517 if (wait)
2518 intel_wait_ddi_buf_idle(dev_priv, port);
2519 }
2520
0e32b39c 2521 val = DP_TP_CTL_ENABLE |
c19b0669 2522 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2523 if (intel_dp->is_mst)
2524 val |= DP_TP_CTL_MODE_MST;
2525 else {
2526 val |= DP_TP_CTL_MODE_SST;
2527 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2528 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2529 }
c19b0669
PZ		 2530 I915_WRITE(DP_TP_CTL(port), val);
2531 POSTING_READ(DP_TP_CTL(port));
2532
2533 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2534 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2535 POSTING_READ(DDI_BUF_CTL(port));
2536
2537 udelay(600);
2538}
00c09d70 2539
1ad960f2
PZ		 2540void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2541{
2542 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2543 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2544 uint32_t val;
2545
2546 intel_ddi_post_disable(intel_encoder);
2547
2548 val = I915_READ(_FDI_RXA_CTL);
2549 val &= ~FDI_RX_ENABLE;
2550 I915_WRITE(_FDI_RXA_CTL, val);
2551
2552 val = I915_READ(_FDI_RXA_MISC);
2553 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2554 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2555 I915_WRITE(_FDI_RXA_MISC, val);
2556
2557 val = I915_READ(_FDI_RXA_CTL);
2558 val &= ~FDI_PCDCLK;
2559 I915_WRITE(_FDI_RXA_CTL, val);
2560
2561 val = I915_READ(_FDI_RXA_CTL);
2562 val &= ~FDI_RX_PLL_ENABLE;
2563 I915_WRITE(_FDI_RXA_CTL, val);
2564}
2565
00c09d70
PZ		 2566static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2567{
0e32b39c
DA		 2568 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2569 int type = intel_dig_port->base.type;
2570
2571 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2572 type != INTEL_OUTPUT_EDP &&
2573 type != INTEL_OUTPUT_UNKNOWN) {
2574 return;
2575 }
00c09d70 2576
0e32b39c 2577 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2578}
2579
6801c18c 2580void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2581 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2582{
2583 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2584 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2585 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2586 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2587 u32 temp, flags = 0;
2588
2589 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2590 if (temp & TRANS_DDI_PHSYNC)
2591 flags |= DRM_MODE_FLAG_PHSYNC;
2592 else
2593 flags |= DRM_MODE_FLAG_NHSYNC;
2594 if (temp & TRANS_DDI_PVSYNC)
2595 flags |= DRM_MODE_FLAG_PVSYNC;
2596 else
2597 flags |= DRM_MODE_FLAG_NVSYNC;
2598
2d112de7 2599 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2600
2601 switch (temp & TRANS_DDI_BPC_MASK) {
2602 case TRANS_DDI_BPC_6:
2603 pipe_config->pipe_bpp = 18;
2604 break;
2605 case TRANS_DDI_BPC_8:
2606 pipe_config->pipe_bpp = 24;
2607 break;
2608 case TRANS_DDI_BPC_10:
2609 pipe_config->pipe_bpp = 30;
2610 break;
2611 case TRANS_DDI_BPC_12:
2612 pipe_config->pipe_bpp = 36;
2613 break;
2614 default:
2615 break;
2616 }
eb14cb74
VS		 2617
2618 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2619 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2620 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2621 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2622
2623 if (intel_hdmi->infoframe_enabled(&encoder->base))
2624 pipe_config->has_infoframe = true;
cbc572a9 2625 break;
eb14cb74
VS		 2626 case TRANS_DDI_MODE_SELECT_DVI:
2627 case TRANS_DDI_MODE_SELECT_FDI:
2628 break;
2629 case TRANS_DDI_MODE_SELECT_DP_SST:
2630 case TRANS_DDI_MODE_SELECT_DP_MST:
2631 pipe_config->has_dp_encoder = true;
2632 intel_dp_get_m_n(intel_crtc, pipe_config);
2633 break;
2634 default:
2635 break;
2636 }
10214420 2637
f458ebbc 2638 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2639 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2640 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2641 pipe_config->has_audio = true;
2642 }
9ed109a7 2643
10214420
DV		 2644 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2645 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2646 /*
2647 * This is a big fat ugly hack.
2648 *
2649 * Some machines in UEFI boot mode provide us a VBT that has 18
2650 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2651 * unknown we fail to light up. Yet the same BIOS boots up with
2652 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2653 * max, not what it tells us to use.
2654 *
2655 * Note: This will still be broken if the eDP panel is not lit
2656 * up by the BIOS, and thus we can't get the mode at module
2657 * load.
2658 */
2659 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2660 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2661 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2662 }
11578553 2663
22606a18 2664 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2665}
2666
00c09d70
PZ		 2667static void intel_ddi_destroy(struct drm_encoder *encoder)
2668{
2669 /* HDMI has nothing special to destroy, so we can go with this. */
2670 intel_dp_encoder_destroy(encoder);
2671}
2672
5bfe2ac0 2673static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2674 struct intel_crtc_state *pipe_config)
00c09d70 2675{
5bfe2ac0 2676 int type = encoder->type;
eccb140b 2677 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2678
5bfe2ac0 2679 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2680
eccb140b
DV		 2681 if (port == PORT_A)
2682 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2683
00c09d70 2684 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2685 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2686 else
5bfe2ac0 2687 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2688}
2689
2690static const struct drm_encoder_funcs intel_ddi_funcs = {
2691 .destroy = intel_ddi_destroy,
2692};
2693
4a28ae58
PZ		 2694static struct intel_connector *
2695intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2696{
2697 struct intel_connector *connector;
2698 enum port port = intel_dig_port->port;
2699
9bdbd0b9 2700 connector = intel_connector_alloc();
4a28ae58
PZ		 2701 if (!connector)
2702 return NULL;
2703
2704 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2705 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2706 kfree(connector);
2707 return NULL;
2708 }
2709
2710 return connector;
2711}
2712
2713static struct intel_connector *
2714intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2715{
2716 struct intel_connector *connector;
2717 enum port port = intel_dig_port->port;
2718
9bdbd0b9 2719 connector = intel_connector_alloc();
4a28ae58
PZ		 2720 if (!connector)
2721 return NULL;
2722
2723 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2724 intel_hdmi_init_connector(intel_dig_port, connector);
2725
2726 return connector;
2727}
2728
00c09d70
PZ		 2729void intel_ddi_init(struct drm_device *dev, enum port port)
2730{
876a8cdf 2731 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2732 struct intel_digital_port *intel_dig_port;
2733 struct intel_encoder *intel_encoder;
2734 struct drm_encoder *encoder;
311a2094
PZ		 2735 bool init_hdmi, init_dp;
2736
2737 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2738 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2739 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2740 if (!init_dp && !init_hdmi) {
f68d697e 2741 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2742 port_name(port));
2743 init_hdmi = true;
2744 init_dp = true;
2745 }
00c09d70 2746
b14c5679 2747 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2748 if (!intel_dig_port)
2749 return;
2750
00c09d70
PZ		 2751 intel_encoder = &intel_dig_port->base;
2752 encoder = &intel_encoder->base;
2753
2754 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2755 DRM_MODE_ENCODER_TMDS);
00c09d70 2756
5bfe2ac0 2757 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2758 intel_encoder->enable = intel_enable_ddi;
2759 intel_encoder->pre_enable = intel_ddi_pre_enable;
2760 intel_encoder->disable = intel_disable_ddi;
2761 intel_encoder->post_disable = intel_ddi_post_disable;
2762 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2763 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2764
2765 intel_dig_port->port = port;
bcf53de4
SM		 2766 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2767 (DDI_BUF_PORT_REVERSAL |
2768 DDI_A_4_LANES);
00c09d70
PZ		 2769
2770 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2771 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2772 intel_encoder->cloneable = 0;
00c09d70
PZ		 2773 intel_encoder->hot_plug = intel_ddi_hot_plug;
2774
f68d697e
CW		 2775 if (init_dp) {
2776 if (!intel_ddi_init_dp_connector(intel_dig_port))
2777 goto err;
13cf5504 2778
f68d697e
CW		 2779 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2780 dev_priv->hpd_irq_port[port] = intel_dig_port;
2781 }
21a8e6a4 2782
311a2094
PZ		 2783 /* In theory we don't need the encoder->type check, but leave it just in
2784 * case we have some really bad VBTs... */
f68d697e
CW		 2785 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2786 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2787 goto err;
21a8e6a4 2788 }
f68d697e
CW		 2789
2790 return;
2791
2792err:
2793 drm_encoder_cleanup(encoder);
2794 kfree(intel_dig_port);
00c09d70 2795}
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