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drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
45244b87
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
31
10122051
JN		 32struct ddi_buf_trans {
33 u32 trans1; /* balance leg enable, de-emph level */
34 u32 trans2; /* vref sel, vswing */
f8896f5d 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 36};
37
97eeb872
VS		 38static const u8 index_to_dp_signal_levels[] = {
39 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
40 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
41 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
42 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
43 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
44 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
45 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
46 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
47 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
48 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
49};
50
45244b87
ED		 51/* HDMI/DVI modes ignore everything but the last 2 items. So we share
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
54 */
10122051 55static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 56 { 0x00FFFFFF, 0x0006000E, 0x0 },
57 { 0x00D75FFF, 0x0005000A, 0x0 },
58 { 0x00C30FFF, 0x00040006, 0x0 },
59 { 0x80AAAFFF, 0x000B0000, 0x0 },
60 { 0x00FFFFFF, 0x0005000A, 0x0 },
61 { 0x00D75FFF, 0x000C0004, 0x0 },
62 { 0x80C30FFF, 0x000B0000, 0x0 },
63 { 0x00FFFFFF, 0x00040006, 0x0 },
64 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 65};
66
10122051 67static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 68 { 0x00FFFFFF, 0x0007000E, 0x0 },
69 { 0x00D75FFF, 0x000F000A, 0x0 },
70 { 0x00C30FFF, 0x00060006, 0x0 },
71 { 0x00AAAFFF, 0x001E0000, 0x0 },
72 { 0x00FFFFFF, 0x000F000A, 0x0 },
73 { 0x00D75FFF, 0x00160004, 0x0 },
74 { 0x00C30FFF, 0x001E0000, 0x0 },
75 { 0x00FFFFFF, 0x00060006, 0x0 },
76 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 77};
78
10122051
JN		 79static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
80 /* Idx NT mV d T mV d db */
f8896f5d
DW		 81 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
82 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
83 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
84 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
85 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
86 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
87 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
88 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
89 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
90 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
91 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
92 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 93};
94
10122051 95static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 96 { 0x00FFFFFF, 0x00000012, 0x0 },
97 { 0x00EBAFFF, 0x00020011, 0x0 },
98 { 0x00C71FFF, 0x0006000F, 0x0 },
99 { 0x00AAAFFF, 0x000E000A, 0x0 },
100 { 0x00FFFFFF, 0x00020011, 0x0 },
101 { 0x00DB6FFF, 0x0005000F, 0x0 },
102 { 0x00BEEFFF, 0x000A000C, 0x0 },
103 { 0x00FFFFFF, 0x0005000F, 0x0 },
104 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 105};
106
10122051 107static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 108 { 0x00FFFFFF, 0x0007000E, 0x0 },
109 { 0x00D75FFF, 0x000E000A, 0x0 },
110 { 0x00BEFFFF, 0x00140006, 0x0 },
111 { 0x80B2CFFF, 0x001B0002, 0x0 },
112 { 0x00FFFFFF, 0x000E000A, 0x0 },
113 { 0x00DB6FFF, 0x00160005, 0x0 },
114 { 0x80C71FFF, 0x001A0002, 0x0 },
115 { 0x00F7DFFF, 0x00180004, 0x0 },
116 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 117};
118
10122051 119static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 120 { 0x00FFFFFF, 0x0001000E, 0x0 },
121 { 0x00D75FFF, 0x0004000A, 0x0 },
122 { 0x00C30FFF, 0x00070006, 0x0 },
123 { 0x00AAAFFF, 0x000C0000, 0x0 },
124 { 0x00FFFFFF, 0x0004000A, 0x0 },
125 { 0x00D75FFF, 0x00090004, 0x0 },
126 { 0x00C30FFF, 0x000C0000, 0x0 },
127 { 0x00FFFFFF, 0x00070006, 0x0 },
128 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 129};
130
10122051
JN		 131static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
132 /* Idx NT mV d T mV df db */
f8896f5d
DW		 133 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
134 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
135 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
136 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
137 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
138 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
139 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
140 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
141 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
142 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 143};
144
5f8b2531 145/* Skylake H and S */
7f88e3af 146static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
d7097cff 150 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
d7097cff 153 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 154 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 155 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 156};
157
f8896f5d
DW		 158/* Skylake U */
159static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 160 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 161 { 0x00005012, 0x00000088, 0x0 },
5ac90567 162 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 163 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 164 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 165 { 0x80005012, 0x000000C0, 0x1 },
166 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 167 { 0x00002016, 0x00000088, 0x0 },
d7097cff 168 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 169};
170
5f8b2531
RV		 171/* Skylake Y */
172static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 173 { 0x00000018, 0x000000A2, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
5ac90567 175 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 176 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 177 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 180 { 0x00000018, 0x00000088, 0x0 },
d7097cff 181 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 182};
183
0fdd4918
RV		 184/* Kabylake H and S */
185static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
186 { 0x00002016, 0x000000A0, 0x0 },
187 { 0x00005012, 0x0000009B, 0x0 },
188 { 0x00007011, 0x00000088, 0x0 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x00002016, 0x0000009B, 0x0 },
191 { 0x00005012, 0x00000088, 0x0 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000097, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
195};
196
197/* Kabylake U */
198static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
199 { 0x0000201B, 0x000000A1, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x0000201B, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00002016, 0x0000004F, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
208};
209
210/* Kabylake Y */
211static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
212 { 0x00001017, 0x000000A1, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000CD, 0x3 },
215 { 0x8000800F, 0x000000C0, 0x3 },
216 { 0x00001017, 0x0000009D, 0x0 },
217 { 0x80005012, 0x000000C0, 0x3 },
218 { 0x80007011, 0x000000C0, 0x3 },
219 { 0x00001017, 0x0000004C, 0x0 },
220 { 0x80005012, 0x000000C0, 0x3 },
221};
222
f8896f5d 223/*
0fdd4918 224 * Skylake/Kabylake H and S
f8896f5d
DW		 225 * eDP 1.4 low vswing translation parameters
226 */
7ad14a29 227static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 228 { 0x00000018, 0x000000A8, 0x0 },
229 { 0x00004013, 0x000000A9, 0x0 },
230 { 0x00007011, 0x000000A2, 0x0 },
231 { 0x00009010, 0x0000009C, 0x0 },
232 { 0x00000018, 0x000000A9, 0x0 },
233 { 0x00006013, 0x000000A2, 0x0 },
234 { 0x00007011, 0x000000A6, 0x0 },
235 { 0x00000018, 0x000000AB, 0x0 },
236 { 0x00007013, 0x0000009F, 0x0 },
237 { 0x00000018, 0x000000DF, 0x0 },
238};
239
240/*
0fdd4918 241 * Skylake/Kabylake U
f8896f5d
DW		 242 * eDP 1.4 low vswing translation parameters
243 */
244static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
245 { 0x00000018, 0x000000A8, 0x0 },
246 { 0x00004013, 0x000000A9, 0x0 },
247 { 0x00007011, 0x000000A2, 0x0 },
248 { 0x00009010, 0x0000009C, 0x0 },
249 { 0x00000018, 0x000000A9, 0x0 },
250 { 0x00006013, 0x000000A2, 0x0 },
251 { 0x00007011, 0x000000A6, 0x0 },
252 { 0x00002016, 0x000000AB, 0x0 },
253 { 0x00005013, 0x0000009F, 0x0 },
254 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 255};
256
f8896f5d 257/*
0fdd4918 258 * Skylake/Kabylake Y
f8896f5d
DW		 259 * eDP 1.4 low vswing translation parameters
260 */
5f8b2531 261static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 262 { 0x00000018, 0x000000A8, 0x0 },
263 { 0x00004013, 0x000000AB, 0x0 },
264 { 0x00007011, 0x000000A4, 0x0 },
265 { 0x00009010, 0x000000DF, 0x0 },
266 { 0x00000018, 0x000000AA, 0x0 },
267 { 0x00006013, 0x000000A4, 0x0 },
268 { 0x00007011, 0x0000009D, 0x0 },
269 { 0x00000018, 0x000000A0, 0x0 },
270 { 0x00006012, 0x000000DF, 0x0 },
271 { 0x00000018, 0x0000008A, 0x0 },
272};
7ad14a29 273
0fdd4918 274/* Skylake/Kabylake U, H and S */
7f88e3af 275static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 276 { 0x00000018, 0x000000AC, 0x0 },
277 { 0x00005012, 0x0000009D, 0x0 },
278 { 0x00007011, 0x00000088, 0x0 },
279 { 0x00000018, 0x000000A1, 0x0 },
280 { 0x00000018, 0x00000098, 0x0 },
281 { 0x00004013, 0x00000088, 0x0 },
2e78416e 282 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 283 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 284 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
285 { 0x80003015, 0x000000C0, 0x1 },
286 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 287};
288
0fdd4918 289/* Skylake/Kabylake Y */
5f8b2531 290static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 293 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 294 { 0x00000018, 0x000000A4, 0x0 },
295 { 0x00000018, 0x0000009D, 0x0 },
296 { 0x00004013, 0x00000080, 0x0 },
2e78416e 297 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 298 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 299 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
300 { 0x80003015, 0x000000C0, 0x3 },
301 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 302};
303
96fb9f9b 304struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 305 u8 margin; /* swing value */
306 u8 scale; /* scale value */
307 u8 enable; /* scale enable */
308 u8 deemphasis;
96fb9f9b
VK		 309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
043eaf36
VS		 313 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
043eaf36
VS		 327 { 26, 0, 0, 128, }, /* 0: 200 0 */
328 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, }, /* 2: 200 4 */
330 { 54, 0, 0, 69, }, /* 3: 200 6 */
331 { 32, 0, 0, 128, }, /* 4: 250 0 */
332 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, }, /* 6: 250 4 */
334 { 43, 0, 0, 128, }, /* 7: 300 0 */
335 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
043eaf36
VS		 344 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 354};
355
83fb7ab4 356struct cnl_ddi_buf_trans {
fb5f4e96
VS		 357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
83fb7ab4
RV		 362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
19b904f8
MN		 496struct icl_combo_phy_ddi_buf_trans {
497 u32 dw2_swing_select;
498 u32 dw2_swing_scalar;
499 u32 dw4_scaling;
500};
501
502/* Voltage Swing Programming for VccIO 0.85V for DP */
503static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
504 /* Voltage mV db */
505 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
506 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
507 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
508 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
509 { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
510 { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
511 { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
512 { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
513 { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
514 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
515};
516
517/* FIXME - After table is updated in Bspec */
518/* Voltage Swing Programming for VccIO 0.85V for eDP */
519static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
520 /* Voltage mV db */
521 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
522 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
523 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
524 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
525 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
526 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
527 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
528 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
529 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
530 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
531};
532
533/* Voltage Swing Programming for VccIO 0.95V for DP */
534static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
535 /* Voltage mV db */
536 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
537 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
538 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
539 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
540 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
541 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
542 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
543 { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
544 { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
545 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
546};
547
548/* FIXME - After table is updated in Bspec */
549/* Voltage Swing Programming for VccIO 0.95V for eDP */
550static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
551 /* Voltage mV db */
552 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
553 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
554 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
555 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
556 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
557 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
558 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
559 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
560 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
561 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
562};
563
564/* Voltage Swing Programming for VccIO 1.05V for DP */
565static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
566 /* Voltage mV db */
567 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
568 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
569 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
570 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
571 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
572 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
573 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
574 { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
575 { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
576 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
577};
578
579/* FIXME - After table is updated in Bspec */
580/* Voltage Swing Programming for VccIO 1.05V for eDP */
581static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
582 /* Voltage mV db */
583 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
584 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
585 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
586 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
587 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
588 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
589 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
590 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
591 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
592 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
593};
594
cd96bea7
MN		 595struct icl_mg_phy_ddi_buf_trans {
596 u32 cri_txdeemph_override_5_0;
597 u32 cri_txdeemph_override_11_6;
598 u32 cri_txdeemph_override_17_12;
599};
600
601static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
602 /* Voltage swing pre-emphasis */
603 { 0x0, 0x1B, 0x00 }, /* 0 0 */
604 { 0x0, 0x23, 0x08 }, /* 0 1 */
605 { 0x0, 0x2D, 0x12 }, /* 0 2 */
606 { 0x0, 0x00, 0x00 }, /* 0 3 */
607 { 0x0, 0x23, 0x00 }, /* 1 0 */
608 { 0x0, 0x2B, 0x09 }, /* 1 1 */
609 { 0x0, 0x2E, 0x11 }, /* 1 2 */
610 { 0x0, 0x2F, 0x00 }, /* 2 0 */
611 { 0x0, 0x33, 0x0C }, /* 2 1 */
612 { 0x0, 0x00, 0x00 }, /* 3 0 */
613};
614
a930acd9
VS		 615static const struct ddi_buf_trans *
616bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
617{
618 if (dev_priv->vbt.edp.low_vswing) {
619 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
620 return bdw_ddi_translations_edp;
621 } else {
622 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
623 return bdw_ddi_translations_dp;
624 }
625}
626
acee2998 627static const struct ddi_buf_trans *
78ab0bae 628skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 629{
0fdd4918 630 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 631 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 632 return skl_y_ddi_translations_dp;
0fdd4918 633 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 634 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 635 return skl_u_ddi_translations_dp;
f8896f5d 636 } else {
f8896f5d 637 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 638 return skl_ddi_translations_dp;
f8896f5d 639 }
f8896f5d
DW		 640}
641
0fdd4918
RV		 642static const struct ddi_buf_trans *
643kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
644{
dfdaa566 645 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
0fdd4918
RV		 646 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
647 return kbl_y_ddi_translations_dp;
da411a48 648 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 649 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
650 return kbl_u_ddi_translations_dp;
651 } else {
652 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
653 return kbl_ddi_translations_dp;
654 }
655}
656
acee2998 657static const struct ddi_buf_trans *
78ab0bae 658skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 659{
06411f08 660 if (dev_priv->vbt.edp.low_vswing) {
dfdaa566 661 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 662 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 663 return skl_y_ddi_translations_edp;
da411a48
RV		 664 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
665 IS_CFL_ULT(dev_priv)) {
f8896f5d 666 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 667 return skl_u_ddi_translations_edp;
f8896f5d 668 } else {
f8896f5d 669 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 670 return skl_ddi_translations_edp;
f8896f5d
DW		 671 }
672 }
cd1101cb 673
da411a48 674 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 675 return kbl_get_buf_trans_dp(dev_priv, n_entries);
676 else
677 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 678}
679
680static const struct ddi_buf_trans *
78ab0bae 681skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 682{
dfdaa566 683 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
5f8b2531 684 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 685 return skl_y_ddi_translations_hdmi;
f8896f5d 686 } else {
f8896f5d 687 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 688 return skl_ddi_translations_hdmi;
f8896f5d 689 }
f8896f5d
DW		 690}
691
edba48fd
VS		 692static int skl_buf_trans_num_entries(enum port port, int n_entries)
693{
694 /* Only DDIA and DDIE can select the 10th register with DP */
695 if (port == PORT_A || port == PORT_E)
696 return min(n_entries, 10);
697 else
698 return min(n_entries, 9);
699}
700
d8fe2c7f
VS		 701static const struct ddi_buf_trans *
702intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 703 enum port port, int *n_entries)
d8fe2c7f
VS		 704{
705 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 706 const struct ddi_buf_trans *ddi_translations =
707 kbl_get_buf_trans_dp(dev_priv, n_entries);
708 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
709 return ddi_translations;
d8fe2c7f 710 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 711 const struct ddi_buf_trans *ddi_translations =
712 skl_get_buf_trans_dp(dev_priv, n_entries);
713 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
714 return ddi_translations;
d8fe2c7f
VS		 715 } else if (IS_BROADWELL(dev_priv)) {
716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
717 return bdw_ddi_translations_dp;
718 } else if (IS_HASWELL(dev_priv)) {
719 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
720 return hsw_ddi_translations_dp;
721 }
722
723 *n_entries = 0;
724 return NULL;
725}
726
727static const struct ddi_buf_trans *
728intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 729 enum port port, int *n_entries)
d8fe2c7f
VS		 730{
731 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 732 const struct ddi_buf_trans *ddi_translations =
733 skl_get_buf_trans_edp(dev_priv, n_entries);
734 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
735 return ddi_translations;
d8fe2c7f
VS		 736 } else if (IS_BROADWELL(dev_priv)) {
737 return bdw_get_buf_trans_edp(dev_priv, n_entries);
738 } else if (IS_HASWELL(dev_priv)) {
739 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
740 return hsw_ddi_translations_dp;
741 }
742
743 *n_entries = 0;
744 return NULL;
745}
746
747static const struct ddi_buf_trans *
748intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
749 int *n_entries)
750{
751 if (IS_BROADWELL(dev_priv)) {
752 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
753 return bdw_ddi_translations_fdi;
754 } else if (IS_HASWELL(dev_priv)) {
755 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
756 return hsw_ddi_translations_fdi;
757 }
758
759 *n_entries = 0;
760 return NULL;
761}
762
975786ee
VS		 763static const struct ddi_buf_trans *
764intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
765 int *n_entries)
766{
767 if (IS_GEN9_BC(dev_priv)) {
768 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
769 } else if (IS_BROADWELL(dev_priv)) {
770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
771 return bdw_ddi_translations_hdmi;
772 } else if (IS_HASWELL(dev_priv)) {
773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
774 return hsw_ddi_translations_hdmi;
775 }
776
777 *n_entries = 0;
778 return NULL;
779}
780
7d4f37b5
VS		 781static const struct bxt_ddi_buf_trans *
782bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
783{
784 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
785 return bxt_ddi_translations_dp;
786}
787
788static const struct bxt_ddi_buf_trans *
789bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
790{
791 if (dev_priv->vbt.edp.low_vswing) {
792 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
793 return bxt_ddi_translations_edp;
794 }
795
796 return bxt_get_buf_trans_dp(dev_priv, n_entries);
797}
798
799static const struct bxt_ddi_buf_trans *
800bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
801{
802 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
803 return bxt_ddi_translations_hdmi;
804}
805
cf3e0fb4
RV		 806static const struct cnl_ddi_buf_trans *
807cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
808{
809 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
810
811 if (voltage == VOLTAGE_INFO_0_85V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
813 return cnl_ddi_translations_hdmi_0_85V;
814 } else if (voltage == VOLTAGE_INFO_0_95V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
816 return cnl_ddi_translations_hdmi_0_95V;
817 } else if (voltage == VOLTAGE_INFO_1_05V) {
818 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
819 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 820 } else {
821 *n_entries = 1; /* shut up gcc */
cf3e0fb4 822 MISSING_CASE(voltage);
83482ca3 823 }
cf3e0fb4
RV		 824 return NULL;
825}
826
827static const struct cnl_ddi_buf_trans *
828cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
829{
830 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
831
832 if (voltage == VOLTAGE_INFO_0_85V) {
833 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
834 return cnl_ddi_translations_dp_0_85V;
835 } else if (voltage == VOLTAGE_INFO_0_95V) {
836 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
837 return cnl_ddi_translations_dp_0_95V;
838 } else if (voltage == VOLTAGE_INFO_1_05V) {
839 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
840 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 841 } else {
842 *n_entries = 1; /* shut up gcc */
cf3e0fb4 843 MISSING_CASE(voltage);
83482ca3 844 }
cf3e0fb4
RV		 845 return NULL;
846}
847
848static const struct cnl_ddi_buf_trans *
849cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
850{
851 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
852
853 if (dev_priv->vbt.edp.low_vswing) {
854 if (voltage == VOLTAGE_INFO_0_85V) {
855 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
856 return cnl_ddi_translations_edp_0_85V;
857 } else if (voltage == VOLTAGE_INFO_0_95V) {
858 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
859 return cnl_ddi_translations_edp_0_95V;
860 } else if (voltage == VOLTAGE_INFO_1_05V) {
861 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
862 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 863 } else {
864 *n_entries = 1; /* shut up gcc */
cf3e0fb4 865 MISSING_CASE(voltage);
83482ca3 866 }
cf3e0fb4
RV		 867 return NULL;
868 } else {
869 return cnl_get_buf_trans_dp(dev_priv, n_entries);
870 }
871}
872
fb5c8e9d
MN		 873static const struct icl_combo_phy_ddi_buf_trans *
874icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
875 int type, int *n_entries)
876{
877 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
878
879 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
880 switch (voltage) {
881 case VOLTAGE_INFO_0_85V:
882 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
883 return icl_combo_phy_ddi_translations_edp_0_85V;
884 case VOLTAGE_INFO_0_95V:
885 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
886 return icl_combo_phy_ddi_translations_edp_0_95V;
887 case VOLTAGE_INFO_1_05V:
888 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
889 return icl_combo_phy_ddi_translations_edp_1_05V;
890 default:
891 MISSING_CASE(voltage);
892 return NULL;
893 }
894 } else {
895 switch (voltage) {
896 case VOLTAGE_INFO_0_85V:
897 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
898 return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
899 case VOLTAGE_INFO_0_95V:
900 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
901 return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
902 case VOLTAGE_INFO_1_05V:
903 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
904 return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
905 default:
906 MISSING_CASE(voltage);
907 return NULL;
908 }
909 }
910}
911
8d8bb85e
VS		 912static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
913{
d02ace87 914 int n_entries, level, default_entry;
8d8bb85e 915
d02ace87 916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 917
dccc7228 918 if (IS_ICELAKE(dev_priv)) {
176597a1 919 if (intel_port_is_combophy(dev_priv, port))
dccc7228
MN		 920 icl_get_combo_buf_trans(dev_priv, port,
921 INTEL_OUTPUT_HDMI, &n_entries);
922 else
923 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
924 default_entry = n_entries - 1;
925 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 926 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
927 default_entry = n_entries - 1;
043eaf36 928 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 929 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
930 default_entry = n_entries - 1;
bf503556 931 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 932 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
933 default_entry = 8;
8d8bb85e 934 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 935 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
936 default_entry = 7;
8d8bb85e 937 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 938 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
939 default_entry = 6;
8d8bb85e
VS		 940 } else {
941 WARN(1, "ddi translation table missing\n");
975786ee 942 return 0;
8d8bb85e
VS		 943 }
944
945 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 946 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
947 level = default_entry;
8d8bb85e 948
d02ace87 949 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 950 return 0;
d02ace87
VS		 951 if (WARN_ON_ONCE(level >= n_entries))
952 level = n_entries - 1;
21b39d2a 953
d02ace87 954 return level;
8d8bb85e
VS		 955}
956
e58623cb
AR		 957/*
958 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 959 * values in advance. This function programs the correct values for
960 * DP/eDP/FDI use cases.
45244b87 961 */
3a6d84e6
VS		 962static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
963 const struct intel_crtc_state *crtc_state)
45244b87 964{
6a7e4f99 965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 966 u32 iboost_bit = 0;
7d1c42e6 967 int i, n_entries;
0fce04c8 968 enum port port = encoder->port;
10122051 969 const struct ddi_buf_trans *ddi_translations;
e58623cb 970
3a6d84e6
VS		 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
973 &n_entries);
974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 976 &n_entries);
3a6d84e6 977 else
edba48fd 978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 979 &n_entries);
e58623cb 980
edba48fd
VS		 981 /* If we're boosting the current, set bit 31 of trans1 */
982 if (IS_GEN9_BC(dev_priv) &&
983 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 985
7d1c42e6 986 for (i = 0; i < n_entries; i++) {
9712e688
VS		 987 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
988 ddi_translations[i].trans1 | iboost_bit);
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
990 ddi_translations[i].trans2);
45244b87 991 }
32bdc400
VS		 992}
993
994/*
995 * Starting with Haswell, DDI port buffers must be programmed with correct
996 * values in advance. This function programs the correct values for
997 * HDMI/DVI use cases.
998 */
7ea79333 999static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 1000 int level)
32bdc400
VS		 1001{
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003 u32 iboost_bit = 0;
d02ace87 1004 int n_entries;
0fce04c8 1005 enum port port = encoder->port;
d02ace87 1006 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 1007
d02ace87 1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 1009
d02ace87 1010 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 1011 return;
d02ace87
VS		 1012 if (WARN_ON_ONCE(level >= n_entries))
1013 level = n_entries - 1;
21b39d2a 1014
975786ee
VS		 1015 /* If we're boosting the current, set bit 31 of trans1 */
1016 if (IS_GEN9_BC(dev_priv) &&
1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 1019
6acab15a 1020 /* Entry 9 is for HDMI: */
ed9c77d2 1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 1022 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 1024 ddi_translations[level].trans2);
45244b87
ED		 1025}
1026
248138b5
PZ		 1027static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028 enum port port)
1029{
f0f59a00 1030 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 1031 int i;
1032
3449ca85 1033 for (i = 0; i < 16; i++) {
248138b5
PZ		 1034 udelay(1);
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036 return;
1037 }
1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039}
c82e4d26 1040
5f88a9c6 1041static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 1042{
0823eb9c 1043 switch (pll->info->id) {
c856052a
ACO		 1044 case DPLL_ID_WRPLL1:
1045 return PORT_CLK_SEL_WRPLL1;
1046 case DPLL_ID_WRPLL2:
1047 return PORT_CLK_SEL_WRPLL2;
1048 case DPLL_ID_SPLL:
1049 return PORT_CLK_SEL_SPLL;
1050 case DPLL_ID_LCPLL_810:
1051 return PORT_CLK_SEL_LCPLL_810;
1052 case DPLL_ID_LCPLL_1350:
1053 return PORT_CLK_SEL_LCPLL_1350;
1054 case DPLL_ID_LCPLL_2700:
1055 return PORT_CLK_SEL_LCPLL_2700;
1056 default:
0823eb9c 1057 MISSING_CASE(pll->info->id);
c856052a
ACO		 1058 return PORT_CLK_SEL_NONE;
1059 }
1060}
1061
c27e917e 1062static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
0e5fa646 1063 const struct intel_crtc_state *crtc_state)
c27e917e 1064{
0e5fa646
ML		 1065 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1066 int clock = crtc_state->port_clock;
c27e917e
PZ		 1067 const enum intel_dpll_id id = pll->info->id;
1068
1069 switch (id) {
1070 default:
1071 MISSING_CASE(id);
f0d759f0 1072 /* fall through */
c27e917e
PZ		 1073 case DPLL_ID_ICL_DPLL0:
1074 case DPLL_ID_ICL_DPLL1:
1075 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1076 case DPLL_ID_ICL_TBTPLL:
1077 switch (clock) {
1078 case 162000:
1079 return DDI_CLK_SEL_TBT_162;
1080 case 270000:
1081 return DDI_CLK_SEL_TBT_270;
1082 case 540000:
1083 return DDI_CLK_SEL_TBT_540;
1084 case 810000:
1085 return DDI_CLK_SEL_TBT_810;
1086 default:
1087 MISSING_CASE(clock);
1088 break;
1089 }
c27e917e
PZ		 1090 case DPLL_ID_ICL_MGPLL1:
1091 case DPLL_ID_ICL_MGPLL2:
1092 case DPLL_ID_ICL_MGPLL3:
1093 case DPLL_ID_ICL_MGPLL4:
1094 return DDI_CLK_SEL_MG;
1095 }
1096}
1097
c82e4d26
ED		 1098/* Starting with Haswell, different DDI ports can work in FDI mode for
1099 * connection to the PCH-located connectors. For this, it is necessary to train
1100 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101 *
1102 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104 * DDI A (which is used for eDP)
1105 */
1106
dc4a1094
ACO		 1107void hsw_fdi_link_train(struct intel_crtc *crtc,
1108 const struct intel_crtc_state *crtc_state)
c82e4d26 1109{
4cbe4b2b 1110 struct drm_device *dev = crtc->base.dev;
fac5e23e 1111 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1112 struct intel_encoder *encoder;
c856052a 1113 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1114
4cbe4b2b 1115 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1116 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1118 }
1119
04945641
PZ		 1120 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121 * mode set "sequence for CRT port" document:
1122 * - TP1 to TP2 time with the default value
1123 * - FDI delay to 90h
8693a824
DL		 1124 *
1125 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1126 */
eede3b53 1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1128 FDI_RX_PWRDN_LANE0_VAL(2) |
1129 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131 /* Enable the PCH Receiver FDI PLL */
3e68320e 1132 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1133 FDI_RX_PLL_ENABLE |
dc4a1094 1134 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1137 udelay(220);
1138
1139 /* Switch from Rawclk to PCDclk */
1140 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1142
1143 /* Configure Port Clock Select */
dc4a1094 1144 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1145 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1147
1148 /* Start the training iterating through available voltages and emphasis,
1149 * testing each value twice. */
10122051 1150 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1151 /* Configure DP_TP_CTL with auto-training */
1152 I915_WRITE(DP_TP_CTL(PORT_E),
1153 DP_TP_CTL_FDI_AUTOTRAIN |
1154 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155 DP_TP_CTL_LINK_TRAIN_PAT1 |
1156 DP_TP_CTL_ENABLE);
1157
876a8cdf
DL		 1158 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159 * DDI E does not support port reversal, the functionality is
1160 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161 * port reversal bit */
c82e4d26 1162 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1163 DDI_BUF_CTL_ENABLE |
dc4a1094 1164 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1165 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1167
1168 udelay(600);
1169
04945641 1170 /* Program PCH FDI Receiver TU */
eede3b53 1171 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1172
1173 /* Enable PCH FDI Receiver with auto-training */
1174 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1175 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1177
1178 /* Wait for FDI receiver lane calibration */
1179 udelay(30);
1180
1181 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1186
1187 /* Wait for FDI auto training time */
1188 udelay(5);
c82e4d26
ED		 1189
1190 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1192 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1193 break;
1194 }
c82e4d26 1195
a308ccb3
VS		 1196 /*
1197 * Leave things enabled even if we failed to train FDI.
1198 * Results in less fireworks from the state checker.
1199 */
1200 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201 DRM_ERROR("FDI link training failed!\n");
1202 break;
c82e4d26 1203 }
04945641 1204
5b421c57
VS		 1205 rx_ctl_val &= ~FDI_RX_ENABLE;
1206 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
248138b5
PZ		 1209 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210 temp &= ~DDI_BUF_CTL_ENABLE;
1211 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
04945641 1214 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1215 temp = I915_READ(DP_TP_CTL(PORT_E));
1216 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1222
04945641 1223 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1224 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1225 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1227 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1229 }
1230
a308ccb3
VS		 1231 /* Enable normal pixel sending for FDI */
1232 I915_WRITE(DP_TP_CTL(PORT_E),
1233 DP_TP_CTL_FDI_AUTOTRAIN |
1234 DP_TP_CTL_LINK_TRAIN_NORMAL |
1235 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236 DP_TP_CTL_ENABLE);
c82e4d26 1237}
0e72a5b5 1238
d7c530b2 1239static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1240{
1241 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242 struct intel_digital_port *intel_dig_port =
1243 enc_to_dig_port(&encoder->base);
1244
1245 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1246 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1247 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1248}
1249
8d9ddbcb 1250static struct intel_encoder *
e9ce1a62 1251intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1252{
e9ce1a62 1253 struct drm_device *dev = crtc->base.dev;
1524e93e 1254 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1255 int num_encoders = 0;
1256
1524e93e
SS		 1257 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258 ret = encoder;
8d9ddbcb
PZ		 1259 num_encoders++;
1260 }
1261
1262 if (num_encoders != 1)
84f44ce7 1263 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1264 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1265
1266 BUG_ON(ret == NULL);
1267 return ret;
1268}
1269
1c0b85c5 1270#define LC_FREQ 2700
1c0b85c5 1271
f0f59a00
VS		 1272static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273 i915_reg_t reg)
11578553
JB		 1274{
1275 int refclk = LC_FREQ;
1276 int n, p, r;
1277 u32 wrpll;
1278
1279 wrpll = I915_READ(reg);
114fe488
DV		 1280 switch (wrpll & WRPLL_PLL_REF_MASK) {
1281 case WRPLL_PLL_SSC:
1282 case WRPLL_PLL_NON_SSC:
11578553
JB		 1283 /*
1284 * We could calculate spread here, but our checking
1285 * code only cares about 5% accuracy, and spread is a max of
1286 * 0.5% downspread.
1287 */
1288 refclk = 135;
1289 break;
114fe488 1290 case WRPLL_PLL_LCPLL:
11578553
JB		 1291 refclk = LC_FREQ;
1292 break;
1293 default:
1294 WARN(1, "bad wrpll refclk\n");
1295 return 0;
1296 }
1297
1298 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
20f0ec16
JB		 1302 /* Convert to KHz, p & r have a fixed point portion */
1303 return (refclk * n * 100) / (p * r);
11578553
JB		 1304}
1305
540e732c 1306static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1307 enum intel_dpll_id pll_id)
540e732c 1308{
f0f59a00 1309 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1310 uint32_t cfgcr1_val, cfgcr2_val;
1311 uint32_t p0, p1, p2, dco_freq;
1312
2952cd6f
RV		 1313 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314 cfgcr2_reg = DPLL_CFGCR2(pll_id);
540e732c
S		 1315
1316 cfgcr1_val = I915_READ(cfgcr1_reg);
1317 cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1323 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324 else
1325 p1 = 1;
1326
1327
1328 switch (p0) {
1329 case DPLL_CFGCR2_PDIV_1:
1330 p0 = 1;
1331 break;
1332 case DPLL_CFGCR2_PDIV_2:
1333 p0 = 2;
1334 break;
1335 case DPLL_CFGCR2_PDIV_3:
1336 p0 = 3;
1337 break;
1338 case DPLL_CFGCR2_PDIV_7:
1339 p0 = 7;
1340 break;
1341 }
1342
1343 switch (p2) {
1344 case DPLL_CFGCR2_KDIV_5:
1345 p2 = 5;
1346 break;
1347 case DPLL_CFGCR2_KDIV_2:
1348 p2 = 2;
1349 break;
1350 case DPLL_CFGCR2_KDIV_3:
1351 p2 = 3;
1352 break;
1353 case DPLL_CFGCR2_KDIV_1:
1354 p2 = 1;
1355 break;
1356 }
1357
1358 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361 1000) / 0x8000;
1362
1363 return dco_freq / (p0 * p1 * p2 * 5);
1364}
1365
a9701a89 1366static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1367 enum intel_dpll_id pll_id)
a9701a89
RV		 1368{
1369 uint32_t cfgcr0, cfgcr1;
1370 uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
5428bf5a
AH		 1372 if (INTEL_GEN(dev_priv) >= 11) {
1373 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375 } else {
1376 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378 }
a9701a89
RV		 1379
1380 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386 else
1387 p1 = 1;
1388
1389
1390 switch (p0) {
1391 case DPLL_CFGCR1_PDIV_2:
1392 p0 = 2;
1393 break;
1394 case DPLL_CFGCR1_PDIV_3:
1395 p0 = 3;
1396 break;
1397 case DPLL_CFGCR1_PDIV_5:
1398 p0 = 5;
1399 break;
1400 case DPLL_CFGCR1_PDIV_7:
1401 p0 = 7;
1402 break;
1403 }
1404
1405 switch (p2) {
1406 case DPLL_CFGCR1_KDIV_1:
1407 p2 = 1;
1408 break;
1409 case DPLL_CFGCR1_KDIV_2:
1410 p2 = 2;
1411 break;
1412 case DPLL_CFGCR1_KDIV_4:
1413 p2 = 4;
1414 break;
1415 }
1416
9f9d594d 1417 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89
RV		 1418
1419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1422 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1423
0e005888
PZ		 1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425 return 0;
1426
a9701a89
RV		 1427 return dco_freq / (p0 * p1 * p2 * 5);
1428}
1429
7b19f544
MN		 1430static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431 enum port port)
1432{
1433 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434
1435 switch (val) {
1436 case DDI_CLK_SEL_NONE:
1437 return 0;
1438 case DDI_CLK_SEL_TBT_162:
1439 return 162000;
1440 case DDI_CLK_SEL_TBT_270:
1441 return 270000;
1442 case DDI_CLK_SEL_TBT_540:
1443 return 540000;
1444 case DDI_CLK_SEL_TBT_810:
1445 return 810000;
1446 default:
1447 MISSING_CASE(val);
1448 return 0;
1449 }
1450}
1451
1452static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453 enum port port)
1454{
1455 u32 mg_pll_div0, mg_clktop_hsclkctl;
1456 u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457 u64 tmp;
1458
1459 refclk = dev_priv->cdclk.hw.ref;
1460
1461 mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462 mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463
1464 m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465 m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466 m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467 (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469
1470 switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472 div1 = 2;
1473 break;
1474 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475 div1 = 3;
1476 break;
1477 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478 div1 = 5;
1479 break;
1480 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481 div1 = 7;
1482 break;
1483 default:
1484 MISSING_CASE(mg_clktop_hsclkctl);
1485 return 0;
1486 }
1487
1488 div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490 /* div2 value of 0 is same as 1 means no div */
1491 if (div2 == 0)
1492 div2 = 1;
1493
1494 /*
1495 * Adjust the original formula to delay the division by 2^22 in order to
1496 * minimize possible rounding errors.
1497 */
1498 tmp = (u64)m1 * m2_int * refclk +
1499 (((u64)m1 * m2_frac * refclk) >> 22);
1500 tmp = div_u64(tmp, 5 * div1 * div2);
1501
1502 return tmp;
1503}
1504
398a017e
VS		 1505static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1506{
1507 int dotclock;
1508
1509 if (pipe_config->has_pch_encoder)
1510 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511 &pipe_config->fdi_m_n);
37a5650b 1512 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1513 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514 &pipe_config->dp_m_n);
1515 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516 dotclock = pipe_config->port_clock * 2 / 3;
1517 else
1518 dotclock = pipe_config->port_clock;
1519
33b7f3ee 1520 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
b22ca995
SS		 1521 dotclock *= 2;
1522
398a017e
VS		 1523 if (pipe_config->pixel_multiplier)
1524 dotclock /= pipe_config->pixel_multiplier;
1525
1526 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1527}
540e732c 1528
51c83cfa
MN		 1529static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530 struct intel_crtc_state *pipe_config)
1531{
1532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533 enum port port = encoder->port;
1534 int link_clock = 0;
1535 uint32_t pll_id;
1536
1537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
176597a1 1538 if (intel_port_is_combophy(dev_priv, port)) {
51c83cfa
MN		 1539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541 else
1542 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1543 pll_id);
1544 } else {
7b19f544
MN		 1545 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547 else
1548 link_clock = icl_calc_mg_pll_link(dev_priv, port);
51c83cfa
MN		 1549 }
1550
1551 pipe_config->port_clock = link_clock;
1552 ddi_dotclock_get(pipe_config);
1553}
1554
a9701a89
RV		 1555static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556 struct intel_crtc_state *pipe_config)
1557{
1558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1559 int link_clock = 0;
2952cd6f
RV		 1560 uint32_t cfgcr0;
1561 enum intel_dpll_id pll_id;
a9701a89
RV		 1562
1563 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1564
1565 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1566
1567 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1569 } else {
1570 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572 switch (link_clock) {
1573 case DPLL_CFGCR0_LINK_RATE_810:
1574 link_clock = 81000;
1575 break;
1576 case DPLL_CFGCR0_LINK_RATE_1080:
1577 link_clock = 108000;
1578 break;
1579 case DPLL_CFGCR0_LINK_RATE_1350:
1580 link_clock = 135000;
1581 break;
1582 case DPLL_CFGCR0_LINK_RATE_1620:
1583 link_clock = 162000;
1584 break;
1585 case DPLL_CFGCR0_LINK_RATE_2160:
1586 link_clock = 216000;
1587 break;
1588 case DPLL_CFGCR0_LINK_RATE_2700:
1589 link_clock = 270000;
1590 break;
1591 case DPLL_CFGCR0_LINK_RATE_3240:
1592 link_clock = 324000;
1593 break;
1594 case DPLL_CFGCR0_LINK_RATE_4050:
1595 link_clock = 405000;
1596 break;
1597 default:
1598 WARN(1, "Unsupported link rate\n");
1599 break;
1600 }
1601 link_clock *= 2;
1602 }
1603
1604 pipe_config->port_clock = link_clock;
1605
1606 ddi_dotclock_get(pipe_config);
1607}
1608
540e732c 1609static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1610 struct intel_crtc_state *pipe_config)
540e732c 1611{
fac5e23e 1612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c 1613 int link_clock = 0;
2952cd6f
RV		 1614 uint32_t dpll_ctl1;
1615 enum intel_dpll_id pll_id;
540e732c 1616
2952cd6f 1617 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1618
1619 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1620
2952cd6f
RV		 1621 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
540e732c 1623 } else {
2952cd6f
RV		 1624 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
540e732c
S		 1626
1627 switch (link_clock) {
71cd8423 1628 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1629 link_clock = 81000;
1630 break;
71cd8423 1631 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1632 link_clock = 108000;
1633 break;
71cd8423 1634 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1635 link_clock = 135000;
1636 break;
71cd8423 1637 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1638 link_clock = 162000;
1639 break;
71cd8423 1640 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1641 link_clock = 216000;
1642 break;
71cd8423 1643 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1644 link_clock = 270000;
1645 break;
1646 default:
1647 WARN(1, "Unsupported link rate\n");
1648 break;
1649 }
1650 link_clock *= 2;
1651 }
1652
1653 pipe_config->port_clock = link_clock;
1654
398a017e 1655 ddi_dotclock_get(pipe_config);
540e732c
S		 1656}
1657
3d51278a 1658static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1659 struct intel_crtc_state *pipe_config)
11578553 1660{
fac5e23e 1661 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1662 int link_clock = 0;
1663 u32 val, pll;
1664
c856052a 1665 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1666 switch (val & PORT_CLK_SEL_MASK) {
1667 case PORT_CLK_SEL_LCPLL_810:
1668 link_clock = 81000;
1669 break;
1670 case PORT_CLK_SEL_LCPLL_1350:
1671 link_clock = 135000;
1672 break;
1673 case PORT_CLK_SEL_LCPLL_2700:
1674 link_clock = 270000;
1675 break;
1676 case PORT_CLK_SEL_WRPLL1:
01403de3 1677 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1678 break;
1679 case PORT_CLK_SEL_WRPLL2:
01403de3 1680 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1681 break;
1682 case PORT_CLK_SEL_SPLL:
1683 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684 if (pll == SPLL_PLL_FREQ_810MHz)
1685 link_clock = 81000;
1686 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687 link_clock = 135000;
1688 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689 link_clock = 270000;
1690 else {
1691 WARN(1, "bad spll freq\n");
1692 return;
1693 }
1694 break;
1695 default:
1696 WARN(1, "bad port clock sel\n");
1697 return;
1698 }
1699
1700 pipe_config->port_clock = link_clock * 2;
1701
398a017e 1702 ddi_dotclock_get(pipe_config);
11578553
JB		 1703}
1704
bb911536 1705static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
977bb38d 1706{
aa610dcb 1707 struct intel_dpll_hw_state *state;
9e2c8475 1708 struct dpll clock;
aa610dcb
ID		 1709
1710 /* For DDI ports we always use a shared PLL. */
bb911536 1711 if (WARN_ON(!crtc_state->shared_dpll))
aa610dcb
ID		 1712 return 0;
1713
bb911536 1714 state = &crtc_state->dpll_hw_state;
aa610dcb
ID		 1715
1716 clock.m1 = 2;
1717 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1723
1724 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1725}
1726
1727static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1728 struct intel_crtc_state *pipe_config)
977bb38d 1729{
bb911536 1730 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
977bb38d 1731
398a017e 1732 ddi_dotclock_get(pipe_config);
977bb38d
S		 1733}
1734
35686a44
VS		 1735static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736 struct intel_crtc_state *pipe_config)
3d51278a 1737{
0853723b 1738 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1739
fdec4df4
RV		 1740 if (IS_ICELAKE(dev_priv))
1741 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1742 else if (IS_CANNONLAKE(dev_priv))
1743 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1744 else if (IS_GEN9_LP(dev_priv))
1745 bxt_ddi_clock_get(encoder, pipe_config);
1746 else if (IS_GEN9_BC(dev_priv))
1747 skl_ddi_clock_get(encoder, pipe_config);
1748 else if (INTEL_GEN(dev_priv) <= 8)
1749 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1750}
1751
3dc38eea 1752void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1753{
3dc38eea 1754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1755 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1756 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1757 u32 temp;
dae84799 1758
5448f53f
VS		 1759 if (!intel_crtc_has_dp_encoder(crtc_state))
1760 return;
4d1de975 1761
5448f53f
VS		 1762 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1763
1764 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1765
1766 if (crtc_state->limited_color_range)
1767 temp |= TRANS_MSA_CEA_RANGE;
1768
5448f53f
VS		 1769 switch (crtc_state->pipe_bpp) {
1770 case 18:
1771 temp |= TRANS_MSA_6_BPC;
1772 break;
1773 case 24:
1774 temp |= TRANS_MSA_8_BPC;
1775 break;
1776 case 30:
1777 temp |= TRANS_MSA_10_BPC;
1778 break;
1779 case 36:
1780 temp |= TRANS_MSA_12_BPC;
1781 break;
1782 default:
1783 MISSING_CASE(crtc_state->pipe_bpp);
1784 break;
dae84799 1785 }
5448f53f 1786
668b6c17
SS		 1787 /*
1788 * As per DP 1.2 spec section 2.3.4.3 while sending
1789 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1790 * colorspace information. The output colorspace encoding is BT601.
1791 */
1792 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1793 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
5448f53f 1794 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1795}
1796
3dc38eea
ACO		 1797void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1798 bool state)
0e32b39c 1799{
3dc38eea 1800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1801 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1802 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c 1803 uint32_t temp;
7e732cac 1804
0e32b39c
DA		 1805 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1806 if (state == true)
1807 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1808 else
1809 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1810 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1811}
1812
3dc38eea 1813void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1814{
3dc38eea 1815 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1816 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1818 enum pipe pipe = crtc->pipe;
3dc38eea 1819 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1820 enum port port = encoder->port;
8d9ddbcb
PZ		 1821 uint32_t temp;
1822
ad80a810
PZ		 1823 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1824 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1825 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1826
3dc38eea 1827 switch (crtc_state->pipe_bpp) {
dfcef252 1828 case 18:
ad80a810 1829 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1830 break;
1831 case 24:
ad80a810 1832 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1833 break;
1834 case 30:
ad80a810 1835 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1836 break;
1837 case 36:
ad80a810 1838 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1839 break;
1840 default:
4e53c2e0 1841 BUG();
dfcef252 1842 }
72662e10 1843
3dc38eea 1844 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1845 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1846 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1847 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1848
e6f0bfc4
PZ		 1849 if (cpu_transcoder == TRANSCODER_EDP) {
1850 switch (pipe) {
1851 case PIPE_A:
c7670b10
PZ		 1852 /* On Haswell, can only use the always-on power well for
1853 * eDP when not using the panel fitter, and when not
1854 * using motion blur mitigation (which we don't
1855 * support). */
772c2a51 1856 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1857 (crtc_state->pch_pfit.enabled ||
1858 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1859 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1860 else
1861 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1862 break;
1863 case PIPE_B:
1864 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1865 break;
1866 case PIPE_C:
1867 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1868 break;
1869 default:
1870 BUG();
1871 break;
1872 }
1873 }
1874
742745f1 1875 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1876 if (crtc_state->has_hdmi_sink)
ad80a810 1877 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1878 else
ad80a810 1879 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1880
1881 if (crtc_state->hdmi_scrambling)
1882 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1883 if (crtc_state->hdmi_high_tmds_clock_ratio)
1884 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1885 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1886 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1887 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1888 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1889 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1890 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1891 } else {
742745f1
VS		 1892 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1893 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1894 }
1895
ad80a810 1896 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1897}
72662e10 1898
90c3e219 1899void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1900{
90c3e219
CT		 1901 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1903 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1904 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1905 uint32_t val = I915_READ(reg);
1906
0e32b39c 1907 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1908 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1909 I915_WRITE(reg, val);
90c3e219
CT		 1910
1911 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1912 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1913 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1914 /* Quirk time at 100ms for reliable operation */
1915 msleep(100);
1916 }
72662e10
ED		 1917}
1918
2320175f
SP		 1919int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1920 bool enable)
1921{
1922 struct drm_device *dev = intel_encoder->base.dev;
1923 struct drm_i915_private *dev_priv = to_i915(dev);
1924 enum pipe pipe = 0;
1925 int ret = 0;
1926 uint32_t tmp;
1927
1928 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1929 intel_encoder->power_domain)))
1930 return -ENXIO;
1931
1932 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1933 ret = -EIO;
1934 goto out;
1935 }
1936
1937 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1938 if (enable)
1939 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1940 else
1941 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1942 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1943out:
1944 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1945 return ret;
1946}
1947
bcbc889b
PZ		 1948bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1949{
1950 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1951 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1952 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1953 int type = intel_connector->base.connector_type;
0fce04c8 1954 enum port port = encoder->port;
bcbc889b
PZ		 1955 enum pipe pipe = 0;
1956 enum transcoder cpu_transcoder;
1957 uint32_t tmp;
e27daab4 1958 bool ret;
bcbc889b 1959
79f255a0 1960 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1961 encoder->power_domain))
882244a3
PZ		 1962 return false;
1963
1524e93e 1964 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1965 ret = false;
1966 goto out;
1967 }
bcbc889b
PZ		 1968
1969 if (port == PORT_A)
1970 cpu_transcoder = TRANSCODER_EDP;
1971 else
1a240d4d 1972 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1973
1974 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1975
1976 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1977 case TRANS_DDI_MODE_SELECT_HDMI:
1978 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1979 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1980 break;
bcbc889b
PZ		 1981
1982 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1983 ret = type == DRM_MODE_CONNECTOR_eDP ||
1984 type == DRM_MODE_CONNECTOR_DisplayPort;
1985 break;
1986
0e32b39c
DA		 1987 case TRANS_DDI_MODE_SELECT_DP_MST:
1988 /* if the transcoder is in MST state then
1989 * connector isn't connected */
e27daab4
ID		 1990 ret = false;
1991 break;
bcbc889b
PZ		 1992
1993 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1994 ret = type == DRM_MODE_CONNECTOR_VGA;
1995 break;
bcbc889b
PZ		 1996
1997 default:
e27daab4
ID		 1998 ret = false;
1999 break;
bcbc889b 2000 }
e27daab4
ID		 2001
2002out:
1524e93e 2003 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 2004
2005 return ret;
bcbc889b
PZ		 2006}
2007
9199c322
ID		 2008static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2009 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 2010{
2011 struct drm_device *dev = encoder->base.dev;
fac5e23e 2012 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 2013 enum port port = encoder->port;
3657e927 2014 enum pipe p;
85234cdc 2015 u32 tmp;
9199c322
ID		 2016 u8 mst_pipe_mask;
2017
2018 *pipe_mask = 0;
2019 *is_dp_mst = false;
85234cdc 2020
79f255a0
ACO		 2021 if (!intel_display_power_get_if_enabled(dev_priv,
2022 encoder->power_domain))
9199c322 2023 return;
e27daab4 2024
fe43d3f5 2025 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 2026 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 2027 goto out;
85234cdc 2028
ad80a810
PZ		 2029 if (port == PORT_A) {
2030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2031
ad80a810 2032 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 2033 default:
2034 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2035 /* fallthrough */
ad80a810
PZ		 2036 case TRANS_DDI_EDP_INPUT_A_ON:
2037 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 2038 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 2039 break;
2040 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 2041 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 2042 break;
2043 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 2044 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 2045 break;
2046 }
2047
e27daab4
ID		 2048 goto out;
2049 }
0e32b39c 2050
9199c322 2051 mst_pipe_mask = 0;
3657e927 2052 for_each_pipe(dev_priv, p) {
9199c322 2053 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 2054
2055 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 2056
9199c322
ID		 2057 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2058 continue;
e27daab4 2059
9199c322
ID		 2060 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2061 TRANS_DDI_MODE_SELECT_DP_MST)
2062 mst_pipe_mask |= BIT(p);
e27daab4 2063
9199c322 2064 *pipe_mask |= BIT(p);
85234cdc
DV		 2065 }
2066
9199c322
ID		 2067 if (!*pipe_mask)
2068 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2069 port_name(port));
2070
2071 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2072 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2073 port_name(port), *pipe_mask);
2074 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2075 }
2076
2077 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2078 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2079 port_name(port), *pipe_mask, mst_pipe_mask);
2080 else
2081 *is_dp_mst = mst_pipe_mask;
85234cdc 2082
e27daab4 2083out:
9199c322 2084 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2085 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2086 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2087 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2088 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2089 DRM_ERROR("Port %c enabled but PHY powered down? "
2090 "(PHY_CTL %08x)\n", port_name(port), tmp);
2091 }
2092
79f255a0 2093 intel_display_power_put(dev_priv, encoder->power_domain);
9199c322 2094}
e27daab4 2095
9199c322
ID		 2096bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2097 enum pipe *pipe)
2098{
2099 u8 pipe_mask;
2100 bool is_mst;
2101
2102 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2103
2104 if (is_mst || !pipe_mask)
2105 return false;
2106
2107 *pipe = ffs(pipe_mask) - 1;
2108
2109 return true;
85234cdc
DV		 2110}
2111
52528055 2112static inline enum intel_display_power_domain
bdaa29b6 2113intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2114{
9e3b5ce9 2115 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2116 * DC states enabled at the same time, while for driver initiated AUX
2117 * transfers we need the same AUX IOs to be powered but with DC states
2118 * disabled. Accordingly use the AUX power domain here which leaves DC
2119 * states enabled.
2120 * However, for non-A AUX ports the corresponding non-EDP transcoders
2121 * would have already enabled power well 2 and DC_OFF. This means we can
2122 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2123 * specific AUX_IO reference without powering up any extra wells.
2124 * Note that PSR is enabled only on Port A even though this function
2125 * returns the correct domain for other ports too.
2126 */
563d22a0 2127 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2128 intel_aux_power_domain(dig_port);
52528055
ID		 2129}
2130
2131static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2132 struct intel_crtc_state *crtc_state)
62b69566 2133{
8e4a3ad9 2134 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2135 struct intel_digital_port *dig_port;
52528055 2136 u64 domains;
62b69566 2137
52528055
ID		 2138 /*
2139 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2140 * happen since fake-MST encoders don't set their get_power_domains()
2141 * hook.
52528055
ID		 2142 */
2143 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
b79ebe74
ID		 2144 return 0;
2145
2146 dig_port = enc_to_dig_port(&encoder->base);
2147 domains = BIT_ULL(dig_port->ddi_io_power_domain);
52528055 2148
8e4a3ad9
ID		 2149 /*
2150 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2151 * ports.
2152 */
2153 if (intel_crtc_has_dp_encoder(crtc_state) ||
2154 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6 2155 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
52528055
ID		 2156
2157 return domains;
62b69566
ACO		 2158}
2159
3dc38eea 2160void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2161{
3dc38eea 2162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2163 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2164 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2165 enum port port = encoder->port;
3dc38eea 2166 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2167
bb523fc0
PZ		 2168 if (cpu_transcoder != TRANSCODER_EDP)
2169 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2170 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2171}
2172
3dc38eea 2173void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2174{
3dc38eea
ACO		 2175 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2176 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2177
bb523fc0
PZ		 2178 if (cpu_transcoder != TRANSCODER_EDP)
2179 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2180 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2181}
2182
a7d8dbc0
VS		 2183static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2184 enum port port, uint8_t iboost)
f8896f5d 2185{
a7d8dbc0
VS		 2186 u32 tmp;
2187
2188 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2189 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2190 if (iboost)
2191 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2192 else
2193 tmp |= BALANCE_LEG_DISABLE(port);
2194 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2195}
2196
081dfcfa
VS		 2197static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2198 int level, enum intel_output_type type)
a7d8dbc0
VS		 2199{
2200 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2202 enum port port = encoder->port;
f8896f5d 2203 uint8_t iboost;
f8896f5d 2204
081dfcfa
VS		 2205 if (type == INTEL_OUTPUT_HDMI)
2206 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2207 else
2208 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2209
081dfcfa
VS		 2210 if (iboost == 0) {
2211 const struct ddi_buf_trans *ddi_translations;
2212 int n_entries;
2213
2214 if (type == INTEL_OUTPUT_HDMI)
2215 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2216 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2217 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2218 else
edba48fd 2219 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2220
21b39d2a
VS		 2221 if (WARN_ON_ONCE(!ddi_translations))
2222 return;
2223 if (WARN_ON_ONCE(level >= n_entries))
2224 level = n_entries - 1;
2225
081dfcfa 2226 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2227 }
2228
2229 /* Make sure that the requested I_boost is valid */
2230 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2231 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2232 return;
2233 }
2234
a7d8dbc0 2235 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2236
a7d8dbc0
VS		 2237 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2238 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2239}
2240
7d4f37b5
VS		 2241static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2242 int level, enum intel_output_type type)
96fb9f9b 2243{
7d4f37b5 2244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2245 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2246 enum port port = encoder->port;
043eaf36 2247 int n_entries;
7d4f37b5
VS		 2248
2249 if (type == INTEL_OUTPUT_HDMI)
2250 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2251 else if (type == INTEL_OUTPUT_EDP)
2252 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2253 else
2254 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2255
21b39d2a
VS		 2256 if (WARN_ON_ONCE(!ddi_translations))
2257 return;
2258 if (WARN_ON_ONCE(level >= n_entries))
2259 level = n_entries - 1;
2260
b6e08203
ACO		 2261 bxt_ddi_phy_set_signal_level(dev_priv, port,
2262 ddi_translations[level].margin,
2263 ddi_translations[level].scale,
2264 ddi_translations[level].enable,
2265 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2266}
2267
ffe5111e
VS		 2268u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2269{
2270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
edba48fd 2271 enum port port = encoder->port;
ffe5111e
VS		 2272 int n_entries;
2273
36cf89f5 2274 if (IS_ICELAKE(dev_priv)) {
176597a1 2275 if (intel_port_is_combophy(dev_priv, port))
36cf89f5
MN		 2276 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2277 &n_entries);
2278 else
2279 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2280 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2281 if (encoder->type == INTEL_OUTPUT_EDP)
2282 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2283 else
2284 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2285 } else if (IS_GEN9_LP(dev_priv)) {
2286 if (encoder->type == INTEL_OUTPUT_EDP)
2287 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2288 else
2289 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2290 } else {
2291 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2292 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2293 else
edba48fd 2294 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2295 }
ffe5111e
VS		 2296
2297 if (WARN_ON(n_entries < 1))
2298 n_entries = 1;
2299 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2300 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2301
2302 return index_to_dp_signal_levels[n_entries - 1] &
2303 DP_TRAIN_VOLTAGE_SWING_MASK;
2304}
2305
4718a365
VS		 2306/*
2307 * We assume that the full set of pre-emphasis values can be
2308 * used on all DDI platforms. Should that change we need to
2309 * rethink this code.
2310 */
2311u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2312{
2313 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2315 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2317 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2319 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2321 default:
2322 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2323 }
2324}
2325
f3cf4ba4
VS		 2326static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2327 int level, enum intel_output_type type)
cf54ca8b 2328{
f3cf4ba4 2329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2330 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2331 enum port port = encoder->port;
f3cf4ba4
VS		 2332 int n_entries, ln;
2333 u32 val;
cf54ca8b 2334
f3cf4ba4 2335 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2336 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2337 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2338 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2339 else
2340 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2341
21b39d2a 2342 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2343 return;
21b39d2a 2344 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2345 level = n_entries - 1;
cf54ca8b
RV		 2346
2347 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2348 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2349 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2350 val |= SCALING_MODE_SEL(2);
2351 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2352
2353 /* Program PORT_TX_DW2 */
2354 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2355 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2356 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2357 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2358 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2359 /* Rcomp scalar is fixed as 0x98 for every table entry */
2360 val |= RCOMP_SCALAR(0x98);
2361 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2362
20303eb4 2363 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2364 /* We cannot write to GRP. It would overrite individual loadgen */
2365 for (ln = 0; ln < 4; ln++) {
2366 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 2367 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2368 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2369 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2370 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2371 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2372 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2373 }
2374
20303eb4 2375 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2376 /* All DW5 values are fixed for every table entry */
2377 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2378 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2379 val |= RTERM_SELECT(6);
2380 val |= TAP3_DISABLE;
2381 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2382
20303eb4 2383 /* Program PORT_TX_DW7 */
cf54ca8b 2384 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2385 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2386 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2387 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2388}
2389
f3cf4ba4
VS		 2390static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2391 int level, enum intel_output_type type)
cf54ca8b 2392{
0091abc3 2393 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2394 enum port port = encoder->port;
f3cf4ba4 2395 int width, rate, ln;
cf54ca8b 2396 u32 val;
0091abc3 2397
f3cf4ba4 2398 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2399 width = 4;
f3cf4ba4 2400 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2401 } else {
f3cf4ba4
VS		 2402 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2403
2404 width = intel_dp->lane_count;
2405 rate = intel_dp->link_rate;
0091abc3 2406 }
cf54ca8b
RV		 2407
2408 /*
2409 * 1. If port type is eDP or DP,
2410 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2411 * else clear to 0b.
2412 */
2413 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2414 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2415 val |= COMMON_KEEPER_EN;
2416 else
2417 val &= ~COMMON_KEEPER_EN;
2418 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2419
2420 /* 2. Program loadgen select */
2421 /*
0091abc3
CT		 2422 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2423 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2424 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2425 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2426 */
0091abc3
CT		 2427 for (ln = 0; ln <= 3; ln++) {
2428 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2429 val &= ~LOADGEN_SELECT;
2430
a8e45a1c
NM		 2431 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2432 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2433 val |= LOADGEN_SELECT;
2434 }
2435 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2436 }
cf54ca8b
RV		 2437
2438 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2439 val = I915_READ(CNL_PORT_CL1CM_DW5);
2440 val |= SUS_CLOCK_CONFIG;
2441 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2442
2443 /* 4. Clear training enable to change swing values */
2444 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2445 val &= ~TX_TRAINING_EN;
2446 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2447
2448 /* 5. Program swing and de-emphasis */
f3cf4ba4 2449 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2450
2451 /* 6. Set training enable to trigger update */
2452 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2453 val |= TX_TRAINING_EN;
2454 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2455}
2456
fb5c8e9d
MN		 2457static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2458 u32 level, enum port port, int type)
2459{
2460 const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2461 u32 n_entries, val;
2462 int ln;
2463
2464 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2465 &n_entries);
2466 if (!ddi_translations)
2467 return;
2468
2469 if (level >= n_entries) {
2470 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2471 level = n_entries - 1;
2472 }
2473
2474 /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2475 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2476 val &= ~RTERM_SELECT_MASK;
2477 val |= RTERM_SELECT(0x6);
2478 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2479
2480 /* Program PORT_TX_DW5 */
2481 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2482 /* Set DisableTap2 and DisableTap3 if MIPI DSI
2483 * Clear DisableTap2 and DisableTap3 for all other Ports
2484 */
2485 if (type == INTEL_OUTPUT_DSI) {
2486 val |= TAP2_DISABLE;
2487 val |= TAP3_DISABLE;
2488 } else {
2489 val &= ~TAP2_DISABLE;
2490 val &= ~TAP3_DISABLE;
2491 }
2492 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2493
2494 /* Program PORT_TX_DW2 */
2495 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2496 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2497 RCOMP_SCALAR_MASK);
2498 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2499 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2500 /* Program Rcomp scalar for every table entry */
2501 val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2502 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2503
2504 /* Program PORT_TX_DW4 */
2505 /* We cannot write to GRP. It would overwrite individual loadgen. */
2506 for (ln = 0; ln <= 3; ln++) {
2507 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2508 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2509 CURSOR_COEFF_MASK);
2510 val |= ddi_translations[level].dw4_scaling;
2511 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2512 }
2513}
2514
2515static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2516 u32 level,
2517 enum intel_output_type type)
2518{
2519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2520 enum port port = encoder->port;
2521 int width = 0;
2522 int rate = 0;
2523 u32 val;
2524 int ln = 0;
2525
2526 if (type == INTEL_OUTPUT_HDMI) {
2527 width = 4;
2528 /* Rate is always < than 6GHz for HDMI */
2529 } else {
2530 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2531
2532 width = intel_dp->lane_count;
2533 rate = intel_dp->link_rate;
2534 }
2535
2536 /*
2537 * 1. If port type is eDP or DP,
2538 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2539 * else clear to 0b.
2540 */
2541 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2542 if (type == INTEL_OUTPUT_HDMI)
2543 val &= ~COMMON_KEEPER_EN;
2544 else
2545 val |= COMMON_KEEPER_EN;
2546 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2547
2548 /* 2. Program loadgen select */
2549 /*
2550 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2551 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2552 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2553 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2554 */
2555 for (ln = 0; ln <= 3; ln++) {
2556 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2557 val &= ~LOADGEN_SELECT;
2558
2559 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2560 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2561 val |= LOADGEN_SELECT;
2562 }
2563 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2564 }
2565
2566 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2567 val = I915_READ(ICL_PORT_CL_DW5(port));
2568 val |= SUS_CLOCK_CONFIG;
2569 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2570
2571 /* 4. Clear training enable to change swing values */
2572 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2573 val &= ~TX_TRAINING_EN;
2574 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2575
2576 /* 5. Program swing and de-emphasis */
2577 icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2578
2579 /* 6. Set training enable to trigger update */
2580 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2581 val |= TX_TRAINING_EN;
2582 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2583}
2584
07685c82
MN		 2585static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2586 int link_clock,
2587 u32 level)
2588{
2589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2590 enum port port = encoder->port;
2591 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2592 u32 n_entries, val;
2593 int ln;
2594
2595 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2596 ddi_translations = icl_mg_phy_ddi_translations;
2597 /* The table does not have values for level 3 and level 9. */
2598 if (level >= n_entries || level == 3 || level == 9) {
2599 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2600 level, n_entries - 2);
2601 level = n_entries - 2;
2602 }
2603
2604 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2605 for (ln = 0; ln < 2; ln++) {
2606 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2607 val &= ~CRI_USE_FS32;
2608 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2609
2610 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2611 val &= ~CRI_USE_FS32;
2612 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2613 }
2614
2615 /* Program MG_TX_SWINGCTRL with values from vswing table */
2616 for (ln = 0; ln < 2; ln++) {
2617 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2618 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2619 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2620 ddi_translations[level].cri_txdeemph_override_17_12);
2621 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2622
2623 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2624 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2625 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2626 ddi_translations[level].cri_txdeemph_override_17_12);
2627 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2628 }
2629
2630 /* Program MG_TX_DRVCTRL with values from vswing table */
2631 for (ln = 0; ln < 2; ln++) {
2632 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2633 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2634 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2635 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2636 ddi_translations[level].cri_txdeemph_override_5_0) |
2637 CRI_TXDEEMPH_OVERRIDE_11_6(
2638 ddi_translations[level].cri_txdeemph_override_11_6) |
2639 CRI_TXDEEMPH_OVERRIDE_EN;
2640 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2641
2642 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2643 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2644 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2645 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2646 ddi_translations[level].cri_txdeemph_override_5_0) |
2647 CRI_TXDEEMPH_OVERRIDE_11_6(
2648 ddi_translations[level].cri_txdeemph_override_11_6) |
2649 CRI_TXDEEMPH_OVERRIDE_EN;
2650 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2651
2652 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2653 }
2654
2655 /*
2656 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2657 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2658 * values from table for which TX1 and TX2 enabled.
2659 */
2660 for (ln = 0; ln < 2; ln++) {
2661 val = I915_READ(MG_CLKHUB(port, ln));
2662 if (link_clock < 300000)
2663 val |= CFG_LOW_RATE_LKREN_EN;
2664 else
2665 val &= ~CFG_LOW_RATE_LKREN_EN;
2666 I915_WRITE(MG_CLKHUB(port, ln), val);
2667 }
2668
2669 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2670 for (ln = 0; ln < 2; ln++) {
2671 val = I915_READ(MG_TX1_DCC(port, ln));
2672 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2673 if (link_clock <= 500000) {
2674 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2675 } else {
2676 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2677 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2678 }
2679 I915_WRITE(MG_TX1_DCC(port, ln), val);
2680
2681 val = I915_READ(MG_TX2_DCC(port, ln));
2682 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2683 if (link_clock <= 500000) {
2684 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2685 } else {
2686 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2687 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2688 }
2689 I915_WRITE(MG_TX2_DCC(port, ln), val);
2690 }
2691
2692 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2693 for (ln = 0; ln < 2; ln++) {
2694 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2695 val |= CRI_CALCINIT;
2696 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2697
2698 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2699 val |= CRI_CALCINIT;
2700 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2701 }
2702}
2703
2704static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2705 int link_clock,
2706 u32 level,
fb5c8e9d
MN		 2707 enum intel_output_type type)
2708{
176597a1 2709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2710 enum port port = encoder->port;
2711
176597a1 2712 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2713 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2714 else
07685c82 2715 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2716}
2717
f8896f5d
DW		 2718static uint32_t translate_signal_level(int signal_levels)
2719{
97eeb872 2720 int i;
f8896f5d 2721
97eeb872
VS		 2722 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2723 if (index_to_dp_signal_levels[i] == signal_levels)
2724 return i;
f8896f5d
DW		 2725 }
2726
97eeb872
VS		 2727 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2728 signal_levels);
2729
2730 return 0;
f8896f5d
DW		 2731}
2732
1b6e2fd2
RV		 2733static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2734{
2735 uint8_t train_set = intel_dp->train_set[0];
2736 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2737 DP_TRAIN_PRE_EMPHASIS_MASK);
2738
2739 return translate_signal_level(signal_levels);
2740}
2741
d509af6c 2742u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2743{
2744 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2745 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2746 struct intel_encoder *encoder = &dport->base;
d02ace87 2747 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2748
fb5c8e9d 2749 if (IS_ICELAKE(dev_priv))
07685c82
MN		 2750 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2751 level, encoder->type);
fb5c8e9d 2752 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2753 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2754 else
7d4f37b5 2755 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2756
2757 return 0;
2758}
2759
2760uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2761{
2762 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2763 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2764 struct intel_encoder *encoder = &dport->base;
d02ace87 2765 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2766
b976dc53 2767 if (IS_GEN9_BC(dev_priv))
081dfcfa 2768 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2769
f8896f5d
DW		 2770 return DDI_BUF_TRANS_SELECT(level);
2771}
2772
bb1c7edc
MK		 2773static inline
2774uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2775 enum port port)
2776{
2777 if (intel_port_is_combophy(dev_priv, port)) {
2778 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2779 } else if (intel_port_is_tc(dev_priv, port)) {
2780 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2781
2782 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2783 }
2784
2785 return 0;
2786}
2787
c27e917e
PZ		 2788void icl_map_plls_to_ports(struct drm_crtc *crtc,
2789 struct intel_crtc_state *crtc_state,
2790 struct drm_atomic_state *old_state)
2791{
2792 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2793 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2794 struct drm_connector_state *conn_state;
2795 struct drm_connector *conn;
2796 int i;
2797
2798 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2799 struct intel_encoder *encoder =
2800 to_intel_encoder(conn_state->best_encoder);
c46ef57d 2801 enum port port;
c27e917e
PZ		 2802 uint32_t val;
2803
2804 if (conn_state->crtc != crtc)
2805 continue;
2806
c46ef57d 2807 port = encoder->port;
c27e917e
PZ		 2808 mutex_lock(&dev_priv->dpll_lock);
2809
2810 val = I915_READ(DPCLKA_CFGCR0_ICL);
bb1c7edc 2811 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2812
176597a1 2813 if (intel_port_is_combophy(dev_priv, port)) {
c27e917e
PZ		 2814 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2815 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2816 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2817 POSTING_READ(DPCLKA_CFGCR0_ICL);
2818 }
2819
bb1c7edc 2820 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
c27e917e
PZ		 2821 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2822
2823 mutex_unlock(&dev_priv->dpll_lock);
2824 }
2825}
2826
2827void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2828 struct intel_crtc_state *crtc_state,
2829 struct drm_atomic_state *old_state)
2830{
2831 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2832 struct drm_connector_state *old_conn_state;
2833 struct drm_connector *conn;
2834 int i;
2835
2836 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2837 struct intel_encoder *encoder =
2838 to_intel_encoder(old_conn_state->best_encoder);
c46ef57d 2839 enum port port;
c27e917e
PZ		 2840
2841 if (old_conn_state->crtc != crtc)
2842 continue;
2843
c46ef57d 2844 port = encoder->port;
c27e917e
PZ		 2845 mutex_lock(&dev_priv->dpll_lock);
2846 I915_WRITE(DPCLKA_CFGCR0_ICL,
2847 I915_READ(DPCLKA_CFGCR0_ICL) |
bb1c7edc 2848 icl_dpclka_cfgcr0_clk_off(dev_priv, port));
c27e917e
PZ		 2849 mutex_unlock(&dev_priv->dpll_lock);
2850 }
2851}
2852
70332ac5
ID		 2853void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2854{
2855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2856 u32 val;
70332ac5 2857 enum port port = encoder->port;
30f5ccfa
ID		 2858 bool clk_enabled;
2859
2860 /*
2861 * In case of DP MST, we sanitize the primary encoder only, not the
2862 * virtual ones.
2863 */
2864 if (encoder->type == INTEL_OUTPUT_DP_MST)
2865 return;
2866
2867 val = I915_READ(DPCLKA_CFGCR0_ICL);
2868 clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2869
2870 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2871 u8 pipe_mask;
2872 bool is_mst;
2873
2874 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2875 /*
2876 * In the unlikely case that BIOS enables DP in MST mode, just
2877 * warn since our MST HW readout is incomplete.
2878 */
2879 if (WARN_ON(is_mst))
2880 return;
2881 }
70332ac5
ID		 2882
2883 if (clk_enabled == !!encoder->base.crtc)
2884 return;
2885
2886 /*
2887 * Punt on the case now where clock is disabled, but the encoder is
2888 * enabled, something else is really broken then.
2889 */
2890 if (WARN_ON(!clk_enabled))
2891 return;
2892
2893 DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n",
2894 port_name(port));
2895 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2896 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2897}
2898
d7c530b2 2899static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2900 const struct intel_crtc_state *crtc_state)
6441ab5f 2901{
e404ba8d 2902 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2903 enum port port = encoder->port;
555e38d2 2904 uint32_t val;
0e5fa646 2905 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2906
c856052a
ACO		 2907 if (WARN_ON(!pll))
2908 return;
2909
04bf68bb 2910 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2911
c27e917e 2912 if (IS_ICELAKE(dev_priv)) {
176597a1 2913 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2914 I915_WRITE(DDI_CLK_SEL(port),
0e5fa646 2915 icl_pll_to_ddi_pll_sel(encoder, crtc_state));
c27e917e 2916 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2917 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2918 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2919 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2920 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2921 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2922
555e38d2
RV		 2923 /*
2924 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2925 * This step and the step before must be done with separate
2926 * register writes.
2927 */
2928 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2929 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2930 I915_WRITE(DPCLKA_CFGCR0, val);
2931 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2932 /* DDI -> PLL mapping */
efa80add
S		 2933 val = I915_READ(DPLL_CTRL2);
2934
2935 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2936 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2937 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2938 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2939
2940 I915_WRITE(DPLL_CTRL2, val);
5416d871 2941
c56b89f1 2942 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2943 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2944 }
8edcda12
RV		 2945
2946 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2947}
2948
6b8506d5
VS		 2949static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2950{
2951 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2952 enum port port = encoder->port;
6b8506d5 2953
c27e917e 2954 if (IS_ICELAKE(dev_priv)) {
176597a1 2955 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2956 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2957 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2958 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2959 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2960 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2961 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2962 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2963 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2964 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2965 }
6b8506d5
VS		 2966}
2967
cb9ff519
ID		 2968static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2969{
2970 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2971 enum port port = dig_port->base.port;
2972 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2973 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2974 u32 val;
2975 int i;
2976
2977 if (tc_port == PORT_TC_NONE)
2978 return;
2979
2980 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2981 val = I915_READ(mg_regs[i]);
2982 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2983 MG_DP_MODE_CFG_TRPWR_GATING |
2984 MG_DP_MODE_CFG_CLNPWR_GATING |
2985 MG_DP_MODE_CFG_DIGPWR_GATING |
2986 MG_DP_MODE_CFG_GAONPWR_GATING;
2987 I915_WRITE(mg_regs[i], val);
2988 }
2989
2990 val = I915_READ(MG_MISC_SUS0(tc_port));
2991 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2992 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2993 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2994 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2995 MG_MISC_SUS0_CFG_TRPWR_GATING |
2996 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2997 MG_MISC_SUS0_CFG_DGPWR_GATING;
2998 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2999}
3000
3001static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3002{
3003 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3004 enum port port = dig_port->base.port;
3005 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3006 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
3007 u32 val;
3008 int i;
3009
3010 if (tc_port == PORT_TC_NONE)
3011 return;
3012
3013 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
3014 val = I915_READ(mg_regs[i]);
3015 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3016 MG_DP_MODE_CFG_TRPWR_GATING |
3017 MG_DP_MODE_CFG_CLNPWR_GATING |
3018 MG_DP_MODE_CFG_DIGPWR_GATING |
3019 MG_DP_MODE_CFG_GAONPWR_GATING);
3020 I915_WRITE(mg_regs[i], val);
3021 }
3022
3023 val = I915_READ(MG_MISC_SUS0(tc_port));
3024 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3025 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3026 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3027 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3028 MG_MISC_SUS0_CFG_TRPWR_GATING |
3029 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3030 MG_MISC_SUS0_CFG_DGPWR_GATING);
3031 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3032}
3033
93b662d3
ID		 3034static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3035{
3036 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3037 enum port port = intel_dig_port->base.port;
3038 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3039 u32 ln0, ln1, lane_info;
3040
3041 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
3042 return;
3043
3044 ln0 = I915_READ(MG_DP_MODE(port, 0));
3045 ln1 = I915_READ(MG_DP_MODE(port, 1));
3046
3047 switch (intel_dig_port->tc_type) {
3048 case TC_PORT_TYPEC:
3049 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3050 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3051
3052 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3053 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3054 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3055
3056 switch (lane_info) {
3057 case 0x1:
3058 case 0x4:
3059 break;
3060 case 0x2:
3061 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3062 break;
3063 case 0x3:
3064 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3065 MG_DP_MODE_CFG_DP_X2_MODE;
3066 break;
3067 case 0x8:
3068 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3069 break;
3070 case 0xC:
3071 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3072 MG_DP_MODE_CFG_DP_X2_MODE;
3073 break;
3074 case 0xF:
3075 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3076 MG_DP_MODE_CFG_DP_X2_MODE;
3077 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3078 MG_DP_MODE_CFG_DP_X2_MODE;
3079 break;
3080 default:
3081 MISSING_CASE(lane_info);
3082 }
3083 break;
3084
3085 case TC_PORT_LEGACY:
3086 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3087 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3088 break;
3089
3090 default:
3091 MISSING_CASE(intel_dig_port->tc_type);
3092 return;
3093 }
3094
3095 I915_WRITE(MG_DP_MODE(port, 0), ln0);
3096 I915_WRITE(MG_DP_MODE(port, 1), ln1);
3097}
3098
ba88d153 3099static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3100 const struct intel_crtc_state *crtc_state,
3101 const struct drm_connector_state *conn_state)
e404ba8d 3102{
ba88d153
MN		 3103 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3104 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3105 enum port port = encoder->port;
62b69566 3106 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3107 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3108 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3109
45e0327e 3110 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3111
45e0327e
VS		 3112 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3113 crtc_state->lane_count, is_mst);
680b71c2
VS		 3114
3115 intel_edp_panel_on(intel_dp);
32bdc400 3116
0e5fa646 3117 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3118
3119 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3120
93b662d3 3121 icl_program_mg_dp_mode(dig_port);
bc334d91 3122 icl_disable_phy_clock_gating(dig_port);
340a44be 3123
fb5c8e9d 3124 if (IS_ICELAKE(dev_priv))
07685c82
MN		 3125 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3126 level, encoder->type);
fb5c8e9d 3127 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3128 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3129 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3130 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3131 else
3a6d84e6 3132 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3133
ba88d153 3134 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3135 if (!is_mst)
3136 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3137 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3138 true);
ba88d153
MN		 3139 intel_dp_start_link_train(intel_dp);
3140 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3141 intel_dp_stop_link_train(intel_dp);
afb2c443 3142
bc334d91
PZ		 3143 icl_enable_phy_clock_gating(dig_port);
3144
2b5cf4ef
ID		 3145 if (!is_mst)
3146 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3147
3148 intel_dsc_enable(encoder, crtc_state);
ba88d153 3149}
901c2daf 3150
ba88d153 3151static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3152 const struct intel_crtc_state *crtc_state,
45e0327e 3153 const struct drm_connector_state *conn_state)
ba88d153 3154{
f99be1b3
VS		 3155 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3156 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3158 enum port port = encoder->port;
ba88d153 3159 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3160 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3161
ba88d153 3162 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3163 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3164
3165 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3166
93b662d3 3167 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3168 icl_disable_phy_clock_gating(dig_port);
3169
fb5c8e9d 3170 if (IS_ICELAKE(dev_priv))
07685c82
MN		 3171 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3172 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3173 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3174 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3175 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3176 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3177 else
7ea79333 3178 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3179
cb9ff519
ID		 3180 icl_enable_phy_clock_gating(dig_port);
3181
2f7460a7 3182 if (IS_GEN9_BC(dev_priv))
081dfcfa 3183 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3184
c7373764
ID		 3185 intel_ddi_enable_pipe_clock(crtc_state);
3186
790ea70c 3187 intel_dig_port->set_infoframes(encoder,
45e0327e 3188 crtc_state->has_infoframe,
f99be1b3 3189 crtc_state, conn_state);
ba88d153 3190}
32bdc400 3191
1524e93e 3192static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3193 const struct intel_crtc_state *crtc_state,
5f88a9c6 3194 const struct drm_connector_state *conn_state)
ba88d153 3195{
45e0327e
VS		 3196 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3198 enum pipe pipe = crtc->pipe;
30cf6db8 3199
1939ba51
VS		 3200 /*
3201 * When called from DP MST code:
3202 * - conn_state will be NULL
3203 * - encoder will be the main encoder (ie. mst->primary)
3204 * - the main connector associated with this port
3205 * won't be active or linked to a crtc
3206 * - crtc_state will be the state of the first stream to
3207 * be activated on this port, and it may not be the same
3208 * stream that will be deactivated last, but each stream
3209 * should have a state that is identical when it comes to
3210 * the DP link parameteres
3211 */
3212
45e0327e 3213 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1
JN		 3214
3215 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3216
06c812d7 3217 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3218 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3219 } else {
3220 struct intel_lspcon *lspcon =
3221 enc_to_intel_lspcon(&encoder->base);
3222
45e0327e 3223 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3224 if (lspcon->active) {
3225 struct intel_digital_port *dig_port =
3226 enc_to_dig_port(&encoder->base);
3227
3228 dig_port->set_infoframes(encoder,
3229 crtc_state->has_infoframe,
3230 crtc_state, conn_state);
3231 }
3232 }
6441ab5f
PZ		 3233}
3234
e725f645
VS		 3235static void intel_disable_ddi_buf(struct intel_encoder *encoder)
3236{
3237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3238 enum port port = encoder->port;
e725f645
VS		 3239 bool wait = false;
3240 u32 val;
3241
3242 val = I915_READ(DDI_BUF_CTL(port));
3243 if (val & DDI_BUF_CTL_ENABLE) {
3244 val &= ~DDI_BUF_CTL_ENABLE;
3245 I915_WRITE(DDI_BUF_CTL(port), val);
3246 wait = true;
3247 }
3248
3249 val = I915_READ(DP_TP_CTL(port));
3250 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3251 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3252 I915_WRITE(DP_TP_CTL(port), val);
3253
3254 if (wait)
3255 intel_wait_ddi_buf_idle(dev_priv, port);
3256}
3257
f45f3da7
VS		 3258static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3259 const struct intel_crtc_state *old_crtc_state,
3260 const struct drm_connector_state *old_conn_state)
6441ab5f 3261{
f45f3da7
VS		 3262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3263 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3264 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3265 bool is_mst = intel_crtc_has_type(old_crtc_state,
3266 INTEL_OUTPUT_DP_MST);
2886e93f 3267
2b5cf4ef
ID		 3268 if (!is_mst) {
3269 intel_ddi_disable_pipe_clock(old_crtc_state);
3270 /*
3271 * Power down sink before disabling the port, otherwise we end
3272 * up getting interrupts from the sink on detecting link loss.
3273 */
be1c63c8 3274 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3275 }
c5f93fcf 3276
f45f3da7 3277 intel_disable_ddi_buf(encoder);
7618138d 3278
f45f3da7
VS		 3279 intel_edp_panel_vdd_on(intel_dp);
3280 intel_edp_panel_off(intel_dp);
a836bdf9 3281
f45f3da7 3282 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
c5f93fcf 3283
f45f3da7
VS		 3284 intel_ddi_clk_disable(encoder);
3285}
c5f93fcf 3286
f45f3da7
VS		 3287static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3288 const struct intel_crtc_state *old_crtc_state,
3289 const struct drm_connector_state *old_conn_state)
3290{
3291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3292 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3293 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3294
790ea70c 3295 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3296 old_crtc_state, old_conn_state);
3297
afb2c443
ID		 3298 intel_ddi_disable_pipe_clock(old_crtc_state);
3299
f45f3da7 3300 intel_disable_ddi_buf(encoder);
62b69566 3301
f45f3da7 3302 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
b2ccb822 3303
f45f3da7
VS		 3304 intel_ddi_clk_disable(encoder);
3305
3306 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3307}
3308
3309static void intel_ddi_post_disable(struct intel_encoder *encoder,
3310 const struct intel_crtc_state *old_crtc_state,
3311 const struct drm_connector_state *old_conn_state)
3312{
3313 /*
1939ba51
VS		 3314 * When called from DP MST code:
3315 * - old_conn_state will be NULL
3316 * - encoder will be the main encoder (ie. mst->primary)
3317 * - the main connector associated with this port
3318 * won't be active or linked to a crtc
3319 * - old_crtc_state will be the state of the last stream to
3320 * be deactivated on this port, and it may not be the same
3321 * stream that was activated last, but each stream
3322 * should have a state that is identical when it comes to
3323 * the DP link parameteres
f45f3da7 3324 */
1939ba51
VS		 3325
3326 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3327 intel_ddi_post_disable_hdmi(encoder,
3328 old_crtc_state, old_conn_state);
3329 else
3330 intel_ddi_post_disable_dp(encoder,
3331 old_crtc_state, old_conn_state);
6441ab5f
PZ		 3332}
3333
1524e93e 3334void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3335 const struct intel_crtc_state *old_crtc_state,
3336 const struct drm_connector_state *old_conn_state)
b7076546 3337{
1524e93e 3338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 3339 uint32_t val;
3340
3341 /*
3342 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3343 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3344 * step 13 is the correct place for it. Step 18 is where it was
3345 * originally before the BUN.
3346 */
3347 val = I915_READ(FDI_RX_CTL(PIPE_A));
3348 val &= ~FDI_RX_ENABLE;
3349 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3350
fb0bd3bd
VS		 3351 intel_disable_ddi_buf(encoder);
3352 intel_ddi_clk_disable(encoder);
b7076546
ML		 3353
3354 val = I915_READ(FDI_RX_MISC(PIPE_A));
3355 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3356 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3357 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3358
3359 val = I915_READ(FDI_RX_CTL(PIPE_A));
3360 val &= ~FDI_PCDCLK;
3361 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3362
3363 val = I915_READ(FDI_RX_CTL(PIPE_A));
3364 val &= ~FDI_RX_PLL_ENABLE;
3365 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3366}
3367
15d05f0e
VS		 3368static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3369 const struct intel_crtc_state *crtc_state,
3370 const struct drm_connector_state *conn_state)
72662e10 3371{
15d05f0e
VS		 3372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3373 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3374 enum port port = encoder->port;
72662e10 3375
15d05f0e
VS		 3376 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3377 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3378
15d05f0e
VS		 3379 intel_edp_backlight_on(crtc_state, conn_state);
3380 intel_psr_enable(intel_dp, crtc_state);
3381 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3382
15d05f0e
VS		 3383 if (crtc_state->has_audio)
3384 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3385}
3386
8f19b401
ID		 3387static i915_reg_t
3388gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3389 enum port port)
3390{
3391 static const i915_reg_t regs[] = {
3392 [PORT_A] = CHICKEN_TRANS_EDP,
3393 [PORT_B] = CHICKEN_TRANS_A,
3394 [PORT_C] = CHICKEN_TRANS_B,
3395 [PORT_D] = CHICKEN_TRANS_C,
3396 [PORT_E] = CHICKEN_TRANS_A,
3397 };
3398
3399 WARN_ON(INTEL_GEN(dev_priv) < 9);
3400
3401 if (WARN_ON(port < PORT_A || port > PORT_E))
3402 port = PORT_A;
3403
3404 return regs[port];
3405}
3406
15d05f0e
VS		 3407static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3408 const struct intel_crtc_state *crtc_state,
3409 const struct drm_connector_state *conn_state)
3410{
3411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3412 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3413 struct drm_connector *connector = conn_state->connector;
0fce04c8 3414 enum port port = encoder->port;
15d05f0e 3415
277ab5ab
VS		 3416 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3417 crtc_state->hdmi_high_tmds_clock_ratio,
3418 crtc_state->hdmi_scrambling))
3419 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3420 connector->base.id, connector->name);
15d05f0e 3421
0519c102
VS		 3422 /* Display WA #1143: skl,kbl,cfl */
3423 if (IS_GEN9_BC(dev_priv)) {
3424 /*
3425 * For some reason these chicken bits have been
3426 * stuffed into a transcoder register, event though
3427 * the bits affect a specific DDI port rather than
3428 * a specific transcoder.
3429 */
8f19b401 3430 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3431 u32 val;
3432
8f19b401 3433 val = I915_READ(reg);
0519c102
VS		 3434
3435 if (port == PORT_E)
3436 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3437 DDIE_TRAINING_OVERRIDE_VALUE;
3438 else
3439 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3440 DDI_TRAINING_OVERRIDE_VALUE;
3441
8f19b401
ID		 3442 I915_WRITE(reg, val);
3443 POSTING_READ(reg);
0519c102
VS		 3444
3445 udelay(1);
3446
3447 if (port == PORT_E)
3448 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3449 DDIE_TRAINING_OVERRIDE_VALUE);
3450 else
3451 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3452 DDI_TRAINING_OVERRIDE_VALUE);
3453
8f19b401 3454 I915_WRITE(reg, val);
0519c102
VS		 3455 }
3456
15d05f0e
VS		 3457 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3458 * are ignored so nothing special needs to be done besides
3459 * enabling the port.
3460 */
3461 I915_WRITE(DDI_BUF_CTL(port),
3462 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3463
15d05f0e
VS		 3464 if (crtc_state->has_audio)
3465 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3466}
3467
3468static void intel_enable_ddi(struct intel_encoder *encoder,
3469 const struct intel_crtc_state *crtc_state,
3470 const struct drm_connector_state *conn_state)
3471{
3472 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3473 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3474 else
3475 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3476
3477 /* Enable hdcp if it's desired */
3478 if (conn_state->content_protection ==
3479 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3480 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3481}
3482
33f083f0
VS		 3483static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3484 const struct intel_crtc_state *old_crtc_state,
3485 const struct drm_connector_state *old_conn_state)
5ab432ef 3486{
33f083f0 3487 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3488
edb2e530
VS		 3489 intel_dp->link_trained = false;
3490
37255d8d 3491 if (old_crtc_state->has_audio)
8ec47de2
VS		 3492 intel_audio_codec_disable(encoder,
3493 old_crtc_state, old_conn_state);
2831d842 3494
33f083f0
VS		 3495 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3496 intel_psr_disable(intel_dp, old_crtc_state);
3497 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3498 /* Disable the decompression in DP Sink */
3499 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3500 false);
33f083f0 3501}
15953637 3502
33f083f0
VS		 3503static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3504 const struct intel_crtc_state *old_crtc_state,
3505 const struct drm_connector_state *old_conn_state)
3506{
277ab5ab
VS		 3507 struct drm_connector *connector = old_conn_state->connector;
3508
33f083f0 3509 if (old_crtc_state->has_audio)
8ec47de2
VS		 3510 intel_audio_codec_disable(encoder,
3511 old_crtc_state, old_conn_state);
d6c50ff8 3512
277ab5ab
VS		 3513 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3514 false, false))
3515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3516 connector->base.id, connector->name);
33f083f0
VS		 3517}
3518
3519static void intel_disable_ddi(struct intel_encoder *encoder,
3520 const struct intel_crtc_state *old_crtc_state,
3521 const struct drm_connector_state *old_conn_state)
3522{
ee5e5e7a
SP		 3523 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3524
33f083f0
VS		 3525 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3526 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3527 else
3528 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3529}
79f689aa 3530
03ad7d88
MN		 3531static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3532 const struct intel_crtc_state *pipe_config,
3533 enum port port)
3534{
3535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3536 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3537 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3538 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3539 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3540
3541 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3542 switch (pipe_config->lane_count) {
3543 case 1:
3544 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3545 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3546 break;
3547 case 2:
3548 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3549 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3550 break;
3551 case 4:
3552 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3553 break;
3554 default:
3555 MISSING_CASE(pipe_config->lane_count);
3556 }
3557 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3558}
3559
bdaa29b6
ID		 3560static void
3561intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3562 const struct intel_crtc_state *crtc_state,
3563 const struct drm_connector_state *conn_state)
03ad7d88 3564{
bdaa29b6 3565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3566 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bdaa29b6
ID		 3567 enum port port = encoder->port;
3568
8e4a3ad9
ID		 3569 if (intel_crtc_has_dp_encoder(crtc_state) ||
3570 intel_port_is_tc(dev_priv, encoder->port))
bdaa29b6
ID		 3571 intel_display_power_get(dev_priv,
3572 intel_ddi_main_link_aux_domain(dig_port));
3573
3574 if (IS_GEN9_LP(dev_priv))
3575 bxt_ddi_phy_set_lane_optim_mask(encoder,
3576 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3577
3578 /*
3579 * Program the lane count for static/dynamic connections on Type-C ports.
3580 * Skip this step for TBT.
3581 */
3582 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3583 dig_port->tc_type == TC_PORT_TBT)
3584 return;
3585
bdaa29b6
ID		 3586 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3587}
3588
3589static void
3590intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3591 const struct intel_crtc_state *crtc_state,
3592 const struct drm_connector_state *conn_state)
3593{
3594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3595 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3596
3597 if (intel_crtc_has_dp_encoder(crtc_state) ||
3598 intel_port_is_tc(dev_priv, encoder->port))
3599 intel_display_power_put(dev_priv,
3600 intel_ddi_main_link_aux_domain(dig_port));
03ad7d88
MN		 3601}
3602
ad64217b 3603void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3604{
ad64217b
ACO		 3605 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3606 struct drm_i915_private *dev_priv =
3607 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3608 enum port port = intel_dig_port->base.port;
c19b0669 3609 uint32_t val;
f3e227df 3610 bool wait = false;
c19b0669
PZ		 3611
3612 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3613 val = I915_READ(DDI_BUF_CTL(port));
3614 if (val & DDI_BUF_CTL_ENABLE) {
3615 val &= ~DDI_BUF_CTL_ENABLE;
3616 I915_WRITE(DDI_BUF_CTL(port), val);
3617 wait = true;
3618 }
3619
3620 val = I915_READ(DP_TP_CTL(port));
3621 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3622 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3623 I915_WRITE(DP_TP_CTL(port), val);
3624 POSTING_READ(DP_TP_CTL(port));
3625
3626 if (wait)
3627 intel_wait_ddi_buf_idle(dev_priv, port);
3628 }
3629
0e32b39c 3630 val = DP_TP_CTL_ENABLE |
c19b0669 3631 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3632 if (intel_dp->link_mst)
0e32b39c
DA		 3633 val |= DP_TP_CTL_MODE_MST;
3634 else {
3635 val |= DP_TP_CTL_MODE_SST;
3636 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3637 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3638 }
c19b0669
PZ		 3639 I915_WRITE(DP_TP_CTL(port), val);
3640 POSTING_READ(DP_TP_CTL(port));
3641
3642 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3643 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3644 POSTING_READ(DDI_BUF_CTL(port));
3645
3646 udelay(600);
3647}
00c09d70 3648
2085cc5d
VS		 3649static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3650 enum transcoder cpu_transcoder)
9935f7fa 3651{
2085cc5d
VS		 3652 if (cpu_transcoder == TRANSCODER_EDP)
3653 return false;
9935f7fa 3654
2085cc5d
VS		 3655 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3656 return false;
3657
3658 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3659 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3660}
3661
53e9bf5e
VS		 3662void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3663 struct intel_crtc_state *crtc_state)
3664{
36c1f028 3665 if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
9378985e 3666 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3667 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3668 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3669}
3670
6801c18c 3671void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3672 struct intel_crtc_state *pipe_config)
045ac3b5 3673{
fac5e23e 3674 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3675 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3676 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3677 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3678 u32 temp, flags = 0;
3679
4d1de975
JN		 3680 /* XXX: DSI transcoder paranoia */
3681 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3682 return;
3683
045ac3b5
JB		 3684 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3685 if (temp & TRANS_DDI_PHSYNC)
3686 flags |= DRM_MODE_FLAG_PHSYNC;
3687 else
3688 flags |= DRM_MODE_FLAG_NHSYNC;
3689 if (temp & TRANS_DDI_PVSYNC)
3690 flags |= DRM_MODE_FLAG_PVSYNC;
3691 else
3692 flags |= DRM_MODE_FLAG_NVSYNC;
3693
2d112de7 3694 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3695
3696 switch (temp & TRANS_DDI_BPC_MASK) {
3697 case TRANS_DDI_BPC_6:
3698 pipe_config->pipe_bpp = 18;
3699 break;
3700 case TRANS_DDI_BPC_8:
3701 pipe_config->pipe_bpp = 24;
3702 break;
3703 case TRANS_DDI_BPC_10:
3704 pipe_config->pipe_bpp = 30;
3705 break;
3706 case TRANS_DDI_BPC_12:
3707 pipe_config->pipe_bpp = 36;
3708 break;
3709 default:
3710 break;
3711 }
eb14cb74
VS		 3712
3713 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3714 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3715 pipe_config->has_hdmi_sink = true;
f99be1b3 3716 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3717
790ea70c 3718 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
bbd440fb 3719 pipe_config->has_infoframe = true;
15953637
SS		 3720
3721 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3722 TRANS_DDI_HDMI_SCRAMBLING_MASK)
3723 pipe_config->hdmi_scrambling = true;
3724 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3725 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3726 /* fall through */
eb14cb74 3727 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3728 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3729 pipe_config->lane_count = 4;
3730 break;
eb14cb74 3731 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3732 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3733 break;
3734 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3735 if (encoder->type == INTEL_OUTPUT_EDP)
3736 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3737 else
3738 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3739 pipe_config->lane_count =
3740 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3741 intel_dp_get_m_n(intel_crtc, pipe_config);
3742 break;
eb14cb74 3743 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3744 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3745 pipe_config->lane_count =
3746 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3747 intel_dp_get_m_n(intel_crtc, pipe_config);
3748 break;
3749 default:
3750 break;
3751 }
10214420 3752
9935f7fa 3753 pipe_config->has_audio =
2085cc5d 3754 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3755
6aa23e65
JN		 3756 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3757 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3758 /*
3759 * This is a big fat ugly hack.
3760 *
3761 * Some machines in UEFI boot mode provide us a VBT that has 18
3762 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3763 * unknown we fail to light up. Yet the same BIOS boots up with
3764 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3765 * max, not what it tells us to use.
3766 *
3767 * Note: This will still be broken if the eDP panel is not lit
3768 * up by the BIOS, and thus we can't get the mode at module
3769 * load.
3770 */
3771 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3772 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3773 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3774 }
11578553 3775
22606a18 3776 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3777
cc3f90f0 3778 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3779 pipe_config->lane_lat_optim_mask =
3780 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3781
3782 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
045ac3b5
JB		 3783}
3784
7e732cac
VS		 3785static enum intel_output_type
3786intel_ddi_compute_output_type(struct intel_encoder *encoder,
3787 struct intel_crtc_state *crtc_state,
3788 struct drm_connector_state *conn_state)
3789{
3790 switch (conn_state->connector->connector_type) {
3791 case DRM_MODE_CONNECTOR_HDMIA:
3792 return INTEL_OUTPUT_HDMI;
3793 case DRM_MODE_CONNECTOR_eDP:
3794 return INTEL_OUTPUT_EDP;
3795 case DRM_MODE_CONNECTOR_DisplayPort:
3796 return INTEL_OUTPUT_DP;
3797 default:
3798 MISSING_CASE(conn_state->connector->connector_type);
3799 return INTEL_OUTPUT_UNUSED;
3800 }
3801}
3802
5bfe2ac0 3803static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 3804 struct intel_crtc_state *pipe_config,
3805 struct drm_connector_state *conn_state)
00c09d70 3806{
fac5e23e 3807 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3808 enum port port = encoder->port;
95a7a2ae 3809 int ret;
00c09d70 3810
eccb140b
DV		 3811 if (port == PORT_A)
3812 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3813
7e732cac 3814 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3815 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3816 else
0a478c27 3817 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 3818
cc3f90f0 3819 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae 3820 pipe_config->lane_lat_optim_mask =
5161d058 3821 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3822
53e9bf5e
VS		 3823 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3824
95a7a2ae
ID		 3825 return ret;
3826
00c09d70
PZ		 3827}
3828
3829static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 3830 .reset = intel_dp_encoder_reset,
3831 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 3832};
3833
4a28ae58
PZ		 3834static struct intel_connector *
3835intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3836{
3837 struct intel_connector *connector;
8f4f2797 3838 enum port port = intel_dig_port->base.port;
4a28ae58 3839
9bdbd0b9 3840 connector = intel_connector_alloc();
4a28ae58
PZ		 3841 if (!connector)
3842 return NULL;
3843
3844 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3845 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3846 kfree(connector);
3847 return NULL;
3848 }
3849
3850 return connector;
3851}
3852
dba14b27
VS		 3853static int modeset_pipe(struct drm_crtc *crtc,
3854 struct drm_modeset_acquire_ctx *ctx)
3855{
3856 struct drm_atomic_state *state;
3857 struct drm_crtc_state *crtc_state;
3858 int ret;
3859
3860 state = drm_atomic_state_alloc(crtc->dev);
3861 if (!state)
3862 return -ENOMEM;
3863
3864 state->acquire_ctx = ctx;
3865
3866 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3867 if (IS_ERR(crtc_state)) {
3868 ret = PTR_ERR(crtc_state);
3869 goto out;
3870 }
3871
3872 crtc_state->mode_changed = true;
3873
3874 ret = drm_atomic_add_affected_connectors(state, crtc);
3875 if (ret)
3876 goto out;
3877
3878 ret = drm_atomic_add_affected_planes(state, crtc);
3879 if (ret)
3880 goto out;
3881
3882 ret = drm_atomic_commit(state);
3883 if (ret)
3884 goto out;
3885
3886 return 0;
3887
3888 out:
3889 drm_atomic_state_put(state);
3890
3891 return ret;
3892}
3893
3894static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3895 struct drm_modeset_acquire_ctx *ctx)
3896{
3897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3898 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3899 struct intel_connector *connector = hdmi->attached_connector;
3900 struct i2c_adapter *adapter =
3901 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3902 struct drm_connector_state *conn_state;
3903 struct intel_crtc_state *crtc_state;
3904 struct intel_crtc *crtc;
3905 u8 config;
3906 int ret;
3907
3908 if (!connector || connector->base.status != connector_status_connected)
3909 return 0;
3910
3911 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3912 ctx);
3913 if (ret)
3914 return ret;
3915
3916 conn_state = connector->base.state;
3917
3918 crtc = to_intel_crtc(conn_state->crtc);
3919 if (!crtc)
3920 return 0;
3921
3922 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3923 if (ret)
3924 return ret;
3925
3926 crtc_state = to_intel_crtc_state(crtc->base.state);
3927
3928 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3929
3930 if (!crtc_state->base.active)
3931 return 0;
3932
3933 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3934 !crtc_state->hdmi_scrambling)
3935 return 0;
3936
3937 if (conn_state->commit &&
3938 !try_wait_for_completion(&conn_state->commit->hw_done))
3939 return 0;
3940
3941 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3942 if (ret < 0) {
3943 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3944 return 0;
3945 }
3946
3947 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3948 crtc_state->hdmi_high_tmds_clock_ratio &&
3949 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3950 crtc_state->hdmi_scrambling)
3951 return 0;
3952
3953 /*
3954 * HDMI 2.0 says that one should not send scrambled data
3955 * prior to configuring the sink scrambling, and that
3956 * TMDS clock/data transmission should be suspended when
3957 * changing the TMDS clock rate in the sink. So let's
3958 * just do a full modeset here, even though some sinks
3959 * would be perfectly happy if were to just reconfigure
3960 * the SCDC settings on the fly.
3961 */
3962 return modeset_pipe(&crtc->base, ctx);
3963}
3964
3965static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3966 struct intel_connector *connector)
3967{
3968 struct drm_modeset_acquire_ctx ctx;
3969 bool changed;
3970 int ret;
3971
3972 changed = intel_encoder_hotplug(encoder, connector);
3973
3974 drm_modeset_acquire_init(&ctx, 0);
3975
3976 for (;;) {
c85d200e
VS		 3977 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3978 ret = intel_hdmi_reset_link(encoder, &ctx);
3979 else
3980 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 3981
3982 if (ret == -EDEADLK) {
3983 drm_modeset_backoff(&ctx);
3984 continue;
3985 }
3986
3987 break;
3988 }
3989
3990 drm_modeset_drop_locks(&ctx);
3991 drm_modeset_acquire_fini(&ctx);
3992 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3993
3994 return changed;
3995}
3996
4a28ae58
PZ		 3997static struct intel_connector *
3998intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3999{
4000 struct intel_connector *connector;
8f4f2797 4001 enum port port = intel_dig_port->base.port;
4a28ae58 4002
9bdbd0b9 4003 connector = intel_connector_alloc();
4a28ae58
PZ		 4004 if (!connector)
4005 return NULL;
4006
4007 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4008 intel_hdmi_init_connector(intel_dig_port, connector);
4009
4010 return connector;
4011}
4012
436009b5
RV		 4013static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4014{
4015 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4016
8f4f2797 4017 if (dport->base.port != PORT_A)
436009b5
RV		 4018 return false;
4019
4020 if (dport->saved_port_bits & DDI_A_4_LANES)
4021 return false;
4022
4023 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4024 * supported configuration
4025 */
4026 if (IS_GEN9_LP(dev_priv))
4027 return true;
4028
4029 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4030 * one who does also have a full A/E split called
4031 * DDI_F what makes DDI_E useless. However for this
4032 * case let's trust VBT info.
4033 */
4034 if (IS_CANNONLAKE(dev_priv) &&
4035 !intel_bios_is_port_present(dev_priv, PORT_E))
4036 return true;
4037
4038 return false;
4039}
4040
3d2011cf
MK		 4041static int
4042intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4043{
4044 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4045 enum port port = intel_dport->base.port;
4046 int max_lanes = 4;
4047
4048 if (INTEL_GEN(dev_priv) >= 11)
4049 return max_lanes;
4050
4051 if (port == PORT_A || port == PORT_E) {
4052 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4053 max_lanes = port == PORT_A ? 4 : 0;
4054 else
4055 /* Both A and E share 2 lanes */
4056 max_lanes = 2;
4057 }
4058
4059 /*
4060 * Some BIOS might fail to set this bit on port A if eDP
4061 * wasn't lit up at boot. Force this bit set when needed
4062 * so we use the proper lane count for our calculations.
4063 */
4064 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4065 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4066 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4067 max_lanes = 4;
4068 }
4069
4070 return max_lanes;
4071}
4072
c39055b0 4073void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 4074{
4075 struct intel_digital_port *intel_dig_port;
4076 struct intel_encoder *intel_encoder;
4077 struct drm_encoder *encoder;
ff662124 4078 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4079 enum pipe pipe;
10e7bec3 4080
311a2094
PZ		 4081
4082 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
4083 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
4084 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 4085
4086 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4087 /*
4088 * Lspcon device needs to be driven with DP connector
4089 * with special detection sequence. So make sure DP
4090 * is initialized before lspcon.
4091 */
4092 init_dp = true;
4093 init_lspcon = true;
4094 init_hdmi = false;
4095 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4096 }
4097
311a2094 4098 if (!init_dp && !init_hdmi) {
500ea70d 4099 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4100 port_name(port));
500ea70d 4101 return;
311a2094 4102 }
00c09d70 4103
b14c5679 4104 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4105 if (!intel_dig_port)
4106 return;
4107
00c09d70
PZ		 4108 intel_encoder = &intel_dig_port->base;
4109 encoder = &intel_encoder->base;
4110
c39055b0 4111 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4112 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4113
c85d200e 4114 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4115 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4116 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4117 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4118 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4119 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4120 intel_encoder->pre_enable = intel_ddi_pre_enable;
4121 intel_encoder->disable = intel_disable_ddi;
4122 intel_encoder->post_disable = intel_ddi_post_disable;
4123 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4124 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 4125 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 4126 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4127 intel_encoder->type = INTEL_OUTPUT_DDI;
4128 intel_encoder->power_domain = intel_port_to_power_domain(port);
4129 intel_encoder->port = port;
3d2011cf 4130 intel_encoder->cloneable = 0;
570b16b5
MK		 4131 for_each_pipe(dev_priv, pipe)
4132 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4133
1e6aa7e5
JN		 4134 if (INTEL_GEN(dev_priv) >= 11)
4135 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4136 DDI_BUF_PORT_REVERSAL;
4137 else
4138 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4139 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4140 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4141 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4142 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4143
62b69566
ACO		 4144 switch (port) {
4145 case PORT_A:
4146 intel_dig_port->ddi_io_power_domain =
4147 POWER_DOMAIN_PORT_DDI_A_IO;
4148 break;
4149 case PORT_B:
4150 intel_dig_port->ddi_io_power_domain =
4151 POWER_DOMAIN_PORT_DDI_B_IO;
4152 break;
4153 case PORT_C:
4154 intel_dig_port->ddi_io_power_domain =
4155 POWER_DOMAIN_PORT_DDI_C_IO;
4156 break;
4157 case PORT_D:
4158 intel_dig_port->ddi_io_power_domain =
4159 POWER_DOMAIN_PORT_DDI_D_IO;
4160 break;
4161 case PORT_E:
4162 intel_dig_port->ddi_io_power_domain =
4163 POWER_DOMAIN_PORT_DDI_E_IO;
4164 break;
9787e835
RV		 4165 case PORT_F:
4166 intel_dig_port->ddi_io_power_domain =
4167 POWER_DOMAIN_PORT_DDI_F_IO;
4168 break;
62b69566
ACO		 4169 default:
4170 MISSING_CASE(port);
4171 }
4172
f68d697e
CW		 4173 if (init_dp) {
4174 if (!intel_ddi_init_dp_connector(intel_dig_port))
4175 goto err;
13cf5504 4176
f68d697e 4177 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4178 }
21a8e6a4 4179
311a2094
PZ		 4180 /* In theory we don't need the encoder->type check, but leave it just in
4181 * case we have some really bad VBTs... */
f68d697e
CW		 4182 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4183 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4184 goto err;
21a8e6a4 4185 }
f68d697e 4186
ff662124
SS		 4187 if (init_lspcon) {
4188 if (lspcon_init(intel_dig_port))
4189 /* TODO: handle hdmi info frame part */
4190 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4191 port_name(port));
4192 else
4193 /*
4194 * LSPCON init faied, but DP init was success, so
4195 * lets try to drive as DP++ port.
4196 */
4197 DRM_ERROR("LSPCON init failed on port %c\n",
4198 port_name(port));
4199 }
4200
06c812d7 4201 intel_infoframe_init(intel_dig_port);
f68d697e
CW		 4202 return;
4203
4204err:
4205 drm_encoder_cleanup(encoder);
4206 kfree(intel_dig_port);
00c09d70 4207}
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