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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
34 | }; | |
35 | ||
45244b87 ED |
36 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
37 | * them for both DP and FDI transports, allowing those ports to | |
38 | * automatically adapt to HDMI connections as well | |
39 | */ | |
10122051 JN |
40 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
41 | { 0x00FFFFFF, 0x0006000E }, | |
42 | { 0x00D75FFF, 0x0005000A }, | |
43 | { 0x00C30FFF, 0x00040006 }, | |
44 | { 0x80AAAFFF, 0x000B0000 }, | |
45 | { 0x00FFFFFF, 0x0005000A }, | |
46 | { 0x00D75FFF, 0x000C0004 }, | |
47 | { 0x80C30FFF, 0x000B0000 }, | |
48 | { 0x00FFFFFF, 0x00040006 }, | |
49 | { 0x80D75FFF, 0x000B0000 }, | |
45244b87 ED |
50 | }; |
51 | ||
10122051 JN |
52 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
53 | { 0x00FFFFFF, 0x0007000E }, | |
54 | { 0x00D75FFF, 0x000F000A }, | |
55 | { 0x00C30FFF, 0x00060006 }, | |
56 | { 0x00AAAFFF, 0x001E0000 }, | |
57 | { 0x00FFFFFF, 0x000F000A }, | |
58 | { 0x00D75FFF, 0x00160004 }, | |
59 | { 0x00C30FFF, 0x001E0000 }, | |
60 | { 0x00FFFFFF, 0x00060006 }, | |
61 | { 0x00D75FFF, 0x001E0000 }, | |
6acab15a PZ |
62 | }; |
63 | ||
10122051 JN |
64 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
65 | /* Idx NT mV d T mV d db */ | |
66 | { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ | |
67 | { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ | |
68 | { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ | |
69 | { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ | |
70 | { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ | |
71 | { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ | |
72 | { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ | |
73 | { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ | |
74 | { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ | |
75 | { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ | |
76 | { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ | |
77 | { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ | |
45244b87 ED |
78 | }; |
79 | ||
10122051 JN |
80 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
81 | { 0x00FFFFFF, 0x00000012 }, | |
82 | { 0x00EBAFFF, 0x00020011 }, | |
83 | { 0x00C71FFF, 0x0006000F }, | |
84 | { 0x00AAAFFF, 0x000E000A }, | |
85 | { 0x00FFFFFF, 0x00020011 }, | |
86 | { 0x00DB6FFF, 0x0005000F }, | |
87 | { 0x00BEEFFF, 0x000A000C }, | |
88 | { 0x00FFFFFF, 0x0005000F }, | |
89 | { 0x00DB6FFF, 0x000A000C }, | |
300644c7 PZ |
90 | }; |
91 | ||
10122051 JN |
92 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
93 | { 0x00FFFFFF, 0x0007000E }, | |
94 | { 0x00D75FFF, 0x000E000A }, | |
95 | { 0x00BEFFFF, 0x00140006 }, | |
96 | { 0x80B2CFFF, 0x001B0002 }, | |
97 | { 0x00FFFFFF, 0x000E000A }, | |
17b523ba | 98 | { 0x00DB6FFF, 0x00160005 }, |
6805b2a7 | 99 | { 0x80C71FFF, 0x001A0002 }, |
10122051 JN |
100 | { 0x00F7DFFF, 0x00180004 }, |
101 | { 0x80D75FFF, 0x001B0002 }, | |
e58623cb AR |
102 | }; |
103 | ||
10122051 JN |
104 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
105 | { 0x00FFFFFF, 0x0001000E }, | |
106 | { 0x00D75FFF, 0x0004000A }, | |
107 | { 0x00C30FFF, 0x00070006 }, | |
108 | { 0x00AAAFFF, 0x000C0000 }, | |
109 | { 0x00FFFFFF, 0x0004000A }, | |
110 | { 0x00D75FFF, 0x00090004 }, | |
111 | { 0x00C30FFF, 0x000C0000 }, | |
112 | { 0x00FFFFFF, 0x00070006 }, | |
113 | { 0x00D75FFF, 0x000C0000 }, | |
e58623cb AR |
114 | }; |
115 | ||
10122051 JN |
116 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
117 | /* Idx NT mV d T mV df db */ | |
118 | { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ | |
119 | { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ | |
120 | { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ | |
121 | { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ | |
122 | { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ | |
123 | { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ | |
124 | { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ | |
125 | { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ | |
126 | { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ | |
127 | { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ | |
a26aa8ba DL |
128 | }; |
129 | ||
7f88e3af | 130 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
6c930688 DL |
131 | { 0x00000018, 0x000000a2 }, |
132 | { 0x00004014, 0x0000009B }, | |
7f88e3af | 133 | { 0x00006012, 0x00000088 }, |
6c930688 DL |
134 | { 0x00008010, 0x00000087 }, |
135 | { 0x00000018, 0x0000009B }, | |
7f88e3af | 136 | { 0x00004014, 0x00000088 }, |
6c930688 | 137 | { 0x00006012, 0x00000087 }, |
7f88e3af | 138 | { 0x00000018, 0x00000088 }, |
6c930688 | 139 | { 0x00004014, 0x00000087 }, |
7f88e3af DL |
140 | }; |
141 | ||
7ad14a29 SJ |
142 | /* eDP 1.4 low vswing translation parameters */ |
143 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { | |
144 | { 0x00000018, 0x000000a8 }, | |
145 | { 0x00002016, 0x000000ab }, | |
146 | { 0x00006012, 0x000000a2 }, | |
147 | { 0x00008010, 0x00000088 }, | |
148 | { 0x00000018, 0x000000ab }, | |
149 | { 0x00004014, 0x000000a2 }, | |
150 | { 0x00006012, 0x000000a6 }, | |
151 | { 0x00000018, 0x000000a2 }, | |
152 | { 0x00005013, 0x0000009c }, | |
153 | { 0x00000018, 0x00000088 }, | |
154 | }; | |
155 | ||
156 | ||
7f88e3af | 157 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
b7192a56 SJ |
158 | { 0x00000018, 0x000000ac }, |
159 | { 0x00005012, 0x0000009d }, | |
160 | { 0x00007011, 0x00000088 }, | |
161 | { 0x00000018, 0x000000a1 }, | |
162 | { 0x00000018, 0x00000098 }, | |
163 | { 0x00004013, 0x00000088 }, | |
164 | { 0x00006012, 0x00000087 }, | |
165 | { 0x00000018, 0x000000df }, | |
166 | { 0x00003015, 0x00000087 }, | |
167 | { 0x00003015, 0x000000c7 }, | |
168 | { 0x00000018, 0x000000c7 }, | |
7f88e3af DL |
169 | }; |
170 | ||
20f4dbe4 | 171 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 172 | { |
0bdee30e | 173 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
174 | int type = intel_encoder->type; |
175 | ||
0e32b39c DA |
176 | if (type == INTEL_OUTPUT_DP_MST) { |
177 | struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; | |
178 | return intel_dig_port->port; | |
179 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || | |
00c09d70 | 180 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
181 | struct intel_digital_port *intel_dig_port = |
182 | enc_to_dig_port(encoder); | |
183 | return intel_dig_port->port; | |
0bdee30e | 184 | |
fc914639 PZ |
185 | } else if (type == INTEL_OUTPUT_ANALOG) { |
186 | return PORT_E; | |
0bdee30e | 187 | |
fc914639 PZ |
188 | } else { |
189 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
190 | BUG(); | |
191 | } | |
192 | } | |
193 | ||
e58623cb AR |
194 | /* |
195 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
196 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
197 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
198 | * in either FDI or DP modes only, as HDMI connections will work with both | |
199 | * of those | |
200 | */ | |
b403745c DL |
201 | static void intel_prepare_ddi_buffers(struct drm_device *dev, |
202 | struct intel_digital_port *intel_dig_port) | |
45244b87 ED |
203 | { |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
205 | u32 reg; | |
b403745c | 206 | int port = intel_dig_port->port; |
7ff44670 | 207 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
7ad14a29 | 208 | size; |
6acab15a | 209 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
10122051 JN |
210 | const struct ddi_buf_trans *ddi_translations_fdi; |
211 | const struct ddi_buf_trans *ddi_translations_dp; | |
212 | const struct ddi_buf_trans *ddi_translations_edp; | |
213 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
214 | const struct ddi_buf_trans *ddi_translations; | |
e58623cb | 215 | |
7f88e3af DL |
216 | if (IS_SKYLAKE(dev)) { |
217 | ddi_translations_fdi = NULL; | |
218 | ddi_translations_dp = skl_ddi_translations_dp; | |
7ad14a29 SJ |
219 | n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
220 | if (dev_priv->vbt.edp_low_vswing) { | |
221 | ddi_translations_edp = skl_ddi_translations_edp; | |
222 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); | |
223 | } else { | |
224 | ddi_translations_edp = skl_ddi_translations_dp; | |
225 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); | |
226 | } | |
227 | ||
7f88e3af DL |
228 | ddi_translations_hdmi = skl_ddi_translations_hdmi; |
229 | n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); | |
b7192a56 | 230 | hdmi_default_entry = 7; |
7f88e3af | 231 | } else if (IS_BROADWELL(dev)) { |
e58623cb AR |
232 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
233 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 234 | ddi_translations_edp = bdw_ddi_translations_edp; |
a26aa8ba | 235 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
7ad14a29 SJ |
236 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
237 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
10122051 | 238 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 239 | hdmi_default_entry = 7; |
e58623cb AR |
240 | } else if (IS_HASWELL(dev)) { |
241 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
242 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 243 | ddi_translations_edp = hsw_ddi_translations_dp; |
a26aa8ba | 244 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
7ad14a29 | 245 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
10122051 | 246 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
7ff44670 | 247 | hdmi_default_entry = 6; |
e58623cb AR |
248 | } else { |
249 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 250 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
251 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
252 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a26aa8ba | 253 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
7ad14a29 SJ |
254 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
255 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
10122051 | 256 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 257 | hdmi_default_entry = 7; |
e58623cb AR |
258 | } |
259 | ||
300644c7 PZ |
260 | switch (port) { |
261 | case PORT_A: | |
262 | ddi_translations = ddi_translations_edp; | |
7ad14a29 | 263 | size = n_edp_entries; |
300644c7 PZ |
264 | break; |
265 | case PORT_B: | |
266 | case PORT_C: | |
300644c7 | 267 | ddi_translations = ddi_translations_dp; |
7ad14a29 | 268 | size = n_dp_entries; |
300644c7 | 269 | break; |
77d8d009 | 270 | case PORT_D: |
7ad14a29 | 271 | if (intel_dp_is_edp(dev, PORT_D)) { |
77d8d009 | 272 | ddi_translations = ddi_translations_edp; |
7ad14a29 SJ |
273 | size = n_edp_entries; |
274 | } else { | |
77d8d009 | 275 | ddi_translations = ddi_translations_dp; |
7ad14a29 SJ |
276 | size = n_dp_entries; |
277 | } | |
77d8d009 | 278 | break; |
300644c7 | 279 | case PORT_E: |
7f88e3af DL |
280 | if (ddi_translations_fdi) |
281 | ddi_translations = ddi_translations_fdi; | |
282 | else | |
283 | ddi_translations = ddi_translations_dp; | |
7ad14a29 | 284 | size = n_dp_entries; |
300644c7 PZ |
285 | break; |
286 | default: | |
287 | BUG(); | |
288 | } | |
45244b87 | 289 | |
7ad14a29 | 290 | for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { |
10122051 JN |
291 | I915_WRITE(reg, ddi_translations[i].trans1); |
292 | reg += 4; | |
293 | I915_WRITE(reg, ddi_translations[i].trans2); | |
45244b87 ED |
294 | reg += 4; |
295 | } | |
ce4dd49e DL |
296 | |
297 | /* Choose a good default if VBT is badly populated */ | |
298 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
299 | hdmi_level >= n_hdmi_entries) | |
7ff44670 | 300 | hdmi_level = hdmi_default_entry; |
ce4dd49e | 301 | |
6acab15a | 302 | /* Entry 9 is for HDMI: */ |
10122051 JN |
303 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); |
304 | reg += 4; | |
305 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); | |
306 | reg += 4; | |
45244b87 ED |
307 | } |
308 | ||
309 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
310 | * mode and port E for FDI. | |
311 | */ | |
312 | void intel_prepare_ddi(struct drm_device *dev) | |
313 | { | |
b403745c DL |
314 | struct intel_digital_port *intel_dig_port; |
315 | bool visited[I915_MAX_PORTS] = { 0, }; | |
45244b87 | 316 | |
0d536cb4 PZ |
317 | if (!HAS_DDI(dev)) |
318 | return; | |
45244b87 | 319 | |
b403745c DL |
320 | for_each_digital_port(dev, intel_dig_port) { |
321 | if (visited[intel_dig_port->port]) | |
322 | continue; | |
323 | ||
324 | intel_prepare_ddi_buffers(dev, intel_dig_port); | |
325 | visited[intel_dig_port->port] = true; | |
326 | } | |
45244b87 | 327 | } |
c82e4d26 | 328 | |
248138b5 PZ |
329 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
330 | enum port port) | |
331 | { | |
332 | uint32_t reg = DDI_BUF_CTL(port); | |
333 | int i; | |
334 | ||
3449ca85 | 335 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
336 | udelay(1); |
337 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
338 | return; | |
339 | } | |
340 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
341 | } | |
c82e4d26 ED |
342 | |
343 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
344 | * connection to the PCH-located connectors. For this, it is necessary to train | |
345 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
346 | * | |
347 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
348 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
349 | * DDI A (which is used for eDP) | |
350 | */ | |
351 | ||
352 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
353 | { | |
354 | struct drm_device *dev = crtc->dev; | |
355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 357 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 358 | |
04945641 PZ |
359 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
360 | * mode set "sequence for CRT port" document: | |
361 | * - TP1 to TP2 time with the default value | |
362 | * - FDI delay to 90h | |
8693a824 DL |
363 | * |
364 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
365 | */ |
366 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
367 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
368 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
369 | ||
370 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 371 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 372 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 373 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
04945641 PZ |
374 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
375 | POSTING_READ(_FDI_RXA_CTL); | |
376 | udelay(220); | |
377 | ||
378 | /* Switch from Rawclk to PCDclk */ | |
379 | rx_ctl_val |= FDI_PCDCLK; | |
380 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
381 | ||
382 | /* Configure Port Clock Select */ | |
6e3c9717 ACO |
383 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
384 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
385 | |
386 | /* Start the training iterating through available voltages and emphasis, | |
387 | * testing each value twice. */ | |
10122051 | 388 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
389 | /* Configure DP_TP_CTL with auto-training */ |
390 | I915_WRITE(DP_TP_CTL(PORT_E), | |
391 | DP_TP_CTL_FDI_AUTOTRAIN | | |
392 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
393 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
394 | DP_TP_CTL_ENABLE); | |
395 | ||
876a8cdf DL |
396 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
397 | * DDI E does not support port reversal, the functionality is | |
398 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
399 | * port reversal bit */ | |
c82e4d26 | 400 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 401 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 402 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 403 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 404 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
405 | |
406 | udelay(600); | |
407 | ||
04945641 PZ |
408 | /* Program PCH FDI Receiver TU */ |
409 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
410 | ||
411 | /* Enable PCH FDI Receiver with auto-training */ | |
412 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
413 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
414 | POSTING_READ(_FDI_RXA_CTL); | |
415 | ||
416 | /* Wait for FDI receiver lane calibration */ | |
417 | udelay(30); | |
418 | ||
419 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
420 | temp = I915_READ(_FDI_RXA_MISC); | |
421 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
422 | I915_WRITE(_FDI_RXA_MISC, temp); | |
423 | POSTING_READ(_FDI_RXA_MISC); | |
424 | ||
425 | /* Wait for FDI auto training time */ | |
426 | udelay(5); | |
c82e4d26 ED |
427 | |
428 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
429 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 430 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
431 | |
432 | /* Enable normal pixel sending for FDI */ | |
433 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
434 | DP_TP_CTL_FDI_AUTOTRAIN | |
435 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
436 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
437 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 438 | |
04945641 | 439 | return; |
c82e4d26 | 440 | } |
04945641 | 441 | |
248138b5 PZ |
442 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
443 | temp &= ~DDI_BUF_CTL_ENABLE; | |
444 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
445 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
446 | ||
04945641 | 447 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
448 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
449 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
450 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
451 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
452 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
453 | ||
454 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
455 | |
456 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
457 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 458 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
459 | |
460 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
461 | temp = I915_READ(_FDI_RXA_MISC); | |
462 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
463 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
464 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 465 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
466 | } |
467 | ||
04945641 | 468 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 469 | } |
0e72a5b5 | 470 | |
44905a27 DA |
471 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
472 | { | |
473 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
474 | struct intel_digital_port *intel_dig_port = | |
475 | enc_to_dig_port(&encoder->base); | |
476 | ||
477 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 478 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
44905a27 DA |
479 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
480 | ||
481 | } | |
482 | ||
8d9ddbcb PZ |
483 | static struct intel_encoder * |
484 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
485 | { | |
486 | struct drm_device *dev = crtc->dev; | |
487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
488 | struct intel_encoder *intel_encoder, *ret = NULL; | |
489 | int num_encoders = 0; | |
490 | ||
491 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
492 | ret = intel_encoder; | |
493 | num_encoders++; | |
494 | } | |
495 | ||
496 | if (num_encoders != 1) | |
84f44ce7 VS |
497 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
498 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
499 | |
500 | BUG_ON(ret == NULL); | |
501 | return ret; | |
502 | } | |
503 | ||
bcddf610 | 504 | struct intel_encoder * |
3165c074 | 505 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 506 | { |
3165c074 ACO |
507 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
508 | struct intel_encoder *ret = NULL; | |
509 | struct drm_atomic_state *state; | |
d0737e1d | 510 | int num_encoders = 0; |
3165c074 | 511 | int i; |
d0737e1d | 512 | |
3165c074 ACO |
513 | state = crtc_state->base.state; |
514 | ||
515 | for (i = 0; i < state->num_connector; i++) { | |
516 | if (!state->connectors[i] || | |
517 | state->connector_states[i]->crtc != crtc_state->base.crtc) | |
518 | continue; | |
519 | ||
520 | ret = to_intel_encoder(state->connector_states[i]->best_encoder); | |
521 | num_encoders++; | |
d0737e1d ACO |
522 | } |
523 | ||
524 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
525 | pipe_name(crtc->pipe)); | |
526 | ||
527 | BUG_ON(ret == NULL); | |
528 | return ret; | |
529 | } | |
530 | ||
1c0b85c5 | 531 | #define LC_FREQ 2700 |
27893390 | 532 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
1c0b85c5 DL |
533 | |
534 | #define P_MIN 2 | |
535 | #define P_MAX 64 | |
536 | #define P_INC 2 | |
537 | ||
538 | /* Constraints for PLL good behavior */ | |
539 | #define REF_MIN 48 | |
540 | #define REF_MAX 400 | |
541 | #define VCO_MIN 2400 | |
542 | #define VCO_MAX 4800 | |
543 | ||
27893390 DL |
544 | #define abs_diff(a, b) ({ \ |
545 | typeof(a) __a = (a); \ | |
546 | typeof(b) __b = (b); \ | |
547 | (void) (&__a == &__b); \ | |
548 | __a > __b ? (__a - __b) : (__b - __a); }) | |
1c0b85c5 DL |
549 | |
550 | struct wrpll_rnp { | |
551 | unsigned p, n2, r2; | |
552 | }; | |
553 | ||
554 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 555 | { |
1c0b85c5 DL |
556 | unsigned budget; |
557 | ||
558 | switch (clock) { | |
559 | case 25175000: | |
560 | case 25200000: | |
561 | case 27000000: | |
562 | case 27027000: | |
563 | case 37762500: | |
564 | case 37800000: | |
565 | case 40500000: | |
566 | case 40541000: | |
567 | case 54000000: | |
568 | case 54054000: | |
569 | case 59341000: | |
570 | case 59400000: | |
571 | case 72000000: | |
572 | case 74176000: | |
573 | case 74250000: | |
574 | case 81000000: | |
575 | case 81081000: | |
576 | case 89012000: | |
577 | case 89100000: | |
578 | case 108000000: | |
579 | case 108108000: | |
580 | case 111264000: | |
581 | case 111375000: | |
582 | case 148352000: | |
583 | case 148500000: | |
584 | case 162000000: | |
585 | case 162162000: | |
586 | case 222525000: | |
587 | case 222750000: | |
588 | case 296703000: | |
589 | case 297000000: | |
590 | budget = 0; | |
591 | break; | |
592 | case 233500000: | |
593 | case 245250000: | |
594 | case 247750000: | |
595 | case 253250000: | |
596 | case 298000000: | |
597 | budget = 1500; | |
598 | break; | |
599 | case 169128000: | |
600 | case 169500000: | |
601 | case 179500000: | |
602 | case 202000000: | |
603 | budget = 2000; | |
604 | break; | |
605 | case 256250000: | |
606 | case 262500000: | |
607 | case 270000000: | |
608 | case 272500000: | |
609 | case 273750000: | |
610 | case 280750000: | |
611 | case 281250000: | |
612 | case 286000000: | |
613 | case 291750000: | |
614 | budget = 4000; | |
615 | break; | |
616 | case 267250000: | |
617 | case 268500000: | |
618 | budget = 5000; | |
619 | break; | |
620 | default: | |
621 | budget = 1000; | |
622 | break; | |
623 | } | |
6441ab5f | 624 | |
1c0b85c5 DL |
625 | return budget; |
626 | } | |
627 | ||
628 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
629 | unsigned r2, unsigned n2, unsigned p, | |
630 | struct wrpll_rnp *best) | |
631 | { | |
632 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 633 | |
1c0b85c5 DL |
634 | /* No best (r,n,p) yet */ |
635 | if (best->p == 0) { | |
636 | best->p = p; | |
637 | best->n2 = n2; | |
638 | best->r2 = r2; | |
639 | return; | |
640 | } | |
6441ab5f | 641 | |
1c0b85c5 DL |
642 | /* |
643 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
644 | * freq2k. | |
645 | * | |
646 | * delta = 1e6 * | |
647 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
648 | * freq2k; | |
649 | * | |
650 | * and we would like delta <= budget. | |
651 | * | |
652 | * If the discrepancy is above the PPM-based budget, always prefer to | |
653 | * improve upon the previous solution. However, if you're within the | |
654 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
655 | */ | |
656 | a = freq2k * budget * p * r2; | |
657 | b = freq2k * budget * best->p * best->r2; | |
27893390 DL |
658 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
659 | diff_best = abs_diff(freq2k * best->p * best->r2, | |
660 | LC_FREQ_2K * best->n2); | |
1c0b85c5 DL |
661 | c = 1000000 * diff; |
662 | d = 1000000 * diff_best; | |
663 | ||
664 | if (a < c && b < d) { | |
665 | /* If both are above the budget, pick the closer */ | |
666 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
667 | best->p = p; | |
668 | best->n2 = n2; | |
669 | best->r2 = r2; | |
670 | } | |
671 | } else if (a >= c && b < d) { | |
672 | /* If A is below the threshold but B is above it? Update. */ | |
673 | best->p = p; | |
674 | best->n2 = n2; | |
675 | best->r2 = r2; | |
676 | } else if (a >= c && b >= d) { | |
677 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
678 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
679 | best->p = p; | |
680 | best->n2 = n2; | |
681 | best->r2 = r2; | |
682 | } | |
683 | } | |
684 | /* Otherwise a < c && b >= d, do nothing */ | |
685 | } | |
686 | ||
11578553 JB |
687 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
688 | int reg) | |
689 | { | |
690 | int refclk = LC_FREQ; | |
691 | int n, p, r; | |
692 | u32 wrpll; | |
693 | ||
694 | wrpll = I915_READ(reg); | |
114fe488 DV |
695 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
696 | case WRPLL_PLL_SSC: | |
697 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
698 | /* |
699 | * We could calculate spread here, but our checking | |
700 | * code only cares about 5% accuracy, and spread is a max of | |
701 | * 0.5% downspread. | |
702 | */ | |
703 | refclk = 135; | |
704 | break; | |
114fe488 | 705 | case WRPLL_PLL_LCPLL: |
11578553 JB |
706 | refclk = LC_FREQ; |
707 | break; | |
708 | default: | |
709 | WARN(1, "bad wrpll refclk\n"); | |
710 | return 0; | |
711 | } | |
712 | ||
713 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
714 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
715 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
716 | ||
20f0ec16 JB |
717 | /* Convert to KHz, p & r have a fixed point portion */ |
718 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
719 | } |
720 | ||
540e732c S |
721 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
722 | uint32_t dpll) | |
723 | { | |
724 | uint32_t cfgcr1_reg, cfgcr2_reg; | |
725 | uint32_t cfgcr1_val, cfgcr2_val; | |
726 | uint32_t p0, p1, p2, dco_freq; | |
727 | ||
728 | cfgcr1_reg = GET_CFG_CR1_REG(dpll); | |
729 | cfgcr2_reg = GET_CFG_CR2_REG(dpll); | |
730 | ||
731 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
732 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
733 | ||
734 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
735 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
736 | ||
737 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
738 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
739 | else | |
740 | p1 = 1; | |
741 | ||
742 | ||
743 | switch (p0) { | |
744 | case DPLL_CFGCR2_PDIV_1: | |
745 | p0 = 1; | |
746 | break; | |
747 | case DPLL_CFGCR2_PDIV_2: | |
748 | p0 = 2; | |
749 | break; | |
750 | case DPLL_CFGCR2_PDIV_3: | |
751 | p0 = 3; | |
752 | break; | |
753 | case DPLL_CFGCR2_PDIV_7: | |
754 | p0 = 7; | |
755 | break; | |
756 | } | |
757 | ||
758 | switch (p2) { | |
759 | case DPLL_CFGCR2_KDIV_5: | |
760 | p2 = 5; | |
761 | break; | |
762 | case DPLL_CFGCR2_KDIV_2: | |
763 | p2 = 2; | |
764 | break; | |
765 | case DPLL_CFGCR2_KDIV_3: | |
766 | p2 = 3; | |
767 | break; | |
768 | case DPLL_CFGCR2_KDIV_1: | |
769 | p2 = 1; | |
770 | break; | |
771 | } | |
772 | ||
773 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
774 | ||
775 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
776 | 1000) / 0x8000; | |
777 | ||
778 | return dco_freq / (p0 * p1 * p2 * 5); | |
779 | } | |
780 | ||
781 | ||
782 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 783 | struct intel_crtc_state *pipe_config) |
540e732c S |
784 | { |
785 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
540e732c S |
786 | int link_clock = 0; |
787 | uint32_t dpll_ctl1, dpll; | |
788 | ||
134ffa44 | 789 | dpll = pipe_config->ddi_pll_sel; |
540e732c S |
790 | |
791 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
792 | ||
793 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
794 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
795 | } else { | |
796 | link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); | |
797 | link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); | |
798 | ||
799 | switch (link_clock) { | |
800 | case DPLL_CRTL1_LINK_RATE_810: | |
801 | link_clock = 81000; | |
802 | break; | |
a8f3ef61 SJ |
803 | case DPLL_CRTL1_LINK_RATE_1080: |
804 | link_clock = 108000; | |
805 | break; | |
540e732c S |
806 | case DPLL_CRTL1_LINK_RATE_1350: |
807 | link_clock = 135000; | |
808 | break; | |
a8f3ef61 SJ |
809 | case DPLL_CRTL1_LINK_RATE_1620: |
810 | link_clock = 162000; | |
811 | break; | |
812 | case DPLL_CRTL1_LINK_RATE_2160: | |
813 | link_clock = 216000; | |
814 | break; | |
540e732c S |
815 | case DPLL_CRTL1_LINK_RATE_2700: |
816 | link_clock = 270000; | |
817 | break; | |
818 | default: | |
819 | WARN(1, "Unsupported link rate\n"); | |
820 | break; | |
821 | } | |
822 | link_clock *= 2; | |
823 | } | |
824 | ||
825 | pipe_config->port_clock = link_clock; | |
826 | ||
827 | if (pipe_config->has_dp_encoder) | |
2d112de7 | 828 | pipe_config->base.adjusted_mode.crtc_clock = |
540e732c S |
829 | intel_dotclock_calculate(pipe_config->port_clock, |
830 | &pipe_config->dp_m_n); | |
831 | else | |
2d112de7 | 832 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
540e732c S |
833 | } |
834 | ||
3d51278a | 835 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 836 | struct intel_crtc_state *pipe_config) |
11578553 JB |
837 | { |
838 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
839 | int link_clock = 0; |
840 | u32 val, pll; | |
841 | ||
26804afd | 842 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
843 | switch (val & PORT_CLK_SEL_MASK) { |
844 | case PORT_CLK_SEL_LCPLL_810: | |
845 | link_clock = 81000; | |
846 | break; | |
847 | case PORT_CLK_SEL_LCPLL_1350: | |
848 | link_clock = 135000; | |
849 | break; | |
850 | case PORT_CLK_SEL_LCPLL_2700: | |
851 | link_clock = 270000; | |
852 | break; | |
853 | case PORT_CLK_SEL_WRPLL1: | |
854 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
855 | break; | |
856 | case PORT_CLK_SEL_WRPLL2: | |
857 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
858 | break; | |
859 | case PORT_CLK_SEL_SPLL: | |
860 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
861 | if (pll == SPLL_PLL_FREQ_810MHz) | |
862 | link_clock = 81000; | |
863 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
864 | link_clock = 135000; | |
865 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
866 | link_clock = 270000; | |
867 | else { | |
868 | WARN(1, "bad spll freq\n"); | |
869 | return; | |
870 | } | |
871 | break; | |
872 | default: | |
873 | WARN(1, "bad port clock sel\n"); | |
874 | return; | |
875 | } | |
876 | ||
877 | pipe_config->port_clock = link_clock * 2; | |
878 | ||
879 | if (pipe_config->has_pch_encoder) | |
2d112de7 | 880 | pipe_config->base.adjusted_mode.crtc_clock = |
11578553 JB |
881 | intel_dotclock_calculate(pipe_config->port_clock, |
882 | &pipe_config->fdi_m_n); | |
883 | else if (pipe_config->has_dp_encoder) | |
2d112de7 | 884 | pipe_config->base.adjusted_mode.crtc_clock = |
11578553 JB |
885 | intel_dotclock_calculate(pipe_config->port_clock, |
886 | &pipe_config->dp_m_n); | |
887 | else | |
2d112de7 | 888 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
11578553 JB |
889 | } |
890 | ||
977bb38d S |
891 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
892 | enum intel_dpll_id dpll) | |
893 | { | |
894 | /* FIXME formula not available in bspec */ | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
899 | struct intel_crtc_state *pipe_config) | |
900 | { | |
901 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
902 | enum port port = intel_ddi_get_encoder_port(encoder); | |
903 | uint32_t dpll = port; | |
904 | ||
905 | pipe_config->port_clock = | |
906 | bxt_calc_pll_link(dev_priv, dpll); | |
907 | ||
908 | if (pipe_config->has_dp_encoder) | |
909 | pipe_config->base.adjusted_mode.crtc_clock = | |
910 | intel_dotclock_calculate(pipe_config->port_clock, | |
911 | &pipe_config->dp_m_n); | |
912 | else | |
913 | pipe_config->base.adjusted_mode.crtc_clock = | |
914 | pipe_config->port_clock; | |
915 | } | |
916 | ||
3d51278a | 917 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 918 | struct intel_crtc_state *pipe_config) |
3d51278a | 919 | { |
22606a18 DL |
920 | struct drm_device *dev = encoder->base.dev; |
921 | ||
922 | if (INTEL_INFO(dev)->gen <= 8) | |
923 | hsw_ddi_clock_get(encoder, pipe_config); | |
977bb38d | 924 | else if (IS_SKYLAKE(dev)) |
22606a18 | 925 | skl_ddi_clock_get(encoder, pipe_config); |
977bb38d S |
926 | else if (IS_BROXTON(dev)) |
927 | bxt_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
928 | } |
929 | ||
1c0b85c5 | 930 | static void |
d664c0ce DL |
931 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
932 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
1c0b85c5 DL |
933 | { |
934 | uint64_t freq2k; | |
935 | unsigned p, n2, r2; | |
936 | struct wrpll_rnp best = { 0, 0, 0 }; | |
937 | unsigned budget; | |
938 | ||
939 | freq2k = clock / 100; | |
940 | ||
941 | budget = wrpll_get_budget_for_freq(clock); | |
942 | ||
943 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
944 | * and directly pass the LC PLL to it. */ | |
945 | if (freq2k == 5400000) { | |
946 | *n2_out = 2; | |
947 | *p_out = 1; | |
948 | *r2_out = 2; | |
949 | return; | |
950 | } | |
951 | ||
952 | /* | |
953 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
954 | * the WR PLL. | |
955 | * | |
956 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
957 | * Injecting R2 = 2 * R gives: | |
958 | * REF_MAX * r2 > LC_FREQ * 2 and | |
959 | * REF_MIN * r2 < LC_FREQ * 2 | |
960 | * | |
961 | * Which means the desired boundaries for r2 are: | |
962 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
963 | * | |
964 | */ | |
965 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
966 | r2 <= LC_FREQ * 2 / REF_MIN; | |
967 | r2++) { | |
968 | ||
969 | /* | |
970 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
971 | * | |
972 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
973 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
974 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
975 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
976 | * | |
977 | * Which means the desired boundaries for n2 are: | |
978 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
979 | */ | |
980 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
981 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
982 | n2++) { | |
983 | ||
984 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
985 | wrpll_update_rnp(freq2k, budget, | |
986 | r2, n2, p, &best); | |
987 | } | |
988 | } | |
6441ab5f | 989 | |
1c0b85c5 DL |
990 | *n2_out = best.n2; |
991 | *p_out = best.p; | |
992 | *r2_out = best.r2; | |
6441ab5f PZ |
993 | } |
994 | ||
0220ab6e | 995 | static bool |
d664c0ce | 996 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 997 | struct intel_crtc_state *crtc_state, |
d664c0ce DL |
998 | struct intel_encoder *intel_encoder, |
999 | int clock) | |
6441ab5f | 1000 | { |
d664c0ce | 1001 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 1002 | struct intel_shared_dpll *pll; |
716c2e55 | 1003 | uint32_t val; |
1c0b85c5 | 1004 | unsigned p, n2, r2; |
6441ab5f | 1005 | |
d664c0ce | 1006 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
0694001b | 1007 | |
114fe488 | 1008 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
1009 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
1010 | WRPLL_DIVIDER_POST(p); | |
1011 | ||
190f68c5 | 1012 | crtc_state->dpll_hw_state.wrpll = val; |
6441ab5f | 1013 | |
190f68c5 | 1014 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
716c2e55 DV |
1015 | if (pll == NULL) { |
1016 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1017 | pipe_name(intel_crtc->pipe)); | |
1018 | return false; | |
0694001b | 1019 | } |
d452c5b6 | 1020 | |
190f68c5 | 1021 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
6441ab5f PZ |
1022 | } |
1023 | ||
6441ab5f PZ |
1024 | return true; |
1025 | } | |
1026 | ||
82d35437 S |
1027 | struct skl_wrpll_params { |
1028 | uint32_t dco_fraction; | |
1029 | uint32_t dco_integer; | |
1030 | uint32_t qdiv_ratio; | |
1031 | uint32_t qdiv_mode; | |
1032 | uint32_t kdiv; | |
1033 | uint32_t pdiv; | |
1034 | uint32_t central_freq; | |
1035 | }; | |
1036 | ||
1037 | static void | |
1038 | skl_ddi_calculate_wrpll(int clock /* in Hz */, | |
1039 | struct skl_wrpll_params *wrpll_params) | |
1040 | { | |
1041 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ | |
21318cce DL |
1042 | uint64_t dco_central_freq[3] = {8400000000ULL, |
1043 | 9000000000ULL, | |
1044 | 9600000000ULL}; | |
82d35437 S |
1045 | uint32_t min_dco_deviation = 400; |
1046 | uint32_t min_dco_index = 3; | |
1047 | uint32_t P0[4] = {1, 2, 3, 7}; | |
1048 | uint32_t P2[4] = {1, 2, 3, 5}; | |
1049 | bool found = false; | |
1050 | uint32_t candidate_p = 0; | |
1051 | uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; | |
1052 | uint32_t candidate_p2[3] = {0}; | |
1053 | uint32_t dco_central_freq_deviation[3]; | |
1054 | uint32_t i, P1, k, dco_count; | |
1055 | bool retry_with_odd = false; | |
1056 | uint64_t dco_freq; | |
1057 | ||
1058 | /* Determine P0, P1 or P2 */ | |
1059 | for (dco_count = 0; dco_count < 3; dco_count++) { | |
1060 | found = false; | |
1061 | candidate_p = | |
1062 | div64_u64(dco_central_freq[dco_count], afe_clock); | |
1063 | if (retry_with_odd == false) | |
1064 | candidate_p = (candidate_p % 2 == 0 ? | |
1065 | candidate_p : candidate_p + 1); | |
1066 | ||
1067 | for (P1 = 1; P1 < candidate_p; P1++) { | |
1068 | for (i = 0; i < 4; i++) { | |
1069 | if (!(P0[i] != 1 || P1 == 1)) | |
1070 | continue; | |
1071 | ||
1072 | for (k = 0; k < 4; k++) { | |
1073 | if (P1 != 1 && P2[k] != 2) | |
1074 | continue; | |
1075 | ||
1076 | if (candidate_p == P0[i] * P1 * P2[k]) { | |
1077 | /* Found possible P0, P1, P2 */ | |
1078 | found = true; | |
1079 | candidate_p0[dco_count] = P0[i]; | |
1080 | candidate_p1[dco_count] = P1; | |
1081 | candidate_p2[dco_count] = P2[k]; | |
1082 | goto found; | |
1083 | } | |
1084 | ||
1085 | } | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | found: | |
1090 | if (found) { | |
1091 | dco_central_freq_deviation[dco_count] = | |
1092 | div64_u64(10000 * | |
1093 | abs_diff((candidate_p * afe_clock), | |
1094 | dco_central_freq[dco_count]), | |
1095 | dco_central_freq[dco_count]); | |
1096 | ||
1097 | if (dco_central_freq_deviation[dco_count] < | |
1098 | min_dco_deviation) { | |
1099 | min_dco_deviation = | |
1100 | dco_central_freq_deviation[dco_count]; | |
1101 | min_dco_index = dco_count; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | if (min_dco_index > 2 && dco_count == 2) { | |
1106 | retry_with_odd = true; | |
1107 | dco_count = 0; | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | if (min_dco_index > 2) { | |
1112 | WARN(1, "No valid values found for the given pixel clock\n"); | |
1113 | } else { | |
1114 | wrpll_params->central_freq = dco_central_freq[min_dco_index]; | |
1115 | ||
1116 | switch (dco_central_freq[min_dco_index]) { | |
21318cce | 1117 | case 9600000000ULL: |
82d35437 S |
1118 | wrpll_params->central_freq = 0; |
1119 | break; | |
21318cce | 1120 | case 9000000000ULL: |
82d35437 S |
1121 | wrpll_params->central_freq = 1; |
1122 | break; | |
21318cce | 1123 | case 8400000000ULL: |
82d35437 S |
1124 | wrpll_params->central_freq = 3; |
1125 | } | |
1126 | ||
1127 | switch (candidate_p0[min_dco_index]) { | |
1128 | case 1: | |
1129 | wrpll_params->pdiv = 0; | |
1130 | break; | |
1131 | case 2: | |
1132 | wrpll_params->pdiv = 1; | |
1133 | break; | |
1134 | case 3: | |
1135 | wrpll_params->pdiv = 2; | |
1136 | break; | |
1137 | case 7: | |
1138 | wrpll_params->pdiv = 4; | |
1139 | break; | |
1140 | default: | |
1141 | WARN(1, "Incorrect PDiv\n"); | |
1142 | } | |
1143 | ||
1144 | switch (candidate_p2[min_dco_index]) { | |
1145 | case 5: | |
1146 | wrpll_params->kdiv = 0; | |
1147 | break; | |
1148 | case 2: | |
1149 | wrpll_params->kdiv = 1; | |
1150 | break; | |
1151 | case 3: | |
1152 | wrpll_params->kdiv = 2; | |
1153 | break; | |
1154 | case 1: | |
1155 | wrpll_params->kdiv = 3; | |
1156 | break; | |
1157 | default: | |
1158 | WARN(1, "Incorrect KDiv\n"); | |
1159 | } | |
1160 | ||
1161 | wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; | |
1162 | wrpll_params->qdiv_mode = | |
1163 | (wrpll_params->qdiv_ratio == 1) ? 0 : 1; | |
1164 | ||
1165 | dco_freq = candidate_p0[min_dco_index] * | |
1166 | candidate_p1[min_dco_index] * | |
1167 | candidate_p2[min_dco_index] * afe_clock; | |
1168 | ||
1169 | /* | |
1170 | * Intermediate values are in Hz. | |
1171 | * Divide by MHz to match bsepc | |
1172 | */ | |
1173 | wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); | |
1174 | wrpll_params->dco_fraction = | |
1175 | div_u64(((div_u64(dco_freq, 24) - | |
1176 | wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); | |
1177 | ||
1178 | } | |
1179 | } | |
1180 | ||
1181 | ||
1182 | static bool | |
1183 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1184 | struct intel_crtc_state *crtc_state, |
82d35437 S |
1185 | struct intel_encoder *intel_encoder, |
1186 | int clock) | |
1187 | { | |
1188 | struct intel_shared_dpll *pll; | |
1189 | uint32_t ctrl1, cfgcr1, cfgcr2; | |
1190 | ||
1191 | /* | |
1192 | * See comment in intel_dpll_hw_state to understand why we always use 0 | |
1193 | * as the DPLL id in this function. | |
1194 | */ | |
1195 | ||
1196 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); | |
1197 | ||
1198 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1199 | struct skl_wrpll_params wrpll_params = { 0, }; | |
1200 | ||
1201 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); | |
1202 | ||
1203 | skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); | |
1204 | ||
1205 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | | |
1206 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | | |
1207 | wrpll_params.dco_integer; | |
1208 | ||
1209 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | | |
1210 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | | |
1211 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | | |
1212 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | | |
1213 | wrpll_params.central_freq; | |
1214 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { | |
1215 | struct drm_encoder *encoder = &intel_encoder->base; | |
1216 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1217 | ||
1218 | switch (intel_dp->link_bw) { | |
1219 | case DP_LINK_BW_1_62: | |
1220 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0); | |
1221 | break; | |
1222 | case DP_LINK_BW_2_7: | |
1223 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0); | |
1224 | break; | |
1225 | case DP_LINK_BW_5_4: | |
1226 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0); | |
1227 | break; | |
1228 | } | |
1229 | ||
1230 | cfgcr1 = cfgcr2 = 0; | |
1231 | } else /* eDP */ | |
1232 | return true; | |
1233 | ||
190f68c5 ACO |
1234 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
1235 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; | |
1236 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; | |
82d35437 | 1237 | |
190f68c5 | 1238 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
82d35437 S |
1239 | if (pll == NULL) { |
1240 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1241 | pipe_name(intel_crtc->pipe)); | |
1242 | return false; | |
1243 | } | |
1244 | ||
1245 | /* shared DPLL id 0 is DPLL 1 */ | |
190f68c5 | 1246 | crtc_state->ddi_pll_sel = pll->id + 1; |
82d35437 S |
1247 | |
1248 | return true; | |
1249 | } | |
0220ab6e | 1250 | |
d683f3bc S |
1251 | /* bxt clock parameters */ |
1252 | struct bxt_clk_div { | |
1253 | uint32_t p1; | |
1254 | uint32_t p2; | |
1255 | uint32_t m2_int; | |
1256 | uint32_t m2_frac; | |
1257 | bool m2_frac_en; | |
1258 | uint32_t n; | |
1259 | uint32_t prop_coef; | |
1260 | uint32_t int_coef; | |
1261 | uint32_t gain_ctl; | |
1262 | uint32_t targ_cnt; | |
1263 | uint32_t lanestagger; | |
1264 | }; | |
1265 | ||
1266 | /* pre-calculated values for DP linkrates */ | |
1267 | static struct bxt_clk_div bxt_dp_clk_val[7] = { | |
1268 | /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1269 | /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, | |
1270 | /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, | |
1271 | /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1272 | /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, | |
1273 | /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1274 | /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} | |
1275 | }; | |
1276 | ||
1277 | static bool | |
1278 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1279 | struct intel_crtc_state *crtc_state, | |
1280 | struct intel_encoder *intel_encoder, | |
1281 | int clock) | |
1282 | { | |
1283 | struct intel_shared_dpll *pll; | |
1284 | struct bxt_clk_div clk_div = {0}; | |
1285 | ||
1286 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1287 | intel_clock_t best_clock; | |
1288 | ||
1289 | /* Calculate HDMI div */ | |
1290 | /* | |
1291 | * FIXME: tie the following calculation into | |
1292 | * i9xx_crtc_compute_clock | |
1293 | */ | |
1294 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { | |
1295 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", | |
1296 | clock, pipe_name(intel_crtc->pipe)); | |
1297 | return false; | |
1298 | } | |
1299 | ||
1300 | clk_div.p1 = best_clock.p1; | |
1301 | clk_div.p2 = best_clock.p2; | |
1302 | WARN_ON(best_clock.m1 != 2); | |
1303 | clk_div.n = best_clock.n; | |
1304 | clk_div.m2_int = best_clock.m2 >> 22; | |
1305 | clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); | |
1306 | clk_div.m2_frac_en = clk_div.m2_frac != 0; | |
1307 | ||
1308 | /* FIXME: set coef, gain, targcnt based on freq band */ | |
1309 | clk_div.prop_coef = 5; | |
1310 | clk_div.int_coef = 11; | |
1311 | clk_div.gain_ctl = 2; | |
1312 | clk_div.targ_cnt = 9; | |
1313 | if (clock > 270000) | |
1314 | clk_div.lanestagger = 0x18; | |
1315 | else if (clock > 135000) | |
1316 | clk_div.lanestagger = 0x0d; | |
1317 | else if (clock > 67000) | |
1318 | clk_div.lanestagger = 0x07; | |
1319 | else if (clock > 33000) | |
1320 | clk_div.lanestagger = 0x04; | |
1321 | else | |
1322 | clk_div.lanestagger = 0x02; | |
1323 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
1324 | intel_encoder->type == INTEL_OUTPUT_EDP) { | |
1325 | struct drm_encoder *encoder = &intel_encoder->base; | |
1326 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1327 | ||
1328 | switch (intel_dp->link_bw) { | |
1329 | case DP_LINK_BW_1_62: | |
1330 | clk_div = bxt_dp_clk_val[0]; | |
1331 | break; | |
1332 | case DP_LINK_BW_2_7: | |
1333 | clk_div = bxt_dp_clk_val[1]; | |
1334 | break; | |
1335 | case DP_LINK_BW_5_4: | |
1336 | clk_div = bxt_dp_clk_val[2]; | |
1337 | break; | |
1338 | default: | |
1339 | clk_div = bxt_dp_clk_val[0]; | |
1340 | DRM_ERROR("Unknown link rate\n"); | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | crtc_state->dpll_hw_state.ebb0 = | |
1345 | PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); | |
1346 | crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; | |
1347 | crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); | |
1348 | crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; | |
1349 | ||
1350 | if (clk_div.m2_frac_en) | |
1351 | crtc_state->dpll_hw_state.pll3 = | |
1352 | PORT_PLL_M2_FRAC_ENABLE; | |
1353 | ||
1354 | crtc_state->dpll_hw_state.pll6 = | |
1355 | clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef); | |
1356 | crtc_state->dpll_hw_state.pll6 |= | |
1357 | PORT_PLL_GAIN_CTL(clk_div.gain_ctl); | |
1358 | ||
1359 | crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt; | |
1360 | ||
1361 | crtc_state->dpll_hw_state.pcsdw12 = | |
1362 | LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; | |
1363 | ||
1364 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); | |
1365 | if (pll == NULL) { | |
1366 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1367 | pipe_name(intel_crtc->pipe)); | |
1368 | return false; | |
1369 | } | |
1370 | ||
1371 | /* shared DPLL id 0 is DPLL A */ | |
1372 | crtc_state->ddi_pll_sel = pll->id; | |
1373 | ||
1374 | return true; | |
1375 | } | |
1376 | ||
0220ab6e DL |
1377 | /* |
1378 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1379 | * intel_crtc->ddi_pll_sel. | |
1380 | * | |
1381 | * For private DPLLs, compute_config() should do the selection for us. This | |
1382 | * function should be folded into compute_config() eventually. | |
1383 | */ | |
190f68c5 ACO |
1384 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1385 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1386 | { |
82d35437 | 1387 | struct drm_device *dev = intel_crtc->base.dev; |
d0737e1d | 1388 | struct intel_encoder *intel_encoder = |
3165c074 | 1389 | intel_ddi_get_crtc_new_encoder(crtc_state); |
190f68c5 | 1390 | int clock = crtc_state->port_clock; |
0220ab6e | 1391 | |
82d35437 | 1392 | if (IS_SKYLAKE(dev)) |
190f68c5 ACO |
1393 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
1394 | intel_encoder, clock); | |
d683f3bc S |
1395 | else if (IS_BROXTON(dev)) |
1396 | return bxt_ddi_pll_select(intel_crtc, crtc_state, | |
1397 | intel_encoder, clock); | |
82d35437 | 1398 | else |
190f68c5 ACO |
1399 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
1400 | intel_encoder, clock); | |
0220ab6e DL |
1401 | } |
1402 | ||
dae84799 PZ |
1403 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1404 | { | |
1405 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1407 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1408 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1409 | int type = intel_encoder->type; |
1410 | uint32_t temp; | |
1411 | ||
0e32b39c | 1412 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
c9809791 | 1413 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1414 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1415 | case 18: |
c9809791 | 1416 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1417 | break; |
1418 | case 24: | |
c9809791 | 1419 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1420 | break; |
1421 | case 30: | |
c9809791 | 1422 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1423 | break; |
1424 | case 36: | |
c9809791 | 1425 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1426 | break; |
1427 | default: | |
4e53c2e0 | 1428 | BUG(); |
dae84799 | 1429 | } |
c9809791 | 1430 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1431 | } |
1432 | } | |
1433 | ||
0e32b39c DA |
1434 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1435 | { | |
1436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1437 | struct drm_device *dev = crtc->dev; | |
1438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 1439 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1440 | uint32_t temp; |
1441 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1442 | if (state == true) | |
1443 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1444 | else | |
1445 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1446 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1447 | } | |
1448 | ||
8228c251 | 1449 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1450 | { |
1451 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1452 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 1453 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
1454 | struct drm_device *dev = crtc->dev; |
1455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 1456 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1457 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1458 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1459 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1460 | uint32_t temp; |
1461 | ||
ad80a810 PZ |
1462 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1463 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1464 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1465 | |
6e3c9717 | 1466 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1467 | case 18: |
ad80a810 | 1468 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1469 | break; |
1470 | case 24: | |
ad80a810 | 1471 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1472 | break; |
1473 | case 30: | |
ad80a810 | 1474 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1475 | break; |
1476 | case 36: | |
ad80a810 | 1477 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1478 | break; |
1479 | default: | |
4e53c2e0 | 1480 | BUG(); |
dfcef252 | 1481 | } |
72662e10 | 1482 | |
6e3c9717 | 1483 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1484 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1485 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1486 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1487 | |
e6f0bfc4 PZ |
1488 | if (cpu_transcoder == TRANSCODER_EDP) { |
1489 | switch (pipe) { | |
1490 | case PIPE_A: | |
c7670b10 PZ |
1491 | /* On Haswell, can only use the always-on power well for |
1492 | * eDP when not using the panel fitter, and when not | |
1493 | * using motion blur mitigation (which we don't | |
1494 | * support). */ | |
fabf6e51 | 1495 | if (IS_HASWELL(dev) && |
6e3c9717 ACO |
1496 | (intel_crtc->config->pch_pfit.enabled || |
1497 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1498 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1499 | else | |
1500 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1501 | break; |
1502 | case PIPE_B: | |
1503 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1504 | break; | |
1505 | case PIPE_C: | |
1506 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1507 | break; | |
1508 | default: | |
1509 | BUG(); | |
1510 | break; | |
1511 | } | |
1512 | } | |
1513 | ||
7739c33b | 1514 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1515 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1516 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1517 | else |
ad80a810 | 1518 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 1519 | |
7739c33b | 1520 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1521 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1522 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
7739c33b PZ |
1523 | |
1524 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
1525 | type == INTEL_OUTPUT_EDP) { | |
1526 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1527 | ||
0e32b39c DA |
1528 | if (intel_dp->is_mst) { |
1529 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1530 | } else | |
1531 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
1532 | ||
1533 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
1534 | } else if (type == INTEL_OUTPUT_DP_MST) { | |
1535 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; | |
1536 | ||
1537 | if (intel_dp->is_mst) { | |
1538 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1539 | } else | |
1540 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
7739c33b | 1541 | |
17aa6be9 | 1542 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 1543 | } else { |
84f44ce7 VS |
1544 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1545 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1546 | } |
1547 | ||
ad80a810 | 1548 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1549 | } |
72662e10 | 1550 | |
ad80a810 PZ |
1551 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1552 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1553 | { |
ad80a810 | 1554 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1555 | uint32_t val = I915_READ(reg); |
1556 | ||
0e32b39c | 1557 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1558 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1559 | I915_WRITE(reg, val); |
72662e10 ED |
1560 | } |
1561 | ||
bcbc889b PZ |
1562 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1563 | { | |
1564 | struct drm_device *dev = intel_connector->base.dev; | |
1565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1566 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
1567 | int type = intel_connector->base.connector_type; | |
1568 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1569 | enum pipe pipe = 0; | |
1570 | enum transcoder cpu_transcoder; | |
882244a3 | 1571 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
1572 | uint32_t tmp; |
1573 | ||
882244a3 | 1574 | power_domain = intel_display_port_power_domain(intel_encoder); |
f458ebbc | 1575 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1576 | return false; |
1577 | ||
bcbc889b PZ |
1578 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
1579 | return false; | |
1580 | ||
1581 | if (port == PORT_A) | |
1582 | cpu_transcoder = TRANSCODER_EDP; | |
1583 | else | |
1a240d4d | 1584 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1585 | |
1586 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1587 | ||
1588 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1589 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1590 | case TRANS_DDI_MODE_SELECT_DVI: | |
1591 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
1592 | ||
1593 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1594 | if (type == DRM_MODE_CONNECTOR_eDP) | |
1595 | return true; | |
bcbc889b | 1596 | return (type == DRM_MODE_CONNECTOR_DisplayPort); |
0e32b39c DA |
1597 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1598 | /* if the transcoder is in MST state then | |
1599 | * connector isn't connected */ | |
1600 | return false; | |
bcbc889b PZ |
1601 | |
1602 | case TRANS_DDI_MODE_SELECT_FDI: | |
1603 | return (type == DRM_MODE_CONNECTOR_VGA); | |
1604 | ||
1605 | default: | |
1606 | return false; | |
1607 | } | |
1608 | } | |
1609 | ||
85234cdc DV |
1610 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1611 | enum pipe *pipe) | |
1612 | { | |
1613 | struct drm_device *dev = encoder->base.dev; | |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1615 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1616 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1617 | u32 tmp; |
1618 | int i; | |
1619 | ||
6d129bea | 1620 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 1621 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
1622 | return false; |
1623 | ||
fe43d3f5 | 1624 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1625 | |
1626 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1627 | return false; | |
1628 | ||
ad80a810 PZ |
1629 | if (port == PORT_A) { |
1630 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1631 | |
ad80a810 PZ |
1632 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1633 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1634 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1635 | *pipe = PIPE_A; | |
1636 | break; | |
1637 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1638 | *pipe = PIPE_B; | |
1639 | break; | |
1640 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1641 | *pipe = PIPE_C; | |
1642 | break; | |
1643 | } | |
1644 | ||
1645 | return true; | |
1646 | } else { | |
1647 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1648 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1649 | ||
1650 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1651 | == TRANS_DDI_SELECT_PORT(port)) { | |
0e32b39c DA |
1652 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
1653 | return false; | |
1654 | ||
ad80a810 PZ |
1655 | *pipe = i; |
1656 | return true; | |
1657 | } | |
85234cdc DV |
1658 | } |
1659 | } | |
1660 | ||
84f44ce7 | 1661 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1662 | |
22f9fe50 | 1663 | return false; |
85234cdc DV |
1664 | } |
1665 | ||
fc914639 PZ |
1666 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1667 | { | |
1668 | struct drm_crtc *crtc = &intel_crtc->base; | |
1669 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1670 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1671 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 1672 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1673 | |
bb523fc0 PZ |
1674 | if (cpu_transcoder != TRANSCODER_EDP) |
1675 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1676 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1677 | } |
1678 | ||
1679 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1680 | { | |
1681 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
6e3c9717 | 1682 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1683 | |
bb523fc0 PZ |
1684 | if (cpu_transcoder != TRANSCODER_EDP) |
1685 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1686 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1687 | } |
1688 | ||
00c09d70 | 1689 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1690 | { |
c19b0669 | 1691 | struct drm_encoder *encoder = &intel_encoder->base; |
efa80add S |
1692 | struct drm_device *dev = encoder->dev; |
1693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
30cf6db8 | 1694 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1695 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1696 | int type = intel_encoder->type; |
6441ab5f | 1697 | |
82a4d9c0 PZ |
1698 | if (type == INTEL_OUTPUT_EDP) { |
1699 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1700 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1701 | } |
6441ab5f | 1702 | |
efa80add | 1703 | if (IS_SKYLAKE(dev)) { |
6e3c9717 | 1704 | uint32_t dpll = crtc->config->ddi_pll_sel; |
efa80add S |
1705 | uint32_t val; |
1706 | ||
5416d871 DL |
1707 | /* |
1708 | * DPLL0 is used for eDP and is the only "private" DPLL (as | |
1709 | * opposed to shared) on SKL | |
1710 | */ | |
1711 | if (type == INTEL_OUTPUT_EDP) { | |
1712 | WARN_ON(dpll != SKL_DPLL0); | |
1713 | ||
1714 | val = I915_READ(DPLL_CTRL1); | |
1715 | ||
1716 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | | |
1717 | DPLL_CTRL1_SSC(dpll) | | |
1718 | DPLL_CRTL1_LINK_RATE_MASK(dpll)); | |
6e3c9717 | 1719 | val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); |
5416d871 DL |
1720 | |
1721 | I915_WRITE(DPLL_CTRL1, val); | |
1722 | POSTING_READ(DPLL_CTRL1); | |
1723 | } | |
1724 | ||
1725 | /* DDI -> PLL mapping */ | |
efa80add S |
1726 | val = I915_READ(DPLL_CTRL2); |
1727 | ||
1728 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
1729 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
1730 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | | |
1731 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); | |
1732 | ||
1733 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 1734 | |
1ab23380 | 1735 | } else if (INTEL_INFO(dev)->gen < 9) { |
6e3c9717 ACO |
1736 | WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
1737 | I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); | |
efa80add | 1738 | } |
c19b0669 | 1739 | |
82a4d9c0 | 1740 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1741 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1742 | |
44905a27 | 1743 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1744 | |
1745 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1746 | intel_dp_start_link_train(intel_dp); | |
1747 | intel_dp_complete_link_train(intel_dp); | |
23f08d83 | 1748 | if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) |
3ab9c637 | 1749 | intel_dp_stop_link_train(intel_dp); |
30cf6db8 DV |
1750 | } else if (type == INTEL_OUTPUT_HDMI) { |
1751 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1752 | ||
1753 | intel_hdmi->set_infoframes(encoder, | |
6e3c9717 ACO |
1754 | crtc->config->has_hdmi_sink, |
1755 | &crtc->config->base.adjusted_mode); | |
c19b0669 | 1756 | } |
6441ab5f PZ |
1757 | } |
1758 | ||
00c09d70 | 1759 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1760 | { |
1761 | struct drm_encoder *encoder = &intel_encoder->base; | |
efa80add S |
1762 | struct drm_device *dev = encoder->dev; |
1763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6441ab5f | 1764 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1765 | int type = intel_encoder->type; |
2886e93f | 1766 | uint32_t val; |
a836bdf9 | 1767 | bool wait = false; |
2886e93f PZ |
1768 | |
1769 | val = I915_READ(DDI_BUF_CTL(port)); | |
1770 | if (val & DDI_BUF_CTL_ENABLE) { | |
1771 | val &= ~DDI_BUF_CTL_ENABLE; | |
1772 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1773 | wait = true; |
2886e93f | 1774 | } |
6441ab5f | 1775 | |
a836bdf9 PZ |
1776 | val = I915_READ(DP_TP_CTL(port)); |
1777 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1778 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1779 | I915_WRITE(DP_TP_CTL(port), val); | |
1780 | ||
1781 | if (wait) | |
1782 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1783 | ||
76bb80ed | 1784 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1785 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1786 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1787 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1788 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1789 | } |
1790 | ||
efa80add S |
1791 | if (IS_SKYLAKE(dev)) |
1792 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | | |
1793 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
1ab23380 | 1794 | else if (INTEL_INFO(dev)->gen < 9) |
efa80add | 1795 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
6441ab5f PZ |
1796 | } |
1797 | ||
00c09d70 | 1798 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1799 | { |
6547fef8 | 1800 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1801 | struct drm_crtc *crtc = encoder->crtc; |
1802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6547fef8 | 1803 | struct drm_device *dev = encoder->dev; |
72662e10 | 1804 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1805 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1806 | int type = intel_encoder->type; | |
72662e10 | 1807 | |
6547fef8 | 1808 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1809 | struct intel_digital_port *intel_dig_port = |
1810 | enc_to_dig_port(encoder); | |
1811 | ||
6547fef8 PZ |
1812 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1813 | * are ignored so nothing special needs to be done besides | |
1814 | * enabling the port. | |
1815 | */ | |
876a8cdf | 1816 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1817 | intel_dig_port->saved_port_bits | |
1818 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1819 | } else if (type == INTEL_OUTPUT_EDP) { |
1820 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1821 | ||
23f08d83 | 1822 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
3ab9c637 ID |
1823 | intel_dp_stop_link_train(intel_dp); |
1824 | ||
4be73780 | 1825 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 1826 | intel_psr_enable(intel_dp); |
c395578e | 1827 | intel_edp_drrs_enable(intel_dp); |
6547fef8 | 1828 | } |
7b9f35a6 | 1829 | |
6e3c9717 | 1830 | if (intel_crtc->config->has_audio) { |
d45a0bf5 | 1831 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
69bfe1a9 | 1832 | intel_audio_codec_enable(intel_encoder); |
7b9f35a6 | 1833 | } |
5ab432ef DV |
1834 | } |
1835 | ||
00c09d70 | 1836 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1837 | { |
d6c50ff8 | 1838 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1839 | struct drm_crtc *crtc = encoder->crtc; |
1840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d6c50ff8 | 1841 | int type = intel_encoder->type; |
7b9f35a6 WX |
1842 | struct drm_device *dev = encoder->dev; |
1843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6c50ff8 | 1844 | |
6e3c9717 | 1845 | if (intel_crtc->config->has_audio) { |
69bfe1a9 | 1846 | intel_audio_codec_disable(intel_encoder); |
d45a0bf5 PZ |
1847 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
1848 | } | |
2831d842 | 1849 | |
d6c50ff8 PZ |
1850 | if (type == INTEL_OUTPUT_EDP) { |
1851 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1852 | ||
c395578e | 1853 | intel_edp_drrs_disable(intel_dp); |
0bc12bcb | 1854 | intel_psr_disable(intel_dp); |
4be73780 | 1855 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1856 | } |
72662e10 | 1857 | } |
79f689aa | 1858 | |
e0b01be4 DV |
1859 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
1860 | struct intel_shared_dpll *pll) | |
1861 | { | |
3e369b76 | 1862 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
e0b01be4 DV |
1863 | POSTING_READ(WRPLL_CTL(pll->id)); |
1864 | udelay(20); | |
1865 | } | |
1866 | ||
12030431 DV |
1867 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
1868 | struct intel_shared_dpll *pll) | |
1869 | { | |
1870 | uint32_t val; | |
1871 | ||
1872 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
1873 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
1874 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1875 | } | |
1876 | ||
d452c5b6 DV |
1877 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
1878 | struct intel_shared_dpll *pll, | |
1879 | struct intel_dpll_hw_state *hw_state) | |
1880 | { | |
1881 | uint32_t val; | |
1882 | ||
f458ebbc | 1883 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
d452c5b6 DV |
1884 | return false; |
1885 | ||
1886 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1887 | hw_state->wrpll = val; | |
1888 | ||
1889 | return val & WRPLL_PLL_ENABLE; | |
1890 | } | |
1891 | ||
ca1381b5 | 1892 | static const char * const hsw_ddi_pll_names[] = { |
9cd86933 DV |
1893 | "WRPLL 1", |
1894 | "WRPLL 2", | |
1895 | }; | |
1896 | ||
143b307c | 1897 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
79f689aa | 1898 | { |
9cd86933 DV |
1899 | int i; |
1900 | ||
716c2e55 | 1901 | dev_priv->num_shared_dpll = 2; |
9cd86933 | 1902 | |
716c2e55 | 1903 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9cd86933 DV |
1904 | dev_priv->shared_dplls[i].id = i; |
1905 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
12030431 | 1906 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
e0b01be4 | 1907 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
d452c5b6 DV |
1908 | dev_priv->shared_dplls[i].get_hw_state = |
1909 | hsw_ddi_pll_get_hw_state; | |
9cd86933 | 1910 | } |
143b307c DL |
1911 | } |
1912 | ||
d1a2dc78 S |
1913 | static const char * const skl_ddi_pll_names[] = { |
1914 | "DPLL 1", | |
1915 | "DPLL 2", | |
1916 | "DPLL 3", | |
1917 | }; | |
1918 | ||
1919 | struct skl_dpll_regs { | |
1920 | u32 ctl, cfgcr1, cfgcr2; | |
1921 | }; | |
1922 | ||
1923 | /* this array is indexed by the *shared* pll id */ | |
1924 | static const struct skl_dpll_regs skl_dpll_regs[3] = { | |
1925 | { | |
1926 | /* DPLL 1 */ | |
1927 | .ctl = LCPLL2_CTL, | |
1928 | .cfgcr1 = DPLL1_CFGCR1, | |
1929 | .cfgcr2 = DPLL1_CFGCR2, | |
1930 | }, | |
1931 | { | |
1932 | /* DPLL 2 */ | |
1933 | .ctl = WRPLL_CTL1, | |
1934 | .cfgcr1 = DPLL2_CFGCR1, | |
1935 | .cfgcr2 = DPLL2_CFGCR2, | |
1936 | }, | |
1937 | { | |
1938 | /* DPLL 3 */ | |
1939 | .ctl = WRPLL_CTL2, | |
1940 | .cfgcr1 = DPLL3_CFGCR1, | |
1941 | .cfgcr2 = DPLL3_CFGCR2, | |
1942 | }, | |
1943 | }; | |
1944 | ||
1945 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
1946 | struct intel_shared_dpll *pll) | |
1947 | { | |
1948 | uint32_t val; | |
1949 | unsigned int dpll; | |
1950 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
1951 | ||
1952 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
1953 | dpll = pll->id + 1; | |
1954 | ||
1955 | val = I915_READ(DPLL_CTRL1); | |
1956 | ||
1957 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | | |
1958 | DPLL_CRTL1_LINK_RATE_MASK(dpll)); | |
1959 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); | |
1960 | ||
1961 | I915_WRITE(DPLL_CTRL1, val); | |
1962 | POSTING_READ(DPLL_CTRL1); | |
1963 | ||
1964 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); | |
1965 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); | |
1966 | POSTING_READ(regs[pll->id].cfgcr1); | |
1967 | POSTING_READ(regs[pll->id].cfgcr2); | |
1968 | ||
1969 | /* the enable bit is always bit 31 */ | |
1970 | I915_WRITE(regs[pll->id].ctl, | |
1971 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); | |
1972 | ||
1973 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) | |
1974 | DRM_ERROR("DPLL %d not locked\n", dpll); | |
1975 | } | |
1976 | ||
1977 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
1978 | struct intel_shared_dpll *pll) | |
1979 | { | |
1980 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
1981 | ||
1982 | /* the enable bit is always bit 31 */ | |
1983 | I915_WRITE(regs[pll->id].ctl, | |
1984 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); | |
1985 | POSTING_READ(regs[pll->id].ctl); | |
1986 | } | |
1987 | ||
1988 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
1989 | struct intel_shared_dpll *pll, | |
1990 | struct intel_dpll_hw_state *hw_state) | |
1991 | { | |
1992 | uint32_t val; | |
1993 | unsigned int dpll; | |
1994 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
1995 | ||
1996 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
1997 | return false; | |
1998 | ||
1999 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
2000 | dpll = pll->id + 1; | |
2001 | ||
2002 | val = I915_READ(regs[pll->id].ctl); | |
2003 | if (!(val & LCPLL_PLL_ENABLE)) | |
2004 | return false; | |
2005 | ||
2006 | val = I915_READ(DPLL_CTRL1); | |
2007 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; | |
2008 | ||
2009 | /* avoid reading back stale values if HDMI mode is not enabled */ | |
2010 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
2011 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); | |
2012 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); | |
2013 | } | |
2014 | ||
2015 | return true; | |
2016 | } | |
2017 | ||
2018 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2019 | { | |
2020 | int i; | |
2021 | ||
2022 | dev_priv->num_shared_dpll = 3; | |
2023 | ||
2024 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2025 | dev_priv->shared_dplls[i].id = i; | |
2026 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; | |
2027 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; | |
2028 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; | |
2029 | dev_priv->shared_dplls[i].get_hw_state = | |
2030 | skl_ddi_pll_get_hw_state; | |
2031 | } | |
2032 | } | |
2033 | ||
5c6706e5 VK |
2034 | static void broxton_phy_init(struct drm_i915_private *dev_priv, |
2035 | enum dpio_phy phy) | |
2036 | { | |
2037 | enum port port; | |
2038 | uint32_t val; | |
2039 | ||
2040 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
2041 | val |= GT_DISPLAY_POWER_ON(phy); | |
2042 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
2043 | ||
2044 | /* Considering 10ms timeout until BSpec is updated */ | |
2045 | if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) | |
2046 | DRM_ERROR("timeout during PHY%d power on\n", phy); | |
2047 | ||
2048 | for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); | |
2049 | port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { | |
2050 | int lane; | |
2051 | ||
2052 | for (lane = 0; lane < 4; lane++) { | |
2053 | val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
2054 | /* | |
2055 | * Note that on CHV this flag is called UPAR, but has | |
2056 | * the same function. | |
2057 | */ | |
2058 | val &= ~LATENCY_OPTIM; | |
2059 | if (lane != 1) | |
2060 | val |= LATENCY_OPTIM; | |
2061 | ||
2062 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); | |
2063 | } | |
2064 | } | |
2065 | ||
2066 | /* Program PLL Rcomp code offset */ | |
2067 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
2068 | val &= ~IREF0RC_OFFSET_MASK; | |
2069 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
2070 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
2071 | ||
2072 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
2073 | val &= ~IREF1RC_OFFSET_MASK; | |
2074 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
2075 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
2076 | ||
2077 | /* Program power gating */ | |
2078 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
2079 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
2080 | SUS_CLK_CONFIG; | |
2081 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
2082 | ||
2083 | if (phy == DPIO_PHY0) { | |
2084 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); | |
2085 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; | |
2086 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); | |
2087 | } | |
2088 | ||
2089 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); | |
2090 | val &= ~OCL2_LDOFUSE_PWR_DIS; | |
2091 | /* | |
2092 | * On PHY1 disable power on the second channel, since no port is | |
2093 | * connected there. On PHY0 both channels have a port, so leave it | |
2094 | * enabled. | |
2095 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should | |
2096 | * power down the second channel on PHY0 as well. | |
2097 | */ | |
2098 | if (phy == DPIO_PHY1) | |
2099 | val |= OCL2_LDOFUSE_PWR_DIS; | |
2100 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); | |
2101 | ||
2102 | if (phy == DPIO_PHY0) { | |
2103 | uint32_t grc_code; | |
2104 | /* | |
2105 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
2106 | * the corresponding calibrated value from PHY1, and disable | |
2107 | * the automatic calibration on PHY0. | |
2108 | */ | |
2109 | if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, | |
2110 | 10)) | |
2111 | DRM_ERROR("timeout waiting for PHY1 GRC\n"); | |
2112 | ||
2113 | val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); | |
2114 | val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
2115 | grc_code = val << GRC_CODE_FAST_SHIFT | | |
2116 | val << GRC_CODE_SLOW_SHIFT | | |
2117 | val; | |
2118 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); | |
2119 | ||
2120 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); | |
2121 | val |= GRC_DIS | GRC_RDY_OVRD; | |
2122 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); | |
2123 | } | |
2124 | ||
2125 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2126 | val |= COMMON_RESET_DIS; | |
2127 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2128 | } | |
2129 | ||
2130 | void broxton_ddi_phy_init(struct drm_device *dev) | |
2131 | { | |
2132 | /* Enable PHY1 first since it provides Rcomp for PHY0 */ | |
2133 | broxton_phy_init(dev->dev_private, DPIO_PHY1); | |
2134 | broxton_phy_init(dev->dev_private, DPIO_PHY0); | |
2135 | } | |
2136 | ||
2137 | static void broxton_phy_uninit(struct drm_i915_private *dev_priv, | |
2138 | enum dpio_phy phy) | |
2139 | { | |
2140 | uint32_t val; | |
2141 | ||
2142 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2143 | val &= ~COMMON_RESET_DIS; | |
2144 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2145 | } | |
2146 | ||
2147 | void broxton_ddi_phy_uninit(struct drm_device *dev) | |
2148 | { | |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2150 | ||
2151 | broxton_phy_uninit(dev_priv, DPIO_PHY1); | |
2152 | broxton_phy_uninit(dev_priv, DPIO_PHY0); | |
2153 | ||
2154 | /* FIXME: do this in broxton_phy_uninit per phy */ | |
2155 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); | |
2156 | } | |
2157 | ||
dfb82408 S |
2158 | static const char * const bxt_ddi_pll_names[] = { |
2159 | "PORT PLL A", | |
2160 | "PORT PLL B", | |
2161 | "PORT PLL C", | |
2162 | }; | |
2163 | ||
2164 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
2165 | struct intel_shared_dpll *pll) | |
2166 | { | |
2167 | uint32_t temp; | |
2168 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2169 | ||
2170 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2171 | temp &= ~PORT_PLL_REF_SEL; | |
2172 | /* Non-SSC reference */ | |
2173 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2174 | ||
2175 | /* Disable 10 bit clock */ | |
2176 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2177 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; | |
2178 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2179 | ||
2180 | /* Write P1 & P2 */ | |
2181 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
2182 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); | |
2183 | temp |= pll->config.hw_state.ebb0; | |
2184 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); | |
2185 | ||
2186 | /* Write M2 integer */ | |
2187 | temp = I915_READ(BXT_PORT_PLL(port, 0)); | |
2188 | temp &= ~PORT_PLL_M2_MASK; | |
2189 | temp |= pll->config.hw_state.pll0; | |
2190 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); | |
2191 | ||
2192 | /* Write N */ | |
2193 | temp = I915_READ(BXT_PORT_PLL(port, 1)); | |
2194 | temp &= ~PORT_PLL_N_MASK; | |
2195 | temp |= pll->config.hw_state.pll1; | |
2196 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); | |
2197 | ||
2198 | /* Write M2 fraction */ | |
2199 | temp = I915_READ(BXT_PORT_PLL(port, 2)); | |
2200 | temp &= ~PORT_PLL_M2_FRAC_MASK; | |
2201 | temp |= pll->config.hw_state.pll2; | |
2202 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); | |
2203 | ||
2204 | /* Write M2 fraction enable */ | |
2205 | temp = I915_READ(BXT_PORT_PLL(port, 3)); | |
2206 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; | |
2207 | temp |= pll->config.hw_state.pll3; | |
2208 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); | |
2209 | ||
2210 | /* Write coeff */ | |
2211 | temp = I915_READ(BXT_PORT_PLL(port, 6)); | |
2212 | temp &= ~PORT_PLL_PROP_COEFF_MASK; | |
2213 | temp &= ~PORT_PLL_INT_COEFF_MASK; | |
2214 | temp &= ~PORT_PLL_GAIN_CTL_MASK; | |
2215 | temp |= pll->config.hw_state.pll6; | |
2216 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); | |
2217 | ||
2218 | /* Write calibration val */ | |
2219 | temp = I915_READ(BXT_PORT_PLL(port, 8)); | |
2220 | temp &= ~PORT_PLL_TARGET_CNT_MASK; | |
2221 | temp |= pll->config.hw_state.pll8; | |
2222 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); | |
2223 | ||
2224 | /* | |
2225 | * FIXME: program PORT_PLL_9/i_lockthresh according to the latest | |
2226 | * specification update. | |
2227 | */ | |
2228 | ||
2229 | /* Recalibrate with new settings */ | |
2230 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2231 | temp |= PORT_PLL_RECALIBRATE; | |
2232 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2233 | /* Enable 10 bit clock */ | |
2234 | temp |= PORT_PLL_10BIT_CLK_ENABLE; | |
2235 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2236 | ||
2237 | /* Enable PLL */ | |
2238 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2239 | temp |= PORT_PLL_ENABLE; | |
2240 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2241 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2242 | ||
2243 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & | |
2244 | PORT_PLL_LOCK), 200)) | |
2245 | DRM_ERROR("PLL %d not locked\n", port); | |
2246 | ||
2247 | /* | |
2248 | * While we write to the group register to program all lanes at once we | |
2249 | * can read only lane registers and we pick lanes 0/1 for that. | |
2250 | */ | |
2251 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
2252 | temp &= ~LANE_STAGGER_MASK; | |
2253 | temp &= ~LANESTAGGER_STRAP_OVRD; | |
2254 | temp |= pll->config.hw_state.pcsdw12; | |
2255 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); | |
2256 | } | |
2257 | ||
2258 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
2259 | struct intel_shared_dpll *pll) | |
2260 | { | |
2261 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2262 | uint32_t temp; | |
2263 | ||
2264 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2265 | temp &= ~PORT_PLL_ENABLE; | |
2266 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2267 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2268 | } | |
2269 | ||
2270 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
2271 | struct intel_shared_dpll *pll, | |
2272 | struct intel_dpll_hw_state *hw_state) | |
2273 | { | |
2274 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2275 | uint32_t val; | |
2276 | ||
2277 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
2278 | return false; | |
2279 | ||
2280 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2281 | if (!(val & PORT_PLL_ENABLE)) | |
2282 | return false; | |
2283 | ||
2284 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
2285 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); | |
2286 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); | |
2287 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); | |
2288 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); | |
2289 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); | |
2290 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); | |
2291 | /* | |
2292 | * While we write to the group register to program all lanes at once we | |
2293 | * can read only lane registers. We configure all lanes the same way, so | |
2294 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. | |
2295 | */ | |
2296 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
2297 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12)) | |
2298 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", | |
2299 | hw_state->pcsdw12, | |
2300 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); | |
2301 | ||
2302 | return true; | |
2303 | } | |
2304 | ||
2305 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2306 | { | |
2307 | int i; | |
2308 | ||
2309 | dev_priv->num_shared_dpll = 3; | |
2310 | ||
2311 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2312 | dev_priv->shared_dplls[i].id = i; | |
2313 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; | |
2314 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; | |
2315 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; | |
2316 | dev_priv->shared_dplls[i].get_hw_state = | |
2317 | bxt_ddi_pll_get_hw_state; | |
2318 | } | |
2319 | } | |
2320 | ||
143b307c DL |
2321 | void intel_ddi_pll_init(struct drm_device *dev) |
2322 | { | |
2323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2324 | uint32_t val = I915_READ(LCPLL_CTL); | |
2325 | ||
d1a2dc78 S |
2326 | if (IS_SKYLAKE(dev)) |
2327 | skl_shared_dplls_init(dev_priv); | |
dfb82408 S |
2328 | else if (IS_BROXTON(dev)) |
2329 | bxt_shared_dplls_init(dev_priv); | |
d1a2dc78 S |
2330 | else |
2331 | hsw_shared_dplls_init(dev_priv); | |
79f689aa | 2332 | |
b2b877ff | 2333 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
1652d19e | 2334 | dev_priv->display.get_display_clock_speed(dev)); |
79f689aa | 2335 | |
121643c2 S |
2336 | if (IS_SKYLAKE(dev)) { |
2337 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) | |
2338 | DRM_ERROR("LCPLL1 is disabled\n"); | |
f8437dd1 VK |
2339 | } else if (IS_BROXTON(dev)) { |
2340 | broxton_init_cdclk(dev); | |
5c6706e5 | 2341 | broxton_ddi_phy_init(dev); |
121643c2 S |
2342 | } else { |
2343 | /* | |
2344 | * The LCPLL register should be turned on by the BIOS. For now | |
2345 | * let's just check its state and print errors in case | |
2346 | * something is wrong. Don't even try to turn it on. | |
2347 | */ | |
2348 | ||
2349 | if (val & LCPLL_CD_SOURCE_FCLK) | |
2350 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
79f689aa | 2351 | |
121643c2 S |
2352 | if (val & LCPLL_PLL_DISABLE) |
2353 | DRM_ERROR("LCPLL is disabled\n"); | |
2354 | } | |
79f689aa | 2355 | } |
c19b0669 PZ |
2356 | |
2357 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
2358 | { | |
174edf1f PZ |
2359 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2360 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 2361 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 2362 | enum port port = intel_dig_port->port; |
c19b0669 | 2363 | uint32_t val; |
f3e227df | 2364 | bool wait = false; |
c19b0669 PZ |
2365 | |
2366 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
2367 | val = I915_READ(DDI_BUF_CTL(port)); | |
2368 | if (val & DDI_BUF_CTL_ENABLE) { | |
2369 | val &= ~DDI_BUF_CTL_ENABLE; | |
2370 | I915_WRITE(DDI_BUF_CTL(port), val); | |
2371 | wait = true; | |
2372 | } | |
2373 | ||
2374 | val = I915_READ(DP_TP_CTL(port)); | |
2375 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2376 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2377 | I915_WRITE(DP_TP_CTL(port), val); | |
2378 | POSTING_READ(DP_TP_CTL(port)); | |
2379 | ||
2380 | if (wait) | |
2381 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2382 | } | |
2383 | ||
0e32b39c | 2384 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 2385 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
0e32b39c DA |
2386 | if (intel_dp->is_mst) |
2387 | val |= DP_TP_CTL_MODE_MST; | |
2388 | else { | |
2389 | val |= DP_TP_CTL_MODE_SST; | |
2390 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2391 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
2392 | } | |
c19b0669 PZ |
2393 | I915_WRITE(DP_TP_CTL(port), val); |
2394 | POSTING_READ(DP_TP_CTL(port)); | |
2395 | ||
2396 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
2397 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
2398 | POSTING_READ(DDI_BUF_CTL(port)); | |
2399 | ||
2400 | udelay(600); | |
2401 | } | |
00c09d70 | 2402 | |
1ad960f2 PZ |
2403 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
2404 | { | |
2405 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
2406 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
2407 | uint32_t val; | |
2408 | ||
2409 | intel_ddi_post_disable(intel_encoder); | |
2410 | ||
2411 | val = I915_READ(_FDI_RXA_CTL); | |
2412 | val &= ~FDI_RX_ENABLE; | |
2413 | I915_WRITE(_FDI_RXA_CTL, val); | |
2414 | ||
2415 | val = I915_READ(_FDI_RXA_MISC); | |
2416 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
2417 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
2418 | I915_WRITE(_FDI_RXA_MISC, val); | |
2419 | ||
2420 | val = I915_READ(_FDI_RXA_CTL); | |
2421 | val &= ~FDI_PCDCLK; | |
2422 | I915_WRITE(_FDI_RXA_CTL, val); | |
2423 | ||
2424 | val = I915_READ(_FDI_RXA_CTL); | |
2425 | val &= ~FDI_RX_PLL_ENABLE; | |
2426 | I915_WRITE(_FDI_RXA_CTL, val); | |
2427 | } | |
2428 | ||
00c09d70 PZ |
2429 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
2430 | { | |
0e32b39c DA |
2431 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
2432 | int type = intel_dig_port->base.type; | |
2433 | ||
2434 | if (type != INTEL_OUTPUT_DISPLAYPORT && | |
2435 | type != INTEL_OUTPUT_EDP && | |
2436 | type != INTEL_OUTPUT_UNKNOWN) { | |
2437 | return; | |
2438 | } | |
00c09d70 | 2439 | |
0e32b39c | 2440 | intel_dp_hot_plug(intel_encoder); |
00c09d70 PZ |
2441 | } |
2442 | ||
6801c18c | 2443 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 2444 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2445 | { |
2446 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
2447 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
0cb09a97 | 2448 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 2449 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
2450 | u32 temp, flags = 0; |
2451 | ||
2452 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
2453 | if (temp & TRANS_DDI_PHSYNC) | |
2454 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2455 | else | |
2456 | flags |= DRM_MODE_FLAG_NHSYNC; | |
2457 | if (temp & TRANS_DDI_PVSYNC) | |
2458 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2459 | else | |
2460 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2461 | ||
2d112de7 | 2462 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2463 | |
2464 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2465 | case TRANS_DDI_BPC_6: | |
2466 | pipe_config->pipe_bpp = 18; | |
2467 | break; | |
2468 | case TRANS_DDI_BPC_8: | |
2469 | pipe_config->pipe_bpp = 24; | |
2470 | break; | |
2471 | case TRANS_DDI_BPC_10: | |
2472 | pipe_config->pipe_bpp = 30; | |
2473 | break; | |
2474 | case TRANS_DDI_BPC_12: | |
2475 | pipe_config->pipe_bpp = 36; | |
2476 | break; | |
2477 | default: | |
2478 | break; | |
2479 | } | |
eb14cb74 VS |
2480 | |
2481 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2482 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2483 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
2484 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2485 | ||
2486 | if (intel_hdmi->infoframe_enabled(&encoder->base)) | |
2487 | pipe_config->has_infoframe = true; | |
cbc572a9 | 2488 | break; |
eb14cb74 VS |
2489 | case TRANS_DDI_MODE_SELECT_DVI: |
2490 | case TRANS_DDI_MODE_SELECT_FDI: | |
2491 | break; | |
2492 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2493 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
2494 | pipe_config->has_dp_encoder = true; | |
2495 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
2496 | break; | |
2497 | default: | |
2498 | break; | |
2499 | } | |
10214420 | 2500 | |
f458ebbc | 2501 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
a60551b1 | 2502 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 2503 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
a60551b1 PZ |
2504 | pipe_config->has_audio = true; |
2505 | } | |
9ed109a7 | 2506 | |
10214420 DV |
2507 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
2508 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
2509 | /* | |
2510 | * This is a big fat ugly hack. | |
2511 | * | |
2512 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2513 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2514 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2515 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2516 | * max, not what it tells us to use. | |
2517 | * | |
2518 | * Note: This will still be broken if the eDP panel is not lit | |
2519 | * up by the BIOS, and thus we can't get the mode at module | |
2520 | * load. | |
2521 | */ | |
2522 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
2523 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
2524 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
2525 | } | |
11578553 | 2526 | |
22606a18 | 2527 | intel_ddi_clock_get(encoder, pipe_config); |
045ac3b5 JB |
2528 | } |
2529 | ||
00c09d70 PZ |
2530 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
2531 | { | |
2532 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
2533 | intel_dp_encoder_destroy(encoder); | |
2534 | } | |
2535 | ||
5bfe2ac0 | 2536 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
5cec258b | 2537 | struct intel_crtc_state *pipe_config) |
00c09d70 | 2538 | { |
5bfe2ac0 | 2539 | int type = encoder->type; |
eccb140b | 2540 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 2541 | |
5bfe2ac0 | 2542 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2543 | |
eccb140b DV |
2544 | if (port == PORT_A) |
2545 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2546 | ||
00c09d70 | 2547 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 2548 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 2549 | else |
5bfe2ac0 | 2550 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
2551 | } |
2552 | ||
2553 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
2554 | .destroy = intel_ddi_destroy, | |
2555 | }; | |
2556 | ||
4a28ae58 PZ |
2557 | static struct intel_connector * |
2558 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2559 | { | |
2560 | struct intel_connector *connector; | |
2561 | enum port port = intel_dig_port->port; | |
2562 | ||
9bdbd0b9 | 2563 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2564 | if (!connector) |
2565 | return NULL; | |
2566 | ||
2567 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2568 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2569 | kfree(connector); | |
2570 | return NULL; | |
2571 | } | |
2572 | ||
2573 | return connector; | |
2574 | } | |
2575 | ||
2576 | static struct intel_connector * | |
2577 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2578 | { | |
2579 | struct intel_connector *connector; | |
2580 | enum port port = intel_dig_port->port; | |
2581 | ||
9bdbd0b9 | 2582 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2583 | if (!connector) |
2584 | return NULL; | |
2585 | ||
2586 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2587 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2588 | ||
2589 | return connector; | |
2590 | } | |
2591 | ||
00c09d70 PZ |
2592 | void intel_ddi_init(struct drm_device *dev, enum port port) |
2593 | { | |
876a8cdf | 2594 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
2595 | struct intel_digital_port *intel_dig_port; |
2596 | struct intel_encoder *intel_encoder; | |
2597 | struct drm_encoder *encoder; | |
311a2094 PZ |
2598 | bool init_hdmi, init_dp; |
2599 | ||
2600 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2601 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2602 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
2603 | if (!init_dp && !init_hdmi) { | |
f68d697e | 2604 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
311a2094 PZ |
2605 | port_name(port)); |
2606 | init_hdmi = true; | |
2607 | init_dp = true; | |
2608 | } | |
00c09d70 | 2609 | |
b14c5679 | 2610 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2611 | if (!intel_dig_port) |
2612 | return; | |
2613 | ||
00c09d70 PZ |
2614 | intel_encoder = &intel_dig_port->base; |
2615 | encoder = &intel_encoder->base; | |
2616 | ||
2617 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
2618 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 2619 | |
5bfe2ac0 | 2620 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
2621 | intel_encoder->enable = intel_enable_ddi; |
2622 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
2623 | intel_encoder->disable = intel_disable_ddi; | |
2624 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2625 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2626 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
2627 | |
2628 | intel_dig_port->port = port; | |
bcf53de4 SM |
2629 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2630 | (DDI_BUF_PORT_REVERSAL | | |
2631 | DDI_A_4_LANES); | |
00c09d70 PZ |
2632 | |
2633 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
f68d697e | 2634 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2635 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
2636 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
2637 | ||
f68d697e CW |
2638 | if (init_dp) { |
2639 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2640 | goto err; | |
13cf5504 | 2641 | |
f68d697e CW |
2642 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
2643 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
2644 | } | |
21a8e6a4 | 2645 | |
311a2094 PZ |
2646 | /* In theory we don't need the encoder->type check, but leave it just in |
2647 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2648 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2649 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2650 | goto err; | |
21a8e6a4 | 2651 | } |
f68d697e CW |
2652 | |
2653 | return; | |
2654 | ||
2655 | err: | |
2656 | drm_encoder_cleanup(encoder); | |
2657 | kfree(intel_dig_port); | |
00c09d70 | 2658 | } |