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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 | 75 | static const u32 bdw_ddi_translations_edp[] = { |
e1b22732 | 76 | 0x00FFFFFF, 0x00000012, /* eDP parameters */ |
300644c7 PZ |
77 | 0x00EBAFFF, 0x00020011, |
78 | 0x00C71FFF, 0x0006000F, | |
9576c27f | 79 | 0x00AAAFFF, 0x000E000A, |
300644c7 PZ |
80 | 0x00FFFFFF, 0x00020011, |
81 | 0x00DB6FFF, 0x0005000F, | |
82 | 0x00BEEFFF, 0x000A000C, | |
83 | 0x00FFFFFF, 0x0005000F, | |
84 | 0x00DB6FFF, 0x000A000C, | |
300644c7 PZ |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
86 | }; | |
87 | ||
e58623cb AR |
88 | static const u32 bdw_ddi_translations_dp[] = { |
89 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
90 | 0x00D75FFF, 0x000E000A, | |
91 | 0x00BEFFFF, 0x00140006, | |
9576c27f | 92 | 0x80B2CFFF, 0x001B0002, |
e58623cb AR |
93 | 0x00FFFFFF, 0x000E000A, |
94 | 0x00D75FFF, 0x00180004, | |
95 | 0x80CB2FFF, 0x001B0002, | |
96 | 0x00F7DFFF, 0x00180004, | |
97 | 0x80D75FFF, 0x001B0002, | |
e58623cb AR |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
99 | }; | |
100 | ||
101 | static const u32 bdw_ddi_translations_fdi[] = { | |
102 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
103 | 0x00D75FFF, 0x0004000A, | |
104 | 0x00C30FFF, 0x00070006, | |
105 | 0x00AAAFFF, 0x000C0000, | |
106 | 0x00FFFFFF, 0x0004000A, | |
107 | 0x00D75FFF, 0x00090004, | |
108 | 0x00C30FFF, 0x000C0000, | |
109 | 0x00FFFFFF, 0x00070006, | |
110 | 0x00D75FFF, 0x000C0000, | |
111 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
112 | }; | |
113 | ||
20f4dbe4 | 114 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 115 | { |
0bdee30e | 116 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
117 | int type = intel_encoder->type; |
118 | ||
174edf1f | 119 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 120 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
121 | struct intel_digital_port *intel_dig_port = |
122 | enc_to_dig_port(encoder); | |
123 | return intel_dig_port->port; | |
0bdee30e | 124 | |
fc914639 PZ |
125 | } else if (type == INTEL_OUTPUT_ANALOG) { |
126 | return PORT_E; | |
0bdee30e | 127 | |
fc914639 PZ |
128 | } else { |
129 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
130 | BUG(); | |
131 | } | |
132 | } | |
133 | ||
e58623cb AR |
134 | /* |
135 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
136 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
137 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
138 | * in either FDI or DP modes only, as HDMI connections will work with both | |
139 | * of those | |
140 | */ | |
ad8d270c | 141 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | u32 reg; | |
145 | int i; | |
6acab15a | 146 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
147 | const u32 *ddi_translations_fdi; |
148 | const u32 *ddi_translations_dp; | |
300644c7 | 149 | const u32 *ddi_translations_edp; |
e58623cb AR |
150 | const u32 *ddi_translations; |
151 | ||
152 | if (IS_BROADWELL(dev)) { | |
153 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
154 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 155 | ddi_translations_edp = bdw_ddi_translations_edp; |
e58623cb AR |
156 | } else if (IS_HASWELL(dev)) { |
157 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
158 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 159 | ddi_translations_edp = hsw_ddi_translations_dp; |
e58623cb AR |
160 | } else { |
161 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 162 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
163 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
164 | ddi_translations_dp = bdw_ddi_translations_dp; | |
165 | } | |
166 | ||
300644c7 PZ |
167 | switch (port) { |
168 | case PORT_A: | |
169 | ddi_translations = ddi_translations_edp; | |
170 | break; | |
171 | case PORT_B: | |
172 | case PORT_C: | |
300644c7 PZ |
173 | ddi_translations = ddi_translations_dp; |
174 | break; | |
77d8d009 | 175 | case PORT_D: |
5d8a7752 | 176 | if (intel_dp_is_edp(dev, PORT_D)) |
77d8d009 PZ |
177 | ddi_translations = ddi_translations_edp; |
178 | else | |
179 | ddi_translations = ddi_translations_dp; | |
180 | break; | |
300644c7 PZ |
181 | case PORT_E: |
182 | ddi_translations = ddi_translations_fdi; | |
183 | break; | |
184 | default: | |
185 | BUG(); | |
186 | } | |
45244b87 | 187 | |
f72d19f0 PZ |
188 | for (i = 0, reg = DDI_BUF_TRANS(port); |
189 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
190 | I915_WRITE(reg, ddi_translations[i]); |
191 | reg += 4; | |
192 | } | |
6acab15a PZ |
193 | /* Entry 9 is for HDMI: */ |
194 | for (i = 0; i < 2; i++) { | |
195 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
196 | reg += 4; | |
197 | } | |
45244b87 ED |
198 | } |
199 | ||
200 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
201 | * mode and port E for FDI. | |
202 | */ | |
203 | void intel_prepare_ddi(struct drm_device *dev) | |
204 | { | |
205 | int port; | |
206 | ||
0d536cb4 PZ |
207 | if (!HAS_DDI(dev)) |
208 | return; | |
45244b87 | 209 | |
ad8d270c PZ |
210 | for (port = PORT_A; port <= PORT_E; port++) |
211 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 212 | } |
c82e4d26 ED |
213 | |
214 | static const long hsw_ddi_buf_ctl_values[] = { | |
215 | DDI_BUF_EMP_400MV_0DB_HSW, | |
216 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
217 | DDI_BUF_EMP_400MV_6DB_HSW, | |
218 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
219 | DDI_BUF_EMP_600MV_0DB_HSW, | |
220 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
221 | DDI_BUF_EMP_600MV_6DB_HSW, | |
222 | DDI_BUF_EMP_800MV_0DB_HSW, | |
223 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
224 | }; | |
225 | ||
248138b5 PZ |
226 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
227 | enum port port) | |
228 | { | |
229 | uint32_t reg = DDI_BUF_CTL(port); | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < 8; i++) { | |
233 | udelay(1); | |
234 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
235 | return; | |
236 | } | |
237 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
238 | } | |
c82e4d26 ED |
239 | |
240 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
241 | * connection to the PCH-located connectors. For this, it is necessary to train | |
242 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
243 | * | |
244 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
245 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
246 | * DDI A (which is used for eDP) | |
247 | */ | |
248 | ||
249 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
250 | { | |
251 | struct drm_device *dev = crtc->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 254 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 255 | |
04945641 PZ |
256 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
257 | * mode set "sequence for CRT port" document: | |
258 | * - TP1 to TP2 time with the default value | |
259 | * - FDI delay to 90h | |
8693a824 DL |
260 | * |
261 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
262 | */ |
263 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
264 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
265 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
266 | ||
267 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 268 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 269 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 270 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
271 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
272 | POSTING_READ(_FDI_RXA_CTL); | |
273 | udelay(220); | |
274 | ||
275 | /* Switch from Rawclk to PCDclk */ | |
276 | rx_ctl_val |= FDI_PCDCLK; | |
277 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
278 | ||
279 | /* Configure Port Clock Select */ | |
de7cfc63 DV |
280 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); |
281 | WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
282 | |
283 | /* Start the training iterating through available voltages and emphasis, | |
284 | * testing each value twice. */ | |
285 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
286 | /* Configure DP_TP_CTL with auto-training */ |
287 | I915_WRITE(DP_TP_CTL(PORT_E), | |
288 | DP_TP_CTL_FDI_AUTOTRAIN | | |
289 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
290 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
291 | DP_TP_CTL_ENABLE); | |
292 | ||
876a8cdf DL |
293 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
294 | * DDI E does not support port reversal, the functionality is | |
295 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
296 | * port reversal bit */ | |
c82e4d26 | 297 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 298 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 299 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
300 | hsw_ddi_buf_ctl_values[i / 2]); |
301 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
302 | |
303 | udelay(600); | |
304 | ||
04945641 PZ |
305 | /* Program PCH FDI Receiver TU */ |
306 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
307 | ||
308 | /* Enable PCH FDI Receiver with auto-training */ | |
309 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
310 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
311 | POSTING_READ(_FDI_RXA_CTL); | |
312 | ||
313 | /* Wait for FDI receiver lane calibration */ | |
314 | udelay(30); | |
315 | ||
316 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
317 | temp = I915_READ(_FDI_RXA_MISC); | |
318 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
319 | I915_WRITE(_FDI_RXA_MISC, temp); | |
320 | POSTING_READ(_FDI_RXA_MISC); | |
321 | ||
322 | /* Wait for FDI auto training time */ | |
323 | udelay(5); | |
c82e4d26 ED |
324 | |
325 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
326 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 327 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
328 | |
329 | /* Enable normal pixel sending for FDI */ | |
330 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
331 | DP_TP_CTL_FDI_AUTOTRAIN | |
332 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
333 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
334 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 335 | |
04945641 | 336 | return; |
c82e4d26 | 337 | } |
04945641 | 338 | |
248138b5 PZ |
339 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
340 | temp &= ~DDI_BUF_CTL_ENABLE; | |
341 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
342 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
343 | ||
04945641 | 344 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
345 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
346 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
347 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
348 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
349 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
350 | ||
351 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
352 | |
353 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
354 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 355 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
356 | |
357 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
358 | temp = I915_READ(_FDI_RXA_MISC); | |
359 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
360 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
361 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 362 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
363 | } |
364 | ||
04945641 | 365 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 366 | } |
0e72a5b5 | 367 | |
8d9ddbcb PZ |
368 | static struct intel_encoder * |
369 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
370 | { | |
371 | struct drm_device *dev = crtc->dev; | |
372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
373 | struct intel_encoder *intel_encoder, *ret = NULL; | |
374 | int num_encoders = 0; | |
375 | ||
376 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
377 | ret = intel_encoder; | |
378 | num_encoders++; | |
379 | } | |
380 | ||
381 | if (num_encoders != 1) | |
84f44ce7 VS |
382 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
383 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
384 | |
385 | BUG_ON(ret == NULL); | |
386 | return ret; | |
387 | } | |
388 | ||
6441ab5f PZ |
389 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
390 | { | |
391 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
392 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
394 | uint32_t val; | |
395 | ||
de7cfc63 | 396 | switch (intel_crtc->config.ddi_pll_sel) { |
6441ab5f PZ |
397 | case PORT_CLK_SEL_WRPLL1: |
398 | plls->wrpll1_refcount--; | |
399 | if (plls->wrpll1_refcount == 0) { | |
400 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
401 | val = I915_READ(WRPLL_CTL1); | |
402 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
403 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
404 | POSTING_READ(WRPLL_CTL1); | |
405 | } | |
0e50338c | 406 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; |
6441ab5f PZ |
407 | break; |
408 | case PORT_CLK_SEL_WRPLL2: | |
409 | plls->wrpll2_refcount--; | |
410 | if (plls->wrpll2_refcount == 0) { | |
411 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
412 | val = I915_READ(WRPLL_CTL2); | |
413 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
414 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
415 | POSTING_READ(WRPLL_CTL2); | |
416 | } | |
0e50338c | 417 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; |
6441ab5f PZ |
418 | break; |
419 | } | |
420 | ||
6441ab5f PZ |
421 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); |
422 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
6441ab5f PZ |
423 | } |
424 | ||
1c0b85c5 DL |
425 | #define LC_FREQ 2700 |
426 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
427 | ||
428 | #define P_MIN 2 | |
429 | #define P_MAX 64 | |
430 | #define P_INC 2 | |
431 | ||
432 | /* Constraints for PLL good behavior */ | |
433 | #define REF_MIN 48 | |
434 | #define REF_MAX 400 | |
435 | #define VCO_MIN 2400 | |
436 | #define VCO_MAX 4800 | |
437 | ||
438 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
439 | ||
440 | struct wrpll_rnp { | |
441 | unsigned p, n2, r2; | |
442 | }; | |
443 | ||
444 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 445 | { |
1c0b85c5 DL |
446 | unsigned budget; |
447 | ||
448 | switch (clock) { | |
449 | case 25175000: | |
450 | case 25200000: | |
451 | case 27000000: | |
452 | case 27027000: | |
453 | case 37762500: | |
454 | case 37800000: | |
455 | case 40500000: | |
456 | case 40541000: | |
457 | case 54000000: | |
458 | case 54054000: | |
459 | case 59341000: | |
460 | case 59400000: | |
461 | case 72000000: | |
462 | case 74176000: | |
463 | case 74250000: | |
464 | case 81000000: | |
465 | case 81081000: | |
466 | case 89012000: | |
467 | case 89100000: | |
468 | case 108000000: | |
469 | case 108108000: | |
470 | case 111264000: | |
471 | case 111375000: | |
472 | case 148352000: | |
473 | case 148500000: | |
474 | case 162000000: | |
475 | case 162162000: | |
476 | case 222525000: | |
477 | case 222750000: | |
478 | case 296703000: | |
479 | case 297000000: | |
480 | budget = 0; | |
481 | break; | |
482 | case 233500000: | |
483 | case 245250000: | |
484 | case 247750000: | |
485 | case 253250000: | |
486 | case 298000000: | |
487 | budget = 1500; | |
488 | break; | |
489 | case 169128000: | |
490 | case 169500000: | |
491 | case 179500000: | |
492 | case 202000000: | |
493 | budget = 2000; | |
494 | break; | |
495 | case 256250000: | |
496 | case 262500000: | |
497 | case 270000000: | |
498 | case 272500000: | |
499 | case 273750000: | |
500 | case 280750000: | |
501 | case 281250000: | |
502 | case 286000000: | |
503 | case 291750000: | |
504 | budget = 4000; | |
505 | break; | |
506 | case 267250000: | |
507 | case 268500000: | |
508 | budget = 5000; | |
509 | break; | |
510 | default: | |
511 | budget = 1000; | |
512 | break; | |
513 | } | |
6441ab5f | 514 | |
1c0b85c5 DL |
515 | return budget; |
516 | } | |
517 | ||
518 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
519 | unsigned r2, unsigned n2, unsigned p, | |
520 | struct wrpll_rnp *best) | |
521 | { | |
522 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 523 | |
1c0b85c5 DL |
524 | /* No best (r,n,p) yet */ |
525 | if (best->p == 0) { | |
526 | best->p = p; | |
527 | best->n2 = n2; | |
528 | best->r2 = r2; | |
529 | return; | |
530 | } | |
6441ab5f | 531 | |
1c0b85c5 DL |
532 | /* |
533 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
534 | * freq2k. | |
535 | * | |
536 | * delta = 1e6 * | |
537 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
538 | * freq2k; | |
539 | * | |
540 | * and we would like delta <= budget. | |
541 | * | |
542 | * If the discrepancy is above the PPM-based budget, always prefer to | |
543 | * improve upon the previous solution. However, if you're within the | |
544 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
545 | */ | |
546 | a = freq2k * budget * p * r2; | |
547 | b = freq2k * budget * best->p * best->r2; | |
548 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
549 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
550 | (LC_FREQ_2K * best->n2)); | |
551 | c = 1000000 * diff; | |
552 | d = 1000000 * diff_best; | |
553 | ||
554 | if (a < c && b < d) { | |
555 | /* If both are above the budget, pick the closer */ | |
556 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
557 | best->p = p; | |
558 | best->n2 = n2; | |
559 | best->r2 = r2; | |
560 | } | |
561 | } else if (a >= c && b < d) { | |
562 | /* If A is below the threshold but B is above it? Update. */ | |
563 | best->p = p; | |
564 | best->n2 = n2; | |
565 | best->r2 = r2; | |
566 | } else if (a >= c && b >= d) { | |
567 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
568 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
569 | best->p = p; | |
570 | best->n2 = n2; | |
571 | best->r2 = r2; | |
572 | } | |
573 | } | |
574 | /* Otherwise a < c && b >= d, do nothing */ | |
575 | } | |
576 | ||
11578553 JB |
577 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
578 | int reg) | |
579 | { | |
580 | int refclk = LC_FREQ; | |
581 | int n, p, r; | |
582 | u32 wrpll; | |
583 | ||
584 | wrpll = I915_READ(reg); | |
114fe488 DV |
585 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
586 | case WRPLL_PLL_SSC: | |
587 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
588 | /* |
589 | * We could calculate spread here, but our checking | |
590 | * code only cares about 5% accuracy, and spread is a max of | |
591 | * 0.5% downspread. | |
592 | */ | |
593 | refclk = 135; | |
594 | break; | |
114fe488 | 595 | case WRPLL_PLL_LCPLL: |
11578553 JB |
596 | refclk = LC_FREQ; |
597 | break; | |
598 | default: | |
599 | WARN(1, "bad wrpll refclk\n"); | |
600 | return 0; | |
601 | } | |
602 | ||
603 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
604 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
605 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
606 | ||
20f0ec16 JB |
607 | /* Convert to KHz, p & r have a fixed point portion */ |
608 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
609 | } |
610 | ||
611 | static void intel_ddi_clock_get(struct intel_encoder *encoder, | |
612 | struct intel_crtc_config *pipe_config) | |
613 | { | |
614 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
615 | int link_clock = 0; |
616 | u32 val, pll; | |
617 | ||
26804afd | 618 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
619 | switch (val & PORT_CLK_SEL_MASK) { |
620 | case PORT_CLK_SEL_LCPLL_810: | |
621 | link_clock = 81000; | |
622 | break; | |
623 | case PORT_CLK_SEL_LCPLL_1350: | |
624 | link_clock = 135000; | |
625 | break; | |
626 | case PORT_CLK_SEL_LCPLL_2700: | |
627 | link_clock = 270000; | |
628 | break; | |
629 | case PORT_CLK_SEL_WRPLL1: | |
630 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
631 | break; | |
632 | case PORT_CLK_SEL_WRPLL2: | |
633 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
634 | break; | |
635 | case PORT_CLK_SEL_SPLL: | |
636 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
637 | if (pll == SPLL_PLL_FREQ_810MHz) | |
638 | link_clock = 81000; | |
639 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
640 | link_clock = 135000; | |
641 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
642 | link_clock = 270000; | |
643 | else { | |
644 | WARN(1, "bad spll freq\n"); | |
645 | return; | |
646 | } | |
647 | break; | |
648 | default: | |
649 | WARN(1, "bad port clock sel\n"); | |
650 | return; | |
651 | } | |
652 | ||
653 | pipe_config->port_clock = link_clock * 2; | |
654 | ||
655 | if (pipe_config->has_pch_encoder) | |
656 | pipe_config->adjusted_mode.crtc_clock = | |
657 | intel_dotclock_calculate(pipe_config->port_clock, | |
658 | &pipe_config->fdi_m_n); | |
659 | else if (pipe_config->has_dp_encoder) | |
660 | pipe_config->adjusted_mode.crtc_clock = | |
661 | intel_dotclock_calculate(pipe_config->port_clock, | |
662 | &pipe_config->dp_m_n); | |
663 | else | |
664 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
665 | } | |
666 | ||
1c0b85c5 DL |
667 | static void |
668 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
669 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
670 | { | |
671 | uint64_t freq2k; | |
672 | unsigned p, n2, r2; | |
673 | struct wrpll_rnp best = { 0, 0, 0 }; | |
674 | unsigned budget; | |
675 | ||
676 | freq2k = clock / 100; | |
677 | ||
678 | budget = wrpll_get_budget_for_freq(clock); | |
679 | ||
680 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
681 | * and directly pass the LC PLL to it. */ | |
682 | if (freq2k == 5400000) { | |
683 | *n2_out = 2; | |
684 | *p_out = 1; | |
685 | *r2_out = 2; | |
686 | return; | |
687 | } | |
688 | ||
689 | /* | |
690 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
691 | * the WR PLL. | |
692 | * | |
693 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
694 | * Injecting R2 = 2 * R gives: | |
695 | * REF_MAX * r2 > LC_FREQ * 2 and | |
696 | * REF_MIN * r2 < LC_FREQ * 2 | |
697 | * | |
698 | * Which means the desired boundaries for r2 are: | |
699 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
700 | * | |
701 | */ | |
702 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
703 | r2 <= LC_FREQ * 2 / REF_MIN; | |
704 | r2++) { | |
705 | ||
706 | /* | |
707 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
708 | * | |
709 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
710 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
711 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
712 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
713 | * | |
714 | * Which means the desired boundaries for n2 are: | |
715 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
716 | */ | |
717 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
718 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
719 | n2++) { | |
720 | ||
721 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
722 | wrpll_update_rnp(freq2k, budget, | |
723 | r2, n2, p, &best); | |
724 | } | |
725 | } | |
6441ab5f | 726 | |
1c0b85c5 DL |
727 | *n2_out = best.n2; |
728 | *p_out = best.p; | |
729 | *r2_out = best.r2; | |
6441ab5f PZ |
730 | } |
731 | ||
566b734a PZ |
732 | /* |
733 | * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and | |
734 | * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to | |
735 | * steal the selected PLL. You need to call intel_ddi_pll_enable to actually | |
736 | * enable the PLL. | |
737 | */ | |
738 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
6441ab5f | 739 | { |
566b734a | 740 | struct drm_crtc *crtc = &intel_crtc->base; |
6441ab5f PZ |
741 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
742 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
743 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
744 | int type = intel_encoder->type; | |
745 | enum pipe pipe = intel_crtc->pipe; | |
ff9a6750 | 746 | int clock = intel_crtc->config.port_clock; |
6441ab5f | 747 | |
6441ab5f PZ |
748 | intel_ddi_put_crtc_pll(crtc); |
749 | ||
0e50338c | 750 | if (type == INTEL_OUTPUT_HDMI) { |
566b734a | 751 | uint32_t reg, val; |
1c0b85c5 | 752 | unsigned p, n2, r2; |
6441ab5f | 753 | |
0694001b PZ |
754 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
755 | ||
114fe488 | 756 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
757 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
758 | WRPLL_DIVIDER_POST(p); | |
759 | ||
760 | if (val == I915_READ(WRPLL_CTL1)) { | |
761 | DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n", | |
762 | pipe_name(pipe)); | |
763 | reg = WRPLL_CTL1; | |
764 | } else if (val == I915_READ(WRPLL_CTL2)) { | |
765 | DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n", | |
766 | pipe_name(pipe)); | |
767 | reg = WRPLL_CTL2; | |
768 | } else if (plls->wrpll1_refcount == 0) { | |
6441ab5f PZ |
769 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", |
770 | pipe_name(pipe)); | |
6441ab5f | 771 | reg = WRPLL_CTL1; |
6441ab5f PZ |
772 | } else if (plls->wrpll2_refcount == 0) { |
773 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
774 | pipe_name(pipe)); | |
6441ab5f | 775 | reg = WRPLL_CTL2; |
6441ab5f PZ |
776 | } else { |
777 | DRM_ERROR("No WRPLLs available!\n"); | |
778 | return false; | |
779 | } | |
780 | ||
566b734a PZ |
781 | DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", |
782 | clock, p, n2, r2); | |
783 | ||
0694001b PZ |
784 | if (reg == WRPLL_CTL1) { |
785 | plls->wrpll1_refcount++; | |
de7cfc63 | 786 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1; |
9cd86933 | 787 | intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1; |
0694001b PZ |
788 | } else { |
789 | plls->wrpll2_refcount++; | |
de7cfc63 | 790 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2; |
9cd86933 | 791 | intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2; |
0694001b | 792 | } |
6441ab5f PZ |
793 | } |
794 | ||
6441ab5f PZ |
795 | return true; |
796 | } | |
797 | ||
566b734a PZ |
798 | /* |
799 | * To be called after intel_ddi_pll_select(). That one selects the PLL to be | |
800 | * used, this one actually enables the PLL. | |
801 | */ | |
802 | void intel_ddi_pll_enable(struct intel_crtc *crtc) | |
803 | { | |
804 | struct drm_device *dev = crtc->base.dev; | |
805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
806 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
807 | int clock = crtc->config.port_clock; | |
808 | uint32_t reg, cur_val, new_val; | |
809 | int refcount; | |
810 | const char *pll_name; | |
811 | uint32_t enable_bit = (1 << 31); | |
812 | unsigned int p, n2, r2; | |
813 | ||
814 | BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE); | |
815 | BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE); | |
816 | ||
de7cfc63 | 817 | switch (crtc->config.ddi_pll_sel) { |
566b734a PZ |
818 | case PORT_CLK_SEL_WRPLL1: |
819 | case PORT_CLK_SEL_WRPLL2: | |
de7cfc63 | 820 | if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) { |
566b734a PZ |
821 | pll_name = "WRPLL1"; |
822 | reg = WRPLL_CTL1; | |
823 | refcount = plls->wrpll1_refcount; | |
824 | } else { | |
825 | pll_name = "WRPLL2"; | |
826 | reg = WRPLL_CTL2; | |
827 | refcount = plls->wrpll2_refcount; | |
828 | } | |
829 | ||
830 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); | |
831 | ||
114fe488 | 832 | new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
566b734a PZ |
833 | WRPLL_DIVIDER_REFERENCE(r2) | |
834 | WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p); | |
835 | ||
836 | break; | |
837 | ||
838 | case PORT_CLK_SEL_NONE: | |
839 | WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n"); | |
840 | return; | |
841 | default: | |
566b734a PZ |
842 | return; |
843 | } | |
844 | ||
845 | cur_val = I915_READ(reg); | |
846 | ||
847 | WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount); | |
848 | if (refcount == 1) { | |
849 | WARN(cur_val & enable_bit, "%s already enabled\n", pll_name); | |
850 | I915_WRITE(reg, new_val); | |
851 | POSTING_READ(reg); | |
852 | udelay(20); | |
853 | } else { | |
854 | WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name); | |
855 | } | |
856 | } | |
857 | ||
dae84799 PZ |
858 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
859 | { | |
860 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
862 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 863 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
864 | int type = intel_encoder->type; |
865 | uint32_t temp; | |
866 | ||
867 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
868 | ||
c9809791 | 869 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 870 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 871 | case 18: |
c9809791 | 872 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
873 | break; |
874 | case 24: | |
c9809791 | 875 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
876 | break; |
877 | case 30: | |
c9809791 | 878 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
879 | break; |
880 | case 36: | |
c9809791 | 881 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
882 | break; |
883 | default: | |
4e53c2e0 | 884 | BUG(); |
dae84799 | 885 | } |
c9809791 | 886 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
887 | } |
888 | } | |
889 | ||
8228c251 | 890 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
891 | { |
892 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
893 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 894 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
895 | struct drm_device *dev = crtc->dev; |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 897 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 898 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 899 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 900 | int type = intel_encoder->type; |
8d9ddbcb PZ |
901 | uint32_t temp; |
902 | ||
ad80a810 PZ |
903 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
904 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 905 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 906 | |
965e0c48 | 907 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 908 | case 18: |
ad80a810 | 909 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
910 | break; |
911 | case 24: | |
ad80a810 | 912 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
913 | break; |
914 | case 30: | |
ad80a810 | 915 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
916 | break; |
917 | case 36: | |
ad80a810 | 918 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
919 | break; |
920 | default: | |
4e53c2e0 | 921 | BUG(); |
dfcef252 | 922 | } |
72662e10 | 923 | |
a666283e | 924 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 925 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 926 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 927 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 928 | |
e6f0bfc4 PZ |
929 | if (cpu_transcoder == TRANSCODER_EDP) { |
930 | switch (pipe) { | |
931 | case PIPE_A: | |
c7670b10 PZ |
932 | /* On Haswell, can only use the always-on power well for |
933 | * eDP when not using the panel fitter, and when not | |
934 | * using motion blur mitigation (which we don't | |
935 | * support). */ | |
fabf6e51 DV |
936 | if (IS_HASWELL(dev) && |
937 | (intel_crtc->config.pch_pfit.enabled || | |
938 | intel_crtc->config.pch_pfit.force_thru)) | |
d6dd9eb1 DV |
939 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
940 | else | |
941 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
942 | break; |
943 | case PIPE_B: | |
944 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
945 | break; | |
946 | case PIPE_C: | |
947 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
948 | break; | |
949 | default: | |
950 | BUG(); | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
7739c33b | 955 | if (type == INTEL_OUTPUT_HDMI) { |
6897b4b5 | 956 | if (intel_crtc->config.has_hdmi_sink) |
ad80a810 | 957 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 958 | else |
ad80a810 | 959 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 960 | |
7739c33b | 961 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 962 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 963 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
964 | |
965 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
966 | type == INTEL_OUTPUT_EDP) { | |
967 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
968 | ||
ad80a810 | 969 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 970 | |
17aa6be9 | 971 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 972 | } else { |
84f44ce7 VS |
973 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
974 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
975 | } |
976 | ||
ad80a810 | 977 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 978 | } |
72662e10 | 979 | |
ad80a810 PZ |
980 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
981 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 982 | { |
ad80a810 | 983 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
984 | uint32_t val = I915_READ(reg); |
985 | ||
ad80a810 PZ |
986 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
987 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 988 | I915_WRITE(reg, val); |
72662e10 ED |
989 | } |
990 | ||
bcbc889b PZ |
991 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
992 | { | |
993 | struct drm_device *dev = intel_connector->base.dev; | |
994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
995 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
996 | int type = intel_connector->base.connector_type; | |
997 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
998 | enum pipe pipe = 0; | |
999 | enum transcoder cpu_transcoder; | |
882244a3 | 1000 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
1001 | uint32_t tmp; |
1002 | ||
882244a3 PZ |
1003 | power_domain = intel_display_port_power_domain(intel_encoder); |
1004 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1005 | return false; | |
1006 | ||
bcbc889b PZ |
1007 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
1008 | return false; | |
1009 | ||
1010 | if (port == PORT_A) | |
1011 | cpu_transcoder = TRANSCODER_EDP; | |
1012 | else | |
1a240d4d | 1013 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1014 | |
1015 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1016 | ||
1017 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1018 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1019 | case TRANS_DDI_MODE_SELECT_DVI: | |
1020 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
1021 | ||
1022 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1023 | if (type == DRM_MODE_CONNECTOR_eDP) | |
1024 | return true; | |
1025 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1026 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
1027 | ||
1028 | case TRANS_DDI_MODE_SELECT_FDI: | |
1029 | return (type == DRM_MODE_CONNECTOR_VGA); | |
1030 | ||
1031 | default: | |
1032 | return false; | |
1033 | } | |
1034 | } | |
1035 | ||
85234cdc DV |
1036 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1037 | enum pipe *pipe) | |
1038 | { | |
1039 | struct drm_device *dev = encoder->base.dev; | |
1040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1041 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1042 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1043 | u32 tmp; |
1044 | int i; | |
1045 | ||
6d129bea ID |
1046 | power_domain = intel_display_port_power_domain(encoder); |
1047 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1048 | return false; | |
1049 | ||
fe43d3f5 | 1050 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1051 | |
1052 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1053 | return false; | |
1054 | ||
ad80a810 PZ |
1055 | if (port == PORT_A) { |
1056 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1057 | |
ad80a810 PZ |
1058 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1059 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1060 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1061 | *pipe = PIPE_A; | |
1062 | break; | |
1063 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1064 | *pipe = PIPE_B; | |
1065 | break; | |
1066 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1067 | *pipe = PIPE_C; | |
1068 | break; | |
1069 | } | |
1070 | ||
1071 | return true; | |
1072 | } else { | |
1073 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1074 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1075 | ||
1076 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1077 | == TRANS_DDI_SELECT_PORT(port)) { | |
1078 | *pipe = i; | |
1079 | return true; | |
1080 | } | |
85234cdc DV |
1081 | } |
1082 | } | |
1083 | ||
84f44ce7 | 1084 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1085 | |
22f9fe50 | 1086 | return false; |
85234cdc DV |
1087 | } |
1088 | ||
6441ab5f PZ |
1089 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) |
1090 | { | |
1091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1092 | enum pipe pipe; | |
1093 | struct intel_crtc *intel_crtc; | |
1094 | ||
0882dae9 PZ |
1095 | dev_priv->ddi_plls.wrpll1_refcount = 0; |
1096 | dev_priv->ddi_plls.wrpll2_refcount = 0; | |
1097 | ||
6441ab5f PZ |
1098 | for_each_pipe(pipe) { |
1099 | intel_crtc = | |
1100 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
1101 | ||
0882dae9 | 1102 | if (!intel_crtc->active) { |
de7cfc63 | 1103 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE; |
6441ab5f | 1104 | continue; |
0882dae9 | 1105 | } |
6441ab5f | 1106 | |
de7cfc63 | 1107 | switch (intel_crtc->config.ddi_pll_sel) { |
6441ab5f PZ |
1108 | case PORT_CLK_SEL_WRPLL1: |
1109 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1110 | break; | |
1111 | case PORT_CLK_SEL_WRPLL2: | |
1112 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | } | |
1117 | ||
fc914639 PZ |
1118 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1119 | { | |
1120 | struct drm_crtc *crtc = &intel_crtc->base; | |
1121 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1122 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1123 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1124 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1125 | |
bb523fc0 PZ |
1126 | if (cpu_transcoder != TRANSCODER_EDP) |
1127 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1128 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1129 | } |
1130 | ||
1131 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1132 | { | |
1133 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1134 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1135 | |
bb523fc0 PZ |
1136 | if (cpu_transcoder != TRANSCODER_EDP) |
1137 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1138 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1139 | } |
1140 | ||
00c09d70 | 1141 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1142 | { |
c19b0669 | 1143 | struct drm_encoder *encoder = &intel_encoder->base; |
c19b0669 | 1144 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
30cf6db8 | 1145 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1146 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1147 | int type = intel_encoder->type; |
6441ab5f | 1148 | |
30cf6db8 DV |
1149 | if (crtc->config.has_audio) { |
1150 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1151 | pipe_name(crtc->pipe)); | |
1152 | ||
1153 | /* write eld */ | |
1154 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1155 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1156 | } | |
1157 | ||
82a4d9c0 PZ |
1158 | if (type == INTEL_OUTPUT_EDP) { |
1159 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1160 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1161 | } |
6441ab5f | 1162 | |
de7cfc63 DV |
1163 | WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); |
1164 | I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); | |
c19b0669 | 1165 | |
82a4d9c0 | 1166 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1167 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 DV |
1168 | struct intel_digital_port *intel_dig_port = |
1169 | enc_to_dig_port(encoder); | |
1170 | ||
1171 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
1172 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | |
1173 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
c19b0669 PZ |
1174 | |
1175 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1176 | intel_dp_start_link_train(intel_dp); | |
1177 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1178 | if (port != PORT_A) |
1179 | intel_dp_stop_link_train(intel_dp); | |
30cf6db8 DV |
1180 | } else if (type == INTEL_OUTPUT_HDMI) { |
1181 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1182 | ||
1183 | intel_hdmi->set_infoframes(encoder, | |
1184 | crtc->config.has_hdmi_sink, | |
1185 | &crtc->config.adjusted_mode); | |
c19b0669 | 1186 | } |
6441ab5f PZ |
1187 | } |
1188 | ||
00c09d70 | 1189 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1190 | { |
1191 | struct drm_encoder *encoder = &intel_encoder->base; | |
1192 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1193 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1194 | int type = intel_encoder->type; |
2886e93f | 1195 | uint32_t val; |
a836bdf9 | 1196 | bool wait = false; |
2886e93f PZ |
1197 | |
1198 | val = I915_READ(DDI_BUF_CTL(port)); | |
1199 | if (val & DDI_BUF_CTL_ENABLE) { | |
1200 | val &= ~DDI_BUF_CTL_ENABLE; | |
1201 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1202 | wait = true; |
2886e93f | 1203 | } |
6441ab5f | 1204 | |
a836bdf9 PZ |
1205 | val = I915_READ(DP_TP_CTL(port)); |
1206 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1207 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1208 | I915_WRITE(DP_TP_CTL(port), val); | |
1209 | ||
1210 | if (wait) | |
1211 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1212 | ||
76bb80ed | 1213 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1214 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1215 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1216 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1217 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1218 | } |
1219 | ||
6441ab5f PZ |
1220 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1221 | } | |
1222 | ||
00c09d70 | 1223 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1224 | { |
6547fef8 | 1225 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1226 | struct drm_crtc *crtc = encoder->crtc; |
1227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1228 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1229 | struct drm_device *dev = encoder->dev; |
72662e10 | 1230 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1231 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1232 | int type = intel_encoder->type; | |
7b9f35a6 | 1233 | uint32_t tmp; |
72662e10 | 1234 | |
6547fef8 | 1235 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1236 | struct intel_digital_port *intel_dig_port = |
1237 | enc_to_dig_port(encoder); | |
1238 | ||
6547fef8 PZ |
1239 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1240 | * are ignored so nothing special needs to be done besides | |
1241 | * enabling the port. | |
1242 | */ | |
876a8cdf | 1243 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1244 | intel_dig_port->saved_port_bits | |
1245 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1246 | } else if (type == INTEL_OUTPUT_EDP) { |
1247 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1248 | ||
3ab9c637 ID |
1249 | if (port == PORT_A) |
1250 | intel_dp_stop_link_train(intel_dp); | |
1251 | ||
4be73780 | 1252 | intel_edp_backlight_on(intel_dp); |
4906557e | 1253 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1254 | } |
7b9f35a6 | 1255 | |
9ed109a7 | 1256 | if (intel_crtc->config.has_audio) { |
d45a0bf5 | 1257 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
7b9f35a6 WX |
1258 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1259 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1260 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1261 | } | |
5ab432ef DV |
1262 | } |
1263 | ||
00c09d70 | 1264 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1265 | { |
d6c50ff8 | 1266 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1267 | struct drm_crtc *crtc = encoder->crtc; |
1268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1269 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1270 | int type = intel_encoder->type; |
7b9f35a6 WX |
1271 | struct drm_device *dev = encoder->dev; |
1272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1273 | uint32_t tmp; | |
d6c50ff8 | 1274 | |
d45a0bf5 PZ |
1275 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1276 | * register is part of the power well on Haswell. */ | |
1277 | if (intel_crtc->config.has_audio) { | |
1278 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1279 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1280 | (pipe * 4)); | |
1281 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1282 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
1283 | } | |
2831d842 | 1284 | |
d6c50ff8 PZ |
1285 | if (type == INTEL_OUTPUT_EDP) { |
1286 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1287 | ||
4906557e | 1288 | intel_edp_psr_disable(intel_dp); |
4be73780 | 1289 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1290 | } |
72662e10 | 1291 | } |
79f689aa | 1292 | |
b8fc2f6a | 1293 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1294 | { |
e39bf98a | 1295 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1296 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1297 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1298 | |
e39bf98a | 1299 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1300 | return 800000; |
e3589908 | 1301 | } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1302 | return 450000; |
e39bf98a | 1303 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1304 | return 450000; |
e39bf98a PZ |
1305 | } else if (IS_HASWELL(dev)) { |
1306 | if (IS_ULT(dev)) | |
1307 | return 337500; | |
1308 | else | |
1309 | return 540000; | |
1310 | } else { | |
1311 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1312 | return 540000; | |
1313 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1314 | return 337500; | |
1315 | else | |
1316 | return 675000; | |
1317 | } | |
79f689aa PZ |
1318 | } |
1319 | ||
9cd86933 DV |
1320 | static char *hsw_ddi_pll_names[] = { |
1321 | "WRPLL 1", | |
1322 | "WRPLL 2", | |
1323 | }; | |
1324 | ||
79f689aa PZ |
1325 | void intel_ddi_pll_init(struct drm_device *dev) |
1326 | { | |
1327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1328 | uint32_t val = I915_READ(LCPLL_CTL); | |
9cd86933 DV |
1329 | int i; |
1330 | ||
1331 | /* Dummy setup until everything is moved over to avoid upsetting the hw | |
1332 | * state cross checker. */ | |
1333 | dev_priv->num_shared_dpll = 0; | |
1334 | ||
1335 | for (i = 0; i < 2; i++) { | |
1336 | dev_priv->shared_dplls[i].id = i; | |
1337 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
1338 | } | |
79f689aa PZ |
1339 | |
1340 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1341 | * just check its state and print errors in case something is wrong. | |
1342 | * Don't even try to turn it on. | |
1343 | */ | |
1344 | ||
b2b877ff | 1345 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1346 | intel_ddi_get_cdclk_freq(dev_priv)); |
1347 | ||
1348 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1349 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1350 | ||
1351 | if (val & LCPLL_PLL_DISABLE) | |
1352 | DRM_ERROR("LCPLL is disabled\n"); | |
1353 | } | |
c19b0669 PZ |
1354 | |
1355 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1356 | { | |
174edf1f PZ |
1357 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1358 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1359 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1360 | enum port port = intel_dig_port->port; |
c19b0669 | 1361 | uint32_t val; |
f3e227df | 1362 | bool wait = false; |
c19b0669 PZ |
1363 | |
1364 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1365 | val = I915_READ(DDI_BUF_CTL(port)); | |
1366 | if (val & DDI_BUF_CTL_ENABLE) { | |
1367 | val &= ~DDI_BUF_CTL_ENABLE; | |
1368 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1369 | wait = true; | |
1370 | } | |
1371 | ||
1372 | val = I915_READ(DP_TP_CTL(port)); | |
1373 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1374 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1375 | I915_WRITE(DP_TP_CTL(port), val); | |
1376 | POSTING_READ(DP_TP_CTL(port)); | |
1377 | ||
1378 | if (wait) | |
1379 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1380 | } | |
1381 | ||
1382 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1383 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
6aba5b6c | 1384 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
c19b0669 PZ |
1385 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1386 | I915_WRITE(DP_TP_CTL(port), val); | |
1387 | POSTING_READ(DP_TP_CTL(port)); | |
1388 | ||
1389 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1390 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1391 | POSTING_READ(DDI_BUF_CTL(port)); | |
1392 | ||
1393 | udelay(600); | |
1394 | } | |
00c09d70 | 1395 | |
1ad960f2 PZ |
1396 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1397 | { | |
1398 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1399 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1400 | uint32_t val; | |
1401 | ||
1402 | intel_ddi_post_disable(intel_encoder); | |
1403 | ||
1404 | val = I915_READ(_FDI_RXA_CTL); | |
1405 | val &= ~FDI_RX_ENABLE; | |
1406 | I915_WRITE(_FDI_RXA_CTL, val); | |
1407 | ||
1408 | val = I915_READ(_FDI_RXA_MISC); | |
1409 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1410 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1411 | I915_WRITE(_FDI_RXA_MISC, val); | |
1412 | ||
1413 | val = I915_READ(_FDI_RXA_CTL); | |
1414 | val &= ~FDI_PCDCLK; | |
1415 | I915_WRITE(_FDI_RXA_CTL, val); | |
1416 | ||
1417 | val = I915_READ(_FDI_RXA_CTL); | |
1418 | val &= ~FDI_RX_PLL_ENABLE; | |
1419 | I915_WRITE(_FDI_RXA_CTL, val); | |
1420 | } | |
1421 | ||
00c09d70 PZ |
1422 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1423 | { | |
1424 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1425 | int type = intel_encoder->type; | |
1426 | ||
1427 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1428 | intel_dp_check_link_status(intel_dp); | |
1429 | } | |
1430 | ||
6801c18c VS |
1431 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1432 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1433 | { |
1434 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1435 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1436 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1437 | u32 temp, flags = 0; | |
1438 | ||
1439 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1440 | if (temp & TRANS_DDI_PHSYNC) | |
1441 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1442 | else | |
1443 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1444 | if (temp & TRANS_DDI_PVSYNC) | |
1445 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1446 | else | |
1447 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1448 | ||
1449 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1450 | |
1451 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1452 | case TRANS_DDI_BPC_6: | |
1453 | pipe_config->pipe_bpp = 18; | |
1454 | break; | |
1455 | case TRANS_DDI_BPC_8: | |
1456 | pipe_config->pipe_bpp = 24; | |
1457 | break; | |
1458 | case TRANS_DDI_BPC_10: | |
1459 | pipe_config->pipe_bpp = 30; | |
1460 | break; | |
1461 | case TRANS_DDI_BPC_12: | |
1462 | pipe_config->pipe_bpp = 36; | |
1463 | break; | |
1464 | default: | |
1465 | break; | |
1466 | } | |
eb14cb74 VS |
1467 | |
1468 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1469 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 1470 | pipe_config->has_hdmi_sink = true; |
eb14cb74 VS |
1471 | case TRANS_DDI_MODE_SELECT_DVI: |
1472 | case TRANS_DDI_MODE_SELECT_FDI: | |
1473 | break; | |
1474 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1475 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1476 | pipe_config->has_dp_encoder = true; | |
1477 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1478 | break; | |
1479 | default: | |
1480 | break; | |
1481 | } | |
10214420 | 1482 | |
a60551b1 PZ |
1483 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1484 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1485 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1486 | pipe_config->has_audio = true; | |
1487 | } | |
9ed109a7 | 1488 | |
10214420 DV |
1489 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1490 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1491 | /* | |
1492 | * This is a big fat ugly hack. | |
1493 | * | |
1494 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1495 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1496 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1497 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1498 | * max, not what it tells us to use. | |
1499 | * | |
1500 | * Note: This will still be broken if the eDP panel is not lit | |
1501 | * up by the BIOS, and thus we can't get the mode at module | |
1502 | * load. | |
1503 | */ | |
1504 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1505 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1506 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1507 | } | |
11578553 JB |
1508 | |
1509 | intel_ddi_clock_get(encoder, pipe_config); | |
045ac3b5 JB |
1510 | } |
1511 | ||
00c09d70 PZ |
1512 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1513 | { | |
1514 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1515 | intel_dp_encoder_destroy(encoder); | |
1516 | } | |
1517 | ||
5bfe2ac0 DV |
1518 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1519 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1520 | { |
5bfe2ac0 | 1521 | int type = encoder->type; |
eccb140b | 1522 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1523 | |
5bfe2ac0 | 1524 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1525 | |
eccb140b DV |
1526 | if (port == PORT_A) |
1527 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1528 | ||
00c09d70 | 1529 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1530 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1531 | else |
5bfe2ac0 | 1532 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1533 | } |
1534 | ||
1535 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1536 | .destroy = intel_ddi_destroy, | |
1537 | }; | |
1538 | ||
4a28ae58 PZ |
1539 | static struct intel_connector * |
1540 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1541 | { | |
1542 | struct intel_connector *connector; | |
1543 | enum port port = intel_dig_port->port; | |
1544 | ||
1545 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1546 | if (!connector) | |
1547 | return NULL; | |
1548 | ||
1549 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1550 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1551 | kfree(connector); | |
1552 | return NULL; | |
1553 | } | |
1554 | ||
1555 | return connector; | |
1556 | } | |
1557 | ||
1558 | static struct intel_connector * | |
1559 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1560 | { | |
1561 | struct intel_connector *connector; | |
1562 | enum port port = intel_dig_port->port; | |
1563 | ||
1564 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1565 | if (!connector) | |
1566 | return NULL; | |
1567 | ||
1568 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1569 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1570 | ||
1571 | return connector; | |
1572 | } | |
1573 | ||
00c09d70 PZ |
1574 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1575 | { | |
876a8cdf | 1576 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1577 | struct intel_digital_port *intel_dig_port; |
1578 | struct intel_encoder *intel_encoder; | |
1579 | struct drm_encoder *encoder; | |
1580 | struct intel_connector *hdmi_connector = NULL; | |
1581 | struct intel_connector *dp_connector = NULL; | |
311a2094 PZ |
1582 | bool init_hdmi, init_dp; |
1583 | ||
1584 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1585 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1586 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1587 | if (!init_dp && !init_hdmi) { | |
1588 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n", | |
1589 | port_name(port)); | |
1590 | init_hdmi = true; | |
1591 | init_dp = true; | |
1592 | } | |
00c09d70 | 1593 | |
b14c5679 | 1594 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1595 | if (!intel_dig_port) |
1596 | return; | |
1597 | ||
00c09d70 PZ |
1598 | intel_encoder = &intel_dig_port->base; |
1599 | encoder = &intel_encoder->base; | |
1600 | ||
1601 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1602 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1603 | |
5bfe2ac0 | 1604 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
1605 | intel_encoder->enable = intel_enable_ddi; |
1606 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1607 | intel_encoder->disable = intel_disable_ddi; | |
1608 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1609 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1610 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1611 | |
1612 | intel_dig_port->port = port; | |
bcf53de4 SM |
1613 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1614 | (DDI_BUF_PORT_REVERSAL | | |
1615 | DDI_A_4_LANES); | |
00c09d70 PZ |
1616 | |
1617 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1618 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
bc079e8b | 1619 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
1620 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1621 | ||
13cf5504 DA |
1622 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
1623 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
1624 | ||
4a28ae58 PZ |
1625 | if (init_dp) |
1626 | dp_connector = intel_ddi_init_dp_connector(intel_dig_port); | |
21a8e6a4 | 1627 | |
311a2094 PZ |
1628 | /* In theory we don't need the encoder->type check, but leave it just in |
1629 | * case we have some really bad VBTs... */ | |
4a28ae58 PZ |
1630 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) |
1631 | hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port); | |
21a8e6a4 | 1632 | |
4a28ae58 PZ |
1633 | if (!dp_connector && !hdmi_connector) { |
1634 | drm_encoder_cleanup(encoder); | |
1635 | kfree(intel_dig_port); | |
21a8e6a4 | 1636 | } |
00c09d70 | 1637 | } |