]>
Commit | Line | Data |
---|---|---|
45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
ac921bdd | 36 | 0x00FFFFFF, 0x0006000E, |
45244b87 ED |
37 | 0x00D75FFF, 0x0005000A, |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
ac921bdd | 48 | 0x00FFFFFF, 0x0007000E, |
45244b87 ED |
49 | 0x00D75FFF, 0x000F000A, |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 | 75 | static const u32 bdw_ddi_translations_edp[] = { |
ac921bdd | 76 | 0x00FFFFFF, 0x00000012, |
300644c7 PZ |
77 | 0x00EBAFFF, 0x00020011, |
78 | 0x00C71FFF, 0x0006000F, | |
9576c27f | 79 | 0x00AAAFFF, 0x000E000A, |
300644c7 PZ |
80 | 0x00FFFFFF, 0x00020011, |
81 | 0x00DB6FFF, 0x0005000F, | |
82 | 0x00BEEFFF, 0x000A000C, | |
83 | 0x00FFFFFF, 0x0005000F, | |
84 | 0x00DB6FFF, 0x000A000C, | |
300644c7 PZ |
85 | }; |
86 | ||
e58623cb | 87 | static const u32 bdw_ddi_translations_dp[] = { |
ac921bdd | 88 | 0x00FFFFFF, 0x0007000E, |
e58623cb AR |
89 | 0x00D75FFF, 0x000E000A, |
90 | 0x00BEFFFF, 0x00140006, | |
9576c27f | 91 | 0x80B2CFFF, 0x001B0002, |
e58623cb AR |
92 | 0x00FFFFFF, 0x000E000A, |
93 | 0x00D75FFF, 0x00180004, | |
94 | 0x80CB2FFF, 0x001B0002, | |
95 | 0x00F7DFFF, 0x00180004, | |
96 | 0x80D75FFF, 0x001B0002, | |
e58623cb AR |
97 | }; |
98 | ||
99 | static const u32 bdw_ddi_translations_fdi[] = { | |
ac921bdd | 100 | 0x00FFFFFF, 0x0001000E, |
e58623cb AR |
101 | 0x00D75FFF, 0x0004000A, |
102 | 0x00C30FFF, 0x00070006, | |
103 | 0x00AAAFFF, 0x000C0000, | |
104 | 0x00FFFFFF, 0x0004000A, | |
105 | 0x00D75FFF, 0x00090004, | |
106 | 0x00C30FFF, 0x000C0000, | |
107 | 0x00FFFFFF, 0x00070006, | |
108 | 0x00D75FFF, 0x000C0000, | |
e58623cb AR |
109 | }; |
110 | ||
a26aa8ba DL |
111 | static const u32 bdw_ddi_translations_hdmi[] = { |
112 | /* Idx NT mV diff T mV diff db */ | |
113 | 0x00FFFFFF, 0x0007000E, /* 0: 400 400 0 */ | |
114 | 0x00D75FFF, 0x000E000A, /* 1: 400 600 3.5 */ | |
115 | 0x00BEFFFF, 0x00140006, /* 2: 400 800 6 */ | |
116 | 0x00FFFFFF, 0x0009000D, /* 3: 450 450 0 */ | |
117 | 0x00FFFFFF, 0x000E000A, /* 4: 600 600 0 */ | |
118 | 0x00D7FFFF, 0x00140006, /* 5: 600 800 2.5 */ | |
119 | 0x80CB2FFF, 0x001B0002, /* 6: 600 1000 4.5 */ | |
120 | 0x00FFFFFF, 0x00140006, /* 7: 800 800 0 */ | |
121 | 0x80E79FFF, 0x001B0002, /* 8: 800 1000 2 */ | |
122 | 0x80FFFFFF, 0x001B0002, /* 9: 1000 1000 0 */ | |
123 | }; | |
124 | ||
20f4dbe4 | 125 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 126 | { |
0bdee30e | 127 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
128 | int type = intel_encoder->type; |
129 | ||
0e32b39c DA |
130 | if (type == INTEL_OUTPUT_DP_MST) { |
131 | struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; | |
132 | return intel_dig_port->port; | |
133 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || | |
00c09d70 | 134 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
135 | struct intel_digital_port *intel_dig_port = |
136 | enc_to_dig_port(encoder); | |
137 | return intel_dig_port->port; | |
0bdee30e | 138 | |
fc914639 PZ |
139 | } else if (type == INTEL_OUTPUT_ANALOG) { |
140 | return PORT_E; | |
0bdee30e | 141 | |
fc914639 PZ |
142 | } else { |
143 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
144 | BUG(); | |
145 | } | |
146 | } | |
147 | ||
e58623cb AR |
148 | /* |
149 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
150 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
151 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
152 | * in either FDI or DP modes only, as HDMI connections will work with both | |
153 | * of those | |
154 | */ | |
ad8d270c | 155 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
156 | { |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | u32 reg; | |
ce4dd49e | 159 | int i, n_hdmi_entries, hdmi_800mV_0dB; |
6acab15a | 160 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
161 | const u32 *ddi_translations_fdi; |
162 | const u32 *ddi_translations_dp; | |
300644c7 | 163 | const u32 *ddi_translations_edp; |
a26aa8ba | 164 | const u32 *ddi_translations_hdmi; |
e58623cb AR |
165 | const u32 *ddi_translations; |
166 | ||
167 | if (IS_BROADWELL(dev)) { | |
168 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
169 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 170 | ddi_translations_edp = bdw_ddi_translations_edp; |
a26aa8ba | 171 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
d6699dd3 | 172 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; |
a26aa8ba | 173 | hdmi_800mV_0dB = 7; |
e58623cb AR |
174 | } else if (IS_HASWELL(dev)) { |
175 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
176 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 177 | ddi_translations_edp = hsw_ddi_translations_dp; |
a26aa8ba | 178 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
d6699dd3 | 179 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi) / 2; |
ce4dd49e | 180 | hdmi_800mV_0dB = 6; |
e58623cb AR |
181 | } else { |
182 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 183 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
184 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
185 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a26aa8ba | 186 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
d6699dd3 | 187 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; |
a26aa8ba | 188 | hdmi_800mV_0dB = 7; |
e58623cb AR |
189 | } |
190 | ||
300644c7 PZ |
191 | switch (port) { |
192 | case PORT_A: | |
193 | ddi_translations = ddi_translations_edp; | |
194 | break; | |
195 | case PORT_B: | |
196 | case PORT_C: | |
300644c7 PZ |
197 | ddi_translations = ddi_translations_dp; |
198 | break; | |
77d8d009 | 199 | case PORT_D: |
5d8a7752 | 200 | if (intel_dp_is_edp(dev, PORT_D)) |
77d8d009 PZ |
201 | ddi_translations = ddi_translations_edp; |
202 | else | |
203 | ddi_translations = ddi_translations_dp; | |
204 | break; | |
300644c7 PZ |
205 | case PORT_E: |
206 | ddi_translations = ddi_translations_fdi; | |
207 | break; | |
208 | default: | |
209 | BUG(); | |
210 | } | |
45244b87 | 211 | |
f72d19f0 PZ |
212 | for (i = 0, reg = DDI_BUF_TRANS(port); |
213 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
214 | I915_WRITE(reg, ddi_translations[i]); |
215 | reg += 4; | |
216 | } | |
ce4dd49e DL |
217 | |
218 | /* Choose a good default if VBT is badly populated */ | |
219 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
220 | hdmi_level >= n_hdmi_entries) | |
221 | hdmi_level = hdmi_800mV_0dB; | |
222 | ||
6acab15a PZ |
223 | /* Entry 9 is for HDMI: */ |
224 | for (i = 0; i < 2; i++) { | |
a26aa8ba | 225 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]); |
6acab15a PZ |
226 | reg += 4; |
227 | } | |
45244b87 ED |
228 | } |
229 | ||
230 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
231 | * mode and port E for FDI. | |
232 | */ | |
233 | void intel_prepare_ddi(struct drm_device *dev) | |
234 | { | |
235 | int port; | |
236 | ||
0d536cb4 PZ |
237 | if (!HAS_DDI(dev)) |
238 | return; | |
45244b87 | 239 | |
ad8d270c PZ |
240 | for (port = PORT_A; port <= PORT_E; port++) |
241 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 242 | } |
c82e4d26 | 243 | |
248138b5 PZ |
244 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
245 | enum port port) | |
246 | { | |
247 | uint32_t reg = DDI_BUF_CTL(port); | |
248 | int i; | |
249 | ||
250 | for (i = 0; i < 8; i++) { | |
251 | udelay(1); | |
252 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
253 | return; | |
254 | } | |
255 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
256 | } | |
c82e4d26 ED |
257 | |
258 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
259 | * connection to the PCH-located connectors. For this, it is necessary to train | |
260 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
261 | * | |
262 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
263 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
264 | * DDI A (which is used for eDP) | |
265 | */ | |
266 | ||
c5fe6a06 SJ |
267 | #define NUM_FDI_TRANSLATION_ENTRIES (ARRAY_SIZE(hsw_ddi_translations_fdi) / 2) |
268 | ||
c82e4d26 ED |
269 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
270 | { | |
271 | struct drm_device *dev = crtc->dev; | |
272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 274 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 275 | |
04945641 PZ |
276 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
277 | * mode set "sequence for CRT port" document: | |
278 | * - TP1 to TP2 time with the default value | |
279 | * - FDI delay to 90h | |
8693a824 DL |
280 | * |
281 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
282 | */ |
283 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
284 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
285 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
286 | ||
287 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 288 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 289 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 290 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
291 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
292 | POSTING_READ(_FDI_RXA_CTL); | |
293 | udelay(220); | |
294 | ||
295 | /* Switch from Rawclk to PCDclk */ | |
296 | rx_ctl_val |= FDI_PCDCLK; | |
297 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
298 | ||
299 | /* Configure Port Clock Select */ | |
de7cfc63 DV |
300 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); |
301 | WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
302 | |
303 | /* Start the training iterating through available voltages and emphasis, | |
304 | * testing each value twice. */ | |
c5fe6a06 | 305 | for (i = 0; i < NUM_FDI_TRANSLATION_ENTRIES * 2; i++) { |
c82e4d26 ED |
306 | /* Configure DP_TP_CTL with auto-training */ |
307 | I915_WRITE(DP_TP_CTL(PORT_E), | |
308 | DP_TP_CTL_FDI_AUTOTRAIN | | |
309 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
310 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
311 | DP_TP_CTL_ENABLE); | |
312 | ||
876a8cdf DL |
313 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
314 | * DDI E does not support port reversal, the functionality is | |
315 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
316 | * port reversal bit */ | |
c82e4d26 | 317 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 318 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 319 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
c5fe6a06 | 320 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 321 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
322 | |
323 | udelay(600); | |
324 | ||
04945641 PZ |
325 | /* Program PCH FDI Receiver TU */ |
326 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
327 | ||
328 | /* Enable PCH FDI Receiver with auto-training */ | |
329 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
330 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
331 | POSTING_READ(_FDI_RXA_CTL); | |
332 | ||
333 | /* Wait for FDI receiver lane calibration */ | |
334 | udelay(30); | |
335 | ||
336 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
337 | temp = I915_READ(_FDI_RXA_MISC); | |
338 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
339 | I915_WRITE(_FDI_RXA_MISC, temp); | |
340 | POSTING_READ(_FDI_RXA_MISC); | |
341 | ||
342 | /* Wait for FDI auto training time */ | |
343 | udelay(5); | |
c82e4d26 ED |
344 | |
345 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
346 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 347 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
348 | |
349 | /* Enable normal pixel sending for FDI */ | |
350 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
351 | DP_TP_CTL_FDI_AUTOTRAIN | |
352 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
353 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
354 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 355 | |
04945641 | 356 | return; |
c82e4d26 | 357 | } |
04945641 | 358 | |
248138b5 PZ |
359 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
360 | temp &= ~DDI_BUF_CTL_ENABLE; | |
361 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
362 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
363 | ||
04945641 | 364 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
365 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
366 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
367 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
368 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
369 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
370 | ||
371 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
372 | |
373 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
374 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 375 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
376 | |
377 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
378 | temp = I915_READ(_FDI_RXA_MISC); | |
379 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
380 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
381 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 382 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
383 | } |
384 | ||
04945641 | 385 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 386 | } |
0e72a5b5 | 387 | |
44905a27 DA |
388 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
389 | { | |
390 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
391 | struct intel_digital_port *intel_dig_port = | |
392 | enc_to_dig_port(&encoder->base); | |
393 | ||
394 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 395 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
44905a27 DA |
396 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
397 | ||
398 | } | |
399 | ||
8d9ddbcb PZ |
400 | static struct intel_encoder * |
401 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
402 | { | |
403 | struct drm_device *dev = crtc->dev; | |
404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
405 | struct intel_encoder *intel_encoder, *ret = NULL; | |
406 | int num_encoders = 0; | |
407 | ||
408 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
409 | ret = intel_encoder; | |
410 | num_encoders++; | |
411 | } | |
412 | ||
413 | if (num_encoders != 1) | |
84f44ce7 VS |
414 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
415 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
416 | |
417 | BUG_ON(ret == NULL); | |
418 | return ret; | |
419 | } | |
420 | ||
1c0b85c5 DL |
421 | #define LC_FREQ 2700 |
422 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
423 | ||
424 | #define P_MIN 2 | |
425 | #define P_MAX 64 | |
426 | #define P_INC 2 | |
427 | ||
428 | /* Constraints for PLL good behavior */ | |
429 | #define REF_MIN 48 | |
430 | #define REF_MAX 400 | |
431 | #define VCO_MIN 2400 | |
432 | #define VCO_MAX 4800 | |
433 | ||
434 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
435 | ||
436 | struct wrpll_rnp { | |
437 | unsigned p, n2, r2; | |
438 | }; | |
439 | ||
440 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 441 | { |
1c0b85c5 DL |
442 | unsigned budget; |
443 | ||
444 | switch (clock) { | |
445 | case 25175000: | |
446 | case 25200000: | |
447 | case 27000000: | |
448 | case 27027000: | |
449 | case 37762500: | |
450 | case 37800000: | |
451 | case 40500000: | |
452 | case 40541000: | |
453 | case 54000000: | |
454 | case 54054000: | |
455 | case 59341000: | |
456 | case 59400000: | |
457 | case 72000000: | |
458 | case 74176000: | |
459 | case 74250000: | |
460 | case 81000000: | |
461 | case 81081000: | |
462 | case 89012000: | |
463 | case 89100000: | |
464 | case 108000000: | |
465 | case 108108000: | |
466 | case 111264000: | |
467 | case 111375000: | |
468 | case 148352000: | |
469 | case 148500000: | |
470 | case 162000000: | |
471 | case 162162000: | |
472 | case 222525000: | |
473 | case 222750000: | |
474 | case 296703000: | |
475 | case 297000000: | |
476 | budget = 0; | |
477 | break; | |
478 | case 233500000: | |
479 | case 245250000: | |
480 | case 247750000: | |
481 | case 253250000: | |
482 | case 298000000: | |
483 | budget = 1500; | |
484 | break; | |
485 | case 169128000: | |
486 | case 169500000: | |
487 | case 179500000: | |
488 | case 202000000: | |
489 | budget = 2000; | |
490 | break; | |
491 | case 256250000: | |
492 | case 262500000: | |
493 | case 270000000: | |
494 | case 272500000: | |
495 | case 273750000: | |
496 | case 280750000: | |
497 | case 281250000: | |
498 | case 286000000: | |
499 | case 291750000: | |
500 | budget = 4000; | |
501 | break; | |
502 | case 267250000: | |
503 | case 268500000: | |
504 | budget = 5000; | |
505 | break; | |
506 | default: | |
507 | budget = 1000; | |
508 | break; | |
509 | } | |
6441ab5f | 510 | |
1c0b85c5 DL |
511 | return budget; |
512 | } | |
513 | ||
514 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
515 | unsigned r2, unsigned n2, unsigned p, | |
516 | struct wrpll_rnp *best) | |
517 | { | |
518 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 519 | |
1c0b85c5 DL |
520 | /* No best (r,n,p) yet */ |
521 | if (best->p == 0) { | |
522 | best->p = p; | |
523 | best->n2 = n2; | |
524 | best->r2 = r2; | |
525 | return; | |
526 | } | |
6441ab5f | 527 | |
1c0b85c5 DL |
528 | /* |
529 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
530 | * freq2k. | |
531 | * | |
532 | * delta = 1e6 * | |
533 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
534 | * freq2k; | |
535 | * | |
536 | * and we would like delta <= budget. | |
537 | * | |
538 | * If the discrepancy is above the PPM-based budget, always prefer to | |
539 | * improve upon the previous solution. However, if you're within the | |
540 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
541 | */ | |
542 | a = freq2k * budget * p * r2; | |
543 | b = freq2k * budget * best->p * best->r2; | |
544 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
545 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
546 | (LC_FREQ_2K * best->n2)); | |
547 | c = 1000000 * diff; | |
548 | d = 1000000 * diff_best; | |
549 | ||
550 | if (a < c && b < d) { | |
551 | /* If both are above the budget, pick the closer */ | |
552 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
553 | best->p = p; | |
554 | best->n2 = n2; | |
555 | best->r2 = r2; | |
556 | } | |
557 | } else if (a >= c && b < d) { | |
558 | /* If A is below the threshold but B is above it? Update. */ | |
559 | best->p = p; | |
560 | best->n2 = n2; | |
561 | best->r2 = r2; | |
562 | } else if (a >= c && b >= d) { | |
563 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
564 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
565 | best->p = p; | |
566 | best->n2 = n2; | |
567 | best->r2 = r2; | |
568 | } | |
569 | } | |
570 | /* Otherwise a < c && b >= d, do nothing */ | |
571 | } | |
572 | ||
11578553 JB |
573 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
574 | int reg) | |
575 | { | |
576 | int refclk = LC_FREQ; | |
577 | int n, p, r; | |
578 | u32 wrpll; | |
579 | ||
580 | wrpll = I915_READ(reg); | |
114fe488 DV |
581 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
582 | case WRPLL_PLL_SSC: | |
583 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
584 | /* |
585 | * We could calculate spread here, but our checking | |
586 | * code only cares about 5% accuracy, and spread is a max of | |
587 | * 0.5% downspread. | |
588 | */ | |
589 | refclk = 135; | |
590 | break; | |
114fe488 | 591 | case WRPLL_PLL_LCPLL: |
11578553 JB |
592 | refclk = LC_FREQ; |
593 | break; | |
594 | default: | |
595 | WARN(1, "bad wrpll refclk\n"); | |
596 | return 0; | |
597 | } | |
598 | ||
599 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
600 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
601 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
602 | ||
20f0ec16 JB |
603 | /* Convert to KHz, p & r have a fixed point portion */ |
604 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
605 | } |
606 | ||
3d51278a DV |
607 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
608 | struct intel_crtc_config *pipe_config) | |
11578553 JB |
609 | { |
610 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
611 | int link_clock = 0; |
612 | u32 val, pll; | |
613 | ||
26804afd | 614 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
615 | switch (val & PORT_CLK_SEL_MASK) { |
616 | case PORT_CLK_SEL_LCPLL_810: | |
617 | link_clock = 81000; | |
618 | break; | |
619 | case PORT_CLK_SEL_LCPLL_1350: | |
620 | link_clock = 135000; | |
621 | break; | |
622 | case PORT_CLK_SEL_LCPLL_2700: | |
623 | link_clock = 270000; | |
624 | break; | |
625 | case PORT_CLK_SEL_WRPLL1: | |
626 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
627 | break; | |
628 | case PORT_CLK_SEL_WRPLL2: | |
629 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
630 | break; | |
631 | case PORT_CLK_SEL_SPLL: | |
632 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
633 | if (pll == SPLL_PLL_FREQ_810MHz) | |
634 | link_clock = 81000; | |
635 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
636 | link_clock = 135000; | |
637 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
638 | link_clock = 270000; | |
639 | else { | |
640 | WARN(1, "bad spll freq\n"); | |
641 | return; | |
642 | } | |
643 | break; | |
644 | default: | |
645 | WARN(1, "bad port clock sel\n"); | |
646 | return; | |
647 | } | |
648 | ||
649 | pipe_config->port_clock = link_clock * 2; | |
650 | ||
651 | if (pipe_config->has_pch_encoder) | |
652 | pipe_config->adjusted_mode.crtc_clock = | |
653 | intel_dotclock_calculate(pipe_config->port_clock, | |
654 | &pipe_config->fdi_m_n); | |
655 | else if (pipe_config->has_dp_encoder) | |
656 | pipe_config->adjusted_mode.crtc_clock = | |
657 | intel_dotclock_calculate(pipe_config->port_clock, | |
658 | &pipe_config->dp_m_n); | |
659 | else | |
660 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
661 | } | |
662 | ||
3d51278a DV |
663 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
664 | struct intel_crtc_config *pipe_config) | |
665 | { | |
666 | hsw_ddi_clock_get(encoder, pipe_config); | |
667 | } | |
668 | ||
1c0b85c5 | 669 | static void |
d664c0ce DL |
670 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
671 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
1c0b85c5 DL |
672 | { |
673 | uint64_t freq2k; | |
674 | unsigned p, n2, r2; | |
675 | struct wrpll_rnp best = { 0, 0, 0 }; | |
676 | unsigned budget; | |
677 | ||
678 | freq2k = clock / 100; | |
679 | ||
680 | budget = wrpll_get_budget_for_freq(clock); | |
681 | ||
682 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
683 | * and directly pass the LC PLL to it. */ | |
684 | if (freq2k == 5400000) { | |
685 | *n2_out = 2; | |
686 | *p_out = 1; | |
687 | *r2_out = 2; | |
688 | return; | |
689 | } | |
690 | ||
691 | /* | |
692 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
693 | * the WR PLL. | |
694 | * | |
695 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
696 | * Injecting R2 = 2 * R gives: | |
697 | * REF_MAX * r2 > LC_FREQ * 2 and | |
698 | * REF_MIN * r2 < LC_FREQ * 2 | |
699 | * | |
700 | * Which means the desired boundaries for r2 are: | |
701 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
702 | * | |
703 | */ | |
704 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
705 | r2 <= LC_FREQ * 2 / REF_MIN; | |
706 | r2++) { | |
707 | ||
708 | /* | |
709 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
710 | * | |
711 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
712 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
713 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
714 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
715 | * | |
716 | * Which means the desired boundaries for n2 are: | |
717 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
718 | */ | |
719 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
720 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
721 | n2++) { | |
722 | ||
723 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
724 | wrpll_update_rnp(freq2k, budget, | |
725 | r2, n2, p, &best); | |
726 | } | |
727 | } | |
6441ab5f | 728 | |
1c0b85c5 DL |
729 | *n2_out = best.n2; |
730 | *p_out = best.p; | |
731 | *r2_out = best.r2; | |
6441ab5f PZ |
732 | } |
733 | ||
0220ab6e | 734 | static bool |
d664c0ce DL |
735 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
736 | struct intel_encoder *intel_encoder, | |
737 | int clock) | |
6441ab5f | 738 | { |
d664c0ce | 739 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 740 | struct intel_shared_dpll *pll; |
716c2e55 | 741 | uint32_t val; |
1c0b85c5 | 742 | unsigned p, n2, r2; |
6441ab5f | 743 | |
d664c0ce | 744 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
0694001b | 745 | |
114fe488 | 746 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
747 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
748 | WRPLL_DIVIDER_POST(p); | |
749 | ||
716c2e55 | 750 | intel_crtc->config.dpll_hw_state.wrpll = val; |
6441ab5f | 751 | |
716c2e55 DV |
752 | pll = intel_get_shared_dpll(intel_crtc); |
753 | if (pll == NULL) { | |
754 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
755 | pipe_name(intel_crtc->pipe)); | |
756 | return false; | |
0694001b | 757 | } |
d452c5b6 | 758 | |
716c2e55 | 759 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
6441ab5f PZ |
760 | } |
761 | ||
6441ab5f PZ |
762 | return true; |
763 | } | |
764 | ||
0220ab6e DL |
765 | |
766 | /* | |
767 | * Tries to find a *shared* PLL for the CRTC and store it in | |
768 | * intel_crtc->ddi_pll_sel. | |
769 | * | |
770 | * For private DPLLs, compute_config() should do the selection for us. This | |
771 | * function should be folded into compute_config() eventually. | |
772 | */ | |
773 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
774 | { | |
775 | struct drm_crtc *crtc = &intel_crtc->base; | |
776 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
0220ab6e DL |
777 | int clock = intel_crtc->config.port_clock; |
778 | ||
779 | intel_put_shared_dpll(intel_crtc); | |
780 | ||
d664c0ce | 781 | return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock); |
0220ab6e DL |
782 | } |
783 | ||
dae84799 PZ |
784 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
785 | { | |
786 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
788 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 789 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
790 | int type = intel_encoder->type; |
791 | uint32_t temp; | |
792 | ||
0e32b39c | 793 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
c9809791 | 794 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 795 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 796 | case 18: |
c9809791 | 797 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
798 | break; |
799 | case 24: | |
c9809791 | 800 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
801 | break; |
802 | case 30: | |
c9809791 | 803 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
804 | break; |
805 | case 36: | |
c9809791 | 806 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
807 | break; |
808 | default: | |
4e53c2e0 | 809 | BUG(); |
dae84799 | 810 | } |
c9809791 | 811 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
812 | } |
813 | } | |
814 | ||
0e32b39c DA |
815 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
816 | { | |
817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
818 | struct drm_device *dev = crtc->dev; | |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
821 | uint32_t temp; | |
822 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
823 | if (state == true) | |
824 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
825 | else | |
826 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
827 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
828 | } | |
829 | ||
8228c251 | 830 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
831 | { |
832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
833 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 834 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
835 | struct drm_device *dev = crtc->dev; |
836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 837 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 838 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 839 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 840 | int type = intel_encoder->type; |
8d9ddbcb PZ |
841 | uint32_t temp; |
842 | ||
ad80a810 PZ |
843 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
844 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 845 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 846 | |
965e0c48 | 847 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 848 | case 18: |
ad80a810 | 849 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
850 | break; |
851 | case 24: | |
ad80a810 | 852 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
853 | break; |
854 | case 30: | |
ad80a810 | 855 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
856 | break; |
857 | case 36: | |
ad80a810 | 858 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
859 | break; |
860 | default: | |
4e53c2e0 | 861 | BUG(); |
dfcef252 | 862 | } |
72662e10 | 863 | |
a666283e | 864 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 865 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 866 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 867 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 868 | |
e6f0bfc4 PZ |
869 | if (cpu_transcoder == TRANSCODER_EDP) { |
870 | switch (pipe) { | |
871 | case PIPE_A: | |
c7670b10 PZ |
872 | /* On Haswell, can only use the always-on power well for |
873 | * eDP when not using the panel fitter, and when not | |
874 | * using motion blur mitigation (which we don't | |
875 | * support). */ | |
fabf6e51 DV |
876 | if (IS_HASWELL(dev) && |
877 | (intel_crtc->config.pch_pfit.enabled || | |
878 | intel_crtc->config.pch_pfit.force_thru)) | |
d6dd9eb1 DV |
879 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
880 | else | |
881 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
882 | break; |
883 | case PIPE_B: | |
884 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
885 | break; | |
886 | case PIPE_C: | |
887 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
888 | break; | |
889 | default: | |
890 | BUG(); | |
891 | break; | |
892 | } | |
893 | } | |
894 | ||
7739c33b | 895 | if (type == INTEL_OUTPUT_HDMI) { |
6897b4b5 | 896 | if (intel_crtc->config.has_hdmi_sink) |
ad80a810 | 897 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 898 | else |
ad80a810 | 899 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 900 | |
7739c33b | 901 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 902 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 903 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
904 | |
905 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
906 | type == INTEL_OUTPUT_EDP) { | |
907 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
908 | ||
0e32b39c DA |
909 | if (intel_dp->is_mst) { |
910 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
911 | } else | |
912 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
913 | ||
914 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
915 | } else if (type == INTEL_OUTPUT_DP_MST) { | |
916 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; | |
917 | ||
918 | if (intel_dp->is_mst) { | |
919 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
920 | } else | |
921 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
7739c33b | 922 | |
17aa6be9 | 923 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 924 | } else { |
84f44ce7 VS |
925 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
926 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
927 | } |
928 | ||
ad80a810 | 929 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 930 | } |
72662e10 | 931 | |
ad80a810 PZ |
932 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
933 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 934 | { |
ad80a810 | 935 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
936 | uint32_t val = I915_READ(reg); |
937 | ||
0e32b39c | 938 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 939 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 940 | I915_WRITE(reg, val); |
72662e10 ED |
941 | } |
942 | ||
bcbc889b PZ |
943 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
944 | { | |
945 | struct drm_device *dev = intel_connector->base.dev; | |
946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
947 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
948 | int type = intel_connector->base.connector_type; | |
949 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
950 | enum pipe pipe = 0; | |
951 | enum transcoder cpu_transcoder; | |
882244a3 | 952 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
953 | uint32_t tmp; |
954 | ||
882244a3 PZ |
955 | power_domain = intel_display_port_power_domain(intel_encoder); |
956 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
957 | return false; | |
958 | ||
bcbc889b PZ |
959 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
960 | return false; | |
961 | ||
962 | if (port == PORT_A) | |
963 | cpu_transcoder = TRANSCODER_EDP; | |
964 | else | |
1a240d4d | 965 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
966 | |
967 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
968 | ||
969 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
970 | case TRANS_DDI_MODE_SELECT_HDMI: | |
971 | case TRANS_DDI_MODE_SELECT_DVI: | |
972 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
973 | ||
974 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
975 | if (type == DRM_MODE_CONNECTOR_eDP) | |
976 | return true; | |
bcbc889b | 977 | return (type == DRM_MODE_CONNECTOR_DisplayPort); |
0e32b39c DA |
978 | case TRANS_DDI_MODE_SELECT_DP_MST: |
979 | /* if the transcoder is in MST state then | |
980 | * connector isn't connected */ | |
981 | return false; | |
bcbc889b PZ |
982 | |
983 | case TRANS_DDI_MODE_SELECT_FDI: | |
984 | return (type == DRM_MODE_CONNECTOR_VGA); | |
985 | ||
986 | default: | |
987 | return false; | |
988 | } | |
989 | } | |
990 | ||
85234cdc DV |
991 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
992 | enum pipe *pipe) | |
993 | { | |
994 | struct drm_device *dev = encoder->base.dev; | |
995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 996 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 997 | enum intel_display_power_domain power_domain; |
85234cdc DV |
998 | u32 tmp; |
999 | int i; | |
1000 | ||
6d129bea ID |
1001 | power_domain = intel_display_port_power_domain(encoder); |
1002 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1003 | return false; | |
1004 | ||
fe43d3f5 | 1005 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1006 | |
1007 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1008 | return false; | |
1009 | ||
ad80a810 PZ |
1010 | if (port == PORT_A) { |
1011 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1012 | |
ad80a810 PZ |
1013 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1014 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1015 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1016 | *pipe = PIPE_A; | |
1017 | break; | |
1018 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1019 | *pipe = PIPE_B; | |
1020 | break; | |
1021 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1022 | *pipe = PIPE_C; | |
1023 | break; | |
1024 | } | |
1025 | ||
1026 | return true; | |
1027 | } else { | |
1028 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1029 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1030 | ||
1031 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1032 | == TRANS_DDI_SELECT_PORT(port)) { | |
0e32b39c DA |
1033 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
1034 | return false; | |
1035 | ||
ad80a810 PZ |
1036 | *pipe = i; |
1037 | return true; | |
1038 | } | |
85234cdc DV |
1039 | } |
1040 | } | |
1041 | ||
84f44ce7 | 1042 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1043 | |
22f9fe50 | 1044 | return false; |
85234cdc DV |
1045 | } |
1046 | ||
fc914639 PZ |
1047 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1048 | { | |
1049 | struct drm_crtc *crtc = &intel_crtc->base; | |
1050 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1051 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1052 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1053 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1054 | |
bb523fc0 PZ |
1055 | if (cpu_transcoder != TRANSCODER_EDP) |
1056 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1057 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1058 | } |
1059 | ||
1060 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1061 | { | |
1062 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1063 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1064 | |
bb523fc0 PZ |
1065 | if (cpu_transcoder != TRANSCODER_EDP) |
1066 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1067 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1068 | } |
1069 | ||
00c09d70 | 1070 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1071 | { |
c19b0669 | 1072 | struct drm_encoder *encoder = &intel_encoder->base; |
c19b0669 | 1073 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
30cf6db8 | 1074 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1075 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1076 | int type = intel_encoder->type; |
6441ab5f | 1077 | |
30cf6db8 DV |
1078 | if (crtc->config.has_audio) { |
1079 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1080 | pipe_name(crtc->pipe)); | |
1081 | ||
1082 | /* write eld */ | |
1083 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1084 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1085 | } | |
1086 | ||
82a4d9c0 PZ |
1087 | if (type == INTEL_OUTPUT_EDP) { |
1088 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1089 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1090 | } |
6441ab5f | 1091 | |
de7cfc63 DV |
1092 | WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); |
1093 | I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); | |
c19b0669 | 1094 | |
82a4d9c0 | 1095 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1096 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1097 | |
44905a27 | 1098 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1099 | |
1100 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1101 | intel_dp_start_link_train(intel_dp); | |
1102 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1103 | if (port != PORT_A) |
1104 | intel_dp_stop_link_train(intel_dp); | |
30cf6db8 DV |
1105 | } else if (type == INTEL_OUTPUT_HDMI) { |
1106 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1107 | ||
1108 | intel_hdmi->set_infoframes(encoder, | |
1109 | crtc->config.has_hdmi_sink, | |
1110 | &crtc->config.adjusted_mode); | |
c19b0669 | 1111 | } |
6441ab5f PZ |
1112 | } |
1113 | ||
00c09d70 | 1114 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1115 | { |
1116 | struct drm_encoder *encoder = &intel_encoder->base; | |
1117 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1118 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1119 | int type = intel_encoder->type; |
2886e93f | 1120 | uint32_t val; |
a836bdf9 | 1121 | bool wait = false; |
2886e93f PZ |
1122 | |
1123 | val = I915_READ(DDI_BUF_CTL(port)); | |
1124 | if (val & DDI_BUF_CTL_ENABLE) { | |
1125 | val &= ~DDI_BUF_CTL_ENABLE; | |
1126 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1127 | wait = true; |
2886e93f | 1128 | } |
6441ab5f | 1129 | |
a836bdf9 PZ |
1130 | val = I915_READ(DP_TP_CTL(port)); |
1131 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1132 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1133 | I915_WRITE(DP_TP_CTL(port), val); | |
1134 | ||
1135 | if (wait) | |
1136 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1137 | ||
76bb80ed | 1138 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1139 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1140 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1141 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1142 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1143 | } |
1144 | ||
6441ab5f PZ |
1145 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1146 | } | |
1147 | ||
00c09d70 | 1148 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1149 | { |
6547fef8 | 1150 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1151 | struct drm_crtc *crtc = encoder->crtc; |
1152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1153 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1154 | struct drm_device *dev = encoder->dev; |
72662e10 | 1155 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1156 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1157 | int type = intel_encoder->type; | |
7b9f35a6 | 1158 | uint32_t tmp; |
72662e10 | 1159 | |
6547fef8 | 1160 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1161 | struct intel_digital_port *intel_dig_port = |
1162 | enc_to_dig_port(encoder); | |
1163 | ||
6547fef8 PZ |
1164 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1165 | * are ignored so nothing special needs to be done besides | |
1166 | * enabling the port. | |
1167 | */ | |
876a8cdf | 1168 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1169 | intel_dig_port->saved_port_bits | |
1170 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1171 | } else if (type == INTEL_OUTPUT_EDP) { |
1172 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1173 | ||
3ab9c637 ID |
1174 | if (port == PORT_A) |
1175 | intel_dp_stop_link_train(intel_dp); | |
1176 | ||
4be73780 | 1177 | intel_edp_backlight_on(intel_dp); |
4906557e | 1178 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1179 | } |
7b9f35a6 | 1180 | |
9ed109a7 | 1181 | if (intel_crtc->config.has_audio) { |
d45a0bf5 | 1182 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
7b9f35a6 WX |
1183 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1184 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1185 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1186 | } | |
5ab432ef DV |
1187 | } |
1188 | ||
00c09d70 | 1189 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1190 | { |
d6c50ff8 | 1191 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1192 | struct drm_crtc *crtc = encoder->crtc; |
1193 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1194 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1195 | int type = intel_encoder->type; |
7b9f35a6 WX |
1196 | struct drm_device *dev = encoder->dev; |
1197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1198 | uint32_t tmp; | |
d6c50ff8 | 1199 | |
d45a0bf5 PZ |
1200 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1201 | * register is part of the power well on Haswell. */ | |
1202 | if (intel_crtc->config.has_audio) { | |
1203 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1204 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1205 | (pipe * 4)); | |
1206 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1207 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
1208 | } | |
2831d842 | 1209 | |
d6c50ff8 PZ |
1210 | if (type == INTEL_OUTPUT_EDP) { |
1211 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1212 | ||
4906557e | 1213 | intel_edp_psr_disable(intel_dp); |
4be73780 | 1214 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1215 | } |
72662e10 | 1216 | } |
79f689aa | 1217 | |
ad13d604 DL |
1218 | static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) |
1219 | { | |
1220 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
1221 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
1222 | ||
1223 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
1224 | return 800000; | |
1225 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
1226 | return 450000; | |
1227 | else if (freq == LCPLL_CLK_FREQ_450) | |
1228 | return 450000; | |
1229 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1230 | return 540000; | |
1231 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1232 | return 337500; | |
1233 | else | |
1234 | return 675000; | |
1235 | } | |
1236 | ||
1237 | static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) | |
79f689aa | 1238 | { |
e39bf98a | 1239 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1240 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1241 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1242 | |
ad13d604 | 1243 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
a4006641 | 1244 | return 800000; |
ad13d604 | 1245 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
b2b877ff | 1246 | return 450000; |
ad13d604 | 1247 | else if (freq == LCPLL_CLK_FREQ_450) |
b2b877ff | 1248 | return 450000; |
ad13d604 DL |
1249 | else if (IS_ULT(dev)) |
1250 | return 337500; | |
1251 | else | |
1252 | return 540000; | |
1253 | } | |
1254 | ||
1255 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) | |
1256 | { | |
1257 | struct drm_device *dev = dev_priv->dev; | |
1258 | ||
1259 | if (IS_BROADWELL(dev)) | |
1260 | return bdw_get_cdclk_freq(dev_priv); | |
1261 | ||
1262 | /* Haswell */ | |
1263 | return hsw_get_cdclk_freq(dev_priv); | |
79f689aa PZ |
1264 | } |
1265 | ||
e0b01be4 DV |
1266 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
1267 | struct intel_shared_dpll *pll) | |
1268 | { | |
e0b01be4 DV |
1269 | I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll); |
1270 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1271 | udelay(20); | |
1272 | } | |
1273 | ||
12030431 DV |
1274 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
1275 | struct intel_shared_dpll *pll) | |
1276 | { | |
1277 | uint32_t val; | |
1278 | ||
1279 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
1280 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
1281 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1282 | } | |
1283 | ||
d452c5b6 DV |
1284 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
1285 | struct intel_shared_dpll *pll, | |
1286 | struct intel_dpll_hw_state *hw_state) | |
1287 | { | |
1288 | uint32_t val; | |
1289 | ||
1290 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
1291 | return false; | |
1292 | ||
1293 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1294 | hw_state->wrpll = val; | |
1295 | ||
1296 | return val & WRPLL_PLL_ENABLE; | |
1297 | } | |
1298 | ||
ca1381b5 | 1299 | static const char * const hsw_ddi_pll_names[] = { |
9cd86933 DV |
1300 | "WRPLL 1", |
1301 | "WRPLL 2", | |
1302 | }; | |
1303 | ||
143b307c | 1304 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
79f689aa | 1305 | { |
9cd86933 DV |
1306 | int i; |
1307 | ||
716c2e55 | 1308 | dev_priv->num_shared_dpll = 2; |
9cd86933 | 1309 | |
716c2e55 | 1310 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9cd86933 DV |
1311 | dev_priv->shared_dplls[i].id = i; |
1312 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
12030431 | 1313 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
e0b01be4 | 1314 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
d452c5b6 DV |
1315 | dev_priv->shared_dplls[i].get_hw_state = |
1316 | hsw_ddi_pll_get_hw_state; | |
9cd86933 | 1317 | } |
143b307c DL |
1318 | } |
1319 | ||
1320 | void intel_ddi_pll_init(struct drm_device *dev) | |
1321 | { | |
1322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1323 | uint32_t val = I915_READ(LCPLL_CTL); | |
1324 | ||
1325 | hsw_shared_dplls_init(dev_priv); | |
79f689aa PZ |
1326 | |
1327 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1328 | * just check its state and print errors in case something is wrong. | |
1329 | * Don't even try to turn it on. | |
1330 | */ | |
1331 | ||
b2b877ff | 1332 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1333 | intel_ddi_get_cdclk_freq(dev_priv)); |
1334 | ||
1335 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1336 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1337 | ||
1338 | if (val & LCPLL_PLL_DISABLE) | |
1339 | DRM_ERROR("LCPLL is disabled\n"); | |
1340 | } | |
c19b0669 PZ |
1341 | |
1342 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1343 | { | |
174edf1f PZ |
1344 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1345 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1346 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1347 | enum port port = intel_dig_port->port; |
c19b0669 | 1348 | uint32_t val; |
f3e227df | 1349 | bool wait = false; |
c19b0669 PZ |
1350 | |
1351 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1352 | val = I915_READ(DDI_BUF_CTL(port)); | |
1353 | if (val & DDI_BUF_CTL_ENABLE) { | |
1354 | val &= ~DDI_BUF_CTL_ENABLE; | |
1355 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1356 | wait = true; | |
1357 | } | |
1358 | ||
1359 | val = I915_READ(DP_TP_CTL(port)); | |
1360 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1361 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1362 | I915_WRITE(DP_TP_CTL(port), val); | |
1363 | POSTING_READ(DP_TP_CTL(port)); | |
1364 | ||
1365 | if (wait) | |
1366 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1367 | } | |
1368 | ||
0e32b39c | 1369 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 1370 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
0e32b39c DA |
1371 | if (intel_dp->is_mst) |
1372 | val |= DP_TP_CTL_MODE_MST; | |
1373 | else { | |
1374 | val |= DP_TP_CTL_MODE_SST; | |
1375 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1376 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1377 | } | |
c19b0669 PZ |
1378 | I915_WRITE(DP_TP_CTL(port), val); |
1379 | POSTING_READ(DP_TP_CTL(port)); | |
1380 | ||
1381 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1382 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1383 | POSTING_READ(DDI_BUF_CTL(port)); | |
1384 | ||
1385 | udelay(600); | |
1386 | } | |
00c09d70 | 1387 | |
1ad960f2 PZ |
1388 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1389 | { | |
1390 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1391 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1392 | uint32_t val; | |
1393 | ||
1394 | intel_ddi_post_disable(intel_encoder); | |
1395 | ||
1396 | val = I915_READ(_FDI_RXA_CTL); | |
1397 | val &= ~FDI_RX_ENABLE; | |
1398 | I915_WRITE(_FDI_RXA_CTL, val); | |
1399 | ||
1400 | val = I915_READ(_FDI_RXA_MISC); | |
1401 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1402 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1403 | I915_WRITE(_FDI_RXA_MISC, val); | |
1404 | ||
1405 | val = I915_READ(_FDI_RXA_CTL); | |
1406 | val &= ~FDI_PCDCLK; | |
1407 | I915_WRITE(_FDI_RXA_CTL, val); | |
1408 | ||
1409 | val = I915_READ(_FDI_RXA_CTL); | |
1410 | val &= ~FDI_RX_PLL_ENABLE; | |
1411 | I915_WRITE(_FDI_RXA_CTL, val); | |
1412 | } | |
1413 | ||
00c09d70 PZ |
1414 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1415 | { | |
0e32b39c DA |
1416 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
1417 | int type = intel_dig_port->base.type; | |
1418 | ||
1419 | if (type != INTEL_OUTPUT_DISPLAYPORT && | |
1420 | type != INTEL_OUTPUT_EDP && | |
1421 | type != INTEL_OUTPUT_UNKNOWN) { | |
1422 | return; | |
1423 | } | |
00c09d70 | 1424 | |
0e32b39c | 1425 | intel_dp_hot_plug(intel_encoder); |
00c09d70 PZ |
1426 | } |
1427 | ||
6801c18c VS |
1428 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1429 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1430 | { |
1431 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1432 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1433 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1434 | u32 temp, flags = 0; | |
1435 | ||
1436 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1437 | if (temp & TRANS_DDI_PHSYNC) | |
1438 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1439 | else | |
1440 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1441 | if (temp & TRANS_DDI_PVSYNC) | |
1442 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1443 | else | |
1444 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1445 | ||
1446 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1447 | |
1448 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1449 | case TRANS_DDI_BPC_6: | |
1450 | pipe_config->pipe_bpp = 18; | |
1451 | break; | |
1452 | case TRANS_DDI_BPC_8: | |
1453 | pipe_config->pipe_bpp = 24; | |
1454 | break; | |
1455 | case TRANS_DDI_BPC_10: | |
1456 | pipe_config->pipe_bpp = 30; | |
1457 | break; | |
1458 | case TRANS_DDI_BPC_12: | |
1459 | pipe_config->pipe_bpp = 36; | |
1460 | break; | |
1461 | default: | |
1462 | break; | |
1463 | } | |
eb14cb74 VS |
1464 | |
1465 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1466 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 1467 | pipe_config->has_hdmi_sink = true; |
eb14cb74 VS |
1468 | case TRANS_DDI_MODE_SELECT_DVI: |
1469 | case TRANS_DDI_MODE_SELECT_FDI: | |
1470 | break; | |
1471 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1472 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1473 | pipe_config->has_dp_encoder = true; | |
1474 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1475 | break; | |
1476 | default: | |
1477 | break; | |
1478 | } | |
10214420 | 1479 | |
a60551b1 PZ |
1480 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1481 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1482 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1483 | pipe_config->has_audio = true; | |
1484 | } | |
9ed109a7 | 1485 | |
10214420 DV |
1486 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1487 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1488 | /* | |
1489 | * This is a big fat ugly hack. | |
1490 | * | |
1491 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1492 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1493 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1494 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1495 | * max, not what it tells us to use. | |
1496 | * | |
1497 | * Note: This will still be broken if the eDP panel is not lit | |
1498 | * up by the BIOS, and thus we can't get the mode at module | |
1499 | * load. | |
1500 | */ | |
1501 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1502 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1503 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1504 | } | |
11578553 | 1505 | |
3d51278a | 1506 | hsw_ddi_clock_get(encoder, pipe_config); |
045ac3b5 JB |
1507 | } |
1508 | ||
00c09d70 PZ |
1509 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1510 | { | |
1511 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1512 | intel_dp_encoder_destroy(encoder); | |
1513 | } | |
1514 | ||
5bfe2ac0 DV |
1515 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1516 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1517 | { |
5bfe2ac0 | 1518 | int type = encoder->type; |
eccb140b | 1519 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1520 | |
5bfe2ac0 | 1521 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1522 | |
eccb140b DV |
1523 | if (port == PORT_A) |
1524 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1525 | ||
00c09d70 | 1526 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1527 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1528 | else |
5bfe2ac0 | 1529 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1530 | } |
1531 | ||
1532 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1533 | .destroy = intel_ddi_destroy, | |
1534 | }; | |
1535 | ||
4a28ae58 PZ |
1536 | static struct intel_connector * |
1537 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1538 | { | |
1539 | struct intel_connector *connector; | |
1540 | enum port port = intel_dig_port->port; | |
1541 | ||
1542 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1543 | if (!connector) | |
1544 | return NULL; | |
1545 | ||
1546 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1547 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1548 | kfree(connector); | |
1549 | return NULL; | |
1550 | } | |
1551 | ||
1552 | return connector; | |
1553 | } | |
1554 | ||
1555 | static struct intel_connector * | |
1556 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1557 | { | |
1558 | struct intel_connector *connector; | |
1559 | enum port port = intel_dig_port->port; | |
1560 | ||
1561 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1562 | if (!connector) | |
1563 | return NULL; | |
1564 | ||
1565 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1566 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1567 | ||
1568 | return connector; | |
1569 | } | |
1570 | ||
00c09d70 PZ |
1571 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1572 | { | |
876a8cdf | 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1574 | struct intel_digital_port *intel_dig_port; |
1575 | struct intel_encoder *intel_encoder; | |
1576 | struct drm_encoder *encoder; | |
311a2094 PZ |
1577 | bool init_hdmi, init_dp; |
1578 | ||
1579 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1580 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1581 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1582 | if (!init_dp && !init_hdmi) { | |
f68d697e | 1583 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
311a2094 PZ |
1584 | port_name(port)); |
1585 | init_hdmi = true; | |
1586 | init_dp = true; | |
1587 | } | |
00c09d70 | 1588 | |
b14c5679 | 1589 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1590 | if (!intel_dig_port) |
1591 | return; | |
1592 | ||
00c09d70 PZ |
1593 | intel_encoder = &intel_dig_port->base; |
1594 | encoder = &intel_encoder->base; | |
1595 | ||
1596 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1597 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1598 | |
5bfe2ac0 | 1599 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
1600 | intel_encoder->enable = intel_enable_ddi; |
1601 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1602 | intel_encoder->disable = intel_disable_ddi; | |
1603 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1604 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1605 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1606 | |
1607 | intel_dig_port->port = port; | |
bcf53de4 SM |
1608 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1609 | (DDI_BUF_PORT_REVERSAL | | |
1610 | DDI_A_4_LANES); | |
00c09d70 PZ |
1611 | |
1612 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
f68d697e | 1613 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 1614 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
1615 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1616 | ||
f68d697e CW |
1617 | if (init_dp) { |
1618 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
1619 | goto err; | |
13cf5504 | 1620 | |
f68d697e CW |
1621 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
1622 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
1623 | } | |
21a8e6a4 | 1624 | |
311a2094 PZ |
1625 | /* In theory we don't need the encoder->type check, but leave it just in |
1626 | * case we have some really bad VBTs... */ | |
f68d697e CW |
1627 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
1628 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
1629 | goto err; | |
21a8e6a4 | 1630 | } |
f68d697e CW |
1631 | |
1632 | return; | |
1633 | ||
1634 | err: | |
1635 | drm_encoder_cleanup(encoder); | |
1636 | kfree(intel_dig_port); | |
00c09d70 | 1637 | } |