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drm/i915/cnl: Move ddi buf trans related functions up.
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
97eeb872
VS		 37static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48};
49
45244b87
ED		 50/* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
10122051 54static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 64};
65
10122051 66static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 76};
77
10122051
JN		 78static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
f8896f5d
DW		 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 92};
93
10122051 94static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 104};
105
10122051 106static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 116};
117
10122051 118static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 128};
129
10122051
JN		 130static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
f8896f5d
DW		 132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 142};
143
5f8b2531 144/* Skylake H and S */
7f88e3af 145static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
d7097cff 152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 155};
156
f8896f5d
DW		 157/* Skylake U */
158static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 159 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 160 { 0x00005012, 0x00000088, 0x0 },
5ac90567 161 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 163 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 166 { 0x00002016, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 168};
169
5f8b2531
RV		 170/* Skylake Y */
171static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
5ac90567 174 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 175 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 176 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 179 { 0x00000018, 0x00000088, 0x0 },
d7097cff 180 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 181};
182
0fdd4918
RV		 183/* Kabylake H and S */
184static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194};
195
196/* Kabylake U */
197static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207};
208
209/* Kabylake Y */
210static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220};
221
f8896f5d 222/*
0fdd4918 223 * Skylake/Kabylake H and S
f8896f5d
DW		 224 * eDP 1.4 low vswing translation parameters
225 */
7ad14a29 226static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237};
238
239/*
0fdd4918 240 * Skylake/Kabylake U
f8896f5d
DW		 241 * eDP 1.4 low vswing translation parameters
242 */
243static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 254};
255
f8896f5d 256/*
0fdd4918 257 * Skylake/Kabylake Y
f8896f5d
DW		 258 * eDP 1.4 low vswing translation parameters
259 */
5f8b2531 260static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271};
7ad14a29 272
0fdd4918 273/* Skylake/Kabylake U, H and S */
7f88e3af 274static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
2e78416e 281 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 282 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 286};
287
0fdd4918 288/* Skylake/Kabylake Y */
5f8b2531 289static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 292 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
2e78416e 296 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 297 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 301};
302
96fb9f9b
VK		 303struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
fe4c63c8
ID		 313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
fe4c63c8
ID		 344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354};
355
83fb7ab4
RV		 356struct cnl_ddi_buf_trans {
357 u32 dw2_swing_sel;
358 u32 dw7_n_scalar;
359 u32 dw4_cursor_coeff;
360 u32 dw4_post_cursor_2;
361 u32 dw4_post_cursor_1;
362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
5a5d24dc 496enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
fc914639 497{
5a5d24dc 498 switch (encoder->type) {
8cd21b7f 499 case INTEL_OUTPUT_DP_MST:
5a5d24dc 500 return enc_to_mst(&encoder->base)->primary->port;
cca0502b 501 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
5a5d24dc 505 return enc_to_dig_port(&encoder->base)->port;
8cd21b7f 506 case INTEL_OUTPUT_ANALOG:
5a5d24dc
VS		 507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
fc914639
PZ		 511 }
512}
513
a930acd9
VS		 514static const struct ddi_buf_trans *
515bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516{
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524}
525
acee2998 526static const struct ddi_buf_trans *
78ab0bae 527skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 528{
0fdd4918 529 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 531 return skl_y_ddi_translations_dp;
0fdd4918 532 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 534 return skl_u_ddi_translations_dp;
f8896f5d 535 } else {
f8896f5d 536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 537 return skl_ddi_translations_dp;
f8896f5d 538 }
f8896f5d
DW		 539}
540
0fdd4918
RV		 541static const struct ddi_buf_trans *
542kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543{
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
da411a48 547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554}
555
acee2998 556static const struct ddi_buf_trans *
78ab0bae 557skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 558{
06411f08 559 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 562 return skl_y_ddi_translations_edp;
da411a48
RV		 563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
f8896f5d 565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 566 return skl_u_ddi_translations_edp;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 569 return skl_ddi_translations_edp;
f8896f5d
DW		 570 }
571 }
cd1101cb 572
da411a48 573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 577}
578
579static const struct ddi_buf_trans *
78ab0bae 580skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 581{
78ab0bae 582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 584 return skl_y_ddi_translations_hdmi;
f8896f5d 585 } else {
f8896f5d 586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 587 return skl_ddi_translations_hdmi;
f8896f5d 588 }
f8896f5d
DW		 589}
590
cf3e0fb4
RV		 591static const struct cnl_ddi_buf_trans *
592cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
593{
594 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
595
596 if (voltage == VOLTAGE_INFO_0_85V) {
597 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
598 return cnl_ddi_translations_hdmi_0_85V;
599 } else if (voltage == VOLTAGE_INFO_0_95V) {
600 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
601 return cnl_ddi_translations_hdmi_0_95V;
602 } else if (voltage == VOLTAGE_INFO_1_05V) {
603 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
604 return cnl_ddi_translations_hdmi_1_05V;
605 } else
606 MISSING_CASE(voltage);
607 return NULL;
608}
609
610static const struct cnl_ddi_buf_trans *
611cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
612{
613 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
614
615 if (voltage == VOLTAGE_INFO_0_85V) {
616 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
617 return cnl_ddi_translations_dp_0_85V;
618 } else if (voltage == VOLTAGE_INFO_0_95V) {
619 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
620 return cnl_ddi_translations_dp_0_95V;
621 } else if (voltage == VOLTAGE_INFO_1_05V) {
622 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
623 return cnl_ddi_translations_dp_1_05V;
624 } else
625 MISSING_CASE(voltage);
626 return NULL;
627}
628
629static const struct cnl_ddi_buf_trans *
630cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
631{
632 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
633
634 if (dev_priv->vbt.edp.low_vswing) {
635 if (voltage == VOLTAGE_INFO_0_85V) {
636 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
637 return cnl_ddi_translations_edp_0_85V;
638 } else if (voltage == VOLTAGE_INFO_0_95V) {
639 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
640 return cnl_ddi_translations_edp_0_95V;
641 } else if (voltage == VOLTAGE_INFO_1_05V) {
642 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
643 return cnl_ddi_translations_edp_1_05V;
644 } else
645 MISSING_CASE(voltage);
646 return NULL;
647 } else {
648 return cnl_get_buf_trans_dp(dev_priv, n_entries);
649 }
650}
651
8d8bb85e
VS		 652static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
653{
654 int n_hdmi_entries;
655 int hdmi_level;
656 int hdmi_default_entry;
657
658 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
659
cc3f90f0 660 if (IS_GEN9_LP(dev_priv))
8d8bb85e
VS		 661 return hdmi_level;
662
b976dc53 663 if (IS_GEN9_BC(dev_priv)) {
8d8bb85e
VS		 664 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
665 hdmi_default_entry = 8;
666 } else if (IS_BROADWELL(dev_priv)) {
667 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
668 hdmi_default_entry = 7;
669 } else if (IS_HASWELL(dev_priv)) {
670 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
671 hdmi_default_entry = 6;
672 } else {
673 WARN(1, "ddi translation table missing\n");
674 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
675 hdmi_default_entry = 7;
676 }
677
678 /* Choose a good default if VBT is badly populated */
679 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
680 hdmi_level >= n_hdmi_entries)
681 hdmi_level = hdmi_default_entry;
682
683 return hdmi_level;
684}
685
7d1c42e6
VS		 686static const struct ddi_buf_trans *
687intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
688 int *n_entries)
689{
da411a48 690 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
7d1c42e6
VS		 691 return kbl_get_buf_trans_dp(dev_priv, n_entries);
692 } else if (IS_SKYLAKE(dev_priv)) {
693 return skl_get_buf_trans_dp(dev_priv, n_entries);
694 } else if (IS_BROADWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
696 return bdw_ddi_translations_dp;
697 } else if (IS_HASWELL(dev_priv)) {
698 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
699 return hsw_ddi_translations_dp;
700 }
701
702 *n_entries = 0;
703 return NULL;
704}
705
706static const struct ddi_buf_trans *
707intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
708 int *n_entries)
709{
da411a48 710 if (IS_GEN9_BC(dev_priv)) {
7d1c42e6
VS		 711 return skl_get_buf_trans_edp(dev_priv, n_entries);
712 } else if (IS_BROADWELL(dev_priv)) {
713 return bdw_get_buf_trans_edp(dev_priv, n_entries);
714 } else if (IS_HASWELL(dev_priv)) {
715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
716 return hsw_ddi_translations_dp;
717 }
718
719 *n_entries = 0;
720 return NULL;
721}
722
723static const struct ddi_buf_trans *
724intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
725 int *n_entries)
726{
727 if (IS_BROADWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
729 return hsw_ddi_translations_fdi;
730 } else if (IS_HASWELL(dev_priv)) {
731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 return hsw_ddi_translations_fdi;
733 }
734
735 *n_entries = 0;
736 return NULL;
737}
738
e58623cb
AR		 739/*
740 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 741 * values in advance. This function programs the correct values for
742 * DP/eDP/FDI use cases.
45244b87 743 */
d7c530b2 744static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
45244b87 745{
6a7e4f99 746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 747 u32 iboost_bit = 0;
7d1c42e6 748 int i, n_entries;
32bdc400 749 enum port port = intel_ddi_get_encoder_port(encoder);
10122051 750 const struct ddi_buf_trans *ddi_translations;
e58623cb 751
7d1c42e6
VS		 752 switch (encoder->type) {
753 case INTEL_OUTPUT_EDP:
754 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
755 &n_entries);
756 break;
757 case INTEL_OUTPUT_DP:
758 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
759 &n_entries);
760 break;
761 case INTEL_OUTPUT_ANALOG:
762 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
763 &n_entries);
764 break;
765 default:
766 MISSING_CASE(encoder->type);
767 return;
e58623cb
AR		 768 }
769
b976dc53 770 if (IS_GEN9_BC(dev_priv)) {
0a91877c
RV		 771 /* If we're boosting the current, set bit 31 of trans1 */
772 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
773 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
774
775 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
776 port != PORT_A && port != PORT_E &&
7d1c42e6
VS		 777 n_entries > 9))
778 n_entries = 9;
300644c7 779 }
45244b87 780
7d1c42e6 781 for (i = 0; i < n_entries; i++) {
9712e688
VS		 782 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
783 ddi_translations[i].trans1 | iboost_bit);
784 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
785 ddi_translations[i].trans2);
45244b87 786 }
32bdc400
VS		 787}
788
789/*
790 * Starting with Haswell, DDI port buffers must be programmed with correct
791 * values in advance. This function programs the correct values for
792 * HDMI/DVI use cases.
793 */
794static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
795{
796 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
797 u32 iboost_bit = 0;
798 int n_hdmi_entries, hdmi_level;
799 enum port port = intel_ddi_get_encoder_port(encoder);
800 const struct ddi_buf_trans *ddi_translations_hdmi;
ce4dd49e 801
32bdc400
VS		 802 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
803
b976dc53 804 if (IS_GEN9_BC(dev_priv)) {
32bdc400 805 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
1edaaa2f 806
32bdc400 807 /* If we're boosting the current, set bit 31 of trans1 */
1edaaa2f 808 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
32bdc400
VS		 809 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
810 } else if (IS_BROADWELL(dev_priv)) {
811 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
812 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
813 } else if (IS_HASWELL(dev_priv)) {
814 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
815 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
816 } else {
817 WARN(1, "ddi translation table missing\n");
818 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
819 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
820 }
821
6acab15a 822 /* Entry 9 is for HDMI: */
ed9c77d2 823 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
9712e688 824 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
ed9c77d2 825 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
9712e688 826 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 827}
828
248138b5
PZ		 829static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
830 enum port port)
831{
f0f59a00 832 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 833 int i;
834
3449ca85 835 for (i = 0; i < 16; i++) {
248138b5
PZ		 836 udelay(1);
837 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
838 return;
839 }
840 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
841}
c82e4d26 842
5f88a9c6 843static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a
ACO		 844{
845 switch (pll->id) {
846 case DPLL_ID_WRPLL1:
847 return PORT_CLK_SEL_WRPLL1;
848 case DPLL_ID_WRPLL2:
849 return PORT_CLK_SEL_WRPLL2;
850 case DPLL_ID_SPLL:
851 return PORT_CLK_SEL_SPLL;
852 case DPLL_ID_LCPLL_810:
853 return PORT_CLK_SEL_LCPLL_810;
854 case DPLL_ID_LCPLL_1350:
855 return PORT_CLK_SEL_LCPLL_1350;
856 case DPLL_ID_LCPLL_2700:
857 return PORT_CLK_SEL_LCPLL_2700;
858 default:
859 MISSING_CASE(pll->id);
860 return PORT_CLK_SEL_NONE;
861 }
862}
863
c82e4d26
ED		 864/* Starting with Haswell, different DDI ports can work in FDI mode for
865 * connection to the PCH-located connectors. For this, it is necessary to train
866 * both the DDI port and PCH receiver for the desired DDI buffer settings.
867 *
868 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
869 * please note that when FDI mode is active on DDI E, it shares 2 lines with
870 * DDI A (which is used for eDP)
871 */
872
dc4a1094
ACO		 873void hsw_fdi_link_train(struct intel_crtc *crtc,
874 const struct intel_crtc_state *crtc_state)
c82e4d26 875{
4cbe4b2b 876 struct drm_device *dev = crtc->base.dev;
fac5e23e 877 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 878 struct intel_encoder *encoder;
c856052a 879 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 880
4cbe4b2b 881 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 882 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
32bdc400 883 intel_prepare_dp_ddi_buffers(encoder);
6a7e4f99
VS		 884 }
885
04945641
PZ		 886 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
887 * mode set "sequence for CRT port" document:
888 * - TP1 to TP2 time with the default value
889 * - FDI delay to 90h
8693a824
DL		 890 *
891 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 892 */
eede3b53 893 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 894 FDI_RX_PWRDN_LANE0_VAL(2) |
895 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
896
897 /* Enable the PCH Receiver FDI PLL */
3e68320e 898 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 899 FDI_RX_PLL_ENABLE |
dc4a1094 900 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 901 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
902 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 903 udelay(220);
904
905 /* Switch from Rawclk to PCDclk */
906 rx_ctl_val |= FDI_PCDCLK;
eede3b53 907 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 908
909 /* Configure Port Clock Select */
dc4a1094 910 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 911 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
912 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 913
914 /* Start the training iterating through available voltages and emphasis,
915 * testing each value twice. */
10122051 916 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 917 /* Configure DP_TP_CTL with auto-training */
918 I915_WRITE(DP_TP_CTL(PORT_E),
919 DP_TP_CTL_FDI_AUTOTRAIN |
920 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
921 DP_TP_CTL_LINK_TRAIN_PAT1 |
922 DP_TP_CTL_ENABLE);
923
876a8cdf
DL		 924 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
925 * DDI E does not support port reversal, the functionality is
926 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
927 * port reversal bit */
c82e4d26 928 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 929 DDI_BUF_CTL_ENABLE |
dc4a1094 930 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 931 DDI_BUF_TRANS_SELECT(i / 2));
04945641 932 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 933
934 udelay(600);
935
04945641 936 /* Program PCH FDI Receiver TU */
eede3b53 937 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 938
939 /* Enable PCH FDI Receiver with auto-training */
940 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 941 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
942 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 943
944 /* Wait for FDI receiver lane calibration */
945 udelay(30);
946
947 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 948 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 949 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 950 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
951 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 952
953 /* Wait for FDI auto training time */
954 udelay(5);
c82e4d26
ED		 955
956 temp = I915_READ(DP_TP_STATUS(PORT_E));
957 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 958 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 959 break;
960 }
c82e4d26 961
a308ccb3
VS		 962 /*
963 * Leave things enabled even if we failed to train FDI.
964 * Results in less fireworks from the state checker.
965 */
966 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
967 DRM_ERROR("FDI link training failed!\n");
968 break;
c82e4d26 969 }
04945641 970
5b421c57
VS		 971 rx_ctl_val &= ~FDI_RX_ENABLE;
972 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
973 POSTING_READ(FDI_RX_CTL(PIPE_A));
974
248138b5
PZ		 975 temp = I915_READ(DDI_BUF_CTL(PORT_E));
976 temp &= ~DDI_BUF_CTL_ENABLE;
977 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
978 POSTING_READ(DDI_BUF_CTL(PORT_E));
979
04945641 980 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 981 temp = I915_READ(DP_TP_CTL(PORT_E));
982 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
983 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
984 I915_WRITE(DP_TP_CTL(PORT_E), temp);
985 POSTING_READ(DP_TP_CTL(PORT_E));
986
987 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 988
04945641 989 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 990 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 991 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
992 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 993 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
994 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 995 }
996
a308ccb3
VS		 997 /* Enable normal pixel sending for FDI */
998 I915_WRITE(DP_TP_CTL(PORT_E),
999 DP_TP_CTL_FDI_AUTOTRAIN |
1000 DP_TP_CTL_LINK_TRAIN_NORMAL |
1001 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1002 DP_TP_CTL_ENABLE);
c82e4d26 1003}
0e72a5b5 1004
d7c530b2 1005static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1006{
1007 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1008 struct intel_digital_port *intel_dig_port =
1009 enc_to_dig_port(&encoder->base);
1010
1011 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1012 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1013 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1014}
1015
8d9ddbcb 1016static struct intel_encoder *
e9ce1a62 1017intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1018{
e9ce1a62 1019 struct drm_device *dev = crtc->base.dev;
1524e93e 1020 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1021 int num_encoders = 0;
1022
1524e93e
SS		 1023 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1024 ret = encoder;
8d9ddbcb
PZ		 1025 num_encoders++;
1026 }
1027
1028 if (num_encoders != 1)
84f44ce7 1029 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1030 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1031
1032 BUG_ON(ret == NULL);
1033 return ret;
1034}
1035
44a126ba
PZ		 1036/* Finds the only possible encoder associated with the given CRTC. */
1037struct intel_encoder *
3165c074 1038intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 1039{
3165c074
ACO		 1040 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1041 struct intel_encoder *ret = NULL;
1042 struct drm_atomic_state *state;
da3ced29
ACO		 1043 struct drm_connector *connector;
1044 struct drm_connector_state *connector_state;
d0737e1d 1045 int num_encoders = 0;
3165c074 1046 int i;
d0737e1d 1047
3165c074
ACO		 1048 state = crtc_state->base.state;
1049
b77c7a90 1050 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 1051 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 1052 continue;
1053
da3ced29 1054 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 1055 num_encoders++;
d0737e1d
ACO		 1056 }
1057
1058 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1059 pipe_name(crtc->pipe));
1060
1061 BUG_ON(ret == NULL);
1062 return ret;
1063}
1064
1c0b85c5 1065#define LC_FREQ 2700
1c0b85c5 1066
f0f59a00
VS		 1067static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1068 i915_reg_t reg)
11578553
JB		 1069{
1070 int refclk = LC_FREQ;
1071 int n, p, r;
1072 u32 wrpll;
1073
1074 wrpll = I915_READ(reg);
114fe488
DV		 1075 switch (wrpll & WRPLL_PLL_REF_MASK) {
1076 case WRPLL_PLL_SSC:
1077 case WRPLL_PLL_NON_SSC:
11578553
JB		 1078 /*
1079 * We could calculate spread here, but our checking
1080 * code only cares about 5% accuracy, and spread is a max of
1081 * 0.5% downspread.
1082 */
1083 refclk = 135;
1084 break;
114fe488 1085 case WRPLL_PLL_LCPLL:
11578553
JB		 1086 refclk = LC_FREQ;
1087 break;
1088 default:
1089 WARN(1, "bad wrpll refclk\n");
1090 return 0;
1091 }
1092
1093 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1094 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1095 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1096
20f0ec16
JB		 1097 /* Convert to KHz, p & r have a fixed point portion */
1098 return (refclk * n * 100) / (p * r);
11578553
JB		 1099}
1100
540e732c
S		 1101static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1102 uint32_t dpll)
1103{
f0f59a00 1104 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1105 uint32_t cfgcr1_val, cfgcr2_val;
1106 uint32_t p0, p1, p2, dco_freq;
1107
923c1241
VS		 1108 cfgcr1_reg = DPLL_CFGCR1(dpll);
1109 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 1110
1111 cfgcr1_val = I915_READ(cfgcr1_reg);
1112 cfgcr2_val = I915_READ(cfgcr2_reg);
1113
1114 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1115 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1116
1117 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1118 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1119 else
1120 p1 = 1;
1121
1122
1123 switch (p0) {
1124 case DPLL_CFGCR2_PDIV_1:
1125 p0 = 1;
1126 break;
1127 case DPLL_CFGCR2_PDIV_2:
1128 p0 = 2;
1129 break;
1130 case DPLL_CFGCR2_PDIV_3:
1131 p0 = 3;
1132 break;
1133 case DPLL_CFGCR2_PDIV_7:
1134 p0 = 7;
1135 break;
1136 }
1137
1138 switch (p2) {
1139 case DPLL_CFGCR2_KDIV_5:
1140 p2 = 5;
1141 break;
1142 case DPLL_CFGCR2_KDIV_2:
1143 p2 = 2;
1144 break;
1145 case DPLL_CFGCR2_KDIV_3:
1146 p2 = 3;
1147 break;
1148 case DPLL_CFGCR2_KDIV_1:
1149 p2 = 1;
1150 break;
1151 }
1152
1153 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1154
1155 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1156 1000) / 0x8000;
1157
1158 return dco_freq / (p0 * p1 * p2 * 5);
1159}
1160
a9701a89
RV		 1161static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1162 uint32_t pll_id)
1163{
1164 uint32_t cfgcr0, cfgcr1;
1165 uint32_t p0, p1, p2, dco_freq, ref_clock;
1166
1167 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1168 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1169
1170 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1171 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1172
1173 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1174 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1175 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1176 else
1177 p1 = 1;
1178
1179
1180 switch (p0) {
1181 case DPLL_CFGCR1_PDIV_2:
1182 p0 = 2;
1183 break;
1184 case DPLL_CFGCR1_PDIV_3:
1185 p0 = 3;
1186 break;
1187 case DPLL_CFGCR1_PDIV_5:
1188 p0 = 5;
1189 break;
1190 case DPLL_CFGCR1_PDIV_7:
1191 p0 = 7;
1192 break;
1193 }
1194
1195 switch (p2) {
1196 case DPLL_CFGCR1_KDIV_1:
1197 p2 = 1;
1198 break;
1199 case DPLL_CFGCR1_KDIV_2:
1200 p2 = 2;
1201 break;
1202 case DPLL_CFGCR1_KDIV_4:
1203 p2 = 4;
1204 break;
1205 }
1206
1207 ref_clock = dev_priv->cdclk.hw.ref;
1208
1209 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1210
1211 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1212 DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
1213
1214 return dco_freq / (p0 * p1 * p2 * 5);
1215}
1216
398a017e
VS		 1217static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1218{
1219 int dotclock;
1220
1221 if (pipe_config->has_pch_encoder)
1222 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1223 &pipe_config->fdi_m_n);
37a5650b 1224 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1225 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1226 &pipe_config->dp_m_n);
1227 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1228 dotclock = pipe_config->port_clock * 2 / 3;
1229 else
1230 dotclock = pipe_config->port_clock;
1231
b22ca995
SS		 1232 if (pipe_config->ycbcr420)
1233 dotclock *= 2;
1234
398a017e
VS		 1235 if (pipe_config->pixel_multiplier)
1236 dotclock /= pipe_config->pixel_multiplier;
1237
1238 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1239}
540e732c 1240
a9701a89
RV		 1241static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1242 struct intel_crtc_state *pipe_config)
1243{
1244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1245 int link_clock = 0;
1246 uint32_t cfgcr0, pll_id;
1247
1248 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1249
1250 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1251
1252 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1253 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1254 } else {
1255 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1256
1257 switch (link_clock) {
1258 case DPLL_CFGCR0_LINK_RATE_810:
1259 link_clock = 81000;
1260 break;
1261 case DPLL_CFGCR0_LINK_RATE_1080:
1262 link_clock = 108000;
1263 break;
1264 case DPLL_CFGCR0_LINK_RATE_1350:
1265 link_clock = 135000;
1266 break;
1267 case DPLL_CFGCR0_LINK_RATE_1620:
1268 link_clock = 162000;
1269 break;
1270 case DPLL_CFGCR0_LINK_RATE_2160:
1271 link_clock = 216000;
1272 break;
1273 case DPLL_CFGCR0_LINK_RATE_2700:
1274 link_clock = 270000;
1275 break;
1276 case DPLL_CFGCR0_LINK_RATE_3240:
1277 link_clock = 324000;
1278 break;
1279 case DPLL_CFGCR0_LINK_RATE_4050:
1280 link_clock = 405000;
1281 break;
1282 default:
1283 WARN(1, "Unsupported link rate\n");
1284 break;
1285 }
1286 link_clock *= 2;
1287 }
1288
1289 pipe_config->port_clock = link_clock;
1290
1291 ddi_dotclock_get(pipe_config);
1292}
1293
540e732c 1294static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1295 struct intel_crtc_state *pipe_config)
540e732c 1296{
fac5e23e 1297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 1298 int link_clock = 0;
1299 uint32_t dpll_ctl1, dpll;
1300
c856052a 1301 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1302
1303 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1304
1305 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1306 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1307 } else {
71cd8423
DL		 1308 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1309 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1310
1311 switch (link_clock) {
71cd8423 1312 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1313 link_clock = 81000;
1314 break;
71cd8423 1315 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1316 link_clock = 108000;
1317 break;
71cd8423 1318 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1319 link_clock = 135000;
1320 break;
71cd8423 1321 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1322 link_clock = 162000;
1323 break;
71cd8423 1324 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1325 link_clock = 216000;
1326 break;
71cd8423 1327 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1328 link_clock = 270000;
1329 break;
1330 default:
1331 WARN(1, "Unsupported link rate\n");
1332 break;
1333 }
1334 link_clock *= 2;
1335 }
1336
1337 pipe_config->port_clock = link_clock;
1338
398a017e 1339 ddi_dotclock_get(pipe_config);
540e732c
S		 1340}
1341
3d51278a 1342static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1343 struct intel_crtc_state *pipe_config)
11578553 1344{
fac5e23e 1345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1346 int link_clock = 0;
1347 u32 val, pll;
1348
c856052a 1349 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1350 switch (val & PORT_CLK_SEL_MASK) {
1351 case PORT_CLK_SEL_LCPLL_810:
1352 link_clock = 81000;
1353 break;
1354 case PORT_CLK_SEL_LCPLL_1350:
1355 link_clock = 135000;
1356 break;
1357 case PORT_CLK_SEL_LCPLL_2700:
1358 link_clock = 270000;
1359 break;
1360 case PORT_CLK_SEL_WRPLL1:
01403de3 1361 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1362 break;
1363 case PORT_CLK_SEL_WRPLL2:
01403de3 1364 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1365 break;
1366 case PORT_CLK_SEL_SPLL:
1367 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1368 if (pll == SPLL_PLL_FREQ_810MHz)
1369 link_clock = 81000;
1370 else if (pll == SPLL_PLL_FREQ_1350MHz)
1371 link_clock = 135000;
1372 else if (pll == SPLL_PLL_FREQ_2700MHz)
1373 link_clock = 270000;
1374 else {
1375 WARN(1, "bad spll freq\n");
1376 return;
1377 }
1378 break;
1379 default:
1380 WARN(1, "bad port clock sel\n");
1381 return;
1382 }
1383
1384 pipe_config->port_clock = link_clock * 2;
1385
398a017e 1386 ddi_dotclock_get(pipe_config);
11578553
JB		 1387}
1388
977bb38d
S		 1389static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1390 enum intel_dpll_id dpll)
1391{
aa610dcb
ID		 1392 struct intel_shared_dpll *pll;
1393 struct intel_dpll_hw_state *state;
9e2c8475 1394 struct dpll clock;
aa610dcb
ID		 1395
1396 /* For DDI ports we always use a shared PLL. */
1397 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1398 return 0;
1399
1400 pll = &dev_priv->shared_dplls[dpll];
2c42e535 1401 state = &pll->state.hw_state;
aa610dcb
ID		 1402
1403 clock.m1 = 2;
1404 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1405 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1406 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1407 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1408 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1409 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1410
1411 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1412}
1413
1414static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1415 struct intel_crtc_state *pipe_config)
1416{
fac5e23e 1417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 1418 enum port port = intel_ddi_get_encoder_port(encoder);
1419 uint32_t dpll = port;
1420
398a017e 1421 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1422
398a017e 1423 ddi_dotclock_get(pipe_config);
977bb38d
S		 1424}
1425
3d51278a 1426void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1427 struct intel_crtc_state *pipe_config)
3d51278a 1428{
0853723b 1429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1430
0853723b 1431 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1432 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1433 else if (IS_GEN9_BC(dev_priv))
22606a18 1434 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1435 else if (IS_GEN9_LP(dev_priv))
977bb38d 1436 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1437 else if (IS_CANNONLAKE(dev_priv))
1438 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1439}
1440
3dc38eea 1441void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1442{
3dc38eea 1443 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1445 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
3dc38eea 1446 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e 1447 int type = encoder->type;
dae84799
PZ		 1448 uint32_t temp;
1449
cca0502b 1450 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1451 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1452
c9809791 1453 temp = TRANS_MSA_SYNC_CLK;
3dc38eea 1454 switch (crtc_state->pipe_bpp) {
dae84799 1455 case 18:
c9809791 1456 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1457 break;
1458 case 24:
c9809791 1459 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1460 break;
1461 case 30:
c9809791 1462 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1463 break;
1464 case 36:
c9809791 1465 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1466 break;
1467 default:
4e53c2e0 1468 BUG();
dae84799 1469 }
c9809791 1470 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1471 }
1472}
1473
3dc38eea
ACO		 1474void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1475 bool state)
0e32b39c 1476{
3dc38eea 1477 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1478 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1479 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c
DA		 1480 uint32_t temp;
1481 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1482 if (state == true)
1483 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1484 else
1485 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1486 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1487}
1488
3dc38eea 1489void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1490{
3dc38eea 1491 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1492 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1493 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1494 enum pipe pipe = crtc->pipe;
3dc38eea 1495 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1524e93e
SS		 1496 enum port port = intel_ddi_get_encoder_port(encoder);
1497 int type = encoder->type;
8d9ddbcb
PZ		 1498 uint32_t temp;
1499
ad80a810
PZ		 1500 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1501 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1502 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1503
3dc38eea 1504 switch (crtc_state->pipe_bpp) {
dfcef252 1505 case 18:
ad80a810 1506 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1507 break;
1508 case 24:
ad80a810 1509 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1510 break;
1511 case 30:
ad80a810 1512 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1513 break;
1514 case 36:
ad80a810 1515 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1516 break;
1517 default:
4e53c2e0 1518 BUG();
dfcef252 1519 }
72662e10 1520
3dc38eea 1521 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1522 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1523 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1524 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1525
e6f0bfc4
PZ		 1526 if (cpu_transcoder == TRANSCODER_EDP) {
1527 switch (pipe) {
1528 case PIPE_A:
c7670b10
PZ		 1529 /* On Haswell, can only use the always-on power well for
1530 * eDP when not using the panel fitter, and when not
1531 * using motion blur mitigation (which we don't
1532 * support). */
772c2a51 1533 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1534 (crtc_state->pch_pfit.enabled ||
1535 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1536 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1537 else
1538 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1539 break;
1540 case PIPE_B:
1541 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1542 break;
1543 case PIPE_C:
1544 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1545 break;
1546 default:
1547 BUG();
1548 break;
1549 }
1550 }
1551
7739c33b 1552 if (type == INTEL_OUTPUT_HDMI) {
3dc38eea 1553 if (crtc_state->has_hdmi_sink)
ad80a810 1554 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1555 else
ad80a810 1556 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1557
1558 if (crtc_state->hdmi_scrambling)
1559 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1560 if (crtc_state->hdmi_high_tmds_clock_ratio)
1561 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
7739c33b 1562 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1563 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1564 temp |= (crtc_state->fdi_lanes - 1) << 1;
cca0502b 1565 } else if (type == INTEL_OUTPUT_DP ||
7739c33b 1566 type == INTEL_OUTPUT_EDP) {
64ee2fd2 1567 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
3dc38eea 1568 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
0e32b39c 1569 } else if (type == INTEL_OUTPUT_DP_MST) {
64ee2fd2 1570 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1572 } else {
84f44ce7 1573 WARN(1, "Invalid encoder type %d for pipe %c\n",
1524e93e 1574 encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1575 }
1576
ad80a810 1577 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1578}
72662e10 1579
ad80a810
PZ		 1580void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1581 enum transcoder cpu_transcoder)
8d9ddbcb 1582{
f0f59a00 1583 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1584 uint32_t val = I915_READ(reg);
1585
0e32b39c 1586 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1587 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1588 I915_WRITE(reg, val);
72662e10
ED		 1589}
1590
bcbc889b
PZ		 1591bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1592{
1593 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1594 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1595 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1596 int type = intel_connector->base.connector_type;
1524e93e 1597 enum port port = intel_ddi_get_encoder_port(encoder);
bcbc889b
PZ		 1598 enum pipe pipe = 0;
1599 enum transcoder cpu_transcoder;
1600 uint32_t tmp;
e27daab4 1601 bool ret;
bcbc889b 1602
79f255a0 1603 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1604 encoder->power_domain))
882244a3
PZ		 1605 return false;
1606
1524e93e 1607 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1608 ret = false;
1609 goto out;
1610 }
bcbc889b
PZ		 1611
1612 if (port == PORT_A)
1613 cpu_transcoder = TRANSCODER_EDP;
1614 else
1a240d4d 1615 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1616
1617 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1618
1619 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1620 case TRANS_DDI_MODE_SELECT_HDMI:
1621 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1622 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1623 break;
bcbc889b
PZ		 1624
1625 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1626 ret = type == DRM_MODE_CONNECTOR_eDP ||
1627 type == DRM_MODE_CONNECTOR_DisplayPort;
1628 break;
1629
0e32b39c
DA		 1630 case TRANS_DDI_MODE_SELECT_DP_MST:
1631 /* if the transcoder is in MST state then
1632 * connector isn't connected */
e27daab4
ID		 1633 ret = false;
1634 break;
bcbc889b
PZ		 1635
1636 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1637 ret = type == DRM_MODE_CONNECTOR_VGA;
1638 break;
bcbc889b
PZ		 1639
1640 default:
e27daab4
ID		 1641 ret = false;
1642 break;
bcbc889b 1643 }
e27daab4
ID		 1644
1645out:
1524e93e 1646 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1647
1648 return ret;
bcbc889b
PZ		 1649}
1650
85234cdc
DV		 1651bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1652 enum pipe *pipe)
1653{
1654 struct drm_device *dev = encoder->base.dev;
fac5e23e 1655 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1656 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1657 u32 tmp;
1658 int i;
e27daab4 1659 bool ret;
85234cdc 1660
79f255a0
ACO		 1661 if (!intel_display_power_get_if_enabled(dev_priv,
1662 encoder->power_domain))
6d129bea
ID		 1663 return false;
1664
e27daab4
ID		 1665 ret = false;
1666
fe43d3f5 1667 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1668
1669 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1670 goto out;
85234cdc 1671
ad80a810
PZ		 1672 if (port == PORT_A) {
1673 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1674
ad80a810
PZ		 1675 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1676 case TRANS_DDI_EDP_INPUT_A_ON:
1677 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1678 *pipe = PIPE_A;
1679 break;
1680 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1681 *pipe = PIPE_B;
1682 break;
1683 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1684 *pipe = PIPE_C;
1685 break;
1686 }
1687
e27daab4 1688 ret = true;
ad80a810 1689
e27daab4
ID		 1690 goto out;
1691 }
0e32b39c 1692
e27daab4
ID		 1693 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1694 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1695
1696 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1697 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1698 TRANS_DDI_MODE_SELECT_DP_MST)
1699 goto out;
1700
1701 *pipe = i;
1702 ret = true;
1703
1704 goto out;
85234cdc
DV		 1705 }
1706 }
1707
84f44ce7 1708 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1709
e27daab4 1710out:
cc3f90f0 1711 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0
ID		 1712 tmp = I915_READ(BXT_PHY_CTL(port));
1713 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1714 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1715 DRM_ERROR("Port %c enabled but PHY powered down? "
1716 "(PHY_CTL %08x)\n", port_name(port), tmp);
1717 }
1718
79f255a0 1719 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1720
1721 return ret;
85234cdc
DV		 1722}
1723
62b69566
ACO		 1724static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1725{
1726 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1727 enum pipe pipe;
1728
1729 if (intel_ddi_get_hw_state(encoder, &pipe))
1730 return BIT_ULL(dig_port->ddi_io_power_domain);
1731
1732 return 0;
1733}
1734
3dc38eea 1735void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1736{
3dc38eea 1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e
SS		 1739 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1740 enum port port = intel_ddi_get_encoder_port(encoder);
3dc38eea 1741 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1742
bb523fc0
PZ		 1743 if (cpu_transcoder != TRANSCODER_EDP)
1744 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1745 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1746}
1747
3dc38eea 1748void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1749{
3dc38eea
ACO		 1750 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1751 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1752
bb523fc0
PZ		 1753 if (cpu_transcoder != TRANSCODER_EDP)
1754 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1755 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1756}
1757
a7d8dbc0
VS		 1758static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1759 enum port port, uint8_t iboost)
f8896f5d 1760{
a7d8dbc0
VS		 1761 u32 tmp;
1762
1763 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1764 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1765 if (iboost)
1766 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1767 else
1768 tmp |= BALANCE_LEG_DISABLE(port);
1769 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1770}
1771
1772static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1773{
1774 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1775 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1776 enum port port = intel_dig_port->port;
1777 int type = encoder->type;
f8896f5d
DW		 1778 const struct ddi_buf_trans *ddi_translations;
1779 uint8_t iboost;
75067dde 1780 uint8_t dp_iboost, hdmi_iboost;
f8896f5d 1781 int n_entries;
f8896f5d 1782
75067dde
AK		 1783 /* VBT may override standard boost values */
1784 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1785 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1786
cca0502b 1787 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1788 if (dp_iboost) {
1789 iboost = dp_iboost;
1790 } else {
da411a48 1791 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 1792 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1793 &n_entries);
1794 else
1795 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1796 &n_entries);
e4d4c05b 1797 iboost = ddi_translations[level].i_boost;
75067dde 1798 }
f8896f5d 1799 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1800 if (dp_iboost) {
1801 iboost = dp_iboost;
1802 } else {
78ab0bae 1803 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1804
1805 if (WARN_ON(port != PORT_A &&
1806 port != PORT_E && n_entries > 9))
1807 n_entries = 9;
1808
e4d4c05b 1809 iboost = ddi_translations[level].i_boost;
75067dde 1810 }
f8896f5d 1811 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1812 if (hdmi_iboost) {
1813 iboost = hdmi_iboost;
1814 } else {
78ab0bae 1815 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1816 iboost = ddi_translations[level].i_boost;
75067dde 1817 }
f8896f5d
DW		 1818 } else {
1819 return;
1820 }
1821
1822 /* Make sure that the requested I_boost is valid */
1823 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1824 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1825 return;
1826 }
1827
a7d8dbc0 1828 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1829
a7d8dbc0
VS		 1830 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1831 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1832}
1833
78ab0bae
VS		 1834static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1835 u32 level, enum port port, int type)
96fb9f9b 1836{
96fb9f9b
VK		 1837 const struct bxt_ddi_buf_trans *ddi_translations;
1838 u32 n_entries, i;
96fb9f9b 1839
06411f08 1840 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1841 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1842 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1843 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1844 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1845 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1846 ddi_translations = bxt_ddi_translations_dp;
1847 } else if (type == INTEL_OUTPUT_HDMI) {
1848 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1849 ddi_translations = bxt_ddi_translations_hdmi;
1850 } else {
1851 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1852 type);
1853 return;
1854 }
1855
1856 /* Check if default value has to be used */
1857 if (level >= n_entries ||
1858 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1859 for (i = 0; i < n_entries; i++) {
1860 if (ddi_translations[i].default_index) {
1861 level = i;
1862 break;
1863 }
1864 }
1865 }
1866
b6e08203
ACO		 1867 bxt_ddi_phy_set_signal_level(dev_priv, port,
1868 ddi_translations[level].margin,
1869 ddi_translations[level].scale,
1870 ddi_translations[level].enable,
1871 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1872}
1873
ffe5111e
VS		 1874u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1875{
1876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1877 int n_entries;
1878
1879 if (encoder->type == INTEL_OUTPUT_EDP)
1880 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1881 else
1882 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1883
1884 if (WARN_ON(n_entries < 1))
1885 n_entries = 1;
1886 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1887 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1888
1889 return index_to_dp_signal_levels[n_entries - 1] &
1890 DP_TRAIN_VOLTAGE_SWING_MASK;
1891}
1892
cf54ca8b
RV		 1893static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1894 u32 level, enum port port, int type)
1895{
1896 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
cc9cabfd 1897 u32 n_entries, val;
cf54ca8b
RV		 1898 int ln;
1899
cf54ca8b 1900 if (type == INTEL_OUTPUT_HDMI) {
cc9cabfd 1901 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
cf54ca8b 1902 } else if (type == INTEL_OUTPUT_DP) {
cc9cabfd 1903 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 1904 } else if (type == INTEL_OUTPUT_EDP) {
cc9cabfd 1905 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
cf54ca8b
RV		 1906 }
1907
cc9cabfd 1908 if (WARN_ON(ddi_translations == NULL))
cf54ca8b 1909 return;
cf54ca8b
RV		 1910
1911 if (level >= n_entries) {
1912 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1913 level = n_entries - 1;
1914 }
1915
1916 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1917 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1918 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1919 val |= SCALING_MODE_SEL(2);
1920 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1921
1922 /* Program PORT_TX_DW2 */
1923 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1924 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1925 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1926 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1927 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1928 /* Rcomp scalar is fixed as 0x98 for every table entry */
1929 val |= RCOMP_SCALAR(0x98);
1930 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1931
1932 /* Program PORT_TX_DW4 */
1933 /* We cannot write to GRP. It would overrite individual loadgen */
1934 for (ln = 0; ln < 4; ln++) {
1935 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1936 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1937 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1938 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1939 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1940 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1941 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1942 }
1943
1944 /* Program PORT_TX_DW5 */
1945 /* All DW5 values are fixed for every table entry */
1946 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1947 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1948 val |= RTERM_SELECT(6);
1949 val |= TAP3_DISABLE;
1950 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1951
1952 /* Program PORT_TX_DW7 */
1953 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1954 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1955 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1956 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1957}
1958
0091abc3 1959static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
cf54ca8b 1960{
0091abc3
CT		 1961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1962 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1963 enum port port = intel_ddi_get_encoder_port(encoder);
1964 int type = encoder->type;
1965 int width = 0;
1966 int rate = 0;
cf54ca8b 1967 u32 val;
0091abc3
CT		 1968 int ln = 0;
1969
1970 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1971 width = intel_dp->lane_count;
1972 rate = intel_dp->link_rate;
61f3e770 1973 } else if (type == INTEL_OUTPUT_HDMI) {
0091abc3
CT		 1974 width = 4;
1975 /* Rate is always < than 6GHz for HDMI */
61f3e770
RV		 1976 } else {
1977 MISSING_CASE(type);
1978 return;
0091abc3 1979 }
cf54ca8b
RV		 1980
1981 /*
1982 * 1. If port type is eDP or DP,
1983 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1984 * else clear to 0b.
1985 */
1986 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1987 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1988 val |= COMMON_KEEPER_EN;
1989 else
1990 val &= ~COMMON_KEEPER_EN;
1991 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1992
1993 /* 2. Program loadgen select */
1994 /*
0091abc3
CT		 1995 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1996 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1997 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1998 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 1999 */
0091abc3
CT		 2000 for (ln = 0; ln <= 3; ln++) {
2001 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2002 val &= ~LOADGEN_SELECT;
2003
a8e45a1c
NM		 2004 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2005 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2006 val |= LOADGEN_SELECT;
2007 }
2008 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2009 }
cf54ca8b
RV		 2010
2011 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2012 val = I915_READ(CNL_PORT_CL1CM_DW5);
2013 val |= SUS_CLOCK_CONFIG;
2014 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2015
2016 /* 4. Clear training enable to change swing values */
2017 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2018 val &= ~TX_TRAINING_EN;
2019 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2020
2021 /* 5. Program swing and de-emphasis */
2022 cnl_ddi_vswing_program(dev_priv, level, port, type);
2023
2024 /* 6. Set training enable to trigger update */
2025 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2026 val |= TX_TRAINING_EN;
2027 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2028}
2029
f8896f5d
DW		 2030static uint32_t translate_signal_level(int signal_levels)
2031{
97eeb872 2032 int i;
f8896f5d 2033
97eeb872
VS		 2034 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2035 if (index_to_dp_signal_levels[i] == signal_levels)
2036 return i;
f8896f5d
DW		 2037 }
2038
97eeb872
VS		 2039 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2040 signal_levels);
2041
2042 return 0;
f8896f5d
DW		 2043}
2044
1b6e2fd2
RV		 2045static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2046{
2047 uint8_t train_set = intel_dp->train_set[0];
2048 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2049 DP_TRAIN_PRE_EMPHASIS_MASK);
2050
2051 return translate_signal_level(signal_levels);
2052}
2053
d509af6c 2054u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2055{
2056 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2057 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2058 struct intel_encoder *encoder = &dport->base;
f8896f5d 2059 enum port port = dport->port;
d509af6c
RV		 2060 u32 level = intel_ddi_dp_level(intel_dp);
2061
2062 if (IS_CANNONLAKE(dev_priv))
2063 cnl_ddi_vswing_sequence(encoder, level);
2064 else
2065 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2066
2067 return 0;
2068}
2069
2070uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2071{
2072 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2073 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2074 struct intel_encoder *encoder = &dport->base;
1b6e2fd2 2075 uint32_t level = intel_ddi_dp_level(intel_dp);
f8896f5d 2076
b976dc53 2077 if (IS_GEN9_BC(dev_priv))
d509af6c
RV		 2078 skl_ddi_set_iboost(encoder, level);
2079
f8896f5d
DW		 2080 return DDI_BUF_TRANS_SELECT(level);
2081}
2082
d7c530b2 2083static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2084 const struct intel_shared_dpll *pll)
6441ab5f 2085{
e404ba8d
VS		 2086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2087 enum port port = intel_ddi_get_encoder_port(encoder);
555e38d2 2088 uint32_t val;
6441ab5f 2089
c856052a
ACO		 2090 if (WARN_ON(!pll))
2091 return;
2092
555e38d2
RV		 2093 if (IS_CANNONLAKE(dev_priv)) {
2094 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2095 val = I915_READ(DPCLKA_CFGCR0);
2096 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2097 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2098
555e38d2
RV		 2099 /*
2100 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2101 * This step and the step before must be done with separate
2102 * register writes.
2103 */
2104 val = I915_READ(DPCLKA_CFGCR0);
2105 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2106 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2107 I915_WRITE(DPCLKA_CFGCR0, val);
2108 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2109 /* DDI -> PLL mapping */
efa80add
S		 2110 val = I915_READ(DPLL_CTRL2);
2111
2112 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2113 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2114 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2115 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2116
2117 I915_WRITE(DPLL_CTRL2, val);
5416d871 2118
e404ba8d 2119 } else if (INTEL_INFO(dev_priv)->gen < 9) {
c856052a 2120 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2121 }
e404ba8d
VS		 2122}
2123
ba88d153
MN		 2124static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2125 int link_rate, uint32_t lane_count,
2126 struct intel_shared_dpll *pll,
2127 bool link_mst)
e404ba8d 2128{
ba88d153
MN		 2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2131 enum port port = intel_ddi_get_encoder_port(encoder);
62b69566 2132 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
381f9570 2133 uint32_t level = intel_ddi_dp_level(intel_dp);
b2ccb822 2134
e081c846
ACO		 2135 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2136
ba88d153
MN		 2137 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2138 link_mst);
2139 if (encoder->type == INTEL_OUTPUT_EDP)
e404ba8d 2140 intel_edp_panel_on(intel_dp);
32bdc400 2141
ba88d153 2142 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2143
2144 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2145
381f9570
RV		 2146 if (IS_CANNONLAKE(dev_priv))
2147 cnl_ddi_vswing_sequence(encoder, level);
2148 else if (IS_GEN9_LP(dev_priv))
2149 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2150 else
2f7460a7
RV		 2151 intel_prepare_dp_ddi_buffers(encoder);
2152
ba88d153
MN		 2153 intel_ddi_init_dp_buf_reg(encoder);
2154 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2155 intel_dp_start_link_train(intel_dp);
2156 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2157 intel_dp_stop_link_train(intel_dp);
2158}
901c2daf 2159
ba88d153 2160static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
b47ef0f7 2161 bool has_infoframe,
ac240288
ML		 2162 const struct intel_crtc_state *crtc_state,
2163 const struct drm_connector_state *conn_state,
5f88a9c6 2164 const struct intel_shared_dpll *pll)
ba88d153 2165{
f99be1b3
VS		 2166 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2167 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2168 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ba88d153
MN		 2169 enum port port = intel_ddi_get_encoder_port(encoder);
2170 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2171 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2172
ba88d153
MN		 2173 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2174 intel_ddi_clk_select(encoder, pll);
62b69566
ACO		 2175
2176 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2177
2f7460a7
RV		 2178 if (IS_CANNONLAKE(dev_priv))
2179 cnl_ddi_vswing_sequence(encoder, level);
cc3f90f0 2180 else if (IS_GEN9_LP(dev_priv))
ba88d153
MN		 2181 bxt_ddi_vswing_sequence(dev_priv, level, port,
2182 INTEL_OUTPUT_HDMI);
2f7460a7
RV		 2183 else
2184 intel_prepare_hdmi_ddi_buffers(encoder);
2185
2186 if (IS_GEN9_BC(dev_priv))
2187 skl_ddi_set_iboost(encoder, level);
8d8bb85e 2188
f99be1b3
VS		 2189 intel_dig_port->set_infoframes(&encoder->base,
2190 has_infoframe,
2191 crtc_state, conn_state);
ba88d153 2192}
32bdc400 2193
1524e93e 2194static void intel_ddi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2195 const struct intel_crtc_state *pipe_config,
2196 const struct drm_connector_state *conn_state)
ba88d153 2197{
1524e93e 2198 int type = encoder->type;
30cf6db8 2199
ba88d153 2200 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1524e93e 2201 intel_ddi_pre_enable_dp(encoder,
3dc38eea
ACO		 2202 pipe_config->port_clock,
2203 pipe_config->lane_count,
2204 pipe_config->shared_dpll,
2205 intel_crtc_has_type(pipe_config,
ba88d153
MN		 2206 INTEL_OUTPUT_DP_MST));
2207 }
2208 if (type == INTEL_OUTPUT_HDMI) {
1524e93e 2209 intel_ddi_pre_enable_hdmi(encoder,
b47ef0f7 2210 pipe_config->has_infoframe,
ac240288 2211 pipe_config, conn_state,
3dc38eea 2212 pipe_config->shared_dpll);
c19b0669 2213 }
6441ab5f
PZ		 2214}
2215
fd6bbda9 2216static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2217 const struct intel_crtc_state *old_crtc_state,
2218 const struct drm_connector_state *old_conn_state)
6441ab5f
PZ		 2219{
2220 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2221 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6441ab5f 2222 enum port port = intel_ddi_get_encoder_port(intel_encoder);
62b69566 2223 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
82a4d9c0 2224 int type = intel_encoder->type;
2886e93f 2225 uint32_t val;
a836bdf9 2226 bool wait = false;
2886e93f 2227
fd6bbda9
ML		 2228 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2229
7618138d 2230 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
c5f93fcf
VS		 2231 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2232
7618138d
ID		 2233 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2234 }
2235
2886e93f
PZ		 2236 val = I915_READ(DDI_BUF_CTL(port));
2237 if (val & DDI_BUF_CTL_ENABLE) {
2238 val &= ~DDI_BUF_CTL_ENABLE;
2239 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2240 wait = true;
2886e93f 2241 }
6441ab5f 2242
a836bdf9
PZ		 2243 val = I915_READ(DP_TP_CTL(port));
2244 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2245 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2246 I915_WRITE(DP_TP_CTL(port), val);
2247
2248 if (wait)
2249 intel_wait_ddi_buf_idle(dev_priv, port);
2250
c5f93fcf 2251 if (type == INTEL_OUTPUT_HDMI) {
f99be1b3
VS		 2252 dig_port->set_infoframes(encoder, false,
2253 old_crtc_state, old_conn_state);
c5f93fcf
VS		 2254 }
2255
2256 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2258
24f3e092 2259 intel_edp_panel_vdd_on(intel_dp);
4be73780 2260 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2261 }
2262
62b69566
ACO		 2263 if (dig_port)
2264 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2265
555e38d2
RV		 2266 if (IS_CANNONLAKE(dev_priv))
2267 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2268 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2269 else if (IS_GEN9_BC(dev_priv))
efa80add
S		 2270 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2271 DPLL_CTRL2_DDI_CLK_OFF(port)));
66478475 2272 else if (INTEL_GEN(dev_priv) < 9)
efa80add 2273 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 2274
2275 if (type == INTEL_OUTPUT_HDMI) {
2276 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2277
2278 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2279 }
6441ab5f
PZ		 2280}
2281
1524e93e 2282void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2283 const struct intel_crtc_state *old_crtc_state,
2284 const struct drm_connector_state *old_conn_state)
b7076546 2285{
1524e93e 2286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2287 uint32_t val;
2288
2289 /*
2290 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2291 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2292 * step 13 is the correct place for it. Step 18 is where it was
2293 * originally before the BUN.
2294 */
2295 val = I915_READ(FDI_RX_CTL(PIPE_A));
2296 val &= ~FDI_RX_ENABLE;
2297 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2298
1524e93e 2299 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
b7076546
ML		 2300
2301 val = I915_READ(FDI_RX_MISC(PIPE_A));
2302 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2303 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2304 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2305
2306 val = I915_READ(FDI_RX_CTL(PIPE_A));
2307 val &= ~FDI_PCDCLK;
2308 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2309
2310 val = I915_READ(FDI_RX_CTL(PIPE_A));
2311 val &= ~FDI_RX_PLL_ENABLE;
2312 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2313}
2314
fd6bbda9 2315static void intel_enable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2316 const struct intel_crtc_state *pipe_config,
2317 const struct drm_connector_state *conn_state)
72662e10 2318{
6547fef8 2319 struct drm_encoder *encoder = &intel_encoder->base;
66478475 2320 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6547fef8
PZ		 2321 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2322 int type = intel_encoder->type;
72662e10 2323
6547fef8 2324 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2325 struct intel_digital_port *intel_dig_port =
2326 enc_to_dig_port(encoder);
15953637
SS		 2327 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2328 bool scrambling = pipe_config->hdmi_scrambling;
2329
2330 intel_hdmi_handle_sink_scrambling(intel_encoder,
2331 conn_state->connector,
2332 clock_ratio, scrambling);
876a8cdf 2333
6547fef8
PZ		 2334 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2335 * are ignored so nothing special needs to be done besides
2336 * enabling the port.
2337 */
876a8cdf 2338 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2339 intel_dig_port->saved_port_bits |
2340 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2341 } else if (type == INTEL_OUTPUT_EDP) {
2342 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2343
66478475 2344 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3ab9c637
ID		 2345 intel_dp_stop_link_train(intel_dp);
2346
b037d58f 2347 intel_edp_backlight_on(pipe_config, conn_state);
d2419ffc 2348 intel_psr_enable(intel_dp, pipe_config);
85cb48a1 2349 intel_edp_drrs_enable(intel_dp, pipe_config);
6547fef8 2350 }
7b9f35a6 2351
37255d8d 2352 if (pipe_config->has_audio)
bbf35e9d 2353 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
5ab432ef
DV		 2354}
2355
fd6bbda9 2356static void intel_disable_ddi(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 2357 const struct intel_crtc_state *old_crtc_state,
2358 const struct drm_connector_state *old_conn_state)
5ab432ef 2359{
d6c50ff8
PZ		 2360 struct drm_encoder *encoder = &intel_encoder->base;
2361 int type = intel_encoder->type;
2362
37255d8d 2363 if (old_crtc_state->has_audio)
69bfe1a9 2364 intel_audio_codec_disable(intel_encoder);
2831d842 2365
15953637
SS		 2366 if (type == INTEL_OUTPUT_HDMI) {
2367 intel_hdmi_handle_sink_scrambling(intel_encoder,
2368 old_conn_state->connector,
2369 false, false);
2370 }
2371
d6c50ff8
PZ		 2372 if (type == INTEL_OUTPUT_EDP) {
2373 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2374
85cb48a1 2375 intel_edp_drrs_disable(intel_dp, old_crtc_state);
d2419ffc 2376 intel_psr_disable(intel_dp, old_crtc_state);
b037d58f 2377 intel_edp_backlight_off(old_conn_state);
d6c50ff8 2378 }
72662e10 2379}
79f689aa 2380
fd6bbda9 2381static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2382 const struct intel_crtc_state *pipe_config,
2383 const struct drm_connector_state *conn_state)
95a7a2ae 2384{
3dc38eea 2385 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2386
47a6bc61 2387 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2388}
2389
ad64217b 2390void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2391{
ad64217b
ACO		 2392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2393 struct drm_i915_private *dev_priv =
2394 to_i915(intel_dig_port->base.base.dev);
174edf1f 2395 enum port port = intel_dig_port->port;
c19b0669 2396 uint32_t val;
f3e227df 2397 bool wait = false;
c19b0669
PZ		 2398
2399 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2400 val = I915_READ(DDI_BUF_CTL(port));
2401 if (val & DDI_BUF_CTL_ENABLE) {
2402 val &= ~DDI_BUF_CTL_ENABLE;
2403 I915_WRITE(DDI_BUF_CTL(port), val);
2404 wait = true;
2405 }
2406
2407 val = I915_READ(DP_TP_CTL(port));
2408 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2409 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2410 I915_WRITE(DP_TP_CTL(port), val);
2411 POSTING_READ(DP_TP_CTL(port));
2412
2413 if (wait)
2414 intel_wait_ddi_buf_idle(dev_priv, port);
2415 }
2416
0e32b39c 2417 val = DP_TP_CTL_ENABLE |
c19b0669 2418 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2419 if (intel_dp->link_mst)
0e32b39c
DA		 2420 val |= DP_TP_CTL_MODE_MST;
2421 else {
2422 val |= DP_TP_CTL_MODE_SST;
2423 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2424 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2425 }
c19b0669
PZ		 2426 I915_WRITE(DP_TP_CTL(port), val);
2427 POSTING_READ(DP_TP_CTL(port));
2428
2429 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2430 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2431 POSTING_READ(DDI_BUF_CTL(port));
2432
2433 udelay(600);
2434}
00c09d70 2435
9935f7fa
LY		 2436bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2437 struct intel_crtc *intel_crtc)
2438{
2439 u32 temp;
2440
2441 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2442 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2443 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2444 return true;
2445 }
2446 return false;
2447}
2448
6801c18c 2449void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2450 struct intel_crtc_state *pipe_config)
045ac3b5 2451{
fac5e23e 2452 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2454 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 2455 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 2456 u32 temp, flags = 0;
2457
4d1de975
JN		 2458 /* XXX: DSI transcoder paranoia */
2459 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2460 return;
2461
045ac3b5
JB		 2462 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2463 if (temp & TRANS_DDI_PHSYNC)
2464 flags |= DRM_MODE_FLAG_PHSYNC;
2465 else
2466 flags |= DRM_MODE_FLAG_NHSYNC;
2467 if (temp & TRANS_DDI_PVSYNC)
2468 flags |= DRM_MODE_FLAG_PVSYNC;
2469 else
2470 flags |= DRM_MODE_FLAG_NVSYNC;
2471
2d112de7 2472 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2473
2474 switch (temp & TRANS_DDI_BPC_MASK) {
2475 case TRANS_DDI_BPC_6:
2476 pipe_config->pipe_bpp = 18;
2477 break;
2478 case TRANS_DDI_BPC_8:
2479 pipe_config->pipe_bpp = 24;
2480 break;
2481 case TRANS_DDI_BPC_10:
2482 pipe_config->pipe_bpp = 30;
2483 break;
2484 case TRANS_DDI_BPC_12:
2485 pipe_config->pipe_bpp = 36;
2486 break;
2487 default:
2488 break;
2489 }
eb14cb74
VS		 2490
2491 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2492 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2493 pipe_config->has_hdmi_sink = true;
f99be1b3 2494 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 2495
f99be1b3 2496 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2497 pipe_config->has_infoframe = true;
15953637
SS		 2498
2499 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2500 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2501 pipe_config->hdmi_scrambling = true;
2502 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2503 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2504 /* fall through */
eb14cb74 2505 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2506 pipe_config->lane_count = 4;
2507 break;
eb14cb74
VS		 2508 case TRANS_DDI_MODE_SELECT_FDI:
2509 break;
2510 case TRANS_DDI_MODE_SELECT_DP_SST:
2511 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2512 pipe_config->lane_count =
2513 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2514 intel_dp_get_m_n(intel_crtc, pipe_config);
2515 break;
2516 default:
2517 break;
2518 }
10214420 2519
9935f7fa
LY		 2520 pipe_config->has_audio =
2521 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 2522
6aa23e65
JN		 2523 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2524 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2525 /*
2526 * This is a big fat ugly hack.
2527 *
2528 * Some machines in UEFI boot mode provide us a VBT that has 18
2529 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2530 * unknown we fail to light up. Yet the same BIOS boots up with
2531 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2532 * max, not what it tells us to use.
2533 *
2534 * Note: This will still be broken if the eDP panel is not lit
2535 * up by the BIOS, and thus we can't get the mode at module
2536 * load.
2537 */
2538 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2539 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2540 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2541 }
11578553 2542
22606a18 2543 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2544
cc3f90f0 2545 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2546 pipe_config->lane_lat_optim_mask =
2547 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2548}
2549
5bfe2ac0 2550static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2551 struct intel_crtc_state *pipe_config,
2552 struct drm_connector_state *conn_state)
00c09d70 2553{
fac5e23e 2554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2555 int type = encoder->type;
eccb140b 2556 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2557 int ret;
00c09d70 2558
5bfe2ac0 2559 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2560
eccb140b
DV		 2561 if (port == PORT_A)
2562 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2563
00c09d70 2564 if (type == INTEL_OUTPUT_HDMI)
0a478c27 2565 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2566 else
0a478c27 2567 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2568
cc3f90f0 2569 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae
ID		 2570 pipe_config->lane_lat_optim_mask =
2571 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
b284eeda 2572 pipe_config->lane_count);
95a7a2ae
ID		 2573
2574 return ret;
2575
00c09d70
PZ		 2576}
2577
2578static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2579 .reset = intel_dp_encoder_reset,
2580 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2581};
2582
4a28ae58
PZ		 2583static struct intel_connector *
2584intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2585{
2586 struct intel_connector *connector;
2587 enum port port = intel_dig_port->port;
2588
9bdbd0b9 2589 connector = intel_connector_alloc();
4a28ae58
PZ		 2590 if (!connector)
2591 return NULL;
2592
2593 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2594 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2595 kfree(connector);
2596 return NULL;
2597 }
2598
2599 return connector;
2600}
2601
2602static struct intel_connector *
2603intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2604{
2605 struct intel_connector *connector;
2606 enum port port = intel_dig_port->port;
2607
9bdbd0b9 2608 connector = intel_connector_alloc();
4a28ae58
PZ		 2609 if (!connector)
2610 return NULL;
2611
2612 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2613 intel_hdmi_init_connector(intel_dig_port, connector);
2614
2615 return connector;
2616}
2617
c39055b0 2618void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 2619{
2620 struct intel_digital_port *intel_dig_port;
2621 struct intel_encoder *intel_encoder;
2622 struct drm_encoder *encoder;
ff662124 2623 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3
VS		 2624 int max_lanes;
2625
2626 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2627 switch (port) {
2628 case PORT_A:
2629 max_lanes = 4;
2630 break;
2631 case PORT_E:
2632 max_lanes = 0;
2633 break;
2634 default:
2635 max_lanes = 4;
2636 break;
2637 }
2638 } else {
2639 switch (port) {
2640 case PORT_A:
2641 max_lanes = 2;
2642 break;
2643 case PORT_E:
2644 max_lanes = 2;
2645 break;
2646 default:
2647 max_lanes = 4;
2648 break;
2649 }
2650 }
311a2094
PZ		 2651
2652 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2653 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2654 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 2655
2656 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2657 /*
2658 * Lspcon device needs to be driven with DP connector
2659 * with special detection sequence. So make sure DP
2660 * is initialized before lspcon.
2661 */
2662 init_dp = true;
2663 init_lspcon = true;
2664 init_hdmi = false;
2665 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2666 }
2667
311a2094 2668 if (!init_dp && !init_hdmi) {
500ea70d 2669 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2670 port_name(port));
500ea70d 2671 return;
311a2094 2672 }
00c09d70 2673
b14c5679 2674 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2675 if (!intel_dig_port)
2676 return;
2677
00c09d70
PZ		 2678 intel_encoder = &intel_dig_port->base;
2679 encoder = &intel_encoder->base;
2680
c39055b0 2681 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 2682 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2683
5bfe2ac0 2684 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2685 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 2686 if (IS_GEN9_LP(dev_priv))
95a7a2ae 2687 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2688 intel_encoder->pre_enable = intel_ddi_pre_enable;
2689 intel_encoder->disable = intel_disable_ddi;
2690 intel_encoder->post_disable = intel_ddi_post_disable;
2691 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2692 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2693 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 2694 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
00c09d70
PZ		 2695
2696 intel_dig_port->port = port;
bcf53de4
SM		 2697 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2698 (DDI_BUF_PORT_REVERSAL |
2699 DDI_A_4_LANES);
00c09d70 2700
62b69566
ACO		 2701 switch (port) {
2702 case PORT_A:
2703 intel_dig_port->ddi_io_power_domain =
2704 POWER_DOMAIN_PORT_DDI_A_IO;
2705 break;
2706 case PORT_B:
2707 intel_dig_port->ddi_io_power_domain =
2708 POWER_DOMAIN_PORT_DDI_B_IO;
2709 break;
2710 case PORT_C:
2711 intel_dig_port->ddi_io_power_domain =
2712 POWER_DOMAIN_PORT_DDI_C_IO;
2713 break;
2714 case PORT_D:
2715 intel_dig_port->ddi_io_power_domain =
2716 POWER_DOMAIN_PORT_DDI_D_IO;
2717 break;
2718 case PORT_E:
2719 intel_dig_port->ddi_io_power_domain =
2720 POWER_DOMAIN_PORT_DDI_E_IO;
2721 break;
2722 default:
2723 MISSING_CASE(port);
2724 }
2725
6c566dc9
MR		 2726 /*
2727 * Bspec says that DDI_A_4_LANES is the only supported configuration
2728 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2729 * wasn't lit up at boot. Force this bit on in our internal
2730 * configuration so that we use the proper lane count for our
2731 * calculations.
2732 */
cc3f90f0 2733 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
6c566dc9
MR		 2734 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2735 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2736 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2737 max_lanes = 4;
6c566dc9
MR		 2738 }
2739 }
2740
ed8d60f4
MR		 2741 intel_dig_port->max_lanes = max_lanes;
2742
00c09d70 2743 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
79f255a0 2744 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2745 intel_encoder->port = port;
f68d697e 2746 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2747 intel_encoder->cloneable = 0;
00c09d70 2748
385e4de0
VS		 2749 intel_infoframe_init(intel_dig_port);
2750
f68d697e
CW		 2751 if (init_dp) {
2752 if (!intel_ddi_init_dp_connector(intel_dig_port))
2753 goto err;
13cf5504 2754
f68d697e 2755 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 2756 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2757 }
21a8e6a4 2758
311a2094
PZ		 2759 /* In theory we don't need the encoder->type check, but leave it just in
2760 * case we have some really bad VBTs... */
f68d697e
CW		 2761 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2762 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2763 goto err;
21a8e6a4 2764 }
f68d697e 2765
ff662124
SS		 2766 if (init_lspcon) {
2767 if (lspcon_init(intel_dig_port))
2768 /* TODO: handle hdmi info frame part */
2769 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2770 port_name(port));
2771 else
2772 /*
2773 * LSPCON init faied, but DP init was success, so
2774 * lets try to drive as DP++ port.
2775 */
2776 DRM_ERROR("LSPCON init failed on port %c\n",
2777 port_name(port));
2778 }
2779
f68d697e
CW		 2780 return;
2781
2782err:
2783 drm_encoder_cleanup(encoder);
2784 kfree(intel_dig_port);
00c09d70 2785}
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