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drm/i915: Use a cached mapping for the physical HWS
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
45244b87
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
31
10122051
JN		 32struct ddi_buf_trans {
33 u32 trans1; /* balance leg enable, de-emph level */
34 u32 trans2; /* vref sel, vswing */
f8896f5d 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 36};
37
97eeb872
VS		 38static const u8 index_to_dp_signal_levels[] = {
39 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
40 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
41 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
42 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
43 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
44 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
45 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
46 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
47 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
48 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
49};
50
45244b87
ED		 51/* HDMI/DVI modes ignore everything but the last 2 items. So we share
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
54 */
10122051 55static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 56 { 0x00FFFFFF, 0x0006000E, 0x0 },
57 { 0x00D75FFF, 0x0005000A, 0x0 },
58 { 0x00C30FFF, 0x00040006, 0x0 },
59 { 0x80AAAFFF, 0x000B0000, 0x0 },
60 { 0x00FFFFFF, 0x0005000A, 0x0 },
61 { 0x00D75FFF, 0x000C0004, 0x0 },
62 { 0x80C30FFF, 0x000B0000, 0x0 },
63 { 0x00FFFFFF, 0x00040006, 0x0 },
64 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 65};
66
10122051 67static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 68 { 0x00FFFFFF, 0x0007000E, 0x0 },
69 { 0x00D75FFF, 0x000F000A, 0x0 },
70 { 0x00C30FFF, 0x00060006, 0x0 },
71 { 0x00AAAFFF, 0x001E0000, 0x0 },
72 { 0x00FFFFFF, 0x000F000A, 0x0 },
73 { 0x00D75FFF, 0x00160004, 0x0 },
74 { 0x00C30FFF, 0x001E0000, 0x0 },
75 { 0x00FFFFFF, 0x00060006, 0x0 },
76 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 77};
78
10122051
JN		 79static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
80 /* Idx NT mV d T mV d db */
f8896f5d
DW		 81 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
82 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
83 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
84 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
85 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
86 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
87 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
88 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
89 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
90 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
91 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
92 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 93};
94
10122051 95static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 96 { 0x00FFFFFF, 0x00000012, 0x0 },
97 { 0x00EBAFFF, 0x00020011, 0x0 },
98 { 0x00C71FFF, 0x0006000F, 0x0 },
99 { 0x00AAAFFF, 0x000E000A, 0x0 },
100 { 0x00FFFFFF, 0x00020011, 0x0 },
101 { 0x00DB6FFF, 0x0005000F, 0x0 },
102 { 0x00BEEFFF, 0x000A000C, 0x0 },
103 { 0x00FFFFFF, 0x0005000F, 0x0 },
104 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 105};
106
10122051 107static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 108 { 0x00FFFFFF, 0x0007000E, 0x0 },
109 { 0x00D75FFF, 0x000E000A, 0x0 },
110 { 0x00BEFFFF, 0x00140006, 0x0 },
111 { 0x80B2CFFF, 0x001B0002, 0x0 },
112 { 0x00FFFFFF, 0x000E000A, 0x0 },
113 { 0x00DB6FFF, 0x00160005, 0x0 },
114 { 0x80C71FFF, 0x001A0002, 0x0 },
115 { 0x00F7DFFF, 0x00180004, 0x0 },
116 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 117};
118
10122051 119static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 120 { 0x00FFFFFF, 0x0001000E, 0x0 },
121 { 0x00D75FFF, 0x0004000A, 0x0 },
122 { 0x00C30FFF, 0x00070006, 0x0 },
123 { 0x00AAAFFF, 0x000C0000, 0x0 },
124 { 0x00FFFFFF, 0x0004000A, 0x0 },
125 { 0x00D75FFF, 0x00090004, 0x0 },
126 { 0x00C30FFF, 0x000C0000, 0x0 },
127 { 0x00FFFFFF, 0x00070006, 0x0 },
128 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 129};
130
10122051
JN		 131static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
132 /* Idx NT mV d T mV df db */
f8896f5d
DW		 133 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
134 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
135 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
136 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
137 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
138 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
139 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
140 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
141 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
142 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 143};
144
5f8b2531 145/* Skylake H and S */
7f88e3af 146static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
d7097cff 150 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
d7097cff 153 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 154 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 155 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 156};
157
f8896f5d
DW		 158/* Skylake U */
159static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 160 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 161 { 0x00005012, 0x00000088, 0x0 },
5ac90567 162 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 163 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 164 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 165 { 0x80005012, 0x000000C0, 0x1 },
166 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 167 { 0x00002016, 0x00000088, 0x0 },
d7097cff 168 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 169};
170
5f8b2531
RV		 171/* Skylake Y */
172static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 173 { 0x00000018, 0x000000A2, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
5ac90567 175 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 176 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 177 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 180 { 0x00000018, 0x00000088, 0x0 },
d7097cff 181 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 182};
183
0fdd4918
RV		 184/* Kabylake H and S */
185static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
186 { 0x00002016, 0x000000A0, 0x0 },
187 { 0x00005012, 0x0000009B, 0x0 },
188 { 0x00007011, 0x00000088, 0x0 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x00002016, 0x0000009B, 0x0 },
191 { 0x00005012, 0x00000088, 0x0 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000097, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
195};
196
197/* Kabylake U */
198static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
199 { 0x0000201B, 0x000000A1, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x0000201B, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00002016, 0x0000004F, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
208};
209
210/* Kabylake Y */
211static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
212 { 0x00001017, 0x000000A1, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000CD, 0x3 },
215 { 0x8000800F, 0x000000C0, 0x3 },
216 { 0x00001017, 0x0000009D, 0x0 },
217 { 0x80005012, 0x000000C0, 0x3 },
218 { 0x80007011, 0x000000C0, 0x3 },
219 { 0x00001017, 0x0000004C, 0x0 },
220 { 0x80005012, 0x000000C0, 0x3 },
221};
222
f8896f5d 223/*
0fdd4918 224 * Skylake/Kabylake H and S
f8896f5d
DW		 225 * eDP 1.4 low vswing translation parameters
226 */
7ad14a29 227static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 228 { 0x00000018, 0x000000A8, 0x0 },
229 { 0x00004013, 0x000000A9, 0x0 },
230 { 0x00007011, 0x000000A2, 0x0 },
231 { 0x00009010, 0x0000009C, 0x0 },
232 { 0x00000018, 0x000000A9, 0x0 },
233 { 0x00006013, 0x000000A2, 0x0 },
234 { 0x00007011, 0x000000A6, 0x0 },
235 { 0x00000018, 0x000000AB, 0x0 },
236 { 0x00007013, 0x0000009F, 0x0 },
237 { 0x00000018, 0x000000DF, 0x0 },
238};
239
240/*
0fdd4918 241 * Skylake/Kabylake U
f8896f5d
DW		 242 * eDP 1.4 low vswing translation parameters
243 */
244static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
245 { 0x00000018, 0x000000A8, 0x0 },
246 { 0x00004013, 0x000000A9, 0x0 },
247 { 0x00007011, 0x000000A2, 0x0 },
248 { 0x00009010, 0x0000009C, 0x0 },
249 { 0x00000018, 0x000000A9, 0x0 },
250 { 0x00006013, 0x000000A2, 0x0 },
251 { 0x00007011, 0x000000A6, 0x0 },
252 { 0x00002016, 0x000000AB, 0x0 },
253 { 0x00005013, 0x0000009F, 0x0 },
254 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 255};
256
f8896f5d 257/*
0fdd4918 258 * Skylake/Kabylake Y
f8896f5d
DW		 259 * eDP 1.4 low vswing translation parameters
260 */
5f8b2531 261static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 262 { 0x00000018, 0x000000A8, 0x0 },
263 { 0x00004013, 0x000000AB, 0x0 },
264 { 0x00007011, 0x000000A4, 0x0 },
265 { 0x00009010, 0x000000DF, 0x0 },
266 { 0x00000018, 0x000000AA, 0x0 },
267 { 0x00006013, 0x000000A4, 0x0 },
268 { 0x00007011, 0x0000009D, 0x0 },
269 { 0x00000018, 0x000000A0, 0x0 },
270 { 0x00006012, 0x000000DF, 0x0 },
271 { 0x00000018, 0x0000008A, 0x0 },
272};
7ad14a29 273
0fdd4918 274/* Skylake/Kabylake U, H and S */
7f88e3af 275static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 276 { 0x00000018, 0x000000AC, 0x0 },
277 { 0x00005012, 0x0000009D, 0x0 },
278 { 0x00007011, 0x00000088, 0x0 },
279 { 0x00000018, 0x000000A1, 0x0 },
280 { 0x00000018, 0x00000098, 0x0 },
281 { 0x00004013, 0x00000088, 0x0 },
2e78416e 282 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 283 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 284 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
285 { 0x80003015, 0x000000C0, 0x1 },
286 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 287};
288
0fdd4918 289/* Skylake/Kabylake Y */
5f8b2531 290static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 293 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 294 { 0x00000018, 0x000000A4, 0x0 },
295 { 0x00000018, 0x0000009D, 0x0 },
296 { 0x00004013, 0x00000080, 0x0 },
2e78416e 297 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 298 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 299 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
300 { 0x80003015, 0x000000C0, 0x3 },
301 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 302};
303
96fb9f9b 304struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 305 u8 margin; /* swing value */
306 u8 scale; /* scale value */
307 u8 enable; /* scale enable */
308 u8 deemphasis;
96fb9f9b
VK		 309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
043eaf36
VS		 313 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
043eaf36
VS		 327 { 26, 0, 0, 128, }, /* 0: 200 0 */
328 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, }, /* 2: 200 4 */
330 { 54, 0, 0, 69, }, /* 3: 200 6 */
331 { 32, 0, 0, 128, }, /* 4: 250 0 */
332 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, }, /* 6: 250 4 */
334 { 43, 0, 0, 128, }, /* 7: 300 0 */
335 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
043eaf36
VS		 344 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 354};
355
83fb7ab4 356struct cnl_ddi_buf_trans {
fb5f4e96
VS		 357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
83fb7ab4
RV		 362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
19b904f8
MN		 496struct icl_combo_phy_ddi_buf_trans {
497 u32 dw2_swing_select;
498 u32 dw2_swing_scalar;
499 u32 dw4_scaling;
500};
501
502/* Voltage Swing Programming for VccIO 0.85V for DP */
503static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
504 /* Voltage mV db */
505 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
506 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
507 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
508 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
509 { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
510 { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
511 { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
512 { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
513 { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
514 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
515};
516
517/* FIXME - After table is updated in Bspec */
518/* Voltage Swing Programming for VccIO 0.85V for eDP */
519static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
520 /* Voltage mV db */
521 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
522 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
523 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
524 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
525 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
526 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
527 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
528 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
529 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
530 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
531};
532
533/* Voltage Swing Programming for VccIO 0.95V for DP */
534static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
535 /* Voltage mV db */
536 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
537 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
538 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
539 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
540 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
541 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
542 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
543 { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
544 { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
545 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
546};
547
548/* FIXME - After table is updated in Bspec */
549/* Voltage Swing Programming for VccIO 0.95V for eDP */
550static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
551 /* Voltage mV db */
552 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
553 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
554 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
555 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
556 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
557 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
558 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
559 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
560 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
561 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
562};
563
564/* Voltage Swing Programming for VccIO 1.05V for DP */
565static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
566 /* Voltage mV db */
567 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
568 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
569 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
570 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
571 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
572 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
573 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
574 { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
575 { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
576 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
577};
578
579/* FIXME - After table is updated in Bspec */
580/* Voltage Swing Programming for VccIO 1.05V for eDP */
581static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
582 /* Voltage mV db */
583 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
584 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
585 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
586 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
587 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
588 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
589 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
590 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
591 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
592 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
593};
594
cd96bea7
MN		 595struct icl_mg_phy_ddi_buf_trans {
596 u32 cri_txdeemph_override_5_0;
597 u32 cri_txdeemph_override_11_6;
598 u32 cri_txdeemph_override_17_12;
599};
600
601static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
602 /* Voltage swing pre-emphasis */
603 { 0x0, 0x1B, 0x00 }, /* 0 0 */
604 { 0x0, 0x23, 0x08 }, /* 0 1 */
605 { 0x0, 0x2D, 0x12 }, /* 0 2 */
606 { 0x0, 0x00, 0x00 }, /* 0 3 */
607 { 0x0, 0x23, 0x00 }, /* 1 0 */
608 { 0x0, 0x2B, 0x09 }, /* 1 1 */
609 { 0x0, 0x2E, 0x11 }, /* 1 2 */
610 { 0x0, 0x2F, 0x00 }, /* 2 0 */
611 { 0x0, 0x33, 0x0C }, /* 2 1 */
612 { 0x0, 0x00, 0x00 }, /* 3 0 */
613};
614
a930acd9
VS		 615static const struct ddi_buf_trans *
616bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
617{
618 if (dev_priv->vbt.edp.low_vswing) {
619 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
620 return bdw_ddi_translations_edp;
621 } else {
622 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
623 return bdw_ddi_translations_dp;
624 }
625}
626
acee2998 627static const struct ddi_buf_trans *
78ab0bae 628skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 629{
0fdd4918 630 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 631 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 632 return skl_y_ddi_translations_dp;
0fdd4918 633 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 634 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 635 return skl_u_ddi_translations_dp;
f8896f5d 636 } else {
f8896f5d 637 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 638 return skl_ddi_translations_dp;
f8896f5d 639 }
f8896f5d
DW		 640}
641
0fdd4918
RV		 642static const struct ddi_buf_trans *
643kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
644{
645 if (IS_KBL_ULX(dev_priv)) {
646 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
647 return kbl_y_ddi_translations_dp;
da411a48 648 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 649 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
650 return kbl_u_ddi_translations_dp;
651 } else {
652 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
653 return kbl_ddi_translations_dp;
654 }
655}
656
acee2998 657static const struct ddi_buf_trans *
78ab0bae 658skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 659{
06411f08 660 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 661 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 662 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 663 return skl_y_ddi_translations_edp;
da411a48
RV		 664 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
665 IS_CFL_ULT(dev_priv)) {
f8896f5d 666 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 667 return skl_u_ddi_translations_edp;
f8896f5d 668 } else {
f8896f5d 669 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 670 return skl_ddi_translations_edp;
f8896f5d
DW		 671 }
672 }
cd1101cb 673
da411a48 674 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 675 return kbl_get_buf_trans_dp(dev_priv, n_entries);
676 else
677 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 678}
679
680static const struct ddi_buf_trans *
78ab0bae 681skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 682{
78ab0bae 683 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 684 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 685 return skl_y_ddi_translations_hdmi;
f8896f5d 686 } else {
f8896f5d 687 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 688 return skl_ddi_translations_hdmi;
f8896f5d 689 }
f8896f5d
DW		 690}
691
edba48fd
VS		 692static int skl_buf_trans_num_entries(enum port port, int n_entries)
693{
694 /* Only DDIA and DDIE can select the 10th register with DP */
695 if (port == PORT_A || port == PORT_E)
696 return min(n_entries, 10);
697 else
698 return min(n_entries, 9);
699}
700
d8fe2c7f
VS		 701static const struct ddi_buf_trans *
702intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 703 enum port port, int *n_entries)
d8fe2c7f
VS		 704{
705 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 706 const struct ddi_buf_trans *ddi_translations =
707 kbl_get_buf_trans_dp(dev_priv, n_entries);
708 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
709 return ddi_translations;
d8fe2c7f 710 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 711 const struct ddi_buf_trans *ddi_translations =
712 skl_get_buf_trans_dp(dev_priv, n_entries);
713 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
714 return ddi_translations;
d8fe2c7f
VS		 715 } else if (IS_BROADWELL(dev_priv)) {
716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
717 return bdw_ddi_translations_dp;
718 } else if (IS_HASWELL(dev_priv)) {
719 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
720 return hsw_ddi_translations_dp;
721 }
722
723 *n_entries = 0;
724 return NULL;
725}
726
727static const struct ddi_buf_trans *
728intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 729 enum port port, int *n_entries)
d8fe2c7f
VS		 730{
731 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 732 const struct ddi_buf_trans *ddi_translations =
733 skl_get_buf_trans_edp(dev_priv, n_entries);
734 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
735 return ddi_translations;
d8fe2c7f
VS		 736 } else if (IS_BROADWELL(dev_priv)) {
737 return bdw_get_buf_trans_edp(dev_priv, n_entries);
738 } else if (IS_HASWELL(dev_priv)) {
739 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
740 return hsw_ddi_translations_dp;
741 }
742
743 *n_entries = 0;
744 return NULL;
745}
746
747static const struct ddi_buf_trans *
748intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
749 int *n_entries)
750{
751 if (IS_BROADWELL(dev_priv)) {
752 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
753 return bdw_ddi_translations_fdi;
754 } else if (IS_HASWELL(dev_priv)) {
755 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
756 return hsw_ddi_translations_fdi;
757 }
758
759 *n_entries = 0;
760 return NULL;
761}
762
975786ee
VS		 763static const struct ddi_buf_trans *
764intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
765 int *n_entries)
766{
767 if (IS_GEN9_BC(dev_priv)) {
768 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
769 } else if (IS_BROADWELL(dev_priv)) {
770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
771 return bdw_ddi_translations_hdmi;
772 } else if (IS_HASWELL(dev_priv)) {
773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
774 return hsw_ddi_translations_hdmi;
775 }
776
777 *n_entries = 0;
778 return NULL;
779}
780
7d4f37b5
VS		 781static const struct bxt_ddi_buf_trans *
782bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
783{
784 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
785 return bxt_ddi_translations_dp;
786}
787
788static const struct bxt_ddi_buf_trans *
789bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
790{
791 if (dev_priv->vbt.edp.low_vswing) {
792 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
793 return bxt_ddi_translations_edp;
794 }
795
796 return bxt_get_buf_trans_dp(dev_priv, n_entries);
797}
798
799static const struct bxt_ddi_buf_trans *
800bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
801{
802 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
803 return bxt_ddi_translations_hdmi;
804}
805
cf3e0fb4
RV		 806static const struct cnl_ddi_buf_trans *
807cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
808{
809 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
810
811 if (voltage == VOLTAGE_INFO_0_85V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
813 return cnl_ddi_translations_hdmi_0_85V;
814 } else if (voltage == VOLTAGE_INFO_0_95V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
816 return cnl_ddi_translations_hdmi_0_95V;
817 } else if (voltage == VOLTAGE_INFO_1_05V) {
818 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
819 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 820 } else {
821 *n_entries = 1; /* shut up gcc */
cf3e0fb4 822 MISSING_CASE(voltage);
83482ca3 823 }
cf3e0fb4
RV		 824 return NULL;
825}
826
827static const struct cnl_ddi_buf_trans *
828cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
829{
830 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
831
832 if (voltage == VOLTAGE_INFO_0_85V) {
833 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
834 return cnl_ddi_translations_dp_0_85V;
835 } else if (voltage == VOLTAGE_INFO_0_95V) {
836 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
837 return cnl_ddi_translations_dp_0_95V;
838 } else if (voltage == VOLTAGE_INFO_1_05V) {
839 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
840 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 841 } else {
842 *n_entries = 1; /* shut up gcc */
cf3e0fb4 843 MISSING_CASE(voltage);
83482ca3 844 }
cf3e0fb4
RV		 845 return NULL;
846}
847
848static const struct cnl_ddi_buf_trans *
849cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
850{
851 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
852
853 if (dev_priv->vbt.edp.low_vswing) {
854 if (voltage == VOLTAGE_INFO_0_85V) {
855 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
856 return cnl_ddi_translations_edp_0_85V;
857 } else if (voltage == VOLTAGE_INFO_0_95V) {
858 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
859 return cnl_ddi_translations_edp_0_95V;
860 } else if (voltage == VOLTAGE_INFO_1_05V) {
861 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
862 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 863 } else {
864 *n_entries = 1; /* shut up gcc */
cf3e0fb4 865 MISSING_CASE(voltage);
83482ca3 866 }
cf3e0fb4
RV		 867 return NULL;
868 } else {
869 return cnl_get_buf_trans_dp(dev_priv, n_entries);
870 }
871}
872
fb5c8e9d
MN		 873static const struct icl_combo_phy_ddi_buf_trans *
874icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
875 int type, int *n_entries)
876{
877 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
878
879 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
880 switch (voltage) {
881 case VOLTAGE_INFO_0_85V:
882 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
883 return icl_combo_phy_ddi_translations_edp_0_85V;
884 case VOLTAGE_INFO_0_95V:
885 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
886 return icl_combo_phy_ddi_translations_edp_0_95V;
887 case VOLTAGE_INFO_1_05V:
888 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
889 return icl_combo_phy_ddi_translations_edp_1_05V;
890 default:
891 MISSING_CASE(voltage);
892 return NULL;
893 }
894 } else {
895 switch (voltage) {
896 case VOLTAGE_INFO_0_85V:
897 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
898 return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
899 case VOLTAGE_INFO_0_95V:
900 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
901 return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
902 case VOLTAGE_INFO_1_05V:
903 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
904 return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
905 default:
906 MISSING_CASE(voltage);
907 return NULL;
908 }
909 }
910}
911
8d8bb85e
VS		 912static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
913{
d02ace87 914 int n_entries, level, default_entry;
8d8bb85e 915
d02ace87 916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 917
dccc7228
MN		 918 if (IS_ICELAKE(dev_priv)) {
919 if (port == PORT_A || port == PORT_B)
920 icl_get_combo_buf_trans(dev_priv, port,
921 INTEL_OUTPUT_HDMI, &n_entries);
922 else
923 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
924 default_entry = n_entries - 1;
925 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 926 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
927 default_entry = n_entries - 1;
043eaf36 928 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 929 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
930 default_entry = n_entries - 1;
bf503556 931 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 932 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
933 default_entry = 8;
8d8bb85e 934 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 935 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
936 default_entry = 7;
8d8bb85e 937 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 938 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
939 default_entry = 6;
8d8bb85e
VS		 940 } else {
941 WARN(1, "ddi translation table missing\n");
975786ee 942 return 0;
8d8bb85e
VS		 943 }
944
945 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 946 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
947 level = default_entry;
8d8bb85e 948
d02ace87 949 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 950 return 0;
d02ace87
VS		 951 if (WARN_ON_ONCE(level >= n_entries))
952 level = n_entries - 1;
21b39d2a 953
d02ace87 954 return level;
8d8bb85e
VS		 955}
956
e58623cb
AR		 957/*
958 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 959 * values in advance. This function programs the correct values for
960 * DP/eDP/FDI use cases.
45244b87 961 */
3a6d84e6
VS		 962static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
963 const struct intel_crtc_state *crtc_state)
45244b87 964{
6a7e4f99 965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 966 u32 iboost_bit = 0;
7d1c42e6 967 int i, n_entries;
0fce04c8 968 enum port port = encoder->port;
10122051 969 const struct ddi_buf_trans *ddi_translations;
e58623cb 970
3a6d84e6
VS		 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
973 &n_entries);
974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 976 &n_entries);
3a6d84e6 977 else
edba48fd 978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 979 &n_entries);
e58623cb 980
edba48fd
VS		 981 /* If we're boosting the current, set bit 31 of trans1 */
982 if (IS_GEN9_BC(dev_priv) &&
983 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 985
7d1c42e6 986 for (i = 0; i < n_entries; i++) {
9712e688
VS		 987 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
988 ddi_translations[i].trans1 | iboost_bit);
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
990 ddi_translations[i].trans2);
45244b87 991 }
32bdc400
VS		 992}
993
994/*
995 * Starting with Haswell, DDI port buffers must be programmed with correct
996 * values in advance. This function programs the correct values for
997 * HDMI/DVI use cases.
998 */
7ea79333 999static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 1000 int level)
32bdc400
VS		 1001{
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003 u32 iboost_bit = 0;
d02ace87 1004 int n_entries;
0fce04c8 1005 enum port port = encoder->port;
d02ace87 1006 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 1007
d02ace87 1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 1009
d02ace87 1010 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 1011 return;
d02ace87
VS		 1012 if (WARN_ON_ONCE(level >= n_entries))
1013 level = n_entries - 1;
21b39d2a 1014
975786ee
VS		 1015 /* If we're boosting the current, set bit 31 of trans1 */
1016 if (IS_GEN9_BC(dev_priv) &&
1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 1019
6acab15a 1020 /* Entry 9 is for HDMI: */
ed9c77d2 1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 1022 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 1024 ddi_translations[level].trans2);
45244b87
ED		 1025}
1026
248138b5
PZ		 1027static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028 enum port port)
1029{
f0f59a00 1030 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 1031 int i;
1032
3449ca85 1033 for (i = 0; i < 16; i++) {
248138b5
PZ		 1034 udelay(1);
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036 return;
1037 }
1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039}
c82e4d26 1040
5f88a9c6 1041static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 1042{
0823eb9c 1043 switch (pll->info->id) {
c856052a
ACO		 1044 case DPLL_ID_WRPLL1:
1045 return PORT_CLK_SEL_WRPLL1;
1046 case DPLL_ID_WRPLL2:
1047 return PORT_CLK_SEL_WRPLL2;
1048 case DPLL_ID_SPLL:
1049 return PORT_CLK_SEL_SPLL;
1050 case DPLL_ID_LCPLL_810:
1051 return PORT_CLK_SEL_LCPLL_810;
1052 case DPLL_ID_LCPLL_1350:
1053 return PORT_CLK_SEL_LCPLL_1350;
1054 case DPLL_ID_LCPLL_2700:
1055 return PORT_CLK_SEL_LCPLL_2700;
1056 default:
0823eb9c 1057 MISSING_CASE(pll->info->id);
c856052a
ACO		 1058 return PORT_CLK_SEL_NONE;
1059 }
1060}
1061
c27e917e
PZ		 1062static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063 const struct intel_shared_dpll *pll)
1064{
1fa11ee2
PZ		 1065 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066 int clock = crtc->config->port_clock;
c27e917e
PZ		 1067 const enum intel_dpll_id id = pll->info->id;
1068
1069 switch (id) {
1070 default:
1071 MISSING_CASE(id);
f0d759f0 1072 /* fall through */
c27e917e
PZ		 1073 case DPLL_ID_ICL_DPLL0:
1074 case DPLL_ID_ICL_DPLL1:
1075 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1076 case DPLL_ID_ICL_TBTPLL:
1077 switch (clock) {
1078 case 162000:
1079 return DDI_CLK_SEL_TBT_162;
1080 case 270000:
1081 return DDI_CLK_SEL_TBT_270;
1082 case 540000:
1083 return DDI_CLK_SEL_TBT_540;
1084 case 810000:
1085 return DDI_CLK_SEL_TBT_810;
1086 default:
1087 MISSING_CASE(clock);
1088 break;
1089 }
c27e917e
PZ		 1090 case DPLL_ID_ICL_MGPLL1:
1091 case DPLL_ID_ICL_MGPLL2:
1092 case DPLL_ID_ICL_MGPLL3:
1093 case DPLL_ID_ICL_MGPLL4:
1094 return DDI_CLK_SEL_MG;
1095 }
1096}
1097
c82e4d26
ED		 1098/* Starting with Haswell, different DDI ports can work in FDI mode for
1099 * connection to the PCH-located connectors. For this, it is necessary to train
1100 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101 *
1102 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104 * DDI A (which is used for eDP)
1105 */
1106
dc4a1094
ACO		 1107void hsw_fdi_link_train(struct intel_crtc *crtc,
1108 const struct intel_crtc_state *crtc_state)
c82e4d26 1109{
4cbe4b2b 1110 struct drm_device *dev = crtc->base.dev;
fac5e23e 1111 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1112 struct intel_encoder *encoder;
c856052a 1113 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1114
4cbe4b2b 1115 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1116 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1118 }
1119
04945641
PZ		 1120 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121 * mode set "sequence for CRT port" document:
1122 * - TP1 to TP2 time with the default value
1123 * - FDI delay to 90h
8693a824
DL		 1124 *
1125 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1126 */
eede3b53 1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1128 FDI_RX_PWRDN_LANE0_VAL(2) |
1129 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131 /* Enable the PCH Receiver FDI PLL */
3e68320e 1132 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1133 FDI_RX_PLL_ENABLE |
dc4a1094 1134 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1137 udelay(220);
1138
1139 /* Switch from Rawclk to PCDclk */
1140 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1142
1143 /* Configure Port Clock Select */
dc4a1094 1144 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1145 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1147
1148 /* Start the training iterating through available voltages and emphasis,
1149 * testing each value twice. */
10122051 1150 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1151 /* Configure DP_TP_CTL with auto-training */
1152 I915_WRITE(DP_TP_CTL(PORT_E),
1153 DP_TP_CTL_FDI_AUTOTRAIN |
1154 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155 DP_TP_CTL_LINK_TRAIN_PAT1 |
1156 DP_TP_CTL_ENABLE);
1157
876a8cdf
DL		 1158 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159 * DDI E does not support port reversal, the functionality is
1160 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161 * port reversal bit */
c82e4d26 1162 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1163 DDI_BUF_CTL_ENABLE |
dc4a1094 1164 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1165 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1167
1168 udelay(600);
1169
04945641 1170 /* Program PCH FDI Receiver TU */
eede3b53 1171 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1172
1173 /* Enable PCH FDI Receiver with auto-training */
1174 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1175 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1177
1178 /* Wait for FDI receiver lane calibration */
1179 udelay(30);
1180
1181 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1186
1187 /* Wait for FDI auto training time */
1188 udelay(5);
c82e4d26
ED		 1189
1190 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1192 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1193 break;
1194 }
c82e4d26 1195
a308ccb3
VS		 1196 /*
1197 * Leave things enabled even if we failed to train FDI.
1198 * Results in less fireworks from the state checker.
1199 */
1200 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201 DRM_ERROR("FDI link training failed!\n");
1202 break;
c82e4d26 1203 }
04945641 1204
5b421c57
VS		 1205 rx_ctl_val &= ~FDI_RX_ENABLE;
1206 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
248138b5
PZ		 1209 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210 temp &= ~DDI_BUF_CTL_ENABLE;
1211 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
04945641 1214 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1215 temp = I915_READ(DP_TP_CTL(PORT_E));
1216 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1222
04945641 1223 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1224 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1225 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1227 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1229 }
1230
a308ccb3
VS		 1231 /* Enable normal pixel sending for FDI */
1232 I915_WRITE(DP_TP_CTL(PORT_E),
1233 DP_TP_CTL_FDI_AUTOTRAIN |
1234 DP_TP_CTL_LINK_TRAIN_NORMAL |
1235 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236 DP_TP_CTL_ENABLE);
c82e4d26 1237}
0e72a5b5 1238
d7c530b2 1239static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1240{
1241 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242 struct intel_digital_port *intel_dig_port =
1243 enc_to_dig_port(&encoder->base);
1244
1245 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1246 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1247 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1248}
1249
8d9ddbcb 1250static struct intel_encoder *
e9ce1a62 1251intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1252{
e9ce1a62 1253 struct drm_device *dev = crtc->base.dev;
1524e93e 1254 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1255 int num_encoders = 0;
1256
1524e93e
SS		 1257 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258 ret = encoder;
8d9ddbcb
PZ		 1259 num_encoders++;
1260 }
1261
1262 if (num_encoders != 1)
84f44ce7 1263 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1264 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1265
1266 BUG_ON(ret == NULL);
1267 return ret;
1268}
1269
1c0b85c5 1270#define LC_FREQ 2700
1c0b85c5 1271
f0f59a00
VS		 1272static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273 i915_reg_t reg)
11578553
JB		 1274{
1275 int refclk = LC_FREQ;
1276 int n, p, r;
1277 u32 wrpll;
1278
1279 wrpll = I915_READ(reg);
114fe488
DV		 1280 switch (wrpll & WRPLL_PLL_REF_MASK) {
1281 case WRPLL_PLL_SSC:
1282 case WRPLL_PLL_NON_SSC:
11578553
JB		 1283 /*
1284 * We could calculate spread here, but our checking
1285 * code only cares about 5% accuracy, and spread is a max of
1286 * 0.5% downspread.
1287 */
1288 refclk = 135;
1289 break;
114fe488 1290 case WRPLL_PLL_LCPLL:
11578553
JB		 1291 refclk = LC_FREQ;
1292 break;
1293 default:
1294 WARN(1, "bad wrpll refclk\n");
1295 return 0;
1296 }
1297
1298 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
20f0ec16
JB		 1302 /* Convert to KHz, p & r have a fixed point portion */
1303 return (refclk * n * 100) / (p * r);
11578553
JB		 1304}
1305
540e732c 1306static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1307 enum intel_dpll_id pll_id)
540e732c 1308{
f0f59a00 1309 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1310 uint32_t cfgcr1_val, cfgcr2_val;
1311 uint32_t p0, p1, p2, dco_freq;
1312
2952cd6f
RV		 1313 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314 cfgcr2_reg = DPLL_CFGCR2(pll_id);
540e732c
S		 1315
1316 cfgcr1_val = I915_READ(cfgcr1_reg);
1317 cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1323 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324 else
1325 p1 = 1;
1326
1327
1328 switch (p0) {
1329 case DPLL_CFGCR2_PDIV_1:
1330 p0 = 1;
1331 break;
1332 case DPLL_CFGCR2_PDIV_2:
1333 p0 = 2;
1334 break;
1335 case DPLL_CFGCR2_PDIV_3:
1336 p0 = 3;
1337 break;
1338 case DPLL_CFGCR2_PDIV_7:
1339 p0 = 7;
1340 break;
1341 }
1342
1343 switch (p2) {
1344 case DPLL_CFGCR2_KDIV_5:
1345 p2 = 5;
1346 break;
1347 case DPLL_CFGCR2_KDIV_2:
1348 p2 = 2;
1349 break;
1350 case DPLL_CFGCR2_KDIV_3:
1351 p2 = 3;
1352 break;
1353 case DPLL_CFGCR2_KDIV_1:
1354 p2 = 1;
1355 break;
1356 }
1357
1358 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361 1000) / 0x8000;
1362
1363 return dco_freq / (p0 * p1 * p2 * 5);
1364}
1365
a9701a89 1366static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1367 enum intel_dpll_id pll_id)
a9701a89
RV		 1368{
1369 uint32_t cfgcr0, cfgcr1;
1370 uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
5428bf5a
AH		 1372 if (INTEL_GEN(dev_priv) >= 11) {
1373 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375 } else {
1376 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378 }
a9701a89
RV		 1379
1380 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386 else
1387 p1 = 1;
1388
1389
1390 switch (p0) {
1391 case DPLL_CFGCR1_PDIV_2:
1392 p0 = 2;
1393 break;
1394 case DPLL_CFGCR1_PDIV_3:
1395 p0 = 3;
1396 break;
1397 case DPLL_CFGCR1_PDIV_5:
1398 p0 = 5;
1399 break;
1400 case DPLL_CFGCR1_PDIV_7:
1401 p0 = 7;
1402 break;
1403 }
1404
1405 switch (p2) {
1406 case DPLL_CFGCR1_KDIV_1:
1407 p2 = 1;
1408 break;
1409 case DPLL_CFGCR1_KDIV_2:
1410 p2 = 2;
1411 break;
1412 case DPLL_CFGCR1_KDIV_4:
1413 p2 = 4;
1414 break;
1415 }
1416
1417 ref_clock = dev_priv->cdclk.hw.ref;
1418
1419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1422 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1423
0e005888
PZ		 1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425 return 0;
1426
a9701a89
RV		 1427 return dco_freq / (p0 * p1 * p2 * 5);
1428}
1429
7b19f544
MN		 1430static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431 enum port port)
1432{
1433 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434
1435 switch (val) {
1436 case DDI_CLK_SEL_NONE:
1437 return 0;
1438 case DDI_CLK_SEL_TBT_162:
1439 return 162000;
1440 case DDI_CLK_SEL_TBT_270:
1441 return 270000;
1442 case DDI_CLK_SEL_TBT_540:
1443 return 540000;
1444 case DDI_CLK_SEL_TBT_810:
1445 return 810000;
1446 default:
1447 MISSING_CASE(val);
1448 return 0;
1449 }
1450}
1451
1452static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453 enum port port)
1454{
1455 u32 mg_pll_div0, mg_clktop_hsclkctl;
1456 u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457 u64 tmp;
1458
1459 refclk = dev_priv->cdclk.hw.ref;
1460
1461 mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462 mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463
1464 m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465 m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466 m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467 (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469
1470 switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472 div1 = 2;
1473 break;
1474 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475 div1 = 3;
1476 break;
1477 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478 div1 = 5;
1479 break;
1480 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481 div1 = 7;
1482 break;
1483 default:
1484 MISSING_CASE(mg_clktop_hsclkctl);
1485 return 0;
1486 }
1487
1488 div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490 /* div2 value of 0 is same as 1 means no div */
1491 if (div2 == 0)
1492 div2 = 1;
1493
1494 /*
1495 * Adjust the original formula to delay the division by 2^22 in order to
1496 * minimize possible rounding errors.
1497 */
1498 tmp = (u64)m1 * m2_int * refclk +
1499 (((u64)m1 * m2_frac * refclk) >> 22);
1500 tmp = div_u64(tmp, 5 * div1 * div2);
1501
1502 return tmp;
1503}
1504
398a017e
VS		 1505static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1506{
1507 int dotclock;
1508
1509 if (pipe_config->has_pch_encoder)
1510 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511 &pipe_config->fdi_m_n);
37a5650b 1512 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1513 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514 &pipe_config->dp_m_n);
1515 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516 dotclock = pipe_config->port_clock * 2 / 3;
1517 else
1518 dotclock = pipe_config->port_clock;
1519
b22ca995
SS		 1520 if (pipe_config->ycbcr420)
1521 dotclock *= 2;
1522
398a017e
VS		 1523 if (pipe_config->pixel_multiplier)
1524 dotclock /= pipe_config->pixel_multiplier;
1525
1526 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1527}
540e732c 1528
51c83cfa
MN		 1529static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530 struct intel_crtc_state *pipe_config)
1531{
1532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533 enum port port = encoder->port;
1534 int link_clock = 0;
1535 uint32_t pll_id;
1536
1537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538 if (port == PORT_A || port == PORT_B) {
1539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541 else
1542 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1543 pll_id);
1544 } else {
7b19f544
MN		 1545 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547 else
1548 link_clock = icl_calc_mg_pll_link(dev_priv, port);
51c83cfa
MN		 1549 }
1550
1551 pipe_config->port_clock = link_clock;
1552 ddi_dotclock_get(pipe_config);
1553}
1554
a9701a89
RV		 1555static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556 struct intel_crtc_state *pipe_config)
1557{
1558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1559 int link_clock = 0;
2952cd6f
RV		 1560 uint32_t cfgcr0;
1561 enum intel_dpll_id pll_id;
a9701a89
RV		 1562
1563 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1564
1565 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1566
1567 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1569 } else {
1570 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572 switch (link_clock) {
1573 case DPLL_CFGCR0_LINK_RATE_810:
1574 link_clock = 81000;
1575 break;
1576 case DPLL_CFGCR0_LINK_RATE_1080:
1577 link_clock = 108000;
1578 break;
1579 case DPLL_CFGCR0_LINK_RATE_1350:
1580 link_clock = 135000;
1581 break;
1582 case DPLL_CFGCR0_LINK_RATE_1620:
1583 link_clock = 162000;
1584 break;
1585 case DPLL_CFGCR0_LINK_RATE_2160:
1586 link_clock = 216000;
1587 break;
1588 case DPLL_CFGCR0_LINK_RATE_2700:
1589 link_clock = 270000;
1590 break;
1591 case DPLL_CFGCR0_LINK_RATE_3240:
1592 link_clock = 324000;
1593 break;
1594 case DPLL_CFGCR0_LINK_RATE_4050:
1595 link_clock = 405000;
1596 break;
1597 default:
1598 WARN(1, "Unsupported link rate\n");
1599 break;
1600 }
1601 link_clock *= 2;
1602 }
1603
1604 pipe_config->port_clock = link_clock;
1605
1606 ddi_dotclock_get(pipe_config);
1607}
1608
540e732c 1609static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1610 struct intel_crtc_state *pipe_config)
540e732c 1611{
fac5e23e 1612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c 1613 int link_clock = 0;
2952cd6f
RV		 1614 uint32_t dpll_ctl1;
1615 enum intel_dpll_id pll_id;
540e732c 1616
2952cd6f 1617 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1618
1619 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1620
2952cd6f
RV		 1621 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
540e732c 1623 } else {
2952cd6f
RV		 1624 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
540e732c
S		 1626
1627 switch (link_clock) {
71cd8423 1628 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1629 link_clock = 81000;
1630 break;
71cd8423 1631 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1632 link_clock = 108000;
1633 break;
71cd8423 1634 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1635 link_clock = 135000;
1636 break;
71cd8423 1637 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1638 link_clock = 162000;
1639 break;
71cd8423 1640 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1641 link_clock = 216000;
1642 break;
71cd8423 1643 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1644 link_clock = 270000;
1645 break;
1646 default:
1647 WARN(1, "Unsupported link rate\n");
1648 break;
1649 }
1650 link_clock *= 2;
1651 }
1652
1653 pipe_config->port_clock = link_clock;
1654
398a017e 1655 ddi_dotclock_get(pipe_config);
540e732c
S		 1656}
1657
3d51278a 1658static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1659 struct intel_crtc_state *pipe_config)
11578553 1660{
fac5e23e 1661 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1662 int link_clock = 0;
1663 u32 val, pll;
1664
c856052a 1665 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1666 switch (val & PORT_CLK_SEL_MASK) {
1667 case PORT_CLK_SEL_LCPLL_810:
1668 link_clock = 81000;
1669 break;
1670 case PORT_CLK_SEL_LCPLL_1350:
1671 link_clock = 135000;
1672 break;
1673 case PORT_CLK_SEL_LCPLL_2700:
1674 link_clock = 270000;
1675 break;
1676 case PORT_CLK_SEL_WRPLL1:
01403de3 1677 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1678 break;
1679 case PORT_CLK_SEL_WRPLL2:
01403de3 1680 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1681 break;
1682 case PORT_CLK_SEL_SPLL:
1683 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684 if (pll == SPLL_PLL_FREQ_810MHz)
1685 link_clock = 81000;
1686 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687 link_clock = 135000;
1688 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689 link_clock = 270000;
1690 else {
1691 WARN(1, "bad spll freq\n");
1692 return;
1693 }
1694 break;
1695 default:
1696 WARN(1, "bad port clock sel\n");
1697 return;
1698 }
1699
1700 pipe_config->port_clock = link_clock * 2;
1701
398a017e 1702 ddi_dotclock_get(pipe_config);
11578553
JB		 1703}
1704
bb911536 1705static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
977bb38d 1706{
aa610dcb 1707 struct intel_dpll_hw_state *state;
9e2c8475 1708 struct dpll clock;
aa610dcb
ID		 1709
1710 /* For DDI ports we always use a shared PLL. */
bb911536 1711 if (WARN_ON(!crtc_state->shared_dpll))
aa610dcb
ID		 1712 return 0;
1713
bb911536 1714 state = &crtc_state->dpll_hw_state;
aa610dcb
ID		 1715
1716 clock.m1 = 2;
1717 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1723
1724 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1725}
1726
1727static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1728 struct intel_crtc_state *pipe_config)
977bb38d 1729{
bb911536 1730 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
977bb38d 1731
398a017e 1732 ddi_dotclock_get(pipe_config);
977bb38d
S		 1733}
1734
35686a44
VS		 1735static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736 struct intel_crtc_state *pipe_config)
3d51278a 1737{
0853723b 1738 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1739
0853723b 1740 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1741 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1742 else if (IS_GEN9_BC(dev_priv))
22606a18 1743 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1744 else if (IS_GEN9_LP(dev_priv))
977bb38d 1745 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1746 else if (IS_CANNONLAKE(dev_priv))
1747 cnl_ddi_clock_get(encoder, pipe_config);
51c83cfa
MN		 1748 else if (IS_ICELAKE(dev_priv))
1749 icl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1750}
1751
3dc38eea 1752void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1753{
3dc38eea 1754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1755 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1756 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1757 u32 temp;
dae84799 1758
5448f53f
VS		 1759 if (!intel_crtc_has_dp_encoder(crtc_state))
1760 return;
4d1de975 1761
5448f53f
VS		 1762 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1763
1764 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1765
1766 if (crtc_state->limited_color_range)
1767 temp |= TRANS_MSA_CEA_RANGE;
1768
5448f53f
VS		 1769 switch (crtc_state->pipe_bpp) {
1770 case 18:
1771 temp |= TRANS_MSA_6_BPC;
1772 break;
1773 case 24:
1774 temp |= TRANS_MSA_8_BPC;
1775 break;
1776 case 30:
1777 temp |= TRANS_MSA_10_BPC;
1778 break;
1779 case 36:
1780 temp |= TRANS_MSA_12_BPC;
1781 break;
1782 default:
1783 MISSING_CASE(crtc_state->pipe_bpp);
1784 break;
dae84799 1785 }
5448f53f
VS		 1786
1787 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1788}
1789
3dc38eea
ACO		 1790void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1791 bool state)
0e32b39c 1792{
3dc38eea 1793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1795 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c 1796 uint32_t temp;
7e732cac 1797
0e32b39c
DA		 1798 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1799 if (state == true)
1800 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1801 else
1802 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1803 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1804}
1805
3dc38eea 1806void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1807{
3dc38eea 1808 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1809 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 enum pipe pipe = crtc->pipe;
3dc38eea 1812 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1813 enum port port = encoder->port;
8d9ddbcb
PZ		 1814 uint32_t temp;
1815
ad80a810
PZ		 1816 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1817 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1818 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1819
3dc38eea 1820 switch (crtc_state->pipe_bpp) {
dfcef252 1821 case 18:
ad80a810 1822 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1823 break;
1824 case 24:
ad80a810 1825 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1826 break;
1827 case 30:
ad80a810 1828 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1829 break;
1830 case 36:
ad80a810 1831 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1832 break;
1833 default:
4e53c2e0 1834 BUG();
dfcef252 1835 }
72662e10 1836
3dc38eea 1837 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1838 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1839 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1840 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1841
e6f0bfc4
PZ		 1842 if (cpu_transcoder == TRANSCODER_EDP) {
1843 switch (pipe) {
1844 case PIPE_A:
c7670b10
PZ		 1845 /* On Haswell, can only use the always-on power well for
1846 * eDP when not using the panel fitter, and when not
1847 * using motion blur mitigation (which we don't
1848 * support). */
772c2a51 1849 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1850 (crtc_state->pch_pfit.enabled ||
1851 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1852 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1853 else
1854 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1855 break;
1856 case PIPE_B:
1857 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1858 break;
1859 case PIPE_C:
1860 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1861 break;
1862 default:
1863 BUG();
1864 break;
1865 }
1866 }
1867
742745f1 1868 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1869 if (crtc_state->has_hdmi_sink)
ad80a810 1870 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1871 else
ad80a810 1872 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1873
1874 if (crtc_state->hdmi_scrambling)
1875 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1876 if (crtc_state->hdmi_high_tmds_clock_ratio)
1877 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1878 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1879 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1880 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1881 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1882 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1883 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1884 } else {
742745f1
VS		 1885 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1886 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1887 }
1888
ad80a810 1889 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1890}
72662e10 1891
90c3e219 1892void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1893{
90c3e219
CT		 1894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1897 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1898 uint32_t val = I915_READ(reg);
1899
0e32b39c 1900 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1901 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1902 I915_WRITE(reg, val);
90c3e219
CT		 1903
1904 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1905 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1906 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1907 /* Quirk time at 100ms for reliable operation */
1908 msleep(100);
1909 }
72662e10
ED		 1910}
1911
2320175f
SP		 1912int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1913 bool enable)
1914{
1915 struct drm_device *dev = intel_encoder->base.dev;
1916 struct drm_i915_private *dev_priv = to_i915(dev);
1917 enum pipe pipe = 0;
1918 int ret = 0;
1919 uint32_t tmp;
1920
1921 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1922 intel_encoder->power_domain)))
1923 return -ENXIO;
1924
1925 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1926 ret = -EIO;
1927 goto out;
1928 }
1929
1930 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1931 if (enable)
1932 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1933 else
1934 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1935 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1936out:
1937 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1938 return ret;
1939}
1940
bcbc889b
PZ		 1941bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1942{
1943 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1944 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1945 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1946 int type = intel_connector->base.connector_type;
0fce04c8 1947 enum port port = encoder->port;
bcbc889b
PZ		 1948 enum pipe pipe = 0;
1949 enum transcoder cpu_transcoder;
1950 uint32_t tmp;
e27daab4 1951 bool ret;
bcbc889b 1952
79f255a0 1953 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1954 encoder->power_domain))
882244a3
PZ		 1955 return false;
1956
1524e93e 1957 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1958 ret = false;
1959 goto out;
1960 }
bcbc889b
PZ		 1961
1962 if (port == PORT_A)
1963 cpu_transcoder = TRANSCODER_EDP;
1964 else
1a240d4d 1965 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1966
1967 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1968
1969 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1970 case TRANS_DDI_MODE_SELECT_HDMI:
1971 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1972 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1973 break;
bcbc889b
PZ		 1974
1975 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1976 ret = type == DRM_MODE_CONNECTOR_eDP ||
1977 type == DRM_MODE_CONNECTOR_DisplayPort;
1978 break;
1979
0e32b39c
DA		 1980 case TRANS_DDI_MODE_SELECT_DP_MST:
1981 /* if the transcoder is in MST state then
1982 * connector isn't connected */
e27daab4
ID		 1983 ret = false;
1984 break;
bcbc889b
PZ		 1985
1986 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1987 ret = type == DRM_MODE_CONNECTOR_VGA;
1988 break;
bcbc889b
PZ		 1989
1990 default:
e27daab4
ID		 1991 ret = false;
1992 break;
bcbc889b 1993 }
e27daab4
ID		 1994
1995out:
1524e93e 1996 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1997
1998 return ret;
bcbc889b
PZ		 1999}
2000
85234cdc
DV		 2001bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2002 enum pipe *pipe)
2003{
2004 struct drm_device *dev = encoder->base.dev;
fac5e23e 2005 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 2006 enum port port = encoder->port;
3657e927 2007 enum pipe p;
85234cdc 2008 u32 tmp;
e27daab4 2009 bool ret;
85234cdc 2010
79f255a0
ACO		 2011 if (!intel_display_power_get_if_enabled(dev_priv,
2012 encoder->power_domain))
6d129bea
ID		 2013 return false;
2014
e27daab4
ID		 2015 ret = false;
2016
fe43d3f5 2017 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2018
2019 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 2020 goto out;
85234cdc 2021
ad80a810
PZ		 2022 if (port == PORT_A) {
2023 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2024
ad80a810
PZ		 2025 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2026 case TRANS_DDI_EDP_INPUT_A_ON:
2027 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2028 *pipe = PIPE_A;
2029 break;
2030 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2031 *pipe = PIPE_B;
2032 break;
2033 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2034 *pipe = PIPE_C;
2035 break;
2036 }
2037
e27daab4 2038 ret = true;
ad80a810 2039
e27daab4
ID		 2040 goto out;
2041 }
0e32b39c 2042
3657e927
MK		 2043 for_each_pipe(dev_priv, p) {
2044 enum transcoder cpu_transcoder = (enum transcoder) p;
2045
2046 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4
ID		 2047
2048 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2049 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2050 TRANS_DDI_MODE_SELECT_DP_MST)
2051 goto out;
2052
3657e927 2053 *pipe = p;
e27daab4
ID		 2054 ret = true;
2055
2056 goto out;
85234cdc
DV		 2057 }
2058 }
2059
84f44ce7 2060 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2061
e27daab4 2062out:
cc3f90f0 2063 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0 2064 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2065 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2066 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2067 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2068 DRM_ERROR("Port %c enabled but PHY powered down? "
2069 "(PHY_CTL %08x)\n", port_name(port), tmp);
2070 }
2071
79f255a0 2072 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 2073
2074 return ret;
85234cdc
DV		 2075}
2076
52528055
ID		 2077static inline enum intel_display_power_domain
2078intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
2079{
2080 /* CNL HW requires corresponding AUX IOs to be powered up for PSR with
2081 * DC states enabled at the same time, while for driver initiated AUX
2082 * transfers we need the same AUX IOs to be powered but with DC states
2083 * disabled. Accordingly use the AUX power domain here which leaves DC
2084 * states enabled.
2085 * However, for non-A AUX ports the corresponding non-EDP transcoders
2086 * would have already enabled power well 2 and DC_OFF. This means we can
2087 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2088 * specific AUX_IO reference without powering up any extra wells.
2089 * Note that PSR is enabled only on Port A even though this function
2090 * returns the correct domain for other ports too.
2091 */
2092 return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2093 intel_dp->aux_power_domain;
2094}
2095
2096static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2097 struct intel_crtc_state *crtc_state)
62b69566 2098{
b79ebe74 2099 struct intel_digital_port *dig_port;
52528055 2100 u64 domains;
62b69566 2101
52528055
ID		 2102 /*
2103 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2104 * happen since fake-MST encoders don't set their get_power_domains()
2105 * hook.
52528055
ID		 2106 */
2107 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
b79ebe74
ID		 2108 return 0;
2109
2110 dig_port = enc_to_dig_port(&encoder->base);
2111 domains = BIT_ULL(dig_port->ddi_io_power_domain);
52528055
ID		 2112
2113 /* AUX power is only needed for (e)DP mode, not for HDMI. */
2114 if (intel_crtc_has_dp_encoder(crtc_state)) {
2115 struct intel_dp *intel_dp = &dig_port->dp;
2116
2117 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
2118 }
2119
2120 return domains;
62b69566
ACO		 2121}
2122
3dc38eea 2123void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2124{
3dc38eea 2125 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2126 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2127 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2128 enum port port = encoder->port;
3dc38eea 2129 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2130
bb523fc0
PZ		 2131 if (cpu_transcoder != TRANSCODER_EDP)
2132 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2133 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2134}
2135
3dc38eea 2136void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2137{
3dc38eea
ACO		 2138 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2139 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2140
bb523fc0
PZ		 2141 if (cpu_transcoder != TRANSCODER_EDP)
2142 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2143 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2144}
2145
a7d8dbc0
VS		 2146static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2147 enum port port, uint8_t iboost)
f8896f5d 2148{
a7d8dbc0
VS		 2149 u32 tmp;
2150
2151 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2152 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2153 if (iboost)
2154 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2155 else
2156 tmp |= BALANCE_LEG_DISABLE(port);
2157 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2158}
2159
081dfcfa
VS		 2160static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2161 int level, enum intel_output_type type)
a7d8dbc0
VS		 2162{
2163 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2165 enum port port = encoder->port;
f8896f5d 2166 uint8_t iboost;
f8896f5d 2167
081dfcfa
VS		 2168 if (type == INTEL_OUTPUT_HDMI)
2169 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2170 else
2171 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2172
081dfcfa
VS		 2173 if (iboost == 0) {
2174 const struct ddi_buf_trans *ddi_translations;
2175 int n_entries;
2176
2177 if (type == INTEL_OUTPUT_HDMI)
2178 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2179 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2180 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2181 else
edba48fd 2182 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2183
21b39d2a
VS		 2184 if (WARN_ON_ONCE(!ddi_translations))
2185 return;
2186 if (WARN_ON_ONCE(level >= n_entries))
2187 level = n_entries - 1;
2188
081dfcfa 2189 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2190 }
2191
2192 /* Make sure that the requested I_boost is valid */
2193 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2194 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2195 return;
2196 }
2197
a7d8dbc0 2198 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2199
a7d8dbc0
VS		 2200 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2201 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2202}
2203
7d4f37b5
VS		 2204static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2205 int level, enum intel_output_type type)
96fb9f9b 2206{
7d4f37b5 2207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2208 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2209 enum port port = encoder->port;
043eaf36 2210 int n_entries;
7d4f37b5
VS		 2211
2212 if (type == INTEL_OUTPUT_HDMI)
2213 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2214 else if (type == INTEL_OUTPUT_EDP)
2215 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2216 else
2217 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2218
21b39d2a
VS		 2219 if (WARN_ON_ONCE(!ddi_translations))
2220 return;
2221 if (WARN_ON_ONCE(level >= n_entries))
2222 level = n_entries - 1;
2223
b6e08203
ACO		 2224 bxt_ddi_phy_set_signal_level(dev_priv, port,
2225 ddi_translations[level].margin,
2226 ddi_translations[level].scale,
2227 ddi_translations[level].enable,
2228 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2229}
2230
ffe5111e
VS		 2231u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2232{
2233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
edba48fd 2234 enum port port = encoder->port;
ffe5111e
VS		 2235 int n_entries;
2236
36cf89f5
MN		 2237 if (IS_ICELAKE(dev_priv)) {
2238 if (port == PORT_A || port == PORT_B)
2239 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2240 &n_entries);
2241 else
2242 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2243 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2244 if (encoder->type == INTEL_OUTPUT_EDP)
2245 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2246 else
2247 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2248 } else if (IS_GEN9_LP(dev_priv)) {
2249 if (encoder->type == INTEL_OUTPUT_EDP)
2250 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2251 else
2252 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2253 } else {
2254 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2255 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2256 else
edba48fd 2257 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2258 }
ffe5111e
VS		 2259
2260 if (WARN_ON(n_entries < 1))
2261 n_entries = 1;
2262 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2263 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2264
2265 return index_to_dp_signal_levels[n_entries - 1] &
2266 DP_TRAIN_VOLTAGE_SWING_MASK;
2267}
2268
4718a365
VS		 2269/*
2270 * We assume that the full set of pre-emphasis values can be
2271 * used on all DDI platforms. Should that change we need to
2272 * rethink this code.
2273 */
2274u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2275{
2276 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2278 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2280 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2282 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2284 default:
2285 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2286 }
2287}
2288
f3cf4ba4
VS		 2289static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2290 int level, enum intel_output_type type)
cf54ca8b 2291{
f3cf4ba4 2292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2293 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2294 enum port port = encoder->port;
f3cf4ba4
VS		 2295 int n_entries, ln;
2296 u32 val;
cf54ca8b 2297
f3cf4ba4 2298 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2299 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2300 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2301 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2302 else
2303 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2304
21b39d2a 2305 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2306 return;
21b39d2a 2307 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2308 level = n_entries - 1;
cf54ca8b
RV		 2309
2310 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2311 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2312 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2313 val |= SCALING_MODE_SEL(2);
2314 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2315
2316 /* Program PORT_TX_DW2 */
2317 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2318 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2319 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2320 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2321 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2322 /* Rcomp scalar is fixed as 0x98 for every table entry */
2323 val |= RCOMP_SCALAR(0x98);
2324 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2325
20303eb4 2326 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2327 /* We cannot write to GRP. It would overrite individual loadgen */
2328 for (ln = 0; ln < 4; ln++) {
2329 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 2330 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2331 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2332 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2333 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2334 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2335 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2336 }
2337
20303eb4 2338 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2339 /* All DW5 values are fixed for every table entry */
2340 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2341 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2342 val |= RTERM_SELECT(6);
2343 val |= TAP3_DISABLE;
2344 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2345
20303eb4 2346 /* Program PORT_TX_DW7 */
cf54ca8b 2347 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2348 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2349 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2350 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2351}
2352
f3cf4ba4
VS		 2353static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2354 int level, enum intel_output_type type)
cf54ca8b 2355{
0091abc3 2356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2357 enum port port = encoder->port;
f3cf4ba4 2358 int width, rate, ln;
cf54ca8b 2359 u32 val;
0091abc3 2360
f3cf4ba4 2361 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2362 width = 4;
f3cf4ba4 2363 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2364 } else {
f3cf4ba4
VS		 2365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2366
2367 width = intel_dp->lane_count;
2368 rate = intel_dp->link_rate;
0091abc3 2369 }
cf54ca8b
RV		 2370
2371 /*
2372 * 1. If port type is eDP or DP,
2373 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2374 * else clear to 0b.
2375 */
2376 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2377 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2378 val |= COMMON_KEEPER_EN;
2379 else
2380 val &= ~COMMON_KEEPER_EN;
2381 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2382
2383 /* 2. Program loadgen select */
2384 /*
0091abc3
CT		 2385 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2386 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2387 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2388 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2389 */
0091abc3
CT		 2390 for (ln = 0; ln <= 3; ln++) {
2391 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2392 val &= ~LOADGEN_SELECT;
2393
a8e45a1c
NM		 2394 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2395 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2396 val |= LOADGEN_SELECT;
2397 }
2398 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2399 }
cf54ca8b
RV		 2400
2401 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2402 val = I915_READ(CNL_PORT_CL1CM_DW5);
2403 val |= SUS_CLOCK_CONFIG;
2404 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2405
2406 /* 4. Clear training enable to change swing values */
2407 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2408 val &= ~TX_TRAINING_EN;
2409 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2410
2411 /* 5. Program swing and de-emphasis */
f3cf4ba4 2412 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2413
2414 /* 6. Set training enable to trigger update */
2415 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2416 val |= TX_TRAINING_EN;
2417 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2418}
2419
fb5c8e9d
MN		 2420static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2421 u32 level, enum port port, int type)
2422{
2423 const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2424 u32 n_entries, val;
2425 int ln;
2426
2427 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2428 &n_entries);
2429 if (!ddi_translations)
2430 return;
2431
2432 if (level >= n_entries) {
2433 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2434 level = n_entries - 1;
2435 }
2436
2437 /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2438 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2439 val &= ~RTERM_SELECT_MASK;
2440 val |= RTERM_SELECT(0x6);
2441 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2442
2443 /* Program PORT_TX_DW5 */
2444 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2445 /* Set DisableTap2 and DisableTap3 if MIPI DSI
2446 * Clear DisableTap2 and DisableTap3 for all other Ports
2447 */
2448 if (type == INTEL_OUTPUT_DSI) {
2449 val |= TAP2_DISABLE;
2450 val |= TAP3_DISABLE;
2451 } else {
2452 val &= ~TAP2_DISABLE;
2453 val &= ~TAP3_DISABLE;
2454 }
2455 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2456
2457 /* Program PORT_TX_DW2 */
2458 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2459 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2460 RCOMP_SCALAR_MASK);
2461 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2462 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2463 /* Program Rcomp scalar for every table entry */
2464 val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2465 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2466
2467 /* Program PORT_TX_DW4 */
2468 /* We cannot write to GRP. It would overwrite individual loadgen. */
2469 for (ln = 0; ln <= 3; ln++) {
2470 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2471 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2472 CURSOR_COEFF_MASK);
2473 val |= ddi_translations[level].dw4_scaling;
2474 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2475 }
2476}
2477
2478static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2479 u32 level,
2480 enum intel_output_type type)
2481{
2482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2483 enum port port = encoder->port;
2484 int width = 0;
2485 int rate = 0;
2486 u32 val;
2487 int ln = 0;
2488
2489 if (type == INTEL_OUTPUT_HDMI) {
2490 width = 4;
2491 /* Rate is always < than 6GHz for HDMI */
2492 } else {
2493 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2494
2495 width = intel_dp->lane_count;
2496 rate = intel_dp->link_rate;
2497 }
2498
2499 /*
2500 * 1. If port type is eDP or DP,
2501 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2502 * else clear to 0b.
2503 */
2504 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2505 if (type == INTEL_OUTPUT_HDMI)
2506 val &= ~COMMON_KEEPER_EN;
2507 else
2508 val |= COMMON_KEEPER_EN;
2509 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2510
2511 /* 2. Program loadgen select */
2512 /*
2513 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2514 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2515 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2516 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2517 */
2518 for (ln = 0; ln <= 3; ln++) {
2519 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2520 val &= ~LOADGEN_SELECT;
2521
2522 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2523 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2524 val |= LOADGEN_SELECT;
2525 }
2526 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2527 }
2528
2529 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2530 val = I915_READ(ICL_PORT_CL_DW5(port));
2531 val |= SUS_CLOCK_CONFIG;
2532 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2533
2534 /* 4. Clear training enable to change swing values */
2535 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2536 val &= ~TX_TRAINING_EN;
2537 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2538
2539 /* 5. Program swing and de-emphasis */
2540 icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2541
2542 /* 6. Set training enable to trigger update */
2543 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2544 val |= TX_TRAINING_EN;
2545 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2546}
2547
07685c82
MN		 2548static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2549 int link_clock,
2550 u32 level)
2551{
2552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2553 enum port port = encoder->port;
2554 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2555 u32 n_entries, val;
2556 int ln;
2557
2558 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2559 ddi_translations = icl_mg_phy_ddi_translations;
2560 /* The table does not have values for level 3 and level 9. */
2561 if (level >= n_entries || level == 3 || level == 9) {
2562 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2563 level, n_entries - 2);
2564 level = n_entries - 2;
2565 }
2566
2567 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2568 for (ln = 0; ln < 2; ln++) {
2569 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2570 val &= ~CRI_USE_FS32;
2571 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2572
2573 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2574 val &= ~CRI_USE_FS32;
2575 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2576 }
2577
2578 /* Program MG_TX_SWINGCTRL with values from vswing table */
2579 for (ln = 0; ln < 2; ln++) {
2580 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2581 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583 ddi_translations[level].cri_txdeemph_override_17_12);
2584 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2585
2586 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2587 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2588 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2589 ddi_translations[level].cri_txdeemph_override_17_12);
2590 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2591 }
2592
2593 /* Program MG_TX_DRVCTRL with values from vswing table */
2594 for (ln = 0; ln < 2; ln++) {
2595 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2596 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2597 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2598 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2599 ddi_translations[level].cri_txdeemph_override_5_0) |
2600 CRI_TXDEEMPH_OVERRIDE_11_6(
2601 ddi_translations[level].cri_txdeemph_override_11_6) |
2602 CRI_TXDEEMPH_OVERRIDE_EN;
2603 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2604
2605 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2606 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2607 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2608 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2609 ddi_translations[level].cri_txdeemph_override_5_0) |
2610 CRI_TXDEEMPH_OVERRIDE_11_6(
2611 ddi_translations[level].cri_txdeemph_override_11_6) |
2612 CRI_TXDEEMPH_OVERRIDE_EN;
2613 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2614
2615 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2616 }
2617
2618 /*
2619 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2620 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2621 * values from table for which TX1 and TX2 enabled.
2622 */
2623 for (ln = 0; ln < 2; ln++) {
2624 val = I915_READ(MG_CLKHUB(port, ln));
2625 if (link_clock < 300000)
2626 val |= CFG_LOW_RATE_LKREN_EN;
2627 else
2628 val &= ~CFG_LOW_RATE_LKREN_EN;
2629 I915_WRITE(MG_CLKHUB(port, ln), val);
2630 }
2631
2632 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2633 for (ln = 0; ln < 2; ln++) {
2634 val = I915_READ(MG_TX1_DCC(port, ln));
2635 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2636 if (link_clock <= 500000) {
2637 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2638 } else {
2639 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2640 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2641 }
2642 I915_WRITE(MG_TX1_DCC(port, ln), val);
2643
2644 val = I915_READ(MG_TX2_DCC(port, ln));
2645 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2646 if (link_clock <= 500000) {
2647 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2648 } else {
2649 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2650 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2651 }
2652 I915_WRITE(MG_TX2_DCC(port, ln), val);
2653 }
2654
2655 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2656 for (ln = 0; ln < 2; ln++) {
2657 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2658 val |= CRI_CALCINIT;
2659 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2660
2661 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2662 val |= CRI_CALCINIT;
2663 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2664 }
2665}
2666
2667static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2668 int link_clock,
2669 u32 level,
fb5c8e9d
MN		 2670 enum intel_output_type type)
2671{
2672 enum port port = encoder->port;
2673
2674 if (port == PORT_A || port == PORT_B)
2675 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2676 else
07685c82 2677 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2678}
2679
f8896f5d
DW		 2680static uint32_t translate_signal_level(int signal_levels)
2681{
97eeb872 2682 int i;
f8896f5d 2683
97eeb872
VS		 2684 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2685 if (index_to_dp_signal_levels[i] == signal_levels)
2686 return i;
f8896f5d
DW		 2687 }
2688
97eeb872
VS		 2689 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2690 signal_levels);
2691
2692 return 0;
f8896f5d
DW		 2693}
2694
1b6e2fd2
RV		 2695static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2696{
2697 uint8_t train_set = intel_dp->train_set[0];
2698 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2699 DP_TRAIN_PRE_EMPHASIS_MASK);
2700
2701 return translate_signal_level(signal_levels);
2702}
2703
d509af6c 2704u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2705{
2706 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2707 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2708 struct intel_encoder *encoder = &dport->base;
d02ace87 2709 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2710
fb5c8e9d 2711 if (IS_ICELAKE(dev_priv))
07685c82
MN		 2712 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2713 level, encoder->type);
fb5c8e9d 2714 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2715 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2716 else
7d4f37b5 2717 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2718
2719 return 0;
2720}
2721
2722uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2723{
2724 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2725 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2726 struct intel_encoder *encoder = &dport->base;
d02ace87 2727 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2728
b976dc53 2729 if (IS_GEN9_BC(dev_priv))
081dfcfa 2730 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2731
f8896f5d
DW		 2732 return DDI_BUF_TRANS_SELECT(level);
2733}
2734
c27e917e
PZ		 2735void icl_map_plls_to_ports(struct drm_crtc *crtc,
2736 struct intel_crtc_state *crtc_state,
2737 struct drm_atomic_state *old_state)
2738{
2739 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2740 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2741 struct drm_connector_state *conn_state;
2742 struct drm_connector *conn;
2743 int i;
2744
2745 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2746 struct intel_encoder *encoder =
2747 to_intel_encoder(conn_state->best_encoder);
c46ef57d 2748 enum port port;
c27e917e
PZ		 2749 uint32_t val;
2750
2751 if (conn_state->crtc != crtc)
2752 continue;
2753
c46ef57d 2754 port = encoder->port;
c27e917e
PZ		 2755 mutex_lock(&dev_priv->dpll_lock);
2756
2757 val = I915_READ(DPCLKA_CFGCR0_ICL);
2758 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2759
2760 if (port == PORT_A || port == PORT_B) {
2761 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2762 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2763 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2764 POSTING_READ(DPCLKA_CFGCR0_ICL);
2765 }
2766
2767 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2768 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2769
2770 mutex_unlock(&dev_priv->dpll_lock);
2771 }
2772}
2773
2774void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2775 struct intel_crtc_state *crtc_state,
2776 struct drm_atomic_state *old_state)
2777{
2778 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2779 struct drm_connector_state *old_conn_state;
2780 struct drm_connector *conn;
2781 int i;
2782
2783 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2784 struct intel_encoder *encoder =
2785 to_intel_encoder(old_conn_state->best_encoder);
c46ef57d 2786 enum port port;
c27e917e
PZ		 2787
2788 if (old_conn_state->crtc != crtc)
2789 continue;
2790
c46ef57d 2791 port = encoder->port;
c27e917e
PZ		 2792 mutex_lock(&dev_priv->dpll_lock);
2793 I915_WRITE(DPCLKA_CFGCR0_ICL,
2794 I915_READ(DPCLKA_CFGCR0_ICL) |
2795 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2796 mutex_unlock(&dev_priv->dpll_lock);
2797 }
2798}
2799
d7c530b2 2800static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2801 const struct intel_shared_dpll *pll)
6441ab5f 2802{
e404ba8d 2803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2804 enum port port = encoder->port;
555e38d2 2805 uint32_t val;
6441ab5f 2806
c856052a
ACO		 2807 if (WARN_ON(!pll))
2808 return;
2809
04bf68bb 2810 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2811
c27e917e
PZ		 2812 if (IS_ICELAKE(dev_priv)) {
2813 if (port >= PORT_C)
2814 I915_WRITE(DDI_CLK_SEL(port),
2815 icl_pll_to_ddi_pll_sel(encoder, pll));
2816 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2817 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2818 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2819 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2820 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2821 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2822
555e38d2
RV		 2823 /*
2824 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2825 * This step and the step before must be done with separate
2826 * register writes.
2827 */
2828 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2829 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2830 I915_WRITE(DPCLKA_CFGCR0, val);
2831 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2832 /* DDI -> PLL mapping */
efa80add
S		 2833 val = I915_READ(DPLL_CTRL2);
2834
2835 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2836 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2837 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2838 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2839
2840 I915_WRITE(DPLL_CTRL2, val);
5416d871 2841
c56b89f1 2842 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2843 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2844 }
8edcda12
RV		 2845
2846 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2847}
2848
6b8506d5
VS		 2849static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2850{
2851 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2852 enum port port = encoder->port;
6b8506d5 2853
c27e917e
PZ		 2854 if (IS_ICELAKE(dev_priv)) {
2855 if (port >= PORT_C)
2856 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2857 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2858 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2859 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2860 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2861 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2862 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2863 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2864 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2865 }
6b8506d5
VS		 2866}
2867
ba88d153 2868static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 2869 const struct intel_crtc_state *crtc_state,
2870 const struct drm_connector_state *conn_state)
e404ba8d 2871{
ba88d153
MN		 2872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2874 enum port port = encoder->port;
62b69566 2875 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 2876 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 2877 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 2878
45e0327e 2879 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 2880
52528055
ID		 2881 intel_display_power_get(dev_priv,
2882 intel_ddi_main_link_aux_domain(intel_dp));
2883
45e0327e
VS		 2884 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2885 crtc_state->lane_count, is_mst);
680b71c2
VS		 2886
2887 intel_edp_panel_on(intel_dp);
32bdc400 2888
45e0327e 2889 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2890
2891 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2892
340a44be 2893 icl_program_mg_dp_mode(intel_dp);
bc334d91 2894 icl_disable_phy_clock_gating(dig_port);
340a44be 2895
fb5c8e9d 2896 if (IS_ICELAKE(dev_priv))
07685c82
MN		 2897 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2898 level, encoder->type);
fb5c8e9d 2899 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2900 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 2901 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2902 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 2903 else
3a6d84e6 2904 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 2905
ba88d153 2906 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 2907 if (!is_mst)
2908 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
ba88d153
MN		 2909 intel_dp_start_link_train(intel_dp);
2910 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2911 intel_dp_stop_link_train(intel_dp);
afb2c443 2912
bc334d91
PZ		 2913 icl_enable_phy_clock_gating(dig_port);
2914
2b5cf4ef
ID		 2915 if (!is_mst)
2916 intel_ddi_enable_pipe_clock(crtc_state);
ba88d153 2917}
901c2daf 2918
ba88d153 2919static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 2920 const struct intel_crtc_state *crtc_state,
45e0327e 2921 const struct drm_connector_state *conn_state)
ba88d153 2922{
f99be1b3
VS		 2923 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2924 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2926 enum port port = encoder->port;
ba88d153 2927 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2928 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2929
ba88d153 2930 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
45e0327e 2931 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2932
2933 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2934
fb5c8e9d 2935 if (IS_ICELAKE(dev_priv))
07685c82
MN		 2936 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2937 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 2938 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2939 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 2940 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2941 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 2942 else
7ea79333 2943 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7
RV		 2944
2945 if (IS_GEN9_BC(dev_priv))
081dfcfa 2946 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 2947
c7373764
ID		 2948 intel_ddi_enable_pipe_clock(crtc_state);
2949
f99be1b3 2950 intel_dig_port->set_infoframes(&encoder->base,
45e0327e 2951 crtc_state->has_infoframe,
f99be1b3 2952 crtc_state, conn_state);
ba88d153 2953}
32bdc400 2954
1524e93e 2955static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 2956 const struct intel_crtc_state *crtc_state,
5f88a9c6 2957 const struct drm_connector_state *conn_state)
ba88d153 2958{
45e0327e
VS		 2959 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2960 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2961 enum pipe pipe = crtc->pipe;
30cf6db8 2962
1939ba51
VS		 2963 /*
2964 * When called from DP MST code:
2965 * - conn_state will be NULL
2966 * - encoder will be the main encoder (ie. mst->primary)
2967 * - the main connector associated with this port
2968 * won't be active or linked to a crtc
2969 * - crtc_state will be the state of the first stream to
2970 * be activated on this port, and it may not be the same
2971 * stream that will be deactivated last, but each stream
2972 * should have a state that is identical when it comes to
2973 * the DP link parameteres
2974 */
2975
45e0327e 2976 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1
JN		 2977
2978 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2979
45e0327e
VS		 2980 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2981 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2982 else
2983 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
6441ab5f
PZ		 2984}
2985
e725f645
VS		 2986static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2987{
2988 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2989 enum port port = encoder->port;
e725f645
VS		 2990 bool wait = false;
2991 u32 val;
2992
2993 val = I915_READ(DDI_BUF_CTL(port));
2994 if (val & DDI_BUF_CTL_ENABLE) {
2995 val &= ~DDI_BUF_CTL_ENABLE;
2996 I915_WRITE(DDI_BUF_CTL(port), val);
2997 wait = true;
2998 }
2999
3000 val = I915_READ(DP_TP_CTL(port));
3001 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3002 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3003 I915_WRITE(DP_TP_CTL(port), val);
3004
3005 if (wait)
3006 intel_wait_ddi_buf_idle(dev_priv, port);
3007}
3008
f45f3da7
VS		 3009static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3010 const struct intel_crtc_state *old_crtc_state,
3011 const struct drm_connector_state *old_conn_state)
6441ab5f 3012{
f45f3da7
VS		 3013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3014 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3015 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3016 bool is_mst = intel_crtc_has_type(old_crtc_state,
3017 INTEL_OUTPUT_DP_MST);
2886e93f 3018
2b5cf4ef
ID		 3019 if (!is_mst) {
3020 intel_ddi_disable_pipe_clock(old_crtc_state);
3021 /*
3022 * Power down sink before disabling the port, otherwise we end
3023 * up getting interrupts from the sink on detecting link loss.
3024 */
be1c63c8 3025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3026 }
c5f93fcf 3027
f45f3da7 3028 intel_disable_ddi_buf(encoder);
7618138d 3029
f45f3da7
VS		 3030 intel_edp_panel_vdd_on(intel_dp);
3031 intel_edp_panel_off(intel_dp);
a836bdf9 3032
f45f3da7 3033 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
c5f93fcf 3034
f45f3da7 3035 intel_ddi_clk_disable(encoder);
52528055
ID		 3036
3037 intel_display_power_put(dev_priv,
3038 intel_ddi_main_link_aux_domain(intel_dp));
f45f3da7 3039}
c5f93fcf 3040
f45f3da7
VS		 3041static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3042 const struct intel_crtc_state *old_crtc_state,
3043 const struct drm_connector_state *old_conn_state)
3044{
3045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3046 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3047 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3048
c7373764
ID		 3049 dig_port->set_infoframes(&encoder->base, false,
3050 old_crtc_state, old_conn_state);
3051
afb2c443
ID		 3052 intel_ddi_disable_pipe_clock(old_crtc_state);
3053
f45f3da7 3054 intel_disable_ddi_buf(encoder);
62b69566 3055
f45f3da7 3056 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
b2ccb822 3057
f45f3da7
VS		 3058 intel_ddi_clk_disable(encoder);
3059
3060 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3061}
3062
3063static void intel_ddi_post_disable(struct intel_encoder *encoder,
3064 const struct intel_crtc_state *old_crtc_state,
3065 const struct drm_connector_state *old_conn_state)
3066{
3067 /*
1939ba51
VS		 3068 * When called from DP MST code:
3069 * - old_conn_state will be NULL
3070 * - encoder will be the main encoder (ie. mst->primary)
3071 * - the main connector associated with this port
3072 * won't be active or linked to a crtc
3073 * - old_crtc_state will be the state of the last stream to
3074 * be deactivated on this port, and it may not be the same
3075 * stream that was activated last, but each stream
3076 * should have a state that is identical when it comes to
3077 * the DP link parameteres
f45f3da7 3078 */
1939ba51
VS		 3079
3080 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3081 intel_ddi_post_disable_hdmi(encoder,
3082 old_crtc_state, old_conn_state);
3083 else
3084 intel_ddi_post_disable_dp(encoder,
3085 old_crtc_state, old_conn_state);
6441ab5f
PZ		 3086}
3087
1524e93e 3088void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3089 const struct intel_crtc_state *old_crtc_state,
3090 const struct drm_connector_state *old_conn_state)
b7076546 3091{
1524e93e 3092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 3093 uint32_t val;
3094
3095 /*
3096 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3097 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3098 * step 13 is the correct place for it. Step 18 is where it was
3099 * originally before the BUN.
3100 */
3101 val = I915_READ(FDI_RX_CTL(PIPE_A));
3102 val &= ~FDI_RX_ENABLE;
3103 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3104
fb0bd3bd
VS		 3105 intel_disable_ddi_buf(encoder);
3106 intel_ddi_clk_disable(encoder);
b7076546
ML		 3107
3108 val = I915_READ(FDI_RX_MISC(PIPE_A));
3109 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3110 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3111 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3112
3113 val = I915_READ(FDI_RX_CTL(PIPE_A));
3114 val &= ~FDI_PCDCLK;
3115 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3116
3117 val = I915_READ(FDI_RX_CTL(PIPE_A));
3118 val &= ~FDI_RX_PLL_ENABLE;
3119 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3120}
3121
15d05f0e
VS		 3122static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3123 const struct intel_crtc_state *crtc_state,
3124 const struct drm_connector_state *conn_state)
72662e10 3125{
15d05f0e
VS		 3126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3127 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3128 enum port port = encoder->port;
72662e10 3129
15d05f0e
VS		 3130 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3131 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3132
15d05f0e
VS		 3133 intel_edp_backlight_on(crtc_state, conn_state);
3134 intel_psr_enable(intel_dp, crtc_state);
3135 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3136
15d05f0e
VS		 3137 if (crtc_state->has_audio)
3138 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3139}
3140
3141static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3142 const struct intel_crtc_state *crtc_state,
3143 const struct drm_connector_state *conn_state)
3144{
3145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3146 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3147 struct drm_connector *connector = conn_state->connector;
0fce04c8 3148 enum port port = encoder->port;
15d05f0e 3149
277ab5ab
VS		 3150 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3151 crtc_state->hdmi_high_tmds_clock_ratio,
3152 crtc_state->hdmi_scrambling))
3153 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3154 connector->base.id, connector->name);
15d05f0e 3155
0519c102
VS		 3156 /* Display WA #1143: skl,kbl,cfl */
3157 if (IS_GEN9_BC(dev_priv)) {
3158 /*
3159 * For some reason these chicken bits have been
3160 * stuffed into a transcoder register, event though
3161 * the bits affect a specific DDI port rather than
3162 * a specific transcoder.
3163 */
3164 static const enum transcoder port_to_transcoder[] = {
3165 [PORT_A] = TRANSCODER_EDP,
3166 [PORT_B] = TRANSCODER_A,
3167 [PORT_C] = TRANSCODER_B,
3168 [PORT_D] = TRANSCODER_C,
3169 [PORT_E] = TRANSCODER_A,
3170 };
3171 enum transcoder transcoder = port_to_transcoder[port];
3172 u32 val;
3173
3174 val = I915_READ(CHICKEN_TRANS(transcoder));
3175
3176 if (port == PORT_E)
3177 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3178 DDIE_TRAINING_OVERRIDE_VALUE;
3179 else
3180 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3181 DDI_TRAINING_OVERRIDE_VALUE;
3182
3183 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3184 POSTING_READ(CHICKEN_TRANS(transcoder));
3185
3186 udelay(1);
3187
3188 if (port == PORT_E)
3189 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3190 DDIE_TRAINING_OVERRIDE_VALUE);
3191 else
3192 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3193 DDI_TRAINING_OVERRIDE_VALUE);
3194
3195 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3196 }
3197
15d05f0e
VS		 3198 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3199 * are ignored so nothing special needs to be done besides
3200 * enabling the port.
3201 */
3202 I915_WRITE(DDI_BUF_CTL(port),
3203 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3204
15d05f0e
VS		 3205 if (crtc_state->has_audio)
3206 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3207}
3208
3209static void intel_enable_ddi(struct intel_encoder *encoder,
3210 const struct intel_crtc_state *crtc_state,
3211 const struct drm_connector_state *conn_state)
3212{
3213 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3214 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3215 else
3216 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3217
3218 /* Enable hdcp if it's desired */
3219 if (conn_state->content_protection ==
3220 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3221 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3222}
3223
33f083f0
VS		 3224static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3225 const struct intel_crtc_state *old_crtc_state,
3226 const struct drm_connector_state *old_conn_state)
5ab432ef 3227{
33f083f0 3228 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3229
edb2e530
VS		 3230 intel_dp->link_trained = false;
3231
37255d8d 3232 if (old_crtc_state->has_audio)
8ec47de2
VS		 3233 intel_audio_codec_disable(encoder,
3234 old_crtc_state, old_conn_state);
2831d842 3235
33f083f0
VS		 3236 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3237 intel_psr_disable(intel_dp, old_crtc_state);
3238 intel_edp_backlight_off(old_conn_state);
3239}
15953637 3240
33f083f0
VS		 3241static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3242 const struct intel_crtc_state *old_crtc_state,
3243 const struct drm_connector_state *old_conn_state)
3244{
277ab5ab
VS		 3245 struct drm_connector *connector = old_conn_state->connector;
3246
33f083f0 3247 if (old_crtc_state->has_audio)
8ec47de2
VS		 3248 intel_audio_codec_disable(encoder,
3249 old_crtc_state, old_conn_state);
d6c50ff8 3250
277ab5ab
VS		 3251 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3252 false, false))
3253 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3254 connector->base.id, connector->name);
33f083f0
VS		 3255}
3256
3257static void intel_disable_ddi(struct intel_encoder *encoder,
3258 const struct intel_crtc_state *old_crtc_state,
3259 const struct drm_connector_state *old_conn_state)
3260{
ee5e5e7a
SP		 3261 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3262
33f083f0
VS		 3263 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3264 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3265 else
3266 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3267}
79f689aa 3268
fd6bbda9 3269static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 3270 const struct intel_crtc_state *pipe_config,
3271 const struct drm_connector_state *conn_state)
95a7a2ae 3272{
3dc38eea 3273 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 3274
47a6bc61 3275 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 3276}
3277
ad64217b 3278void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3279{
ad64217b
ACO		 3280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3281 struct drm_i915_private *dev_priv =
3282 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3283 enum port port = intel_dig_port->base.port;
c19b0669 3284 uint32_t val;
f3e227df 3285 bool wait = false;
c19b0669
PZ		 3286
3287 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3288 val = I915_READ(DDI_BUF_CTL(port));
3289 if (val & DDI_BUF_CTL_ENABLE) {
3290 val &= ~DDI_BUF_CTL_ENABLE;
3291 I915_WRITE(DDI_BUF_CTL(port), val);
3292 wait = true;
3293 }
3294
3295 val = I915_READ(DP_TP_CTL(port));
3296 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3297 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3298 I915_WRITE(DP_TP_CTL(port), val);
3299 POSTING_READ(DP_TP_CTL(port));
3300
3301 if (wait)
3302 intel_wait_ddi_buf_idle(dev_priv, port);
3303 }
3304
0e32b39c 3305 val = DP_TP_CTL_ENABLE |
c19b0669 3306 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3307 if (intel_dp->link_mst)
0e32b39c
DA		 3308 val |= DP_TP_CTL_MODE_MST;
3309 else {
3310 val |= DP_TP_CTL_MODE_SST;
3311 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3312 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3313 }
c19b0669
PZ		 3314 I915_WRITE(DP_TP_CTL(port), val);
3315 POSTING_READ(DP_TP_CTL(port));
3316
3317 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3318 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3319 POSTING_READ(DDI_BUF_CTL(port));
3320
3321 udelay(600);
3322}
00c09d70 3323
2085cc5d
VS		 3324static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3325 enum transcoder cpu_transcoder)
9935f7fa 3326{
2085cc5d
VS		 3327 if (cpu_transcoder == TRANSCODER_EDP)
3328 return false;
9935f7fa 3329
2085cc5d
VS		 3330 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3331 return false;
3332
3333 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3334 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3335}
3336
53e9bf5e
VS		 3337void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3338 struct intel_crtc_state *crtc_state)
3339{
3340 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3341 crtc_state->min_voltage_level = 2;
9378985e
PZ		 3342 else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3343 crtc_state->min_voltage_level = 1;
53e9bf5e
VS		 3344}
3345
6801c18c 3346void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3347 struct intel_crtc_state *pipe_config)
045ac3b5 3348{
fac5e23e 3349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3350 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3351 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3352 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3353 u32 temp, flags = 0;
3354
4d1de975
JN		 3355 /* XXX: DSI transcoder paranoia */
3356 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3357 return;
3358
045ac3b5
JB		 3359 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3360 if (temp & TRANS_DDI_PHSYNC)
3361 flags |= DRM_MODE_FLAG_PHSYNC;
3362 else
3363 flags |= DRM_MODE_FLAG_NHSYNC;
3364 if (temp & TRANS_DDI_PVSYNC)
3365 flags |= DRM_MODE_FLAG_PVSYNC;
3366 else
3367 flags |= DRM_MODE_FLAG_NVSYNC;
3368
2d112de7 3369 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3370
3371 switch (temp & TRANS_DDI_BPC_MASK) {
3372 case TRANS_DDI_BPC_6:
3373 pipe_config->pipe_bpp = 18;
3374 break;
3375 case TRANS_DDI_BPC_8:
3376 pipe_config->pipe_bpp = 24;
3377 break;
3378 case TRANS_DDI_BPC_10:
3379 pipe_config->pipe_bpp = 30;
3380 break;
3381 case TRANS_DDI_BPC_12:
3382 pipe_config->pipe_bpp = 36;
3383 break;
3384 default:
3385 break;
3386 }
eb14cb74
VS		 3387
3388 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3389 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3390 pipe_config->has_hdmi_sink = true;
f99be1b3 3391 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3392
f99be1b3 3393 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 3394 pipe_config->has_infoframe = true;
15953637
SS		 3395
3396 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3397 TRANS_DDI_HDMI_SCRAMBLING_MASK)
3398 pipe_config->hdmi_scrambling = true;
3399 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3400 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3401 /* fall through */
eb14cb74 3402 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3403 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3404 pipe_config->lane_count = 4;
3405 break;
eb14cb74 3406 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3407 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3408 break;
3409 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3410 if (encoder->type == INTEL_OUTPUT_EDP)
3411 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3412 else
3413 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3414 pipe_config->lane_count =
3415 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3416 intel_dp_get_m_n(intel_crtc, pipe_config);
3417 break;
eb14cb74 3418 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3419 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3420 pipe_config->lane_count =
3421 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3422 intel_dp_get_m_n(intel_crtc, pipe_config);
3423 break;
3424 default:
3425 break;
3426 }
10214420 3427
9935f7fa 3428 pipe_config->has_audio =
2085cc5d 3429 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3430
6aa23e65
JN		 3431 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3432 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3433 /*
3434 * This is a big fat ugly hack.
3435 *
3436 * Some machines in UEFI boot mode provide us a VBT that has 18
3437 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3438 * unknown we fail to light up. Yet the same BIOS boots up with
3439 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3440 * max, not what it tells us to use.
3441 *
3442 * Note: This will still be broken if the eDP panel is not lit
3443 * up by the BIOS, and thus we can't get the mode at module
3444 * load.
3445 */
3446 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3447 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3448 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3449 }
11578553 3450
22606a18 3451 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3452
cc3f90f0 3453 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3454 pipe_config->lane_lat_optim_mask =
3455 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3456
3457 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
045ac3b5
JB		 3458}
3459
7e732cac
VS		 3460static enum intel_output_type
3461intel_ddi_compute_output_type(struct intel_encoder *encoder,
3462 struct intel_crtc_state *crtc_state,
3463 struct drm_connector_state *conn_state)
3464{
3465 switch (conn_state->connector->connector_type) {
3466 case DRM_MODE_CONNECTOR_HDMIA:
3467 return INTEL_OUTPUT_HDMI;
3468 case DRM_MODE_CONNECTOR_eDP:
3469 return INTEL_OUTPUT_EDP;
3470 case DRM_MODE_CONNECTOR_DisplayPort:
3471 return INTEL_OUTPUT_DP;
3472 default:
3473 MISSING_CASE(conn_state->connector->connector_type);
3474 return INTEL_OUTPUT_UNUSED;
3475 }
3476}
3477
5bfe2ac0 3478static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 3479 struct intel_crtc_state *pipe_config,
3480 struct drm_connector_state *conn_state)
00c09d70 3481{
fac5e23e 3482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3483 enum port port = encoder->port;
95a7a2ae 3484 int ret;
00c09d70 3485
eccb140b
DV		 3486 if (port == PORT_A)
3487 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3488
7e732cac 3489 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3490 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3491 else
0a478c27 3492 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 3493
cc3f90f0 3494 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae 3495 pipe_config->lane_lat_optim_mask =
5161d058 3496 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3497
53e9bf5e
VS		 3498 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3499
95a7a2ae
ID		 3500 return ret;
3501
00c09d70
PZ		 3502}
3503
3504static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 3505 .reset = intel_dp_encoder_reset,
3506 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 3507};
3508
4a28ae58
PZ		 3509static struct intel_connector *
3510intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3511{
3512 struct intel_connector *connector;
8f4f2797 3513 enum port port = intel_dig_port->base.port;
4a28ae58 3514
9bdbd0b9 3515 connector = intel_connector_alloc();
4a28ae58
PZ		 3516 if (!connector)
3517 return NULL;
3518
3519 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3520 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3521 kfree(connector);
3522 return NULL;
3523 }
3524
3525 return connector;
3526}
3527
dba14b27
VS		 3528static int modeset_pipe(struct drm_crtc *crtc,
3529 struct drm_modeset_acquire_ctx *ctx)
3530{
3531 struct drm_atomic_state *state;
3532 struct drm_crtc_state *crtc_state;
3533 int ret;
3534
3535 state = drm_atomic_state_alloc(crtc->dev);
3536 if (!state)
3537 return -ENOMEM;
3538
3539 state->acquire_ctx = ctx;
3540
3541 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3542 if (IS_ERR(crtc_state)) {
3543 ret = PTR_ERR(crtc_state);
3544 goto out;
3545 }
3546
3547 crtc_state->mode_changed = true;
3548
3549 ret = drm_atomic_add_affected_connectors(state, crtc);
3550 if (ret)
3551 goto out;
3552
3553 ret = drm_atomic_add_affected_planes(state, crtc);
3554 if (ret)
3555 goto out;
3556
3557 ret = drm_atomic_commit(state);
3558 if (ret)
3559 goto out;
3560
3561 return 0;
3562
3563 out:
3564 drm_atomic_state_put(state);
3565
3566 return ret;
3567}
3568
3569static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3570 struct drm_modeset_acquire_ctx *ctx)
3571{
3572 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3573 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3574 struct intel_connector *connector = hdmi->attached_connector;
3575 struct i2c_adapter *adapter =
3576 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3577 struct drm_connector_state *conn_state;
3578 struct intel_crtc_state *crtc_state;
3579 struct intel_crtc *crtc;
3580 u8 config;
3581 int ret;
3582
3583 if (!connector || connector->base.status != connector_status_connected)
3584 return 0;
3585
3586 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3587 ctx);
3588 if (ret)
3589 return ret;
3590
3591 conn_state = connector->base.state;
3592
3593 crtc = to_intel_crtc(conn_state->crtc);
3594 if (!crtc)
3595 return 0;
3596
3597 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3598 if (ret)
3599 return ret;
3600
3601 crtc_state = to_intel_crtc_state(crtc->base.state);
3602
3603 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3604
3605 if (!crtc_state->base.active)
3606 return 0;
3607
3608 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3609 !crtc_state->hdmi_scrambling)
3610 return 0;
3611
3612 if (conn_state->commit &&
3613 !try_wait_for_completion(&conn_state->commit->hw_done))
3614 return 0;
3615
3616 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3617 if (ret < 0) {
3618 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3619 return 0;
3620 }
3621
3622 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3623 crtc_state->hdmi_high_tmds_clock_ratio &&
3624 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3625 crtc_state->hdmi_scrambling)
3626 return 0;
3627
3628 /*
3629 * HDMI 2.0 says that one should not send scrambled data
3630 * prior to configuring the sink scrambling, and that
3631 * TMDS clock/data transmission should be suspended when
3632 * changing the TMDS clock rate in the sink. So let's
3633 * just do a full modeset here, even though some sinks
3634 * would be perfectly happy if were to just reconfigure
3635 * the SCDC settings on the fly.
3636 */
3637 return modeset_pipe(&crtc->base, ctx);
3638}
3639
3640static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3641 struct intel_connector *connector)
3642{
3643 struct drm_modeset_acquire_ctx ctx;
3644 bool changed;
3645 int ret;
3646
3647 changed = intel_encoder_hotplug(encoder, connector);
3648
3649 drm_modeset_acquire_init(&ctx, 0);
3650
3651 for (;;) {
c85d200e
VS		 3652 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3653 ret = intel_hdmi_reset_link(encoder, &ctx);
3654 else
3655 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 3656
3657 if (ret == -EDEADLK) {
3658 drm_modeset_backoff(&ctx);
3659 continue;
3660 }
3661
3662 break;
3663 }
3664
3665 drm_modeset_drop_locks(&ctx);
3666 drm_modeset_acquire_fini(&ctx);
3667 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3668
3669 return changed;
3670}
3671
4a28ae58
PZ		 3672static struct intel_connector *
3673intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3674{
3675 struct intel_connector *connector;
8f4f2797 3676 enum port port = intel_dig_port->base.port;
4a28ae58 3677
9bdbd0b9 3678 connector = intel_connector_alloc();
4a28ae58
PZ		 3679 if (!connector)
3680 return NULL;
3681
3682 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3683 intel_hdmi_init_connector(intel_dig_port, connector);
3684
3685 return connector;
3686}
3687
436009b5
RV		 3688static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3689{
3690 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3691
8f4f2797 3692 if (dport->base.port != PORT_A)
436009b5
RV		 3693 return false;
3694
3695 if (dport->saved_port_bits & DDI_A_4_LANES)
3696 return false;
3697
3698 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3699 * supported configuration
3700 */
3701 if (IS_GEN9_LP(dev_priv))
3702 return true;
3703
3704 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3705 * one who does also have a full A/E split called
3706 * DDI_F what makes DDI_E useless. However for this
3707 * case let's trust VBT info.
3708 */
3709 if (IS_CANNONLAKE(dev_priv) &&
3710 !intel_bios_is_port_present(dev_priv, PORT_E))
3711 return true;
3712
3713 return false;
3714}
3715
3d2011cf
MK		 3716static int
3717intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3718{
3719 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3720 enum port port = intel_dport->base.port;
3721 int max_lanes = 4;
3722
3723 if (INTEL_GEN(dev_priv) >= 11)
3724 return max_lanes;
3725
3726 if (port == PORT_A || port == PORT_E) {
3727 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3728 max_lanes = port == PORT_A ? 4 : 0;
3729 else
3730 /* Both A and E share 2 lanes */
3731 max_lanes = 2;
3732 }
3733
3734 /*
3735 * Some BIOS might fail to set this bit on port A if eDP
3736 * wasn't lit up at boot. Force this bit set when needed
3737 * so we use the proper lane count for our calculations.
3738 */
3739 if (intel_ddi_a_force_4_lanes(intel_dport)) {
3740 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3741 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3742 max_lanes = 4;
3743 }
3744
3745 return max_lanes;
3746}
3747
c39055b0 3748void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 3749{
3750 struct intel_digital_port *intel_dig_port;
3751 struct intel_encoder *intel_encoder;
3752 struct drm_encoder *encoder;
ff662124 3753 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3 3754
311a2094
PZ		 3755
3756 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3757 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3758 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 3759
3760 if (intel_bios_is_lspcon_present(dev_priv, port)) {
3761 /*
3762 * Lspcon device needs to be driven with DP connector
3763 * with special detection sequence. So make sure DP
3764 * is initialized before lspcon.
3765 */
3766 init_dp = true;
3767 init_lspcon = true;
3768 init_hdmi = false;
3769 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3770 }
3771
311a2094 3772 if (!init_dp && !init_hdmi) {
500ea70d 3773 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3774 port_name(port));
500ea70d 3775 return;
311a2094 3776 }
00c09d70 3777
b14c5679 3778 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3779 if (!intel_dig_port)
3780 return;
3781
00c09d70
PZ		 3782 intel_encoder = &intel_dig_port->base;
3783 encoder = &intel_encoder->base;
3784
c39055b0 3785 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 3786 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 3787
c85d200e 3788 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 3789 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 3790 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 3791 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 3792 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3793 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 3794 intel_encoder->pre_enable = intel_ddi_pre_enable;
3795 intel_encoder->disable = intel_disable_ddi;
3796 intel_encoder->post_disable = intel_ddi_post_disable;
3797 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3798 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 3799 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 3800 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 3801 intel_encoder->type = INTEL_OUTPUT_DDI;
3802 intel_encoder->power_domain = intel_port_to_power_domain(port);
3803 intel_encoder->port = port;
3804 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3805 intel_encoder->cloneable = 0;
00c09d70 3806
1e6aa7e5
JN		 3807 if (INTEL_GEN(dev_priv) >= 11)
3808 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3809 DDI_BUF_PORT_REVERSAL;
3810 else
3811 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3812 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 3813 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3814 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
00c09d70 3815
62b69566
ACO		 3816 switch (port) {
3817 case PORT_A:
3818 intel_dig_port->ddi_io_power_domain =
3819 POWER_DOMAIN_PORT_DDI_A_IO;
3820 break;
3821 case PORT_B:
3822 intel_dig_port->ddi_io_power_domain =
3823 POWER_DOMAIN_PORT_DDI_B_IO;
3824 break;
3825 case PORT_C:
3826 intel_dig_port->ddi_io_power_domain =
3827 POWER_DOMAIN_PORT_DDI_C_IO;
3828 break;
3829 case PORT_D:
3830 intel_dig_port->ddi_io_power_domain =
3831 POWER_DOMAIN_PORT_DDI_D_IO;
3832 break;
3833 case PORT_E:
3834 intel_dig_port->ddi_io_power_domain =
3835 POWER_DOMAIN_PORT_DDI_E_IO;
3836 break;
9787e835
RV		 3837 case PORT_F:
3838 intel_dig_port->ddi_io_power_domain =
3839 POWER_DOMAIN_PORT_DDI_F_IO;
3840 break;
62b69566
ACO		 3841 default:
3842 MISSING_CASE(port);
3843 }
3844
385e4de0
VS		 3845 intel_infoframe_init(intel_dig_port);
3846
f68d697e
CW		 3847 if (init_dp) {
3848 if (!intel_ddi_init_dp_connector(intel_dig_port))
3849 goto err;
13cf5504 3850
f68d697e 3851 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 3852 }
21a8e6a4 3853
311a2094
PZ		 3854 /* In theory we don't need the encoder->type check, but leave it just in
3855 * case we have some really bad VBTs... */
f68d697e
CW		 3856 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3857 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3858 goto err;
21a8e6a4 3859 }
f68d697e 3860
ff662124
SS		 3861 if (init_lspcon) {
3862 if (lspcon_init(intel_dig_port))
3863 /* TODO: handle hdmi info frame part */
3864 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3865 port_name(port));
3866 else
3867 /*
3868 * LSPCON init faied, but DP init was success, so
3869 * lets try to drive as DP++ port.
3870 */
3871 DRM_ERROR("LSPCON init failed on port %c\n",
3872 port_name(port));
3873 }
3874
f68d697e
CW		 3875 return;
3876
3877err:
3878 drm_encoder_cleanup(encoder);
3879 kfree(intel_dig_port);
00c09d70 3880}
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