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drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
45244b87
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
31
10122051
JN		 32struct ddi_buf_trans {
33 u32 trans1; /* balance leg enable, de-emph level */
34 u32 trans2; /* vref sel, vswing */
f8896f5d 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 36};
37
97eeb872
VS		 38static const u8 index_to_dp_signal_levels[] = {
39 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
40 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
41 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
42 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
43 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
44 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
45 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
46 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
47 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
48 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
49};
50
45244b87
ED		 51/* HDMI/DVI modes ignore everything but the last 2 items. So we share
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
54 */
10122051 55static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 56 { 0x00FFFFFF, 0x0006000E, 0x0 },
57 { 0x00D75FFF, 0x0005000A, 0x0 },
58 { 0x00C30FFF, 0x00040006, 0x0 },
59 { 0x80AAAFFF, 0x000B0000, 0x0 },
60 { 0x00FFFFFF, 0x0005000A, 0x0 },
61 { 0x00D75FFF, 0x000C0004, 0x0 },
62 { 0x80C30FFF, 0x000B0000, 0x0 },
63 { 0x00FFFFFF, 0x00040006, 0x0 },
64 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 65};
66
10122051 67static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 68 { 0x00FFFFFF, 0x0007000E, 0x0 },
69 { 0x00D75FFF, 0x000F000A, 0x0 },
70 { 0x00C30FFF, 0x00060006, 0x0 },
71 { 0x00AAAFFF, 0x001E0000, 0x0 },
72 { 0x00FFFFFF, 0x000F000A, 0x0 },
73 { 0x00D75FFF, 0x00160004, 0x0 },
74 { 0x00C30FFF, 0x001E0000, 0x0 },
75 { 0x00FFFFFF, 0x00060006, 0x0 },
76 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 77};
78
10122051
JN		 79static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
80 /* Idx NT mV d T mV d db */
f8896f5d
DW		 81 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
82 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
83 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
84 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
85 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
86 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
87 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
88 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
89 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
90 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
91 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
92 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 93};
94
10122051 95static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 96 { 0x00FFFFFF, 0x00000012, 0x0 },
97 { 0x00EBAFFF, 0x00020011, 0x0 },
98 { 0x00C71FFF, 0x0006000F, 0x0 },
99 { 0x00AAAFFF, 0x000E000A, 0x0 },
100 { 0x00FFFFFF, 0x00020011, 0x0 },
101 { 0x00DB6FFF, 0x0005000F, 0x0 },
102 { 0x00BEEFFF, 0x000A000C, 0x0 },
103 { 0x00FFFFFF, 0x0005000F, 0x0 },
104 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 105};
106
10122051 107static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 108 { 0x00FFFFFF, 0x0007000E, 0x0 },
109 { 0x00D75FFF, 0x000E000A, 0x0 },
110 { 0x00BEFFFF, 0x00140006, 0x0 },
111 { 0x80B2CFFF, 0x001B0002, 0x0 },
112 { 0x00FFFFFF, 0x000E000A, 0x0 },
113 { 0x00DB6FFF, 0x00160005, 0x0 },
114 { 0x80C71FFF, 0x001A0002, 0x0 },
115 { 0x00F7DFFF, 0x00180004, 0x0 },
116 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 117};
118
10122051 119static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 120 { 0x00FFFFFF, 0x0001000E, 0x0 },
121 { 0x00D75FFF, 0x0004000A, 0x0 },
122 { 0x00C30FFF, 0x00070006, 0x0 },
123 { 0x00AAAFFF, 0x000C0000, 0x0 },
124 { 0x00FFFFFF, 0x0004000A, 0x0 },
125 { 0x00D75FFF, 0x00090004, 0x0 },
126 { 0x00C30FFF, 0x000C0000, 0x0 },
127 { 0x00FFFFFF, 0x00070006, 0x0 },
128 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 129};
130
10122051
JN		 131static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
132 /* Idx NT mV d T mV df db */
f8896f5d
DW		 133 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
134 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
135 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
136 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
137 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
138 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
139 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
140 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
141 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
142 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 143};
144
5f8b2531 145/* Skylake H and S */
7f88e3af 146static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
d7097cff 150 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
d7097cff 153 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 154 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 155 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 156};
157
f8896f5d
DW		 158/* Skylake U */
159static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 160 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 161 { 0x00005012, 0x00000088, 0x0 },
5ac90567 162 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 163 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 164 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 165 { 0x80005012, 0x000000C0, 0x1 },
166 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 167 { 0x00002016, 0x00000088, 0x0 },
d7097cff 168 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 169};
170
5f8b2531
RV		 171/* Skylake Y */
172static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 173 { 0x00000018, 0x000000A2, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
5ac90567 175 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 176 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 177 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 180 { 0x00000018, 0x00000088, 0x0 },
d7097cff 181 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 182};
183
0fdd4918
RV		 184/* Kabylake H and S */
185static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
186 { 0x00002016, 0x000000A0, 0x0 },
187 { 0x00005012, 0x0000009B, 0x0 },
188 { 0x00007011, 0x00000088, 0x0 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x00002016, 0x0000009B, 0x0 },
191 { 0x00005012, 0x00000088, 0x0 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000097, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
195};
196
197/* Kabylake U */
198static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
199 { 0x0000201B, 0x000000A1, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x0000201B, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00002016, 0x0000004F, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
208};
209
210/* Kabylake Y */
211static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
212 { 0x00001017, 0x000000A1, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000CD, 0x3 },
215 { 0x8000800F, 0x000000C0, 0x3 },
216 { 0x00001017, 0x0000009D, 0x0 },
217 { 0x80005012, 0x000000C0, 0x3 },
218 { 0x80007011, 0x000000C0, 0x3 },
219 { 0x00001017, 0x0000004C, 0x0 },
220 { 0x80005012, 0x000000C0, 0x3 },
221};
222
f8896f5d 223/*
0fdd4918 224 * Skylake/Kabylake H and S
f8896f5d
DW		 225 * eDP 1.4 low vswing translation parameters
226 */
7ad14a29 227static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 228 { 0x00000018, 0x000000A8, 0x0 },
229 { 0x00004013, 0x000000A9, 0x0 },
230 { 0x00007011, 0x000000A2, 0x0 },
231 { 0x00009010, 0x0000009C, 0x0 },
232 { 0x00000018, 0x000000A9, 0x0 },
233 { 0x00006013, 0x000000A2, 0x0 },
234 { 0x00007011, 0x000000A6, 0x0 },
235 { 0x00000018, 0x000000AB, 0x0 },
236 { 0x00007013, 0x0000009F, 0x0 },
237 { 0x00000018, 0x000000DF, 0x0 },
238};
239
240/*
0fdd4918 241 * Skylake/Kabylake U
f8896f5d
DW		 242 * eDP 1.4 low vswing translation parameters
243 */
244static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
245 { 0x00000018, 0x000000A8, 0x0 },
246 { 0x00004013, 0x000000A9, 0x0 },
247 { 0x00007011, 0x000000A2, 0x0 },
248 { 0x00009010, 0x0000009C, 0x0 },
249 { 0x00000018, 0x000000A9, 0x0 },
250 { 0x00006013, 0x000000A2, 0x0 },
251 { 0x00007011, 0x000000A6, 0x0 },
252 { 0x00002016, 0x000000AB, 0x0 },
253 { 0x00005013, 0x0000009F, 0x0 },
254 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 255};
256
f8896f5d 257/*
0fdd4918 258 * Skylake/Kabylake Y
f8896f5d
DW		 259 * eDP 1.4 low vswing translation parameters
260 */
5f8b2531 261static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 262 { 0x00000018, 0x000000A8, 0x0 },
263 { 0x00004013, 0x000000AB, 0x0 },
264 { 0x00007011, 0x000000A4, 0x0 },
265 { 0x00009010, 0x000000DF, 0x0 },
266 { 0x00000018, 0x000000AA, 0x0 },
267 { 0x00006013, 0x000000A4, 0x0 },
268 { 0x00007011, 0x0000009D, 0x0 },
269 { 0x00000018, 0x000000A0, 0x0 },
270 { 0x00006012, 0x000000DF, 0x0 },
271 { 0x00000018, 0x0000008A, 0x0 },
272};
7ad14a29 273
0fdd4918 274/* Skylake/Kabylake U, H and S */
7f88e3af 275static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 276 { 0x00000018, 0x000000AC, 0x0 },
277 { 0x00005012, 0x0000009D, 0x0 },
278 { 0x00007011, 0x00000088, 0x0 },
279 { 0x00000018, 0x000000A1, 0x0 },
280 { 0x00000018, 0x00000098, 0x0 },
281 { 0x00004013, 0x00000088, 0x0 },
2e78416e 282 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 283 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 284 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
285 { 0x80003015, 0x000000C0, 0x1 },
286 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 287};
288
0fdd4918 289/* Skylake/Kabylake Y */
5f8b2531 290static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 293 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 294 { 0x00000018, 0x000000A4, 0x0 },
295 { 0x00000018, 0x0000009D, 0x0 },
296 { 0x00004013, 0x00000080, 0x0 },
2e78416e 297 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 298 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 299 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
300 { 0x80003015, 0x000000C0, 0x3 },
301 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 302};
303
96fb9f9b 304struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 305 u8 margin; /* swing value */
306 u8 scale; /* scale value */
307 u8 enable; /* scale enable */
308 u8 deemphasis;
96fb9f9b
VK		 309};
310
96fb9f9b
VK		 311static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
043eaf36
VS		 313 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 323};
324
d9d7000d
SJ		 325static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
043eaf36
VS		 327 { 26, 0, 0, 128, }, /* 0: 200 0 */
328 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, }, /* 2: 200 4 */
330 { 54, 0, 0, 69, }, /* 3: 200 6 */
331 { 32, 0, 0, 128, }, /* 4: 250 0 */
332 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, }, /* 6: 250 4 */
334 { 43, 0, 0, 128, }, /* 7: 300 0 */
335 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 337};
338
96fb9f9b
VK		 339/* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
043eaf36
VS		 344 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 354};
355
83fb7ab4 356struct cnl_ddi_buf_trans {
fb5f4e96
VS		 357 u8 dw2_swing_sel;
358 u8 dw7_n_scalar;
359 u8 dw4_cursor_coeff;
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
83fb7ab4
RV		 362};
363
364/* Voltage Swing Programming for VccIO 0.85V for DP */
365static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377};
378
379/* Voltage Swing Programming for VccIO 0.85V for HDMI */
380static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389};
390
391/* Voltage Swing Programming for VccIO 0.85V for eDP */
392static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403};
404
405/* Voltage Swing Programming for VccIO 0.95V for DP */
406static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418};
419
420/* Voltage Swing Programming for VccIO 0.95V for HDMI */
421static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434};
435
436/* Voltage Swing Programming for VccIO 0.95V for eDP */
437static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449};
450
451/* Voltage Swing Programming for VccIO 1.05V for DP */
452static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464};
465
466/* Voltage Swing Programming for VccIO 1.05V for HDMI */
467static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480};
481
482/* Voltage Swing Programming for VccIO 1.05V for eDP */
483static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494};
495
a930acd9
VS		 496static const struct ddi_buf_trans *
497bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
498{
499 if (dev_priv->vbt.edp.low_vswing) {
500 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
501 return bdw_ddi_translations_edp;
502 } else {
503 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
504 return bdw_ddi_translations_dp;
505 }
506}
507
acee2998 508static const struct ddi_buf_trans *
78ab0bae 509skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 510{
0fdd4918 511 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 512 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 513 return skl_y_ddi_translations_dp;
0fdd4918 514 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 515 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 516 return skl_u_ddi_translations_dp;
f8896f5d 517 } else {
f8896f5d 518 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 519 return skl_ddi_translations_dp;
f8896f5d 520 }
f8896f5d
DW		 521}
522
0fdd4918
RV		 523static const struct ddi_buf_trans *
524kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
525{
526 if (IS_KBL_ULX(dev_priv)) {
527 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
528 return kbl_y_ddi_translations_dp;
da411a48 529 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 530 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
531 return kbl_u_ddi_translations_dp;
532 } else {
533 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
534 return kbl_ddi_translations_dp;
535 }
536}
537
acee2998 538static const struct ddi_buf_trans *
78ab0bae 539skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 540{
06411f08 541 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 542 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 543 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 544 return skl_y_ddi_translations_edp;
da411a48
RV		 545 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
546 IS_CFL_ULT(dev_priv)) {
f8896f5d 547 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 548 return skl_u_ddi_translations_edp;
f8896f5d 549 } else {
f8896f5d 550 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 551 return skl_ddi_translations_edp;
f8896f5d
DW		 552 }
553 }
cd1101cb 554
da411a48 555 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 556 return kbl_get_buf_trans_dp(dev_priv, n_entries);
557 else
558 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 559}
560
561static const struct ddi_buf_trans *
78ab0bae 562skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 563{
78ab0bae 564 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 565 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 566 return skl_y_ddi_translations_hdmi;
f8896f5d 567 } else {
f8896f5d 568 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 569 return skl_ddi_translations_hdmi;
f8896f5d 570 }
f8896f5d
DW		 571}
572
edba48fd
VS		 573static int skl_buf_trans_num_entries(enum port port, int n_entries)
574{
575 /* Only DDIA and DDIE can select the 10th register with DP */
576 if (port == PORT_A || port == PORT_E)
577 return min(n_entries, 10);
578 else
579 return min(n_entries, 9);
580}
581
d8fe2c7f
VS		 582static const struct ddi_buf_trans *
583intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 584 enum port port, int *n_entries)
d8fe2c7f
VS		 585{
586 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 587 const struct ddi_buf_trans *ddi_translations =
588 kbl_get_buf_trans_dp(dev_priv, n_entries);
589 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
590 return ddi_translations;
d8fe2c7f 591 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 592 const struct ddi_buf_trans *ddi_translations =
593 skl_get_buf_trans_dp(dev_priv, n_entries);
594 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
595 return ddi_translations;
d8fe2c7f
VS		 596 } else if (IS_BROADWELL(dev_priv)) {
597 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
598 return bdw_ddi_translations_dp;
599 } else if (IS_HASWELL(dev_priv)) {
600 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
601 return hsw_ddi_translations_dp;
602 }
603
604 *n_entries = 0;
605 return NULL;
606}
607
608static const struct ddi_buf_trans *
609intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 610 enum port port, int *n_entries)
d8fe2c7f
VS		 611{
612 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 613 const struct ddi_buf_trans *ddi_translations =
614 skl_get_buf_trans_edp(dev_priv, n_entries);
615 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
616 return ddi_translations;
d8fe2c7f
VS		 617 } else if (IS_BROADWELL(dev_priv)) {
618 return bdw_get_buf_trans_edp(dev_priv, n_entries);
619 } else if (IS_HASWELL(dev_priv)) {
620 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
621 return hsw_ddi_translations_dp;
622 }
623
624 *n_entries = 0;
625 return NULL;
626}
627
628static const struct ddi_buf_trans *
629intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
630 int *n_entries)
631{
632 if (IS_BROADWELL(dev_priv)) {
633 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
634 return bdw_ddi_translations_fdi;
635 } else if (IS_HASWELL(dev_priv)) {
636 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
637 return hsw_ddi_translations_fdi;
638 }
639
640 *n_entries = 0;
641 return NULL;
642}
643
975786ee
VS		 644static const struct ddi_buf_trans *
645intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
646 int *n_entries)
647{
648 if (IS_GEN9_BC(dev_priv)) {
649 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
650 } else if (IS_BROADWELL(dev_priv)) {
651 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
652 return bdw_ddi_translations_hdmi;
653 } else if (IS_HASWELL(dev_priv)) {
654 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
655 return hsw_ddi_translations_hdmi;
656 }
657
658 *n_entries = 0;
659 return NULL;
660}
661
7d4f37b5
VS		 662static const struct bxt_ddi_buf_trans *
663bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
664{
665 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
666 return bxt_ddi_translations_dp;
667}
668
669static const struct bxt_ddi_buf_trans *
670bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
671{
672 if (dev_priv->vbt.edp.low_vswing) {
673 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
674 return bxt_ddi_translations_edp;
675 }
676
677 return bxt_get_buf_trans_dp(dev_priv, n_entries);
678}
679
680static const struct bxt_ddi_buf_trans *
681bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
682{
683 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
684 return bxt_ddi_translations_hdmi;
685}
686
cf3e0fb4
RV		 687static const struct cnl_ddi_buf_trans *
688cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
689{
690 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
691
692 if (voltage == VOLTAGE_INFO_0_85V) {
693 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
694 return cnl_ddi_translations_hdmi_0_85V;
695 } else if (voltage == VOLTAGE_INFO_0_95V) {
696 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
697 return cnl_ddi_translations_hdmi_0_95V;
698 } else if (voltage == VOLTAGE_INFO_1_05V) {
699 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
700 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 701 } else {
702 *n_entries = 1; /* shut up gcc */
cf3e0fb4 703 MISSING_CASE(voltage);
83482ca3 704 }
cf3e0fb4
RV		 705 return NULL;
706}
707
708static const struct cnl_ddi_buf_trans *
709cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
710{
711 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
712
713 if (voltage == VOLTAGE_INFO_0_85V) {
714 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
715 return cnl_ddi_translations_dp_0_85V;
716 } else if (voltage == VOLTAGE_INFO_0_95V) {
717 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
718 return cnl_ddi_translations_dp_0_95V;
719 } else if (voltage == VOLTAGE_INFO_1_05V) {
720 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
721 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 722 } else {
723 *n_entries = 1; /* shut up gcc */
cf3e0fb4 724 MISSING_CASE(voltage);
83482ca3 725 }
cf3e0fb4
RV		 726 return NULL;
727}
728
729static const struct cnl_ddi_buf_trans *
730cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
731{
732 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
733
734 if (dev_priv->vbt.edp.low_vswing) {
735 if (voltage == VOLTAGE_INFO_0_85V) {
736 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
737 return cnl_ddi_translations_edp_0_85V;
738 } else if (voltage == VOLTAGE_INFO_0_95V) {
739 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
740 return cnl_ddi_translations_edp_0_95V;
741 } else if (voltage == VOLTAGE_INFO_1_05V) {
742 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
743 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 744 } else {
745 *n_entries = 1; /* shut up gcc */
cf3e0fb4 746 MISSING_CASE(voltage);
83482ca3 747 }
cf3e0fb4
RV		 748 return NULL;
749 } else {
750 return cnl_get_buf_trans_dp(dev_priv, n_entries);
751 }
752}
753
8d8bb85e
VS		 754static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
755{
d02ace87 756 int n_entries, level, default_entry;
8d8bb85e 757
d02ace87 758 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 759
bf503556 760 if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 761 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
762 default_entry = n_entries - 1;
043eaf36 763 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 764 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
765 default_entry = n_entries - 1;
bf503556 766 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 767 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
768 default_entry = 8;
8d8bb85e 769 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 770 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
771 default_entry = 7;
8d8bb85e 772 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 773 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
774 default_entry = 6;
8d8bb85e
VS		 775 } else {
776 WARN(1, "ddi translation table missing\n");
975786ee 777 return 0;
8d8bb85e
VS		 778 }
779
780 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 781 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
782 level = default_entry;
8d8bb85e 783
d02ace87 784 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 785 return 0;
d02ace87
VS		 786 if (WARN_ON_ONCE(level >= n_entries))
787 level = n_entries - 1;
21b39d2a 788
d02ace87 789 return level;
8d8bb85e
VS		 790}
791
e58623cb
AR		 792/*
793 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 794 * values in advance. This function programs the correct values for
795 * DP/eDP/FDI use cases.
45244b87 796 */
3a6d84e6
VS		 797static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
798 const struct intel_crtc_state *crtc_state)
45244b87 799{
6a7e4f99 800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 801 u32 iboost_bit = 0;
7d1c42e6 802 int i, n_entries;
0fce04c8 803 enum port port = encoder->port;
10122051 804 const struct ddi_buf_trans *ddi_translations;
e58623cb 805
3a6d84e6
VS		 806 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
807 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
808 &n_entries);
809 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 810 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 811 &n_entries);
3a6d84e6 812 else
edba48fd 813 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 814 &n_entries);
e58623cb 815
edba48fd
VS		 816 /* If we're boosting the current, set bit 31 of trans1 */
817 if (IS_GEN9_BC(dev_priv) &&
818 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
819 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 820
7d1c42e6 821 for (i = 0; i < n_entries; i++) {
9712e688
VS		 822 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
823 ddi_translations[i].trans1 | iboost_bit);
824 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
825 ddi_translations[i].trans2);
45244b87 826 }
32bdc400
VS		 827}
828
829/*
830 * Starting with Haswell, DDI port buffers must be programmed with correct
831 * values in advance. This function programs the correct values for
832 * HDMI/DVI use cases.
833 */
7ea79333 834static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 835 int level)
32bdc400
VS		 836{
837 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
838 u32 iboost_bit = 0;
d02ace87 839 int n_entries;
0fce04c8 840 enum port port = encoder->port;
d02ace87 841 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 842
d02ace87 843 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 844
d02ace87 845 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 846 return;
d02ace87
VS		 847 if (WARN_ON_ONCE(level >= n_entries))
848 level = n_entries - 1;
21b39d2a 849
975786ee
VS		 850 /* If we're boosting the current, set bit 31 of trans1 */
851 if (IS_GEN9_BC(dev_priv) &&
852 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
853 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 854
6acab15a 855 /* Entry 9 is for HDMI: */
ed9c77d2 856 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 857 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 858 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 859 ddi_translations[level].trans2);
45244b87
ED		 860}
861
248138b5
PZ		 862static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
863 enum port port)
864{
f0f59a00 865 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 866 int i;
867
3449ca85 868 for (i = 0; i < 16; i++) {
248138b5
PZ		 869 udelay(1);
870 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
871 return;
872 }
873 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
874}
c82e4d26 875
5f88a9c6 876static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a
ACO		 877{
878 switch (pll->id) {
879 case DPLL_ID_WRPLL1:
880 return PORT_CLK_SEL_WRPLL1;
881 case DPLL_ID_WRPLL2:
882 return PORT_CLK_SEL_WRPLL2;
883 case DPLL_ID_SPLL:
884 return PORT_CLK_SEL_SPLL;
885 case DPLL_ID_LCPLL_810:
886 return PORT_CLK_SEL_LCPLL_810;
887 case DPLL_ID_LCPLL_1350:
888 return PORT_CLK_SEL_LCPLL_1350;
889 case DPLL_ID_LCPLL_2700:
890 return PORT_CLK_SEL_LCPLL_2700;
891 default:
892 MISSING_CASE(pll->id);
893 return PORT_CLK_SEL_NONE;
894 }
895}
896
c82e4d26
ED		 897/* Starting with Haswell, different DDI ports can work in FDI mode for
898 * connection to the PCH-located connectors. For this, it is necessary to train
899 * both the DDI port and PCH receiver for the desired DDI buffer settings.
900 *
901 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
902 * please note that when FDI mode is active on DDI E, it shares 2 lines with
903 * DDI A (which is used for eDP)
904 */
905
dc4a1094
ACO		 906void hsw_fdi_link_train(struct intel_crtc *crtc,
907 const struct intel_crtc_state *crtc_state)
c82e4d26 908{
4cbe4b2b 909 struct drm_device *dev = crtc->base.dev;
fac5e23e 910 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 911 struct intel_encoder *encoder;
c856052a 912 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 913
4cbe4b2b 914 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 915 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 916 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 917 }
918
04945641
PZ		 919 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
920 * mode set "sequence for CRT port" document:
921 * - TP1 to TP2 time with the default value
922 * - FDI delay to 90h
8693a824
DL		 923 *
924 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 925 */
eede3b53 926 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 927 FDI_RX_PWRDN_LANE0_VAL(2) |
928 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
929
930 /* Enable the PCH Receiver FDI PLL */
3e68320e 931 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 932 FDI_RX_PLL_ENABLE |
dc4a1094 933 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 934 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
935 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 936 udelay(220);
937
938 /* Switch from Rawclk to PCDclk */
939 rx_ctl_val |= FDI_PCDCLK;
eede3b53 940 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 941
942 /* Configure Port Clock Select */
dc4a1094 943 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 944 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
945 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 946
947 /* Start the training iterating through available voltages and emphasis,
948 * testing each value twice. */
10122051 949 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 950 /* Configure DP_TP_CTL with auto-training */
951 I915_WRITE(DP_TP_CTL(PORT_E),
952 DP_TP_CTL_FDI_AUTOTRAIN |
953 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
954 DP_TP_CTL_LINK_TRAIN_PAT1 |
955 DP_TP_CTL_ENABLE);
956
876a8cdf
DL		 957 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
958 * DDI E does not support port reversal, the functionality is
959 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
960 * port reversal bit */
c82e4d26 961 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 962 DDI_BUF_CTL_ENABLE |
dc4a1094 963 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 964 DDI_BUF_TRANS_SELECT(i / 2));
04945641 965 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 966
967 udelay(600);
968
04945641 969 /* Program PCH FDI Receiver TU */
eede3b53 970 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 971
972 /* Enable PCH FDI Receiver with auto-training */
973 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 974 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
975 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 976
977 /* Wait for FDI receiver lane calibration */
978 udelay(30);
979
980 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 981 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 982 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 983 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
984 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 985
986 /* Wait for FDI auto training time */
987 udelay(5);
c82e4d26
ED		 988
989 temp = I915_READ(DP_TP_STATUS(PORT_E));
990 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 991 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 992 break;
993 }
c82e4d26 994
a308ccb3
VS		 995 /*
996 * Leave things enabled even if we failed to train FDI.
997 * Results in less fireworks from the state checker.
998 */
999 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1000 DRM_ERROR("FDI link training failed!\n");
1001 break;
c82e4d26 1002 }
04945641 1003
5b421c57
VS		 1004 rx_ctl_val &= ~FDI_RX_ENABLE;
1005 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1006 POSTING_READ(FDI_RX_CTL(PIPE_A));
1007
248138b5
PZ		 1008 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1009 temp &= ~DDI_BUF_CTL_ENABLE;
1010 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1011 POSTING_READ(DDI_BUF_CTL(PORT_E));
1012
04945641 1013 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1014 temp = I915_READ(DP_TP_CTL(PORT_E));
1015 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1016 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1017 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1018 POSTING_READ(DP_TP_CTL(PORT_E));
1019
1020 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1021
04945641 1022 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1023 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1024 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1025 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1026 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1027 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1028 }
1029
a308ccb3
VS		 1030 /* Enable normal pixel sending for FDI */
1031 I915_WRITE(DP_TP_CTL(PORT_E),
1032 DP_TP_CTL_FDI_AUTOTRAIN |
1033 DP_TP_CTL_LINK_TRAIN_NORMAL |
1034 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1035 DP_TP_CTL_ENABLE);
c82e4d26 1036}
0e72a5b5 1037
d7c530b2 1038static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1039{
1040 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1041 struct intel_digital_port *intel_dig_port =
1042 enc_to_dig_port(&encoder->base);
1043
1044 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1045 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1046 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1047}
1048
8d9ddbcb 1049static struct intel_encoder *
e9ce1a62 1050intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1051{
e9ce1a62 1052 struct drm_device *dev = crtc->base.dev;
1524e93e 1053 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1054 int num_encoders = 0;
1055
1524e93e
SS		 1056 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1057 ret = encoder;
8d9ddbcb
PZ		 1058 num_encoders++;
1059 }
1060
1061 if (num_encoders != 1)
84f44ce7 1062 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1063 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1064
1065 BUG_ON(ret == NULL);
1066 return ret;
1067}
1068
44a126ba
PZ		 1069/* Finds the only possible encoder associated with the given CRTC. */
1070struct intel_encoder *
3165c074 1071intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 1072{
3165c074
ACO		 1073 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1074 struct intel_encoder *ret = NULL;
1075 struct drm_atomic_state *state;
da3ced29
ACO		 1076 struct drm_connector *connector;
1077 struct drm_connector_state *connector_state;
d0737e1d 1078 int num_encoders = 0;
3165c074 1079 int i;
d0737e1d 1080
3165c074
ACO		 1081 state = crtc_state->base.state;
1082
b77c7a90 1083 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 1084 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 1085 continue;
1086
da3ced29 1087 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 1088 num_encoders++;
d0737e1d
ACO		 1089 }
1090
1091 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1092 pipe_name(crtc->pipe));
1093
1094 BUG_ON(ret == NULL);
1095 return ret;
1096}
1097
1c0b85c5 1098#define LC_FREQ 2700
1c0b85c5 1099
f0f59a00
VS		 1100static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1101 i915_reg_t reg)
11578553
JB		 1102{
1103 int refclk = LC_FREQ;
1104 int n, p, r;
1105 u32 wrpll;
1106
1107 wrpll = I915_READ(reg);
114fe488
DV		 1108 switch (wrpll & WRPLL_PLL_REF_MASK) {
1109 case WRPLL_PLL_SSC:
1110 case WRPLL_PLL_NON_SSC:
11578553
JB		 1111 /*
1112 * We could calculate spread here, but our checking
1113 * code only cares about 5% accuracy, and spread is a max of
1114 * 0.5% downspread.
1115 */
1116 refclk = 135;
1117 break;
114fe488 1118 case WRPLL_PLL_LCPLL:
11578553
JB		 1119 refclk = LC_FREQ;
1120 break;
1121 default:
1122 WARN(1, "bad wrpll refclk\n");
1123 return 0;
1124 }
1125
1126 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1127 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1128 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1129
20f0ec16
JB		 1130 /* Convert to KHz, p & r have a fixed point portion */
1131 return (refclk * n * 100) / (p * r);
11578553
JB		 1132}
1133
540e732c 1134static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1135 enum intel_dpll_id pll_id)
540e732c 1136{
f0f59a00 1137 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 1138 uint32_t cfgcr1_val, cfgcr2_val;
1139 uint32_t p0, p1, p2, dco_freq;
1140
2952cd6f
RV		 1141 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1142 cfgcr2_reg = DPLL_CFGCR2(pll_id);
540e732c
S		 1143
1144 cfgcr1_val = I915_READ(cfgcr1_reg);
1145 cfgcr2_val = I915_READ(cfgcr2_reg);
1146
1147 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1148 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1149
1150 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1151 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1152 else
1153 p1 = 1;
1154
1155
1156 switch (p0) {
1157 case DPLL_CFGCR2_PDIV_1:
1158 p0 = 1;
1159 break;
1160 case DPLL_CFGCR2_PDIV_2:
1161 p0 = 2;
1162 break;
1163 case DPLL_CFGCR2_PDIV_3:
1164 p0 = 3;
1165 break;
1166 case DPLL_CFGCR2_PDIV_7:
1167 p0 = 7;
1168 break;
1169 }
1170
1171 switch (p2) {
1172 case DPLL_CFGCR2_KDIV_5:
1173 p2 = 5;
1174 break;
1175 case DPLL_CFGCR2_KDIV_2:
1176 p2 = 2;
1177 break;
1178 case DPLL_CFGCR2_KDIV_3:
1179 p2 = 3;
1180 break;
1181 case DPLL_CFGCR2_KDIV_1:
1182 p2 = 1;
1183 break;
1184 }
1185
1186 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1187
1188 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1189 1000) / 0x8000;
1190
1191 return dco_freq / (p0 * p1 * p2 * 5);
1192}
1193
a9701a89 1194static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
2952cd6f 1195 enum intel_dpll_id pll_id)
a9701a89
RV		 1196{
1197 uint32_t cfgcr0, cfgcr1;
1198 uint32_t p0, p1, p2, dco_freq, ref_clock;
1199
1200 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1201 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1202
1203 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1204 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1205
1206 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1207 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1208 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1209 else
1210 p1 = 1;
1211
1212
1213 switch (p0) {
1214 case DPLL_CFGCR1_PDIV_2:
1215 p0 = 2;
1216 break;
1217 case DPLL_CFGCR1_PDIV_3:
1218 p0 = 3;
1219 break;
1220 case DPLL_CFGCR1_PDIV_5:
1221 p0 = 5;
1222 break;
1223 case DPLL_CFGCR1_PDIV_7:
1224 p0 = 7;
1225 break;
1226 }
1227
1228 switch (p2) {
1229 case DPLL_CFGCR1_KDIV_1:
1230 p2 = 1;
1231 break;
1232 case DPLL_CFGCR1_KDIV_2:
1233 p2 = 2;
1234 break;
1235 case DPLL_CFGCR1_KDIV_4:
1236 p2 = 4;
1237 break;
1238 }
1239
1240 ref_clock = dev_priv->cdclk.hw.ref;
1241
1242 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1243
1244 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1245 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1246
0e005888
PZ		 1247 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1248 return 0;
1249
a9701a89
RV		 1250 return dco_freq / (p0 * p1 * p2 * 5);
1251}
1252
398a017e
VS		 1253static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1254{
1255 int dotclock;
1256
1257 if (pipe_config->has_pch_encoder)
1258 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1259 &pipe_config->fdi_m_n);
37a5650b 1260 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1261 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1262 &pipe_config->dp_m_n);
1263 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1264 dotclock = pipe_config->port_clock * 2 / 3;
1265 else
1266 dotclock = pipe_config->port_clock;
1267
b22ca995
SS		 1268 if (pipe_config->ycbcr420)
1269 dotclock *= 2;
1270
398a017e
VS		 1271 if (pipe_config->pixel_multiplier)
1272 dotclock /= pipe_config->pixel_multiplier;
1273
1274 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1275}
540e732c 1276
a9701a89
RV		 1277static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1278 struct intel_crtc_state *pipe_config)
1279{
1280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1281 int link_clock = 0;
2952cd6f
RV		 1282 uint32_t cfgcr0;
1283 enum intel_dpll_id pll_id;
a9701a89
RV		 1284
1285 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1286
1287 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1288
1289 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1290 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1291 } else {
1292 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1293
1294 switch (link_clock) {
1295 case DPLL_CFGCR0_LINK_RATE_810:
1296 link_clock = 81000;
1297 break;
1298 case DPLL_CFGCR0_LINK_RATE_1080:
1299 link_clock = 108000;
1300 break;
1301 case DPLL_CFGCR0_LINK_RATE_1350:
1302 link_clock = 135000;
1303 break;
1304 case DPLL_CFGCR0_LINK_RATE_1620:
1305 link_clock = 162000;
1306 break;
1307 case DPLL_CFGCR0_LINK_RATE_2160:
1308 link_clock = 216000;
1309 break;
1310 case DPLL_CFGCR0_LINK_RATE_2700:
1311 link_clock = 270000;
1312 break;
1313 case DPLL_CFGCR0_LINK_RATE_3240:
1314 link_clock = 324000;
1315 break;
1316 case DPLL_CFGCR0_LINK_RATE_4050:
1317 link_clock = 405000;
1318 break;
1319 default:
1320 WARN(1, "Unsupported link rate\n");
1321 break;
1322 }
1323 link_clock *= 2;
1324 }
1325
1326 pipe_config->port_clock = link_clock;
1327
1328 ddi_dotclock_get(pipe_config);
1329}
1330
540e732c 1331static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1332 struct intel_crtc_state *pipe_config)
540e732c 1333{
fac5e23e 1334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c 1335 int link_clock = 0;
2952cd6f
RV		 1336 uint32_t dpll_ctl1;
1337 enum intel_dpll_id pll_id;
540e732c 1338
2952cd6f 1339 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
540e732c
S		 1340
1341 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1342
2952cd6f
RV		 1343 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1344 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
540e732c 1345 } else {
2952cd6f
RV		 1346 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1347 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
540e732c
S		 1348
1349 switch (link_clock) {
71cd8423 1350 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1351 link_clock = 81000;
1352 break;
71cd8423 1353 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1354 link_clock = 108000;
1355 break;
71cd8423 1356 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1357 link_clock = 135000;
1358 break;
71cd8423 1359 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1360 link_clock = 162000;
1361 break;
71cd8423 1362 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1363 link_clock = 216000;
1364 break;
71cd8423 1365 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1366 link_clock = 270000;
1367 break;
1368 default:
1369 WARN(1, "Unsupported link rate\n");
1370 break;
1371 }
1372 link_clock *= 2;
1373 }
1374
1375 pipe_config->port_clock = link_clock;
1376
398a017e 1377 ddi_dotclock_get(pipe_config);
540e732c
S		 1378}
1379
3d51278a 1380static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1381 struct intel_crtc_state *pipe_config)
11578553 1382{
fac5e23e 1383 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1384 int link_clock = 0;
1385 u32 val, pll;
1386
c856052a 1387 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1388 switch (val & PORT_CLK_SEL_MASK) {
1389 case PORT_CLK_SEL_LCPLL_810:
1390 link_clock = 81000;
1391 break;
1392 case PORT_CLK_SEL_LCPLL_1350:
1393 link_clock = 135000;
1394 break;
1395 case PORT_CLK_SEL_LCPLL_2700:
1396 link_clock = 270000;
1397 break;
1398 case PORT_CLK_SEL_WRPLL1:
01403de3 1399 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1400 break;
1401 case PORT_CLK_SEL_WRPLL2:
01403de3 1402 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1403 break;
1404 case PORT_CLK_SEL_SPLL:
1405 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1406 if (pll == SPLL_PLL_FREQ_810MHz)
1407 link_clock = 81000;
1408 else if (pll == SPLL_PLL_FREQ_1350MHz)
1409 link_clock = 135000;
1410 else if (pll == SPLL_PLL_FREQ_2700MHz)
1411 link_clock = 270000;
1412 else {
1413 WARN(1, "bad spll freq\n");
1414 return;
1415 }
1416 break;
1417 default:
1418 WARN(1, "bad port clock sel\n");
1419 return;
1420 }
1421
1422 pipe_config->port_clock = link_clock * 2;
1423
398a017e 1424 ddi_dotclock_get(pipe_config);
11578553
JB		 1425}
1426
bb911536 1427static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
977bb38d 1428{
aa610dcb 1429 struct intel_dpll_hw_state *state;
9e2c8475 1430 struct dpll clock;
aa610dcb
ID		 1431
1432 /* For DDI ports we always use a shared PLL. */
bb911536 1433 if (WARN_ON(!crtc_state->shared_dpll))
aa610dcb
ID		 1434 return 0;
1435
bb911536 1436 state = &crtc_state->dpll_hw_state;
aa610dcb
ID		 1437
1438 clock.m1 = 2;
1439 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1440 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1441 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1442 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1443 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1444 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1445
1446 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1447}
1448
1449static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1450 struct intel_crtc_state *pipe_config)
977bb38d 1451{
bb911536 1452 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
977bb38d 1453
398a017e 1454 ddi_dotclock_get(pipe_config);
977bb38d
S		 1455}
1456
35686a44
VS		 1457static void intel_ddi_clock_get(struct intel_encoder *encoder,
1458 struct intel_crtc_state *pipe_config)
3d51278a 1459{
0853723b 1460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1461
0853723b 1462 if (INTEL_GEN(dev_priv) <= 8)
22606a18 1463 hsw_ddi_clock_get(encoder, pipe_config);
b976dc53 1464 else if (IS_GEN9_BC(dev_priv))
22606a18 1465 skl_ddi_clock_get(encoder, pipe_config);
cc3f90f0 1466 else if (IS_GEN9_LP(dev_priv))
977bb38d 1467 bxt_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1468 else if (IS_CANNONLAKE(dev_priv))
1469 cnl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1470}
1471
3dc38eea 1472void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1473{
3dc38eea 1474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1476 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1477 u32 temp;
dae84799 1478
5448f53f
VS		 1479 if (!intel_crtc_has_dp_encoder(crtc_state))
1480 return;
4d1de975 1481
5448f53f
VS		 1482 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1483
1484 temp = TRANS_MSA_SYNC_CLK;
1485 switch (crtc_state->pipe_bpp) {
1486 case 18:
1487 temp |= TRANS_MSA_6_BPC;
1488 break;
1489 case 24:
1490 temp |= TRANS_MSA_8_BPC;
1491 break;
1492 case 30:
1493 temp |= TRANS_MSA_10_BPC;
1494 break;
1495 case 36:
1496 temp |= TRANS_MSA_12_BPC;
1497 break;
1498 default:
1499 MISSING_CASE(crtc_state->pipe_bpp);
1500 break;
dae84799 1501 }
5448f53f
VS		 1502
1503 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1504}
1505
3dc38eea
ACO		 1506void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1507 bool state)
0e32b39c 1508{
3dc38eea 1509 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0e32b39c 1512 uint32_t temp;
7e732cac 1513
0e32b39c
DA		 1514 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1515 if (state == true)
1516 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1517 else
1518 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1519 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1520}
1521
3dc38eea 1522void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1523{
3dc38eea 1524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1525 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1526 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1527 enum pipe pipe = crtc->pipe;
3dc38eea 1528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1529 enum port port = encoder->port;
8d9ddbcb
PZ		 1530 uint32_t temp;
1531
ad80a810
PZ		 1532 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1533 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1534 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1535
3dc38eea 1536 switch (crtc_state->pipe_bpp) {
dfcef252 1537 case 18:
ad80a810 1538 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1539 break;
1540 case 24:
ad80a810 1541 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1542 break;
1543 case 30:
ad80a810 1544 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1545 break;
1546 case 36:
ad80a810 1547 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1548 break;
1549 default:
4e53c2e0 1550 BUG();
dfcef252 1551 }
72662e10 1552
3dc38eea 1553 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1554 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1555 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1556 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1557
e6f0bfc4
PZ		 1558 if (cpu_transcoder == TRANSCODER_EDP) {
1559 switch (pipe) {
1560 case PIPE_A:
c7670b10
PZ		 1561 /* On Haswell, can only use the always-on power well for
1562 * eDP when not using the panel fitter, and when not
1563 * using motion blur mitigation (which we don't
1564 * support). */
772c2a51 1565 if (IS_HASWELL(dev_priv) &&
3dc38eea
ACO		 1566 (crtc_state->pch_pfit.enabled ||
1567 crtc_state->pch_pfit.force_thru))
d6dd9eb1
DV		 1568 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1569 else
1570 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1571 break;
1572 case PIPE_B:
1573 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1574 break;
1575 case PIPE_C:
1576 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1577 break;
1578 default:
1579 BUG();
1580 break;
1581 }
1582 }
1583
742745f1 1584 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1585 if (crtc_state->has_hdmi_sink)
ad80a810 1586 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1587 else
ad80a810 1588 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1589
1590 if (crtc_state->hdmi_scrambling)
1591 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1592 if (crtc_state->hdmi_high_tmds_clock_ratio)
1593 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1594 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1595 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1596 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1597 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1598 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1599 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1600 } else {
742745f1
VS		 1601 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1602 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1603 }
1604
ad80a810 1605 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1606}
72662e10 1607
ad80a810
PZ		 1608void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1609 enum transcoder cpu_transcoder)
8d9ddbcb 1610{
f0f59a00 1611 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1612 uint32_t val = I915_READ(reg);
1613
0e32b39c 1614 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1615 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1616 I915_WRITE(reg, val);
72662e10
ED		 1617}
1618
2320175f
SP		 1619int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1620 bool enable)
1621{
1622 struct drm_device *dev = intel_encoder->base.dev;
1623 struct drm_i915_private *dev_priv = to_i915(dev);
1624 enum pipe pipe = 0;
1625 int ret = 0;
1626 uint32_t tmp;
1627
1628 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1629 intel_encoder->power_domain)))
1630 return -ENXIO;
1631
1632 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1633 ret = -EIO;
1634 goto out;
1635 }
1636
1637 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1638 if (enable)
1639 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1640 else
1641 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1642 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1643out:
1644 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1645 return ret;
1646}
1647
bcbc889b
PZ		 1648bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1649{
1650 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1651 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1652 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1653 int type = intel_connector->base.connector_type;
0fce04c8 1654 enum port port = encoder->port;
bcbc889b
PZ		 1655 enum pipe pipe = 0;
1656 enum transcoder cpu_transcoder;
1657 uint32_t tmp;
e27daab4 1658 bool ret;
bcbc889b 1659
79f255a0 1660 if (!intel_display_power_get_if_enabled(dev_priv,
1524e93e 1661 encoder->power_domain))
882244a3
PZ		 1662 return false;
1663
1524e93e 1664 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1665 ret = false;
1666 goto out;
1667 }
bcbc889b
PZ		 1668
1669 if (port == PORT_A)
1670 cpu_transcoder = TRANSCODER_EDP;
1671 else
1a240d4d 1672 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1673
1674 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1675
1676 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1677 case TRANS_DDI_MODE_SELECT_HDMI:
1678 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1679 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1680 break;
bcbc889b
PZ		 1681
1682 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1683 ret = type == DRM_MODE_CONNECTOR_eDP ||
1684 type == DRM_MODE_CONNECTOR_DisplayPort;
1685 break;
1686
0e32b39c
DA		 1687 case TRANS_DDI_MODE_SELECT_DP_MST:
1688 /* if the transcoder is in MST state then
1689 * connector isn't connected */
e27daab4
ID		 1690 ret = false;
1691 break;
bcbc889b
PZ		 1692
1693 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1694 ret = type == DRM_MODE_CONNECTOR_VGA;
1695 break;
bcbc889b
PZ		 1696
1697 default:
e27daab4
ID		 1698 ret = false;
1699 break;
bcbc889b 1700 }
e27daab4
ID		 1701
1702out:
1524e93e 1703 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1704
1705 return ret;
bcbc889b
PZ		 1706}
1707
85234cdc
DV		 1708bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1709 enum pipe *pipe)
1710{
1711 struct drm_device *dev = encoder->base.dev;
fac5e23e 1712 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1713 enum port port = encoder->port;
3657e927 1714 enum pipe p;
85234cdc 1715 u32 tmp;
e27daab4 1716 bool ret;
85234cdc 1717
79f255a0
ACO		 1718 if (!intel_display_power_get_if_enabled(dev_priv,
1719 encoder->power_domain))
6d129bea
ID		 1720 return false;
1721
e27daab4
ID		 1722 ret = false;
1723
fe43d3f5 1724 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1725
1726 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1727 goto out;
85234cdc 1728
ad80a810
PZ		 1729 if (port == PORT_A) {
1730 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1731
ad80a810
PZ		 1732 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1733 case TRANS_DDI_EDP_INPUT_A_ON:
1734 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1735 *pipe = PIPE_A;
1736 break;
1737 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1738 *pipe = PIPE_B;
1739 break;
1740 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1741 *pipe = PIPE_C;
1742 break;
1743 }
1744
e27daab4 1745 ret = true;
ad80a810 1746
e27daab4
ID		 1747 goto out;
1748 }
0e32b39c 1749
3657e927
MK		 1750 for_each_pipe(dev_priv, p) {
1751 enum transcoder cpu_transcoder = (enum transcoder) p;
1752
1753 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4
ID		 1754
1755 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1756 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1757 TRANS_DDI_MODE_SELECT_DP_MST)
1758 goto out;
1759
3657e927 1760 *pipe = p;
e27daab4
ID		 1761 ret = true;
1762
1763 goto out;
85234cdc
DV		 1764 }
1765 }
1766
84f44ce7 1767 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1768
e27daab4 1769out:
cc3f90f0 1770 if (ret && IS_GEN9_LP(dev_priv)) {
e93da0a0 1771 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 1772 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1773 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 1774 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1775 DRM_ERROR("Port %c enabled but PHY powered down? "
1776 "(PHY_CTL %08x)\n", port_name(port), tmp);
1777 }
1778
79f255a0 1779 intel_display_power_put(dev_priv, encoder->power_domain);
e27daab4
ID		 1780
1781 return ret;
85234cdc
DV		 1782}
1783
62b69566
ACO		 1784static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1785{
1786 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1787 enum pipe pipe;
1788
1789 if (intel_ddi_get_hw_state(encoder, &pipe))
1790 return BIT_ULL(dig_port->ddi_io_power_domain);
1791
1792 return 0;
1793}
1794
3dc38eea 1795void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1796{
3dc38eea 1797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 1799 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 1800 enum port port = encoder->port;
3dc38eea 1801 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1802
bb523fc0
PZ		 1803 if (cpu_transcoder != TRANSCODER_EDP)
1804 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1805 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1806}
1807
3dc38eea 1808void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 1809{
3dc38eea
ACO		 1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1811 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 1812
bb523fc0
PZ		 1813 if (cpu_transcoder != TRANSCODER_EDP)
1814 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1815 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1816}
1817
a7d8dbc0
VS		 1818static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1819 enum port port, uint8_t iboost)
f8896f5d 1820{
a7d8dbc0
VS		 1821 u32 tmp;
1822
1823 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1824 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1825 if (iboost)
1826 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1827 else
1828 tmp |= BALANCE_LEG_DISABLE(port);
1829 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1830}
1831
081dfcfa
VS		 1832static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1833 int level, enum intel_output_type type)
a7d8dbc0
VS		 1834{
1835 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 1836 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1837 enum port port = encoder->port;
f8896f5d 1838 uint8_t iboost;
f8896f5d 1839
081dfcfa
VS		 1840 if (type == INTEL_OUTPUT_HDMI)
1841 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1842 else
1843 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 1844
081dfcfa
VS		 1845 if (iboost == 0) {
1846 const struct ddi_buf_trans *ddi_translations;
1847 int n_entries;
1848
1849 if (type == INTEL_OUTPUT_HDMI)
1850 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1851 else if (type == INTEL_OUTPUT_EDP)
edba48fd 1852 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 1853 else
edba48fd 1854 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 1855
21b39d2a
VS		 1856 if (WARN_ON_ONCE(!ddi_translations))
1857 return;
1858 if (WARN_ON_ONCE(level >= n_entries))
1859 level = n_entries - 1;
1860
081dfcfa 1861 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 1862 }
1863
1864 /* Make sure that the requested I_boost is valid */
1865 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1866 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1867 return;
1868 }
1869
a7d8dbc0 1870 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 1871
a7d8dbc0
VS		 1872 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1873 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 1874}
1875
7d4f37b5
VS		 1876static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1877 int level, enum intel_output_type type)
96fb9f9b 1878{
7d4f37b5 1879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 1880 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 1881 enum port port = encoder->port;
043eaf36 1882 int n_entries;
7d4f37b5
VS		 1883
1884 if (type == INTEL_OUTPUT_HDMI)
1885 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1886 else if (type == INTEL_OUTPUT_EDP)
1887 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1888 else
1889 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 1890
21b39d2a
VS		 1891 if (WARN_ON_ONCE(!ddi_translations))
1892 return;
1893 if (WARN_ON_ONCE(level >= n_entries))
1894 level = n_entries - 1;
1895
b6e08203
ACO		 1896 bxt_ddi_phy_set_signal_level(dev_priv, port,
1897 ddi_translations[level].margin,
1898 ddi_translations[level].scale,
1899 ddi_translations[level].enable,
1900 ddi_translations[level].deemphasis);
96fb9f9b
VK		 1901}
1902
ffe5111e
VS		 1903u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1904{
1905 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
edba48fd 1906 enum port port = encoder->port;
ffe5111e
VS		 1907 int n_entries;
1908
5fcf34b1
RV		 1909 if (IS_CANNONLAKE(dev_priv)) {
1910 if (encoder->type == INTEL_OUTPUT_EDP)
1911 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1912 else
1913 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 1914 } else if (IS_GEN9_LP(dev_priv)) {
1915 if (encoder->type == INTEL_OUTPUT_EDP)
1916 bxt_get_buf_trans_edp(dev_priv, &n_entries);
1917 else
1918 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 1919 } else {
1920 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 1921 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 1922 else
edba48fd 1923 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 1924 }
ffe5111e
VS		 1925
1926 if (WARN_ON(n_entries < 1))
1927 n_entries = 1;
1928 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1929 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1930
1931 return index_to_dp_signal_levels[n_entries - 1] &
1932 DP_TRAIN_VOLTAGE_SWING_MASK;
1933}
1934
f3cf4ba4
VS		 1935static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1936 int level, enum intel_output_type type)
cf54ca8b 1937{
f3cf4ba4 1938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 1939 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 1940 enum port port = encoder->port;
f3cf4ba4
VS		 1941 int n_entries, ln;
1942 u32 val;
cf54ca8b 1943
f3cf4ba4 1944 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 1945 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 1946 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 1947 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 1948 else
1949 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 1950
21b39d2a 1951 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 1952 return;
21b39d2a 1953 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 1954 level = n_entries - 1;
cf54ca8b
RV		 1955
1956 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1957 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1958 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 1959 val |= SCALING_MODE_SEL(2);
1960 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1961
1962 /* Program PORT_TX_DW2 */
1963 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 1964 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1965 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 1966 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1967 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1968 /* Rcomp scalar is fixed as 0x98 for every table entry */
1969 val |= RCOMP_SCALAR(0x98);
1970 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1971
20303eb4 1972 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 1973 /* We cannot write to GRP. It would overrite individual loadgen */
1974 for (ln = 0; ln < 4; ln++) {
1975 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1f588aeb
RV		 1976 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1977 CURSOR_COEFF_MASK);
cf54ca8b
RV		 1978 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1979 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1980 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1981 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1982 }
1983
20303eb4 1984 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 1985 /* All DW5 values are fixed for every table entry */
1986 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 1987 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 1988 val |= RTERM_SELECT(6);
1989 val |= TAP3_DISABLE;
1990 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1991
20303eb4 1992 /* Program PORT_TX_DW7 */
cf54ca8b 1993 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 1994 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 1995 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1996 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1997}
1998
f3cf4ba4
VS		 1999static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2000 int level, enum intel_output_type type)
cf54ca8b 2001{
0091abc3 2002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2003 enum port port = encoder->port;
f3cf4ba4 2004 int width, rate, ln;
cf54ca8b 2005 u32 val;
0091abc3 2006
f3cf4ba4 2007 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2008 width = 4;
f3cf4ba4 2009 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2010 } else {
f3cf4ba4
VS		 2011 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012
2013 width = intel_dp->lane_count;
2014 rate = intel_dp->link_rate;
0091abc3 2015 }
cf54ca8b
RV		 2016
2017 /*
2018 * 1. If port type is eDP or DP,
2019 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2020 * else clear to 0b.
2021 */
2022 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2023 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2024 val |= COMMON_KEEPER_EN;
2025 else
2026 val &= ~COMMON_KEEPER_EN;
2027 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2028
2029 /* 2. Program loadgen select */
2030 /*
0091abc3
CT		 2031 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2032 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2033 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2034 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2035 */
0091abc3
CT		 2036 for (ln = 0; ln <= 3; ln++) {
2037 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2038 val &= ~LOADGEN_SELECT;
2039
a8e45a1c
NM		 2040 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2041 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2042 val |= LOADGEN_SELECT;
2043 }
2044 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2045 }
cf54ca8b
RV		 2046
2047 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2048 val = I915_READ(CNL_PORT_CL1CM_DW5);
2049 val |= SUS_CLOCK_CONFIG;
2050 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2051
2052 /* 4. Clear training enable to change swing values */
2053 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2054 val &= ~TX_TRAINING_EN;
2055 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2056
2057 /* 5. Program swing and de-emphasis */
f3cf4ba4 2058 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2059
2060 /* 6. Set training enable to trigger update */
2061 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2062 val |= TX_TRAINING_EN;
2063 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2064}
2065
f8896f5d
DW		 2066static uint32_t translate_signal_level(int signal_levels)
2067{
97eeb872 2068 int i;
f8896f5d 2069
97eeb872
VS		 2070 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2071 if (index_to_dp_signal_levels[i] == signal_levels)
2072 return i;
f8896f5d
DW		 2073 }
2074
97eeb872
VS		 2075 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2076 signal_levels);
2077
2078 return 0;
f8896f5d
DW		 2079}
2080
1b6e2fd2
RV		 2081static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2082{
2083 uint8_t train_set = intel_dp->train_set[0];
2084 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2085 DP_TRAIN_PRE_EMPHASIS_MASK);
2086
2087 return translate_signal_level(signal_levels);
2088}
2089
d509af6c 2090u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2091{
2092 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2093 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2094 struct intel_encoder *encoder = &dport->base;
d02ace87 2095 int level = intel_ddi_dp_level(intel_dp);
d509af6c
RV		 2096
2097 if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2098 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2099 else
7d4f37b5 2100 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2101
2102 return 0;
2103}
2104
2105uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2106{
2107 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2108 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2109 struct intel_encoder *encoder = &dport->base;
d02ace87 2110 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2111
b976dc53 2112 if (IS_GEN9_BC(dev_priv))
081dfcfa 2113 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2114
f8896f5d
DW		 2115 return DDI_BUF_TRANS_SELECT(level);
2116}
2117
d7c530b2 2118static void intel_ddi_clk_select(struct intel_encoder *encoder,
5f88a9c6 2119 const struct intel_shared_dpll *pll)
6441ab5f 2120{
e404ba8d 2121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2122 enum port port = encoder->port;
555e38d2 2123 uint32_t val;
6441ab5f 2124
c856052a
ACO		 2125 if (WARN_ON(!pll))
2126 return;
2127
04bf68bb 2128 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2129
555e38d2
RV		 2130 if (IS_CANNONLAKE(dev_priv)) {
2131 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2132 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2133 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
555e38d2
RV		 2134 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2135 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2136
555e38d2
RV		 2137 /*
2138 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2139 * This step and the step before must be done with separate
2140 * register writes.
2141 */
2142 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2143 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2144 I915_WRITE(DPCLKA_CFGCR0, val);
2145 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2146 /* DDI -> PLL mapping */
efa80add
S		 2147 val = I915_READ(DPLL_CTRL2);
2148
2149 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2150 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
c856052a 2151 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
efa80add
S		 2152 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2153
2154 I915_WRITE(DPLL_CTRL2, val);
5416d871 2155
c56b89f1 2156 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2157 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2158 }
8edcda12
RV		 2159
2160 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2161}
2162
6b8506d5
VS		 2163static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2164{
2165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2166 enum port port = encoder->port;
6b8506d5
VS		 2167
2168 if (IS_CANNONLAKE(dev_priv))
2169 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2170 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2171 else if (IS_GEN9_BC(dev_priv))
2172 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2173 DPLL_CTRL2_DDI_CLK_OFF(port));
2174 else if (INTEL_GEN(dev_priv) < 9)
2175 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2176}
2177
ba88d153 2178static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 2179 const struct intel_crtc_state *crtc_state,
2180 const struct drm_connector_state *conn_state)
e404ba8d 2181{
ba88d153
MN		 2182 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2184 enum port port = encoder->port;
62b69566 2185 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 2186 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 2187 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 2188
45e0327e 2189 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 2190
45e0327e
VS		 2191 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2192 crtc_state->lane_count, is_mst);
680b71c2
VS		 2193
2194 intel_edp_panel_on(intel_dp);
32bdc400 2195
45e0327e 2196 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2197
2198 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2199
381f9570 2200 if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2201 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 2202 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2203 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 2204 else
3a6d84e6 2205 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 2206
ba88d153 2207 intel_ddi_init_dp_buf_reg(encoder);
45e0327e 2208 if (!is_mst)
5ea2355a 2209 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
ba88d153
MN		 2210 intel_dp_start_link_train(intel_dp);
2211 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2212 intel_dp_stop_link_train(intel_dp);
2213}
901c2daf 2214
ba88d153 2215static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 2216 const struct intel_crtc_state *crtc_state,
45e0327e 2217 const struct drm_connector_state *conn_state)
ba88d153 2218{
f99be1b3
VS		 2219 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2220 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 2221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2222 enum port port = encoder->port;
ba88d153 2223 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 2224 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 2225
ba88d153 2226 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
45e0327e 2227 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
62b69566
ACO		 2228
2229 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2230
2f7460a7 2231 if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2232 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 2233 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 2234 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 2235 else
7ea79333 2236 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7
RV		 2237
2238 if (IS_GEN9_BC(dev_priv))
081dfcfa 2239 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 2240
f99be1b3 2241 intel_dig_port->set_infoframes(&encoder->base,
45e0327e 2242 crtc_state->has_infoframe,
f99be1b3 2243 crtc_state, conn_state);
ba88d153 2244}
32bdc400 2245
1524e93e 2246static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 2247 const struct intel_crtc_state *crtc_state,
5f88a9c6 2248 const struct drm_connector_state *conn_state)
ba88d153 2249{
45e0327e
VS		 2250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2251 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2252 enum pipe pipe = crtc->pipe;
30cf6db8 2253
1939ba51
VS		 2254 /*
2255 * When called from DP MST code:
2256 * - conn_state will be NULL
2257 * - encoder will be the main encoder (ie. mst->primary)
2258 * - the main connector associated with this port
2259 * won't be active or linked to a crtc
2260 * - crtc_state will be the state of the first stream to
2261 * be activated on this port, and it may not be the same
2262 * stream that will be deactivated last, but each stream
2263 * should have a state that is identical when it comes to
2264 * the DP link parameteres
2265 */
2266
45e0327e 2267 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1
JN		 2268
2269 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2270
45e0327e
VS		 2271 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2272 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2273 else
2274 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
6441ab5f
PZ		 2275}
2276
e725f645
VS		 2277static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2278{
2279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2280 enum port port = encoder->port;
e725f645
VS		 2281 bool wait = false;
2282 u32 val;
2283
2284 val = I915_READ(DDI_BUF_CTL(port));
2285 if (val & DDI_BUF_CTL_ENABLE) {
2286 val &= ~DDI_BUF_CTL_ENABLE;
2287 I915_WRITE(DDI_BUF_CTL(port), val);
2288 wait = true;
2289 }
2290
2291 val = I915_READ(DP_TP_CTL(port));
2292 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2293 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2294 I915_WRITE(DP_TP_CTL(port), val);
2295
2296 if (wait)
2297 intel_wait_ddi_buf_idle(dev_priv, port);
2298}
2299
f45f3da7
VS		 2300static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2301 const struct intel_crtc_state *old_crtc_state,
2302 const struct drm_connector_state *old_conn_state)
6441ab5f 2303{
f45f3da7
VS		 2304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2305 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2306 struct intel_dp *intel_dp = &dig_port->dp;
1939ba51 2307 bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST);
2886e93f 2308
f45f3da7
VS		 2309 /*
2310 * Power down sink before disabling the port, otherwise we end
2311 * up getting interrupts from the sink on detecting link loss.
2312 */
2313 if (!is_mst)
2314 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
c5f93fcf 2315
f45f3da7 2316 intel_disable_ddi_buf(encoder);
7618138d 2317
f45f3da7
VS		 2318 intel_edp_panel_vdd_on(intel_dp);
2319 intel_edp_panel_off(intel_dp);
a836bdf9 2320
f45f3da7 2321 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
c5f93fcf 2322
f45f3da7
VS		 2323 intel_ddi_clk_disable(encoder);
2324}
c5f93fcf 2325
f45f3da7
VS		 2326static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2327 const struct intel_crtc_state *old_crtc_state,
2328 const struct drm_connector_state *old_conn_state)
2329{
2330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2331 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2332 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 2333
f45f3da7 2334 intel_disable_ddi_buf(encoder);
62b69566 2335
f45f3da7
VS		 2336 dig_port->set_infoframes(&encoder->base, false,
2337 old_crtc_state, old_conn_state);
b2ccb822 2338
f45f3da7 2339 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
b2ccb822 2340
f45f3da7
VS		 2341 intel_ddi_clk_disable(encoder);
2342
2343 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2344}
2345
2346static void intel_ddi_post_disable(struct intel_encoder *encoder,
2347 const struct intel_crtc_state *old_crtc_state,
2348 const struct drm_connector_state *old_conn_state)
2349{
2350 /*
1939ba51
VS		 2351 * When called from DP MST code:
2352 * - old_conn_state will be NULL
2353 * - encoder will be the main encoder (ie. mst->primary)
2354 * - the main connector associated with this port
2355 * won't be active or linked to a crtc
2356 * - old_crtc_state will be the state of the last stream to
2357 * be deactivated on this port, and it may not be the same
2358 * stream that was activated last, but each stream
2359 * should have a state that is identical when it comes to
2360 * the DP link parameteres
f45f3da7 2361 */
1939ba51
VS		 2362
2363 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 2364 intel_ddi_post_disable_hdmi(encoder,
2365 old_crtc_state, old_conn_state);
2366 else
2367 intel_ddi_post_disable_dp(encoder,
2368 old_crtc_state, old_conn_state);
6441ab5f
PZ		 2369}
2370
1524e93e 2371void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2372 const struct intel_crtc_state *old_crtc_state,
2373 const struct drm_connector_state *old_conn_state)
b7076546 2374{
1524e93e 2375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b7076546
ML		 2376 uint32_t val;
2377
2378 /*
2379 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2380 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2381 * step 13 is the correct place for it. Step 18 is where it was
2382 * originally before the BUN.
2383 */
2384 val = I915_READ(FDI_RX_CTL(PIPE_A));
2385 val &= ~FDI_RX_ENABLE;
2386 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2387
fb0bd3bd
VS		 2388 intel_disable_ddi_buf(encoder);
2389 intel_ddi_clk_disable(encoder);
b7076546
ML		 2390
2391 val = I915_READ(FDI_RX_MISC(PIPE_A));
2392 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2393 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2394 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2395
2396 val = I915_READ(FDI_RX_CTL(PIPE_A));
2397 val &= ~FDI_PCDCLK;
2398 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2399
2400 val = I915_READ(FDI_RX_CTL(PIPE_A));
2401 val &= ~FDI_RX_PLL_ENABLE;
2402 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2403}
2404
15d05f0e
VS		 2405static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2406 const struct intel_crtc_state *crtc_state,
2407 const struct drm_connector_state *conn_state)
72662e10 2408{
15d05f0e
VS		 2409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2410 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 2411 enum port port = encoder->port;
72662e10 2412
15d05f0e
VS		 2413 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2414 intel_dp_stop_link_train(intel_dp);
d6c50ff8 2415
15d05f0e
VS		 2416 intel_edp_backlight_on(crtc_state, conn_state);
2417 intel_psr_enable(intel_dp, crtc_state);
2418 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 2419
15d05f0e
VS		 2420 if (crtc_state->has_audio)
2421 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2422}
2423
2424static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2425 const struct intel_crtc_state *crtc_state,
2426 const struct drm_connector_state *conn_state)
2427{
2428 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2429 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
0fce04c8 2430 enum port port = encoder->port;
15d05f0e
VS		 2431
2432 intel_hdmi_handle_sink_scrambling(encoder,
2433 conn_state->connector,
2434 crtc_state->hdmi_high_tmds_clock_ratio,
2435 crtc_state->hdmi_scrambling);
2436
0519c102
VS		 2437 /* Display WA #1143: skl,kbl,cfl */
2438 if (IS_GEN9_BC(dev_priv)) {
2439 /*
2440 * For some reason these chicken bits have been
2441 * stuffed into a transcoder register, event though
2442 * the bits affect a specific DDI port rather than
2443 * a specific transcoder.
2444 */
2445 static const enum transcoder port_to_transcoder[] = {
2446 [PORT_A] = TRANSCODER_EDP,
2447 [PORT_B] = TRANSCODER_A,
2448 [PORT_C] = TRANSCODER_B,
2449 [PORT_D] = TRANSCODER_C,
2450 [PORT_E] = TRANSCODER_A,
2451 };
2452 enum transcoder transcoder = port_to_transcoder[port];
2453 u32 val;
2454
2455 val = I915_READ(CHICKEN_TRANS(transcoder));
2456
2457 if (port == PORT_E)
2458 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2459 DDIE_TRAINING_OVERRIDE_VALUE;
2460 else
2461 val |= DDI_TRAINING_OVERRIDE_ENABLE |
2462 DDI_TRAINING_OVERRIDE_VALUE;
2463
2464 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2465 POSTING_READ(CHICKEN_TRANS(transcoder));
2466
2467 udelay(1);
2468
2469 if (port == PORT_E)
2470 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2471 DDIE_TRAINING_OVERRIDE_VALUE);
2472 else
2473 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2474 DDI_TRAINING_OVERRIDE_VALUE);
2475
2476 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2477 }
2478
15d05f0e
VS		 2479 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2480 * are ignored so nothing special needs to be done besides
2481 * enabling the port.
2482 */
2483 I915_WRITE(DDI_BUF_CTL(port),
2484 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 2485
15d05f0e
VS		 2486 if (crtc_state->has_audio)
2487 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2488}
2489
2490static void intel_enable_ddi(struct intel_encoder *encoder,
2491 const struct intel_crtc_state *crtc_state,
2492 const struct drm_connector_state *conn_state)
2493{
2494 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2495 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2496 else
2497 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 2498
2499 /* Enable hdcp if it's desired */
2500 if (conn_state->content_protection ==
2501 DRM_MODE_CONTENT_PROTECTION_DESIRED)
2502 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 2503}
2504
33f083f0
VS		 2505static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2506 const struct intel_crtc_state *old_crtc_state,
2507 const struct drm_connector_state *old_conn_state)
5ab432ef 2508{
33f083f0 2509 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 2510
37255d8d 2511 if (old_crtc_state->has_audio)
8ec47de2
VS		 2512 intel_audio_codec_disable(encoder,
2513 old_crtc_state, old_conn_state);
2831d842 2514
33f083f0
VS		 2515 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2516 intel_psr_disable(intel_dp, old_crtc_state);
2517 intel_edp_backlight_off(old_conn_state);
2518}
15953637 2519
33f083f0
VS		 2520static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2521 const struct intel_crtc_state *old_crtc_state,
2522 const struct drm_connector_state *old_conn_state)
2523{
2524 if (old_crtc_state->has_audio)
8ec47de2
VS		 2525 intel_audio_codec_disable(encoder,
2526 old_crtc_state, old_conn_state);
d6c50ff8 2527
33f083f0
VS		 2528 intel_hdmi_handle_sink_scrambling(encoder,
2529 old_conn_state->connector,
2530 false, false);
2531}
2532
2533static void intel_disable_ddi(struct intel_encoder *encoder,
2534 const struct intel_crtc_state *old_crtc_state,
2535 const struct drm_connector_state *old_conn_state)
2536{
ee5e5e7a
SP		 2537 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2538
33f083f0
VS		 2539 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2540 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2541 else
2542 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 2543}
79f689aa 2544
fd6bbda9 2545static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2546 const struct intel_crtc_state *pipe_config,
2547 const struct drm_connector_state *conn_state)
95a7a2ae 2548{
3dc38eea 2549 uint8_t mask = pipe_config->lane_lat_optim_mask;
95a7a2ae 2550
47a6bc61 2551 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
95a7a2ae
ID		 2552}
2553
ad64217b 2554void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2555{
ad64217b
ACO		 2556 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2557 struct drm_i915_private *dev_priv =
2558 to_i915(intel_dig_port->base.base.dev);
8f4f2797 2559 enum port port = intel_dig_port->base.port;
c19b0669 2560 uint32_t val;
f3e227df 2561 bool wait = false;
c19b0669
PZ		 2562
2563 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2564 val = I915_READ(DDI_BUF_CTL(port));
2565 if (val & DDI_BUF_CTL_ENABLE) {
2566 val &= ~DDI_BUF_CTL_ENABLE;
2567 I915_WRITE(DDI_BUF_CTL(port), val);
2568 wait = true;
2569 }
2570
2571 val = I915_READ(DP_TP_CTL(port));
2572 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2573 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2574 I915_WRITE(DP_TP_CTL(port), val);
2575 POSTING_READ(DP_TP_CTL(port));
2576
2577 if (wait)
2578 intel_wait_ddi_buf_idle(dev_priv, port);
2579 }
2580
0e32b39c 2581 val = DP_TP_CTL_ENABLE |
c19b0669 2582 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 2583 if (intel_dp->link_mst)
0e32b39c
DA		 2584 val |= DP_TP_CTL_MODE_MST;
2585 else {
2586 val |= DP_TP_CTL_MODE_SST;
2587 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2588 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2589 }
c19b0669
PZ		 2590 I915_WRITE(DP_TP_CTL(port), val);
2591 POSTING_READ(DP_TP_CTL(port));
2592
2593 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2594 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2595 POSTING_READ(DDI_BUF_CTL(port));
2596
2597 udelay(600);
2598}
00c09d70 2599
2085cc5d
VS		 2600static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2601 enum transcoder cpu_transcoder)
9935f7fa 2602{
2085cc5d
VS		 2603 if (cpu_transcoder == TRANSCODER_EDP)
2604 return false;
9935f7fa 2605
2085cc5d
VS		 2606 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
2607 return false;
2608
2609 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
2610 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 2611}
2612
53e9bf5e
VS		 2613void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
2614 struct intel_crtc_state *crtc_state)
2615{
2616 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
2617 crtc_state->min_voltage_level = 2;
2618}
2619
6801c18c 2620void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2621 struct intel_crtc_state *pipe_config)
045ac3b5 2622{
fac5e23e 2623 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 2624 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 2625 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 2626 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 2627 u32 temp, flags = 0;
2628
4d1de975
JN		 2629 /* XXX: DSI transcoder paranoia */
2630 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2631 return;
2632
045ac3b5
JB		 2633 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2634 if (temp & TRANS_DDI_PHSYNC)
2635 flags |= DRM_MODE_FLAG_PHSYNC;
2636 else
2637 flags |= DRM_MODE_FLAG_NHSYNC;
2638 if (temp & TRANS_DDI_PVSYNC)
2639 flags |= DRM_MODE_FLAG_PVSYNC;
2640 else
2641 flags |= DRM_MODE_FLAG_NVSYNC;
2642
2d112de7 2643 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2644
2645 switch (temp & TRANS_DDI_BPC_MASK) {
2646 case TRANS_DDI_BPC_6:
2647 pipe_config->pipe_bpp = 18;
2648 break;
2649 case TRANS_DDI_BPC_8:
2650 pipe_config->pipe_bpp = 24;
2651 break;
2652 case TRANS_DDI_BPC_10:
2653 pipe_config->pipe_bpp = 30;
2654 break;
2655 case TRANS_DDI_BPC_12:
2656 pipe_config->pipe_bpp = 36;
2657 break;
2658 default:
2659 break;
2660 }
eb14cb74
VS		 2661
2662 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2663 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2664 pipe_config->has_hdmi_sink = true;
f99be1b3 2665 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 2666
f99be1b3 2667 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2668 pipe_config->has_infoframe = true;
15953637
SS		 2669
2670 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2671 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2672 pipe_config->hdmi_scrambling = true;
2673 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2674 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 2675 /* fall through */
eb14cb74 2676 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 2677 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 2678 pipe_config->lane_count = 4;
2679 break;
eb14cb74 2680 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 2681 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 2682 break;
2683 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 2684 if (encoder->type == INTEL_OUTPUT_EDP)
2685 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2686 else
2687 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2688 pipe_config->lane_count =
2689 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2690 intel_dp_get_m_n(intel_crtc, pipe_config);
2691 break;
eb14cb74 2692 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 2693 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 2694 pipe_config->lane_count =
2695 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2696 intel_dp_get_m_n(intel_crtc, pipe_config);
2697 break;
2698 default:
2699 break;
2700 }
10214420 2701
9935f7fa 2702 pipe_config->has_audio =
2085cc5d 2703 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 2704
6aa23e65
JN		 2705 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2706 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2707 /*
2708 * This is a big fat ugly hack.
2709 *
2710 * Some machines in UEFI boot mode provide us a VBT that has 18
2711 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2712 * unknown we fail to light up. Yet the same BIOS boots up with
2713 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2714 * max, not what it tells us to use.
2715 *
2716 * Note: This will still be broken if the eDP panel is not lit
2717 * up by the BIOS, and thus we can't get the mode at module
2718 * load.
2719 */
2720 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2721 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2722 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2723 }
11578553 2724
22606a18 2725 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 2726
cc3f90f0 2727 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 2728 pipe_config->lane_lat_optim_mask =
2729 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 2730
2731 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
045ac3b5
JB		 2732}
2733
7e732cac
VS		 2734static enum intel_output_type
2735intel_ddi_compute_output_type(struct intel_encoder *encoder,
2736 struct intel_crtc_state *crtc_state,
2737 struct drm_connector_state *conn_state)
2738{
2739 switch (conn_state->connector->connector_type) {
2740 case DRM_MODE_CONNECTOR_HDMIA:
2741 return INTEL_OUTPUT_HDMI;
2742 case DRM_MODE_CONNECTOR_eDP:
2743 return INTEL_OUTPUT_EDP;
2744 case DRM_MODE_CONNECTOR_DisplayPort:
2745 return INTEL_OUTPUT_DP;
2746 default:
2747 MISSING_CASE(conn_state->connector->connector_type);
2748 return INTEL_OUTPUT_UNUSED;
2749 }
2750}
2751
5bfe2ac0 2752static bool intel_ddi_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 2753 struct intel_crtc_state *pipe_config,
2754 struct drm_connector_state *conn_state)
00c09d70 2755{
fac5e23e 2756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2757 enum port port = encoder->port;
95a7a2ae 2758 int ret;
00c09d70 2759
eccb140b
DV		 2760 if (port == PORT_A)
2761 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2762
7e732cac 2763 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 2764 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 2765 else
0a478c27 2766 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
95a7a2ae 2767
cc3f90f0 2768 if (IS_GEN9_LP(dev_priv) && ret)
95a7a2ae 2769 pipe_config->lane_lat_optim_mask =
5161d058 2770 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 2771
53e9bf5e
VS		 2772 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2773
95a7a2ae
ID		 2774 return ret;
2775
00c09d70
PZ		 2776}
2777
2778static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2779 .reset = intel_dp_encoder_reset,
2780 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2781};
2782
4a28ae58
PZ		 2783static struct intel_connector *
2784intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2785{
2786 struct intel_connector *connector;
8f4f2797 2787 enum port port = intel_dig_port->base.port;
4a28ae58 2788
9bdbd0b9 2789 connector = intel_connector_alloc();
4a28ae58
PZ		 2790 if (!connector)
2791 return NULL;
2792
2793 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2794 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2795 kfree(connector);
2796 return NULL;
2797 }
2798
2799 return connector;
2800}
2801
dba14b27
VS		 2802static int modeset_pipe(struct drm_crtc *crtc,
2803 struct drm_modeset_acquire_ctx *ctx)
2804{
2805 struct drm_atomic_state *state;
2806 struct drm_crtc_state *crtc_state;
2807 int ret;
2808
2809 state = drm_atomic_state_alloc(crtc->dev);
2810 if (!state)
2811 return -ENOMEM;
2812
2813 state->acquire_ctx = ctx;
2814
2815 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2816 if (IS_ERR(crtc_state)) {
2817 ret = PTR_ERR(crtc_state);
2818 goto out;
2819 }
2820
2821 crtc_state->mode_changed = true;
2822
2823 ret = drm_atomic_add_affected_connectors(state, crtc);
2824 if (ret)
2825 goto out;
2826
2827 ret = drm_atomic_add_affected_planes(state, crtc);
2828 if (ret)
2829 goto out;
2830
2831 ret = drm_atomic_commit(state);
2832 if (ret)
2833 goto out;
2834
2835 return 0;
2836
2837 out:
2838 drm_atomic_state_put(state);
2839
2840 return ret;
2841}
2842
2843static int intel_hdmi_reset_link(struct intel_encoder *encoder,
2844 struct drm_modeset_acquire_ctx *ctx)
2845{
2846 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2847 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
2848 struct intel_connector *connector = hdmi->attached_connector;
2849 struct i2c_adapter *adapter =
2850 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2851 struct drm_connector_state *conn_state;
2852 struct intel_crtc_state *crtc_state;
2853 struct intel_crtc *crtc;
2854 u8 config;
2855 int ret;
2856
2857 if (!connector || connector->base.status != connector_status_connected)
2858 return 0;
2859
2860 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
2861 ctx);
2862 if (ret)
2863 return ret;
2864
2865 conn_state = connector->base.state;
2866
2867 crtc = to_intel_crtc(conn_state->crtc);
2868 if (!crtc)
2869 return 0;
2870
2871 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
2872 if (ret)
2873 return ret;
2874
2875 crtc_state = to_intel_crtc_state(crtc->base.state);
2876
2877 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
2878
2879 if (!crtc_state->base.active)
2880 return 0;
2881
2882 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
2883 !crtc_state->hdmi_scrambling)
2884 return 0;
2885
2886 if (conn_state->commit &&
2887 !try_wait_for_completion(&conn_state->commit->hw_done))
2888 return 0;
2889
2890 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
2891 if (ret < 0) {
2892 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
2893 return 0;
2894 }
2895
2896 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
2897 crtc_state->hdmi_high_tmds_clock_ratio &&
2898 !!(config & SCDC_SCRAMBLING_ENABLE) ==
2899 crtc_state->hdmi_scrambling)
2900 return 0;
2901
2902 /*
2903 * HDMI 2.0 says that one should not send scrambled data
2904 * prior to configuring the sink scrambling, and that
2905 * TMDS clock/data transmission should be suspended when
2906 * changing the TMDS clock rate in the sink. So let's
2907 * just do a full modeset here, even though some sinks
2908 * would be perfectly happy if were to just reconfigure
2909 * the SCDC settings on the fly.
2910 */
2911 return modeset_pipe(&crtc->base, ctx);
2912}
2913
2914static bool intel_ddi_hotplug(struct intel_encoder *encoder,
2915 struct intel_connector *connector)
2916{
2917 struct drm_modeset_acquire_ctx ctx;
2918 bool changed;
2919 int ret;
2920
2921 changed = intel_encoder_hotplug(encoder, connector);
2922
2923 drm_modeset_acquire_init(&ctx, 0);
2924
2925 for (;;) {
2926 ret = intel_hdmi_reset_link(encoder, &ctx);
2927
2928 if (ret == -EDEADLK) {
2929 drm_modeset_backoff(&ctx);
2930 continue;
2931 }
2932
2933 break;
2934 }
2935
2936 drm_modeset_drop_locks(&ctx);
2937 drm_modeset_acquire_fini(&ctx);
2938 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
2939
2940 return changed;
2941}
2942
4a28ae58
PZ		 2943static struct intel_connector *
2944intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2945{
2946 struct intel_connector *connector;
8f4f2797 2947 enum port port = intel_dig_port->base.port;
4a28ae58 2948
9bdbd0b9 2949 connector = intel_connector_alloc();
4a28ae58
PZ		 2950 if (!connector)
2951 return NULL;
2952
2953 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2954 intel_hdmi_init_connector(intel_dig_port, connector);
2955
2956 return connector;
2957}
2958
436009b5
RV		 2959static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
2960{
2961 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2962
8f4f2797 2963 if (dport->base.port != PORT_A)
436009b5
RV		 2964 return false;
2965
2966 if (dport->saved_port_bits & DDI_A_4_LANES)
2967 return false;
2968
2969 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
2970 * supported configuration
2971 */
2972 if (IS_GEN9_LP(dev_priv))
2973 return true;
2974
2975 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
2976 * one who does also have a full A/E split called
2977 * DDI_F what makes DDI_E useless. However for this
2978 * case let's trust VBT info.
2979 */
2980 if (IS_CANNONLAKE(dev_priv) &&
2981 !intel_bios_is_port_present(dev_priv, PORT_E))
2982 return true;
2983
2984 return false;
2985}
2986
3d2011cf
MK		 2987static int
2988intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
2989{
2990 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
2991 enum port port = intel_dport->base.port;
2992 int max_lanes = 4;
2993
2994 if (INTEL_GEN(dev_priv) >= 11)
2995 return max_lanes;
2996
2997 if (port == PORT_A || port == PORT_E) {
2998 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
2999 max_lanes = port == PORT_A ? 4 : 0;
3000 else
3001 /* Both A and E share 2 lanes */
3002 max_lanes = 2;
3003 }
3004
3005 /*
3006 * Some BIOS might fail to set this bit on port A if eDP
3007 * wasn't lit up at boot. Force this bit set when needed
3008 * so we use the proper lane count for our calculations.
3009 */
3010 if (intel_ddi_a_force_4_lanes(intel_dport)) {
3011 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3012 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3013 max_lanes = 4;
3014 }
3015
3016 return max_lanes;
3017}
3018
c39055b0 3019void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70
PZ		 3020{
3021 struct intel_digital_port *intel_dig_port;
3022 struct intel_encoder *intel_encoder;
3023 struct drm_encoder *encoder;
ff662124 3024 bool init_hdmi, init_dp, init_lspcon = false;
10e7bec3 3025
311a2094
PZ		 3026
3027 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3028 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3029 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
ff662124
SS		 3030
3031 if (intel_bios_is_lspcon_present(dev_priv, port)) {
3032 /*
3033 * Lspcon device needs to be driven with DP connector
3034 * with special detection sequence. So make sure DP
3035 * is initialized before lspcon.
3036 */
3037 init_dp = true;
3038 init_lspcon = true;
3039 init_hdmi = false;
3040 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3041 }
3042
311a2094 3043 if (!init_dp && !init_hdmi) {
500ea70d 3044 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3045 port_name(port));
500ea70d 3046 return;
311a2094 3047 }
00c09d70 3048
b14c5679 3049 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3050 if (!intel_dig_port)
3051 return;
3052
00c09d70
PZ		 3053 intel_encoder = &intel_dig_port->base;
3054 encoder = &intel_encoder->base;
3055
c39055b0 3056 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 3057 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 3058
dba14b27
VS		 3059 if (init_hdmi)
3060 intel_encoder->hotplug = intel_ddi_hotplug;
3061 else
3062 intel_encoder->hotplug = intel_encoder_hotplug;
7e732cac 3063 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 3064 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 3065 intel_encoder->enable = intel_enable_ddi;
cc3f90f0 3066 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3067 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 3068 intel_encoder->pre_enable = intel_ddi_pre_enable;
3069 intel_encoder->disable = intel_disable_ddi;
3070 intel_encoder->post_disable = intel_ddi_post_disable;
3071 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3072 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 3073 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 3074 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 3075 intel_encoder->type = INTEL_OUTPUT_DDI;
3076 intel_encoder->power_domain = intel_port_to_power_domain(port);
3077 intel_encoder->port = port;
3078 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3079 intel_encoder->cloneable = 0;
00c09d70 3080
bcf53de4
SM		 3081 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3082 (DDI_BUF_PORT_REVERSAL |
3083 DDI_A_4_LANES);
3d2011cf
MK		 3084 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3085 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
00c09d70 3086
62b69566
ACO		 3087 switch (port) {
3088 case PORT_A:
3089 intel_dig_port->ddi_io_power_domain =
3090 POWER_DOMAIN_PORT_DDI_A_IO;
3091 break;
3092 case PORT_B:
3093 intel_dig_port->ddi_io_power_domain =
3094 POWER_DOMAIN_PORT_DDI_B_IO;
3095 break;
3096 case PORT_C:
3097 intel_dig_port->ddi_io_power_domain =
3098 POWER_DOMAIN_PORT_DDI_C_IO;
3099 break;
3100 case PORT_D:
3101 intel_dig_port->ddi_io_power_domain =
3102 POWER_DOMAIN_PORT_DDI_D_IO;
3103 break;
3104 case PORT_E:
3105 intel_dig_port->ddi_io_power_domain =
3106 POWER_DOMAIN_PORT_DDI_E_IO;
3107 break;
9787e835
RV		 3108 case PORT_F:
3109 intel_dig_port->ddi_io_power_domain =
3110 POWER_DOMAIN_PORT_DDI_F_IO;
3111 break;
62b69566
ACO		 3112 default:
3113 MISSING_CASE(port);
3114 }
3115
385e4de0
VS		 3116 intel_infoframe_init(intel_dig_port);
3117
f68d697e
CW		 3118 if (init_dp) {
3119 if (!intel_ddi_init_dp_connector(intel_dig_port))
3120 goto err;
13cf5504 3121
f68d697e 3122 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
ca4c3890 3123 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3124 }
21a8e6a4 3125
311a2094
PZ		 3126 /* In theory we don't need the encoder->type check, but leave it just in
3127 * case we have some really bad VBTs... */
f68d697e
CW		 3128 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3129 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3130 goto err;
21a8e6a4 3131 }
f68d697e 3132
ff662124
SS		 3133 if (init_lspcon) {
3134 if (lspcon_init(intel_dig_port))
3135 /* TODO: handle hdmi info frame part */
3136 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3137 port_name(port));
3138 else
3139 /*
3140 * LSPCON init faied, but DP init was success, so
3141 * lets try to drive as DP++ port.
3142 */
3143 DRM_ERROR("LSPCON init failed on port %c\n",
3144 port_name(port));
3145 }
3146
f68d697e
CW		 3147 return;
3148
3149err:
3150 drm_encoder_cleanup(encoder);
3151 kfree(intel_dig_port);
00c09d70 3152}
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