[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_device_info.h

/*
 * Copyright © 2014-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DEVICE_INFO_H_
#define _INTEL_DEVICE_INFO_H_

#include "intel_display.h"

struct drm_printer;
struct drm_i915_private;

/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	/* gen2 */
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	/* gen3 */
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
	/* gen4 */
	INTEL_I965G,
	INTEL_I965GM,
	INTEL_G45,
	INTEL_GM45,
	/* gen5 */
	INTEL_IRONLAKE,
	/* gen6 */
	INTEL_SANDYBRIDGE,
	/* gen7 */
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	/* gen8 */
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	/* gen9 */
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
	INTEL_COFFEELAKE,
	/* gen10 */
	INTEL_CANNONLAKE,
	INTEL_MAX_PLATFORMS
};

#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
	func(is_lp); \
	func(is_alpha_support); \
	/* Keep has_* in alphabetical order */ \
	func(has_64bit_reloc); \
	func(has_aliasing_ppgtt); \
	func(has_csr); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_reset_engine); \
	func(has_fbc); \
	func(has_fpga_dbg); \
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_guc_ct); \
	func(has_hotplug); \
	func(has_l3_dpf); \
	func(has_llc); \
	func(has_logical_ring_contexts); \
	func(has_logical_ring_preemption); \
	func(has_overlay); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
	func(has_snoop); \
	func(unfenced_needs_alignment); \
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
	func(supports_tv); \
	func(has_ipc);

struct sseu_dev_info {
	u8 slice_mask;
	u8 subslice_mask;
	u8 eu_total;
	u8 eu_per_subslice;
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
};

struct intel_device_info {
	u16 device_id;
	u16 gen_mask;

	u8 gen;
	u8 gt; /* GT number, 0 if undefined */
	u8 num_rings;
	u8 ring_mask; /* Rings supported by the HW */

	enum intel_platform platform;
	u32 platform_mask;

	u32 display_mmio_offset;

	u8 num_pipes;
	u8 num_sprites[I915_MAX_PIPES];
	u8 num_scalers[I915_MAX_PIPES];

	unsigned int page_sizes; /* page sizes supported by the HW */

#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
	u16 ddb_size; /* in blocks */

	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
	int cursor_offsets[I915_MAX_PIPES];

	/* Slice/subslice/EU info */
	struct sseu_dev_info sseu;

	u32 cs_timestamp_frequency_khz;

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
};

static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

const char *intel_platform_name(enum intel_platform platform);

void intel_device_info_runtime_init(struct intel_device_info *info);
void intel_device_info_dump(const struct intel_device_info *info,
			    struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_info *info,
				  struct drm_printer *p);
void intel_device_info_dump_runtime(const struct intel_device_info *info,
				    struct drm_printer *p);

#endif
Commit	Line	Data
b978520d MW	1	/*
	2	* Copyright © 2014-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DEVICE_INFO_H_
	26	#define _INTEL_DEVICE_INFO_H_
	27
	28	#include "intel_display.h"
	29
	30	struct drm_printer;
	31	struct drm_i915_private;
	32
	33	/* Keep in gen based order, and chronological order within a gen */
	34	enum intel_platform {
	35	INTEL_PLATFORM_UNINITIALIZED = 0,
	36	/* gen2 */
	37	INTEL_I830,
	38	INTEL_I845G,
	39	INTEL_I85X,
	40	INTEL_I865G,
	41	/* gen3 */
	42	INTEL_I915G,
	43	INTEL_I915GM,
	44	INTEL_I945G,
	45	INTEL_I945GM,
	46	INTEL_G33,
	47	INTEL_PINEVIEW,
	48	/* gen4 */
	49	INTEL_I965G,
	50	INTEL_I965GM,
	51	INTEL_G45,
	52	INTEL_GM45,
	53	/* gen5 */
	54	INTEL_IRONLAKE,
	55	/* gen6 */
	56	INTEL_SANDYBRIDGE,
	57	/* gen7 */
	58	INTEL_IVYBRIDGE,
	59	INTEL_VALLEYVIEW,
	60	INTEL_HASWELL,
	61	/* gen8 */
	62	INTEL_BROADWELL,
	63	INTEL_CHERRYVIEW,
	64	/* gen9 */
65	INTEL_SKYLAKE,
66	INTEL_BROXTON,
67	INTEL_KABYLAKE,
68	INTEL_GEMINILAKE,
69	INTEL_COFFEELAKE,
70	/* gen10 */
71	INTEL_CANNONLAKE,
72	INTEL_MAX_PLATFORMS
73	};
74
75	#define DEV_INFO_FOR_EACH_FLAG(func) \
76	func(is_mobile); \
77	func(is_lp); \
78	func(is_alpha_support); \
79	/* Keep has_* in alphabetical order */ \
80	func(has_64bit_reloc); \
81	func(has_aliasing_ppgtt); \
82	func(has_csr); \
83	func(has_ddi); \
84	func(has_dp_mst); \
85	func(has_reset_engine); \
86	func(has_fbc); \
87	func(has_fpga_dbg); \
88	func(has_full_ppgtt); \
89	func(has_full_48bit_ppgtt); \
90	func(has_gmch_display); \
91	func(has_guc); \
92	func(has_guc_ct); \
93	func(has_hotplug); \
94	func(has_l3_dpf); \
95	func(has_llc); \
96	func(has_logical_ring_contexts); \
97	func(has_logical_ring_preemption); \
98	func(has_overlay); \
99	func(has_pooled_eu); \
100	func(has_psr); \
101	func(has_rc6); \
102	func(has_rc6p); \
103	func(has_resource_streamer); \
104	func(has_runtime_pm); \
105	func(has_snoop); \
106	func(unfenced_needs_alignment); \
107	func(cursor_needs_physical); \
108	func(hws_needs_physical); \
109	func(overlay_needs_physical); \
110	func(supports_tv); \
111	func(has_ipc);
112
113	struct sseu_dev_info {
114	u8 slice_mask;
115	u8 subslice_mask;
116	u8 eu_total;
117	u8 eu_per_subslice;
118	u8 min_eu_in_pool;
119	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
120	u8 subslice_7eu[3];
121	u8 has_slice_pg:1;
122	u8 has_subslice_pg:1;
123	u8 has_eu_pg:1;
124	};
125
126	struct intel_device_info {
127	u16 device_id;
128	u16 gen_mask;
129
130	u8 gen;
131	u8 gt; /* GT number, 0 if undefined */
132	u8 num_rings;
133	u8 ring_mask; /* Rings supported by the HW */
134
135	enum intel_platform platform;
136	u32 platform_mask;
137
138	u32 display_mmio_offset;
139
140	u8 num_pipes;
141	u8 num_sprites[I915_MAX_PIPES];
142	u8 num_scalers[I915_MAX_PIPES];
143
144	unsigned int page_sizes; /* page sizes supported by the HW */
145
146	#define DEFINE_FLAG(name) u8 name:1
147	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
148	#undef DEFINE_FLAG
149	u16 ddb_size; /* in blocks */
150
151	/* Register offsets for the various display pipes and transcoders */
152	int pipe_offsets[I915_MAX_TRANSCODERS];
153	int trans_offsets[I915_MAX_TRANSCODERS];
154	int palette_offsets[I915_MAX_PIPES];
155	int cursor_offsets[I915_MAX_PIPES];
156
157	/* Slice/subslice/EU info */
158	struct sseu_dev_info sseu;
159
160	u32 cs_timestamp_frequency_khz;
161
162	struct color_luts {
163	u16 degamma_lut_size;
164	u16 gamma_lut_size;
165	} color;
166	};
167
168	static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
169	{
170	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
171	}
172
173	const char *intel_platform_name(enum intel_platform platform);
174
6a7e51f3	175	void intel_device_info_runtime_init(struct intel_device_info *info);
b978520d MW	176	void intel_device_info_dump(const struct intel_device_info *info,
	177	struct drm_printer *p);
	178	void intel_device_info_dump_flags(const struct intel_device_info *info,
	179	struct drm_printer *p);
5fbbe8d4 MW	180	void intel_device_info_dump_runtime(const struct intel_device_info *info,
5fbbe8d4 MW	181	struct drm_printer *p);
b978520d MW	182
b978520d MW	183	#endif