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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
4feed0eb | 1346 | enum intel_display_power_domain power_domain; |
b24e7179 | 1347 | |
b6b5d049 VS |
1348 | /* if we need the pipe quirk it must be always on */ |
1349 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1350 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1351 | state = true; |
1352 | ||
4feed0eb ID |
1353 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1354 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1355 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1356 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1357 | |
1358 | intel_display_power_put(dev_priv, power_domain); | |
1359 | } else { | |
1360 | cur_state = false; | |
69310161 PZ |
1361 | } |
1362 | ||
e2c719b7 | 1363 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1364 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1365 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1366 | } |
1367 | ||
931872fc CW |
1368 | static void assert_plane(struct drm_i915_private *dev_priv, |
1369 | enum plane plane, bool state) | |
b24e7179 | 1370 | { |
b24e7179 | 1371 | u32 val; |
931872fc | 1372 | bool cur_state; |
b24e7179 | 1373 | |
649636ef | 1374 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1375 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1376 | I915_STATE_WARN(cur_state != state, |
931872fc | 1377 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1378 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1379 | } |
1380 | ||
931872fc CW |
1381 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1382 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1383 | ||
b24e7179 JB |
1384 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1385 | enum pipe pipe) | |
1386 | { | |
653e1026 | 1387 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1388 | int i; |
b24e7179 | 1389 | |
653e1026 VS |
1390 | /* Primary planes are fixed to pipes on gen4+ */ |
1391 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1392 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1393 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1394 | "plane %c assertion failure, should be disabled but not\n", |
1395 | plane_name(pipe)); | |
19ec1358 | 1396 | return; |
28c05794 | 1397 | } |
19ec1358 | 1398 | |
b24e7179 | 1399 | /* Need to check both planes against the pipe */ |
055e393f | 1400 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1401 | u32 val = I915_READ(DSPCNTR(i)); |
1402 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1403 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1404 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1405 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1406 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1407 | } |
1408 | } | |
1409 | ||
19332d7a JB |
1410 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe) | |
1412 | { | |
20674eef | 1413 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1414 | int sprite; |
19332d7a | 1415 | |
7feb8b88 | 1416 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1417 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1418 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1419 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1420 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1421 | sprite, pipe_name(pipe)); | |
1422 | } | |
666a4537 | 1423 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1424 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1425 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1426 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1427 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1428 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1429 | } |
1430 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1431 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1432 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1433 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1434 | plane_name(pipe), pipe_name(pipe)); |
1435 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1436 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1437 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1439 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1440 | } |
1441 | } | |
1442 | ||
08c71e5e VS |
1443 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1444 | { | |
e2c719b7 | 1445 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1446 | drm_crtc_vblank_put(crtc); |
1447 | } | |
1448 | ||
89eff4be | 1449 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1450 | { |
1451 | u32 val; | |
1452 | bool enabled; | |
1453 | ||
e2c719b7 | 1454 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1455 | |
92f2584a JB |
1456 | val = I915_READ(PCH_DREF_CONTROL); |
1457 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1458 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1459 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1460 | } |
1461 | ||
ab9412ba DV |
1462 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1463 | enum pipe pipe) | |
92f2584a | 1464 | { |
92f2584a JB |
1465 | u32 val; |
1466 | bool enabled; | |
1467 | ||
649636ef | 1468 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1469 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1470 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1471 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1472 | pipe_name(pipe)); | |
92f2584a JB |
1473 | } |
1474 | ||
4e634389 KP |
1475 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1476 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1477 | { |
1478 | if ((val & DP_PORT_EN) == 0) | |
1479 | return false; | |
1480 | ||
1481 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1482 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1483 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1484 | return false; | |
44f37d1f CML |
1485 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1486 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1487 | return false; | |
f0575e92 KP |
1488 | } else { |
1489 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1490 | return false; | |
1491 | } | |
1492 | return true; | |
1493 | } | |
1494 | ||
1519b995 KP |
1495 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1496 | enum pipe pipe, u32 val) | |
1497 | { | |
dc0fa718 | 1498 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1499 | return false; |
1500 | ||
1501 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1502 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1503 | return false; |
44f37d1f CML |
1504 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1505 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1506 | return false; | |
1519b995 | 1507 | } else { |
dc0fa718 | 1508 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1509 | return false; |
1510 | } | |
1511 | return true; | |
1512 | } | |
1513 | ||
1514 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1515 | enum pipe pipe, u32 val) | |
1516 | { | |
1517 | if ((val & LVDS_PORT_EN) == 0) | |
1518 | return false; | |
1519 | ||
1520 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1521 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1522 | return false; | |
1523 | } else { | |
1524 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1525 | return false; | |
1526 | } | |
1527 | return true; | |
1528 | } | |
1529 | ||
1530 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1531 | enum pipe pipe, u32 val) | |
1532 | { | |
1533 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1534 | return false; | |
1535 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1536 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1537 | return false; | |
1538 | } else { | |
1539 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1540 | return false; | |
1541 | } | |
1542 | return true; | |
1543 | } | |
1544 | ||
291906f1 | 1545 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1546 | enum pipe pipe, i915_reg_t reg, |
1547 | u32 port_sel) | |
291906f1 | 1548 | { |
47a05eca | 1549 | u32 val = I915_READ(reg); |
e2c719b7 | 1550 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1551 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1552 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1553 | |
e2c719b7 | 1554 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1555 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1556 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1557 | } |
1558 | ||
1559 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1560 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1561 | { |
47a05eca | 1562 | u32 val = I915_READ(reg); |
e2c719b7 | 1563 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1564 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1565 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1566 | |
e2c719b7 | 1567 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1568 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1569 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1570 | } |
1571 | ||
1572 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1573 | enum pipe pipe) | |
1574 | { | |
291906f1 | 1575 | u32 val; |
291906f1 | 1576 | |
f0575e92 KP |
1577 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1578 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1579 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1580 | |
649636ef | 1581 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1582 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1583 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1584 | pipe_name(pipe)); |
291906f1 | 1585 | |
649636ef | 1586 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1587 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1588 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1589 | pipe_name(pipe)); |
291906f1 | 1590 | |
e2debe91 PZ |
1591 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1592 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1593 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1594 | } |
1595 | ||
d288f65f | 1596 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1597 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1598 | { |
426115cf DV |
1599 | struct drm_device *dev = crtc->base.dev; |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1601 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1602 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1603 | |
426115cf | 1604 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1605 | |
87442f73 | 1606 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1607 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1608 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1609 | |
426115cf DV |
1610 | I915_WRITE(reg, dpll); |
1611 | POSTING_READ(reg); | |
1612 | udelay(150); | |
1613 | ||
1614 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1615 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1616 | ||
d288f65f | 1617 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1618 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1619 | |
1620 | /* We do this three times for luck */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
426115cf | 1627 | I915_WRITE(reg, dpll); |
87442f73 DV |
1628 | POSTING_READ(reg); |
1629 | udelay(150); /* wait for warmup */ | |
1630 | } | |
1631 | ||
d288f65f | 1632 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1633 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1634 | { |
1635 | struct drm_device *dev = crtc->base.dev; | |
1636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1637 | int pipe = crtc->pipe; | |
1638 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1639 | u32 tmp; |
1640 | ||
1641 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1642 | ||
a580516d | 1643 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1644 | |
1645 | /* Enable back the 10bit clock to display controller */ | |
1646 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1647 | tmp |= DPIO_DCLKP_EN; | |
1648 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1649 | ||
54433e91 VS |
1650 | mutex_unlock(&dev_priv->sb_lock); |
1651 | ||
9d556c99 CML |
1652 | /* |
1653 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1654 | */ | |
1655 | udelay(1); | |
1656 | ||
1657 | /* Enable PLL */ | |
d288f65f | 1658 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1659 | |
1660 | /* Check PLL is locked */ | |
a11b0703 | 1661 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1662 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1663 | ||
a11b0703 | 1664 | /* not sure when this should be written */ |
d288f65f | 1665 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1666 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1667 | } |
1668 | ||
1c4e0274 VS |
1669 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1670 | { | |
1671 | struct intel_crtc *crtc; | |
1672 | int count = 0; | |
1673 | ||
1674 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1675 | count += crtc->base.state->active && |
409ee761 | 1676 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1677 | |
1678 | return count; | |
1679 | } | |
1680 | ||
66e3d5c0 | 1681 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1682 | { |
66e3d5c0 DV |
1683 | struct drm_device *dev = crtc->base.dev; |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1685 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1686 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1687 | |
66e3d5c0 | 1688 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1689 | |
63d7bbe9 | 1690 | /* No really, not for ILK+ */ |
3d13ef2e | 1691 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1692 | |
1693 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1694 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1695 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1696 | |
1c4e0274 VS |
1697 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1698 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1699 | /* | |
1700 | * It appears to be important that we don't enable this | |
1701 | * for the current pipe before otherwise configuring the | |
1702 | * PLL. No idea how this should be handled if multiple | |
1703 | * DVO outputs are enabled simultaneosly. | |
1704 | */ | |
1705 | dpll |= DPLL_DVO_2X_MODE; | |
1706 | I915_WRITE(DPLL(!crtc->pipe), | |
1707 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1708 | } | |
66e3d5c0 | 1709 | |
c2b63374 VS |
1710 | /* |
1711 | * Apparently we need to have VGA mode enabled prior to changing | |
1712 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1713 | * dividers, even though the register value does change. | |
1714 | */ | |
1715 | I915_WRITE(reg, 0); | |
1716 | ||
8e7a65aa VS |
1717 | I915_WRITE(reg, dpll); |
1718 | ||
66e3d5c0 DV |
1719 | /* Wait for the clocks to stabilize. */ |
1720 | POSTING_READ(reg); | |
1721 | udelay(150); | |
1722 | ||
1723 | if (INTEL_INFO(dev)->gen >= 4) { | |
1724 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1725 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1726 | } else { |
1727 | /* The pixel multiplier can only be updated once the | |
1728 | * DPLL is enabled and the clocks are stable. | |
1729 | * | |
1730 | * So write it again. | |
1731 | */ | |
1732 | I915_WRITE(reg, dpll); | |
1733 | } | |
63d7bbe9 JB |
1734 | |
1735 | /* We do this three times for luck */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1742 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1743 | POSTING_READ(reg); |
1744 | udelay(150); /* wait for warmup */ | |
1745 | } | |
1746 | ||
1747 | /** | |
50b44a44 | 1748 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1749 | * @dev_priv: i915 private structure |
1750 | * @pipe: pipe PLL to disable | |
1751 | * | |
1752 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1753 | * | |
1754 | * Note! This is for pre-ILK only. | |
1755 | */ | |
1c4e0274 | 1756 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1757 | { |
1c4e0274 VS |
1758 | struct drm_device *dev = crtc->base.dev; |
1759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1760 | enum pipe pipe = crtc->pipe; | |
1761 | ||
1762 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1763 | if (IS_I830(dev) && | |
409ee761 | 1764 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1765 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1766 | I915_WRITE(DPLL(PIPE_B), |
1767 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1768 | I915_WRITE(DPLL(PIPE_A), | |
1769 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1770 | } | |
1771 | ||
b6b5d049 VS |
1772 | /* Don't disable pipe or pipe PLLs if needed */ |
1773 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1774 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1775 | return; |
1776 | ||
1777 | /* Make sure the pipe isn't still relying on us */ | |
1778 | assert_pipe_disabled(dev_priv, pipe); | |
1779 | ||
b8afb911 | 1780 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1781 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1782 | } |
1783 | ||
f6071166 JB |
1784 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1785 | { | |
b8afb911 | 1786 | u32 val; |
f6071166 JB |
1787 | |
1788 | /* Make sure the pipe isn't still relying on us */ | |
1789 | assert_pipe_disabled(dev_priv, pipe); | |
1790 | ||
e5cbfbfb ID |
1791 | /* |
1792 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1793 | * The latter is needed for VGA hotplug / manual detection. | |
1794 | */ | |
b8afb911 | 1795 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1796 | if (pipe == PIPE_B) |
60bfe44f | 1797 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1798 | I915_WRITE(DPLL(pipe), val); |
1799 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1800 | |
1801 | } | |
1802 | ||
1803 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1804 | { | |
d752048d | 1805 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1806 | u32 val; |
1807 | ||
a11b0703 VS |
1808 | /* Make sure the pipe isn't still relying on us */ |
1809 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1810 | |
a11b0703 | 1811 | /* Set PLL en = 0 */ |
60bfe44f VS |
1812 | val = DPLL_SSC_REF_CLK_CHV | |
1813 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1814 | if (pipe != PIPE_A) |
1815 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1816 | I915_WRITE(DPLL(pipe), val); | |
1817 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1818 | |
a580516d | 1819 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1820 | |
1821 | /* Disable 10bit clock to display controller */ | |
1822 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1823 | val &= ~DPIO_DCLKP_EN; | |
1824 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1825 | ||
a580516d | 1826 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1827 | } |
1828 | ||
e4607fcf | 1829 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1830 | struct intel_digital_port *dport, |
1831 | unsigned int expected_mask) | |
89b667f8 JB |
1832 | { |
1833 | u32 port_mask; | |
f0f59a00 | 1834 | i915_reg_t dpll_reg; |
89b667f8 | 1835 | |
e4607fcf CML |
1836 | switch (dport->port) { |
1837 | case PORT_B: | |
89b667f8 | 1838 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1839 | dpll_reg = DPLL(0); |
e4607fcf CML |
1840 | break; |
1841 | case PORT_C: | |
89b667f8 | 1842 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1843 | dpll_reg = DPLL(0); |
9b6de0a1 | 1844 | expected_mask <<= 4; |
00fc31b7 CML |
1845 | break; |
1846 | case PORT_D: | |
1847 | port_mask = DPLL_PORTD_READY_MASK; | |
1848 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1849 | break; |
1850 | default: | |
1851 | BUG(); | |
1852 | } | |
89b667f8 | 1853 | |
9b6de0a1 VS |
1854 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1855 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1856 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1857 | } |
1858 | ||
b14b1055 DV |
1859 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1860 | { | |
1861 | struct drm_device *dev = crtc->base.dev; | |
1862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1863 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1864 | ||
be19f0ff CW |
1865 | if (WARN_ON(pll == NULL)) |
1866 | return; | |
1867 | ||
3e369b76 | 1868 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1869 | if (pll->active == 0) { |
1870 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1871 | WARN_ON(pll->on); | |
1872 | assert_shared_dpll_disabled(dev_priv, pll); | |
1873 | ||
1874 | pll->mode_set(dev_priv, pll); | |
1875 | } | |
1876 | } | |
1877 | ||
92f2584a | 1878 | /** |
85b3894f | 1879 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1880 | * @dev_priv: i915 private structure |
1881 | * @pipe: pipe PLL to enable | |
1882 | * | |
1883 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1884 | * drives the transcoder clock. | |
1885 | */ | |
85b3894f | 1886 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1887 | { |
3d13ef2e DL |
1888 | struct drm_device *dev = crtc->base.dev; |
1889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1890 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1891 | |
87a875bb | 1892 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1893 | return; |
1894 | ||
3e369b76 | 1895 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1896 | return; |
ee7b9f93 | 1897 | |
74dd6928 | 1898 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1899 | pll->name, pll->active, pll->on, |
e2b78267 | 1900 | crtc->base.base.id); |
92f2584a | 1901 | |
cdbd2316 DV |
1902 | if (pll->active++) { |
1903 | WARN_ON(!pll->on); | |
e9d6944e | 1904 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1905 | return; |
1906 | } | |
f4a091c7 | 1907 | WARN_ON(pll->on); |
ee7b9f93 | 1908 | |
bd2bb1b9 PZ |
1909 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1910 | ||
46edb027 | 1911 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1912 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1913 | pll->on = true; |
92f2584a JB |
1914 | } |
1915 | ||
f6daaec2 | 1916 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1917 | { |
3d13ef2e DL |
1918 | struct drm_device *dev = crtc->base.dev; |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1920 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1921 | |
92f2584a | 1922 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1923 | if (INTEL_INFO(dev)->gen < 5) |
1924 | return; | |
1925 | ||
eddfcbcd ML |
1926 | if (pll == NULL) |
1927 | return; | |
92f2584a | 1928 | |
eddfcbcd | 1929 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1930 | return; |
7a419866 | 1931 | |
46edb027 DV |
1932 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1933 | pll->name, pll->active, pll->on, | |
e2b78267 | 1934 | crtc->base.base.id); |
7a419866 | 1935 | |
48da64a8 | 1936 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1937 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1938 | return; |
1939 | } | |
1940 | ||
e9d6944e | 1941 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1942 | WARN_ON(!pll->on); |
cdbd2316 | 1943 | if (--pll->active) |
7a419866 | 1944 | return; |
ee7b9f93 | 1945 | |
46edb027 | 1946 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1947 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1948 | pll->on = false; |
bd2bb1b9 PZ |
1949 | |
1950 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1951 | } |
1952 | ||
b8a4f404 PZ |
1953 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1954 | enum pipe pipe) | |
040484af | 1955 | { |
23670b32 | 1956 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1957 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1959 | i915_reg_t reg; |
1960 | uint32_t val, pipeconf_val; | |
040484af JB |
1961 | |
1962 | /* PCH only available on ILK+ */ | |
55522f37 | 1963 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1964 | |
1965 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1966 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1967 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1968 | |
1969 | /* FDI must be feeding us bits for PCH ports */ | |
1970 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1971 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1972 | ||
23670b32 DV |
1973 | if (HAS_PCH_CPT(dev)) { |
1974 | /* Workaround: Set the timing override bit before enabling the | |
1975 | * pch transcoder. */ | |
1976 | reg = TRANS_CHICKEN2(pipe); | |
1977 | val = I915_READ(reg); | |
1978 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1979 | I915_WRITE(reg, val); | |
59c859d6 | 1980 | } |
23670b32 | 1981 | |
ab9412ba | 1982 | reg = PCH_TRANSCONF(pipe); |
040484af | 1983 | val = I915_READ(reg); |
5f7f726d | 1984 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1985 | |
1986 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1987 | /* | |
c5de7c6f VS |
1988 | * Make the BPC in transcoder be consistent with |
1989 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1990 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1991 | */ |
dfd07d72 | 1992 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1993 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1994 | val |= PIPECONF_8BPC; | |
1995 | else | |
1996 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1997 | } |
5f7f726d PZ |
1998 | |
1999 | val &= ~TRANS_INTERLACE_MASK; | |
2000 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2001 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2002 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2003 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2004 | else | |
2005 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2006 | else |
2007 | val |= TRANS_PROGRESSIVE; | |
2008 | ||
040484af JB |
2009 | I915_WRITE(reg, val | TRANS_ENABLE); |
2010 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2011 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2012 | } |
2013 | ||
8fb033d7 | 2014 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2015 | enum transcoder cpu_transcoder) |
040484af | 2016 | { |
8fb033d7 | 2017 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2018 | |
2019 | /* PCH only available on ILK+ */ | |
55522f37 | 2020 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2021 | |
8fb033d7 | 2022 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2023 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2024 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2025 | |
223a6fdf | 2026 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2027 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2028 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2029 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2030 | |
25f3ef11 | 2031 | val = TRANS_ENABLE; |
937bb610 | 2032 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2033 | |
9a76b1c6 PZ |
2034 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2035 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2036 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2037 | else |
2038 | val |= TRANS_PROGRESSIVE; | |
2039 | ||
ab9412ba DV |
2040 | I915_WRITE(LPT_TRANSCONF, val); |
2041 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2042 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2043 | } |
2044 | ||
b8a4f404 PZ |
2045 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2046 | enum pipe pipe) | |
040484af | 2047 | { |
23670b32 | 2048 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2049 | i915_reg_t reg; |
2050 | uint32_t val; | |
040484af JB |
2051 | |
2052 | /* FDI relies on the transcoder */ | |
2053 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2054 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2055 | ||
291906f1 JB |
2056 | /* Ports must be off as well */ |
2057 | assert_pch_ports_disabled(dev_priv, pipe); | |
2058 | ||
ab9412ba | 2059 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2060 | val = I915_READ(reg); |
2061 | val &= ~TRANS_ENABLE; | |
2062 | I915_WRITE(reg, val); | |
2063 | /* wait for PCH transcoder off, transcoder state */ | |
2064 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2065 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2066 | |
c465613b | 2067 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2068 | /* Workaround: Clear the timing override chicken bit again. */ |
2069 | reg = TRANS_CHICKEN2(pipe); | |
2070 | val = I915_READ(reg); | |
2071 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2072 | I915_WRITE(reg, val); | |
2073 | } | |
040484af JB |
2074 | } |
2075 | ||
ab4d966c | 2076 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2077 | { |
8fb033d7 PZ |
2078 | u32 val; |
2079 | ||
ab9412ba | 2080 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2081 | val &= ~TRANS_ENABLE; |
ab9412ba | 2082 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2083 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2084 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2085 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2086 | |
2087 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2088 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2089 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2090 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2091 | } |
2092 | ||
b24e7179 | 2093 | /** |
309cfea8 | 2094 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2095 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2096 | * |
0372264a | 2097 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2098 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2099 | */ |
e1fdc473 | 2100 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2101 | { |
0372264a PZ |
2102 | struct drm_device *dev = crtc->base.dev; |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2104 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2105 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2106 | enum pipe pch_transcoder; |
f0f59a00 | 2107 | i915_reg_t reg; |
b24e7179 JB |
2108 | u32 val; |
2109 | ||
9e2ee2dd VS |
2110 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2111 | ||
58c6eaa2 | 2112 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2113 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2114 | assert_sprites_disabled(dev_priv, pipe); |
2115 | ||
681e5811 | 2116 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2117 | pch_transcoder = TRANSCODER_A; |
2118 | else | |
2119 | pch_transcoder = pipe; | |
2120 | ||
b24e7179 JB |
2121 | /* |
2122 | * A pipe without a PLL won't actually be able to drive bits from | |
2123 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2124 | * need the check. | |
2125 | */ | |
50360403 | 2126 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2127 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2128 | assert_dsi_pll_enabled(dev_priv); |
2129 | else | |
2130 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2131 | else { |
6e3c9717 | 2132 | if (crtc->config->has_pch_encoder) { |
040484af | 2133 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2134 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2135 | assert_fdi_tx_pll_enabled(dev_priv, |
2136 | (enum pipe) cpu_transcoder); | |
040484af JB |
2137 | } |
2138 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2139 | } | |
b24e7179 | 2140 | |
702e7a56 | 2141 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2142 | val = I915_READ(reg); |
7ad25d48 | 2143 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2144 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2145 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2146 | return; |
7ad25d48 | 2147 | } |
00d70b15 CW |
2148 | |
2149 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2150 | POSTING_READ(reg); |
b7792d8b VS |
2151 | |
2152 | /* | |
2153 | * Until the pipe starts DSL will read as 0, which would cause | |
2154 | * an apparent vblank timestamp jump, which messes up also the | |
2155 | * frame count when it's derived from the timestamps. So let's | |
2156 | * wait for the pipe to start properly before we call | |
2157 | * drm_crtc_vblank_on() | |
2158 | */ | |
2159 | if (dev->max_vblank_count == 0 && | |
2160 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2161 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2162 | } |
2163 | ||
2164 | /** | |
309cfea8 | 2165 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2166 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2167 | * |
575f7ab7 VS |
2168 | * Disable the pipe of @crtc, making sure that various hardware |
2169 | * specific requirements are met, if applicable, e.g. plane | |
2170 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2171 | * |
2172 | * Will wait until the pipe has shut down before returning. | |
2173 | */ | |
575f7ab7 | 2174 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2175 | { |
575f7ab7 | 2176 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2177 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2178 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2179 | i915_reg_t reg; |
b24e7179 JB |
2180 | u32 val; |
2181 | ||
9e2ee2dd VS |
2182 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2183 | ||
b24e7179 JB |
2184 | /* |
2185 | * Make sure planes won't keep trying to pump pixels to us, | |
2186 | * or we might hang the display. | |
2187 | */ | |
2188 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2189 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2190 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2191 | |
702e7a56 | 2192 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2193 | val = I915_READ(reg); |
00d70b15 CW |
2194 | if ((val & PIPECONF_ENABLE) == 0) |
2195 | return; | |
2196 | ||
67adc644 VS |
2197 | /* |
2198 | * Double wide has implications for planes | |
2199 | * so best keep it disabled when not needed. | |
2200 | */ | |
6e3c9717 | 2201 | if (crtc->config->double_wide) |
67adc644 VS |
2202 | val &= ~PIPECONF_DOUBLE_WIDE; |
2203 | ||
2204 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2205 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2206 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2207 | val &= ~PIPECONF_ENABLE; |
2208 | ||
2209 | I915_WRITE(reg, val); | |
2210 | if ((val & PIPECONF_ENABLE) == 0) | |
2211 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2212 | } |
2213 | ||
693db184 CW |
2214 | static bool need_vtd_wa(struct drm_device *dev) |
2215 | { | |
2216 | #ifdef CONFIG_INTEL_IOMMU | |
2217 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2218 | return true; | |
2219 | #endif | |
2220 | return false; | |
2221 | } | |
2222 | ||
832be82f VS |
2223 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2224 | { | |
2225 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2226 | } | |
2227 | ||
7b49f948 VS |
2228 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2229 | uint64_t fb_modifier, unsigned int cpp) | |
2230 | { | |
2231 | switch (fb_modifier) { | |
2232 | case DRM_FORMAT_MOD_NONE: | |
2233 | return cpp; | |
2234 | case I915_FORMAT_MOD_X_TILED: | |
2235 | if (IS_GEN2(dev_priv)) | |
2236 | return 128; | |
2237 | else | |
2238 | return 512; | |
2239 | case I915_FORMAT_MOD_Y_TILED: | |
2240 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2241 | return 128; | |
2242 | else | |
2243 | return 512; | |
2244 | case I915_FORMAT_MOD_Yf_TILED: | |
2245 | switch (cpp) { | |
2246 | case 1: | |
2247 | return 64; | |
2248 | case 2: | |
2249 | case 4: | |
2250 | return 128; | |
2251 | case 8: | |
2252 | case 16: | |
2253 | return 256; | |
2254 | default: | |
2255 | MISSING_CASE(cpp); | |
2256 | return cpp; | |
2257 | } | |
2258 | break; | |
2259 | default: | |
2260 | MISSING_CASE(fb_modifier); | |
2261 | return cpp; | |
2262 | } | |
2263 | } | |
2264 | ||
832be82f VS |
2265 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2266 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2267 | { |
832be82f VS |
2268 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2269 | return 1; | |
2270 | else | |
2271 | return intel_tile_size(dev_priv) / | |
2272 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2273 | } |
2274 | ||
2275 | unsigned int | |
2276 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2277 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2278 | { |
832be82f VS |
2279 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2280 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2281 | ||
2282 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2283 | } |
2284 | ||
75c82a53 | 2285 | static void |
f64b98cd TU |
2286 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2287 | const struct drm_plane_state *plane_state) | |
2288 | { | |
832be82f | 2289 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
7723f47d | 2290 | struct intel_rotation_info *info = &view->params.rotated; |
d9b3288e | 2291 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2292 | |
f64b98cd TU |
2293 | *view = i915_ggtt_view_normal; |
2294 | ||
50470bb0 | 2295 | if (!plane_state) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
121920fa | 2298 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2299 | return; |
50470bb0 | 2300 | |
9abc4648 | 2301 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2302 | |
2303 | info->height = fb->height; | |
2304 | info->pixel_format = fb->pixel_format; | |
2305 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2306 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2307 | info->fb_modifier = fb->modifier[0]; |
2308 | ||
d9b3288e VS |
2309 | tile_size = intel_tile_size(dev_priv); |
2310 | ||
2311 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
b16bb01f | 2312 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
d9b3288e VS |
2313 | tile_height = tile_size / tile_width; |
2314 | ||
2315 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2316 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2317 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2318 | |
89e3e142 | 2319 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2320 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2321 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2322 | tile_height = tile_size / tile_width; | |
2323 | ||
2324 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2325 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2326 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2327 | } |
f64b98cd TU |
2328 | } |
2329 | ||
603525d7 | 2330 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2331 | { |
2332 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2333 | return 256 * 1024; | |
985b8bb4 | 2334 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2335 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2336 | return 128 * 1024; |
2337 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2338 | return 4 * 1024; | |
2339 | else | |
44c5905e | 2340 | return 0; |
4e9a86b6 VS |
2341 | } |
2342 | ||
603525d7 VS |
2343 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2344 | uint64_t fb_modifier) | |
2345 | { | |
2346 | switch (fb_modifier) { | |
2347 | case DRM_FORMAT_MOD_NONE: | |
2348 | return intel_linear_alignment(dev_priv); | |
2349 | case I915_FORMAT_MOD_X_TILED: | |
2350 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2351 | return 256 * 1024; | |
2352 | return 0; | |
2353 | case I915_FORMAT_MOD_Y_TILED: | |
2354 | case I915_FORMAT_MOD_Yf_TILED: | |
2355 | return 1 * 1024 * 1024; | |
2356 | default: | |
2357 | MISSING_CASE(fb_modifier); | |
2358 | return 0; | |
2359 | } | |
2360 | } | |
2361 | ||
127bd2ac | 2362 | int |
850c4cdc TU |
2363 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2364 | struct drm_framebuffer *fb, | |
7580d774 | 2365 | const struct drm_plane_state *plane_state) |
6b95a207 | 2366 | { |
850c4cdc | 2367 | struct drm_device *dev = fb->dev; |
ce453d81 | 2368 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2369 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2370 | struct i915_ggtt_view view; |
6b95a207 KH |
2371 | u32 alignment; |
2372 | int ret; | |
2373 | ||
ebcdd39e MR |
2374 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2375 | ||
603525d7 | 2376 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2377 | |
75c82a53 | 2378 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2379 | |
693db184 CW |
2380 | /* Note that the w/a also requires 64 PTE of padding following the |
2381 | * bo. We currently fill all unused PTE with the shadow page and so | |
2382 | * we should always have valid PTE following the scanout preventing | |
2383 | * the VT-d warning. | |
2384 | */ | |
2385 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2386 | alignment = 256 * 1024; | |
2387 | ||
d6dd6843 PZ |
2388 | /* |
2389 | * Global gtt pte registers are special registers which actually forward | |
2390 | * writes to a chunk of system memory. Which means that there is no risk | |
2391 | * that the register values disappear as soon as we call | |
2392 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2393 | * pin/unpin/fence and not more. | |
2394 | */ | |
2395 | intel_runtime_pm_get(dev_priv); | |
2396 | ||
7580d774 ML |
2397 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2398 | &view); | |
48b956c5 | 2399 | if (ret) |
b26a6b35 | 2400 | goto err_pm; |
6b95a207 KH |
2401 | |
2402 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2403 | * fence, whereas 965+ only requires a fence if using | |
2404 | * framebuffer compression. For simplicity, we always install | |
2405 | * a fence as the cost is not that onerous. | |
2406 | */ | |
9807216f VK |
2407 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2408 | ret = i915_gem_object_get_fence(obj); | |
2409 | if (ret == -EDEADLK) { | |
2410 | /* | |
2411 | * -EDEADLK means there are no free fences | |
2412 | * no pending flips. | |
2413 | * | |
2414 | * This is propagated to atomic, but it uses | |
2415 | * -EDEADLK to force a locking recovery, so | |
2416 | * change the returned error to -EBUSY. | |
2417 | */ | |
2418 | ret = -EBUSY; | |
2419 | goto err_unpin; | |
2420 | } else if (ret) | |
2421 | goto err_unpin; | |
1690e1eb | 2422 | |
9807216f VK |
2423 | i915_gem_object_pin_fence(obj); |
2424 | } | |
6b95a207 | 2425 | |
d6dd6843 | 2426 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2427 | return 0; |
48b956c5 CW |
2428 | |
2429 | err_unpin: | |
f64b98cd | 2430 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2431 | err_pm: |
d6dd6843 | 2432 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2433 | return ret; |
6b95a207 KH |
2434 | } |
2435 | ||
82bc3b2d TU |
2436 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2437 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2438 | { |
82bc3b2d | 2439 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2440 | struct i915_ggtt_view view; |
82bc3b2d | 2441 | |
ebcdd39e MR |
2442 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2443 | ||
75c82a53 | 2444 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2445 | |
9807216f VK |
2446 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2447 | i915_gem_object_unpin_fence(obj); | |
2448 | ||
f64b98cd | 2449 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2450 | } |
2451 | ||
c2c75131 DV |
2452 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2453 | * is assumed to be a power-of-two. */ | |
54ea9da8 VS |
2454 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2455 | int *x, int *y, | |
2456 | uint64_t fb_modifier, | |
2457 | unsigned int cpp, | |
2458 | unsigned int pitch) | |
c2c75131 | 2459 | { |
b5c65338 | 2460 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2461 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2462 | unsigned int tile_rows, tiles; |
c2c75131 | 2463 | |
d843310d VS |
2464 | tile_size = intel_tile_size(dev_priv); |
2465 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2466 | tile_height = tile_size / tile_width; | |
2467 | ||
2468 | tile_rows = *y / tile_height; | |
2469 | *y %= tile_height; | |
c2c75131 | 2470 | |
d843310d VS |
2471 | tiles = *x / (tile_width/cpp); |
2472 | *x %= tile_width/cpp; | |
bc752862 | 2473 | |
d843310d | 2474 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2475 | } else { |
4e9a86b6 | 2476 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2477 | unsigned int offset; |
2478 | ||
2479 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2480 | *y = (offset & alignment) / pitch; |
2481 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2482 | return offset & ~alignment; | |
bc752862 | 2483 | } |
c2c75131 DV |
2484 | } |
2485 | ||
b35d63fa | 2486 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2487 | { |
2488 | switch (format) { | |
2489 | case DISPPLANE_8BPP: | |
2490 | return DRM_FORMAT_C8; | |
2491 | case DISPPLANE_BGRX555: | |
2492 | return DRM_FORMAT_XRGB1555; | |
2493 | case DISPPLANE_BGRX565: | |
2494 | return DRM_FORMAT_RGB565; | |
2495 | default: | |
2496 | case DISPPLANE_BGRX888: | |
2497 | return DRM_FORMAT_XRGB8888; | |
2498 | case DISPPLANE_RGBX888: | |
2499 | return DRM_FORMAT_XBGR8888; | |
2500 | case DISPPLANE_BGRX101010: | |
2501 | return DRM_FORMAT_XRGB2101010; | |
2502 | case DISPPLANE_RGBX101010: | |
2503 | return DRM_FORMAT_XBGR2101010; | |
2504 | } | |
2505 | } | |
2506 | ||
bc8d7dff DL |
2507 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2508 | { | |
2509 | switch (format) { | |
2510 | case PLANE_CTL_FORMAT_RGB_565: | |
2511 | return DRM_FORMAT_RGB565; | |
2512 | default: | |
2513 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2514 | if (rgb_order) { | |
2515 | if (alpha) | |
2516 | return DRM_FORMAT_ABGR8888; | |
2517 | else | |
2518 | return DRM_FORMAT_XBGR8888; | |
2519 | } else { | |
2520 | if (alpha) | |
2521 | return DRM_FORMAT_ARGB8888; | |
2522 | else | |
2523 | return DRM_FORMAT_XRGB8888; | |
2524 | } | |
2525 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2526 | if (rgb_order) | |
2527 | return DRM_FORMAT_XBGR2101010; | |
2528 | else | |
2529 | return DRM_FORMAT_XRGB2101010; | |
2530 | } | |
2531 | } | |
2532 | ||
5724dbd1 | 2533 | static bool |
f6936e29 DV |
2534 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2535 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2536 | { |
2537 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2538 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2539 | struct drm_i915_gem_object *obj = NULL; |
2540 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2541 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2542 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2543 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2544 | PAGE_SIZE); | |
2545 | ||
2546 | size_aligned -= base_aligned; | |
46f297fb | 2547 | |
ff2652ea CW |
2548 | if (plane_config->size == 0) |
2549 | return false; | |
2550 | ||
3badb49f PZ |
2551 | /* If the FB is too big, just don't use it since fbdev is not very |
2552 | * important and we should probably use that space with FBC or other | |
2553 | * features. */ | |
2554 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2555 | return false; | |
2556 | ||
12c83d99 TU |
2557 | mutex_lock(&dev->struct_mutex); |
2558 | ||
f37b5c2b DV |
2559 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2560 | base_aligned, | |
2561 | base_aligned, | |
2562 | size_aligned); | |
12c83d99 TU |
2563 | if (!obj) { |
2564 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2565 | return false; |
12c83d99 | 2566 | } |
46f297fb | 2567 | |
49af449b DL |
2568 | obj->tiling_mode = plane_config->tiling; |
2569 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2570 | obj->stride = fb->pitches[0]; |
46f297fb | 2571 | |
6bf129df DL |
2572 | mode_cmd.pixel_format = fb->pixel_format; |
2573 | mode_cmd.width = fb->width; | |
2574 | mode_cmd.height = fb->height; | |
2575 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2576 | mode_cmd.modifier[0] = fb->modifier[0]; |
2577 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2578 | |
6bf129df | 2579 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2580 | &mode_cmd, obj)) { |
46f297fb JB |
2581 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2582 | goto out_unref_obj; | |
2583 | } | |
12c83d99 | 2584 | |
46f297fb | 2585 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2586 | |
f6936e29 | 2587 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2588 | return true; |
46f297fb JB |
2589 | |
2590 | out_unref_obj: | |
2591 | drm_gem_object_unreference(&obj->base); | |
2592 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2593 | return false; |
2594 | } | |
2595 | ||
afd65eb4 MR |
2596 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2597 | static void | |
2598 | update_state_fb(struct drm_plane *plane) | |
2599 | { | |
2600 | if (plane->fb == plane->state->fb) | |
2601 | return; | |
2602 | ||
2603 | if (plane->state->fb) | |
2604 | drm_framebuffer_unreference(plane->state->fb); | |
2605 | plane->state->fb = plane->fb; | |
2606 | if (plane->state->fb) | |
2607 | drm_framebuffer_reference(plane->state->fb); | |
2608 | } | |
2609 | ||
5724dbd1 | 2610 | static void |
f6936e29 DV |
2611 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2612 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2613 | { |
2614 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2615 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2616 | struct drm_crtc *c; |
2617 | struct intel_crtc *i; | |
2ff8fde1 | 2618 | struct drm_i915_gem_object *obj; |
88595ac9 | 2619 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2620 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2621 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2622 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2623 | struct intel_plane_state *intel_state = |
2624 | to_intel_plane_state(plane_state); | |
88595ac9 | 2625 | struct drm_framebuffer *fb; |
484b41dd | 2626 | |
2d14030b | 2627 | if (!plane_config->fb) |
484b41dd JB |
2628 | return; |
2629 | ||
f6936e29 | 2630 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2631 | fb = &plane_config->fb->base; |
2632 | goto valid_fb; | |
f55548b5 | 2633 | } |
484b41dd | 2634 | |
2d14030b | 2635 | kfree(plane_config->fb); |
484b41dd JB |
2636 | |
2637 | /* | |
2638 | * Failed to alloc the obj, check to see if we should share | |
2639 | * an fb with another CRTC instead | |
2640 | */ | |
70e1e0ec | 2641 | for_each_crtc(dev, c) { |
484b41dd JB |
2642 | i = to_intel_crtc(c); |
2643 | ||
2644 | if (c == &intel_crtc->base) | |
2645 | continue; | |
2646 | ||
2ff8fde1 MR |
2647 | if (!i->active) |
2648 | continue; | |
2649 | ||
88595ac9 DV |
2650 | fb = c->primary->fb; |
2651 | if (!fb) | |
484b41dd JB |
2652 | continue; |
2653 | ||
88595ac9 | 2654 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2655 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2656 | drm_framebuffer_reference(fb); |
2657 | goto valid_fb; | |
484b41dd JB |
2658 | } |
2659 | } | |
88595ac9 | 2660 | |
200757f5 MR |
2661 | /* |
2662 | * We've failed to reconstruct the BIOS FB. Current display state | |
2663 | * indicates that the primary plane is visible, but has a NULL FB, | |
2664 | * which will lead to problems later if we don't fix it up. The | |
2665 | * simplest solution is to just disable the primary plane now and | |
2666 | * pretend the BIOS never had it enabled. | |
2667 | */ | |
2668 | to_intel_plane_state(plane_state)->visible = false; | |
2669 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2670 | intel_pre_disable_primary(&intel_crtc->base); | |
2671 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2672 | ||
88595ac9 DV |
2673 | return; |
2674 | ||
2675 | valid_fb: | |
f44e2659 VS |
2676 | plane_state->src_x = 0; |
2677 | plane_state->src_y = 0; | |
be5651f2 ML |
2678 | plane_state->src_w = fb->width << 16; |
2679 | plane_state->src_h = fb->height << 16; | |
2680 | ||
f44e2659 VS |
2681 | plane_state->crtc_x = 0; |
2682 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2683 | plane_state->crtc_w = fb->width; |
2684 | plane_state->crtc_h = fb->height; | |
2685 | ||
0a8d8a86 MR |
2686 | intel_state->src.x1 = plane_state->src_x; |
2687 | intel_state->src.y1 = plane_state->src_y; | |
2688 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2689 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2690 | intel_state->dst.x1 = plane_state->crtc_x; | |
2691 | intel_state->dst.y1 = plane_state->crtc_y; | |
2692 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2693 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2694 | ||
88595ac9 DV |
2695 | obj = intel_fb_obj(fb); |
2696 | if (obj->tiling_mode != I915_TILING_NONE) | |
2697 | dev_priv->preserve_bios_swizzle = true; | |
2698 | ||
be5651f2 ML |
2699 | drm_framebuffer_reference(fb); |
2700 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2701 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2702 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2703 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2704 | } |
2705 | ||
a8d201af ML |
2706 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2707 | const struct intel_crtc_state *crtc_state, | |
2708 | const struct intel_plane_state *plane_state) | |
81255565 | 2709 | { |
a8d201af | 2710 | struct drm_device *dev = primary->dev; |
81255565 | 2711 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2713 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2714 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2715 | int plane = intel_crtc->plane; |
54ea9da8 | 2716 | u32 linear_offset; |
81255565 | 2717 | u32 dspcntr; |
f0f59a00 | 2718 | i915_reg_t reg = DSPCNTR(plane); |
ac484963 | 2719 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2720 | int x = plane_state->src.x1 >> 16; |
2721 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2722 | |
f45651ba VS |
2723 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2724 | ||
fdd508a6 | 2725 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2726 | |
2727 | if (INTEL_INFO(dev)->gen < 4) { | |
2728 | if (intel_crtc->pipe == PIPE_B) | |
2729 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2730 | ||
2731 | /* pipesrc and dspsize control the size that is scaled from, | |
2732 | * which should always be the user's requested size. | |
2733 | */ | |
2734 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2735 | ((crtc_state->pipe_src_h - 1) << 16) | |
2736 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2737 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2738 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2739 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2740 | ((crtc_state->pipe_src_h - 1) << 16) | |
2741 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2742 | I915_WRITE(PRIMPOS(plane), 0); |
2743 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2744 | } |
81255565 | 2745 | |
57779d06 VS |
2746 | switch (fb->pixel_format) { |
2747 | case DRM_FORMAT_C8: | |
81255565 JB |
2748 | dspcntr |= DISPPLANE_8BPP; |
2749 | break; | |
57779d06 | 2750 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2751 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2752 | break; |
57779d06 VS |
2753 | case DRM_FORMAT_RGB565: |
2754 | dspcntr |= DISPPLANE_BGRX565; | |
2755 | break; | |
2756 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2757 | dspcntr |= DISPPLANE_BGRX888; |
2758 | break; | |
2759 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2760 | dspcntr |= DISPPLANE_RGBX888; |
2761 | break; | |
2762 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2763 | dspcntr |= DISPPLANE_BGRX101010; |
2764 | break; | |
2765 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2766 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2767 | break; |
2768 | default: | |
baba133a | 2769 | BUG(); |
81255565 | 2770 | } |
57779d06 | 2771 | |
f45651ba VS |
2772 | if (INTEL_INFO(dev)->gen >= 4 && |
2773 | obj->tiling_mode != I915_TILING_NONE) | |
2774 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2775 | |
de1aa629 VS |
2776 | if (IS_G4X(dev)) |
2777 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2778 | ||
ac484963 | 2779 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2780 | |
c2c75131 DV |
2781 | if (INTEL_INFO(dev)->gen >= 4) { |
2782 | intel_crtc->dspaddr_offset = | |
ce1e5c14 | 2783 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2784 | fb->modifier[0], cpp, |
ce1e5c14 | 2785 | fb->pitches[0]); |
c2c75131 DV |
2786 | linear_offset -= intel_crtc->dspaddr_offset; |
2787 | } else { | |
e506a0c6 | 2788 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2789 | } |
e506a0c6 | 2790 | |
a8d201af | 2791 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2792 | dspcntr |= DISPPLANE_ROTATE_180; |
2793 | ||
a8d201af ML |
2794 | x += (crtc_state->pipe_src_w - 1); |
2795 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2796 | |
2797 | /* Finding the last pixel of the last line of the display | |
2798 | data and adding to linear_offset*/ | |
2799 | linear_offset += | |
a8d201af | 2800 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2801 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2802 | } |
2803 | ||
2db3366b PZ |
2804 | intel_crtc->adjusted_x = x; |
2805 | intel_crtc->adjusted_y = y; | |
2806 | ||
48404c1e SJ |
2807 | I915_WRITE(reg, dspcntr); |
2808 | ||
01f2c773 | 2809 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2810 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2811 | I915_WRITE(DSPSURF(plane), |
2812 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2813 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2814 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2815 | } else |
f343c5f6 | 2816 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2817 | POSTING_READ(reg); |
17638cd6 JB |
2818 | } |
2819 | ||
a8d201af ML |
2820 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2821 | struct drm_crtc *crtc) | |
17638cd6 JB |
2822 | { |
2823 | struct drm_device *dev = crtc->dev; | |
2824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2826 | int plane = intel_crtc->plane; |
f45651ba | 2827 | |
a8d201af ML |
2828 | I915_WRITE(DSPCNTR(plane), 0); |
2829 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2830 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2831 | else |
2832 | I915_WRITE(DSPADDR(plane), 0); | |
2833 | POSTING_READ(DSPCNTR(plane)); | |
2834 | } | |
c9ba6fad | 2835 | |
a8d201af ML |
2836 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2837 | const struct intel_crtc_state *crtc_state, | |
2838 | const struct intel_plane_state *plane_state) | |
2839 | { | |
2840 | struct drm_device *dev = primary->dev; | |
2841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2843 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2844 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2845 | int plane = intel_crtc->plane; | |
54ea9da8 | 2846 | u32 linear_offset; |
a8d201af ML |
2847 | u32 dspcntr; |
2848 | i915_reg_t reg = DSPCNTR(plane); | |
ac484963 | 2849 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2850 | int x = plane_state->src.x1 >> 16; |
2851 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2852 | |
f45651ba | 2853 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2854 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2855 | |
2856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2857 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2858 | |
57779d06 VS |
2859 | switch (fb->pixel_format) { |
2860 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2861 | dspcntr |= DISPPLANE_8BPP; |
2862 | break; | |
57779d06 VS |
2863 | case DRM_FORMAT_RGB565: |
2864 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2865 | break; |
57779d06 | 2866 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2867 | dspcntr |= DISPPLANE_BGRX888; |
2868 | break; | |
2869 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2870 | dspcntr |= DISPPLANE_RGBX888; |
2871 | break; | |
2872 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2873 | dspcntr |= DISPPLANE_BGRX101010; |
2874 | break; | |
2875 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2876 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2877 | break; |
2878 | default: | |
baba133a | 2879 | BUG(); |
17638cd6 JB |
2880 | } |
2881 | ||
2882 | if (obj->tiling_mode != I915_TILING_NONE) | |
2883 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2884 | |
f45651ba | 2885 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2886 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2887 | |
ac484963 | 2888 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2889 | intel_crtc->dspaddr_offset = |
ce1e5c14 | 2890 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2891 | fb->modifier[0], cpp, |
ce1e5c14 | 2892 | fb->pitches[0]); |
c2c75131 | 2893 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2894 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2895 | dspcntr |= DISPPLANE_ROTATE_180; |
2896 | ||
2897 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2898 | x += (crtc_state->pipe_src_w - 1); |
2899 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2900 | |
2901 | /* Finding the last pixel of the last line of the display | |
2902 | data and adding to linear_offset*/ | |
2903 | linear_offset += | |
a8d201af | 2904 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2905 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2906 | } |
2907 | } | |
2908 | ||
2db3366b PZ |
2909 | intel_crtc->adjusted_x = x; |
2910 | intel_crtc->adjusted_y = y; | |
2911 | ||
48404c1e | 2912 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2913 | |
01f2c773 | 2914 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2915 | I915_WRITE(DSPSURF(plane), |
2916 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2917 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2918 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2919 | } else { | |
2920 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2921 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2922 | } | |
17638cd6 | 2923 | POSTING_READ(reg); |
17638cd6 JB |
2924 | } |
2925 | ||
7b49f948 VS |
2926 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2927 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2928 | { |
7b49f948 | 2929 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2930 | return 64; |
7b49f948 VS |
2931 | } else { |
2932 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2933 | ||
2934 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2935 | } |
2936 | } | |
2937 | ||
44eb0cb9 MK |
2938 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2939 | struct drm_i915_gem_object *obj, | |
2940 | unsigned int plane) | |
121920fa | 2941 | { |
ce7f1728 | 2942 | struct i915_ggtt_view view; |
dedf278c | 2943 | struct i915_vma *vma; |
44eb0cb9 | 2944 | u64 offset; |
121920fa | 2945 | |
e7941294 | 2946 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
ce7f1728 | 2947 | intel_plane->base.state); |
121920fa | 2948 | |
ce7f1728 | 2949 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2950 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2951 | view.type)) |
dedf278c TU |
2952 | return -1; |
2953 | ||
44eb0cb9 | 2954 | offset = vma->node.start; |
dedf278c TU |
2955 | |
2956 | if (plane == 1) { | |
7723f47d | 2957 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2958 | PAGE_SIZE; |
2959 | } | |
2960 | ||
44eb0cb9 MK |
2961 | WARN_ON(upper_32_bits(offset)); |
2962 | ||
2963 | return lower_32_bits(offset); | |
121920fa TU |
2964 | } |
2965 | ||
e435d6e5 ML |
2966 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2967 | { | |
2968 | struct drm_device *dev = intel_crtc->base.dev; | |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2970 | ||
2971 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2972 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2973 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2974 | } |
2975 | ||
a1b2278e CK |
2976 | /* |
2977 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2978 | */ | |
0583236e | 2979 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2980 | { |
a1b2278e CK |
2981 | struct intel_crtc_scaler_state *scaler_state; |
2982 | int i; | |
2983 | ||
a1b2278e CK |
2984 | scaler_state = &intel_crtc->config->scaler_state; |
2985 | ||
2986 | /* loop through and disable scalers that aren't in use */ | |
2987 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2988 | if (!scaler_state->scalers[i].in_use) |
2989 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2990 | } |
2991 | } | |
2992 | ||
6156a456 | 2993 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2994 | { |
6156a456 | 2995 | switch (pixel_format) { |
d161cf7a | 2996 | case DRM_FORMAT_C8: |
c34ce3d1 | 2997 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2998 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2999 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3000 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3001 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3002 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3003 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3004 | /* |
3005 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3006 | * to be already pre-multiplied. We need to add a knob (or a different | |
3007 | * DRM_FORMAT) for user-space to configure that. | |
3008 | */ | |
f75fb42a | 3009 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3011 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3012 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3014 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3015 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3017 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3018 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3019 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3020 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3021 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3022 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3023 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3024 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3025 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3026 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3027 | default: |
4249eeef | 3028 | MISSING_CASE(pixel_format); |
70d21f0e | 3029 | } |
8cfcba41 | 3030 | |
c34ce3d1 | 3031 | return 0; |
6156a456 | 3032 | } |
70d21f0e | 3033 | |
6156a456 CK |
3034 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3035 | { | |
6156a456 | 3036 | switch (fb_modifier) { |
30af77c4 | 3037 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3038 | break; |
30af77c4 | 3039 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3040 | return PLANE_CTL_TILED_X; |
b321803d | 3041 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3042 | return PLANE_CTL_TILED_Y; |
b321803d | 3043 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3044 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3045 | default: |
6156a456 | 3046 | MISSING_CASE(fb_modifier); |
70d21f0e | 3047 | } |
8cfcba41 | 3048 | |
c34ce3d1 | 3049 | return 0; |
6156a456 | 3050 | } |
70d21f0e | 3051 | |
6156a456 CK |
3052 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3053 | { | |
3b7a5119 | 3054 | switch (rotation) { |
6156a456 CK |
3055 | case BIT(DRM_ROTATE_0): |
3056 | break; | |
1e8df167 SJ |
3057 | /* |
3058 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3059 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3060 | */ | |
3b7a5119 | 3061 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3062 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3063 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3064 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3065 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3066 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3067 | default: |
3068 | MISSING_CASE(rotation); | |
3069 | } | |
3070 | ||
c34ce3d1 | 3071 | return 0; |
6156a456 CK |
3072 | } |
3073 | ||
a8d201af ML |
3074 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3075 | const struct intel_crtc_state *crtc_state, | |
3076 | const struct intel_plane_state *plane_state) | |
6156a456 | 3077 | { |
a8d201af | 3078 | struct drm_device *dev = plane->dev; |
6156a456 | 3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3081 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3082 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3083 | int pipe = intel_crtc->pipe; |
3084 | u32 plane_ctl, stride_div, stride; | |
3085 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3086 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3087 | int x_offset, y_offset; |
44eb0cb9 | 3088 | u32 surf_addr; |
a8d201af ML |
3089 | int scaler_id = plane_state->scaler_id; |
3090 | int src_x = plane_state->src.x1 >> 16; | |
3091 | int src_y = plane_state->src.y1 >> 16; | |
3092 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3093 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3094 | int dst_x = plane_state->dst.x1; | |
3095 | int dst_y = plane_state->dst.y1; | |
3096 | int dst_w = drm_rect_width(&plane_state->dst); | |
3097 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3098 | |
6156a456 CK |
3099 | plane_ctl = PLANE_CTL_ENABLE | |
3100 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3101 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3102 | ||
3103 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3104 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3105 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3106 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3107 | ||
7b49f948 | 3108 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3109 | fb->pixel_format); |
dedf278c | 3110 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3111 | |
a42e5a23 PZ |
3112 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3113 | ||
3b7a5119 | 3114 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3115 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3116 | ||
3b7a5119 | 3117 | /* stride = Surface height in tiles */ |
832be82f | 3118 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3119 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3120 | x_offset = stride * tile_height - src_y - src_h; |
3121 | y_offset = src_x; | |
6156a456 | 3122 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3123 | } else { |
3124 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3125 | x_offset = src_x; |
3126 | y_offset = src_y; | |
6156a456 | 3127 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3128 | } |
3129 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3130 | |
2db3366b PZ |
3131 | intel_crtc->adjusted_x = x_offset; |
3132 | intel_crtc->adjusted_y = y_offset; | |
3133 | ||
70d21f0e | 3134 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3135 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3136 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3137 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3138 | |
3139 | if (scaler_id >= 0) { | |
3140 | uint32_t ps_ctrl = 0; | |
3141 | ||
3142 | WARN_ON(!dst_w || !dst_h); | |
3143 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3144 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3145 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3146 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3147 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3148 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3149 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3150 | } else { | |
3151 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3152 | } | |
3153 | ||
121920fa | 3154 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3155 | |
3156 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3157 | } | |
3158 | ||
a8d201af ML |
3159 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3160 | struct drm_crtc *crtc) | |
17638cd6 JB |
3161 | { |
3162 | struct drm_device *dev = crtc->dev; | |
3163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3164 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3165 | |
a8d201af ML |
3166 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3167 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3168 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3169 | } | |
29b9bde6 | 3170 | |
a8d201af ML |
3171 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3172 | static int | |
3173 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3174 | int x, int y, enum mode_set_atomic state) | |
3175 | { | |
3176 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3177 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3178 | ||
3179 | return -ENODEV; | |
81255565 JB |
3180 | } |
3181 | ||
7514747d | 3182 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3183 | { |
96a02917 VS |
3184 | struct drm_crtc *crtc; |
3185 | ||
70e1e0ec | 3186 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3188 | enum plane plane = intel_crtc->plane; | |
3189 | ||
3190 | intel_prepare_page_flip(dev, plane); | |
3191 | intel_finish_page_flip_plane(dev, plane); | |
3192 | } | |
7514747d VS |
3193 | } |
3194 | ||
3195 | static void intel_update_primary_planes(struct drm_device *dev) | |
3196 | { | |
7514747d | 3197 | struct drm_crtc *crtc; |
96a02917 | 3198 | |
70e1e0ec | 3199 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3200 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3201 | struct intel_plane_state *plane_state; | |
96a02917 | 3202 | |
11c22da6 | 3203 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3204 | plane_state = to_intel_plane_state(plane->base.state); |
3205 | ||
a8d201af ML |
3206 | if (plane_state->visible) |
3207 | plane->update_plane(&plane->base, | |
3208 | to_intel_crtc_state(crtc->state), | |
3209 | plane_state); | |
11c22da6 ML |
3210 | |
3211 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3212 | } |
3213 | } | |
3214 | ||
7514747d VS |
3215 | void intel_prepare_reset(struct drm_device *dev) |
3216 | { | |
3217 | /* no reset support for gen2 */ | |
3218 | if (IS_GEN2(dev)) | |
3219 | return; | |
3220 | ||
3221 | /* reset doesn't touch the display */ | |
3222 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3223 | return; | |
3224 | ||
3225 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3226 | /* |
3227 | * Disabling the crtcs gracefully seems nicer. Also the | |
3228 | * g33 docs say we should at least disable all the planes. | |
3229 | */ | |
6b72d486 | 3230 | intel_display_suspend(dev); |
7514747d VS |
3231 | } |
3232 | ||
3233 | void intel_finish_reset(struct drm_device *dev) | |
3234 | { | |
3235 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3236 | ||
3237 | /* | |
3238 | * Flips in the rings will be nuked by the reset, | |
3239 | * so complete all pending flips so that user space | |
3240 | * will get its events and not get stuck. | |
3241 | */ | |
3242 | intel_complete_page_flips(dev); | |
3243 | ||
3244 | /* no reset support for gen2 */ | |
3245 | if (IS_GEN2(dev)) | |
3246 | return; | |
3247 | ||
3248 | /* reset doesn't touch the display */ | |
3249 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3250 | /* | |
3251 | * Flips in the rings have been nuked by the reset, | |
3252 | * so update the base address of all primary | |
3253 | * planes to the the last fb to make sure we're | |
3254 | * showing the correct fb after a reset. | |
11c22da6 ML |
3255 | * |
3256 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3257 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3258 | */ |
3259 | intel_update_primary_planes(dev); | |
3260 | return; | |
3261 | } | |
3262 | ||
3263 | /* | |
3264 | * The display has been reset as well, | |
3265 | * so need a full re-initialization. | |
3266 | */ | |
3267 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3268 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3269 | ||
3270 | intel_modeset_init_hw(dev); | |
3271 | ||
3272 | spin_lock_irq(&dev_priv->irq_lock); | |
3273 | if (dev_priv->display.hpd_irq_setup) | |
3274 | dev_priv->display.hpd_irq_setup(dev); | |
3275 | spin_unlock_irq(&dev_priv->irq_lock); | |
3276 | ||
043e9bda | 3277 | intel_display_resume(dev); |
7514747d VS |
3278 | |
3279 | intel_hpd_init(dev_priv); | |
3280 | ||
3281 | drm_modeset_unlock_all(dev); | |
3282 | } | |
3283 | ||
7d5e3799 CW |
3284 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3285 | { | |
3286 | struct drm_device *dev = crtc->dev; | |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3289 | bool pending; |
3290 | ||
3291 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3292 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3293 | return false; | |
3294 | ||
5e2d7afc | 3295 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3296 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3297 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3298 | |
3299 | return pending; | |
3300 | } | |
3301 | ||
bfd16b2a ML |
3302 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3303 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3304 | { |
3305 | struct drm_device *dev = crtc->base.dev; | |
3306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3307 | struct intel_crtc_state *pipe_config = |
3308 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3309 | |
bfd16b2a ML |
3310 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3311 | crtc->base.mode = crtc->base.state->mode; | |
3312 | ||
3313 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3314 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3315 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3316 | |
44522d85 ML |
3317 | if (HAS_DDI(dev)) |
3318 | intel_set_pipe_csc(&crtc->base); | |
3319 | ||
e30e8f75 GP |
3320 | /* |
3321 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3322 | * that in compute_mode_changes we check the native mode (not the pfit | |
3323 | * mode) to see if we can flip rather than do a full mode set. In the | |
3324 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3325 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3326 | * sized surface. | |
e30e8f75 GP |
3327 | */ |
3328 | ||
e30e8f75 | 3329 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3330 | ((pipe_config->pipe_src_w - 1) << 16) | |
3331 | (pipe_config->pipe_src_h - 1)); | |
3332 | ||
3333 | /* on skylake this is done by detaching scalers */ | |
3334 | if (INTEL_INFO(dev)->gen >= 9) { | |
3335 | skl_detach_scalers(crtc); | |
3336 | ||
3337 | if (pipe_config->pch_pfit.enabled) | |
3338 | skylake_pfit_enable(crtc); | |
3339 | } else if (HAS_PCH_SPLIT(dev)) { | |
3340 | if (pipe_config->pch_pfit.enabled) | |
3341 | ironlake_pfit_enable(crtc); | |
3342 | else if (old_crtc_state->pch_pfit.enabled) | |
3343 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3344 | } |
e30e8f75 GP |
3345 | } |
3346 | ||
5e84e1a4 ZW |
3347 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3348 | { | |
3349 | struct drm_device *dev = crtc->dev; | |
3350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3352 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3353 | i915_reg_t reg; |
3354 | u32 temp; | |
5e84e1a4 ZW |
3355 | |
3356 | /* enable normal train */ | |
3357 | reg = FDI_TX_CTL(pipe); | |
3358 | temp = I915_READ(reg); | |
61e499bf | 3359 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3360 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3361 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3362 | } else { |
3363 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3364 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3365 | } |
5e84e1a4 ZW |
3366 | I915_WRITE(reg, temp); |
3367 | ||
3368 | reg = FDI_RX_CTL(pipe); | |
3369 | temp = I915_READ(reg); | |
3370 | if (HAS_PCH_CPT(dev)) { | |
3371 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3372 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3373 | } else { | |
3374 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3375 | temp |= FDI_LINK_TRAIN_NONE; | |
3376 | } | |
3377 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3378 | ||
3379 | /* wait one idle pattern time */ | |
3380 | POSTING_READ(reg); | |
3381 | udelay(1000); | |
357555c0 JB |
3382 | |
3383 | /* IVB wants error correction enabled */ | |
3384 | if (IS_IVYBRIDGE(dev)) | |
3385 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3386 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3387 | } |
3388 | ||
8db9d77b ZW |
3389 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3390 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3391 | { | |
3392 | struct drm_device *dev = crtc->dev; | |
3393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3395 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3396 | i915_reg_t reg; |
3397 | u32 temp, tries; | |
8db9d77b | 3398 | |
1c8562f6 | 3399 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3400 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3401 | |
e1a44743 AJ |
3402 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3403 | for train result */ | |
5eddb70b CW |
3404 | reg = FDI_RX_IMR(pipe); |
3405 | temp = I915_READ(reg); | |
e1a44743 AJ |
3406 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3407 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3408 | I915_WRITE(reg, temp); |
3409 | I915_READ(reg); | |
e1a44743 AJ |
3410 | udelay(150); |
3411 | ||
8db9d77b | 3412 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3413 | reg = FDI_TX_CTL(pipe); |
3414 | temp = I915_READ(reg); | |
627eb5a3 | 3415 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3416 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3417 | temp &= ~FDI_LINK_TRAIN_NONE; |
3418 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3419 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3420 | |
5eddb70b CW |
3421 | reg = FDI_RX_CTL(pipe); |
3422 | temp = I915_READ(reg); | |
8db9d77b ZW |
3423 | temp &= ~FDI_LINK_TRAIN_NONE; |
3424 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3425 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3426 | ||
3427 | POSTING_READ(reg); | |
8db9d77b ZW |
3428 | udelay(150); |
3429 | ||
5b2adf89 | 3430 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3431 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3432 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3433 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3434 | |
5eddb70b | 3435 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3436 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3437 | temp = I915_READ(reg); |
8db9d77b ZW |
3438 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3439 | ||
3440 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3441 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3442 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3443 | break; |
3444 | } | |
8db9d77b | 3445 | } |
e1a44743 | 3446 | if (tries == 5) |
5eddb70b | 3447 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3448 | |
3449 | /* Train 2 */ | |
5eddb70b CW |
3450 | reg = FDI_TX_CTL(pipe); |
3451 | temp = I915_READ(reg); | |
8db9d77b ZW |
3452 | temp &= ~FDI_LINK_TRAIN_NONE; |
3453 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3454 | I915_WRITE(reg, temp); |
8db9d77b | 3455 | |
5eddb70b CW |
3456 | reg = FDI_RX_CTL(pipe); |
3457 | temp = I915_READ(reg); | |
8db9d77b ZW |
3458 | temp &= ~FDI_LINK_TRAIN_NONE; |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3460 | I915_WRITE(reg, temp); |
8db9d77b | 3461 | |
5eddb70b CW |
3462 | POSTING_READ(reg); |
3463 | udelay(150); | |
8db9d77b | 3464 | |
5eddb70b | 3465 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3466 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3467 | temp = I915_READ(reg); |
8db9d77b ZW |
3468 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3469 | ||
3470 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3471 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3472 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3473 | break; | |
3474 | } | |
8db9d77b | 3475 | } |
e1a44743 | 3476 | if (tries == 5) |
5eddb70b | 3477 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3480 | |
8db9d77b ZW |
3481 | } |
3482 | ||
0206e353 | 3483 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3484 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3485 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3486 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3487 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3488 | }; | |
3489 | ||
3490 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3491 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3492 | { | |
3493 | struct drm_device *dev = crtc->dev; | |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3495 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3496 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3497 | i915_reg_t reg; |
3498 | u32 temp, i, retry; | |
8db9d77b | 3499 | |
e1a44743 AJ |
3500 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3501 | for train result */ | |
5eddb70b CW |
3502 | reg = FDI_RX_IMR(pipe); |
3503 | temp = I915_READ(reg); | |
e1a44743 AJ |
3504 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3505 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3506 | I915_WRITE(reg, temp); |
3507 | ||
3508 | POSTING_READ(reg); | |
e1a44743 AJ |
3509 | udelay(150); |
3510 | ||
8db9d77b | 3511 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3512 | reg = FDI_TX_CTL(pipe); |
3513 | temp = I915_READ(reg); | |
627eb5a3 | 3514 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3515 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3516 | temp &= ~FDI_LINK_TRAIN_NONE; |
3517 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3518 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3519 | /* SNB-B */ | |
3520 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3521 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3522 | |
d74cf324 DV |
3523 | I915_WRITE(FDI_RX_MISC(pipe), |
3524 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3525 | ||
5eddb70b CW |
3526 | reg = FDI_RX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
8db9d77b ZW |
3528 | if (HAS_PCH_CPT(dev)) { |
3529 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3531 | } else { | |
3532 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3533 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3534 | } | |
5eddb70b CW |
3535 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3536 | ||
3537 | POSTING_READ(reg); | |
8db9d77b ZW |
3538 | udelay(150); |
3539 | ||
0206e353 | 3540 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3541 | reg = FDI_TX_CTL(pipe); |
3542 | temp = I915_READ(reg); | |
8db9d77b ZW |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3544 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3545 | I915_WRITE(reg, temp); |
3546 | ||
3547 | POSTING_READ(reg); | |
8db9d77b ZW |
3548 | udelay(500); |
3549 | ||
fa37d39e SP |
3550 | for (retry = 0; retry < 5; retry++) { |
3551 | reg = FDI_RX_IIR(pipe); | |
3552 | temp = I915_READ(reg); | |
3553 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3554 | if (temp & FDI_RX_BIT_LOCK) { | |
3555 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3556 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3557 | break; | |
3558 | } | |
3559 | udelay(50); | |
8db9d77b | 3560 | } |
fa37d39e SP |
3561 | if (retry < 5) |
3562 | break; | |
8db9d77b ZW |
3563 | } |
3564 | if (i == 4) | |
5eddb70b | 3565 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3566 | |
3567 | /* Train 2 */ | |
5eddb70b CW |
3568 | reg = FDI_TX_CTL(pipe); |
3569 | temp = I915_READ(reg); | |
8db9d77b ZW |
3570 | temp &= ~FDI_LINK_TRAIN_NONE; |
3571 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3572 | if (IS_GEN6(dev)) { | |
3573 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3574 | /* SNB-B */ | |
3575 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3576 | } | |
5eddb70b | 3577 | I915_WRITE(reg, temp); |
8db9d77b | 3578 | |
5eddb70b CW |
3579 | reg = FDI_RX_CTL(pipe); |
3580 | temp = I915_READ(reg); | |
8db9d77b ZW |
3581 | if (HAS_PCH_CPT(dev)) { |
3582 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3584 | } else { | |
3585 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3586 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3587 | } | |
5eddb70b CW |
3588 | I915_WRITE(reg, temp); |
3589 | ||
3590 | POSTING_READ(reg); | |
8db9d77b ZW |
3591 | udelay(150); |
3592 | ||
0206e353 | 3593 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3594 | reg = FDI_TX_CTL(pipe); |
3595 | temp = I915_READ(reg); | |
8db9d77b ZW |
3596 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3597 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3598 | I915_WRITE(reg, temp); |
3599 | ||
3600 | POSTING_READ(reg); | |
8db9d77b ZW |
3601 | udelay(500); |
3602 | ||
fa37d39e SP |
3603 | for (retry = 0; retry < 5; retry++) { |
3604 | reg = FDI_RX_IIR(pipe); | |
3605 | temp = I915_READ(reg); | |
3606 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3607 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3608 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3609 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3610 | break; | |
3611 | } | |
3612 | udelay(50); | |
8db9d77b | 3613 | } |
fa37d39e SP |
3614 | if (retry < 5) |
3615 | break; | |
8db9d77b ZW |
3616 | } |
3617 | if (i == 4) | |
5eddb70b | 3618 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3619 | |
3620 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3621 | } | |
3622 | ||
357555c0 JB |
3623 | /* Manual link training for Ivy Bridge A0 parts */ |
3624 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3625 | { | |
3626 | struct drm_device *dev = crtc->dev; | |
3627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3629 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3630 | i915_reg_t reg; |
3631 | u32 temp, i, j; | |
357555c0 JB |
3632 | |
3633 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3634 | for train result */ | |
3635 | reg = FDI_RX_IMR(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3638 | temp &= ~FDI_RX_BIT_LOCK; | |
3639 | I915_WRITE(reg, temp); | |
3640 | ||
3641 | POSTING_READ(reg); | |
3642 | udelay(150); | |
3643 | ||
01a415fd DV |
3644 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3645 | I915_READ(FDI_RX_IIR(pipe))); | |
3646 | ||
139ccd3f JB |
3647 | /* Try each vswing and preemphasis setting twice before moving on */ |
3648 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3649 | /* disable first in case we need to retry */ | |
3650 | reg = FDI_TX_CTL(pipe); | |
3651 | temp = I915_READ(reg); | |
3652 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3653 | temp &= ~FDI_TX_ENABLE; | |
3654 | I915_WRITE(reg, temp); | |
357555c0 | 3655 | |
139ccd3f JB |
3656 | reg = FDI_RX_CTL(pipe); |
3657 | temp = I915_READ(reg); | |
3658 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3659 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3660 | temp &= ~FDI_RX_ENABLE; | |
3661 | I915_WRITE(reg, temp); | |
357555c0 | 3662 | |
139ccd3f | 3663 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3664 | reg = FDI_TX_CTL(pipe); |
3665 | temp = I915_READ(reg); | |
139ccd3f | 3666 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3667 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3668 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3669 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3670 | temp |= snb_b_fdi_train_param[j/2]; |
3671 | temp |= FDI_COMPOSITE_SYNC; | |
3672 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3673 | |
139ccd3f JB |
3674 | I915_WRITE(FDI_RX_MISC(pipe), |
3675 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3676 | |
139ccd3f | 3677 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3678 | temp = I915_READ(reg); |
139ccd3f JB |
3679 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3680 | temp |= FDI_COMPOSITE_SYNC; | |
3681 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3682 | |
139ccd3f JB |
3683 | POSTING_READ(reg); |
3684 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3685 | |
139ccd3f JB |
3686 | for (i = 0; i < 4; i++) { |
3687 | reg = FDI_RX_IIR(pipe); | |
3688 | temp = I915_READ(reg); | |
3689 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3690 | |
139ccd3f JB |
3691 | if (temp & FDI_RX_BIT_LOCK || |
3692 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3693 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3694 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3695 | i); | |
3696 | break; | |
3697 | } | |
3698 | udelay(1); /* should be 0.5us */ | |
3699 | } | |
3700 | if (i == 4) { | |
3701 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3702 | continue; | |
3703 | } | |
357555c0 | 3704 | |
139ccd3f | 3705 | /* Train 2 */ |
357555c0 JB |
3706 | reg = FDI_TX_CTL(pipe); |
3707 | temp = I915_READ(reg); | |
139ccd3f JB |
3708 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3709 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3710 | I915_WRITE(reg, temp); | |
3711 | ||
3712 | reg = FDI_RX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3715 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3716 | I915_WRITE(reg, temp); |
3717 | ||
3718 | POSTING_READ(reg); | |
139ccd3f | 3719 | udelay(2); /* should be 1.5us */ |
357555c0 | 3720 | |
139ccd3f JB |
3721 | for (i = 0; i < 4; i++) { |
3722 | reg = FDI_RX_IIR(pipe); | |
3723 | temp = I915_READ(reg); | |
3724 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3725 | |
139ccd3f JB |
3726 | if (temp & FDI_RX_SYMBOL_LOCK || |
3727 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3728 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3729 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3730 | i); | |
3731 | goto train_done; | |
3732 | } | |
3733 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3734 | } |
139ccd3f JB |
3735 | if (i == 4) |
3736 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3737 | } |
357555c0 | 3738 | |
139ccd3f | 3739 | train_done: |
357555c0 JB |
3740 | DRM_DEBUG_KMS("FDI train done.\n"); |
3741 | } | |
3742 | ||
88cefb6c | 3743 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3744 | { |
88cefb6c | 3745 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3746 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3747 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3748 | i915_reg_t reg; |
3749 | u32 temp; | |
c64e311e | 3750 | |
c98e9dcf | 3751 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3752 | reg = FDI_RX_CTL(pipe); |
3753 | temp = I915_READ(reg); | |
627eb5a3 | 3754 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3755 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3756 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3757 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3758 | ||
3759 | POSTING_READ(reg); | |
c98e9dcf JB |
3760 | udelay(200); |
3761 | ||
3762 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3763 | temp = I915_READ(reg); |
3764 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3765 | ||
3766 | POSTING_READ(reg); | |
c98e9dcf JB |
3767 | udelay(200); |
3768 | ||
20749730 PZ |
3769 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3770 | reg = FDI_TX_CTL(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3773 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3774 | |
20749730 PZ |
3775 | POSTING_READ(reg); |
3776 | udelay(100); | |
6be4a607 | 3777 | } |
0e23b99d JB |
3778 | } |
3779 | ||
88cefb6c DV |
3780 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3781 | { | |
3782 | struct drm_device *dev = intel_crtc->base.dev; | |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3784 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3785 | i915_reg_t reg; |
3786 | u32 temp; | |
88cefb6c DV |
3787 | |
3788 | /* Switch from PCDclk to Rawclk */ | |
3789 | reg = FDI_RX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3792 | ||
3793 | /* Disable CPU FDI TX PLL */ | |
3794 | reg = FDI_TX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3797 | ||
3798 | POSTING_READ(reg); | |
3799 | udelay(100); | |
3800 | ||
3801 | reg = FDI_RX_CTL(pipe); | |
3802 | temp = I915_READ(reg); | |
3803 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3804 | ||
3805 | /* Wait for the clocks to turn off. */ | |
3806 | POSTING_READ(reg); | |
3807 | udelay(100); | |
3808 | } | |
3809 | ||
0fc932b8 JB |
3810 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3811 | { | |
3812 | struct drm_device *dev = crtc->dev; | |
3813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3815 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3816 | i915_reg_t reg; |
3817 | u32 temp; | |
0fc932b8 JB |
3818 | |
3819 | /* disable CPU FDI tx and PCH FDI rx */ | |
3820 | reg = FDI_TX_CTL(pipe); | |
3821 | temp = I915_READ(reg); | |
3822 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3823 | POSTING_READ(reg); | |
3824 | ||
3825 | reg = FDI_RX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
3827 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3828 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3829 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3830 | ||
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | ||
3834 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3835 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3836 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3837 | |
3838 | /* still set train pattern 1 */ | |
3839 | reg = FDI_TX_CTL(pipe); | |
3840 | temp = I915_READ(reg); | |
3841 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3842 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3843 | I915_WRITE(reg, temp); | |
3844 | ||
3845 | reg = FDI_RX_CTL(pipe); | |
3846 | temp = I915_READ(reg); | |
3847 | if (HAS_PCH_CPT(dev)) { | |
3848 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3850 | } else { | |
3851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3852 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3853 | } | |
3854 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3855 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3856 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3857 | I915_WRITE(reg, temp); |
3858 | ||
3859 | POSTING_READ(reg); | |
3860 | udelay(100); | |
3861 | } | |
3862 | ||
5dce5b93 CW |
3863 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3864 | { | |
3865 | struct intel_crtc *crtc; | |
3866 | ||
3867 | /* Note that we don't need to be called with mode_config.lock here | |
3868 | * as our list of CRTC objects is static for the lifetime of the | |
3869 | * device and so cannot disappear as we iterate. Similarly, we can | |
3870 | * happily treat the predicates as racy, atomic checks as userspace | |
3871 | * cannot claim and pin a new fb without at least acquring the | |
3872 | * struct_mutex and so serialising with us. | |
3873 | */ | |
d3fcc808 | 3874 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3875 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3876 | continue; | |
3877 | ||
3878 | if (crtc->unpin_work) | |
3879 | intel_wait_for_vblank(dev, crtc->pipe); | |
3880 | ||
3881 | return true; | |
3882 | } | |
3883 | ||
3884 | return false; | |
3885 | } | |
3886 | ||
d6bbafa1 CW |
3887 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3888 | { | |
3889 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3890 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3891 | ||
3892 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3893 | smp_rmb(); | |
3894 | intel_crtc->unpin_work = NULL; | |
3895 | ||
3896 | if (work->event) | |
3897 | drm_send_vblank_event(intel_crtc->base.dev, | |
3898 | intel_crtc->pipe, | |
3899 | work->event); | |
3900 | ||
3901 | drm_crtc_vblank_put(&intel_crtc->base); | |
3902 | ||
3903 | wake_up_all(&dev_priv->pending_flip_queue); | |
3904 | queue_work(dev_priv->wq, &work->work); | |
3905 | ||
3906 | trace_i915_flip_complete(intel_crtc->plane, | |
3907 | work->pending_flip_obj); | |
3908 | } | |
3909 | ||
5008e874 | 3910 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3911 | { |
0f91128d | 3912 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3913 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3914 | long ret; |
e6c3a2a6 | 3915 | |
2c10d571 | 3916 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3917 | |
3918 | ret = wait_event_interruptible_timeout( | |
3919 | dev_priv->pending_flip_queue, | |
3920 | !intel_crtc_has_pending_flip(crtc), | |
3921 | 60*HZ); | |
3922 | ||
3923 | if (ret < 0) | |
3924 | return ret; | |
3925 | ||
3926 | if (ret == 0) { | |
9c787942 | 3927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3928 | |
5e2d7afc | 3929 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3930 | if (intel_crtc->unpin_work) { |
3931 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3932 | page_flip_completed(intel_crtc); | |
3933 | } | |
5e2d7afc | 3934 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3935 | } |
5bb61643 | 3936 | |
5008e874 | 3937 | return 0; |
e6c3a2a6 CW |
3938 | } |
3939 | ||
060f02d8 VS |
3940 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3941 | { | |
3942 | u32 temp; | |
3943 | ||
3944 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3945 | ||
3946 | mutex_lock(&dev_priv->sb_lock); | |
3947 | ||
3948 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3949 | temp |= SBI_SSCCTL_DISABLE; | |
3950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3951 | ||
3952 | mutex_unlock(&dev_priv->sb_lock); | |
3953 | } | |
3954 | ||
e615efe4 ED |
3955 | /* Program iCLKIP clock to the desired frequency */ |
3956 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3957 | { | |
3958 | struct drm_device *dev = crtc->dev; | |
3959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3960 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3961 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3962 | u32 temp; | |
3963 | ||
060f02d8 | 3964 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3965 | |
3966 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3967 | if (clock == 20000) { |
e615efe4 ED |
3968 | auxdiv = 1; |
3969 | divsel = 0x41; | |
3970 | phaseinc = 0x20; | |
3971 | } else { | |
3972 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3973 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3974 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3975 | * convert the virtual clock precision to KHz here for higher |
3976 | * precision. | |
3977 | */ | |
3978 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3979 | u32 iclk_pi_range = 64; | |
3980 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3981 | ||
a2572f5c | 3982 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3983 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3984 | pi_value = desired_divisor % iclk_pi_range; | |
3985 | ||
3986 | auxdiv = 0; | |
3987 | divsel = msb_divisor_value - 2; | |
3988 | phaseinc = pi_value; | |
3989 | } | |
3990 | ||
3991 | /* This should not happen with any sane values */ | |
3992 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3993 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3994 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3995 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3996 | ||
3997 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3998 | clock, |
e615efe4 ED |
3999 | auxdiv, |
4000 | divsel, | |
4001 | phasedir, | |
4002 | phaseinc); | |
4003 | ||
060f02d8 VS |
4004 | mutex_lock(&dev_priv->sb_lock); |
4005 | ||
e615efe4 | 4006 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4007 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4008 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4009 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4010 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4011 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4012 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4013 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4014 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4015 | |
4016 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4017 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4018 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4019 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4020 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4021 | |
4022 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4023 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4024 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4025 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4026 | |
060f02d8 VS |
4027 | mutex_unlock(&dev_priv->sb_lock); |
4028 | ||
e615efe4 ED |
4029 | /* Wait for initialization time */ |
4030 | udelay(24); | |
4031 | ||
4032 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4033 | } | |
4034 | ||
275f01b2 DV |
4035 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4036 | enum pipe pch_transcoder) | |
4037 | { | |
4038 | struct drm_device *dev = crtc->base.dev; | |
4039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4041 | |
4042 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4043 | I915_READ(HTOTAL(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4045 | I915_READ(HBLANK(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4047 | I915_READ(HSYNC(cpu_transcoder))); | |
4048 | ||
4049 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4050 | I915_READ(VTOTAL(cpu_transcoder))); | |
4051 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4052 | I915_READ(VBLANK(cpu_transcoder))); | |
4053 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4054 | I915_READ(VSYNC(cpu_transcoder))); | |
4055 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4056 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4057 | } | |
4058 | ||
003632d9 | 4059 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4060 | { |
4061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4062 | uint32_t temp; | |
4063 | ||
4064 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4065 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4066 | return; |
4067 | ||
4068 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4069 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4070 | ||
003632d9 ACO |
4071 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4072 | if (enable) | |
4073 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4074 | ||
4075 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4076 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4077 | POSTING_READ(SOUTH_CHICKEN1); | |
4078 | } | |
4079 | ||
4080 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4081 | { | |
4082 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4083 | |
4084 | switch (intel_crtc->pipe) { | |
4085 | case PIPE_A: | |
4086 | break; | |
4087 | case PIPE_B: | |
6e3c9717 | 4088 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4089 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4090 | else |
003632d9 | 4091 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4092 | |
4093 | break; | |
4094 | case PIPE_C: | |
003632d9 | 4095 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4096 | |
4097 | break; | |
4098 | default: | |
4099 | BUG(); | |
4100 | } | |
4101 | } | |
4102 | ||
c48b5305 VS |
4103 | /* Return which DP Port should be selected for Transcoder DP control */ |
4104 | static enum port | |
4105 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4106 | { | |
4107 | struct drm_device *dev = crtc->dev; | |
4108 | struct intel_encoder *encoder; | |
4109 | ||
4110 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4111 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4112 | encoder->type == INTEL_OUTPUT_EDP) | |
4113 | return enc_to_dig_port(&encoder->base)->port; | |
4114 | } | |
4115 | ||
4116 | return -1; | |
4117 | } | |
4118 | ||
f67a559d JB |
4119 | /* |
4120 | * Enable PCH resources required for PCH ports: | |
4121 | * - PCH PLLs | |
4122 | * - FDI training & RX/TX | |
4123 | * - update transcoder timings | |
4124 | * - DP transcoding bits | |
4125 | * - transcoder | |
4126 | */ | |
4127 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4128 | { |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4132 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4133 | u32 temp; |
2c07245f | 4134 | |
ab9412ba | 4135 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4136 | |
1fbc0d78 DV |
4137 | if (IS_IVYBRIDGE(dev)) |
4138 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4139 | ||
cd986abb DV |
4140 | /* Write the TU size bits before fdi link training, so that error |
4141 | * detection works. */ | |
4142 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4143 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4144 | ||
3860b2ec VS |
4145 | /* |
4146 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4147 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4148 | */ | |
4149 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4150 | ||
c98e9dcf | 4151 | /* For PCH output, training FDI link */ |
674cf967 | 4152 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4153 | |
3ad8a208 DV |
4154 | /* We need to program the right clock selection before writing the pixel |
4155 | * mutliplier into the DPLL. */ | |
303b81e0 | 4156 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4157 | u32 sel; |
4b645f14 | 4158 | |
c98e9dcf | 4159 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4160 | temp |= TRANS_DPLL_ENABLE(pipe); |
4161 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4162 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4163 | temp |= sel; |
4164 | else | |
4165 | temp &= ~sel; | |
c98e9dcf | 4166 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4167 | } |
5eddb70b | 4168 | |
3ad8a208 DV |
4169 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4170 | * transcoder, and we actually should do this to not upset any PCH | |
4171 | * transcoder that already use the clock when we share it. | |
4172 | * | |
4173 | * Note that enable_shared_dpll tries to do the right thing, but | |
4174 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4175 | * the right LVDS enable sequence. */ | |
85b3894f | 4176 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4177 | |
d9b6cb56 JB |
4178 | /* set transcoder timing, panel must allow it */ |
4179 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4180 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4181 | |
303b81e0 | 4182 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4183 | |
3860b2ec VS |
4184 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4185 | ||
c98e9dcf | 4186 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4187 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4188 | const struct drm_display_mode *adjusted_mode = |
4189 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4190 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4191 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4192 | temp = I915_READ(reg); |
4193 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4194 | TRANS_DP_SYNC_MASK | |
4195 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4196 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4197 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4198 | |
9c4edaee | 4199 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4200 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4201 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4202 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4203 | |
4204 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4205 | case PORT_B: |
5eddb70b | 4206 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4207 | break; |
c48b5305 | 4208 | case PORT_C: |
5eddb70b | 4209 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4210 | break; |
c48b5305 | 4211 | case PORT_D: |
5eddb70b | 4212 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4213 | break; |
4214 | default: | |
e95d41e1 | 4215 | BUG(); |
32f9d658 | 4216 | } |
2c07245f | 4217 | |
5eddb70b | 4218 | I915_WRITE(reg, temp); |
6be4a607 | 4219 | } |
b52eb4dc | 4220 | |
b8a4f404 | 4221 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4222 | } |
4223 | ||
1507e5bd PZ |
4224 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4225 | { | |
4226 | struct drm_device *dev = crtc->dev; | |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4229 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4230 | |
ab9412ba | 4231 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4232 | |
8c52b5e8 | 4233 | lpt_program_iclkip(crtc); |
1507e5bd | 4234 | |
0540e488 | 4235 | /* Set transcoder timing. */ |
275f01b2 | 4236 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4237 | |
937bb610 | 4238 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4239 | } |
4240 | ||
190f68c5 ACO |
4241 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4242 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4243 | { |
e2b78267 | 4244 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4245 | struct intel_shared_dpll *pll; |
de419ab6 | 4246 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4247 | enum intel_dpll_id i; |
00490c22 | 4248 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4249 | |
de419ab6 ML |
4250 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4251 | ||
98b6bd99 DV |
4252 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4253 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4254 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4255 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4256 | |
46edb027 DV |
4257 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4258 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4259 | |
de419ab6 | 4260 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4261 | |
98b6bd99 DV |
4262 | goto found; |
4263 | } | |
4264 | ||
bcddf610 S |
4265 | if (IS_BROXTON(dev_priv->dev)) { |
4266 | /* PLL is attached to port in bxt */ | |
4267 | struct intel_encoder *encoder; | |
4268 | struct intel_digital_port *intel_dig_port; | |
4269 | ||
4270 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4271 | if (WARN_ON(!encoder)) | |
4272 | return NULL; | |
4273 | ||
4274 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4275 | /* 1:1 mapping between ports and PLLs */ | |
4276 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4277 | pll = &dev_priv->shared_dplls[i]; | |
4278 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4279 | crtc->base.base.id, pll->name); | |
de419ab6 | 4280 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4281 | |
4282 | goto found; | |
00490c22 ML |
4283 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4284 | /* Do not consider SPLL */ | |
4285 | max = 2; | |
bcddf610 | 4286 | |
00490c22 | 4287 | for (i = 0; i < max; i++) { |
e72f9fbf | 4288 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4289 | |
4290 | /* Only want to check enabled timings first */ | |
de419ab6 | 4291 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4292 | continue; |
4293 | ||
190f68c5 | 4294 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4295 | &shared_dpll[i].hw_state, |
4296 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4297 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4298 | crtc->base.base.id, pll->name, |
de419ab6 | 4299 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4300 | pll->active); |
ee7b9f93 JB |
4301 | goto found; |
4302 | } | |
4303 | } | |
4304 | ||
4305 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4306 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4307 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4308 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4309 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4310 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4311 | goto found; |
4312 | } | |
4313 | } | |
4314 | ||
4315 | return NULL; | |
4316 | ||
4317 | found: | |
de419ab6 ML |
4318 | if (shared_dpll[i].crtc_mask == 0) |
4319 | shared_dpll[i].hw_state = | |
4320 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4321 | |
190f68c5 | 4322 | crtc_state->shared_dpll = i; |
46edb027 DV |
4323 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4324 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4325 | |
de419ab6 | 4326 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4327 | |
ee7b9f93 JB |
4328 | return pll; |
4329 | } | |
4330 | ||
de419ab6 | 4331 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4332 | { |
de419ab6 ML |
4333 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4334 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4335 | struct intel_shared_dpll *pll; |
4336 | enum intel_dpll_id i; | |
4337 | ||
de419ab6 ML |
4338 | if (!to_intel_atomic_state(state)->dpll_set) |
4339 | return; | |
8bd31e67 | 4340 | |
de419ab6 | 4341 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4342 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4343 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4344 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4345 | } |
4346 | } | |
4347 | ||
a1520318 | 4348 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4349 | { |
4350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4351 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4352 | u32 temp; |
4353 | ||
4354 | temp = I915_READ(dslreg); | |
4355 | udelay(500); | |
4356 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4357 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4358 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4359 | } |
4360 | } | |
4361 | ||
86adf9d7 ML |
4362 | static int |
4363 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4364 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4365 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4366 | { |
86adf9d7 ML |
4367 | struct intel_crtc_scaler_state *scaler_state = |
4368 | &crtc_state->scaler_state; | |
4369 | struct intel_crtc *intel_crtc = | |
4370 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4371 | int need_scaling; |
6156a456 CK |
4372 | |
4373 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4374 | (src_h != dst_w || src_w != dst_h): | |
4375 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4376 | |
4377 | /* | |
4378 | * if plane is being disabled or scaler is no more required or force detach | |
4379 | * - free scaler binded to this plane/crtc | |
4380 | * - in order to do this, update crtc->scaler_usage | |
4381 | * | |
4382 | * Here scaler state in crtc_state is set free so that | |
4383 | * scaler can be assigned to other user. Actual register | |
4384 | * update to free the scaler is done in plane/panel-fit programming. | |
4385 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4386 | */ | |
86adf9d7 | 4387 | if (force_detach || !need_scaling) { |
a1b2278e | 4388 | if (*scaler_id >= 0) { |
86adf9d7 | 4389 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4390 | scaler_state->scalers[*scaler_id].in_use = 0; |
4391 | ||
86adf9d7 ML |
4392 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4393 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4394 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4395 | scaler_state->scaler_users); |
4396 | *scaler_id = -1; | |
4397 | } | |
4398 | return 0; | |
4399 | } | |
4400 | ||
4401 | /* range checks */ | |
4402 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4403 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4404 | ||
4405 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4406 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4407 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4408 | "size is out of scaler range\n", |
86adf9d7 | 4409 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4410 | return -EINVAL; |
4411 | } | |
4412 | ||
86adf9d7 ML |
4413 | /* mark this plane as a scaler user in crtc_state */ |
4414 | scaler_state->scaler_users |= (1 << scaler_user); | |
4415 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4416 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4417 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4418 | scaler_state->scaler_users); | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | ||
4423 | /** | |
4424 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4425 | * | |
4426 | * @state: crtc's scaler state | |
86adf9d7 ML |
4427 | * |
4428 | * Return | |
4429 | * 0 - scaler_usage updated successfully | |
4430 | * error - requested scaling cannot be supported or other error condition | |
4431 | */ | |
e435d6e5 | 4432 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4433 | { |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4435 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4436 | |
4437 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4438 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4439 | ||
e435d6e5 | 4440 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4441 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4442 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4443 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4444 | } |
4445 | ||
4446 | /** | |
4447 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4448 | * | |
4449 | * @state: crtc's scaler state | |
86adf9d7 ML |
4450 | * @plane_state: atomic plane state to update |
4451 | * | |
4452 | * Return | |
4453 | * 0 - scaler_usage updated successfully | |
4454 | * error - requested scaling cannot be supported or other error condition | |
4455 | */ | |
da20eabd ML |
4456 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4457 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4458 | { |
4459 | ||
4460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4461 | struct intel_plane *intel_plane = |
4462 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4463 | struct drm_framebuffer *fb = plane_state->base.fb; |
4464 | int ret; | |
4465 | ||
4466 | bool force_detach = !fb || !plane_state->visible; | |
4467 | ||
4468 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4469 | intel_plane->base.base.id, intel_crtc->pipe, | |
4470 | drm_plane_index(&intel_plane->base)); | |
4471 | ||
4472 | ret = skl_update_scaler(crtc_state, force_detach, | |
4473 | drm_plane_index(&intel_plane->base), | |
4474 | &plane_state->scaler_id, | |
4475 | plane_state->base.rotation, | |
4476 | drm_rect_width(&plane_state->src) >> 16, | |
4477 | drm_rect_height(&plane_state->src) >> 16, | |
4478 | drm_rect_width(&plane_state->dst), | |
4479 | drm_rect_height(&plane_state->dst)); | |
4480 | ||
4481 | if (ret || plane_state->scaler_id < 0) | |
4482 | return ret; | |
4483 | ||
a1b2278e | 4484 | /* check colorkey */ |
818ed961 | 4485 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4486 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4487 | intel_plane->base.base.id); |
a1b2278e CK |
4488 | return -EINVAL; |
4489 | } | |
4490 | ||
4491 | /* Check src format */ | |
86adf9d7 ML |
4492 | switch (fb->pixel_format) { |
4493 | case DRM_FORMAT_RGB565: | |
4494 | case DRM_FORMAT_XBGR8888: | |
4495 | case DRM_FORMAT_XRGB8888: | |
4496 | case DRM_FORMAT_ABGR8888: | |
4497 | case DRM_FORMAT_ARGB8888: | |
4498 | case DRM_FORMAT_XRGB2101010: | |
4499 | case DRM_FORMAT_XBGR2101010: | |
4500 | case DRM_FORMAT_YUYV: | |
4501 | case DRM_FORMAT_YVYU: | |
4502 | case DRM_FORMAT_UYVY: | |
4503 | case DRM_FORMAT_VYUY: | |
4504 | break; | |
4505 | default: | |
4506 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4507 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4508 | return -EINVAL; | |
a1b2278e CK |
4509 | } |
4510 | ||
a1b2278e CK |
4511 | return 0; |
4512 | } | |
4513 | ||
e435d6e5 ML |
4514 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4515 | { | |
4516 | int i; | |
4517 | ||
4518 | for (i = 0; i < crtc->num_scalers; i++) | |
4519 | skl_detach_scaler(crtc, i); | |
4520 | } | |
4521 | ||
4522 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4523 | { |
4524 | struct drm_device *dev = crtc->base.dev; | |
4525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4526 | int pipe = crtc->pipe; | |
a1b2278e CK |
4527 | struct intel_crtc_scaler_state *scaler_state = |
4528 | &crtc->config->scaler_state; | |
4529 | ||
4530 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4531 | ||
6e3c9717 | 4532 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4533 | int id; |
4534 | ||
4535 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4536 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4537 | return; | |
4538 | } | |
4539 | ||
4540 | id = scaler_state->scaler_id; | |
4541 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4542 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4543 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4544 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4545 | ||
4546 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4547 | } |
4548 | } | |
4549 | ||
b074cec8 JB |
4550 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4551 | { | |
4552 | struct drm_device *dev = crtc->base.dev; | |
4553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4554 | int pipe = crtc->pipe; | |
4555 | ||
6e3c9717 | 4556 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4557 | /* Force use of hard-coded filter coefficients |
4558 | * as some pre-programmed values are broken, | |
4559 | * e.g. x201. | |
4560 | */ | |
4561 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4563 | PF_PIPE_SEL_IVB(pipe)); | |
4564 | else | |
4565 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4566 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4567 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4568 | } |
4569 | } | |
4570 | ||
20bc8673 | 4571 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4572 | { |
cea165c3 VS |
4573 | struct drm_device *dev = crtc->base.dev; |
4574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4575 | |
6e3c9717 | 4576 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4577 | return; |
4578 | ||
cea165c3 VS |
4579 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4580 | intel_wait_for_vblank(dev, crtc->pipe); | |
4581 | ||
d77e4531 | 4582 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4583 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4584 | mutex_lock(&dev_priv->rps.hw_lock); |
4585 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4587 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4588 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4589 | * mailbox." Moreover, the mailbox may return a bogus state, |
4590 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4591 | */ |
4592 | } else { | |
4593 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4594 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4595 | * is essentially intel_wait_for_vblank. If we don't have this | |
4596 | * and don't wait for vblanks until the end of crtc_enable, then | |
4597 | * the HW state readout code will complain that the expected | |
4598 | * IPS_CTL value is not the one we read. */ | |
4599 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4600 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4601 | } | |
d77e4531 PZ |
4602 | } |
4603 | ||
20bc8673 | 4604 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4605 | { |
4606 | struct drm_device *dev = crtc->base.dev; | |
4607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4608 | ||
6e3c9717 | 4609 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4610 | return; |
4611 | ||
4612 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4613 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4614 | mutex_lock(&dev_priv->rps.hw_lock); |
4615 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4616 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4617 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4618 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4619 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4620 | } else { |
2a114cc1 | 4621 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4622 | POSTING_READ(IPS_CTL); |
4623 | } | |
d77e4531 PZ |
4624 | |
4625 | /* We need to wait for a vblank before we can disable the plane. */ | |
4626 | intel_wait_for_vblank(dev, crtc->pipe); | |
4627 | } | |
4628 | ||
4629 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4630 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4631 | { | |
4632 | struct drm_device *dev = crtc->dev; | |
4633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4635 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4636 | int i; |
4637 | bool reenable_ips = false; | |
4638 | ||
4639 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4640 | if (!crtc->state->active) |
d77e4531 PZ |
4641 | return; |
4642 | ||
50360403 | 4643 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4644 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4645 | assert_dsi_pll_enabled(dev_priv); |
4646 | else | |
4647 | assert_pll_enabled(dev_priv, pipe); | |
4648 | } | |
4649 | ||
d77e4531 PZ |
4650 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4651 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4652 | */ | |
6e3c9717 | 4653 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4654 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4655 | GAMMA_MODE_MODE_SPLIT)) { | |
4656 | hsw_disable_ips(intel_crtc); | |
4657 | reenable_ips = true; | |
4658 | } | |
4659 | ||
4660 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4661 | i915_reg_t palreg; |
f65a9c5b VS |
4662 | |
4663 | if (HAS_GMCH_DISPLAY(dev)) | |
4664 | palreg = PALETTE(pipe, i); | |
4665 | else | |
4666 | palreg = LGC_PALETTE(pipe, i); | |
4667 | ||
4668 | I915_WRITE(palreg, | |
d77e4531 PZ |
4669 | (intel_crtc->lut_r[i] << 16) | |
4670 | (intel_crtc->lut_g[i] << 8) | | |
4671 | intel_crtc->lut_b[i]); | |
4672 | } | |
4673 | ||
4674 | if (reenable_ips) | |
4675 | hsw_enable_ips(intel_crtc); | |
4676 | } | |
4677 | ||
7cac945f | 4678 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4679 | { |
7cac945f | 4680 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4681 | struct drm_device *dev = intel_crtc->base.dev; |
4682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4683 | ||
4684 | mutex_lock(&dev->struct_mutex); | |
4685 | dev_priv->mm.interruptible = false; | |
4686 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4687 | dev_priv->mm.interruptible = true; | |
4688 | mutex_unlock(&dev->struct_mutex); | |
4689 | } | |
4690 | ||
4691 | /* Let userspace switch the overlay on again. In most cases userspace | |
4692 | * has to recompute where to put it anyway. | |
4693 | */ | |
4694 | } | |
4695 | ||
87d4300a ML |
4696 | /** |
4697 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4698 | * @crtc: the CRTC whose primary plane was just enabled | |
4699 | * | |
4700 | * Performs potentially sleeping operations that must be done after the primary | |
4701 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4702 | * called due to an explicit primary plane update, or due to an implicit | |
4703 | * re-enable that is caused when a sprite plane is updated to no longer | |
4704 | * completely hide the primary plane. | |
4705 | */ | |
4706 | static void | |
4707 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4708 | { |
4709 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4710 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4712 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4713 | |
87d4300a ML |
4714 | /* |
4715 | * FIXME IPS should be fine as long as one plane is | |
4716 | * enabled, but in practice it seems to have problems | |
4717 | * when going from primary only to sprite only and vice | |
4718 | * versa. | |
4719 | */ | |
a5c4d7bc VS |
4720 | hsw_enable_ips(intel_crtc); |
4721 | ||
f99d7069 | 4722 | /* |
87d4300a ML |
4723 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4724 | * So don't enable underrun reporting before at least some planes | |
4725 | * are enabled. | |
4726 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4727 | * but leave the pipe running. | |
f99d7069 | 4728 | */ |
87d4300a ML |
4729 | if (IS_GEN2(dev)) |
4730 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4731 | ||
aca7b684 VS |
4732 | /* Underruns don't always raise interrupts, so check manually. */ |
4733 | intel_check_cpu_fifo_underruns(dev_priv); | |
4734 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4735 | } |
4736 | ||
87d4300a ML |
4737 | /** |
4738 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4739 | * @crtc: the CRTC whose primary plane is to be disabled | |
4740 | * | |
4741 | * Performs potentially sleeping operations that must be done before the | |
4742 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4743 | * be called due to an explicit primary plane update, or due to an implicit | |
4744 | * disable that is caused when a sprite plane completely hides the primary | |
4745 | * plane. | |
4746 | */ | |
4747 | static void | |
4748 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4749 | { |
4750 | struct drm_device *dev = crtc->dev; | |
4751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4753 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4754 | |
87d4300a ML |
4755 | /* |
4756 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4757 | * So diasble underrun reporting before all the planes get disabled. | |
4758 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4759 | * but leave the pipe running. | |
4760 | */ | |
4761 | if (IS_GEN2(dev)) | |
4762 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4763 | |
87d4300a ML |
4764 | /* |
4765 | * Vblank time updates from the shadow to live plane control register | |
4766 | * are blocked if the memory self-refresh mode is active at that | |
4767 | * moment. So to make sure the plane gets truly disabled, disable | |
4768 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4769 | * will be checked/applied by the HW only at the next frame start | |
4770 | * event which is after the vblank start event, so we need to have a | |
4771 | * wait-for-vblank between disabling the plane and the pipe. | |
4772 | */ | |
262cd2e1 | 4773 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4774 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4775 | dev_priv->wm.vlv.cxsr = false; |
4776 | intel_wait_for_vblank(dev, pipe); | |
4777 | } | |
87d4300a | 4778 | |
87d4300a ML |
4779 | /* |
4780 | * FIXME IPS should be fine as long as one plane is | |
4781 | * enabled, but in practice it seems to have problems | |
4782 | * when going from primary only to sprite only and vice | |
4783 | * versa. | |
4784 | */ | |
a5c4d7bc | 4785 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4786 | } |
4787 | ||
ac21b225 ML |
4788 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4789 | { | |
4790 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4791 | struct intel_crtc_state *pipe_config = |
4792 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4793 | struct drm_device *dev = crtc->base.dev; |
ac21b225 | 4794 | |
ac21b225 ML |
4795 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4796 | ||
ab1d3a0e | 4797 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4798 | |
b9001114 | 4799 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4800 | intel_update_watermarks(&crtc->base); |
4801 | ||
c80ac854 | 4802 | if (atomic->update_fbc) |
1eb52238 | 4803 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4804 | |
4805 | if (atomic->post_enable_primary) | |
4806 | intel_post_enable_primary(&crtc->base); | |
4807 | ||
ac21b225 ML |
4808 | memset(atomic, 0, sizeof(*atomic)); |
4809 | } | |
4810 | ||
5c74cd73 | 4811 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4812 | { |
5c74cd73 | 4813 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4814 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4815 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4816 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4817 | struct intel_crtc_state *pipe_config = |
4818 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4819 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4820 | struct drm_plane *primary = crtc->base.primary; | |
4821 | struct drm_plane_state *old_pri_state = | |
4822 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4823 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4824 | |
1eb52238 PZ |
4825 | if (atomic->update_fbc) |
4826 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4827 | |
5c74cd73 ML |
4828 | if (old_pri_state) { |
4829 | struct intel_plane_state *primary_state = | |
4830 | to_intel_plane_state(primary->state); | |
4831 | struct intel_plane_state *old_primary_state = | |
4832 | to_intel_plane_state(old_pri_state); | |
4833 | ||
4834 | if (old_primary_state->visible && | |
4835 | (modeset || !primary_state->visible)) | |
4836 | intel_pre_disable_primary(&crtc->base); | |
4837 | } | |
852eb00d | 4838 | |
ab1d3a0e | 4839 | if (pipe_config->disable_cxsr) { |
852eb00d | 4840 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4841 | |
4842 | if (old_crtc_state->base.active) | |
4843 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4844 | } |
92826fcd | 4845 | |
bf220452 | 4846 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) |
92826fcd | 4847 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4848 | } |
4849 | ||
d032ffa0 | 4850 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4851 | { |
4852 | struct drm_device *dev = crtc->dev; | |
4853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4854 | struct drm_plane *p; |
87d4300a ML |
4855 | int pipe = intel_crtc->pipe; |
4856 | ||
7cac945f | 4857 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4858 | |
d032ffa0 ML |
4859 | drm_for_each_plane_mask(p, dev, plane_mask) |
4860 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4861 | |
f99d7069 DV |
4862 | /* |
4863 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4864 | * to compute the mask of flip planes precisely. For the time being | |
4865 | * consider this a flip to a NULL plane. | |
4866 | */ | |
4867 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4868 | } |
4869 | ||
f67a559d JB |
4870 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4871 | { | |
4872 | struct drm_device *dev = crtc->dev; | |
4873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4875 | struct intel_encoder *encoder; |
f67a559d | 4876 | int pipe = intel_crtc->pipe; |
f67a559d | 4877 | |
53d9f4e9 | 4878 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4879 | return; |
4880 | ||
81b088ca VS |
4881 | if (intel_crtc->config->has_pch_encoder) |
4882 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4883 | ||
6e3c9717 | 4884 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4885 | intel_prepare_shared_dpll(intel_crtc); |
4886 | ||
6e3c9717 | 4887 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4888 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4889 | |
4890 | intel_set_pipe_timings(intel_crtc); | |
4891 | ||
6e3c9717 | 4892 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4893 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4894 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4895 | } |
4896 | ||
4897 | ironlake_set_pipeconf(crtc); | |
4898 | ||
f67a559d | 4899 | intel_crtc->active = true; |
8664281b | 4900 | |
a72e4c9f | 4901 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4902 | |
f6736a1a | 4903 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4904 | if (encoder->pre_enable) |
4905 | encoder->pre_enable(encoder); | |
f67a559d | 4906 | |
6e3c9717 | 4907 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4908 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4909 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4910 | * enabling. */ | |
88cefb6c | 4911 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4912 | } else { |
4913 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4914 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4915 | } | |
f67a559d | 4916 | |
b074cec8 | 4917 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4918 | |
9c54c0dd JB |
4919 | /* |
4920 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4921 | * clocks enabled | |
4922 | */ | |
4923 | intel_crtc_load_lut(crtc); | |
4924 | ||
f37fcc2a | 4925 | intel_update_watermarks(crtc); |
e1fdc473 | 4926 | intel_enable_pipe(intel_crtc); |
f67a559d | 4927 | |
6e3c9717 | 4928 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4929 | ironlake_pch_enable(crtc); |
c98e9dcf | 4930 | |
f9b61ff6 DV |
4931 | assert_vblank_disabled(crtc); |
4932 | drm_crtc_vblank_on(crtc); | |
4933 | ||
fa5c73b1 DV |
4934 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4935 | encoder->enable(encoder); | |
61b77ddd DV |
4936 | |
4937 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4938 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4939 | |
4940 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4941 | if (intel_crtc->config->has_pch_encoder) | |
4942 | intel_wait_for_vblank(dev, pipe); | |
4943 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4944 | } |
4945 | ||
42db64ef PZ |
4946 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4947 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4948 | { | |
f5adf94e | 4949 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4950 | } |
4951 | ||
4f771f10 PZ |
4952 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4953 | { | |
4954 | struct drm_device *dev = crtc->dev; | |
4955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4957 | struct intel_encoder *encoder; | |
99d736a2 ML |
4958 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4959 | struct intel_crtc_state *pipe_config = | |
4960 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4961 | |
53d9f4e9 | 4962 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4963 | return; |
4964 | ||
81b088ca VS |
4965 | if (intel_crtc->config->has_pch_encoder) |
4966 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4967 | false); | |
4968 | ||
df8ad70c DV |
4969 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4970 | intel_enable_shared_dpll(intel_crtc); | |
4971 | ||
6e3c9717 | 4972 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4973 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4974 | |
4975 | intel_set_pipe_timings(intel_crtc); | |
4976 | ||
6e3c9717 ACO |
4977 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4978 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4979 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4980 | } |
4981 | ||
6e3c9717 | 4982 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4983 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4984 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4985 | } |
4986 | ||
4987 | haswell_set_pipeconf(crtc); | |
4988 | ||
4989 | intel_set_pipe_csc(crtc); | |
4990 | ||
4f771f10 | 4991 | intel_crtc->active = true; |
8664281b | 4992 | |
6b698516 DV |
4993 | if (intel_crtc->config->has_pch_encoder) |
4994 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4995 | else | |
4996 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4997 | ||
7d4aefd0 | 4998 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4999 | if (encoder->pre_enable) |
5000 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5001 | } |
4f771f10 | 5002 | |
d2d65408 | 5003 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5004 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5005 | |
a65347ba | 5006 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5007 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5008 | |
1c132b44 | 5009 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5010 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5011 | else |
1c132b44 | 5012 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5013 | |
5014 | /* | |
5015 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5016 | * clocks enabled | |
5017 | */ | |
5018 | intel_crtc_load_lut(crtc); | |
5019 | ||
1f544388 | 5020 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5021 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5022 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5023 | |
f37fcc2a | 5024 | intel_update_watermarks(crtc); |
e1fdc473 | 5025 | intel_enable_pipe(intel_crtc); |
42db64ef | 5026 | |
6e3c9717 | 5027 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5028 | lpt_pch_enable(crtc); |
4f771f10 | 5029 | |
a65347ba | 5030 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5031 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5032 | ||
f9b61ff6 DV |
5033 | assert_vblank_disabled(crtc); |
5034 | drm_crtc_vblank_on(crtc); | |
5035 | ||
8807e55b | 5036 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5037 | encoder->enable(encoder); |
8807e55b JN |
5038 | intel_opregion_notify_encoder(encoder, true); |
5039 | } | |
4f771f10 | 5040 | |
6b698516 DV |
5041 | if (intel_crtc->config->has_pch_encoder) { |
5042 | intel_wait_for_vblank(dev, pipe); | |
5043 | intel_wait_for_vblank(dev, pipe); | |
5044 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5045 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5046 | true); | |
6b698516 | 5047 | } |
d2d65408 | 5048 | |
e4916946 PZ |
5049 | /* If we change the relative order between pipe/planes enabling, we need |
5050 | * to change the workaround. */ | |
99d736a2 ML |
5051 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5052 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5053 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5054 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5055 | } | |
4f771f10 PZ |
5056 | } |
5057 | ||
bfd16b2a | 5058 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5059 | { |
5060 | struct drm_device *dev = crtc->base.dev; | |
5061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5062 | int pipe = crtc->pipe; | |
5063 | ||
5064 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5065 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5066 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5067 | I915_WRITE(PF_CTL(pipe), 0); |
5068 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5069 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5070 | } | |
5071 | } | |
5072 | ||
6be4a607 JB |
5073 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5074 | { | |
5075 | struct drm_device *dev = crtc->dev; | |
5076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5078 | struct intel_encoder *encoder; |
6be4a607 | 5079 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5080 | |
37ca8d4c VS |
5081 | if (intel_crtc->config->has_pch_encoder) |
5082 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5083 | ||
ea9d758d DV |
5084 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5085 | encoder->disable(encoder); | |
5086 | ||
f9b61ff6 DV |
5087 | drm_crtc_vblank_off(crtc); |
5088 | assert_vblank_disabled(crtc); | |
5089 | ||
3860b2ec VS |
5090 | /* |
5091 | * Sometimes spurious CPU pipe underruns happen when the | |
5092 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5093 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5094 | */ | |
5095 | if (intel_crtc->config->has_pch_encoder) | |
5096 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5097 | ||
575f7ab7 | 5098 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5099 | |
bfd16b2a | 5100 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5101 | |
3860b2ec | 5102 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5103 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5104 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5105 | } | |
5a74f70a | 5106 | |
bf49ec8c DV |
5107 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5108 | if (encoder->post_disable) | |
5109 | encoder->post_disable(encoder); | |
2c07245f | 5110 | |
6e3c9717 | 5111 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5112 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5113 | |
d925c59a | 5114 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5115 | i915_reg_t reg; |
5116 | u32 temp; | |
5117 | ||
d925c59a DV |
5118 | /* disable TRANS_DP_CTL */ |
5119 | reg = TRANS_DP_CTL(pipe); | |
5120 | temp = I915_READ(reg); | |
5121 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5122 | TRANS_DP_PORT_SEL_MASK); | |
5123 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5124 | I915_WRITE(reg, temp); | |
5125 | ||
5126 | /* disable DPLL_SEL */ | |
5127 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5128 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5129 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5130 | } |
e3421a18 | 5131 | |
d925c59a DV |
5132 | ironlake_fdi_pll_disable(intel_crtc); |
5133 | } | |
81b088ca VS |
5134 | |
5135 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5136 | } |
1b3c7a47 | 5137 | |
4f771f10 | 5138 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5139 | { |
4f771f10 PZ |
5140 | struct drm_device *dev = crtc->dev; |
5141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5143 | struct intel_encoder *encoder; |
6e3c9717 | 5144 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5145 | |
d2d65408 VS |
5146 | if (intel_crtc->config->has_pch_encoder) |
5147 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5148 | false); | |
5149 | ||
8807e55b JN |
5150 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5151 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5152 | encoder->disable(encoder); |
8807e55b | 5153 | } |
4f771f10 | 5154 | |
f9b61ff6 DV |
5155 | drm_crtc_vblank_off(crtc); |
5156 | assert_vblank_disabled(crtc); | |
5157 | ||
575f7ab7 | 5158 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5159 | |
6e3c9717 | 5160 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5161 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5162 | ||
a65347ba | 5163 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5164 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5165 | |
1c132b44 | 5166 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5167 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5168 | else |
bfd16b2a | 5169 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5170 | |
a65347ba | 5171 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5172 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5173 | |
97b040aa ID |
5174 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5175 | if (encoder->post_disable) | |
5176 | encoder->post_disable(encoder); | |
81b088ca | 5177 | |
92966a37 VS |
5178 | if (intel_crtc->config->has_pch_encoder) { |
5179 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5180 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5181 | intel_ddi_fdi_disable(crtc); |
5182 | ||
81b088ca VS |
5183 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5184 | true); | |
92966a37 | 5185 | } |
4f771f10 PZ |
5186 | } |
5187 | ||
2dd24552 JB |
5188 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5189 | { | |
5190 | struct drm_device *dev = crtc->base.dev; | |
5191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5192 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5193 | |
681a8504 | 5194 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5195 | return; |
5196 | ||
2dd24552 | 5197 | /* |
c0b03411 DV |
5198 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5199 | * according to register description and PRM. | |
2dd24552 | 5200 | */ |
c0b03411 DV |
5201 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5202 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5203 | |
b074cec8 JB |
5204 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5205 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5206 | |
5207 | /* Border color in case we don't scale up to the full screen. Black by | |
5208 | * default, change to something else for debugging. */ | |
5209 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5210 | } |
5211 | ||
d05410f9 DA |
5212 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5213 | { | |
5214 | switch (port) { | |
5215 | case PORT_A: | |
6331a704 | 5216 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5217 | case PORT_B: |
6331a704 | 5218 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5219 | case PORT_C: |
6331a704 | 5220 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5221 | case PORT_D: |
6331a704 | 5222 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5223 | case PORT_E: |
6331a704 | 5224 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5225 | default: |
b9fec167 | 5226 | MISSING_CASE(port); |
d05410f9 DA |
5227 | return POWER_DOMAIN_PORT_OTHER; |
5228 | } | |
5229 | } | |
5230 | ||
25f78f58 VS |
5231 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5232 | { | |
5233 | switch (port) { | |
5234 | case PORT_A: | |
5235 | return POWER_DOMAIN_AUX_A; | |
5236 | case PORT_B: | |
5237 | return POWER_DOMAIN_AUX_B; | |
5238 | case PORT_C: | |
5239 | return POWER_DOMAIN_AUX_C; | |
5240 | case PORT_D: | |
5241 | return POWER_DOMAIN_AUX_D; | |
5242 | case PORT_E: | |
5243 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5244 | return POWER_DOMAIN_AUX_D; | |
5245 | default: | |
b9fec167 | 5246 | MISSING_CASE(port); |
25f78f58 VS |
5247 | return POWER_DOMAIN_AUX_A; |
5248 | } | |
5249 | } | |
5250 | ||
319be8ae ID |
5251 | enum intel_display_power_domain |
5252 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5253 | { | |
5254 | struct drm_device *dev = intel_encoder->base.dev; | |
5255 | struct intel_digital_port *intel_dig_port; | |
5256 | ||
5257 | switch (intel_encoder->type) { | |
5258 | case INTEL_OUTPUT_UNKNOWN: | |
5259 | /* Only DDI platforms should ever use this output type */ | |
5260 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5261 | case INTEL_OUTPUT_DISPLAYPORT: | |
5262 | case INTEL_OUTPUT_HDMI: | |
5263 | case INTEL_OUTPUT_EDP: | |
5264 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5265 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5266 | case INTEL_OUTPUT_DP_MST: |
5267 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5268 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5269 | case INTEL_OUTPUT_ANALOG: |
5270 | return POWER_DOMAIN_PORT_CRT; | |
5271 | case INTEL_OUTPUT_DSI: | |
5272 | return POWER_DOMAIN_PORT_DSI; | |
5273 | default: | |
5274 | return POWER_DOMAIN_PORT_OTHER; | |
5275 | } | |
5276 | } | |
5277 | ||
25f78f58 VS |
5278 | enum intel_display_power_domain |
5279 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5280 | { | |
5281 | struct drm_device *dev = intel_encoder->base.dev; | |
5282 | struct intel_digital_port *intel_dig_port; | |
5283 | ||
5284 | switch (intel_encoder->type) { | |
5285 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5286 | case INTEL_OUTPUT_HDMI: |
5287 | /* | |
5288 | * Only DDI platforms should ever use these output types. | |
5289 | * We can get here after the HDMI detect code has already set | |
5290 | * the type of the shared encoder. Since we can't be sure | |
5291 | * what's the status of the given connectors, play safe and | |
5292 | * run the DP detection too. | |
5293 | */ | |
25f78f58 VS |
5294 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5295 | case INTEL_OUTPUT_DISPLAYPORT: | |
5296 | case INTEL_OUTPUT_EDP: | |
5297 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5298 | return port_to_aux_power_domain(intel_dig_port->port); | |
5299 | case INTEL_OUTPUT_DP_MST: | |
5300 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5301 | return port_to_aux_power_domain(intel_dig_port->port); | |
5302 | default: | |
b9fec167 | 5303 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5304 | return POWER_DOMAIN_AUX_A; |
5305 | } | |
5306 | } | |
5307 | ||
74bff5f9 ML |
5308 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5309 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5310 | { |
319be8ae | 5311 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5312 | struct drm_encoder *encoder; |
319be8ae ID |
5313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5314 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5315 | unsigned long mask; |
74bff5f9 | 5316 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5317 | |
74bff5f9 | 5318 | if (!crtc_state->base.active) |
292b990e ML |
5319 | return 0; |
5320 | ||
77d22dca ID |
5321 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5322 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5323 | if (crtc_state->pch_pfit.enabled || |
5324 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5325 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5326 | ||
74bff5f9 ML |
5327 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5328 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5329 | ||
319be8ae | 5330 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5331 | } |
319be8ae | 5332 | |
77d22dca ID |
5333 | return mask; |
5334 | } | |
5335 | ||
74bff5f9 ML |
5336 | static unsigned long |
5337 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5338 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5339 | { |
292b990e ML |
5340 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5342 | enum intel_display_power_domain domain; | |
5343 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5344 | |
292b990e | 5345 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5346 | intel_crtc->enabled_power_domains = new_domains = |
5347 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5348 | |
292b990e ML |
5349 | domains = new_domains & ~old_domains; |
5350 | ||
5351 | for_each_power_domain(domain, domains) | |
5352 | intel_display_power_get(dev_priv, domain); | |
5353 | ||
5354 | return old_domains & ~new_domains; | |
5355 | } | |
5356 | ||
5357 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5358 | unsigned long domains) | |
5359 | { | |
5360 | enum intel_display_power_domain domain; | |
5361 | ||
5362 | for_each_power_domain(domain, domains) | |
5363 | intel_display_power_put(dev_priv, domain); | |
5364 | } | |
77d22dca | 5365 | |
adafdc6f MK |
5366 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5367 | { | |
5368 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5369 | ||
5370 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5371 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5372 | return max_cdclk_freq; | |
5373 | else if (IS_CHERRYVIEW(dev_priv)) | |
5374 | return max_cdclk_freq*95/100; | |
5375 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5376 | return 2*max_cdclk_freq*90/100; | |
5377 | else | |
5378 | return max_cdclk_freq*90/100; | |
5379 | } | |
5380 | ||
560a7ae4 DL |
5381 | static void intel_update_max_cdclk(struct drm_device *dev) |
5382 | { | |
5383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5384 | ||
ef11bdb3 | 5385 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5386 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5387 | ||
5388 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5389 | dev_priv->max_cdclk_freq = 675000; | |
5390 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5391 | dev_priv->max_cdclk_freq = 540000; | |
5392 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5393 | dev_priv->max_cdclk_freq = 450000; | |
5394 | else | |
5395 | dev_priv->max_cdclk_freq = 337500; | |
5396 | } else if (IS_BROADWELL(dev)) { | |
5397 | /* | |
5398 | * FIXME with extra cooling we can allow | |
5399 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5400 | * How can we know if extra cooling is | |
5401 | * available? PCI ID, VTB, something else? | |
5402 | */ | |
5403 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5404 | dev_priv->max_cdclk_freq = 450000; | |
5405 | else if (IS_BDW_ULX(dev)) | |
5406 | dev_priv->max_cdclk_freq = 450000; | |
5407 | else if (IS_BDW_ULT(dev)) | |
5408 | dev_priv->max_cdclk_freq = 540000; | |
5409 | else | |
5410 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5411 | } else if (IS_CHERRYVIEW(dev)) { |
5412 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5413 | } else if (IS_VALLEYVIEW(dev)) { |
5414 | dev_priv->max_cdclk_freq = 400000; | |
5415 | } else { | |
5416 | /* otherwise assume cdclk is fixed */ | |
5417 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5418 | } | |
5419 | ||
adafdc6f MK |
5420 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5421 | ||
560a7ae4 DL |
5422 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5423 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5424 | |
5425 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5426 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5427 | } |
5428 | ||
5429 | static void intel_update_cdclk(struct drm_device *dev) | |
5430 | { | |
5431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5432 | ||
5433 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5434 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5435 | dev_priv->cdclk_freq); | |
5436 | ||
5437 | /* | |
5438 | * Program the gmbus_freq based on the cdclk frequency. | |
5439 | * BSpec erroneously claims we should aim for 4MHz, but | |
5440 | * in fact 1MHz is the correct frequency. | |
5441 | */ | |
666a4537 | 5442 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5443 | /* |
5444 | * Program the gmbus_freq based on the cdclk frequency. | |
5445 | * BSpec erroneously claims we should aim for 4MHz, but | |
5446 | * in fact 1MHz is the correct frequency. | |
5447 | */ | |
5448 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5449 | } | |
5450 | ||
5451 | if (dev_priv->max_cdclk_freq == 0) | |
5452 | intel_update_max_cdclk(dev); | |
5453 | } | |
5454 | ||
70d0c574 | 5455 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5456 | { |
5457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5458 | uint32_t divider; | |
5459 | uint32_t ratio; | |
5460 | uint32_t current_freq; | |
5461 | int ret; | |
5462 | ||
5463 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5464 | switch (frequency) { | |
5465 | case 144000: | |
5466 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5467 | ratio = BXT_DE_PLL_RATIO(60); | |
5468 | break; | |
5469 | case 288000: | |
5470 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5471 | ratio = BXT_DE_PLL_RATIO(60); | |
5472 | break; | |
5473 | case 384000: | |
5474 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5475 | ratio = BXT_DE_PLL_RATIO(60); | |
5476 | break; | |
5477 | case 576000: | |
5478 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5479 | ratio = BXT_DE_PLL_RATIO(60); | |
5480 | break; | |
5481 | case 624000: | |
5482 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5483 | ratio = BXT_DE_PLL_RATIO(65); | |
5484 | break; | |
5485 | case 19200: | |
5486 | /* | |
5487 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5488 | * to suppress GCC warning. | |
5489 | */ | |
5490 | ratio = 0; | |
5491 | divider = 0; | |
5492 | break; | |
5493 | default: | |
5494 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5495 | ||
5496 | return; | |
5497 | } | |
5498 | ||
5499 | mutex_lock(&dev_priv->rps.hw_lock); | |
5500 | /* Inform power controller of upcoming frequency change */ | |
5501 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5502 | 0x80000000); | |
5503 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5504 | ||
5505 | if (ret) { | |
5506 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5507 | ret, frequency); | |
5508 | return; | |
5509 | } | |
5510 | ||
5511 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5512 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5513 | current_freq = current_freq * 500 + 1000; | |
5514 | ||
5515 | /* | |
5516 | * DE PLL has to be disabled when | |
5517 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5518 | * - before setting to 624MHz (PLL needs toggling) | |
5519 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5520 | */ | |
5521 | if (frequency == 19200 || frequency == 624000 || | |
5522 | current_freq == 624000) { | |
5523 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5524 | /* Timeout 200us */ | |
5525 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5526 | 1)) | |
5527 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5528 | } | |
5529 | ||
5530 | if (frequency != 19200) { | |
5531 | uint32_t val; | |
5532 | ||
5533 | val = I915_READ(BXT_DE_PLL_CTL); | |
5534 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5535 | val |= ratio; | |
5536 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5537 | ||
5538 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5539 | /* Timeout 200us */ | |
5540 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5541 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5542 | ||
5543 | val = I915_READ(CDCLK_CTL); | |
5544 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5545 | val |= divider; | |
5546 | /* | |
5547 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5548 | * enable otherwise. | |
5549 | */ | |
5550 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5551 | if (frequency >= 500000) | |
5552 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5553 | ||
5554 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5555 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5556 | val |= (frequency - 1000) / 500; | |
5557 | I915_WRITE(CDCLK_CTL, val); | |
5558 | } | |
5559 | ||
5560 | mutex_lock(&dev_priv->rps.hw_lock); | |
5561 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5562 | DIV_ROUND_UP(frequency, 25000)); | |
5563 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5564 | ||
5565 | if (ret) { | |
5566 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5567 | ret, frequency); | |
5568 | return; | |
5569 | } | |
5570 | ||
a47871bd | 5571 | intel_update_cdclk(dev); |
f8437dd1 VK |
5572 | } |
5573 | ||
5574 | void broxton_init_cdclk(struct drm_device *dev) | |
5575 | { | |
5576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5577 | uint32_t val; | |
5578 | ||
5579 | /* | |
5580 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5581 | * or else the reset will hang because there is no PCH to respond. | |
5582 | * Move the handshake programming to initialization sequence. | |
5583 | * Previously was left up to BIOS. | |
5584 | */ | |
5585 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5586 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5587 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5588 | ||
5589 | /* Enable PG1 for cdclk */ | |
5590 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5591 | ||
5592 | /* check if cd clock is enabled */ | |
5593 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5594 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5595 | return; | |
5596 | } | |
5597 | ||
5598 | /* | |
5599 | * FIXME: | |
5600 | * - The initial CDCLK needs to be read from VBT. | |
5601 | * Need to make this change after VBT has changes for BXT. | |
5602 | * - check if setting the max (or any) cdclk freq is really necessary | |
5603 | * here, it belongs to modeset time | |
5604 | */ | |
5605 | broxton_set_cdclk(dev, 624000); | |
5606 | ||
5607 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5608 | POSTING_READ(DBUF_CTL); |
5609 | ||
f8437dd1 VK |
5610 | udelay(10); |
5611 | ||
5612 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5613 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5614 | } | |
5615 | ||
5616 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5617 | { | |
5618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5619 | ||
5620 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5621 | POSTING_READ(DBUF_CTL); |
5622 | ||
f8437dd1 VK |
5623 | udelay(10); |
5624 | ||
5625 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5626 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5627 | ||
5628 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5629 | broxton_set_cdclk(dev, 19200); | |
5630 | ||
5631 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5632 | } | |
5633 | ||
5d96d8af DL |
5634 | static const struct skl_cdclk_entry { |
5635 | unsigned int freq; | |
5636 | unsigned int vco; | |
5637 | } skl_cdclk_frequencies[] = { | |
5638 | { .freq = 308570, .vco = 8640 }, | |
5639 | { .freq = 337500, .vco = 8100 }, | |
5640 | { .freq = 432000, .vco = 8640 }, | |
5641 | { .freq = 450000, .vco = 8100 }, | |
5642 | { .freq = 540000, .vco = 8100 }, | |
5643 | { .freq = 617140, .vco = 8640 }, | |
5644 | { .freq = 675000, .vco = 8100 }, | |
5645 | }; | |
5646 | ||
5647 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5648 | { | |
5649 | return (freq - 1000) / 500; | |
5650 | } | |
5651 | ||
5652 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5653 | { | |
5654 | unsigned int i; | |
5655 | ||
5656 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5657 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5658 | ||
5659 | if (e->freq == freq) | |
5660 | return e->vco; | |
5661 | } | |
5662 | ||
5663 | return 8100; | |
5664 | } | |
5665 | ||
5666 | static void | |
5667 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5668 | { | |
5669 | unsigned int min_freq; | |
5670 | u32 val; | |
5671 | ||
5672 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5673 | val = I915_READ(CDCLK_CTL); | |
5674 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5675 | val |= CDCLK_FREQ_337_308; | |
5676 | ||
5677 | if (required_vco == 8640) | |
5678 | min_freq = 308570; | |
5679 | else | |
5680 | min_freq = 337500; | |
5681 | ||
5682 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5683 | ||
5684 | I915_WRITE(CDCLK_CTL, val); | |
5685 | POSTING_READ(CDCLK_CTL); | |
5686 | ||
5687 | /* | |
5688 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5689 | * taking into account the VCO required to operate the eDP panel at the | |
5690 | * desired frequency. The usual DP link rates operate with a VCO of | |
5691 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5692 | * The modeset code is responsible for the selection of the exact link | |
5693 | * rate later on, with the constraint of choosing a frequency that | |
5694 | * works with required_vco. | |
5695 | */ | |
5696 | val = I915_READ(DPLL_CTRL1); | |
5697 | ||
5698 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5699 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5700 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5701 | if (required_vco == 8640) | |
5702 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5703 | SKL_DPLL0); | |
5704 | else | |
5705 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5706 | SKL_DPLL0); | |
5707 | ||
5708 | I915_WRITE(DPLL_CTRL1, val); | |
5709 | POSTING_READ(DPLL_CTRL1); | |
5710 | ||
5711 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5712 | ||
5713 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5714 | DRM_ERROR("DPLL0 not locked\n"); | |
5715 | } | |
5716 | ||
5717 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5718 | { | |
5719 | int ret; | |
5720 | u32 val; | |
5721 | ||
5722 | /* inform PCU we want to change CDCLK */ | |
5723 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5724 | mutex_lock(&dev_priv->rps.hw_lock); | |
5725 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5726 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5727 | ||
5728 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5729 | } | |
5730 | ||
5731 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5732 | { | |
5733 | unsigned int i; | |
5734 | ||
5735 | for (i = 0; i < 15; i++) { | |
5736 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5737 | return true; | |
5738 | udelay(10); | |
5739 | } | |
5740 | ||
5741 | return false; | |
5742 | } | |
5743 | ||
5744 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5745 | { | |
560a7ae4 | 5746 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5747 | u32 freq_select, pcu_ack; |
5748 | ||
5749 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5750 | ||
5751 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5752 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5753 | return; | |
5754 | } | |
5755 | ||
5756 | /* set CDCLK_CTL */ | |
5757 | switch(freq) { | |
5758 | case 450000: | |
5759 | case 432000: | |
5760 | freq_select = CDCLK_FREQ_450_432; | |
5761 | pcu_ack = 1; | |
5762 | break; | |
5763 | case 540000: | |
5764 | freq_select = CDCLK_FREQ_540; | |
5765 | pcu_ack = 2; | |
5766 | break; | |
5767 | case 308570: | |
5768 | case 337500: | |
5769 | default: | |
5770 | freq_select = CDCLK_FREQ_337_308; | |
5771 | pcu_ack = 0; | |
5772 | break; | |
5773 | case 617140: | |
5774 | case 675000: | |
5775 | freq_select = CDCLK_FREQ_675_617; | |
5776 | pcu_ack = 3; | |
5777 | break; | |
5778 | } | |
5779 | ||
5780 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5781 | POSTING_READ(CDCLK_CTL); | |
5782 | ||
5783 | /* inform PCU of the change */ | |
5784 | mutex_lock(&dev_priv->rps.hw_lock); | |
5785 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5786 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5787 | |
5788 | intel_update_cdclk(dev); | |
5d96d8af DL |
5789 | } |
5790 | ||
5791 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5792 | { | |
5793 | /* disable DBUF power */ | |
5794 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5795 | POSTING_READ(DBUF_CTL); | |
5796 | ||
5797 | udelay(10); | |
5798 | ||
5799 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5800 | DRM_ERROR("DBuf power disable timeout\n"); | |
5801 | ||
ab96c1ee ID |
5802 | /* disable DPLL0 */ |
5803 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5804 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5805 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5806 | } |
5807 | ||
5808 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5809 | { | |
5d96d8af DL |
5810 | unsigned int required_vco; |
5811 | ||
39d9b85a GW |
5812 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5813 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5814 | /* enable DPLL0 */ | |
5815 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5816 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5817 | } |
5818 | ||
5d96d8af DL |
5819 | /* set CDCLK to the frequency the BIOS chose */ |
5820 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5821 | ||
5822 | /* enable DBUF power */ | |
5823 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5824 | POSTING_READ(DBUF_CTL); | |
5825 | ||
5826 | udelay(10); | |
5827 | ||
5828 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5829 | DRM_ERROR("DBuf power enable timeout\n"); | |
5830 | } | |
5831 | ||
c73666f3 SK |
5832 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5833 | { | |
5834 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5835 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5836 | int freq = dev_priv->skl_boot_cdclk; | |
5837 | ||
f1b391a5 SK |
5838 | /* |
5839 | * check if the pre-os intialized the display | |
5840 | * There is SWF18 scratchpad register defined which is set by the | |
5841 | * pre-os which can be used by the OS drivers to check the status | |
5842 | */ | |
5843 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5844 | goto sanitize; | |
5845 | ||
c73666f3 SK |
5846 | /* Is PLL enabled and locked ? */ |
5847 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5848 | goto sanitize; | |
5849 | ||
5850 | /* DPLL okay; verify the cdclock | |
5851 | * | |
5852 | * Noticed in some instances that the freq selection is correct but | |
5853 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5854 | * enable display. Verify the same as well. | |
5855 | */ | |
5856 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5857 | /* All well; nothing to sanitize */ | |
5858 | return false; | |
5859 | sanitize: | |
5860 | /* | |
5861 | * As of now initialize with max cdclk till | |
5862 | * we get dynamic cdclk support | |
5863 | * */ | |
5864 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5865 | skl_init_cdclk(dev_priv); | |
5866 | ||
5867 | /* we did have to sanitize */ | |
5868 | return true; | |
5869 | } | |
5870 | ||
30a970c6 JB |
5871 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5872 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5873 | { | |
5874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5875 | u32 val, cmd; | |
5876 | ||
164dfd28 VK |
5877 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5878 | != dev_priv->cdclk_freq); | |
d60c4473 | 5879 | |
dfcab17e | 5880 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5881 | cmd = 2; |
dfcab17e | 5882 | else if (cdclk == 266667) |
30a970c6 JB |
5883 | cmd = 1; |
5884 | else | |
5885 | cmd = 0; | |
5886 | ||
5887 | mutex_lock(&dev_priv->rps.hw_lock); | |
5888 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5889 | val &= ~DSPFREQGUAR_MASK; | |
5890 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5891 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5892 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5893 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5894 | 50)) { | |
5895 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5896 | } | |
5897 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5898 | ||
54433e91 VS |
5899 | mutex_lock(&dev_priv->sb_lock); |
5900 | ||
dfcab17e | 5901 | if (cdclk == 400000) { |
6bcda4f0 | 5902 | u32 divider; |
30a970c6 | 5903 | |
6bcda4f0 | 5904 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5905 | |
30a970c6 JB |
5906 | /* adjust cdclk divider */ |
5907 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5908 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5909 | val |= divider; |
5910 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5911 | |
5912 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5913 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5914 | 50)) |
5915 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5916 | } |
5917 | ||
30a970c6 JB |
5918 | /* adjust self-refresh exit latency value */ |
5919 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5920 | val &= ~0x7f; | |
5921 | ||
5922 | /* | |
5923 | * For high bandwidth configs, we set a higher latency in the bunit | |
5924 | * so that the core display fetch happens in time to avoid underruns. | |
5925 | */ | |
dfcab17e | 5926 | if (cdclk == 400000) |
30a970c6 JB |
5927 | val |= 4500 / 250; /* 4.5 usec */ |
5928 | else | |
5929 | val |= 3000 / 250; /* 3.0 usec */ | |
5930 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5931 | |
a580516d | 5932 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5933 | |
b6283055 | 5934 | intel_update_cdclk(dev); |
30a970c6 JB |
5935 | } |
5936 | ||
383c5a6a VS |
5937 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5938 | { | |
5939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5940 | u32 val, cmd; | |
5941 | ||
164dfd28 VK |
5942 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5943 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5944 | |
5945 | switch (cdclk) { | |
383c5a6a VS |
5946 | case 333333: |
5947 | case 320000: | |
383c5a6a | 5948 | case 266667: |
383c5a6a | 5949 | case 200000: |
383c5a6a VS |
5950 | break; |
5951 | default: | |
5f77eeb0 | 5952 | MISSING_CASE(cdclk); |
383c5a6a VS |
5953 | return; |
5954 | } | |
5955 | ||
9d0d3fda VS |
5956 | /* |
5957 | * Specs are full of misinformation, but testing on actual | |
5958 | * hardware has shown that we just need to write the desired | |
5959 | * CCK divider into the Punit register. | |
5960 | */ | |
5961 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5962 | ||
383c5a6a VS |
5963 | mutex_lock(&dev_priv->rps.hw_lock); |
5964 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5965 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5966 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5967 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5968 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5969 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5970 | 50)) { | |
5971 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5972 | } | |
5973 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5974 | ||
b6283055 | 5975 | intel_update_cdclk(dev); |
383c5a6a VS |
5976 | } |
5977 | ||
30a970c6 JB |
5978 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5979 | int max_pixclk) | |
5980 | { | |
6bcda4f0 | 5981 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5982 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5983 | |
30a970c6 JB |
5984 | /* |
5985 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5986 | * 200MHz | |
5987 | * 267MHz | |
29dc7ef3 | 5988 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5989 | * 400MHz (VLV only) |
5990 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5991 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5992 | * |
5993 | * We seem to get an unstable or solid color picture at 200MHz. | |
5994 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5995 | * are off. | |
30a970c6 | 5996 | */ |
6cca3195 VS |
5997 | if (!IS_CHERRYVIEW(dev_priv) && |
5998 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5999 | return 400000; |
6cca3195 | 6000 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6001 | return freq_320; |
e37c67a1 | 6002 | else if (max_pixclk > 0) |
dfcab17e | 6003 | return 266667; |
e37c67a1 VS |
6004 | else |
6005 | return 200000; | |
30a970c6 JB |
6006 | } |
6007 | ||
f8437dd1 VK |
6008 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6009 | int max_pixclk) | |
6010 | { | |
6011 | /* | |
6012 | * FIXME: | |
6013 | * - remove the guardband, it's not needed on BXT | |
6014 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6015 | */ | |
6016 | if (max_pixclk > 576000*9/10) | |
6017 | return 624000; | |
6018 | else if (max_pixclk > 384000*9/10) | |
6019 | return 576000; | |
6020 | else if (max_pixclk > 288000*9/10) | |
6021 | return 384000; | |
6022 | else if (max_pixclk > 144000*9/10) | |
6023 | return 288000; | |
6024 | else | |
6025 | return 144000; | |
6026 | } | |
6027 | ||
e8788cbc | 6028 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6029 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6030 | struct drm_atomic_state *state) | |
30a970c6 | 6031 | { |
565602d7 ML |
6032 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6034 | struct drm_crtc *crtc; | |
6035 | struct drm_crtc_state *crtc_state; | |
6036 | unsigned max_pixclk = 0, i; | |
6037 | enum pipe pipe; | |
30a970c6 | 6038 | |
565602d7 ML |
6039 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6040 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6041 | |
565602d7 ML |
6042 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6043 | int pixclk = 0; | |
6044 | ||
6045 | if (crtc_state->enable) | |
6046 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6047 | |
565602d7 | 6048 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6049 | } |
6050 | ||
565602d7 ML |
6051 | for_each_pipe(dev_priv, pipe) |
6052 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6053 | ||
30a970c6 JB |
6054 | return max_pixclk; |
6055 | } | |
6056 | ||
27c329ed | 6057 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6058 | { |
27c329ed ML |
6059 | struct drm_device *dev = state->dev; |
6060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6061 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6062 | struct intel_atomic_state *intel_state = |
6063 | to_intel_atomic_state(state); | |
30a970c6 | 6064 | |
304603f4 ACO |
6065 | if (max_pixclk < 0) |
6066 | return max_pixclk; | |
30a970c6 | 6067 | |
1a617b77 | 6068 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6069 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6070 | |
1a617b77 ML |
6071 | if (!intel_state->active_crtcs) |
6072 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6073 | ||
27c329ed ML |
6074 | return 0; |
6075 | } | |
304603f4 | 6076 | |
27c329ed ML |
6077 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6078 | { | |
6079 | struct drm_device *dev = state->dev; | |
6080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6081 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6082 | struct intel_atomic_state *intel_state = |
6083 | to_intel_atomic_state(state); | |
85a96e7a | 6084 | |
27c329ed ML |
6085 | if (max_pixclk < 0) |
6086 | return max_pixclk; | |
85a96e7a | 6087 | |
1a617b77 | 6088 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6089 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6090 | |
1a617b77 ML |
6091 | if (!intel_state->active_crtcs) |
6092 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6093 | ||
27c329ed | 6094 | return 0; |
30a970c6 JB |
6095 | } |
6096 | ||
1e69cd74 VS |
6097 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6098 | { | |
6099 | unsigned int credits, default_credits; | |
6100 | ||
6101 | if (IS_CHERRYVIEW(dev_priv)) | |
6102 | default_credits = PFI_CREDIT(12); | |
6103 | else | |
6104 | default_credits = PFI_CREDIT(8); | |
6105 | ||
bfa7df01 | 6106 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6107 | /* CHV suggested value is 31 or 63 */ |
6108 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6109 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6110 | else |
6111 | credits = PFI_CREDIT(15); | |
6112 | } else { | |
6113 | credits = default_credits; | |
6114 | } | |
6115 | ||
6116 | /* | |
6117 | * WA - write default credits before re-programming | |
6118 | * FIXME: should we also set the resend bit here? | |
6119 | */ | |
6120 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6121 | default_credits); | |
6122 | ||
6123 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6124 | credits | PFI_CREDIT_RESEND); | |
6125 | ||
6126 | /* | |
6127 | * FIXME is this guaranteed to clear | |
6128 | * immediately or should we poll for it? | |
6129 | */ | |
6130 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6131 | } | |
6132 | ||
27c329ed | 6133 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6134 | { |
a821fc46 | 6135 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6136 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6137 | struct intel_atomic_state *old_intel_state = |
6138 | to_intel_atomic_state(old_state); | |
6139 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6140 | |
27c329ed ML |
6141 | /* |
6142 | * FIXME: We can end up here with all power domains off, yet | |
6143 | * with a CDCLK frequency other than the minimum. To account | |
6144 | * for this take the PIPE-A power domain, which covers the HW | |
6145 | * blocks needed for the following programming. This can be | |
6146 | * removed once it's guaranteed that we get here either with | |
6147 | * the minimum CDCLK set, or the required power domains | |
6148 | * enabled. | |
6149 | */ | |
6150 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6151 | |
27c329ed ML |
6152 | if (IS_CHERRYVIEW(dev)) |
6153 | cherryview_set_cdclk(dev, req_cdclk); | |
6154 | else | |
6155 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6156 | |
27c329ed | 6157 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6158 | |
27c329ed | 6159 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6160 | } |
6161 | ||
89b667f8 JB |
6162 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6163 | { | |
6164 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6165 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6167 | struct intel_encoder *encoder; | |
6168 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6169 | |
53d9f4e9 | 6170 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6171 | return; |
6172 | ||
6e3c9717 | 6173 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6174 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6175 | |
6176 | intel_set_pipe_timings(intel_crtc); | |
6177 | ||
c14b0485 VS |
6178 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6180 | ||
6181 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6182 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6183 | } | |
6184 | ||
5b18e57c DV |
6185 | i9xx_set_pipeconf(intel_crtc); |
6186 | ||
89b667f8 | 6187 | intel_crtc->active = true; |
89b667f8 | 6188 | |
a72e4c9f | 6189 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6190 | |
89b667f8 JB |
6191 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6192 | if (encoder->pre_pll_enable) | |
6193 | encoder->pre_pll_enable(encoder); | |
6194 | ||
a65347ba | 6195 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6196 | if (IS_CHERRYVIEW(dev)) { |
6197 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6198 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6199 | } else { |
6200 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6201 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6202 | } |
9d556c99 | 6203 | } |
89b667f8 JB |
6204 | |
6205 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6206 | if (encoder->pre_enable) | |
6207 | encoder->pre_enable(encoder); | |
6208 | ||
2dd24552 JB |
6209 | i9xx_pfit_enable(intel_crtc); |
6210 | ||
63cbb074 VS |
6211 | intel_crtc_load_lut(crtc); |
6212 | ||
e1fdc473 | 6213 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6214 | |
4b3a9526 VS |
6215 | assert_vblank_disabled(crtc); |
6216 | drm_crtc_vblank_on(crtc); | |
6217 | ||
f9b61ff6 DV |
6218 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6219 | encoder->enable(encoder); | |
89b667f8 JB |
6220 | } |
6221 | ||
f13c2ef3 DV |
6222 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6223 | { | |
6224 | struct drm_device *dev = crtc->base.dev; | |
6225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6226 | ||
6e3c9717 ACO |
6227 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6228 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6229 | } |
6230 | ||
0b8765c6 | 6231 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6232 | { |
6233 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6234 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6236 | struct intel_encoder *encoder; |
79e53945 | 6237 | int pipe = intel_crtc->pipe; |
79e53945 | 6238 | |
53d9f4e9 | 6239 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6240 | return; |
6241 | ||
f13c2ef3 DV |
6242 | i9xx_set_pll_dividers(intel_crtc); |
6243 | ||
6e3c9717 | 6244 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6245 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6246 | |
6247 | intel_set_pipe_timings(intel_crtc); | |
6248 | ||
5b18e57c DV |
6249 | i9xx_set_pipeconf(intel_crtc); |
6250 | ||
f7abfe8b | 6251 | intel_crtc->active = true; |
6b383a7f | 6252 | |
4a3436e8 | 6253 | if (!IS_GEN2(dev)) |
a72e4c9f | 6254 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6255 | |
9d6d9f19 MK |
6256 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6257 | if (encoder->pre_enable) | |
6258 | encoder->pre_enable(encoder); | |
6259 | ||
f6736a1a DV |
6260 | i9xx_enable_pll(intel_crtc); |
6261 | ||
2dd24552 JB |
6262 | i9xx_pfit_enable(intel_crtc); |
6263 | ||
63cbb074 VS |
6264 | intel_crtc_load_lut(crtc); |
6265 | ||
f37fcc2a | 6266 | intel_update_watermarks(crtc); |
e1fdc473 | 6267 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6268 | |
4b3a9526 VS |
6269 | assert_vblank_disabled(crtc); |
6270 | drm_crtc_vblank_on(crtc); | |
6271 | ||
f9b61ff6 DV |
6272 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6273 | encoder->enable(encoder); | |
0b8765c6 | 6274 | } |
79e53945 | 6275 | |
87476d63 DV |
6276 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6277 | { | |
6278 | struct drm_device *dev = crtc->base.dev; | |
6279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6280 | |
6e3c9717 | 6281 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6282 | return; |
87476d63 | 6283 | |
328d8e82 | 6284 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6285 | |
328d8e82 DV |
6286 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6287 | I915_READ(PFIT_CONTROL)); | |
6288 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6289 | } |
6290 | ||
0b8765c6 JB |
6291 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6292 | { | |
6293 | struct drm_device *dev = crtc->dev; | |
6294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6296 | struct intel_encoder *encoder; |
0b8765c6 | 6297 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6298 | |
6304cd91 VS |
6299 | /* |
6300 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6301 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6302 | * We also need to wait on all gmch platforms because of the |
6303 | * self-refresh mode constraint explained above. | |
6304cd91 | 6304 | */ |
564ed191 | 6305 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6306 | |
4b3a9526 VS |
6307 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6308 | encoder->disable(encoder); | |
6309 | ||
f9b61ff6 DV |
6310 | drm_crtc_vblank_off(crtc); |
6311 | assert_vblank_disabled(crtc); | |
6312 | ||
575f7ab7 | 6313 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6314 | |
87476d63 | 6315 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6316 | |
89b667f8 JB |
6317 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6318 | if (encoder->post_disable) | |
6319 | encoder->post_disable(encoder); | |
6320 | ||
a65347ba | 6321 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6322 | if (IS_CHERRYVIEW(dev)) |
6323 | chv_disable_pll(dev_priv, pipe); | |
6324 | else if (IS_VALLEYVIEW(dev)) | |
6325 | vlv_disable_pll(dev_priv, pipe); | |
6326 | else | |
1c4e0274 | 6327 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6328 | } |
0b8765c6 | 6329 | |
d6db995f VS |
6330 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6331 | if (encoder->post_pll_disable) | |
6332 | encoder->post_pll_disable(encoder); | |
6333 | ||
4a3436e8 | 6334 | if (!IS_GEN2(dev)) |
a72e4c9f | 6335 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6336 | } |
6337 | ||
b17d48e2 ML |
6338 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6339 | { | |
6340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6341 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6342 | enum intel_display_power_domain domain; | |
6343 | unsigned long domains; | |
6344 | ||
6345 | if (!intel_crtc->active) | |
6346 | return; | |
6347 | ||
a539205a | 6348 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6349 | WARN_ON(intel_crtc->unpin_work); |
6350 | ||
a539205a | 6351 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6352 | |
6353 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6354 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6355 | } |
6356 | ||
b17d48e2 | 6357 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6358 | intel_crtc->active = false; |
58f9c0bc | 6359 | intel_fbc_disable(intel_crtc); |
37d9078b | 6360 | intel_update_watermarks(crtc); |
1f7457b1 | 6361 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6362 | |
6363 | domains = intel_crtc->enabled_power_domains; | |
6364 | for_each_power_domain(domain, domains) | |
6365 | intel_display_power_put(dev_priv, domain); | |
6366 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6367 | |
6368 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6369 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6370 | } |
6371 | ||
6b72d486 ML |
6372 | /* |
6373 | * turn all crtc's off, but do not adjust state | |
6374 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6375 | */ | |
70e0bd74 | 6376 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6377 | { |
e2c8b870 | 6378 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6379 | struct drm_atomic_state *state; |
e2c8b870 | 6380 | int ret; |
70e0bd74 | 6381 | |
e2c8b870 ML |
6382 | state = drm_atomic_helper_suspend(dev); |
6383 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6384 | if (ret) |
6385 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6386 | else |
6387 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6388 | return ret; |
ee7b9f93 JB |
6389 | } |
6390 | ||
ea5b213a | 6391 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6392 | { |
4ef69c7a | 6393 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6394 | |
ea5b213a CW |
6395 | drm_encoder_cleanup(encoder); |
6396 | kfree(intel_encoder); | |
7e7d76c3 JB |
6397 | } |
6398 | ||
0a91ca29 DV |
6399 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6400 | * internal consistency). */ | |
b980514c | 6401 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6402 | { |
35dd3c64 ML |
6403 | struct drm_crtc *crtc = connector->base.state->crtc; |
6404 | ||
6405 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6406 | connector->base.base.id, | |
6407 | connector->base.name); | |
6408 | ||
0a91ca29 | 6409 | if (connector->get_hw_state(connector)) { |
e85376cb | 6410 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6411 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6412 | |
35dd3c64 ML |
6413 | I915_STATE_WARN(!crtc, |
6414 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6415 | |
35dd3c64 ML |
6416 | if (!crtc) |
6417 | return; | |
6418 | ||
6419 | I915_STATE_WARN(!crtc->state->active, | |
6420 | "connector is active, but attached crtc isn't\n"); | |
6421 | ||
e85376cb | 6422 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6423 | return; |
6424 | ||
e85376cb | 6425 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6426 | "atomic encoder doesn't match attached encoder\n"); |
6427 | ||
e85376cb | 6428 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6429 | "attached encoder crtc differs from connector crtc\n"); |
6430 | } else { | |
4d688a2a ML |
6431 | I915_STATE_WARN(crtc && crtc->state->active, |
6432 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6433 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6434 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6435 | } |
79e53945 JB |
6436 | } |
6437 | ||
08d9bc92 ACO |
6438 | int intel_connector_init(struct intel_connector *connector) |
6439 | { | |
5350a031 | 6440 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6441 | |
5350a031 | 6442 | if (!connector->base.state) |
08d9bc92 ACO |
6443 | return -ENOMEM; |
6444 | ||
08d9bc92 ACO |
6445 | return 0; |
6446 | } | |
6447 | ||
6448 | struct intel_connector *intel_connector_alloc(void) | |
6449 | { | |
6450 | struct intel_connector *connector; | |
6451 | ||
6452 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6453 | if (!connector) | |
6454 | return NULL; | |
6455 | ||
6456 | if (intel_connector_init(connector) < 0) { | |
6457 | kfree(connector); | |
6458 | return NULL; | |
6459 | } | |
6460 | ||
6461 | return connector; | |
6462 | } | |
6463 | ||
f0947c37 DV |
6464 | /* Simple connector->get_hw_state implementation for encoders that support only |
6465 | * one connector and no cloning and hence the encoder state determines the state | |
6466 | * of the connector. */ | |
6467 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6468 | { |
24929352 | 6469 | enum pipe pipe = 0; |
f0947c37 | 6470 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6471 | |
f0947c37 | 6472 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6473 | } |
6474 | ||
6d293983 | 6475 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6476 | { |
6d293983 ACO |
6477 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6478 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6479 | |
6480 | return 0; | |
6481 | } | |
6482 | ||
6d293983 | 6483 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6484 | struct intel_crtc_state *pipe_config) |
1857e1da | 6485 | { |
6d293983 ACO |
6486 | struct drm_atomic_state *state = pipe_config->base.state; |
6487 | struct intel_crtc *other_crtc; | |
6488 | struct intel_crtc_state *other_crtc_state; | |
6489 | ||
1857e1da DV |
6490 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6491 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6492 | if (pipe_config->fdi_lanes > 4) { | |
6493 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6494 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6495 | return -EINVAL; |
1857e1da DV |
6496 | } |
6497 | ||
bafb6553 | 6498 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6499 | if (pipe_config->fdi_lanes > 2) { |
6500 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6501 | pipe_config->fdi_lanes); | |
6d293983 | 6502 | return -EINVAL; |
1857e1da | 6503 | } else { |
6d293983 | 6504 | return 0; |
1857e1da DV |
6505 | } |
6506 | } | |
6507 | ||
6508 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6509 | return 0; |
1857e1da DV |
6510 | |
6511 | /* Ivybridge 3 pipe is really complicated */ | |
6512 | switch (pipe) { | |
6513 | case PIPE_A: | |
6d293983 | 6514 | return 0; |
1857e1da | 6515 | case PIPE_B: |
6d293983 ACO |
6516 | if (pipe_config->fdi_lanes <= 2) |
6517 | return 0; | |
6518 | ||
6519 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6520 | other_crtc_state = | |
6521 | intel_atomic_get_crtc_state(state, other_crtc); | |
6522 | if (IS_ERR(other_crtc_state)) | |
6523 | return PTR_ERR(other_crtc_state); | |
6524 | ||
6525 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6526 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6527 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6528 | return -EINVAL; |
1857e1da | 6529 | } |
6d293983 | 6530 | return 0; |
1857e1da | 6531 | case PIPE_C: |
251cc67c VS |
6532 | if (pipe_config->fdi_lanes > 2) { |
6533 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6534 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6535 | return -EINVAL; |
251cc67c | 6536 | } |
6d293983 ACO |
6537 | |
6538 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6539 | other_crtc_state = | |
6540 | intel_atomic_get_crtc_state(state, other_crtc); | |
6541 | if (IS_ERR(other_crtc_state)) | |
6542 | return PTR_ERR(other_crtc_state); | |
6543 | ||
6544 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6545 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6546 | return -EINVAL; |
1857e1da | 6547 | } |
6d293983 | 6548 | return 0; |
1857e1da DV |
6549 | default: |
6550 | BUG(); | |
6551 | } | |
6552 | } | |
6553 | ||
e29c22c0 DV |
6554 | #define RETRY 1 |
6555 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6556 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6557 | { |
1857e1da | 6558 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6559 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6560 | int lane, link_bw, fdi_dotclock, ret; |
6561 | bool needs_recompute = false; | |
877d48d5 | 6562 | |
e29c22c0 | 6563 | retry: |
877d48d5 DV |
6564 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6565 | * each output octet as 10 bits. The actual frequency | |
6566 | * is stored as a divider into a 100MHz clock, and the | |
6567 | * mode pixel clock is stored in units of 1KHz. | |
6568 | * Hence the bw of each lane in terms of the mode signal | |
6569 | * is: | |
6570 | */ | |
6571 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6572 | ||
241bfc38 | 6573 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6574 | |
2bd89a07 | 6575 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6576 | pipe_config->pipe_bpp); |
6577 | ||
6578 | pipe_config->fdi_lanes = lane; | |
6579 | ||
2bd89a07 | 6580 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6581 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6582 | |
6d293983 ACO |
6583 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6584 | intel_crtc->pipe, pipe_config); | |
6585 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6586 | pipe_config->pipe_bpp -= 2*3; |
6587 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6588 | pipe_config->pipe_bpp); | |
6589 | needs_recompute = true; | |
6590 | pipe_config->bw_constrained = true; | |
6591 | ||
6592 | goto retry; | |
6593 | } | |
6594 | ||
6595 | if (needs_recompute) | |
6596 | return RETRY; | |
6597 | ||
6d293983 | 6598 | return ret; |
877d48d5 DV |
6599 | } |
6600 | ||
8cfb3407 VS |
6601 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6602 | struct intel_crtc_state *pipe_config) | |
6603 | { | |
6604 | if (pipe_config->pipe_bpp > 24) | |
6605 | return false; | |
6606 | ||
6607 | /* HSW can handle pixel rate up to cdclk? */ | |
6608 | if (IS_HASWELL(dev_priv->dev)) | |
6609 | return true; | |
6610 | ||
6611 | /* | |
b432e5cf VS |
6612 | * We compare against max which means we must take |
6613 | * the increased cdclk requirement into account when | |
6614 | * calculating the new cdclk. | |
6615 | * | |
6616 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6617 | */ |
6618 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6619 | dev_priv->max_cdclk_freq * 95 / 100; | |
6620 | } | |
6621 | ||
42db64ef | 6622 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6623 | struct intel_crtc_state *pipe_config) |
42db64ef | 6624 | { |
8cfb3407 VS |
6625 | struct drm_device *dev = crtc->base.dev; |
6626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6627 | ||
d330a953 | 6628 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6629 | hsw_crtc_supports_ips(crtc) && |
6630 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6631 | } |
6632 | ||
39acb4aa VS |
6633 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6634 | { | |
6635 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6636 | ||
6637 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6638 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6639 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6640 | } | |
6641 | ||
a43f6e0f | 6642 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6643 | struct intel_crtc_state *pipe_config) |
79e53945 | 6644 | { |
a43f6e0f | 6645 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6646 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6647 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6648 | |
ad3a4479 | 6649 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6650 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6651 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6652 | |
6653 | /* | |
39acb4aa | 6654 | * Enable double wide mode when the dot clock |
cf532bb2 | 6655 | * is > 90% of the (display) core speed. |
cf532bb2 | 6656 | */ |
39acb4aa VS |
6657 | if (intel_crtc_supports_double_wide(crtc) && |
6658 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6659 | clock_limit *= 2; |
cf532bb2 | 6660 | pipe_config->double_wide = true; |
ad3a4479 VS |
6661 | } |
6662 | ||
39acb4aa VS |
6663 | if (adjusted_mode->crtc_clock > clock_limit) { |
6664 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6665 | adjusted_mode->crtc_clock, clock_limit, | |
6666 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6667 | return -EINVAL; |
39acb4aa | 6668 | } |
2c07245f | 6669 | } |
89749350 | 6670 | |
1d1d0e27 VS |
6671 | /* |
6672 | * Pipe horizontal size must be even in: | |
6673 | * - DVO ganged mode | |
6674 | * - LVDS dual channel mode | |
6675 | * - Double wide pipe | |
6676 | */ | |
a93e255f | 6677 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6678 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6679 | pipe_config->pipe_src_w &= ~1; | |
6680 | ||
8693a824 DL |
6681 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6682 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6683 | */ |
6684 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6685 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6686 | return -EINVAL; |
44f46b42 | 6687 | |
f5adf94e | 6688 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6689 | hsw_compute_ips_config(crtc, pipe_config); |
6690 | ||
877d48d5 | 6691 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6692 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6693 | |
cf5a15be | 6694 | return 0; |
79e53945 JB |
6695 | } |
6696 | ||
1652d19e VS |
6697 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6698 | { | |
6699 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6700 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6701 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6702 | uint32_t linkrate; | |
6703 | ||
414355a7 | 6704 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6705 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6706 | |
6707 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6708 | return 540000; | |
6709 | ||
6710 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6711 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6712 | |
71cd8423 DL |
6713 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6714 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6715 | /* vco 8640 */ |
6716 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6717 | case CDCLK_FREQ_450_432: | |
6718 | return 432000; | |
6719 | case CDCLK_FREQ_337_308: | |
6720 | return 308570; | |
6721 | case CDCLK_FREQ_675_617: | |
6722 | return 617140; | |
6723 | default: | |
6724 | WARN(1, "Unknown cd freq selection\n"); | |
6725 | } | |
6726 | } else { | |
6727 | /* vco 8100 */ | |
6728 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6729 | case CDCLK_FREQ_450_432: | |
6730 | return 450000; | |
6731 | case CDCLK_FREQ_337_308: | |
6732 | return 337500; | |
6733 | case CDCLK_FREQ_675_617: | |
6734 | return 675000; | |
6735 | default: | |
6736 | WARN(1, "Unknown cd freq selection\n"); | |
6737 | } | |
6738 | } | |
6739 | ||
6740 | /* error case, do as if DPLL0 isn't enabled */ | |
6741 | return 24000; | |
6742 | } | |
6743 | ||
acd3f3d3 BP |
6744 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6745 | { | |
6746 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6747 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6748 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6749 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6750 | int cdclk; | |
6751 | ||
6752 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6753 | return 19200; | |
6754 | ||
6755 | cdclk = 19200 * pll_ratio / 2; | |
6756 | ||
6757 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6758 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6759 | return cdclk; /* 576MHz or 624MHz */ | |
6760 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6761 | return cdclk * 2 / 3; /* 384MHz */ | |
6762 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6763 | return cdclk / 2; /* 288MHz */ | |
6764 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6765 | return cdclk / 4; /* 144MHz */ | |
6766 | } | |
6767 | ||
6768 | /* error case, do as if DE PLL isn't enabled */ | |
6769 | return 19200; | |
6770 | } | |
6771 | ||
1652d19e VS |
6772 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6773 | { | |
6774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6775 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6776 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6777 | ||
6778 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6779 | return 800000; | |
6780 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6781 | return 450000; | |
6782 | else if (freq == LCPLL_CLK_FREQ_450) | |
6783 | return 450000; | |
6784 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6785 | return 540000; | |
6786 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6787 | return 337500; | |
6788 | else | |
6789 | return 675000; | |
6790 | } | |
6791 | ||
6792 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6793 | { | |
6794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6795 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6796 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6797 | ||
6798 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6799 | return 800000; | |
6800 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6801 | return 450000; | |
6802 | else if (freq == LCPLL_CLK_FREQ_450) | |
6803 | return 450000; | |
6804 | else if (IS_HSW_ULT(dev)) | |
6805 | return 337500; | |
6806 | else | |
6807 | return 540000; | |
79e53945 JB |
6808 | } |
6809 | ||
25eb05fc JB |
6810 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6811 | { | |
bfa7df01 VS |
6812 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6813 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6814 | } |
6815 | ||
b37a6434 VS |
6816 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6817 | { | |
6818 | return 450000; | |
6819 | } | |
6820 | ||
e70236a8 JB |
6821 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6822 | { | |
6823 | return 400000; | |
6824 | } | |
79e53945 | 6825 | |
e70236a8 | 6826 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6827 | { |
e907f170 | 6828 | return 333333; |
e70236a8 | 6829 | } |
79e53945 | 6830 | |
e70236a8 JB |
6831 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6832 | { | |
6833 | return 200000; | |
6834 | } | |
79e53945 | 6835 | |
257a7ffc DV |
6836 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6837 | { | |
6838 | u16 gcfgc = 0; | |
6839 | ||
6840 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6841 | ||
6842 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6843 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6844 | return 266667; |
257a7ffc | 6845 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6846 | return 333333; |
257a7ffc | 6847 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6848 | return 444444; |
257a7ffc DV |
6849 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6850 | return 200000; | |
6851 | default: | |
6852 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6853 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6854 | return 133333; |
257a7ffc | 6855 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6856 | return 166667; |
257a7ffc DV |
6857 | } |
6858 | } | |
6859 | ||
e70236a8 JB |
6860 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6861 | { | |
6862 | u16 gcfgc = 0; | |
79e53945 | 6863 | |
e70236a8 JB |
6864 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6865 | ||
6866 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6867 | return 133333; |
e70236a8 JB |
6868 | else { |
6869 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6870 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6871 | return 333333; |
e70236a8 JB |
6872 | default: |
6873 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6874 | return 190000; | |
79e53945 | 6875 | } |
e70236a8 JB |
6876 | } |
6877 | } | |
6878 | ||
6879 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6880 | { | |
e907f170 | 6881 | return 266667; |
e70236a8 JB |
6882 | } |
6883 | ||
1b1d2716 | 6884 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6885 | { |
6886 | u16 hpllcc = 0; | |
1b1d2716 | 6887 | |
65cd2b3f VS |
6888 | /* |
6889 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6890 | * encoding is different :( | |
6891 | * FIXME is this the right way to detect 852GM/852GMV? | |
6892 | */ | |
6893 | if (dev->pdev->revision == 0x1) | |
6894 | return 133333; | |
6895 | ||
1b1d2716 VS |
6896 | pci_bus_read_config_word(dev->pdev->bus, |
6897 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6898 | ||
e70236a8 JB |
6899 | /* Assume that the hardware is in the high speed state. This |
6900 | * should be the default. | |
6901 | */ | |
6902 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6903 | case GC_CLOCK_133_200: | |
1b1d2716 | 6904 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6905 | case GC_CLOCK_100_200: |
6906 | return 200000; | |
6907 | case GC_CLOCK_166_250: | |
6908 | return 250000; | |
6909 | case GC_CLOCK_100_133: | |
e907f170 | 6910 | return 133333; |
1b1d2716 VS |
6911 | case GC_CLOCK_133_266: |
6912 | case GC_CLOCK_133_266_2: | |
6913 | case GC_CLOCK_166_266: | |
6914 | return 266667; | |
e70236a8 | 6915 | } |
79e53945 | 6916 | |
e70236a8 JB |
6917 | /* Shouldn't happen */ |
6918 | return 0; | |
6919 | } | |
79e53945 | 6920 | |
e70236a8 JB |
6921 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6922 | { | |
e907f170 | 6923 | return 133333; |
79e53945 JB |
6924 | } |
6925 | ||
34edce2f VS |
6926 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6927 | { | |
6928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6929 | static const unsigned int blb_vco[8] = { | |
6930 | [0] = 3200000, | |
6931 | [1] = 4000000, | |
6932 | [2] = 5333333, | |
6933 | [3] = 4800000, | |
6934 | [4] = 6400000, | |
6935 | }; | |
6936 | static const unsigned int pnv_vco[8] = { | |
6937 | [0] = 3200000, | |
6938 | [1] = 4000000, | |
6939 | [2] = 5333333, | |
6940 | [3] = 4800000, | |
6941 | [4] = 2666667, | |
6942 | }; | |
6943 | static const unsigned int cl_vco[8] = { | |
6944 | [0] = 3200000, | |
6945 | [1] = 4000000, | |
6946 | [2] = 5333333, | |
6947 | [3] = 6400000, | |
6948 | [4] = 3333333, | |
6949 | [5] = 3566667, | |
6950 | [6] = 4266667, | |
6951 | }; | |
6952 | static const unsigned int elk_vco[8] = { | |
6953 | [0] = 3200000, | |
6954 | [1] = 4000000, | |
6955 | [2] = 5333333, | |
6956 | [3] = 4800000, | |
6957 | }; | |
6958 | static const unsigned int ctg_vco[8] = { | |
6959 | [0] = 3200000, | |
6960 | [1] = 4000000, | |
6961 | [2] = 5333333, | |
6962 | [3] = 6400000, | |
6963 | [4] = 2666667, | |
6964 | [5] = 4266667, | |
6965 | }; | |
6966 | const unsigned int *vco_table; | |
6967 | unsigned int vco; | |
6968 | uint8_t tmp = 0; | |
6969 | ||
6970 | /* FIXME other chipsets? */ | |
6971 | if (IS_GM45(dev)) | |
6972 | vco_table = ctg_vco; | |
6973 | else if (IS_G4X(dev)) | |
6974 | vco_table = elk_vco; | |
6975 | else if (IS_CRESTLINE(dev)) | |
6976 | vco_table = cl_vco; | |
6977 | else if (IS_PINEVIEW(dev)) | |
6978 | vco_table = pnv_vco; | |
6979 | else if (IS_G33(dev)) | |
6980 | vco_table = blb_vco; | |
6981 | else | |
6982 | return 0; | |
6983 | ||
6984 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6985 | ||
6986 | vco = vco_table[tmp & 0x7]; | |
6987 | if (vco == 0) | |
6988 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6989 | else | |
6990 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6991 | ||
6992 | return vco; | |
6993 | } | |
6994 | ||
6995 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6996 | { | |
6997 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6998 | uint16_t tmp = 0; | |
6999 | ||
7000 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7001 | ||
7002 | cdclk_sel = (tmp >> 12) & 0x1; | |
7003 | ||
7004 | switch (vco) { | |
7005 | case 2666667: | |
7006 | case 4000000: | |
7007 | case 5333333: | |
7008 | return cdclk_sel ? 333333 : 222222; | |
7009 | case 3200000: | |
7010 | return cdclk_sel ? 320000 : 228571; | |
7011 | default: | |
7012 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7013 | return 222222; | |
7014 | } | |
7015 | } | |
7016 | ||
7017 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7018 | { | |
7019 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7020 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7021 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7022 | const uint8_t *div_table; | |
7023 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7024 | uint16_t tmp = 0; | |
7025 | ||
7026 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7027 | ||
7028 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7029 | ||
7030 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7031 | goto fail; | |
7032 | ||
7033 | switch (vco) { | |
7034 | case 3200000: | |
7035 | div_table = div_3200; | |
7036 | break; | |
7037 | case 4000000: | |
7038 | div_table = div_4000; | |
7039 | break; | |
7040 | case 5333333: | |
7041 | div_table = div_5333; | |
7042 | break; | |
7043 | default: | |
7044 | goto fail; | |
7045 | } | |
7046 | ||
7047 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7048 | ||
caf4e252 | 7049 | fail: |
34edce2f VS |
7050 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7051 | return 200000; | |
7052 | } | |
7053 | ||
7054 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7055 | { | |
7056 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7057 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7058 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7059 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7060 | const uint8_t *div_table; | |
7061 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7062 | uint16_t tmp = 0; | |
7063 | ||
7064 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7065 | ||
7066 | cdclk_sel = (tmp >> 4) & 0x7; | |
7067 | ||
7068 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7069 | goto fail; | |
7070 | ||
7071 | switch (vco) { | |
7072 | case 3200000: | |
7073 | div_table = div_3200; | |
7074 | break; | |
7075 | case 4000000: | |
7076 | div_table = div_4000; | |
7077 | break; | |
7078 | case 4800000: | |
7079 | div_table = div_4800; | |
7080 | break; | |
7081 | case 5333333: | |
7082 | div_table = div_5333; | |
7083 | break; | |
7084 | default: | |
7085 | goto fail; | |
7086 | } | |
7087 | ||
7088 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7089 | ||
caf4e252 | 7090 | fail: |
34edce2f VS |
7091 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7092 | return 190476; | |
7093 | } | |
7094 | ||
2c07245f | 7095 | static void |
a65851af | 7096 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7097 | { |
a65851af VS |
7098 | while (*num > DATA_LINK_M_N_MASK || |
7099 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7100 | *num >>= 1; |
7101 | *den >>= 1; | |
7102 | } | |
7103 | } | |
7104 | ||
a65851af VS |
7105 | static void compute_m_n(unsigned int m, unsigned int n, |
7106 | uint32_t *ret_m, uint32_t *ret_n) | |
7107 | { | |
7108 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7109 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7110 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7111 | } | |
7112 | ||
e69d0bc1 DV |
7113 | void |
7114 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7115 | int pixel_clock, int link_clock, | |
7116 | struct intel_link_m_n *m_n) | |
2c07245f | 7117 | { |
e69d0bc1 | 7118 | m_n->tu = 64; |
a65851af VS |
7119 | |
7120 | compute_m_n(bits_per_pixel * pixel_clock, | |
7121 | link_clock * nlanes * 8, | |
7122 | &m_n->gmch_m, &m_n->gmch_n); | |
7123 | ||
7124 | compute_m_n(pixel_clock, link_clock, | |
7125 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7126 | } |
7127 | ||
a7615030 CW |
7128 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7129 | { | |
d330a953 JN |
7130 | if (i915.panel_use_ssc >= 0) |
7131 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7132 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7133 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7134 | } |
7135 | ||
a93e255f ACO |
7136 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7137 | int num_connectors) | |
c65d77d8 | 7138 | { |
a93e255f | 7139 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7140 | struct drm_i915_private *dev_priv = dev->dev_private; |
7141 | int refclk; | |
7142 | ||
a93e255f ACO |
7143 | WARN_ON(!crtc_state->base.state); |
7144 | ||
666a4537 | 7145 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7146 | refclk = 100000; |
a93e255f | 7147 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7148 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7149 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7150 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7151 | } else if (!IS_GEN2(dev)) { |
7152 | refclk = 96000; | |
7153 | } else { | |
7154 | refclk = 48000; | |
7155 | } | |
7156 | ||
7157 | return refclk; | |
7158 | } | |
7159 | ||
7429e9d4 | 7160 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7161 | { |
7df00d7a | 7162 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7163 | } |
f47709a9 | 7164 | |
7429e9d4 DV |
7165 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7166 | { | |
7167 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7168 | } |
7169 | ||
f47709a9 | 7170 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7171 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7172 | intel_clock_t *reduced_clock) |
7173 | { | |
f47709a9 | 7174 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7175 | u32 fp, fp2 = 0; |
7176 | ||
7177 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7178 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7179 | if (reduced_clock) |
7429e9d4 | 7180 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7181 | } else { |
190f68c5 | 7182 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7183 | if (reduced_clock) |
7429e9d4 | 7184 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7185 | } |
7186 | ||
190f68c5 | 7187 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7188 | |
f47709a9 | 7189 | crtc->lowfreq_avail = false; |
a93e255f | 7190 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7191 | reduced_clock) { |
190f68c5 | 7192 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7193 | crtc->lowfreq_avail = true; |
a7516a05 | 7194 | } else { |
190f68c5 | 7195 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7196 | } |
7197 | } | |
7198 | ||
5e69f97f CML |
7199 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7200 | pipe) | |
89b667f8 JB |
7201 | { |
7202 | u32 reg_val; | |
7203 | ||
7204 | /* | |
7205 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7206 | * and set it to a reasonable value instead. | |
7207 | */ | |
ab3c759a | 7208 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7209 | reg_val &= 0xffffff00; |
7210 | reg_val |= 0x00000030; | |
ab3c759a | 7211 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7212 | |
ab3c759a | 7213 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7214 | reg_val &= 0x8cffffff; |
7215 | reg_val = 0x8c000000; | |
ab3c759a | 7216 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7217 | |
ab3c759a | 7218 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7219 | reg_val &= 0xffffff00; |
ab3c759a | 7220 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7221 | |
ab3c759a | 7222 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7223 | reg_val &= 0x00ffffff; |
7224 | reg_val |= 0xb0000000; | |
ab3c759a | 7225 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7226 | } |
7227 | ||
b551842d DV |
7228 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7229 | struct intel_link_m_n *m_n) | |
7230 | { | |
7231 | struct drm_device *dev = crtc->base.dev; | |
7232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7233 | int pipe = crtc->pipe; | |
7234 | ||
e3b95f1e DV |
7235 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7236 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7237 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7238 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7239 | } |
7240 | ||
7241 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7242 | struct intel_link_m_n *m_n, |
7243 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7244 | { |
7245 | struct drm_device *dev = crtc->base.dev; | |
7246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7247 | int pipe = crtc->pipe; | |
6e3c9717 | 7248 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7249 | |
7250 | if (INTEL_INFO(dev)->gen >= 5) { | |
7251 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7252 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7253 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7254 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7255 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7256 | * for gen < 8) and if DRRS is supported (to make sure the | |
7257 | * registers are not unnecessarily accessed). | |
7258 | */ | |
44395bfe | 7259 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7260 | crtc->config->has_drrs) { |
f769cd24 VK |
7261 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7262 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7263 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7264 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7265 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7266 | } | |
b551842d | 7267 | } else { |
e3b95f1e DV |
7268 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7269 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7270 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7271 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7272 | } |
7273 | } | |
7274 | ||
fe3cd48d | 7275 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7276 | { |
fe3cd48d R |
7277 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7278 | ||
7279 | if (m_n == M1_N1) { | |
7280 | dp_m_n = &crtc->config->dp_m_n; | |
7281 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7282 | } else if (m_n == M2_N2) { | |
7283 | ||
7284 | /* | |
7285 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7286 | * needs to be programmed into M1_N1. | |
7287 | */ | |
7288 | dp_m_n = &crtc->config->dp_m2_n2; | |
7289 | } else { | |
7290 | DRM_ERROR("Unsupported divider value\n"); | |
7291 | return; | |
7292 | } | |
7293 | ||
6e3c9717 ACO |
7294 | if (crtc->config->has_pch_encoder) |
7295 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7296 | else |
fe3cd48d | 7297 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7298 | } |
7299 | ||
251ac862 DV |
7300 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7301 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7302 | { |
7303 | u32 dpll, dpll_md; | |
7304 | ||
7305 | /* | |
7306 | * Enable DPIO clock input. We should never disable the reference | |
7307 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7308 | * on it. | |
7309 | */ | |
60bfe44f VS |
7310 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7311 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7312 | /* We should never disable this, set it here for state tracking */ |
7313 | if (crtc->pipe == PIPE_B) | |
7314 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7315 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7316 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7317 | |
d288f65f | 7318 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7319 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7320 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7321 | } |
7322 | ||
d288f65f | 7323 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7324 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7325 | { |
f47709a9 | 7326 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7327 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7328 | int pipe = crtc->pipe; |
bdd4b6a6 | 7329 | u32 mdiv; |
a0c4da24 | 7330 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7331 | u32 coreclk, reg_val; |
a0c4da24 | 7332 | |
a580516d | 7333 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7334 | |
d288f65f VS |
7335 | bestn = pipe_config->dpll.n; |
7336 | bestm1 = pipe_config->dpll.m1; | |
7337 | bestm2 = pipe_config->dpll.m2; | |
7338 | bestp1 = pipe_config->dpll.p1; | |
7339 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7340 | |
89b667f8 JB |
7341 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7342 | ||
7343 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7344 | if (pipe == PIPE_B) |
5e69f97f | 7345 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7346 | |
7347 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7348 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7349 | |
7350 | /* Disable target IRef on PLL */ | |
ab3c759a | 7351 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7352 | reg_val &= 0x00ffffff; |
ab3c759a | 7353 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7354 | |
7355 | /* Disable fast lock */ | |
ab3c759a | 7356 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7357 | |
7358 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7359 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7360 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7361 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7362 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7363 | |
7364 | /* | |
7365 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7366 | * but we don't support that). | |
7367 | * Note: don't use the DAC post divider as it seems unstable. | |
7368 | */ | |
7369 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7370 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7371 | |
a0c4da24 | 7372 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7373 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7374 | |
89b667f8 | 7375 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7376 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7377 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7378 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7379 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7380 | 0x009f0003); |
89b667f8 | 7381 | else |
ab3c759a | 7382 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7383 | 0x00d0000f); |
7384 | ||
681a8504 | 7385 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7386 | /* Use SSC source */ |
bdd4b6a6 | 7387 | if (pipe == PIPE_A) |
ab3c759a | 7388 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7389 | 0x0df40000); |
7390 | else | |
ab3c759a | 7391 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7392 | 0x0df70000); |
7393 | } else { /* HDMI or VGA */ | |
7394 | /* Use bend source */ | |
bdd4b6a6 | 7395 | if (pipe == PIPE_A) |
ab3c759a | 7396 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7397 | 0x0df70000); |
7398 | else | |
ab3c759a | 7399 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7400 | 0x0df40000); |
7401 | } | |
a0c4da24 | 7402 | |
ab3c759a | 7403 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7404 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7405 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7406 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7407 | coreclk |= 0x01000000; |
ab3c759a | 7408 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7409 | |
ab3c759a | 7410 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7411 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7412 | } |
7413 | ||
251ac862 DV |
7414 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7415 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7416 | { |
60bfe44f VS |
7417 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7418 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7419 | DPLL_VCO_ENABLE; |
7420 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7421 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7422 | |
d288f65f VS |
7423 | pipe_config->dpll_hw_state.dpll_md = |
7424 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7425 | } |
7426 | ||
d288f65f | 7427 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7428 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7429 | { |
7430 | struct drm_device *dev = crtc->base.dev; | |
7431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7432 | int pipe = crtc->pipe; | |
f0f59a00 | 7433 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7434 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7435 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7436 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7437 | u32 dpio_val; |
9cbe40c1 | 7438 | int vco; |
9d556c99 | 7439 | |
d288f65f VS |
7440 | bestn = pipe_config->dpll.n; |
7441 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7442 | bestm1 = pipe_config->dpll.m1; | |
7443 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7444 | bestp1 = pipe_config->dpll.p1; | |
7445 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7446 | vco = pipe_config->dpll.vco; |
a945ce7e | 7447 | dpio_val = 0; |
9cbe40c1 | 7448 | loopfilter = 0; |
9d556c99 CML |
7449 | |
7450 | /* | |
7451 | * Enable Refclk and SSC | |
7452 | */ | |
a11b0703 | 7453 | I915_WRITE(dpll_reg, |
d288f65f | 7454 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7455 | |
a580516d | 7456 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7457 | |
9d556c99 CML |
7458 | /* p1 and p2 divider */ |
7459 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7460 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7461 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7462 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7463 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7464 | ||
7465 | /* Feedback post-divider - m2 */ | |
7466 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7467 | ||
7468 | /* Feedback refclk divider - n and m1 */ | |
7469 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7470 | DPIO_CHV_M1_DIV_BY_2 | | |
7471 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7472 | ||
7473 | /* M2 fraction division */ | |
25a25dfc | 7474 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7475 | |
7476 | /* M2 fraction division enable */ | |
a945ce7e VP |
7477 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7478 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7479 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7480 | if (bestm2_frac) | |
7481 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7482 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7483 | |
de3a0fde VP |
7484 | /* Program digital lock detect threshold */ |
7485 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7486 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7487 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7488 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7489 | if (!bestm2_frac) | |
7490 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7491 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7492 | ||
9d556c99 | 7493 | /* Loop filter */ |
9cbe40c1 VP |
7494 | if (vco == 5400000) { |
7495 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7496 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7497 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7498 | tribuf_calcntr = 0x9; | |
7499 | } else if (vco <= 6200000) { | |
7500 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7501 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7502 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7503 | tribuf_calcntr = 0x9; | |
7504 | } else if (vco <= 6480000) { | |
7505 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7506 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7507 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7508 | tribuf_calcntr = 0x8; | |
7509 | } else { | |
7510 | /* Not supported. Apply the same limits as in the max case */ | |
7511 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7512 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7513 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7514 | tribuf_calcntr = 0; | |
7515 | } | |
9d556c99 CML |
7516 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7517 | ||
968040b2 | 7518 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7519 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7520 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7521 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7522 | ||
9d556c99 CML |
7523 | /* AFC Recal */ |
7524 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7525 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7526 | DPIO_AFC_RECAL); | |
7527 | ||
a580516d | 7528 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7529 | } |
7530 | ||
d288f65f VS |
7531 | /** |
7532 | * vlv_force_pll_on - forcibly enable just the PLL | |
7533 | * @dev_priv: i915 private structure | |
7534 | * @pipe: pipe PLL to enable | |
7535 | * @dpll: PLL configuration | |
7536 | * | |
7537 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7538 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7539 | * be enabled. | |
7540 | */ | |
3f36b937 TU |
7541 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7542 | const struct dpll *dpll) | |
d288f65f VS |
7543 | { |
7544 | struct intel_crtc *crtc = | |
7545 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7546 | struct intel_crtc_state *pipe_config; |
7547 | ||
7548 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7549 | if (!pipe_config) | |
7550 | return -ENOMEM; | |
7551 | ||
7552 | pipe_config->base.crtc = &crtc->base; | |
7553 | pipe_config->pixel_multiplier = 1; | |
7554 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7555 | |
7556 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7557 | chv_compute_dpll(crtc, pipe_config); |
7558 | chv_prepare_pll(crtc, pipe_config); | |
7559 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7560 | } else { |
3f36b937 TU |
7561 | vlv_compute_dpll(crtc, pipe_config); |
7562 | vlv_prepare_pll(crtc, pipe_config); | |
7563 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7564 | } |
3f36b937 TU |
7565 | |
7566 | kfree(pipe_config); | |
7567 | ||
7568 | return 0; | |
d288f65f VS |
7569 | } |
7570 | ||
7571 | /** | |
7572 | * vlv_force_pll_off - forcibly disable just the PLL | |
7573 | * @dev_priv: i915 private structure | |
7574 | * @pipe: pipe PLL to disable | |
7575 | * | |
7576 | * Disable the PLL for @pipe. To be used in cases where we need | |
7577 | * the PLL enabled even when @pipe is not going to be enabled. | |
7578 | */ | |
7579 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7580 | { | |
7581 | if (IS_CHERRYVIEW(dev)) | |
7582 | chv_disable_pll(to_i915(dev), pipe); | |
7583 | else | |
7584 | vlv_disable_pll(to_i915(dev), pipe); | |
7585 | } | |
7586 | ||
251ac862 DV |
7587 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7588 | struct intel_crtc_state *crtc_state, | |
7589 | intel_clock_t *reduced_clock, | |
7590 | int num_connectors) | |
eb1cbe48 | 7591 | { |
f47709a9 | 7592 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7593 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7594 | u32 dpll; |
7595 | bool is_sdvo; | |
190f68c5 | 7596 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7597 | |
190f68c5 | 7598 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7599 | |
a93e255f ACO |
7600 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7601 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7602 | |
7603 | dpll = DPLL_VGA_MODE_DIS; | |
7604 | ||
a93e255f | 7605 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7606 | dpll |= DPLLB_MODE_LVDS; |
7607 | else | |
7608 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7609 | |
ef1b460d | 7610 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7611 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7612 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7613 | } |
198a037f DV |
7614 | |
7615 | if (is_sdvo) | |
4a33e48d | 7616 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7617 | |
190f68c5 | 7618 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7619 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7620 | |
7621 | /* compute bitmask from p1 value */ | |
7622 | if (IS_PINEVIEW(dev)) | |
7623 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7624 | else { | |
7625 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7626 | if (IS_G4X(dev) && reduced_clock) | |
7627 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7628 | } | |
7629 | switch (clock->p2) { | |
7630 | case 5: | |
7631 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7632 | break; | |
7633 | case 7: | |
7634 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7635 | break; | |
7636 | case 10: | |
7637 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7638 | break; | |
7639 | case 14: | |
7640 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7641 | break; | |
7642 | } | |
7643 | if (INTEL_INFO(dev)->gen >= 4) | |
7644 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7645 | ||
190f68c5 | 7646 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7647 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7648 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7649 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7650 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7651 | else | |
7652 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7653 | ||
7654 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7655 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7656 | |
eb1cbe48 | 7657 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7658 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7659 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7660 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7661 | } |
7662 | } | |
7663 | ||
251ac862 DV |
7664 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7665 | struct intel_crtc_state *crtc_state, | |
7666 | intel_clock_t *reduced_clock, | |
7667 | int num_connectors) | |
eb1cbe48 | 7668 | { |
f47709a9 | 7669 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7670 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7671 | u32 dpll; |
190f68c5 | 7672 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7673 | |
190f68c5 | 7674 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7675 | |
eb1cbe48 DV |
7676 | dpll = DPLL_VGA_MODE_DIS; |
7677 | ||
a93e255f | 7678 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7679 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7680 | } else { | |
7681 | if (clock->p1 == 2) | |
7682 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7683 | else | |
7684 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7685 | if (clock->p2 == 4) | |
7686 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7687 | } | |
7688 | ||
a93e255f | 7689 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7690 | dpll |= DPLL_DVO_2X_MODE; |
7691 | ||
a93e255f | 7692 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7693 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7694 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7695 | else | |
7696 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7697 | ||
7698 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7699 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7700 | } |
7701 | ||
8a654f3b | 7702 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7703 | { |
7704 | struct drm_device *dev = intel_crtc->base.dev; | |
7705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7706 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7707 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7708 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7709 | uint32_t crtc_vtotal, crtc_vblank_end; |
7710 | int vsyncshift = 0; | |
4d8a62ea DV |
7711 | |
7712 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7713 | * the hw state checker will get angry at the mismatch. */ | |
7714 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7715 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7716 | |
609aeaca | 7717 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7718 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7719 | crtc_vtotal -= 1; |
7720 | crtc_vblank_end -= 1; | |
609aeaca | 7721 | |
409ee761 | 7722 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7723 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7724 | else | |
7725 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7726 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7727 | if (vsyncshift < 0) |
7728 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7729 | } |
7730 | ||
7731 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7732 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7733 | |
fe2b8f9d | 7734 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7735 | (adjusted_mode->crtc_hdisplay - 1) | |
7736 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7737 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7738 | (adjusted_mode->crtc_hblank_start - 1) | |
7739 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7740 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7741 | (adjusted_mode->crtc_hsync_start - 1) | |
7742 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7743 | ||
fe2b8f9d | 7744 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7745 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7746 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7747 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7748 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7749 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7750 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7751 | (adjusted_mode->crtc_vsync_start - 1) | |
7752 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7753 | ||
b5e508d4 PZ |
7754 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7755 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7756 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7757 | * bits. */ | |
7758 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7759 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7760 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7761 | ||
b0e77b9c PZ |
7762 | /* pipesrc controls the size that is scaled from, which should |
7763 | * always be the user's requested size. | |
7764 | */ | |
7765 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7766 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7767 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7768 | } |
7769 | ||
1bd1bd80 | 7770 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7771 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7772 | { |
7773 | struct drm_device *dev = crtc->base.dev; | |
7774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7775 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7776 | uint32_t tmp; | |
7777 | ||
7778 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7779 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7780 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7781 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7782 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7783 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7784 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7785 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7786 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7787 | |
7788 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7789 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7790 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7791 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7792 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7793 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7794 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7795 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7796 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7797 | |
7798 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7799 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7800 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7801 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7802 | } |
7803 | ||
7804 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7805 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7806 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7807 | ||
2d112de7 ACO |
7808 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7809 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7810 | } |
7811 | ||
f6a83288 | 7812 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7813 | struct intel_crtc_state *pipe_config) |
babea61d | 7814 | { |
2d112de7 ACO |
7815 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7816 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7817 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7818 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7819 | |
2d112de7 ACO |
7820 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7821 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7822 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7823 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7824 | |
2d112de7 | 7825 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7826 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7827 | |
2d112de7 ACO |
7828 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7829 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7830 | |
7831 | mode->hsync = drm_mode_hsync(mode); | |
7832 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7833 | drm_mode_set_name(mode); | |
babea61d JB |
7834 | } |
7835 | ||
84b046f3 DV |
7836 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7837 | { | |
7838 | struct drm_device *dev = intel_crtc->base.dev; | |
7839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7840 | uint32_t pipeconf; | |
7841 | ||
9f11a9e4 | 7842 | pipeconf = 0; |
84b046f3 | 7843 | |
b6b5d049 VS |
7844 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7845 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7846 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7847 | |
6e3c9717 | 7848 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7849 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7850 | |
ff9ce46e | 7851 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7852 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7853 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7854 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7855 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7856 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7857 | |
6e3c9717 | 7858 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7859 | case 18: |
7860 | pipeconf |= PIPECONF_6BPC; | |
7861 | break; | |
7862 | case 24: | |
7863 | pipeconf |= PIPECONF_8BPC; | |
7864 | break; | |
7865 | case 30: | |
7866 | pipeconf |= PIPECONF_10BPC; | |
7867 | break; | |
7868 | default: | |
7869 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7870 | BUG(); | |
84b046f3 DV |
7871 | } |
7872 | } | |
7873 | ||
7874 | if (HAS_PIPE_CXSR(dev)) { | |
7875 | if (intel_crtc->lowfreq_avail) { | |
7876 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7877 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7878 | } else { | |
7879 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7880 | } |
7881 | } | |
7882 | ||
6e3c9717 | 7883 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7884 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7885 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7886 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7887 | else | |
7888 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7889 | } else | |
84b046f3 DV |
7890 | pipeconf |= PIPECONF_PROGRESSIVE; |
7891 | ||
666a4537 WB |
7892 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7893 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7894 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7895 | |
84b046f3 DV |
7896 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7897 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7898 | } | |
7899 | ||
190f68c5 ACO |
7900 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7901 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7902 | { |
c7653199 | 7903 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7904 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7905 | int refclk, num_connectors = 0; |
c329a4ec DV |
7906 | intel_clock_t clock; |
7907 | bool ok; | |
d4906093 | 7908 | const intel_limit_t *limit; |
55bb9992 | 7909 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7910 | struct drm_connector *connector; |
55bb9992 ACO |
7911 | struct drm_connector_state *connector_state; |
7912 | int i; | |
79e53945 | 7913 | |
dd3cd74a ACO |
7914 | memset(&crtc_state->dpll_hw_state, 0, |
7915 | sizeof(crtc_state->dpll_hw_state)); | |
7916 | ||
a65347ba JN |
7917 | if (crtc_state->has_dsi_encoder) |
7918 | return 0; | |
43565a06 | 7919 | |
a65347ba JN |
7920 | for_each_connector_in_state(state, connector, connector_state, i) { |
7921 | if (connector_state->crtc == &crtc->base) | |
7922 | num_connectors++; | |
79e53945 JB |
7923 | } |
7924 | ||
190f68c5 | 7925 | if (!crtc_state->clock_set) { |
a93e255f | 7926 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7927 | |
e9fd1c02 JN |
7928 | /* |
7929 | * Returns a set of divisors for the desired target clock with | |
7930 | * the given refclk, or FALSE. The returned values represent | |
7931 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7932 | * 2) / p1 / p2. | |
7933 | */ | |
a93e255f ACO |
7934 | limit = intel_limit(crtc_state, refclk); |
7935 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7936 | crtc_state->port_clock, |
e9fd1c02 | 7937 | refclk, NULL, &clock); |
f2335330 | 7938 | if (!ok) { |
e9fd1c02 JN |
7939 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7940 | return -EINVAL; | |
7941 | } | |
79e53945 | 7942 | |
f2335330 | 7943 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7944 | crtc_state->dpll.n = clock.n; |
7945 | crtc_state->dpll.m1 = clock.m1; | |
7946 | crtc_state->dpll.m2 = clock.m2; | |
7947 | crtc_state->dpll.p1 = clock.p1; | |
7948 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7949 | } |
7026d4ac | 7950 | |
e9fd1c02 | 7951 | if (IS_GEN2(dev)) { |
c329a4ec | 7952 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7953 | num_connectors); |
9d556c99 | 7954 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7955 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7956 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7957 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7958 | } else { |
c329a4ec | 7959 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7960 | num_connectors); |
e9fd1c02 | 7961 | } |
79e53945 | 7962 | |
c8f7a0db | 7963 | return 0; |
f564048e EA |
7964 | } |
7965 | ||
2fa2fe9a | 7966 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7967 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7968 | { |
7969 | struct drm_device *dev = crtc->base.dev; | |
7970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7971 | uint32_t tmp; | |
7972 | ||
dc9e7dec VS |
7973 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7974 | return; | |
7975 | ||
2fa2fe9a | 7976 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7977 | if (!(tmp & PFIT_ENABLE)) |
7978 | return; | |
2fa2fe9a | 7979 | |
06922821 | 7980 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7981 | if (INTEL_INFO(dev)->gen < 4) { |
7982 | if (crtc->pipe != PIPE_B) | |
7983 | return; | |
2fa2fe9a DV |
7984 | } else { |
7985 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7986 | return; | |
7987 | } | |
7988 | ||
06922821 | 7989 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7990 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7991 | if (INTEL_INFO(dev)->gen < 5) | |
7992 | pipe_config->gmch_pfit.lvds_border_bits = | |
7993 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7994 | } | |
7995 | ||
acbec814 | 7996 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7997 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7998 | { |
7999 | struct drm_device *dev = crtc->base.dev; | |
8000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8001 | int pipe = pipe_config->cpu_transcoder; | |
8002 | intel_clock_t clock; | |
8003 | u32 mdiv; | |
662c6ecb | 8004 | int refclk = 100000; |
acbec814 | 8005 | |
f573de5a SK |
8006 | /* In case of MIPI DPLL will not even be used */ |
8007 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8008 | return; | |
8009 | ||
a580516d | 8010 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8011 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8012 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8013 | |
8014 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8015 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8016 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8017 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8018 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8019 | ||
dccbea3b | 8020 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8021 | } |
8022 | ||
5724dbd1 DL |
8023 | static void |
8024 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8025 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8026 | { |
8027 | struct drm_device *dev = crtc->base.dev; | |
8028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8029 | u32 val, base, offset; | |
8030 | int pipe = crtc->pipe, plane = crtc->plane; | |
8031 | int fourcc, pixel_format; | |
6761dd31 | 8032 | unsigned int aligned_height; |
b113d5ee | 8033 | struct drm_framebuffer *fb; |
1b842c89 | 8034 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8035 | |
42a7b088 DL |
8036 | val = I915_READ(DSPCNTR(plane)); |
8037 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8038 | return; | |
8039 | ||
d9806c9f | 8040 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8041 | if (!intel_fb) { |
1ad292b5 JB |
8042 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8043 | return; | |
8044 | } | |
8045 | ||
1b842c89 DL |
8046 | fb = &intel_fb->base; |
8047 | ||
18c5247e DV |
8048 | if (INTEL_INFO(dev)->gen >= 4) { |
8049 | if (val & DISPPLANE_TILED) { | |
49af449b | 8050 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8051 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8052 | } | |
8053 | } | |
1ad292b5 JB |
8054 | |
8055 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8056 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8057 | fb->pixel_format = fourcc; |
8058 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8059 | |
8060 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8061 | if (plane_config->tiling) |
1ad292b5 JB |
8062 | offset = I915_READ(DSPTILEOFF(plane)); |
8063 | else | |
8064 | offset = I915_READ(DSPLINOFF(plane)); | |
8065 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8066 | } else { | |
8067 | base = I915_READ(DSPADDR(plane)); | |
8068 | } | |
8069 | plane_config->base = base; | |
8070 | ||
8071 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8072 | fb->width = ((val >> 16) & 0xfff) + 1; |
8073 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8074 | |
8075 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8076 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8077 | |
b113d5ee | 8078 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8079 | fb->pixel_format, |
8080 | fb->modifier[0]); | |
1ad292b5 | 8081 | |
f37b5c2b | 8082 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8083 | |
2844a921 DL |
8084 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8085 | pipe_name(pipe), plane, fb->width, fb->height, | |
8086 | fb->bits_per_pixel, base, fb->pitches[0], | |
8087 | plane_config->size); | |
1ad292b5 | 8088 | |
2d14030b | 8089 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8090 | } |
8091 | ||
70b23a98 | 8092 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8093 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8094 | { |
8095 | struct drm_device *dev = crtc->base.dev; | |
8096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8097 | int pipe = pipe_config->cpu_transcoder; | |
8098 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8099 | intel_clock_t clock; | |
0d7b6b11 | 8100 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8101 | int refclk = 100000; |
8102 | ||
a580516d | 8103 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8104 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8105 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8106 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8107 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8108 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8109 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8110 | |
8111 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8112 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8113 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8114 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8115 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8116 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8117 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8118 | ||
dccbea3b | 8119 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8120 | } |
8121 | ||
0e8ffe1b | 8122 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8123 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8124 | { |
8125 | struct drm_device *dev = crtc->base.dev; | |
8126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8127 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8128 | uint32_t tmp; |
1729050e | 8129 | bool ret; |
0e8ffe1b | 8130 | |
1729050e ID |
8131 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8132 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8133 | return false; |
8134 | ||
e143a21c | 8135 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8136 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8137 | |
1729050e ID |
8138 | ret = false; |
8139 | ||
0e8ffe1b DV |
8140 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8141 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8142 | goto out; |
0e8ffe1b | 8143 | |
666a4537 | 8144 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8145 | switch (tmp & PIPECONF_BPC_MASK) { |
8146 | case PIPECONF_6BPC: | |
8147 | pipe_config->pipe_bpp = 18; | |
8148 | break; | |
8149 | case PIPECONF_8BPC: | |
8150 | pipe_config->pipe_bpp = 24; | |
8151 | break; | |
8152 | case PIPECONF_10BPC: | |
8153 | pipe_config->pipe_bpp = 30; | |
8154 | break; | |
8155 | default: | |
8156 | break; | |
8157 | } | |
8158 | } | |
8159 | ||
666a4537 WB |
8160 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8161 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8162 | pipe_config->limited_color_range = true; |
8163 | ||
282740f7 VS |
8164 | if (INTEL_INFO(dev)->gen < 4) |
8165 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8166 | ||
1bd1bd80 DV |
8167 | intel_get_pipe_timings(crtc, pipe_config); |
8168 | ||
2fa2fe9a DV |
8169 | i9xx_get_pfit_config(crtc, pipe_config); |
8170 | ||
6c49f241 DV |
8171 | if (INTEL_INFO(dev)->gen >= 4) { |
8172 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8173 | pipe_config->pixel_multiplier = | |
8174 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8175 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8176 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8177 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8178 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8179 | pipe_config->pixel_multiplier = | |
8180 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8181 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8182 | } else { | |
8183 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8184 | * port and will be fixed up in the encoder->get_config | |
8185 | * function. */ | |
8186 | pipe_config->pixel_multiplier = 1; | |
8187 | } | |
8bcc2795 | 8188 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8189 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8190 | /* |
8191 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8192 | * on 830. Filter it out here so that we don't | |
8193 | * report errors due to that. | |
8194 | */ | |
8195 | if (IS_I830(dev)) | |
8196 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8197 | ||
8bcc2795 DV |
8198 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8199 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8200 | } else { |
8201 | /* Mask out read-only status bits. */ | |
8202 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8203 | DPLL_PORTC_READY_MASK | | |
8204 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8205 | } |
6c49f241 | 8206 | |
70b23a98 VS |
8207 | if (IS_CHERRYVIEW(dev)) |
8208 | chv_crtc_clock_get(crtc, pipe_config); | |
8209 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8210 | vlv_crtc_clock_get(crtc, pipe_config); |
8211 | else | |
8212 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8213 | |
0f64614d VS |
8214 | /* |
8215 | * Normally the dotclock is filled in by the encoder .get_config() | |
8216 | * but in case the pipe is enabled w/o any ports we need a sane | |
8217 | * default. | |
8218 | */ | |
8219 | pipe_config->base.adjusted_mode.crtc_clock = | |
8220 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8221 | ||
1729050e ID |
8222 | ret = true; |
8223 | ||
8224 | out: | |
8225 | intel_display_power_put(dev_priv, power_domain); | |
8226 | ||
8227 | return ret; | |
0e8ffe1b DV |
8228 | } |
8229 | ||
dde86e2d | 8230 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8231 | { |
8232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8233 | struct intel_encoder *encoder; |
74cfd7ac | 8234 | u32 val, final; |
13d83a67 | 8235 | bool has_lvds = false; |
199e5d79 | 8236 | bool has_cpu_edp = false; |
199e5d79 | 8237 | bool has_panel = false; |
99eb6a01 KP |
8238 | bool has_ck505 = false; |
8239 | bool can_ssc = false; | |
13d83a67 JB |
8240 | |
8241 | /* We need to take the global config into account */ | |
b2784e15 | 8242 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8243 | switch (encoder->type) { |
8244 | case INTEL_OUTPUT_LVDS: | |
8245 | has_panel = true; | |
8246 | has_lvds = true; | |
8247 | break; | |
8248 | case INTEL_OUTPUT_EDP: | |
8249 | has_panel = true; | |
2de6905f | 8250 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8251 | has_cpu_edp = true; |
8252 | break; | |
6847d71b PZ |
8253 | default: |
8254 | break; | |
13d83a67 JB |
8255 | } |
8256 | } | |
8257 | ||
99eb6a01 | 8258 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8259 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8260 | can_ssc = has_ck505; |
8261 | } else { | |
8262 | has_ck505 = false; | |
8263 | can_ssc = true; | |
8264 | } | |
8265 | ||
2de6905f ID |
8266 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8267 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8268 | |
8269 | /* Ironlake: try to setup display ref clock before DPLL | |
8270 | * enabling. This is only under driver's control after | |
8271 | * PCH B stepping, previous chipset stepping should be | |
8272 | * ignoring this setting. | |
8273 | */ | |
74cfd7ac CW |
8274 | val = I915_READ(PCH_DREF_CONTROL); |
8275 | ||
8276 | /* As we must carefully and slowly disable/enable each source in turn, | |
8277 | * compute the final state we want first and check if we need to | |
8278 | * make any changes at all. | |
8279 | */ | |
8280 | final = val; | |
8281 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8282 | if (has_ck505) | |
8283 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8284 | else | |
8285 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8286 | ||
8287 | final &= ~DREF_SSC_SOURCE_MASK; | |
8288 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8289 | final &= ~DREF_SSC1_ENABLE; | |
8290 | ||
8291 | if (has_panel) { | |
8292 | final |= DREF_SSC_SOURCE_ENABLE; | |
8293 | ||
8294 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8295 | final |= DREF_SSC1_ENABLE; | |
8296 | ||
8297 | if (has_cpu_edp) { | |
8298 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8299 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8300 | else | |
8301 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8302 | } else | |
8303 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8304 | } else { | |
8305 | final |= DREF_SSC_SOURCE_DISABLE; | |
8306 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8307 | } | |
8308 | ||
8309 | if (final == val) | |
8310 | return; | |
8311 | ||
13d83a67 | 8312 | /* Always enable nonspread source */ |
74cfd7ac | 8313 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8314 | |
99eb6a01 | 8315 | if (has_ck505) |
74cfd7ac | 8316 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8317 | else |
74cfd7ac | 8318 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8319 | |
199e5d79 | 8320 | if (has_panel) { |
74cfd7ac CW |
8321 | val &= ~DREF_SSC_SOURCE_MASK; |
8322 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8323 | |
199e5d79 | 8324 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8325 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8326 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8327 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8328 | } else |
74cfd7ac | 8329 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8330 | |
8331 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8332 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8333 | POSTING_READ(PCH_DREF_CONTROL); |
8334 | udelay(200); | |
8335 | ||
74cfd7ac | 8336 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8337 | |
8338 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8339 | if (has_cpu_edp) { |
99eb6a01 | 8340 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8341 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8342 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8343 | } else |
74cfd7ac | 8344 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8345 | } else |
74cfd7ac | 8346 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8347 | |
74cfd7ac | 8348 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8349 | POSTING_READ(PCH_DREF_CONTROL); |
8350 | udelay(200); | |
8351 | } else { | |
8352 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8353 | ||
74cfd7ac | 8354 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8355 | |
8356 | /* Turn off CPU output */ | |
74cfd7ac | 8357 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8358 | |
74cfd7ac | 8359 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8360 | POSTING_READ(PCH_DREF_CONTROL); |
8361 | udelay(200); | |
8362 | ||
8363 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8364 | val &= ~DREF_SSC_SOURCE_MASK; |
8365 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8366 | |
8367 | /* Turn off SSC1 */ | |
74cfd7ac | 8368 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8369 | |
74cfd7ac | 8370 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8371 | POSTING_READ(PCH_DREF_CONTROL); |
8372 | udelay(200); | |
8373 | } | |
74cfd7ac CW |
8374 | |
8375 | BUG_ON(val != final); | |
13d83a67 JB |
8376 | } |
8377 | ||
f31f2d55 | 8378 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8379 | { |
f31f2d55 | 8380 | uint32_t tmp; |
dde86e2d | 8381 | |
0ff066a9 PZ |
8382 | tmp = I915_READ(SOUTH_CHICKEN2); |
8383 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8384 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8385 | |
0ff066a9 PZ |
8386 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8387 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8388 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8389 | |
0ff066a9 PZ |
8390 | tmp = I915_READ(SOUTH_CHICKEN2); |
8391 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8392 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8393 | |
0ff066a9 PZ |
8394 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8395 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8396 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8397 | } |
8398 | ||
8399 | /* WaMPhyProgramming:hsw */ | |
8400 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8401 | { | |
8402 | uint32_t tmp; | |
dde86e2d PZ |
8403 | |
8404 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8405 | tmp &= ~(0xFF << 24); | |
8406 | tmp |= (0x12 << 24); | |
8407 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8408 | ||
dde86e2d PZ |
8409 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8410 | tmp |= (1 << 11); | |
8411 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8412 | ||
8413 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8414 | tmp |= (1 << 11); | |
8415 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8416 | ||
dde86e2d PZ |
8417 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8418 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8419 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8420 | ||
8421 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8422 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8423 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8424 | ||
0ff066a9 PZ |
8425 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8426 | tmp &= ~(7 << 13); | |
8427 | tmp |= (5 << 13); | |
8428 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8429 | |
0ff066a9 PZ |
8430 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8431 | tmp &= ~(7 << 13); | |
8432 | tmp |= (5 << 13); | |
8433 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8434 | |
8435 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8436 | tmp &= ~0xFF; | |
8437 | tmp |= 0x1C; | |
8438 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8439 | ||
8440 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8441 | tmp &= ~0xFF; | |
8442 | tmp |= 0x1C; | |
8443 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8444 | ||
8445 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8446 | tmp &= ~(0xFF << 16); | |
8447 | tmp |= (0x1C << 16); | |
8448 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8449 | ||
8450 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8451 | tmp &= ~(0xFF << 16); | |
8452 | tmp |= (0x1C << 16); | |
8453 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8454 | ||
0ff066a9 PZ |
8455 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8456 | tmp |= (1 << 27); | |
8457 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8458 | |
0ff066a9 PZ |
8459 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8460 | tmp |= (1 << 27); | |
8461 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8462 | |
0ff066a9 PZ |
8463 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8464 | tmp &= ~(0xF << 28); | |
8465 | tmp |= (4 << 28); | |
8466 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8467 | |
0ff066a9 PZ |
8468 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8469 | tmp &= ~(0xF << 28); | |
8470 | tmp |= (4 << 28); | |
8471 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8472 | } |
8473 | ||
2fa86a1f PZ |
8474 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8475 | * Programming" based on the parameters passed: | |
8476 | * - Sequence to enable CLKOUT_DP | |
8477 | * - Sequence to enable CLKOUT_DP without spread | |
8478 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8479 | */ | |
8480 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8481 | bool with_fdi) | |
f31f2d55 PZ |
8482 | { |
8483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8484 | uint32_t reg, tmp; |
8485 | ||
8486 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8487 | with_spread = true; | |
c2699524 | 8488 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8489 | with_fdi = false; |
f31f2d55 | 8490 | |
a580516d | 8491 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8492 | |
8493 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8494 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8495 | tmp |= SBI_SSCCTL_PATHALT; | |
8496 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8497 | ||
8498 | udelay(24); | |
8499 | ||
2fa86a1f PZ |
8500 | if (with_spread) { |
8501 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8502 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8503 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8504 | |
2fa86a1f PZ |
8505 | if (with_fdi) { |
8506 | lpt_reset_fdi_mphy(dev_priv); | |
8507 | lpt_program_fdi_mphy(dev_priv); | |
8508 | } | |
8509 | } | |
dde86e2d | 8510 | |
c2699524 | 8511 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8512 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8513 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8514 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8515 | |
a580516d | 8516 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8517 | } |
8518 | ||
47701c3b PZ |
8519 | /* Sequence to disable CLKOUT_DP */ |
8520 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8521 | { | |
8522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8523 | uint32_t reg, tmp; | |
8524 | ||
a580516d | 8525 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8526 | |
c2699524 | 8527 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8528 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8529 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8530 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8531 | ||
8532 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8533 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8534 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8535 | tmp |= SBI_SSCCTL_PATHALT; | |
8536 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8537 | udelay(32); | |
8538 | } | |
8539 | tmp |= SBI_SSCCTL_DISABLE; | |
8540 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8541 | } | |
8542 | ||
a580516d | 8543 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8544 | } |
8545 | ||
f7be2c21 VS |
8546 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8547 | ||
8548 | static const uint16_t sscdivintphase[] = { | |
8549 | [BEND_IDX( 50)] = 0x3B23, | |
8550 | [BEND_IDX( 45)] = 0x3B23, | |
8551 | [BEND_IDX( 40)] = 0x3C23, | |
8552 | [BEND_IDX( 35)] = 0x3C23, | |
8553 | [BEND_IDX( 30)] = 0x3D23, | |
8554 | [BEND_IDX( 25)] = 0x3D23, | |
8555 | [BEND_IDX( 20)] = 0x3E23, | |
8556 | [BEND_IDX( 15)] = 0x3E23, | |
8557 | [BEND_IDX( 10)] = 0x3F23, | |
8558 | [BEND_IDX( 5)] = 0x3F23, | |
8559 | [BEND_IDX( 0)] = 0x0025, | |
8560 | [BEND_IDX( -5)] = 0x0025, | |
8561 | [BEND_IDX(-10)] = 0x0125, | |
8562 | [BEND_IDX(-15)] = 0x0125, | |
8563 | [BEND_IDX(-20)] = 0x0225, | |
8564 | [BEND_IDX(-25)] = 0x0225, | |
8565 | [BEND_IDX(-30)] = 0x0325, | |
8566 | [BEND_IDX(-35)] = 0x0325, | |
8567 | [BEND_IDX(-40)] = 0x0425, | |
8568 | [BEND_IDX(-45)] = 0x0425, | |
8569 | [BEND_IDX(-50)] = 0x0525, | |
8570 | }; | |
8571 | ||
8572 | /* | |
8573 | * Bend CLKOUT_DP | |
8574 | * steps -50 to 50 inclusive, in steps of 5 | |
8575 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8576 | * change in clock period = -(steps / 10) * 5.787 ps | |
8577 | */ | |
8578 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8579 | { | |
8580 | uint32_t tmp; | |
8581 | int idx = BEND_IDX(steps); | |
8582 | ||
8583 | if (WARN_ON(steps % 5 != 0)) | |
8584 | return; | |
8585 | ||
8586 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8587 | return; | |
8588 | ||
8589 | mutex_lock(&dev_priv->sb_lock); | |
8590 | ||
8591 | if (steps % 10 != 0) | |
8592 | tmp = 0xAAAAAAAB; | |
8593 | else | |
8594 | tmp = 0x00000000; | |
8595 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8596 | ||
8597 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8598 | tmp &= 0xffff0000; | |
8599 | tmp |= sscdivintphase[idx]; | |
8600 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8601 | ||
8602 | mutex_unlock(&dev_priv->sb_lock); | |
8603 | } | |
8604 | ||
8605 | #undef BEND_IDX | |
8606 | ||
bf8fa3d3 PZ |
8607 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8608 | { | |
bf8fa3d3 PZ |
8609 | struct intel_encoder *encoder; |
8610 | bool has_vga = false; | |
8611 | ||
b2784e15 | 8612 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8613 | switch (encoder->type) { |
8614 | case INTEL_OUTPUT_ANALOG: | |
8615 | has_vga = true; | |
8616 | break; | |
6847d71b PZ |
8617 | default: |
8618 | break; | |
bf8fa3d3 PZ |
8619 | } |
8620 | } | |
8621 | ||
f7be2c21 VS |
8622 | if (has_vga) { |
8623 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8624 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8625 | } else { |
47701c3b | 8626 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8627 | } |
bf8fa3d3 PZ |
8628 | } |
8629 | ||
dde86e2d PZ |
8630 | /* |
8631 | * Initialize reference clocks when the driver loads | |
8632 | */ | |
8633 | void intel_init_pch_refclk(struct drm_device *dev) | |
8634 | { | |
8635 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8636 | ironlake_init_pch_refclk(dev); | |
8637 | else if (HAS_PCH_LPT(dev)) | |
8638 | lpt_init_pch_refclk(dev); | |
8639 | } | |
8640 | ||
55bb9992 | 8641 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8642 | { |
55bb9992 | 8643 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8644 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8645 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8646 | struct drm_connector *connector; |
55bb9992 | 8647 | struct drm_connector_state *connector_state; |
d9d444cb | 8648 | struct intel_encoder *encoder; |
55bb9992 | 8649 | int num_connectors = 0, i; |
d9d444cb JB |
8650 | bool is_lvds = false; |
8651 | ||
da3ced29 | 8652 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8653 | if (connector_state->crtc != crtc_state->base.crtc) |
8654 | continue; | |
8655 | ||
8656 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8657 | ||
d9d444cb JB |
8658 | switch (encoder->type) { |
8659 | case INTEL_OUTPUT_LVDS: | |
8660 | is_lvds = true; | |
8661 | break; | |
6847d71b PZ |
8662 | default: |
8663 | break; | |
d9d444cb JB |
8664 | } |
8665 | num_connectors++; | |
8666 | } | |
8667 | ||
8668 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8669 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8670 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8671 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8672 | } |
8673 | ||
8674 | return 120000; | |
8675 | } | |
8676 | ||
6ff93609 | 8677 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8678 | { |
c8203565 | 8679 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8680 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8681 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8682 | uint32_t val; |
8683 | ||
78114071 | 8684 | val = 0; |
c8203565 | 8685 | |
6e3c9717 | 8686 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8687 | case 18: |
dfd07d72 | 8688 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8689 | break; |
8690 | case 24: | |
dfd07d72 | 8691 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8692 | break; |
8693 | case 30: | |
dfd07d72 | 8694 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8695 | break; |
8696 | case 36: | |
dfd07d72 | 8697 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8698 | break; |
8699 | default: | |
cc769b62 PZ |
8700 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8701 | BUG(); | |
c8203565 PZ |
8702 | } |
8703 | ||
6e3c9717 | 8704 | if (intel_crtc->config->dither) |
c8203565 PZ |
8705 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8706 | ||
6e3c9717 | 8707 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8708 | val |= PIPECONF_INTERLACED_ILK; |
8709 | else | |
8710 | val |= PIPECONF_PROGRESSIVE; | |
8711 | ||
6e3c9717 | 8712 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8713 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8714 | |
c8203565 PZ |
8715 | I915_WRITE(PIPECONF(pipe), val); |
8716 | POSTING_READ(PIPECONF(pipe)); | |
8717 | } | |
8718 | ||
86d3efce VS |
8719 | /* |
8720 | * Set up the pipe CSC unit. | |
8721 | * | |
8722 | * Currently only full range RGB to limited range RGB conversion | |
8723 | * is supported, but eventually this should handle various | |
8724 | * RGB<->YCbCr scenarios as well. | |
8725 | */ | |
50f3b016 | 8726 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8727 | { |
8728 | struct drm_device *dev = crtc->dev; | |
8729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8731 | int pipe = intel_crtc->pipe; | |
8732 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8733 | ||
8734 | /* | |
8735 | * TODO: Check what kind of values actually come out of the pipe | |
8736 | * with these coeff/postoff values and adjust to get the best | |
8737 | * accuracy. Perhaps we even need to take the bpc value into | |
8738 | * consideration. | |
8739 | */ | |
8740 | ||
6e3c9717 | 8741 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8742 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8743 | ||
8744 | /* | |
8745 | * GY/GU and RY/RU should be the other way around according | |
8746 | * to BSpec, but reality doesn't agree. Just set them up in | |
8747 | * a way that results in the correct picture. | |
8748 | */ | |
8749 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8750 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8751 | ||
8752 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8753 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8754 | ||
8755 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8756 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8757 | ||
8758 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8759 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8760 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8761 | ||
8762 | if (INTEL_INFO(dev)->gen > 6) { | |
8763 | uint16_t postoff = 0; | |
8764 | ||
6e3c9717 | 8765 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8766 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8767 | |
8768 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8769 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8770 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8771 | ||
8772 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8773 | } else { | |
8774 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8775 | ||
6e3c9717 | 8776 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8777 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8778 | ||
8779 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8780 | } | |
8781 | } | |
8782 | ||
6ff93609 | 8783 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8784 | { |
756f85cf PZ |
8785 | struct drm_device *dev = crtc->dev; |
8786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8788 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8789 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8790 | uint32_t val; |
8791 | ||
3eff4faa | 8792 | val = 0; |
ee2b0b38 | 8793 | |
6e3c9717 | 8794 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8795 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8796 | ||
6e3c9717 | 8797 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8798 | val |= PIPECONF_INTERLACED_ILK; |
8799 | else | |
8800 | val |= PIPECONF_PROGRESSIVE; | |
8801 | ||
702e7a56 PZ |
8802 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8803 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8804 | |
8805 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8806 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8807 | |
3cdf122c | 8808 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8809 | val = 0; |
8810 | ||
6e3c9717 | 8811 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8812 | case 18: |
8813 | val |= PIPEMISC_DITHER_6_BPC; | |
8814 | break; | |
8815 | case 24: | |
8816 | val |= PIPEMISC_DITHER_8_BPC; | |
8817 | break; | |
8818 | case 30: | |
8819 | val |= PIPEMISC_DITHER_10_BPC; | |
8820 | break; | |
8821 | case 36: | |
8822 | val |= PIPEMISC_DITHER_12_BPC; | |
8823 | break; | |
8824 | default: | |
8825 | /* Case prevented by pipe_config_set_bpp. */ | |
8826 | BUG(); | |
8827 | } | |
8828 | ||
6e3c9717 | 8829 | if (intel_crtc->config->dither) |
756f85cf PZ |
8830 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8831 | ||
8832 | I915_WRITE(PIPEMISC(pipe), val); | |
8833 | } | |
ee2b0b38 PZ |
8834 | } |
8835 | ||
6591c6e4 | 8836 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8837 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8838 | intel_clock_t *clock, |
8839 | bool *has_reduced_clock, | |
8840 | intel_clock_t *reduced_clock) | |
8841 | { | |
8842 | struct drm_device *dev = crtc->dev; | |
8843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8844 | int refclk; |
d4906093 | 8845 | const intel_limit_t *limit; |
c329a4ec | 8846 | bool ret; |
79e53945 | 8847 | |
55bb9992 | 8848 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8849 | |
d4906093 ML |
8850 | /* |
8851 | * Returns a set of divisors for the desired target clock with the given | |
8852 | * refclk, or FALSE. The returned values represent the clock equation: | |
8853 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8854 | */ | |
a93e255f ACO |
8855 | limit = intel_limit(crtc_state, refclk); |
8856 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8857 | crtc_state->port_clock, |
ee9300bb | 8858 | refclk, NULL, clock); |
6591c6e4 PZ |
8859 | if (!ret) |
8860 | return false; | |
cda4b7d3 | 8861 | |
6591c6e4 PZ |
8862 | return true; |
8863 | } | |
8864 | ||
d4b1931c PZ |
8865 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8866 | { | |
8867 | /* | |
8868 | * Account for spread spectrum to avoid | |
8869 | * oversubscribing the link. Max center spread | |
8870 | * is 2.5%; use 5% for safety's sake. | |
8871 | */ | |
8872 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8873 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8874 | } |
8875 | ||
7429e9d4 | 8876 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8877 | { |
7429e9d4 | 8878 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8879 | } |
8880 | ||
de13a2e3 | 8881 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8882 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8883 | u32 *fp, |
9a7c7890 | 8884 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8885 | { |
de13a2e3 | 8886 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8887 | struct drm_device *dev = crtc->dev; |
8888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8889 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8890 | struct drm_connector *connector; |
55bb9992 ACO |
8891 | struct drm_connector_state *connector_state; |
8892 | struct intel_encoder *encoder; | |
de13a2e3 | 8893 | uint32_t dpll; |
55bb9992 | 8894 | int factor, num_connectors = 0, i; |
09ede541 | 8895 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8896 | |
da3ced29 | 8897 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8898 | if (connector_state->crtc != crtc_state->base.crtc) |
8899 | continue; | |
8900 | ||
8901 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8902 | ||
8903 | switch (encoder->type) { | |
79e53945 JB |
8904 | case INTEL_OUTPUT_LVDS: |
8905 | is_lvds = true; | |
8906 | break; | |
8907 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8908 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8909 | is_sdvo = true; |
79e53945 | 8910 | break; |
6847d71b PZ |
8911 | default: |
8912 | break; | |
79e53945 | 8913 | } |
43565a06 | 8914 | |
c751ce4f | 8915 | num_connectors++; |
79e53945 | 8916 | } |
79e53945 | 8917 | |
c1858123 | 8918 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8919 | factor = 21; |
8920 | if (is_lvds) { | |
8921 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8922 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8923 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8924 | factor = 25; |
190f68c5 | 8925 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8926 | factor = 20; |
c1858123 | 8927 | |
190f68c5 | 8928 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8929 | *fp |= FP_CB_TUNE; |
2c07245f | 8930 | |
9a7c7890 DV |
8931 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8932 | *fp2 |= FP_CB_TUNE; | |
8933 | ||
5eddb70b | 8934 | dpll = 0; |
2c07245f | 8935 | |
a07d6787 EA |
8936 | if (is_lvds) |
8937 | dpll |= DPLLB_MODE_LVDS; | |
8938 | else | |
8939 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8940 | |
190f68c5 | 8941 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8942 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8943 | |
8944 | if (is_sdvo) | |
4a33e48d | 8945 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8946 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8947 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8948 | |
a07d6787 | 8949 | /* compute bitmask from p1 value */ |
190f68c5 | 8950 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8951 | /* also FPA1 */ |
190f68c5 | 8952 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8953 | |
190f68c5 | 8954 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8955 | case 5: |
8956 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8957 | break; | |
8958 | case 7: | |
8959 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8960 | break; | |
8961 | case 10: | |
8962 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8963 | break; | |
8964 | case 14: | |
8965 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8966 | break; | |
79e53945 JB |
8967 | } |
8968 | ||
b4c09f3b | 8969 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8970 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8971 | else |
8972 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8973 | ||
959e16d6 | 8974 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8975 | } |
8976 | ||
190f68c5 ACO |
8977 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8978 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8979 | { |
c7653199 | 8980 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8981 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8982 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8983 | bool ok, has_reduced_clock = false; |
8b47047b | 8984 | bool is_lvds = false; |
e2b78267 | 8985 | struct intel_shared_dpll *pll; |
de13a2e3 | 8986 | |
dd3cd74a ACO |
8987 | memset(&crtc_state->dpll_hw_state, 0, |
8988 | sizeof(crtc_state->dpll_hw_state)); | |
8989 | ||
7905df29 | 8990 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8991 | |
5dc5298b PZ |
8992 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8993 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8994 | |
190f68c5 | 8995 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8996 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8997 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8998 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8999 | return -EINVAL; | |
79e53945 | 9000 | } |
f47709a9 | 9001 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9002 | if (!crtc_state->clock_set) { |
9003 | crtc_state->dpll.n = clock.n; | |
9004 | crtc_state->dpll.m1 = clock.m1; | |
9005 | crtc_state->dpll.m2 = clock.m2; | |
9006 | crtc_state->dpll.p1 = clock.p1; | |
9007 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9008 | } |
79e53945 | 9009 | |
5dc5298b | 9010 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9011 | if (crtc_state->has_pch_encoder) { |
9012 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9013 | if (has_reduced_clock) |
7429e9d4 | 9014 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9015 | |
190f68c5 | 9016 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9017 | &fp, &reduced_clock, |
9018 | has_reduced_clock ? &fp2 : NULL); | |
9019 | ||
190f68c5 ACO |
9020 | crtc_state->dpll_hw_state.dpll = dpll; |
9021 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9022 | if (has_reduced_clock) |
190f68c5 | 9023 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9024 | else |
190f68c5 | 9025 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9026 | |
190f68c5 | 9027 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9028 | if (pll == NULL) { |
84f44ce7 | 9029 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9030 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9031 | return -EINVAL; |
9032 | } | |
3fb37703 | 9033 | } |
79e53945 | 9034 | |
ab585dea | 9035 | if (is_lvds && has_reduced_clock) |
c7653199 | 9036 | crtc->lowfreq_avail = true; |
bcd644e0 | 9037 | else |
c7653199 | 9038 | crtc->lowfreq_avail = false; |
e2b78267 | 9039 | |
c8f7a0db | 9040 | return 0; |
79e53945 JB |
9041 | } |
9042 | ||
eb14cb74 VS |
9043 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9044 | struct intel_link_m_n *m_n) | |
9045 | { | |
9046 | struct drm_device *dev = crtc->base.dev; | |
9047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9048 | enum pipe pipe = crtc->pipe; | |
9049 | ||
9050 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9051 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9052 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9053 | & ~TU_SIZE_MASK; | |
9054 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9055 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9056 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9057 | } | |
9058 | ||
9059 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9060 | enum transcoder transcoder, | |
b95af8be VK |
9061 | struct intel_link_m_n *m_n, |
9062 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9063 | { |
9064 | struct drm_device *dev = crtc->base.dev; | |
9065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9066 | enum pipe pipe = crtc->pipe; |
72419203 | 9067 | |
eb14cb74 VS |
9068 | if (INTEL_INFO(dev)->gen >= 5) { |
9069 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9070 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9071 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9072 | & ~TU_SIZE_MASK; | |
9073 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9074 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9075 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9076 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9077 | * gen < 8) and if DRRS is supported (to make sure the | |
9078 | * registers are not unnecessarily read). | |
9079 | */ | |
9080 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9081 | crtc->config->has_drrs) { |
b95af8be VK |
9082 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9083 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9084 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9085 | & ~TU_SIZE_MASK; | |
9086 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9087 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9088 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9089 | } | |
eb14cb74 VS |
9090 | } else { |
9091 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9092 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9093 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9094 | & ~TU_SIZE_MASK; | |
9095 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9096 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9097 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9098 | } | |
9099 | } | |
9100 | ||
9101 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9102 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9103 | { |
681a8504 | 9104 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9105 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9106 | else | |
9107 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9108 | &pipe_config->dp_m_n, |
9109 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9110 | } |
72419203 | 9111 | |
eb14cb74 | 9112 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9113 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9114 | { |
9115 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9116 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9117 | } |
9118 | ||
bd2e244f | 9119 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9120 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9121 | { |
9122 | struct drm_device *dev = crtc->base.dev; | |
9123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9124 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9125 | uint32_t ps_ctrl = 0; | |
9126 | int id = -1; | |
9127 | int i; | |
bd2e244f | 9128 | |
a1b2278e CK |
9129 | /* find scaler attached to this pipe */ |
9130 | for (i = 0; i < crtc->num_scalers; i++) { | |
9131 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9132 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9133 | id = i; | |
9134 | pipe_config->pch_pfit.enabled = true; | |
9135 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9136 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9137 | break; | |
9138 | } | |
9139 | } | |
bd2e244f | 9140 | |
a1b2278e CK |
9141 | scaler_state->scaler_id = id; |
9142 | if (id >= 0) { | |
9143 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9144 | } else { | |
9145 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9146 | } |
9147 | } | |
9148 | ||
5724dbd1 DL |
9149 | static void |
9150 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9151 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9152 | { |
9153 | struct drm_device *dev = crtc->base.dev; | |
9154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9155 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9156 | int pipe = crtc->pipe; |
9157 | int fourcc, pixel_format; | |
6761dd31 | 9158 | unsigned int aligned_height; |
bc8d7dff | 9159 | struct drm_framebuffer *fb; |
1b842c89 | 9160 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9161 | |
d9806c9f | 9162 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9163 | if (!intel_fb) { |
bc8d7dff DL |
9164 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9165 | return; | |
9166 | } | |
9167 | ||
1b842c89 DL |
9168 | fb = &intel_fb->base; |
9169 | ||
bc8d7dff | 9170 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9171 | if (!(val & PLANE_CTL_ENABLE)) |
9172 | goto error; | |
9173 | ||
bc8d7dff DL |
9174 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9175 | fourcc = skl_format_to_fourcc(pixel_format, | |
9176 | val & PLANE_CTL_ORDER_RGBX, | |
9177 | val & PLANE_CTL_ALPHA_MASK); | |
9178 | fb->pixel_format = fourcc; | |
9179 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9180 | ||
40f46283 DL |
9181 | tiling = val & PLANE_CTL_TILED_MASK; |
9182 | switch (tiling) { | |
9183 | case PLANE_CTL_TILED_LINEAR: | |
9184 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9185 | break; | |
9186 | case PLANE_CTL_TILED_X: | |
9187 | plane_config->tiling = I915_TILING_X; | |
9188 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9189 | break; | |
9190 | case PLANE_CTL_TILED_Y: | |
9191 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9192 | break; | |
9193 | case PLANE_CTL_TILED_YF: | |
9194 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9195 | break; | |
9196 | default: | |
9197 | MISSING_CASE(tiling); | |
9198 | goto error; | |
9199 | } | |
9200 | ||
bc8d7dff DL |
9201 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9202 | plane_config->base = base; | |
9203 | ||
9204 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9205 | ||
9206 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9207 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9208 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9209 | ||
9210 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9211 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9212 | fb->pixel_format); |
bc8d7dff DL |
9213 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9214 | ||
9215 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9216 | fb->pixel_format, |
9217 | fb->modifier[0]); | |
bc8d7dff | 9218 | |
f37b5c2b | 9219 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9220 | |
9221 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9222 | pipe_name(pipe), fb->width, fb->height, | |
9223 | fb->bits_per_pixel, base, fb->pitches[0], | |
9224 | plane_config->size); | |
9225 | ||
2d14030b | 9226 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9227 | return; |
9228 | ||
9229 | error: | |
9230 | kfree(fb); | |
9231 | } | |
9232 | ||
2fa2fe9a | 9233 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9234 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9235 | { |
9236 | struct drm_device *dev = crtc->base.dev; | |
9237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9238 | uint32_t tmp; | |
9239 | ||
9240 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9241 | ||
9242 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9243 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9244 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9245 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9246 | |
9247 | /* We currently do not free assignements of panel fitters on | |
9248 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9249 | * differentiates them) so just WARN about this case for now. */ | |
9250 | if (IS_GEN7(dev)) { | |
9251 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9252 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9253 | } | |
2fa2fe9a | 9254 | } |
79e53945 JB |
9255 | } |
9256 | ||
5724dbd1 DL |
9257 | static void |
9258 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9259 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9260 | { |
9261 | struct drm_device *dev = crtc->base.dev; | |
9262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9263 | u32 val, base, offset; | |
aeee5a49 | 9264 | int pipe = crtc->pipe; |
4c6baa59 | 9265 | int fourcc, pixel_format; |
6761dd31 | 9266 | unsigned int aligned_height; |
b113d5ee | 9267 | struct drm_framebuffer *fb; |
1b842c89 | 9268 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9269 | |
42a7b088 DL |
9270 | val = I915_READ(DSPCNTR(pipe)); |
9271 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9272 | return; | |
9273 | ||
d9806c9f | 9274 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9275 | if (!intel_fb) { |
4c6baa59 JB |
9276 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9277 | return; | |
9278 | } | |
9279 | ||
1b842c89 DL |
9280 | fb = &intel_fb->base; |
9281 | ||
18c5247e DV |
9282 | if (INTEL_INFO(dev)->gen >= 4) { |
9283 | if (val & DISPPLANE_TILED) { | |
49af449b | 9284 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9285 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9286 | } | |
9287 | } | |
4c6baa59 JB |
9288 | |
9289 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9290 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9291 | fb->pixel_format = fourcc; |
9292 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9293 | |
aeee5a49 | 9294 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9295 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9296 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9297 | } else { |
49af449b | 9298 | if (plane_config->tiling) |
aeee5a49 | 9299 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9300 | else |
aeee5a49 | 9301 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9302 | } |
9303 | plane_config->base = base; | |
9304 | ||
9305 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9306 | fb->width = ((val >> 16) & 0xfff) + 1; |
9307 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9308 | |
9309 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9310 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9311 | |
b113d5ee | 9312 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9313 | fb->pixel_format, |
9314 | fb->modifier[0]); | |
4c6baa59 | 9315 | |
f37b5c2b | 9316 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9317 | |
2844a921 DL |
9318 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9319 | pipe_name(pipe), fb->width, fb->height, | |
9320 | fb->bits_per_pixel, base, fb->pitches[0], | |
9321 | plane_config->size); | |
b113d5ee | 9322 | |
2d14030b | 9323 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9324 | } |
9325 | ||
0e8ffe1b | 9326 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9327 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9328 | { |
9329 | struct drm_device *dev = crtc->base.dev; | |
9330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9331 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9332 | uint32_t tmp; |
1729050e | 9333 | bool ret; |
0e8ffe1b | 9334 | |
1729050e ID |
9335 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9336 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9337 | return false; |
9338 | ||
e143a21c | 9339 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9340 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9341 | |
1729050e | 9342 | ret = false; |
0e8ffe1b DV |
9343 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9344 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9345 | goto out; |
0e8ffe1b | 9346 | |
42571aef VS |
9347 | switch (tmp & PIPECONF_BPC_MASK) { |
9348 | case PIPECONF_6BPC: | |
9349 | pipe_config->pipe_bpp = 18; | |
9350 | break; | |
9351 | case PIPECONF_8BPC: | |
9352 | pipe_config->pipe_bpp = 24; | |
9353 | break; | |
9354 | case PIPECONF_10BPC: | |
9355 | pipe_config->pipe_bpp = 30; | |
9356 | break; | |
9357 | case PIPECONF_12BPC: | |
9358 | pipe_config->pipe_bpp = 36; | |
9359 | break; | |
9360 | default: | |
9361 | break; | |
9362 | } | |
9363 | ||
b5a9fa09 DV |
9364 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9365 | pipe_config->limited_color_range = true; | |
9366 | ||
ab9412ba | 9367 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9368 | struct intel_shared_dpll *pll; |
9369 | ||
88adfff1 DV |
9370 | pipe_config->has_pch_encoder = true; |
9371 | ||
627eb5a3 DV |
9372 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9373 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9374 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9375 | |
9376 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9377 | |
c0d43d62 | 9378 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9379 | pipe_config->shared_dpll = |
9380 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9381 | } else { |
9382 | tmp = I915_READ(PCH_DPLL_SEL); | |
9383 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9384 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9385 | else | |
9386 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9387 | } | |
66e985c0 DV |
9388 | |
9389 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9390 | ||
9391 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9392 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9393 | |
9394 | tmp = pipe_config->dpll_hw_state.dpll; | |
9395 | pipe_config->pixel_multiplier = | |
9396 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9397 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9398 | |
9399 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9400 | } else { |
9401 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9402 | } |
9403 | ||
1bd1bd80 DV |
9404 | intel_get_pipe_timings(crtc, pipe_config); |
9405 | ||
2fa2fe9a DV |
9406 | ironlake_get_pfit_config(crtc, pipe_config); |
9407 | ||
1729050e ID |
9408 | ret = true; |
9409 | ||
9410 | out: | |
9411 | intel_display_power_put(dev_priv, power_domain); | |
9412 | ||
9413 | return ret; | |
0e8ffe1b DV |
9414 | } |
9415 | ||
be256dc7 PZ |
9416 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9417 | { | |
9418 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9419 | struct intel_crtc *crtc; |
be256dc7 | 9420 | |
d3fcc808 | 9421 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9422 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9423 | pipe_name(crtc->pipe)); |
9424 | ||
e2c719b7 RC |
9425 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9426 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9427 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9428 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9429 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9430 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9431 | "CPU PWM1 enabled\n"); |
c5107b87 | 9432 | if (IS_HASWELL(dev)) |
e2c719b7 | 9433 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9434 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9435 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9436 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9437 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9438 | "Utility pin enabled\n"); |
e2c719b7 | 9439 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9440 | |
9926ada1 PZ |
9441 | /* |
9442 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9443 | * interrupts remain enabled. We used to check for that, but since it's | |
9444 | * gen-specific and since we only disable LCPLL after we fully disable | |
9445 | * the interrupts, the check below should be enough. | |
9446 | */ | |
e2c719b7 | 9447 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9448 | } |
9449 | ||
9ccd5aeb PZ |
9450 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9451 | { | |
9452 | struct drm_device *dev = dev_priv->dev; | |
9453 | ||
9454 | if (IS_HASWELL(dev)) | |
9455 | return I915_READ(D_COMP_HSW); | |
9456 | else | |
9457 | return I915_READ(D_COMP_BDW); | |
9458 | } | |
9459 | ||
3c4c9b81 PZ |
9460 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9461 | { | |
9462 | struct drm_device *dev = dev_priv->dev; | |
9463 | ||
9464 | if (IS_HASWELL(dev)) { | |
9465 | mutex_lock(&dev_priv->rps.hw_lock); | |
9466 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9467 | val)) | |
f475dadf | 9468 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9469 | mutex_unlock(&dev_priv->rps.hw_lock); |
9470 | } else { | |
9ccd5aeb PZ |
9471 | I915_WRITE(D_COMP_BDW, val); |
9472 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9473 | } |
be256dc7 PZ |
9474 | } |
9475 | ||
9476 | /* | |
9477 | * This function implements pieces of two sequences from BSpec: | |
9478 | * - Sequence for display software to disable LCPLL | |
9479 | * - Sequence for display software to allow package C8+ | |
9480 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9481 | * register. Callers should take care of disabling all the display engine | |
9482 | * functions, doing the mode unset, fixing interrupts, etc. | |
9483 | */ | |
6ff58d53 PZ |
9484 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9485 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9486 | { |
9487 | uint32_t val; | |
9488 | ||
9489 | assert_can_disable_lcpll(dev_priv); | |
9490 | ||
9491 | val = I915_READ(LCPLL_CTL); | |
9492 | ||
9493 | if (switch_to_fclk) { | |
9494 | val |= LCPLL_CD_SOURCE_FCLK; | |
9495 | I915_WRITE(LCPLL_CTL, val); | |
9496 | ||
9497 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9498 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9499 | DRM_ERROR("Switching to FCLK failed\n"); | |
9500 | ||
9501 | val = I915_READ(LCPLL_CTL); | |
9502 | } | |
9503 | ||
9504 | val |= LCPLL_PLL_DISABLE; | |
9505 | I915_WRITE(LCPLL_CTL, val); | |
9506 | POSTING_READ(LCPLL_CTL); | |
9507 | ||
9508 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9509 | DRM_ERROR("LCPLL still locked\n"); | |
9510 | ||
9ccd5aeb | 9511 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9512 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9513 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9514 | ndelay(100); |
9515 | ||
9ccd5aeb PZ |
9516 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9517 | 1)) | |
be256dc7 PZ |
9518 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9519 | ||
9520 | if (allow_power_down) { | |
9521 | val = I915_READ(LCPLL_CTL); | |
9522 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9523 | I915_WRITE(LCPLL_CTL, val); | |
9524 | POSTING_READ(LCPLL_CTL); | |
9525 | } | |
9526 | } | |
9527 | ||
9528 | /* | |
9529 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9530 | * source. | |
9531 | */ | |
6ff58d53 | 9532 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9533 | { |
9534 | uint32_t val; | |
9535 | ||
9536 | val = I915_READ(LCPLL_CTL); | |
9537 | ||
9538 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9539 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9540 | return; | |
9541 | ||
a8a8bd54 PZ |
9542 | /* |
9543 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9544 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9545 | */ |
59bad947 | 9546 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9547 | |
be256dc7 PZ |
9548 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9549 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9550 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9551 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9552 | } |
9553 | ||
9ccd5aeb | 9554 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9555 | val |= D_COMP_COMP_FORCE; |
9556 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9557 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9558 | |
9559 | val = I915_READ(LCPLL_CTL); | |
9560 | val &= ~LCPLL_PLL_DISABLE; | |
9561 | I915_WRITE(LCPLL_CTL, val); | |
9562 | ||
9563 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9564 | DRM_ERROR("LCPLL not locked yet\n"); | |
9565 | ||
9566 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9567 | val = I915_READ(LCPLL_CTL); | |
9568 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9569 | I915_WRITE(LCPLL_CTL, val); | |
9570 | ||
9571 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9572 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9573 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9574 | } | |
215733fa | 9575 | |
59bad947 | 9576 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9577 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9578 | } |
9579 | ||
765dab67 PZ |
9580 | /* |
9581 | * Package states C8 and deeper are really deep PC states that can only be | |
9582 | * reached when all the devices on the system allow it, so even if the graphics | |
9583 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9584 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9585 | * | |
9586 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9587 | * well is disabled and most interrupts are disabled, and these are also | |
9588 | * requirements for runtime PM. When these conditions are met, we manually do | |
9589 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9590 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9591 | * hang the machine. | |
9592 | * | |
9593 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9594 | * the state of some registers, so when we come back from PC8+ we need to | |
9595 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9596 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9597 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9598 | * because of the runtime PM support). | |
9599 | * | |
9600 | * For more, read "Display Sequences for Package C8" on the hardware | |
9601 | * documentation. | |
9602 | */ | |
a14cb6fc | 9603 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9604 | { |
c67a470b PZ |
9605 | struct drm_device *dev = dev_priv->dev; |
9606 | uint32_t val; | |
9607 | ||
c67a470b PZ |
9608 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9609 | ||
c2699524 | 9610 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9611 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9612 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9613 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9614 | } | |
9615 | ||
9616 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9617 | hsw_disable_lcpll(dev_priv, true, true); |
9618 | } | |
9619 | ||
a14cb6fc | 9620 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9621 | { |
9622 | struct drm_device *dev = dev_priv->dev; | |
9623 | uint32_t val; | |
9624 | ||
c67a470b PZ |
9625 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9626 | ||
9627 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9628 | lpt_init_pch_refclk(dev); |
9629 | ||
c2699524 | 9630 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9631 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9632 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9633 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9634 | } | |
c67a470b PZ |
9635 | } |
9636 | ||
27c329ed | 9637 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9638 | { |
a821fc46 | 9639 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9640 | struct intel_atomic_state *old_intel_state = |
9641 | to_intel_atomic_state(old_state); | |
9642 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9643 | |
27c329ed | 9644 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9645 | } |
9646 | ||
b432e5cf | 9647 | /* compute the max rate for new configuration */ |
27c329ed | 9648 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9649 | { |
565602d7 ML |
9650 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9651 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9652 | struct drm_crtc *crtc; | |
9653 | struct drm_crtc_state *cstate; | |
27c329ed | 9654 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9655 | unsigned max_pixel_rate = 0, i; |
9656 | enum pipe pipe; | |
b432e5cf | 9657 | |
565602d7 ML |
9658 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9659 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9660 | |
565602d7 ML |
9661 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9662 | int pixel_rate; | |
27c329ed | 9663 | |
565602d7 ML |
9664 | crtc_state = to_intel_crtc_state(cstate); |
9665 | if (!crtc_state->base.enable) { | |
9666 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9667 | continue; |
565602d7 | 9668 | } |
b432e5cf | 9669 | |
27c329ed | 9670 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9671 | |
9672 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9673 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9674 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9675 | ||
565602d7 | 9676 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9677 | } |
9678 | ||
565602d7 ML |
9679 | for_each_pipe(dev_priv, pipe) |
9680 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9681 | ||
b432e5cf VS |
9682 | return max_pixel_rate; |
9683 | } | |
9684 | ||
9685 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9686 | { | |
9687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9688 | uint32_t val, data; | |
9689 | int ret; | |
9690 | ||
9691 | if (WARN((I915_READ(LCPLL_CTL) & | |
9692 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9693 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9694 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9695 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9696 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9697 | return; | |
9698 | ||
9699 | mutex_lock(&dev_priv->rps.hw_lock); | |
9700 | ret = sandybridge_pcode_write(dev_priv, | |
9701 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9702 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9703 | if (ret) { | |
9704 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9705 | return; | |
9706 | } | |
9707 | ||
9708 | val = I915_READ(LCPLL_CTL); | |
9709 | val |= LCPLL_CD_SOURCE_FCLK; | |
9710 | I915_WRITE(LCPLL_CTL, val); | |
9711 | ||
9712 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9713 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9714 | DRM_ERROR("Switching to FCLK failed\n"); | |
9715 | ||
9716 | val = I915_READ(LCPLL_CTL); | |
9717 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9718 | ||
9719 | switch (cdclk) { | |
9720 | case 450000: | |
9721 | val |= LCPLL_CLK_FREQ_450; | |
9722 | data = 0; | |
9723 | break; | |
9724 | case 540000: | |
9725 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9726 | data = 1; | |
9727 | break; | |
9728 | case 337500: | |
9729 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9730 | data = 2; | |
9731 | break; | |
9732 | case 675000: | |
9733 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9734 | data = 3; | |
9735 | break; | |
9736 | default: | |
9737 | WARN(1, "invalid cdclk frequency\n"); | |
9738 | return; | |
9739 | } | |
9740 | ||
9741 | I915_WRITE(LCPLL_CTL, val); | |
9742 | ||
9743 | val = I915_READ(LCPLL_CTL); | |
9744 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9745 | I915_WRITE(LCPLL_CTL, val); | |
9746 | ||
9747 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9748 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9749 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9750 | ||
9751 | mutex_lock(&dev_priv->rps.hw_lock); | |
9752 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9753 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9754 | ||
9755 | intel_update_cdclk(dev); | |
9756 | ||
9757 | WARN(cdclk != dev_priv->cdclk_freq, | |
9758 | "cdclk requested %d kHz but got %d kHz\n", | |
9759 | cdclk, dev_priv->cdclk_freq); | |
9760 | } | |
9761 | ||
27c329ed | 9762 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9763 | { |
27c329ed | 9764 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9765 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9766 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9767 | int cdclk; |
9768 | ||
9769 | /* | |
9770 | * FIXME should also account for plane ratio | |
9771 | * once 64bpp pixel formats are supported. | |
9772 | */ | |
27c329ed | 9773 | if (max_pixclk > 540000) |
b432e5cf | 9774 | cdclk = 675000; |
27c329ed | 9775 | else if (max_pixclk > 450000) |
b432e5cf | 9776 | cdclk = 540000; |
27c329ed | 9777 | else if (max_pixclk > 337500) |
b432e5cf VS |
9778 | cdclk = 450000; |
9779 | else | |
9780 | cdclk = 337500; | |
9781 | ||
b432e5cf | 9782 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9783 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9784 | cdclk, dev_priv->max_cdclk_freq); | |
9785 | return -EINVAL; | |
b432e5cf VS |
9786 | } |
9787 | ||
1a617b77 ML |
9788 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9789 | if (!intel_state->active_crtcs) | |
9790 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9791 | |
9792 | return 0; | |
9793 | } | |
9794 | ||
27c329ed | 9795 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9796 | { |
27c329ed | 9797 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9798 | struct intel_atomic_state *old_intel_state = |
9799 | to_intel_atomic_state(old_state); | |
9800 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9801 | |
27c329ed | 9802 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9803 | } |
9804 | ||
190f68c5 ACO |
9805 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9806 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9807 | { |
af3997b5 MK |
9808 | struct intel_encoder *intel_encoder = |
9809 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9810 | ||
9811 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9812 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9813 | return -EINVAL; | |
9814 | } | |
716c2e55 | 9815 | |
c7653199 | 9816 | crtc->lowfreq_avail = false; |
644cef34 | 9817 | |
c8f7a0db | 9818 | return 0; |
79e53945 JB |
9819 | } |
9820 | ||
3760b59c S |
9821 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9822 | enum port port, | |
9823 | struct intel_crtc_state *pipe_config) | |
9824 | { | |
9825 | switch (port) { | |
9826 | case PORT_A: | |
9827 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9828 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9829 | break; | |
9830 | case PORT_B: | |
9831 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9832 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9833 | break; | |
9834 | case PORT_C: | |
9835 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9836 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9837 | break; | |
9838 | default: | |
9839 | DRM_ERROR("Incorrect port type\n"); | |
9840 | } | |
9841 | } | |
9842 | ||
96b7dfb7 S |
9843 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9844 | enum port port, | |
5cec258b | 9845 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9846 | { |
3148ade7 | 9847 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9848 | |
9849 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9850 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9851 | ||
9852 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9853 | case SKL_DPLL0: |
9854 | /* | |
9855 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9856 | * of the shared DPLL framework and thus needs to be read out | |
9857 | * separately | |
9858 | */ | |
9859 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9860 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9861 | break; | |
96b7dfb7 S |
9862 | case SKL_DPLL1: |
9863 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9864 | break; | |
9865 | case SKL_DPLL2: | |
9866 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9867 | break; | |
9868 | case SKL_DPLL3: | |
9869 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9870 | break; | |
96b7dfb7 S |
9871 | } |
9872 | } | |
9873 | ||
7d2c8175 DL |
9874 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9875 | enum port port, | |
5cec258b | 9876 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9877 | { |
9878 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9879 | ||
9880 | switch (pipe_config->ddi_pll_sel) { | |
9881 | case PORT_CLK_SEL_WRPLL1: | |
9882 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9883 | break; | |
9884 | case PORT_CLK_SEL_WRPLL2: | |
9885 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9886 | break; | |
00490c22 ML |
9887 | case PORT_CLK_SEL_SPLL: |
9888 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9889 | break; |
7d2c8175 DL |
9890 | } |
9891 | } | |
9892 | ||
26804afd | 9893 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9894 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9895 | { |
9896 | struct drm_device *dev = crtc->base.dev; | |
9897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9898 | struct intel_shared_dpll *pll; |
26804afd DV |
9899 | enum port port; |
9900 | uint32_t tmp; | |
9901 | ||
9902 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9903 | ||
9904 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9905 | ||
ef11bdb3 | 9906 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9907 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9908 | else if (IS_BROXTON(dev)) |
9909 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9910 | else |
9911 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9912 | |
d452c5b6 DV |
9913 | if (pipe_config->shared_dpll >= 0) { |
9914 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9915 | ||
9916 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9917 | &pipe_config->dpll_hw_state)); | |
9918 | } | |
9919 | ||
26804afd DV |
9920 | /* |
9921 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9922 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9923 | * the PCH transcoder is on. | |
9924 | */ | |
ca370455 DL |
9925 | if (INTEL_INFO(dev)->gen < 9 && |
9926 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9927 | pipe_config->has_pch_encoder = true; |
9928 | ||
9929 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9930 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9931 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9932 | ||
9933 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9934 | } | |
9935 | } | |
9936 | ||
0e8ffe1b | 9937 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9938 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9939 | { |
9940 | struct drm_device *dev = crtc->base.dev; | |
9941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9942 | enum intel_display_power_domain power_domain; |
9943 | unsigned long power_domain_mask; | |
0e8ffe1b | 9944 | uint32_t tmp; |
1729050e | 9945 | bool ret; |
0e8ffe1b | 9946 | |
1729050e ID |
9947 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9948 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9949 | return false; |
1729050e ID |
9950 | power_domain_mask = BIT(power_domain); |
9951 | ||
9952 | ret = false; | |
b5482bd0 | 9953 | |
e143a21c | 9954 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9955 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9956 | ||
eccb140b DV |
9957 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9958 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9959 | enum pipe trans_edp_pipe; | |
9960 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9961 | default: | |
9962 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9963 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9964 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9965 | trans_edp_pipe = PIPE_A; | |
9966 | break; | |
9967 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9968 | trans_edp_pipe = PIPE_B; | |
9969 | break; | |
9970 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9971 | trans_edp_pipe = PIPE_C; | |
9972 | break; | |
9973 | } | |
9974 | ||
9975 | if (trans_edp_pipe == crtc->pipe) | |
9976 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9977 | } | |
9978 | ||
1729050e ID |
9979 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
9980 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9981 | goto out; | |
9982 | power_domain_mask |= BIT(power_domain); | |
2bfce950 | 9983 | |
eccb140b | 9984 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b | 9985 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 9986 | goto out; |
0e8ffe1b | 9987 | |
26804afd | 9988 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9989 | |
1bd1bd80 DV |
9990 | intel_get_pipe_timings(crtc, pipe_config); |
9991 | ||
a1b2278e CK |
9992 | if (INTEL_INFO(dev)->gen >= 9) { |
9993 | skl_init_scalers(dev, crtc, pipe_config); | |
9994 | } | |
9995 | ||
af99ceda CK |
9996 | if (INTEL_INFO(dev)->gen >= 9) { |
9997 | pipe_config->scaler_state.scaler_id = -1; | |
9998 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9999 | } | |
10000 | ||
1729050e ID |
10001 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10002 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10003 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10004 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10005 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10006 | else |
1c132b44 | 10007 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10008 | } |
88adfff1 | 10009 | |
e59150dc JB |
10010 | if (IS_HASWELL(dev)) |
10011 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10012 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10013 | |
ebb69c95 CT |
10014 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10015 | pipe_config->pixel_multiplier = | |
10016 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10017 | } else { | |
10018 | pipe_config->pixel_multiplier = 1; | |
10019 | } | |
6c49f241 | 10020 | |
1729050e ID |
10021 | ret = true; |
10022 | ||
10023 | out: | |
10024 | for_each_power_domain(power_domain, power_domain_mask) | |
10025 | intel_display_power_put(dev_priv, power_domain); | |
10026 | ||
10027 | return ret; | |
0e8ffe1b DV |
10028 | } |
10029 | ||
55a08b3f ML |
10030 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10031 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10032 | { |
10033 | struct drm_device *dev = crtc->dev; | |
10034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10036 | uint32_t cntl = 0, size = 0; |
560b85bb | 10037 | |
55a08b3f ML |
10038 | if (plane_state && plane_state->visible) { |
10039 | unsigned int width = plane_state->base.crtc_w; | |
10040 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10041 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10042 | ||
10043 | switch (stride) { | |
10044 | default: | |
10045 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10046 | width, stride); | |
10047 | stride = 256; | |
10048 | /* fallthrough */ | |
10049 | case 256: | |
10050 | case 512: | |
10051 | case 1024: | |
10052 | case 2048: | |
10053 | break; | |
4b0e333e CW |
10054 | } |
10055 | ||
dc41c154 VS |
10056 | cntl |= CURSOR_ENABLE | |
10057 | CURSOR_GAMMA_ENABLE | | |
10058 | CURSOR_FORMAT_ARGB | | |
10059 | CURSOR_STRIDE(stride); | |
10060 | ||
10061 | size = (height << 12) | width; | |
4b0e333e | 10062 | } |
560b85bb | 10063 | |
dc41c154 VS |
10064 | if (intel_crtc->cursor_cntl != 0 && |
10065 | (intel_crtc->cursor_base != base || | |
10066 | intel_crtc->cursor_size != size || | |
10067 | intel_crtc->cursor_cntl != cntl)) { | |
10068 | /* On these chipsets we can only modify the base/size/stride | |
10069 | * whilst the cursor is disabled. | |
10070 | */ | |
0b87c24e VS |
10071 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10072 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10073 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10074 | } |
560b85bb | 10075 | |
99d1f387 | 10076 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10077 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10078 | intel_crtc->cursor_base = base; |
10079 | } | |
4726e0b0 | 10080 | |
dc41c154 VS |
10081 | if (intel_crtc->cursor_size != size) { |
10082 | I915_WRITE(CURSIZE, size); | |
10083 | intel_crtc->cursor_size = size; | |
4b0e333e | 10084 | } |
560b85bb | 10085 | |
4b0e333e | 10086 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10087 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10088 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10089 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10090 | } |
560b85bb CW |
10091 | } |
10092 | ||
55a08b3f ML |
10093 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10094 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10095 | { |
10096 | struct drm_device *dev = crtc->dev; | |
10097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10099 | int pipe = intel_crtc->pipe; | |
663f3122 | 10100 | uint32_t cntl = 0; |
4b0e333e | 10101 | |
55a08b3f | 10102 | if (plane_state && plane_state->visible) { |
4b0e333e | 10103 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10104 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10105 | case 64: |
10106 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10107 | break; | |
10108 | case 128: | |
10109 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10110 | break; | |
10111 | case 256: | |
10112 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10113 | break; | |
10114 | default: | |
55a08b3f | 10115 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10116 | return; |
65a21cd6 | 10117 | } |
4b0e333e | 10118 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10119 | |
fc6f93bc | 10120 | if (HAS_DDI(dev)) |
47bf17a7 | 10121 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10122 | |
55a08b3f ML |
10123 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10124 | cntl |= CURSOR_ROTATE_180; | |
10125 | } | |
4398ad45 | 10126 | |
4b0e333e CW |
10127 | if (intel_crtc->cursor_cntl != cntl) { |
10128 | I915_WRITE(CURCNTR(pipe), cntl); | |
10129 | POSTING_READ(CURCNTR(pipe)); | |
10130 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10131 | } |
4b0e333e | 10132 | |
65a21cd6 | 10133 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10134 | I915_WRITE(CURBASE(pipe), base); |
10135 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10136 | |
10137 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10138 | } |
10139 | ||
cda4b7d3 | 10140 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10141 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10142 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10143 | { |
10144 | struct drm_device *dev = crtc->dev; | |
10145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10147 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10148 | u32 base = intel_crtc->cursor_addr; |
10149 | u32 pos = 0; | |
cda4b7d3 | 10150 | |
55a08b3f ML |
10151 | if (plane_state) { |
10152 | int x = plane_state->base.crtc_x; | |
10153 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10154 | |
55a08b3f ML |
10155 | if (x < 0) { |
10156 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10157 | x = -x; | |
10158 | } | |
10159 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10160 | |
55a08b3f ML |
10161 | if (y < 0) { |
10162 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10163 | y = -y; | |
10164 | } | |
10165 | pos |= y << CURSOR_Y_SHIFT; | |
10166 | ||
10167 | /* ILK+ do this automagically */ | |
10168 | if (HAS_GMCH_DISPLAY(dev) && | |
10169 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10170 | base += (plane_state->base.crtc_h * | |
10171 | plane_state->base.crtc_w - 1) * 4; | |
10172 | } | |
cda4b7d3 | 10173 | } |
cda4b7d3 | 10174 | |
5efb3e28 VS |
10175 | I915_WRITE(CURPOS(pipe), pos); |
10176 | ||
8ac54669 | 10177 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10178 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10179 | else |
55a08b3f | 10180 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10181 | } |
10182 | ||
dc41c154 VS |
10183 | static bool cursor_size_ok(struct drm_device *dev, |
10184 | uint32_t width, uint32_t height) | |
10185 | { | |
10186 | if (width == 0 || height == 0) | |
10187 | return false; | |
10188 | ||
10189 | /* | |
10190 | * 845g/865g are special in that they are only limited by | |
10191 | * the width of their cursors, the height is arbitrary up to | |
10192 | * the precision of the register. Everything else requires | |
10193 | * square cursors, limited to a few power-of-two sizes. | |
10194 | */ | |
10195 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10196 | if ((width & 63) != 0) | |
10197 | return false; | |
10198 | ||
10199 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10200 | return false; | |
10201 | ||
10202 | if (height > 1023) | |
10203 | return false; | |
10204 | } else { | |
10205 | switch (width | height) { | |
10206 | case 256: | |
10207 | case 128: | |
10208 | if (IS_GEN2(dev)) | |
10209 | return false; | |
10210 | case 64: | |
10211 | break; | |
10212 | default: | |
10213 | return false; | |
10214 | } | |
10215 | } | |
10216 | ||
10217 | return true; | |
10218 | } | |
10219 | ||
79e53945 | 10220 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10221 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10222 | { |
7203425a | 10223 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10225 | |
7203425a | 10226 | for (i = start; i < end; i++) { |
79e53945 JB |
10227 | intel_crtc->lut_r[i] = red[i] >> 8; |
10228 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10229 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10230 | } | |
10231 | ||
10232 | intel_crtc_load_lut(crtc); | |
10233 | } | |
10234 | ||
79e53945 JB |
10235 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10236 | static struct drm_display_mode load_detect_mode = { | |
10237 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10238 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10239 | }; | |
10240 | ||
a8bb6818 DV |
10241 | struct drm_framebuffer * |
10242 | __intel_framebuffer_create(struct drm_device *dev, | |
10243 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10244 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10245 | { |
10246 | struct intel_framebuffer *intel_fb; | |
10247 | int ret; | |
10248 | ||
10249 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10250 | if (!intel_fb) |
d2dff872 | 10251 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10252 | |
10253 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10254 | if (ret) |
10255 | goto err; | |
d2dff872 CW |
10256 | |
10257 | return &intel_fb->base; | |
dcb1394e | 10258 | |
dd4916c5 | 10259 | err: |
dd4916c5 | 10260 | kfree(intel_fb); |
dd4916c5 | 10261 | return ERR_PTR(ret); |
d2dff872 CW |
10262 | } |
10263 | ||
b5ea642a | 10264 | static struct drm_framebuffer * |
a8bb6818 DV |
10265 | intel_framebuffer_create(struct drm_device *dev, |
10266 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10267 | struct drm_i915_gem_object *obj) | |
10268 | { | |
10269 | struct drm_framebuffer *fb; | |
10270 | int ret; | |
10271 | ||
10272 | ret = i915_mutex_lock_interruptible(dev); | |
10273 | if (ret) | |
10274 | return ERR_PTR(ret); | |
10275 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10276 | mutex_unlock(&dev->struct_mutex); | |
10277 | ||
10278 | return fb; | |
10279 | } | |
10280 | ||
d2dff872 CW |
10281 | static u32 |
10282 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10283 | { | |
10284 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10285 | return ALIGN(pitch, 64); | |
10286 | } | |
10287 | ||
10288 | static u32 | |
10289 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10290 | { | |
10291 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10292 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10293 | } |
10294 | ||
10295 | static struct drm_framebuffer * | |
10296 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10297 | struct drm_display_mode *mode, | |
10298 | int depth, int bpp) | |
10299 | { | |
dcb1394e | 10300 | struct drm_framebuffer *fb; |
d2dff872 | 10301 | struct drm_i915_gem_object *obj; |
0fed39bd | 10302 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10303 | |
10304 | obj = i915_gem_alloc_object(dev, | |
10305 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10306 | if (obj == NULL) | |
10307 | return ERR_PTR(-ENOMEM); | |
10308 | ||
10309 | mode_cmd.width = mode->hdisplay; | |
10310 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10311 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10312 | bpp); | |
5ca0c34a | 10313 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10314 | |
dcb1394e LW |
10315 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10316 | if (IS_ERR(fb)) | |
10317 | drm_gem_object_unreference_unlocked(&obj->base); | |
10318 | ||
10319 | return fb; | |
d2dff872 CW |
10320 | } |
10321 | ||
10322 | static struct drm_framebuffer * | |
10323 | mode_fits_in_fbdev(struct drm_device *dev, | |
10324 | struct drm_display_mode *mode) | |
10325 | { | |
0695726e | 10326 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10327 | struct drm_i915_private *dev_priv = dev->dev_private; |
10328 | struct drm_i915_gem_object *obj; | |
10329 | struct drm_framebuffer *fb; | |
10330 | ||
4c0e5528 | 10331 | if (!dev_priv->fbdev) |
d2dff872 CW |
10332 | return NULL; |
10333 | ||
4c0e5528 | 10334 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10335 | return NULL; |
10336 | ||
4c0e5528 DV |
10337 | obj = dev_priv->fbdev->fb->obj; |
10338 | BUG_ON(!obj); | |
10339 | ||
8bcd4553 | 10340 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10341 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10342 | fb->bits_per_pixel)) | |
d2dff872 CW |
10343 | return NULL; |
10344 | ||
01f2c773 | 10345 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10346 | return NULL; |
10347 | ||
edde3617 | 10348 | drm_framebuffer_reference(fb); |
d2dff872 | 10349 | return fb; |
4520f53a DV |
10350 | #else |
10351 | return NULL; | |
10352 | #endif | |
d2dff872 CW |
10353 | } |
10354 | ||
d3a40d1b ACO |
10355 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10356 | struct drm_crtc *crtc, | |
10357 | struct drm_display_mode *mode, | |
10358 | struct drm_framebuffer *fb, | |
10359 | int x, int y) | |
10360 | { | |
10361 | struct drm_plane_state *plane_state; | |
10362 | int hdisplay, vdisplay; | |
10363 | int ret; | |
10364 | ||
10365 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10366 | if (IS_ERR(plane_state)) | |
10367 | return PTR_ERR(plane_state); | |
10368 | ||
10369 | if (mode) | |
10370 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10371 | else | |
10372 | hdisplay = vdisplay = 0; | |
10373 | ||
10374 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10375 | if (ret) | |
10376 | return ret; | |
10377 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10378 | plane_state->crtc_x = 0; | |
10379 | plane_state->crtc_y = 0; | |
10380 | plane_state->crtc_w = hdisplay; | |
10381 | plane_state->crtc_h = vdisplay; | |
10382 | plane_state->src_x = x << 16; | |
10383 | plane_state->src_y = y << 16; | |
10384 | plane_state->src_w = hdisplay << 16; | |
10385 | plane_state->src_h = vdisplay << 16; | |
10386 | ||
10387 | return 0; | |
10388 | } | |
10389 | ||
d2434ab7 | 10390 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10391 | struct drm_display_mode *mode, |
51fd371b RC |
10392 | struct intel_load_detect_pipe *old, |
10393 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10394 | { |
10395 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10396 | struct intel_encoder *intel_encoder = |
10397 | intel_attached_encoder(connector); | |
79e53945 | 10398 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10399 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10400 | struct drm_crtc *crtc = NULL; |
10401 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10402 | struct drm_framebuffer *fb; |
51fd371b | 10403 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10404 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10405 | struct drm_connector_state *connector_state; |
4be07317 | 10406 | struct intel_crtc_state *crtc_state; |
51fd371b | 10407 | int ret, i = -1; |
79e53945 | 10408 | |
d2dff872 | 10409 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10410 | connector->base.id, connector->name, |
8e329a03 | 10411 | encoder->base.id, encoder->name); |
d2dff872 | 10412 | |
edde3617 ML |
10413 | old->restore_state = NULL; |
10414 | ||
51fd371b RC |
10415 | retry: |
10416 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10417 | if (ret) | |
ad3c558f | 10418 | goto fail; |
6e9f798d | 10419 | |
79e53945 JB |
10420 | /* |
10421 | * Algorithm gets a little messy: | |
7a5e4805 | 10422 | * |
79e53945 JB |
10423 | * - if the connector already has an assigned crtc, use it (but make |
10424 | * sure it's on first) | |
7a5e4805 | 10425 | * |
79e53945 JB |
10426 | * - try to find the first unused crtc that can drive this connector, |
10427 | * and use that if we find one | |
79e53945 JB |
10428 | */ |
10429 | ||
10430 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10431 | if (connector->state->crtc) { |
10432 | crtc = connector->state->crtc; | |
8261b191 | 10433 | |
51fd371b | 10434 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10435 | if (ret) |
ad3c558f | 10436 | goto fail; |
8261b191 CW |
10437 | |
10438 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10439 | goto found; |
79e53945 JB |
10440 | } |
10441 | ||
10442 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10443 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10444 | i++; |
10445 | if (!(encoder->possible_crtcs & (1 << i))) | |
10446 | continue; | |
edde3617 ML |
10447 | |
10448 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10449 | if (ret) | |
10450 | goto fail; | |
10451 | ||
10452 | if (possible_crtc->state->enable) { | |
10453 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10454 | continue; |
edde3617 | 10455 | } |
a459249c VS |
10456 | |
10457 | crtc = possible_crtc; | |
10458 | break; | |
79e53945 JB |
10459 | } |
10460 | ||
10461 | /* | |
10462 | * If we didn't find an unused CRTC, don't use any. | |
10463 | */ | |
10464 | if (!crtc) { | |
7173188d | 10465 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10466 | goto fail; |
79e53945 JB |
10467 | } |
10468 | ||
edde3617 ML |
10469 | found: |
10470 | intel_crtc = to_intel_crtc(crtc); | |
10471 | ||
4d02e2de DV |
10472 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10473 | if (ret) | |
ad3c558f | 10474 | goto fail; |
79e53945 | 10475 | |
83a57153 | 10476 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10477 | restore_state = drm_atomic_state_alloc(dev); |
10478 | if (!state || !restore_state) { | |
10479 | ret = -ENOMEM; | |
10480 | goto fail; | |
10481 | } | |
83a57153 ACO |
10482 | |
10483 | state->acquire_ctx = ctx; | |
edde3617 | 10484 | restore_state->acquire_ctx = ctx; |
83a57153 | 10485 | |
944b0c76 ACO |
10486 | connector_state = drm_atomic_get_connector_state(state, connector); |
10487 | if (IS_ERR(connector_state)) { | |
10488 | ret = PTR_ERR(connector_state); | |
10489 | goto fail; | |
10490 | } | |
10491 | ||
edde3617 ML |
10492 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10493 | if (ret) | |
10494 | goto fail; | |
944b0c76 | 10495 | |
4be07317 ACO |
10496 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10497 | if (IS_ERR(crtc_state)) { | |
10498 | ret = PTR_ERR(crtc_state); | |
10499 | goto fail; | |
10500 | } | |
10501 | ||
49d6fa21 | 10502 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10503 | |
6492711d CW |
10504 | if (!mode) |
10505 | mode = &load_detect_mode; | |
79e53945 | 10506 | |
d2dff872 CW |
10507 | /* We need a framebuffer large enough to accommodate all accesses |
10508 | * that the plane may generate whilst we perform load detection. | |
10509 | * We can not rely on the fbcon either being present (we get called | |
10510 | * during its initialisation to detect all boot displays, or it may | |
10511 | * not even exist) or that it is large enough to satisfy the | |
10512 | * requested mode. | |
10513 | */ | |
94352cf9 DV |
10514 | fb = mode_fits_in_fbdev(dev, mode); |
10515 | if (fb == NULL) { | |
d2dff872 | 10516 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10517 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10518 | } else |
10519 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10520 | if (IS_ERR(fb)) { |
d2dff872 | 10521 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10522 | goto fail; |
79e53945 | 10523 | } |
79e53945 | 10524 | |
d3a40d1b ACO |
10525 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10526 | if (ret) | |
10527 | goto fail; | |
10528 | ||
edde3617 ML |
10529 | drm_framebuffer_unreference(fb); |
10530 | ||
10531 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10532 | if (ret) | |
10533 | goto fail; | |
10534 | ||
10535 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10536 | if (!ret) | |
10537 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10538 | if (!ret) | |
10539 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10540 | if (ret) { | |
10541 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10542 | goto fail; | |
10543 | } | |
8c7b5ccb | 10544 | |
74c090b1 | 10545 | if (drm_atomic_commit(state)) { |
6492711d | 10546 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10547 | goto fail; |
79e53945 | 10548 | } |
edde3617 ML |
10549 | |
10550 | old->restore_state = restore_state; | |
7173188d | 10551 | |
79e53945 | 10552 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10553 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10554 | return true; |
412b61d8 | 10555 | |
ad3c558f | 10556 | fail: |
e5d958ef | 10557 | drm_atomic_state_free(state); |
edde3617 ML |
10558 | drm_atomic_state_free(restore_state); |
10559 | restore_state = state = NULL; | |
83a57153 | 10560 | |
51fd371b RC |
10561 | if (ret == -EDEADLK) { |
10562 | drm_modeset_backoff(ctx); | |
10563 | goto retry; | |
10564 | } | |
10565 | ||
412b61d8 | 10566 | return false; |
79e53945 JB |
10567 | } |
10568 | ||
d2434ab7 | 10569 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10570 | struct intel_load_detect_pipe *old, |
10571 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10572 | { |
d2434ab7 DV |
10573 | struct intel_encoder *intel_encoder = |
10574 | intel_attached_encoder(connector); | |
4ef69c7a | 10575 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10576 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10577 | int ret; |
79e53945 | 10578 | |
d2dff872 | 10579 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10580 | connector->base.id, connector->name, |
8e329a03 | 10581 | encoder->base.id, encoder->name); |
d2dff872 | 10582 | |
edde3617 | 10583 | if (!state) |
0622a53c | 10584 | return; |
79e53945 | 10585 | |
edde3617 ML |
10586 | ret = drm_atomic_commit(state); |
10587 | if (ret) { | |
10588 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10589 | drm_atomic_state_free(state); | |
10590 | } | |
79e53945 JB |
10591 | } |
10592 | ||
da4a1efa | 10593 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10594 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10595 | { |
10596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10597 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10598 | ||
10599 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10600 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10601 | else if (HAS_PCH_SPLIT(dev)) |
10602 | return 120000; | |
10603 | else if (!IS_GEN2(dev)) | |
10604 | return 96000; | |
10605 | else | |
10606 | return 48000; | |
10607 | } | |
10608 | ||
79e53945 | 10609 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10610 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10611 | struct intel_crtc_state *pipe_config) |
79e53945 | 10612 | { |
f1f644dc | 10613 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10614 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10615 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10616 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10617 | u32 fp; |
10618 | intel_clock_t clock; | |
dccbea3b | 10619 | int port_clock; |
da4a1efa | 10620 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10621 | |
10622 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10623 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10624 | else |
293623f7 | 10625 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10626 | |
10627 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10628 | if (IS_PINEVIEW(dev)) { |
10629 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10630 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10631 | } else { |
10632 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10633 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10634 | } | |
10635 | ||
a6c45cf0 | 10636 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10637 | if (IS_PINEVIEW(dev)) |
10638 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10639 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10640 | else |
10641 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10642 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10643 | ||
10644 | switch (dpll & DPLL_MODE_MASK) { | |
10645 | case DPLLB_MODE_DAC_SERIAL: | |
10646 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10647 | 5 : 10; | |
10648 | break; | |
10649 | case DPLLB_MODE_LVDS: | |
10650 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10651 | 7 : 14; | |
10652 | break; | |
10653 | default: | |
28c97730 | 10654 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10655 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10656 | return; |
79e53945 JB |
10657 | } |
10658 | ||
ac58c3f0 | 10659 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10660 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10661 | else |
dccbea3b | 10662 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10663 | } else { |
0fb58223 | 10664 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10665 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10666 | |
10667 | if (is_lvds) { | |
10668 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10669 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10670 | |
10671 | if (lvds & LVDS_CLKB_POWER_UP) | |
10672 | clock.p2 = 7; | |
10673 | else | |
10674 | clock.p2 = 14; | |
79e53945 JB |
10675 | } else { |
10676 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10677 | clock.p1 = 2; | |
10678 | else { | |
10679 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10680 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10681 | } | |
10682 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10683 | clock.p2 = 4; | |
10684 | else | |
10685 | clock.p2 = 2; | |
79e53945 | 10686 | } |
da4a1efa | 10687 | |
dccbea3b | 10688 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10689 | } |
10690 | ||
18442d08 VS |
10691 | /* |
10692 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10693 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10694 | * encoder's get_config() function. |
10695 | */ | |
dccbea3b | 10696 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10697 | } |
10698 | ||
6878da05 VS |
10699 | int intel_dotclock_calculate(int link_freq, |
10700 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10701 | { |
f1f644dc JB |
10702 | /* |
10703 | * The calculation for the data clock is: | |
1041a02f | 10704 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10705 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10706 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10707 | * |
10708 | * and the link clock is simpler: | |
1041a02f | 10709 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10710 | */ |
10711 | ||
6878da05 VS |
10712 | if (!m_n->link_n) |
10713 | return 0; | |
f1f644dc | 10714 | |
6878da05 VS |
10715 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10716 | } | |
f1f644dc | 10717 | |
18442d08 | 10718 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10719 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10720 | { |
10721 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10722 | |
18442d08 VS |
10723 | /* read out port_clock from the DPLL */ |
10724 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10725 | |
f1f644dc | 10726 | /* |
18442d08 | 10727 | * This value does not include pixel_multiplier. |
241bfc38 | 10728 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10729 | * agree once we know their relationship in the encoder's |
10730 | * get_config() function. | |
79e53945 | 10731 | */ |
2d112de7 | 10732 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10733 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10734 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10735 | } |
10736 | ||
10737 | /** Returns the currently programmed mode of the given pipe. */ | |
10738 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10739 | struct drm_crtc *crtc) | |
10740 | { | |
548f245b | 10741 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10743 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10744 | struct drm_display_mode *mode; |
3f36b937 | 10745 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10746 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10747 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10748 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10749 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10750 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10751 | |
10752 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10753 | if (!mode) | |
10754 | return NULL; | |
10755 | ||
3f36b937 TU |
10756 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10757 | if (!pipe_config) { | |
10758 | kfree(mode); | |
10759 | return NULL; | |
10760 | } | |
10761 | ||
f1f644dc JB |
10762 | /* |
10763 | * Construct a pipe_config sufficient for getting the clock info | |
10764 | * back out of crtc_clock_get. | |
10765 | * | |
10766 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10767 | * to use a real value here instead. | |
10768 | */ | |
3f36b937 TU |
10769 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10770 | pipe_config->pixel_multiplier = 1; | |
10771 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10772 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10773 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10774 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10775 | ||
10776 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10777 | mode->hdisplay = (htot & 0xffff) + 1; |
10778 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10779 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10780 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10781 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10782 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10783 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10784 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10785 | ||
10786 | drm_mode_set_name(mode); | |
79e53945 | 10787 | |
3f36b937 TU |
10788 | kfree(pipe_config); |
10789 | ||
79e53945 JB |
10790 | return mode; |
10791 | } | |
10792 | ||
f047e395 CW |
10793 | void intel_mark_busy(struct drm_device *dev) |
10794 | { | |
c67a470b PZ |
10795 | struct drm_i915_private *dev_priv = dev->dev_private; |
10796 | ||
f62a0076 CW |
10797 | if (dev_priv->mm.busy) |
10798 | return; | |
10799 | ||
43694d69 | 10800 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10801 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10802 | if (INTEL_INFO(dev)->gen >= 6) |
10803 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10804 | dev_priv->mm.busy = true; |
f047e395 CW |
10805 | } |
10806 | ||
10807 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10808 | { |
c67a470b | 10809 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10810 | |
f62a0076 CW |
10811 | if (!dev_priv->mm.busy) |
10812 | return; | |
10813 | ||
10814 | dev_priv->mm.busy = false; | |
10815 | ||
3d13ef2e | 10816 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10817 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10818 | |
43694d69 | 10819 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10820 | } |
10821 | ||
79e53945 JB |
10822 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10823 | { | |
10824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10825 | struct drm_device *dev = crtc->dev; |
10826 | struct intel_unpin_work *work; | |
67e77c5a | 10827 | |
5e2d7afc | 10828 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10829 | work = intel_crtc->unpin_work; |
10830 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10831 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10832 | |
10833 | if (work) { | |
10834 | cancel_work_sync(&work->work); | |
10835 | kfree(work); | |
10836 | } | |
79e53945 JB |
10837 | |
10838 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10839 | |
79e53945 JB |
10840 | kfree(intel_crtc); |
10841 | } | |
10842 | ||
6b95a207 KH |
10843 | static void intel_unpin_work_fn(struct work_struct *__work) |
10844 | { | |
10845 | struct intel_unpin_work *work = | |
10846 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10847 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10848 | struct drm_device *dev = crtc->base.dev; | |
10849 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10850 | |
b4a98e57 | 10851 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10852 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10853 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10854 | |
f06cc1b9 | 10855 | if (work->flip_queued_req) |
146d84f0 | 10856 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10857 | mutex_unlock(&dev->struct_mutex); |
10858 | ||
a9ff8714 | 10859 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10860 | intel_fbc_post_update(crtc); |
89ed88ba | 10861 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10862 | |
a9ff8714 VS |
10863 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10864 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10865 | |
6b95a207 KH |
10866 | kfree(work); |
10867 | } | |
10868 | ||
1afe3e9d | 10869 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10870 | struct drm_crtc *crtc) |
6b95a207 | 10871 | { |
6b95a207 KH |
10872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10873 | struct intel_unpin_work *work; | |
6b95a207 KH |
10874 | unsigned long flags; |
10875 | ||
10876 | /* Ignore early vblank irqs */ | |
10877 | if (intel_crtc == NULL) | |
10878 | return; | |
10879 | ||
f326038a DV |
10880 | /* |
10881 | * This is called both by irq handlers and the reset code (to complete | |
10882 | * lost pageflips) so needs the full irqsave spinlocks. | |
10883 | */ | |
6b95a207 KH |
10884 | spin_lock_irqsave(&dev->event_lock, flags); |
10885 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10886 | |
10887 | /* Ensure we don't miss a work->pending update ... */ | |
10888 | smp_rmb(); | |
10889 | ||
10890 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10891 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10892 | return; | |
10893 | } | |
10894 | ||
d6bbafa1 | 10895 | page_flip_completed(intel_crtc); |
0af7e4df | 10896 | |
6b95a207 | 10897 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10898 | } |
10899 | ||
1afe3e9d JB |
10900 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10901 | { | |
fbee40df | 10902 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10903 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10904 | ||
49b14a5c | 10905 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10906 | } |
10907 | ||
10908 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10909 | { | |
fbee40df | 10910 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10911 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10912 | ||
49b14a5c | 10913 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10914 | } |
10915 | ||
75f7f3ec VS |
10916 | /* Is 'a' after or equal to 'b'? */ |
10917 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10918 | { | |
10919 | return !((a - b) & 0x80000000); | |
10920 | } | |
10921 | ||
10922 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10923 | { | |
10924 | struct drm_device *dev = crtc->base.dev; | |
10925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10926 | ||
bdfa7542 VS |
10927 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10928 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10929 | return true; | |
10930 | ||
75f7f3ec VS |
10931 | /* |
10932 | * The relevant registers doen't exist on pre-ctg. | |
10933 | * As the flip done interrupt doesn't trigger for mmio | |
10934 | * flips on gmch platforms, a flip count check isn't | |
10935 | * really needed there. But since ctg has the registers, | |
10936 | * include it in the check anyway. | |
10937 | */ | |
10938 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10939 | return true; | |
10940 | ||
e8861675 ML |
10941 | /* |
10942 | * BDW signals flip done immediately if the plane | |
10943 | * is disabled, even if the plane enable is already | |
10944 | * armed to occur at the next vblank :( | |
10945 | */ | |
10946 | ||
75f7f3ec VS |
10947 | /* |
10948 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10949 | * used the same base address. In that case the mmio flip might | |
10950 | * have completed, but the CS hasn't even executed the flip yet. | |
10951 | * | |
10952 | * A flip count check isn't enough as the CS might have updated | |
10953 | * the base address just after start of vblank, but before we | |
10954 | * managed to process the interrupt. This means we'd complete the | |
10955 | * CS flip too soon. | |
10956 | * | |
10957 | * Combining both checks should get us a good enough result. It may | |
10958 | * still happen that the CS flip has been executed, but has not | |
10959 | * yet actually completed. But in case the base address is the same | |
10960 | * anyway, we don't really care. | |
10961 | */ | |
10962 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10963 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10964 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10965 | crtc->unpin_work->flip_count); |
10966 | } | |
10967 | ||
6b95a207 KH |
10968 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10969 | { | |
fbee40df | 10970 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10971 | struct intel_crtc *intel_crtc = |
10972 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10973 | unsigned long flags; | |
10974 | ||
f326038a DV |
10975 | |
10976 | /* | |
10977 | * This is called both by irq handlers and the reset code (to complete | |
10978 | * lost pageflips) so needs the full irqsave spinlocks. | |
10979 | * | |
10980 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10981 | * generate a page-flip completion irq, i.e. every modeset |
10982 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10983 | */ | |
6b95a207 | 10984 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10985 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10986 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10987 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10988 | } | |
10989 | ||
6042639c | 10990 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10991 | { |
10992 | /* Ensure that the work item is consistent when activating it ... */ | |
10993 | smp_wmb(); | |
6042639c | 10994 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10995 | /* and that it is marked active as soon as the irq could fire. */ |
10996 | smp_wmb(); | |
10997 | } | |
10998 | ||
8c9f3aaf JB |
10999 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11000 | struct drm_crtc *crtc, | |
11001 | struct drm_framebuffer *fb, | |
ed8d1975 | 11002 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11003 | struct drm_i915_gem_request *req, |
ed8d1975 | 11004 | uint32_t flags) |
8c9f3aaf | 11005 | { |
6258fbe2 | 11006 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11008 | u32 flip_mask; |
11009 | int ret; | |
11010 | ||
5fb9de1a | 11011 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11012 | if (ret) |
4fa62c89 | 11013 | return ret; |
8c9f3aaf JB |
11014 | |
11015 | /* Can't queue multiple flips, so wait for the previous | |
11016 | * one to finish before executing the next. | |
11017 | */ | |
11018 | if (intel_crtc->plane) | |
11019 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11020 | else | |
11021 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11022 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11023 | intel_ring_emit(ring, MI_NOOP); | |
11024 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11025 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11026 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11027 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11028 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11029 | |
6042639c | 11030 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11031 | return 0; |
8c9f3aaf JB |
11032 | } |
11033 | ||
11034 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11035 | struct drm_crtc *crtc, | |
11036 | struct drm_framebuffer *fb, | |
ed8d1975 | 11037 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11038 | struct drm_i915_gem_request *req, |
ed8d1975 | 11039 | uint32_t flags) |
8c9f3aaf | 11040 | { |
6258fbe2 | 11041 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11043 | u32 flip_mask; |
11044 | int ret; | |
11045 | ||
5fb9de1a | 11046 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11047 | if (ret) |
4fa62c89 | 11048 | return ret; |
8c9f3aaf JB |
11049 | |
11050 | if (intel_crtc->plane) | |
11051 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11052 | else | |
11053 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11054 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11055 | intel_ring_emit(ring, MI_NOOP); | |
11056 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11057 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11058 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11059 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11060 | intel_ring_emit(ring, MI_NOOP); |
11061 | ||
6042639c | 11062 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11063 | return 0; |
8c9f3aaf JB |
11064 | } |
11065 | ||
11066 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11067 | struct drm_crtc *crtc, | |
11068 | struct drm_framebuffer *fb, | |
ed8d1975 | 11069 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11070 | struct drm_i915_gem_request *req, |
ed8d1975 | 11071 | uint32_t flags) |
8c9f3aaf | 11072 | { |
6258fbe2 | 11073 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11074 | struct drm_i915_private *dev_priv = dev->dev_private; |
11075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11076 | uint32_t pf, pipesrc; | |
11077 | int ret; | |
11078 | ||
5fb9de1a | 11079 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11080 | if (ret) |
4fa62c89 | 11081 | return ret; |
8c9f3aaf JB |
11082 | |
11083 | /* i965+ uses the linear or tiled offsets from the | |
11084 | * Display Registers (which do not change across a page-flip) | |
11085 | * so we need only reprogram the base address. | |
11086 | */ | |
6d90c952 DV |
11087 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11088 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11089 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11090 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11091 | obj->tiling_mode); |
8c9f3aaf JB |
11092 | |
11093 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11094 | * untested on non-native modes, so ignore it for now. | |
11095 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11096 | */ | |
11097 | pf = 0; | |
11098 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11099 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11100 | |
6042639c | 11101 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11102 | return 0; |
8c9f3aaf JB |
11103 | } |
11104 | ||
11105 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11106 | struct drm_crtc *crtc, | |
11107 | struct drm_framebuffer *fb, | |
ed8d1975 | 11108 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11109 | struct drm_i915_gem_request *req, |
ed8d1975 | 11110 | uint32_t flags) |
8c9f3aaf | 11111 | { |
6258fbe2 | 11112 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11113 | struct drm_i915_private *dev_priv = dev->dev_private; |
11114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11115 | uint32_t pf, pipesrc; | |
11116 | int ret; | |
11117 | ||
5fb9de1a | 11118 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11119 | if (ret) |
4fa62c89 | 11120 | return ret; |
8c9f3aaf | 11121 | |
6d90c952 DV |
11122 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11123 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11124 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11125 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11126 | |
dc257cf1 DV |
11127 | /* Contrary to the suggestions in the documentation, |
11128 | * "Enable Panel Fitter" does not seem to be required when page | |
11129 | * flipping with a non-native mode, and worse causes a normal | |
11130 | * modeset to fail. | |
11131 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11132 | */ | |
11133 | pf = 0; | |
8c9f3aaf | 11134 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11135 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11136 | |
6042639c | 11137 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11138 | return 0; |
8c9f3aaf JB |
11139 | } |
11140 | ||
7c9017e5 JB |
11141 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11142 | struct drm_crtc *crtc, | |
11143 | struct drm_framebuffer *fb, | |
ed8d1975 | 11144 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11145 | struct drm_i915_gem_request *req, |
ed8d1975 | 11146 | uint32_t flags) |
7c9017e5 | 11147 | { |
6258fbe2 | 11148 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11150 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11151 | int len, ret; |
11152 | ||
eba905b2 | 11153 | switch (intel_crtc->plane) { |
cb05d8de DV |
11154 | case PLANE_A: |
11155 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11156 | break; | |
11157 | case PLANE_B: | |
11158 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11159 | break; | |
11160 | case PLANE_C: | |
11161 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11162 | break; | |
11163 | default: | |
11164 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11165 | return -ENODEV; |
cb05d8de DV |
11166 | } |
11167 | ||
ffe74d75 | 11168 | len = 4; |
f476828a | 11169 | if (ring->id == RCS) { |
ffe74d75 | 11170 | len += 6; |
f476828a DL |
11171 | /* |
11172 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11173 | * 48bits addresses, and we need a NOOP for the batch size to | |
11174 | * stay even. | |
11175 | */ | |
11176 | if (IS_GEN8(dev)) | |
11177 | len += 2; | |
11178 | } | |
ffe74d75 | 11179 | |
f66fab8e VS |
11180 | /* |
11181 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11182 | * "The full packet must be contained within the same cache line." | |
11183 | * | |
11184 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11185 | * cacheline, if we ever start emitting more commands before | |
11186 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11187 | * then do the cacheline alignment, and finally emit the | |
11188 | * MI_DISPLAY_FLIP. | |
11189 | */ | |
bba09b12 | 11190 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11191 | if (ret) |
4fa62c89 | 11192 | return ret; |
f66fab8e | 11193 | |
5fb9de1a | 11194 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11195 | if (ret) |
4fa62c89 | 11196 | return ret; |
7c9017e5 | 11197 | |
ffe74d75 CW |
11198 | /* Unmask the flip-done completion message. Note that the bspec says that |
11199 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11200 | * more than one flip event at any time (or ensure that one flip message | |
11201 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11202 | * Experimentation says that BCS works despite DERRMR masking all | |
11203 | * flip-done completion events and that unmasking all planes at once | |
11204 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11205 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11206 | */ | |
11207 | if (ring->id == RCS) { | |
11208 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11209 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11210 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11211 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11212 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11213 | if (IS_GEN8(dev)) |
f1afe24f | 11214 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11215 | MI_SRM_LRM_GLOBAL_GTT); |
11216 | else | |
f1afe24f | 11217 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11218 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11219 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11220 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11221 | if (IS_GEN8(dev)) { |
11222 | intel_ring_emit(ring, 0); | |
11223 | intel_ring_emit(ring, MI_NOOP); | |
11224 | } | |
ffe74d75 CW |
11225 | } |
11226 | ||
cb05d8de | 11227 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11228 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11229 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11230 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11231 | |
6042639c | 11232 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11233 | return 0; |
7c9017e5 JB |
11234 | } |
11235 | ||
84c33a64 SG |
11236 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11237 | struct drm_i915_gem_object *obj) | |
11238 | { | |
11239 | /* | |
11240 | * This is not being used for older platforms, because | |
11241 | * non-availability of flip done interrupt forces us to use | |
11242 | * CS flips. Older platforms derive flip done using some clever | |
11243 | * tricks involving the flip_pending status bits and vblank irqs. | |
11244 | * So using MMIO flips there would disrupt this mechanism. | |
11245 | */ | |
11246 | ||
8e09bf83 CW |
11247 | if (ring == NULL) |
11248 | return true; | |
11249 | ||
84c33a64 SG |
11250 | if (INTEL_INFO(ring->dev)->gen < 5) |
11251 | return false; | |
11252 | ||
11253 | if (i915.use_mmio_flip < 0) | |
11254 | return false; | |
11255 | else if (i915.use_mmio_flip > 0) | |
11256 | return true; | |
14bf993e OM |
11257 | else if (i915.enable_execlists) |
11258 | return true; | |
fd8e058a AG |
11259 | else if (obj->base.dma_buf && |
11260 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11261 | false)) | |
11262 | return true; | |
84c33a64 | 11263 | else |
b4716185 | 11264 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11265 | } |
11266 | ||
6042639c | 11267 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11268 | unsigned int rotation, |
6042639c | 11269 | struct intel_unpin_work *work) |
ff944564 DL |
11270 | { |
11271 | struct drm_device *dev = intel_crtc->base.dev; | |
11272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11273 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11274 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11275 | u32 ctl, stride, tile_height; |
ff944564 DL |
11276 | |
11277 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11278 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11279 | switch (fb->modifier[0]) { |
11280 | case DRM_FORMAT_MOD_NONE: | |
11281 | break; | |
11282 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11283 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11284 | break; |
11285 | case I915_FORMAT_MOD_Y_TILED: | |
11286 | ctl |= PLANE_CTL_TILED_Y; | |
11287 | break; | |
11288 | case I915_FORMAT_MOD_Yf_TILED: | |
11289 | ctl |= PLANE_CTL_TILED_YF; | |
11290 | break; | |
11291 | default: | |
11292 | MISSING_CASE(fb->modifier[0]); | |
11293 | } | |
ff944564 DL |
11294 | |
11295 | /* | |
11296 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11297 | * linear buffers or in number of tiles for tiled buffers. | |
11298 | */ | |
86efe24a TU |
11299 | if (intel_rotation_90_or_270(rotation)) { |
11300 | /* stride = Surface height in tiles */ | |
832be82f | 11301 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11302 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11303 | } else { | |
11304 | stride = fb->pitches[0] / | |
7b49f948 VS |
11305 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11306 | fb->pixel_format); | |
86efe24a | 11307 | } |
ff944564 DL |
11308 | |
11309 | /* | |
11310 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11311 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11312 | */ | |
11313 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11314 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11315 | ||
6042639c | 11316 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11317 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11318 | } | |
11319 | ||
6042639c CW |
11320 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11321 | struct intel_unpin_work *work) | |
84c33a64 SG |
11322 | { |
11323 | struct drm_device *dev = intel_crtc->base.dev; | |
11324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11325 | struct intel_framebuffer *intel_fb = | |
11326 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11327 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11328 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11329 | u32 dspcntr; |
84c33a64 | 11330 | |
84c33a64 SG |
11331 | dspcntr = I915_READ(reg); |
11332 | ||
c5d97472 DL |
11333 | if (obj->tiling_mode != I915_TILING_NONE) |
11334 | dspcntr |= DISPPLANE_TILED; | |
11335 | else | |
11336 | dspcntr &= ~DISPPLANE_TILED; | |
11337 | ||
84c33a64 SG |
11338 | I915_WRITE(reg, dspcntr); |
11339 | ||
6042639c | 11340 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11341 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11342 | } |
11343 | ||
11344 | /* | |
11345 | * XXX: This is the temporary way to update the plane registers until we get | |
11346 | * around to using the usual plane update functions for MMIO flips | |
11347 | */ | |
6042639c | 11348 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11349 | { |
6042639c CW |
11350 | struct intel_crtc *crtc = mmio_flip->crtc; |
11351 | struct intel_unpin_work *work; | |
11352 | ||
11353 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11354 | work = crtc->unpin_work; | |
11355 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11356 | if (work == NULL) | |
11357 | return; | |
ff944564 | 11358 | |
6042639c | 11359 | intel_mark_page_flip_active(work); |
ff944564 | 11360 | |
6042639c | 11361 | intel_pipe_update_start(crtc); |
ff944564 | 11362 | |
6042639c | 11363 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11364 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11365 | else |
11366 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11367 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11368 | |
6042639c | 11369 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11370 | } |
11371 | ||
9362c7c5 | 11372 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11373 | { |
b2cfe0ab CW |
11374 | struct intel_mmio_flip *mmio_flip = |
11375 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11376 | struct intel_framebuffer *intel_fb = |
11377 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11378 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11379 | |
6042639c | 11380 | if (mmio_flip->req) { |
eed29a5b | 11381 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11382 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11383 | false, NULL, |
11384 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11385 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11386 | } | |
84c33a64 | 11387 | |
fd8e058a AG |
11388 | /* For framebuffer backed by dmabuf, wait for fence */ |
11389 | if (obj->base.dma_buf) | |
11390 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11391 | false, false, | |
11392 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11393 | ||
6042639c | 11394 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11395 | kfree(mmio_flip); |
84c33a64 SG |
11396 | } |
11397 | ||
11398 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11399 | struct drm_crtc *crtc, | |
86efe24a | 11400 | struct drm_i915_gem_object *obj) |
84c33a64 | 11401 | { |
b2cfe0ab CW |
11402 | struct intel_mmio_flip *mmio_flip; |
11403 | ||
11404 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11405 | if (mmio_flip == NULL) | |
11406 | return -ENOMEM; | |
84c33a64 | 11407 | |
bcafc4e3 | 11408 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11409 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11410 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11411 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11412 | |
b2cfe0ab CW |
11413 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11414 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11415 | |
84c33a64 SG |
11416 | return 0; |
11417 | } | |
11418 | ||
8c9f3aaf JB |
11419 | static int intel_default_queue_flip(struct drm_device *dev, |
11420 | struct drm_crtc *crtc, | |
11421 | struct drm_framebuffer *fb, | |
ed8d1975 | 11422 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11423 | struct drm_i915_gem_request *req, |
ed8d1975 | 11424 | uint32_t flags) |
8c9f3aaf JB |
11425 | { |
11426 | return -ENODEV; | |
11427 | } | |
11428 | ||
d6bbafa1 CW |
11429 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11430 | struct drm_crtc *crtc) | |
11431 | { | |
11432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11434 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11435 | u32 addr; | |
11436 | ||
11437 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11438 | return true; | |
11439 | ||
908565c2 CW |
11440 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11441 | return false; | |
11442 | ||
d6bbafa1 CW |
11443 | if (!work->enable_stall_check) |
11444 | return false; | |
11445 | ||
11446 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11447 | if (work->flip_queued_req && |
11448 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11449 | return false; |
11450 | ||
1e3feefd | 11451 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11452 | } |
11453 | ||
1e3feefd | 11454 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11455 | return false; |
11456 | ||
11457 | /* Potential stall - if we see that the flip has happened, | |
11458 | * assume a missed interrupt. */ | |
11459 | if (INTEL_INFO(dev)->gen >= 4) | |
11460 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11461 | else | |
11462 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11463 | ||
11464 | /* There is a potential issue here with a false positive after a flip | |
11465 | * to the same address. We could address this by checking for a | |
11466 | * non-incrementing frame counter. | |
11467 | */ | |
11468 | return addr == work->gtt_offset; | |
11469 | } | |
11470 | ||
11471 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11472 | { | |
11473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11474 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11476 | struct intel_unpin_work *work; |
f326038a | 11477 | |
6c51d46f | 11478 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11479 | |
11480 | if (crtc == NULL) | |
11481 | return; | |
11482 | ||
f326038a | 11483 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11484 | work = intel_crtc->unpin_work; |
11485 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11486 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11487 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11488 | page_flip_completed(intel_crtc); |
6ad790c0 | 11489 | work = NULL; |
d6bbafa1 | 11490 | } |
6ad790c0 CW |
11491 | if (work != NULL && |
11492 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11493 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11494 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11495 | } |
11496 | ||
6b95a207 KH |
11497 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11498 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11499 | struct drm_pending_vblank_event *event, |
11500 | uint32_t page_flip_flags) | |
6b95a207 KH |
11501 | { |
11502 | struct drm_device *dev = crtc->dev; | |
11503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11504 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11505 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11507 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11508 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11509 | struct intel_unpin_work *work; |
a4872ba6 | 11510 | struct intel_engine_cs *ring; |
cf5d8a46 | 11511 | bool mmio_flip; |
91af127f | 11512 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11513 | int ret; |
6b95a207 | 11514 | |
2ff8fde1 MR |
11515 | /* |
11516 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11517 | * check to be safe. In the future we may enable pageflipping from | |
11518 | * a disabled primary plane. | |
11519 | */ | |
11520 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11521 | return -EBUSY; | |
11522 | ||
e6a595d2 | 11523 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11524 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11525 | return -EINVAL; |
11526 | ||
11527 | /* | |
11528 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11529 | * Note that pitch changes could also affect these register. | |
11530 | */ | |
11531 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11532 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11533 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11534 | return -EINVAL; |
11535 | ||
f900db47 CW |
11536 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11537 | goto out_hang; | |
11538 | ||
b14c5679 | 11539 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11540 | if (work == NULL) |
11541 | return -ENOMEM; | |
11542 | ||
6b95a207 | 11543 | work->event = event; |
b4a98e57 | 11544 | work->crtc = crtc; |
ab8d6675 | 11545 | work->old_fb = old_fb; |
6b95a207 KH |
11546 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11547 | ||
87b6b101 | 11548 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11549 | if (ret) |
11550 | goto free_work; | |
11551 | ||
6b95a207 | 11552 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11553 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11554 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11555 | /* Before declaring the flip queue wedged, check if |
11556 | * the hardware completed the operation behind our backs. | |
11557 | */ | |
11558 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11559 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11560 | page_flip_completed(intel_crtc); | |
11561 | } else { | |
11562 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11563 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11564 | |
d6bbafa1 CW |
11565 | drm_crtc_vblank_put(crtc); |
11566 | kfree(work); | |
11567 | return -EBUSY; | |
11568 | } | |
6b95a207 KH |
11569 | } |
11570 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11571 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11572 | |
b4a98e57 CW |
11573 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11574 | flush_workqueue(dev_priv->wq); | |
11575 | ||
75dfca80 | 11576 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11577 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11578 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11579 | |
f4510a27 | 11580 | crtc->primary->fb = fb; |
afd65eb4 | 11581 | update_state_fb(crtc->primary); |
e8216e50 | 11582 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11583 | |
e1f99ce6 | 11584 | work->pending_flip_obj = obj; |
e1f99ce6 | 11585 | |
89ed88ba CW |
11586 | ret = i915_mutex_lock_interruptible(dev); |
11587 | if (ret) | |
11588 | goto cleanup; | |
11589 | ||
b4a98e57 | 11590 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11591 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11592 | |
75f7f3ec | 11593 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11594 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11595 | |
666a4537 | 11596 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11597 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11598 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11599 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11600 | ring = NULL; | |
48bf5b2d | 11601 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11602 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11603 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11604 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11605 | if (ring == NULL || ring->id != RCS) |
11606 | ring = &dev_priv->ring[BCS]; | |
11607 | } else { | |
11608 | ring = &dev_priv->ring[RCS]; | |
11609 | } | |
11610 | ||
cf5d8a46 CW |
11611 | mmio_flip = use_mmio_flip(ring, obj); |
11612 | ||
11613 | /* When using CS flips, we want to emit semaphores between rings. | |
11614 | * However, when using mmio flips we will create a task to do the | |
11615 | * synchronisation, so all we want here is to pin the framebuffer | |
11616 | * into the display plane and skip any waits. | |
11617 | */ | |
7580d774 ML |
11618 | if (!mmio_flip) { |
11619 | ret = i915_gem_object_sync(obj, ring, &request); | |
11620 | if (ret) | |
11621 | goto cleanup_pending; | |
11622 | } | |
11623 | ||
82bc3b2d | 11624 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11625 | crtc->primary->state); |
8c9f3aaf JB |
11626 | if (ret) |
11627 | goto cleanup_pending; | |
6b95a207 | 11628 | |
dedf278c TU |
11629 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11630 | obj, 0); | |
11631 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11632 | |
cf5d8a46 | 11633 | if (mmio_flip) { |
86efe24a | 11634 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11635 | if (ret) |
11636 | goto cleanup_unpin; | |
11637 | ||
f06cc1b9 JH |
11638 | i915_gem_request_assign(&work->flip_queued_req, |
11639 | obj->last_write_req); | |
d6bbafa1 | 11640 | } else { |
6258fbe2 | 11641 | if (!request) { |
26827088 DG |
11642 | request = i915_gem_request_alloc(ring, NULL); |
11643 | if (IS_ERR(request)) { | |
11644 | ret = PTR_ERR(request); | |
6258fbe2 | 11645 | goto cleanup_unpin; |
26827088 | 11646 | } |
6258fbe2 JH |
11647 | } |
11648 | ||
11649 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11650 | page_flip_flags); |
11651 | if (ret) | |
11652 | goto cleanup_unpin; | |
11653 | ||
6258fbe2 | 11654 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11655 | } |
11656 | ||
91af127f | 11657 | if (request) |
75289874 | 11658 | i915_add_request_no_flush(request); |
91af127f | 11659 | |
1e3feefd | 11660 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11661 | work->enable_stall_check = true; |
4fa62c89 | 11662 | |
ab8d6675 | 11663 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11664 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11665 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11666 | |
a9ff8714 VS |
11667 | intel_frontbuffer_flip_prepare(dev, |
11668 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11669 | |
e5510fac JB |
11670 | trace_i915_flip_request(intel_crtc->plane, obj); |
11671 | ||
6b95a207 | 11672 | return 0; |
96b099fd | 11673 | |
4fa62c89 | 11674 | cleanup_unpin: |
82bc3b2d | 11675 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11676 | cleanup_pending: |
0aa498d5 | 11677 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11678 | i915_gem_request_cancel(request); |
b4a98e57 | 11679 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11680 | mutex_unlock(&dev->struct_mutex); |
11681 | cleanup: | |
f4510a27 | 11682 | crtc->primary->fb = old_fb; |
afd65eb4 | 11683 | update_state_fb(crtc->primary); |
89ed88ba CW |
11684 | |
11685 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11686 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11687 | |
5e2d7afc | 11688 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11689 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11690 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11691 | |
87b6b101 | 11692 | drm_crtc_vblank_put(crtc); |
7317c75e | 11693 | free_work: |
96b099fd CW |
11694 | kfree(work); |
11695 | ||
f900db47 | 11696 | if (ret == -EIO) { |
02e0efb5 ML |
11697 | struct drm_atomic_state *state; |
11698 | struct drm_plane_state *plane_state; | |
11699 | ||
f900db47 | 11700 | out_hang: |
02e0efb5 ML |
11701 | state = drm_atomic_state_alloc(dev); |
11702 | if (!state) | |
11703 | return -ENOMEM; | |
11704 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11705 | ||
11706 | retry: | |
11707 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11708 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11709 | if (!ret) { | |
11710 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11711 | ||
11712 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11713 | if (!ret) | |
11714 | ret = drm_atomic_commit(state); | |
11715 | } | |
11716 | ||
11717 | if (ret == -EDEADLK) { | |
11718 | drm_modeset_backoff(state->acquire_ctx); | |
11719 | drm_atomic_state_clear(state); | |
11720 | goto retry; | |
11721 | } | |
11722 | ||
11723 | if (ret) | |
11724 | drm_atomic_state_free(state); | |
11725 | ||
f0d3dad3 | 11726 | if (ret == 0 && event) { |
5e2d7afc | 11727 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11728 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11729 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11730 | } |
f900db47 | 11731 | } |
96b099fd | 11732 | return ret; |
6b95a207 KH |
11733 | } |
11734 | ||
da20eabd ML |
11735 | |
11736 | /** | |
11737 | * intel_wm_need_update - Check whether watermarks need updating | |
11738 | * @plane: drm plane | |
11739 | * @state: new plane state | |
11740 | * | |
11741 | * Check current plane state versus the new one to determine whether | |
11742 | * watermarks need to be recalculated. | |
11743 | * | |
11744 | * Returns true or false. | |
11745 | */ | |
11746 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11747 | struct drm_plane_state *state) | |
11748 | { | |
d21fbe87 MR |
11749 | struct intel_plane_state *new = to_intel_plane_state(state); |
11750 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11751 | ||
11752 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11753 | if (new->visible != cur->visible) |
11754 | return true; | |
11755 | ||
11756 | if (!cur->base.fb || !new->base.fb) | |
11757 | return false; | |
11758 | ||
11759 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11760 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11761 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11762 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11763 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11764 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11765 | return true; |
7809e5ae | 11766 | |
2791a16c | 11767 | return false; |
7809e5ae MR |
11768 | } |
11769 | ||
d21fbe87 MR |
11770 | static bool needs_scaling(struct intel_plane_state *state) |
11771 | { | |
11772 | int src_w = drm_rect_width(&state->src) >> 16; | |
11773 | int src_h = drm_rect_height(&state->src) >> 16; | |
11774 | int dst_w = drm_rect_width(&state->dst); | |
11775 | int dst_h = drm_rect_height(&state->dst); | |
11776 | ||
11777 | return (src_w != dst_w || src_h != dst_h); | |
11778 | } | |
11779 | ||
da20eabd ML |
11780 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11781 | struct drm_plane_state *plane_state) | |
11782 | { | |
ab1d3a0e | 11783 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11784 | struct drm_crtc *crtc = crtc_state->crtc; |
11785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11786 | struct drm_plane *plane = plane_state->plane; | |
11787 | struct drm_device *dev = crtc->dev; | |
da20eabd ML |
11788 | struct intel_plane_state *old_plane_state = |
11789 | to_intel_plane_state(plane->state); | |
11790 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11791 | bool mode_changed = needs_modeset(crtc_state); |
11792 | bool was_crtc_enabled = crtc->state->active; | |
11793 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11794 | bool turn_off, turn_on, visible, was_visible; |
11795 | struct drm_framebuffer *fb = plane_state->fb; | |
11796 | ||
11797 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11798 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11799 | ret = skl_update_scaler_plane( | |
11800 | to_intel_crtc_state(crtc_state), | |
11801 | to_intel_plane_state(plane_state)); | |
11802 | if (ret) | |
11803 | return ret; | |
11804 | } | |
11805 | ||
da20eabd ML |
11806 | was_visible = old_plane_state->visible; |
11807 | visible = to_intel_plane_state(plane_state)->visible; | |
11808 | ||
11809 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11810 | was_visible = false; | |
11811 | ||
35c08f43 ML |
11812 | /* |
11813 | * Visibility is calculated as if the crtc was on, but | |
11814 | * after scaler setup everything depends on it being off | |
11815 | * when the crtc isn't active. | |
11816 | */ | |
11817 | if (!is_crtc_enabled) | |
11818 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11819 | |
11820 | if (!was_visible && !visible) | |
11821 | return 0; | |
11822 | ||
e8861675 ML |
11823 | if (fb != old_plane_state->base.fb) |
11824 | pipe_config->fb_changed = true; | |
11825 | ||
da20eabd ML |
11826 | turn_off = was_visible && (!visible || mode_changed); |
11827 | turn_on = visible && (!was_visible || mode_changed); | |
11828 | ||
11829 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11830 | plane->base.id, fb ? fb->base.id : -1); | |
11831 | ||
11832 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11833 | plane->base.id, was_visible, visible, | |
11834 | turn_off, turn_on, mode_changed); | |
11835 | ||
92826fcd ML |
11836 | if (turn_on || turn_off) { |
11837 | pipe_config->wm_changed = true; | |
11838 | ||
852eb00d | 11839 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11840 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11841 | pipe_config->disable_cxsr = true; |
852eb00d | 11842 | } else if (intel_wm_need_update(plane, plane_state)) { |
92826fcd | 11843 | pipe_config->wm_changed = true; |
852eb00d | 11844 | } |
da20eabd | 11845 | |
8be6ca85 | 11846 | if (visible || was_visible) |
a9ff8714 VS |
11847 | intel_crtc->atomic.fb_bits |= |
11848 | to_intel_plane(plane)->frontbuffer_bit; | |
11849 | ||
da20eabd ML |
11850 | switch (plane->type) { |
11851 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 11852 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 11853 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 11854 | |
da20eabd ML |
11855 | break; |
11856 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11857 | break; |
11858 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11859 | /* |
11860 | * WaCxSRDisabledForSpriteScaling:ivb | |
11861 | * | |
11862 | * cstate->update_wm was already set above, so this flag will | |
11863 | * take effect when we commit and program watermarks. | |
11864 | */ | |
11865 | if (IS_IVYBRIDGE(dev) && | |
11866 | needs_scaling(to_intel_plane_state(plane_state)) && | |
e8861675 ML |
11867 | !needs_scaling(old_plane_state)) |
11868 | pipe_config->disable_lp_wm = true; | |
d21fbe87 MR |
11869 | |
11870 | break; | |
da20eabd ML |
11871 | } |
11872 | return 0; | |
11873 | } | |
11874 | ||
6d3a1ce7 ML |
11875 | static bool encoders_cloneable(const struct intel_encoder *a, |
11876 | const struct intel_encoder *b) | |
11877 | { | |
11878 | /* masks could be asymmetric, so check both ways */ | |
11879 | return a == b || (a->cloneable & (1 << b->type) && | |
11880 | b->cloneable & (1 << a->type)); | |
11881 | } | |
11882 | ||
11883 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11884 | struct intel_crtc *crtc, | |
11885 | struct intel_encoder *encoder) | |
11886 | { | |
11887 | struct intel_encoder *source_encoder; | |
11888 | struct drm_connector *connector; | |
11889 | struct drm_connector_state *connector_state; | |
11890 | int i; | |
11891 | ||
11892 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11893 | if (connector_state->crtc != &crtc->base) | |
11894 | continue; | |
11895 | ||
11896 | source_encoder = | |
11897 | to_intel_encoder(connector_state->best_encoder); | |
11898 | if (!encoders_cloneable(encoder, source_encoder)) | |
11899 | return false; | |
11900 | } | |
11901 | ||
11902 | return true; | |
11903 | } | |
11904 | ||
11905 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11906 | struct intel_crtc *crtc) | |
11907 | { | |
11908 | struct intel_encoder *encoder; | |
11909 | struct drm_connector *connector; | |
11910 | struct drm_connector_state *connector_state; | |
11911 | int i; | |
11912 | ||
11913 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11914 | if (connector_state->crtc != &crtc->base) | |
11915 | continue; | |
11916 | ||
11917 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11918 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11919 | return false; | |
11920 | } | |
11921 | ||
11922 | return true; | |
11923 | } | |
11924 | ||
11925 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11926 | struct drm_crtc_state *crtc_state) | |
11927 | { | |
cf5a15be | 11928 | struct drm_device *dev = crtc->dev; |
ad421372 | 11929 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11931 | struct intel_crtc_state *pipe_config = |
11932 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11933 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11934 | int ret; |
6d3a1ce7 ML |
11935 | bool mode_changed = needs_modeset(crtc_state); |
11936 | ||
11937 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11938 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11939 | return -EINVAL; | |
11940 | } | |
11941 | ||
852eb00d | 11942 | if (mode_changed && !crtc_state->active) |
92826fcd | 11943 | pipe_config->wm_changed = true; |
eddfcbcd | 11944 | |
ad421372 ML |
11945 | if (mode_changed && crtc_state->enable && |
11946 | dev_priv->display.crtc_compute_clock && | |
11947 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11948 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11949 | pipe_config); | |
11950 | if (ret) | |
11951 | return ret; | |
11952 | } | |
11953 | ||
e435d6e5 | 11954 | ret = 0; |
86c8bbbe MR |
11955 | if (dev_priv->display.compute_pipe_wm) { |
11956 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
bf220452 | 11957 | if (ret) |
86c8bbbe MR |
11958 | return ret; |
11959 | } | |
11960 | ||
e435d6e5 ML |
11961 | if (INTEL_INFO(dev)->gen >= 9) { |
11962 | if (mode_changed) | |
11963 | ret = skl_update_scaler_crtc(pipe_config); | |
11964 | ||
11965 | if (!ret) | |
11966 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11967 | pipe_config); | |
11968 | } | |
11969 | ||
11970 | return ret; | |
6d3a1ce7 ML |
11971 | } |
11972 | ||
65b38e0d | 11973 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11974 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11975 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11976 | .atomic_begin = intel_begin_crtc_commit, |
11977 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11978 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11979 | }; |
11980 | ||
d29b2f9d ACO |
11981 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11982 | { | |
11983 | struct intel_connector *connector; | |
11984 | ||
11985 | for_each_intel_connector(dev, connector) { | |
11986 | if (connector->base.encoder) { | |
11987 | connector->base.state->best_encoder = | |
11988 | connector->base.encoder; | |
11989 | connector->base.state->crtc = | |
11990 | connector->base.encoder->crtc; | |
11991 | } else { | |
11992 | connector->base.state->best_encoder = NULL; | |
11993 | connector->base.state->crtc = NULL; | |
11994 | } | |
11995 | } | |
11996 | } | |
11997 | ||
050f7aeb | 11998 | static void |
eba905b2 | 11999 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12000 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12001 | { |
12002 | int bpp = pipe_config->pipe_bpp; | |
12003 | ||
12004 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12005 | connector->base.base.id, | |
c23cc417 | 12006 | connector->base.name); |
050f7aeb DV |
12007 | |
12008 | /* Don't use an invalid EDID bpc value */ | |
12009 | if (connector->base.display_info.bpc && | |
12010 | connector->base.display_info.bpc * 3 < bpp) { | |
12011 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12012 | bpp, connector->base.display_info.bpc*3); | |
12013 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12014 | } | |
12015 | ||
013dd9e0 JN |
12016 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12017 | if (connector->base.display_info.bpc == 0) { | |
12018 | int type = connector->base.connector_type; | |
12019 | int clamp_bpp = 24; | |
12020 | ||
12021 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12022 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12023 | type == DRM_MODE_CONNECTOR_eDP) | |
12024 | clamp_bpp = 18; | |
12025 | ||
12026 | if (bpp > clamp_bpp) { | |
12027 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12028 | bpp, clamp_bpp); | |
12029 | pipe_config->pipe_bpp = clamp_bpp; | |
12030 | } | |
050f7aeb DV |
12031 | } |
12032 | } | |
12033 | ||
4e53c2e0 | 12034 | static int |
050f7aeb | 12035 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12036 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12037 | { |
050f7aeb | 12038 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12039 | struct drm_atomic_state *state; |
da3ced29 ACO |
12040 | struct drm_connector *connector; |
12041 | struct drm_connector_state *connector_state; | |
1486017f | 12042 | int bpp, i; |
4e53c2e0 | 12043 | |
666a4537 | 12044 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12045 | bpp = 10*3; |
d328c9d7 DV |
12046 | else if (INTEL_INFO(dev)->gen >= 5) |
12047 | bpp = 12*3; | |
12048 | else | |
12049 | bpp = 8*3; | |
12050 | ||
4e53c2e0 | 12051 | |
4e53c2e0 DV |
12052 | pipe_config->pipe_bpp = bpp; |
12053 | ||
1486017f ACO |
12054 | state = pipe_config->base.state; |
12055 | ||
4e53c2e0 | 12056 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12057 | for_each_connector_in_state(state, connector, connector_state, i) { |
12058 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12059 | continue; |
12060 | ||
da3ced29 ACO |
12061 | connected_sink_compute_bpp(to_intel_connector(connector), |
12062 | pipe_config); | |
4e53c2e0 DV |
12063 | } |
12064 | ||
12065 | return bpp; | |
12066 | } | |
12067 | ||
644db711 DV |
12068 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12069 | { | |
12070 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12071 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12072 | mode->crtc_clock, |
644db711 DV |
12073 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12074 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12075 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12076 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12077 | } | |
12078 | ||
c0b03411 | 12079 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12080 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12081 | const char *context) |
12082 | { | |
6a60cd87 CK |
12083 | struct drm_device *dev = crtc->base.dev; |
12084 | struct drm_plane *plane; | |
12085 | struct intel_plane *intel_plane; | |
12086 | struct intel_plane_state *state; | |
12087 | struct drm_framebuffer *fb; | |
12088 | ||
12089 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12090 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12091 | |
12092 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12093 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12094 | pipe_config->pipe_bpp, pipe_config->dither); | |
12095 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12096 | pipe_config->has_pch_encoder, | |
12097 | pipe_config->fdi_lanes, | |
12098 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12099 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12100 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12101 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12102 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12103 | pipe_config->lane_count, |
eb14cb74 VS |
12104 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12105 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12106 | pipe_config->dp_m_n.tu); | |
b95af8be | 12107 | |
90a6b7b0 | 12108 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12109 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12110 | pipe_config->lane_count, |
b95af8be VK |
12111 | pipe_config->dp_m2_n2.gmch_m, |
12112 | pipe_config->dp_m2_n2.gmch_n, | |
12113 | pipe_config->dp_m2_n2.link_m, | |
12114 | pipe_config->dp_m2_n2.link_n, | |
12115 | pipe_config->dp_m2_n2.tu); | |
12116 | ||
55072d19 DV |
12117 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12118 | pipe_config->has_audio, | |
12119 | pipe_config->has_infoframe); | |
12120 | ||
c0b03411 | 12121 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12122 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12123 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12124 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12125 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12126 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12127 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12128 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12129 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12130 | crtc->num_scalers, | |
12131 | pipe_config->scaler_state.scaler_users, | |
12132 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12133 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12134 | pipe_config->gmch_pfit.control, | |
12135 | pipe_config->gmch_pfit.pgm_ratios, | |
12136 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12137 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12138 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12139 | pipe_config->pch_pfit.size, |
12140 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12141 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12142 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12143 | |
415ff0f6 | 12144 | if (IS_BROXTON(dev)) { |
05712c15 | 12145 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12146 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12147 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12148 | pipe_config->ddi_pll_sel, |
12149 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12150 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12151 | pipe_config->dpll_hw_state.pll0, |
12152 | pipe_config->dpll_hw_state.pll1, | |
12153 | pipe_config->dpll_hw_state.pll2, | |
12154 | pipe_config->dpll_hw_state.pll3, | |
12155 | pipe_config->dpll_hw_state.pll6, | |
12156 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12157 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12158 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12159 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12160 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12161 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12162 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12163 | pipe_config->ddi_pll_sel, | |
12164 | pipe_config->dpll_hw_state.ctrl1, | |
12165 | pipe_config->dpll_hw_state.cfgcr1, | |
12166 | pipe_config->dpll_hw_state.cfgcr2); | |
12167 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12168 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12169 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12170 | pipe_config->dpll_hw_state.wrpll, |
12171 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12172 | } else { |
12173 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12174 | "fp0: 0x%x, fp1: 0x%x\n", | |
12175 | pipe_config->dpll_hw_state.dpll, | |
12176 | pipe_config->dpll_hw_state.dpll_md, | |
12177 | pipe_config->dpll_hw_state.fp0, | |
12178 | pipe_config->dpll_hw_state.fp1); | |
12179 | } | |
12180 | ||
6a60cd87 CK |
12181 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12182 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12183 | intel_plane = to_intel_plane(plane); | |
12184 | if (intel_plane->pipe != crtc->pipe) | |
12185 | continue; | |
12186 | ||
12187 | state = to_intel_plane_state(plane->state); | |
12188 | fb = state->base.fb; | |
12189 | if (!fb) { | |
12190 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12191 | "disabled, scaler_id = %d\n", | |
12192 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12193 | plane->base.id, intel_plane->pipe, | |
12194 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12195 | drm_plane_index(plane), state->scaler_id); | |
12196 | continue; | |
12197 | } | |
12198 | ||
12199 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12200 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12201 | plane->base.id, intel_plane->pipe, | |
12202 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12203 | drm_plane_index(plane)); | |
12204 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12205 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12206 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12207 | state->scaler_id, | |
12208 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12209 | drm_rect_width(&state->src) >> 16, | |
12210 | drm_rect_height(&state->src) >> 16, | |
12211 | state->dst.x1, state->dst.y1, | |
12212 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12213 | } | |
c0b03411 DV |
12214 | } |
12215 | ||
5448a00d | 12216 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12217 | { |
5448a00d | 12218 | struct drm_device *dev = state->dev; |
da3ced29 | 12219 | struct drm_connector *connector; |
00f0b378 VS |
12220 | unsigned int used_ports = 0; |
12221 | ||
12222 | /* | |
12223 | * Walk the connector list instead of the encoder | |
12224 | * list to detect the problem on ddi platforms | |
12225 | * where there's just one encoder per digital port. | |
12226 | */ | |
0bff4858 VS |
12227 | drm_for_each_connector(connector, dev) { |
12228 | struct drm_connector_state *connector_state; | |
12229 | struct intel_encoder *encoder; | |
12230 | ||
12231 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12232 | if (!connector_state) | |
12233 | connector_state = connector->state; | |
12234 | ||
5448a00d | 12235 | if (!connector_state->best_encoder) |
00f0b378 VS |
12236 | continue; |
12237 | ||
5448a00d ACO |
12238 | encoder = to_intel_encoder(connector_state->best_encoder); |
12239 | ||
12240 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12241 | |
12242 | switch (encoder->type) { | |
12243 | unsigned int port_mask; | |
12244 | case INTEL_OUTPUT_UNKNOWN: | |
12245 | if (WARN_ON(!HAS_DDI(dev))) | |
12246 | break; | |
12247 | case INTEL_OUTPUT_DISPLAYPORT: | |
12248 | case INTEL_OUTPUT_HDMI: | |
12249 | case INTEL_OUTPUT_EDP: | |
12250 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12251 | ||
12252 | /* the same port mustn't appear more than once */ | |
12253 | if (used_ports & port_mask) | |
12254 | return false; | |
12255 | ||
12256 | used_ports |= port_mask; | |
12257 | default: | |
12258 | break; | |
12259 | } | |
12260 | } | |
12261 | ||
12262 | return true; | |
12263 | } | |
12264 | ||
83a57153 ACO |
12265 | static void |
12266 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12267 | { | |
12268 | struct drm_crtc_state tmp_state; | |
663a3640 | 12269 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12270 | struct intel_dpll_hw_state dpll_hw_state; |
12271 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12272 | uint32_t ddi_pll_sel; |
c4e2d043 | 12273 | bool force_thru; |
83a57153 | 12274 | |
7546a384 ACO |
12275 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12276 | * kzalloc'd. Code that depends on any field being zero should be | |
12277 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12278 | * only fields that are know to not cause problems are preserved. */ | |
12279 | ||
83a57153 | 12280 | tmp_state = crtc_state->base; |
663a3640 | 12281 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12282 | shared_dpll = crtc_state->shared_dpll; |
12283 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12284 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12285 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12286 | |
83a57153 | 12287 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12288 | |
83a57153 | 12289 | crtc_state->base = tmp_state; |
663a3640 | 12290 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12291 | crtc_state->shared_dpll = shared_dpll; |
12292 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12293 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12294 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12295 | } |
12296 | ||
548ee15b | 12297 | static int |
b8cecdf5 | 12298 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12299 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12300 | { |
b359283a | 12301 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12302 | struct intel_encoder *encoder; |
da3ced29 | 12303 | struct drm_connector *connector; |
0b901879 | 12304 | struct drm_connector_state *connector_state; |
d328c9d7 | 12305 | int base_bpp, ret = -EINVAL; |
0b901879 | 12306 | int i; |
e29c22c0 | 12307 | bool retry = true; |
ee7b9f93 | 12308 | |
83a57153 | 12309 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12310 | |
e143a21c DV |
12311 | pipe_config->cpu_transcoder = |
12312 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12313 | |
2960bc9c ID |
12314 | /* |
12315 | * Sanitize sync polarity flags based on requested ones. If neither | |
12316 | * positive or negative polarity is requested, treat this as meaning | |
12317 | * negative polarity. | |
12318 | */ | |
2d112de7 | 12319 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12320 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12321 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12322 | |
2d112de7 | 12323 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12324 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12325 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12326 | |
d328c9d7 DV |
12327 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12328 | pipe_config); | |
12329 | if (base_bpp < 0) | |
4e53c2e0 DV |
12330 | goto fail; |
12331 | ||
e41a56be VS |
12332 | /* |
12333 | * Determine the real pipe dimensions. Note that stereo modes can | |
12334 | * increase the actual pipe size due to the frame doubling and | |
12335 | * insertion of additional space for blanks between the frame. This | |
12336 | * is stored in the crtc timings. We use the requested mode to do this | |
12337 | * computation to clearly distinguish it from the adjusted mode, which | |
12338 | * can be changed by the connectors in the below retry loop. | |
12339 | */ | |
2d112de7 | 12340 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12341 | &pipe_config->pipe_src_w, |
12342 | &pipe_config->pipe_src_h); | |
e41a56be | 12343 | |
e29c22c0 | 12344 | encoder_retry: |
ef1b460d | 12345 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12346 | pipe_config->port_clock = 0; |
ef1b460d | 12347 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12348 | |
135c81b8 | 12349 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12350 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12351 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12352 | |
7758a113 DV |
12353 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12354 | * adjust it according to limitations or connector properties, and also | |
12355 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12356 | */ |
da3ced29 | 12357 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12358 | if (connector_state->crtc != crtc) |
7758a113 | 12359 | continue; |
7ae89233 | 12360 | |
0b901879 ACO |
12361 | encoder = to_intel_encoder(connector_state->best_encoder); |
12362 | ||
efea6e8e DV |
12363 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12364 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12365 | goto fail; |
12366 | } | |
ee7b9f93 | 12367 | } |
47f1c6c9 | 12368 | |
ff9a6750 DV |
12369 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12370 | * done afterwards in case the encoder adjusts the mode. */ | |
12371 | if (!pipe_config->port_clock) | |
2d112de7 | 12372 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12373 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12374 | |
a43f6e0f | 12375 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12376 | if (ret < 0) { |
7758a113 DV |
12377 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12378 | goto fail; | |
ee7b9f93 | 12379 | } |
e29c22c0 DV |
12380 | |
12381 | if (ret == RETRY) { | |
12382 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12383 | ret = -EINVAL; | |
12384 | goto fail; | |
12385 | } | |
12386 | ||
12387 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12388 | retry = false; | |
12389 | goto encoder_retry; | |
12390 | } | |
12391 | ||
e8fa4270 DV |
12392 | /* Dithering seems to not pass-through bits correctly when it should, so |
12393 | * only enable it on 6bpc panels. */ | |
12394 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12395 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12396 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12397 | |
7758a113 | 12398 | fail: |
548ee15b | 12399 | return ret; |
ee7b9f93 | 12400 | } |
47f1c6c9 | 12401 | |
ea9d758d | 12402 | static void |
4740b0f2 | 12403 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12404 | { |
0a9ab303 ACO |
12405 | struct drm_crtc *crtc; |
12406 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12407 | int i; |
ea9d758d | 12408 | |
7668851f | 12409 | /* Double check state. */ |
8a75d157 | 12410 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12411 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12412 | |
12413 | /* Update hwmode for vblank functions */ | |
12414 | if (crtc->state->active) | |
12415 | crtc->hwmode = crtc->state->adjusted_mode; | |
12416 | else | |
12417 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12418 | |
12419 | /* | |
12420 | * Update legacy state to satisfy fbc code. This can | |
12421 | * be removed when fbc uses the atomic state. | |
12422 | */ | |
12423 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12424 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12425 | ||
12426 | crtc->primary->fb = plane_state->fb; | |
12427 | crtc->x = plane_state->src_x >> 16; | |
12428 | crtc->y = plane_state->src_y >> 16; | |
12429 | } | |
ea9d758d | 12430 | } |
ea9d758d DV |
12431 | } |
12432 | ||
3bd26263 | 12433 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12434 | { |
3bd26263 | 12435 | int diff; |
f1f644dc JB |
12436 | |
12437 | if (clock1 == clock2) | |
12438 | return true; | |
12439 | ||
12440 | if (!clock1 || !clock2) | |
12441 | return false; | |
12442 | ||
12443 | diff = abs(clock1 - clock2); | |
12444 | ||
12445 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12446 | return true; | |
12447 | ||
12448 | return false; | |
12449 | } | |
12450 | ||
25c5b266 DV |
12451 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12452 | list_for_each_entry((intel_crtc), \ | |
12453 | &(dev)->mode_config.crtc_list, \ | |
12454 | base.head) \ | |
95150bdf | 12455 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12456 | |
cfb23ed6 ML |
12457 | static bool |
12458 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12459 | unsigned int m2, unsigned int n2, | |
12460 | bool exact) | |
12461 | { | |
12462 | if (m == m2 && n == n2) | |
12463 | return true; | |
12464 | ||
12465 | if (exact || !m || !n || !m2 || !n2) | |
12466 | return false; | |
12467 | ||
12468 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12469 | ||
31d10b57 ML |
12470 | if (n > n2) { |
12471 | while (n > n2) { | |
cfb23ed6 ML |
12472 | m2 <<= 1; |
12473 | n2 <<= 1; | |
12474 | } | |
31d10b57 ML |
12475 | } else if (n < n2) { |
12476 | while (n < n2) { | |
cfb23ed6 ML |
12477 | m <<= 1; |
12478 | n <<= 1; | |
12479 | } | |
12480 | } | |
12481 | ||
31d10b57 ML |
12482 | if (n != n2) |
12483 | return false; | |
12484 | ||
12485 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12486 | } |
12487 | ||
12488 | static bool | |
12489 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12490 | struct intel_link_m_n *m2_n2, | |
12491 | bool adjust) | |
12492 | { | |
12493 | if (m_n->tu == m2_n2->tu && | |
12494 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12495 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12496 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12497 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12498 | if (adjust) | |
12499 | *m2_n2 = *m_n; | |
12500 | ||
12501 | return true; | |
12502 | } | |
12503 | ||
12504 | return false; | |
12505 | } | |
12506 | ||
0e8ffe1b | 12507 | static bool |
2fa2fe9a | 12508 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12509 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12510 | struct intel_crtc_state *pipe_config, |
12511 | bool adjust) | |
0e8ffe1b | 12512 | { |
cfb23ed6 ML |
12513 | bool ret = true; |
12514 | ||
12515 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12516 | do { \ | |
12517 | if (!adjust) \ | |
12518 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12519 | else \ | |
12520 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12521 | } while (0) | |
12522 | ||
66e985c0 DV |
12523 | #define PIPE_CONF_CHECK_X(name) \ |
12524 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12525 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12526 | "(expected 0x%08x, found 0x%08x)\n", \ |
12527 | current_config->name, \ | |
12528 | pipe_config->name); \ | |
cfb23ed6 | 12529 | ret = false; \ |
66e985c0 DV |
12530 | } |
12531 | ||
08a24034 DV |
12532 | #define PIPE_CONF_CHECK_I(name) \ |
12533 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12534 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12535 | "(expected %i, found %i)\n", \ |
12536 | current_config->name, \ | |
12537 | pipe_config->name); \ | |
cfb23ed6 ML |
12538 | ret = false; \ |
12539 | } | |
12540 | ||
12541 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12542 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12543 | &pipe_config->name,\ | |
12544 | adjust)) { \ | |
12545 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12546 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12547 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12548 | current_config->name.tu, \ | |
12549 | current_config->name.gmch_m, \ | |
12550 | current_config->name.gmch_n, \ | |
12551 | current_config->name.link_m, \ | |
12552 | current_config->name.link_n, \ | |
12553 | pipe_config->name.tu, \ | |
12554 | pipe_config->name.gmch_m, \ | |
12555 | pipe_config->name.gmch_n, \ | |
12556 | pipe_config->name.link_m, \ | |
12557 | pipe_config->name.link_n); \ | |
12558 | ret = false; \ | |
12559 | } | |
12560 | ||
12561 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12562 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12563 | &pipe_config->name, adjust) && \ | |
12564 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12565 | &pipe_config->name, adjust)) { \ | |
12566 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12567 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12568 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12569 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12570 | current_config->name.tu, \ | |
12571 | current_config->name.gmch_m, \ | |
12572 | current_config->name.gmch_n, \ | |
12573 | current_config->name.link_m, \ | |
12574 | current_config->name.link_n, \ | |
12575 | current_config->alt_name.tu, \ | |
12576 | current_config->alt_name.gmch_m, \ | |
12577 | current_config->alt_name.gmch_n, \ | |
12578 | current_config->alt_name.link_m, \ | |
12579 | current_config->alt_name.link_n, \ | |
12580 | pipe_config->name.tu, \ | |
12581 | pipe_config->name.gmch_m, \ | |
12582 | pipe_config->name.gmch_n, \ | |
12583 | pipe_config->name.link_m, \ | |
12584 | pipe_config->name.link_n); \ | |
12585 | ret = false; \ | |
88adfff1 DV |
12586 | } |
12587 | ||
b95af8be VK |
12588 | /* This is required for BDW+ where there is only one set of registers for |
12589 | * switching between high and low RR. | |
12590 | * This macro can be used whenever a comparison has to be made between one | |
12591 | * hw state and multiple sw state variables. | |
12592 | */ | |
12593 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12594 | if ((current_config->name != pipe_config->name) && \ | |
12595 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12596 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12597 | "(expected %i or %i, found %i)\n", \ |
12598 | current_config->name, \ | |
12599 | current_config->alt_name, \ | |
12600 | pipe_config->name); \ | |
cfb23ed6 | 12601 | ret = false; \ |
b95af8be VK |
12602 | } |
12603 | ||
1bd1bd80 DV |
12604 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12605 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12606 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12607 | "(expected %i, found %i)\n", \ |
12608 | current_config->name & (mask), \ | |
12609 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12610 | ret = false; \ |
1bd1bd80 DV |
12611 | } |
12612 | ||
5e550656 VS |
12613 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12614 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12615 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12616 | "(expected %i, found %i)\n", \ |
12617 | current_config->name, \ | |
12618 | pipe_config->name); \ | |
cfb23ed6 | 12619 | ret = false; \ |
5e550656 VS |
12620 | } |
12621 | ||
bb760063 DV |
12622 | #define PIPE_CONF_QUIRK(quirk) \ |
12623 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12624 | ||
eccb140b DV |
12625 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12626 | ||
08a24034 DV |
12627 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12628 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12629 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12630 | |
eb14cb74 | 12631 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12632 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12633 | |
12634 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12635 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12636 | ||
cfb23ed6 ML |
12637 | if (current_config->has_drrs) |
12638 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12639 | } else | |
12640 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12641 | |
a65347ba JN |
12642 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12643 | ||
2d112de7 ACO |
12644 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12645 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12646 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12647 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12648 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12649 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12650 | |
2d112de7 ACO |
12651 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12652 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12653 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12654 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12655 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12656 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12657 | |
c93f54cf | 12658 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12659 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12660 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12661 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12662 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12663 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12664 | |
9ed109a7 DV |
12665 | PIPE_CONF_CHECK_I(has_audio); |
12666 | ||
2d112de7 | 12667 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12668 | DRM_MODE_FLAG_INTERLACE); |
12669 | ||
bb760063 | 12670 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12671 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12672 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12673 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12674 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12675 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12676 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12677 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12678 | DRM_MODE_FLAG_NVSYNC); |
12679 | } | |
045ac3b5 | 12680 | |
333b8ca8 | 12681 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12682 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12683 | if (INTEL_INFO(dev)->gen < 4) | |
12684 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12685 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12686 | |
bfd16b2a ML |
12687 | if (!adjust) { |
12688 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12689 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12690 | ||
12691 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12692 | if (current_config->pch_pfit.enabled) { | |
12693 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12694 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12695 | } | |
2fa2fe9a | 12696 | |
7aefe2b5 ML |
12697 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12698 | } | |
a1b2278e | 12699 | |
e59150dc JB |
12700 | /* BDW+ don't expose a synchronous way to read the state */ |
12701 | if (IS_HASWELL(dev)) | |
12702 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12703 | |
282740f7 VS |
12704 | PIPE_CONF_CHECK_I(double_wide); |
12705 | ||
26804afd DV |
12706 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12707 | ||
c0d43d62 | 12708 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12709 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12710 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12711 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12712 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12713 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12714 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12715 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12716 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12717 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12718 | |
42571aef VS |
12719 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12720 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12721 | ||
2d112de7 | 12722 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12723 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12724 | |
66e985c0 | 12725 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12726 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12727 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12728 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12729 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12730 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12731 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12732 | |
cfb23ed6 | 12733 | return ret; |
0e8ffe1b DV |
12734 | } |
12735 | ||
08db6652 DL |
12736 | static void check_wm_state(struct drm_device *dev) |
12737 | { | |
12738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12739 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12740 | struct intel_crtc *intel_crtc; | |
12741 | int plane; | |
12742 | ||
12743 | if (INTEL_INFO(dev)->gen < 9) | |
12744 | return; | |
12745 | ||
12746 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12747 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12748 | ||
12749 | for_each_intel_crtc(dev, intel_crtc) { | |
12750 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12751 | const enum pipe pipe = intel_crtc->pipe; | |
12752 | ||
12753 | if (!intel_crtc->active) | |
12754 | continue; | |
12755 | ||
12756 | /* planes */ | |
dd740780 | 12757 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12758 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12759 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12760 | ||
12761 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12762 | continue; | |
12763 | ||
12764 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12765 | "(expected (%u,%u), found (%u,%u))\n", | |
12766 | pipe_name(pipe), plane + 1, | |
12767 | sw_entry->start, sw_entry->end, | |
12768 | hw_entry->start, hw_entry->end); | |
12769 | } | |
12770 | ||
12771 | /* cursor */ | |
4969d33e MR |
12772 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12773 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12774 | |
12775 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12776 | continue; | |
12777 | ||
12778 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12779 | "(expected (%u,%u), found (%u,%u))\n", | |
12780 | pipe_name(pipe), | |
12781 | sw_entry->start, sw_entry->end, | |
12782 | hw_entry->start, hw_entry->end); | |
12783 | } | |
12784 | } | |
12785 | ||
91d1b4bd | 12786 | static void |
35dd3c64 ML |
12787 | check_connector_state(struct drm_device *dev, |
12788 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12789 | { |
35dd3c64 ML |
12790 | struct drm_connector_state *old_conn_state; |
12791 | struct drm_connector *connector; | |
12792 | int i; | |
8af6cf88 | 12793 | |
35dd3c64 ML |
12794 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12795 | struct drm_encoder *encoder = connector->encoder; | |
12796 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12797 | |
8af6cf88 DV |
12798 | /* This also checks the encoder/connector hw state with the |
12799 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12800 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12801 | |
ad3c558f | 12802 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12803 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12804 | } |
91d1b4bd DV |
12805 | } |
12806 | ||
12807 | static void | |
12808 | check_encoder_state(struct drm_device *dev) | |
12809 | { | |
12810 | struct intel_encoder *encoder; | |
12811 | struct intel_connector *connector; | |
8af6cf88 | 12812 | |
b2784e15 | 12813 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12814 | bool enabled = false; |
4d20cd86 | 12815 | enum pipe pipe; |
8af6cf88 DV |
12816 | |
12817 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12818 | encoder->base.base.id, | |
8e329a03 | 12819 | encoder->base.name); |
8af6cf88 | 12820 | |
3a3371ff | 12821 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12822 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12823 | continue; |
12824 | enabled = true; | |
ad3c558f ML |
12825 | |
12826 | I915_STATE_WARN(connector->base.state->crtc != | |
12827 | encoder->base.crtc, | |
12828 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12829 | } |
0e32b39c | 12830 | |
e2c719b7 | 12831 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12832 | "encoder's enabled state mismatch " |
12833 | "(expected %i, found %i)\n", | |
12834 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12835 | |
12836 | if (!encoder->base.crtc) { | |
4d20cd86 | 12837 | bool active; |
7c60d198 | 12838 | |
4d20cd86 ML |
12839 | active = encoder->get_hw_state(encoder, &pipe); |
12840 | I915_STATE_WARN(active, | |
12841 | "encoder detached but still enabled on pipe %c.\n", | |
12842 | pipe_name(pipe)); | |
7c60d198 | 12843 | } |
8af6cf88 | 12844 | } |
91d1b4bd DV |
12845 | } |
12846 | ||
12847 | static void | |
4d20cd86 | 12848 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12849 | { |
fbee40df | 12850 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12851 | struct intel_encoder *encoder; |
4d20cd86 ML |
12852 | struct drm_crtc_state *old_crtc_state; |
12853 | struct drm_crtc *crtc; | |
12854 | int i; | |
8af6cf88 | 12855 | |
4d20cd86 ML |
12856 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12858 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12859 | bool active; |
8af6cf88 | 12860 | |
bfd16b2a ML |
12861 | if (!needs_modeset(crtc->state) && |
12862 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12863 | continue; |
045ac3b5 | 12864 | |
4d20cd86 ML |
12865 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12866 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12867 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12868 | pipe_config->base.crtc = crtc; | |
12869 | pipe_config->base.state = old_state; | |
8af6cf88 | 12870 | |
4d20cd86 ML |
12871 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12872 | crtc->base.id); | |
8af6cf88 | 12873 | |
4d20cd86 ML |
12874 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12875 | pipe_config); | |
d62cf62a | 12876 | |
b6b5d049 | 12877 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12878 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12879 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12880 | active = crtc->state->active; | |
6c49f241 | 12881 | |
4d20cd86 | 12882 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12883 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12884 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12885 | |
4d20cd86 | 12886 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12887 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12888 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12889 | ||
12890 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12891 | enum pipe pipe; | |
12892 | ||
12893 | active = encoder->get_hw_state(encoder, &pipe); | |
12894 | I915_STATE_WARN(active != crtc->state->active, | |
12895 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12896 | encoder->base.base.id, active, crtc->state->active); | |
12897 | ||
12898 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12899 | "Encoder connected to wrong pipe %c\n", | |
12900 | pipe_name(pipe)); | |
12901 | ||
12902 | if (active) | |
12903 | encoder->get_config(encoder, pipe_config); | |
12904 | } | |
53d9f4e9 | 12905 | |
4d20cd86 | 12906 | if (!crtc->state->active) |
cfb23ed6 ML |
12907 | continue; |
12908 | ||
4d20cd86 ML |
12909 | sw_config = to_intel_crtc_state(crtc->state); |
12910 | if (!intel_pipe_config_compare(dev, sw_config, | |
12911 | pipe_config, false)) { | |
e2c719b7 | 12912 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12913 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12914 | "[hw state]"); |
4d20cd86 | 12915 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12916 | "[sw state]"); |
12917 | } | |
8af6cf88 DV |
12918 | } |
12919 | } | |
12920 | ||
91d1b4bd DV |
12921 | static void |
12922 | check_shared_dpll_state(struct drm_device *dev) | |
12923 | { | |
fbee40df | 12924 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12925 | struct intel_crtc *crtc; |
12926 | struct intel_dpll_hw_state dpll_hw_state; | |
12927 | int i; | |
5358901f DV |
12928 | |
12929 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12930 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12931 | int enabled_crtcs = 0, active_crtcs = 0; | |
12932 | bool active; | |
12933 | ||
12934 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12935 | ||
12936 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12937 | ||
12938 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12939 | ||
e2c719b7 | 12940 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12941 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12942 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12943 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12944 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12945 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12946 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12947 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12948 | "pll on state mismatch (expected %i, found %i)\n", |
12949 | pll->on, active); | |
12950 | ||
d3fcc808 | 12951 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12952 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12953 | enabled_crtcs++; |
12954 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12955 | active_crtcs++; | |
12956 | } | |
e2c719b7 | 12957 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12958 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12959 | pll->active, active_crtcs); | |
e2c719b7 | 12960 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12961 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12962 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12963 | |
e2c719b7 | 12964 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12965 | sizeof(dpll_hw_state)), |
12966 | "pll hw state mismatch\n"); | |
5358901f | 12967 | } |
8af6cf88 DV |
12968 | } |
12969 | ||
ee165b1a ML |
12970 | static void |
12971 | intel_modeset_check_state(struct drm_device *dev, | |
12972 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12973 | { |
08db6652 | 12974 | check_wm_state(dev); |
35dd3c64 | 12975 | check_connector_state(dev, old_state); |
91d1b4bd | 12976 | check_encoder_state(dev); |
4d20cd86 | 12977 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12978 | check_shared_dpll_state(dev); |
12979 | } | |
12980 | ||
5cec258b | 12981 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12982 | int dotclock) |
12983 | { | |
12984 | /* | |
12985 | * FDI already provided one idea for the dotclock. | |
12986 | * Yell if the encoder disagrees. | |
12987 | */ | |
2d112de7 | 12988 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12989 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12990 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12991 | } |
12992 | ||
80715b2f VS |
12993 | static void update_scanline_offset(struct intel_crtc *crtc) |
12994 | { | |
12995 | struct drm_device *dev = crtc->base.dev; | |
12996 | ||
12997 | /* | |
12998 | * The scanline counter increments at the leading edge of hsync. | |
12999 | * | |
13000 | * On most platforms it starts counting from vtotal-1 on the | |
13001 | * first active line. That means the scanline counter value is | |
13002 | * always one less than what we would expect. Ie. just after | |
13003 | * start of vblank, which also occurs at start of hsync (on the | |
13004 | * last active line), the scanline counter will read vblank_start-1. | |
13005 | * | |
13006 | * On gen2 the scanline counter starts counting from 1 instead | |
13007 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13008 | * to keep the value positive), instead of adding one. | |
13009 | * | |
13010 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13011 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13012 | * there's an extra 1 line difference. So we need to add two instead of | |
13013 | * one to the value. | |
13014 | */ | |
13015 | if (IS_GEN2(dev)) { | |
124abe07 | 13016 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13017 | int vtotal; |
13018 | ||
124abe07 VS |
13019 | vtotal = adjusted_mode->crtc_vtotal; |
13020 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13021 | vtotal /= 2; |
13022 | ||
13023 | crtc->scanline_offset = vtotal - 1; | |
13024 | } else if (HAS_DDI(dev) && | |
409ee761 | 13025 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13026 | crtc->scanline_offset = 2; |
13027 | } else | |
13028 | crtc->scanline_offset = 1; | |
13029 | } | |
13030 | ||
ad421372 | 13031 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13032 | { |
225da59b | 13033 | struct drm_device *dev = state->dev; |
ed6739ef | 13034 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13035 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13036 | struct drm_crtc *crtc; |
13037 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13038 | int i; |
ed6739ef ACO |
13039 | |
13040 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13041 | return; |
ed6739ef | 13042 | |
0a9ab303 | 13043 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13045 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13046 | |
fb1a38a9 | 13047 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13048 | continue; |
13049 | ||
fb1a38a9 ML |
13050 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13051 | ||
13052 | if (old_dpll == DPLL_ID_PRIVATE) | |
13053 | continue; | |
0a9ab303 | 13054 | |
ad421372 ML |
13055 | if (!shared_dpll) |
13056 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13057 | |
fb1a38a9 | 13058 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13059 | } |
ed6739ef ACO |
13060 | } |
13061 | ||
99d736a2 ML |
13062 | /* |
13063 | * This implements the workaround described in the "notes" section of the mode | |
13064 | * set sequence documentation. When going from no pipes or single pipe to | |
13065 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13066 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13067 | */ | |
13068 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13069 | { | |
13070 | struct drm_crtc_state *crtc_state; | |
13071 | struct intel_crtc *intel_crtc; | |
13072 | struct drm_crtc *crtc; | |
13073 | struct intel_crtc_state *first_crtc_state = NULL; | |
13074 | struct intel_crtc_state *other_crtc_state = NULL; | |
13075 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13076 | int i; | |
13077 | ||
13078 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13079 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13080 | intel_crtc = to_intel_crtc(crtc); | |
13081 | ||
13082 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13083 | continue; | |
13084 | ||
13085 | if (first_crtc_state) { | |
13086 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13087 | break; | |
13088 | } else { | |
13089 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13090 | first_pipe = intel_crtc->pipe; | |
13091 | } | |
13092 | } | |
13093 | ||
13094 | /* No workaround needed? */ | |
13095 | if (!first_crtc_state) | |
13096 | return 0; | |
13097 | ||
13098 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13099 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13100 | struct intel_crtc_state *pipe_config; | |
13101 | ||
13102 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13103 | if (IS_ERR(pipe_config)) | |
13104 | return PTR_ERR(pipe_config); | |
13105 | ||
13106 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13107 | ||
13108 | if (!pipe_config->base.active || | |
13109 | needs_modeset(&pipe_config->base)) | |
13110 | continue; | |
13111 | ||
13112 | /* 2 or more enabled crtcs means no need for w/a */ | |
13113 | if (enabled_pipe != INVALID_PIPE) | |
13114 | return 0; | |
13115 | ||
13116 | enabled_pipe = intel_crtc->pipe; | |
13117 | } | |
13118 | ||
13119 | if (enabled_pipe != INVALID_PIPE) | |
13120 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13121 | else if (other_crtc_state) | |
13122 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13123 | ||
13124 | return 0; | |
13125 | } | |
13126 | ||
27c329ed ML |
13127 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13128 | { | |
13129 | struct drm_crtc *crtc; | |
13130 | struct drm_crtc_state *crtc_state; | |
13131 | int ret = 0; | |
13132 | ||
13133 | /* add all active pipes to the state */ | |
13134 | for_each_crtc(state->dev, crtc) { | |
13135 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13136 | if (IS_ERR(crtc_state)) | |
13137 | return PTR_ERR(crtc_state); | |
13138 | ||
13139 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13140 | continue; | |
13141 | ||
13142 | crtc_state->mode_changed = true; | |
13143 | ||
13144 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13145 | if (ret) | |
13146 | break; | |
13147 | ||
13148 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13149 | if (ret) | |
13150 | break; | |
13151 | } | |
13152 | ||
13153 | return ret; | |
13154 | } | |
13155 | ||
c347a676 | 13156 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13157 | { |
565602d7 ML |
13158 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13159 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13160 | struct drm_crtc *crtc; | |
13161 | struct drm_crtc_state *crtc_state; | |
13162 | int ret = 0, i; | |
054518dd | 13163 | |
b359283a ML |
13164 | if (!check_digital_port_conflicts(state)) { |
13165 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13166 | return -EINVAL; | |
13167 | } | |
13168 | ||
565602d7 ML |
13169 | intel_state->modeset = true; |
13170 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13171 | ||
13172 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13173 | if (crtc_state->active) | |
13174 | intel_state->active_crtcs |= 1 << i; | |
13175 | else | |
13176 | intel_state->active_crtcs &= ~(1 << i); | |
13177 | } | |
13178 | ||
054518dd ACO |
13179 | /* |
13180 | * See if the config requires any additional preparation, e.g. | |
13181 | * to adjust global state with pipes off. We need to do this | |
13182 | * here so we can get the modeset_pipe updated config for the new | |
13183 | * mode set on this crtc. For other crtcs we need to use the | |
13184 | * adjusted_mode bits in the crtc directly. | |
13185 | */ | |
27c329ed | 13186 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13187 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13188 | ||
1a617b77 | 13189 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13190 | ret = intel_modeset_all_pipes(state); |
13191 | ||
13192 | if (ret < 0) | |
054518dd | 13193 | return ret; |
e8788cbc ML |
13194 | |
13195 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13196 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13197 | } else |
1a617b77 | 13198 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13199 | |
ad421372 | 13200 | intel_modeset_clear_plls(state); |
054518dd | 13201 | |
565602d7 | 13202 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13203 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13204 | |
ad421372 | 13205 | return 0; |
c347a676 ACO |
13206 | } |
13207 | ||
aa363136 MR |
13208 | /* |
13209 | * Handle calculation of various watermark data at the end of the atomic check | |
13210 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13211 | * handlers to ensure that all derived state has been updated. | |
13212 | */ | |
13213 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13214 | { | |
13215 | struct drm_device *dev = state->dev; | |
13216 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13217 | struct drm_crtc *crtc; | |
13218 | struct drm_crtc_state *cstate; | |
13219 | struct drm_plane *plane; | |
13220 | struct drm_plane_state *pstate; | |
13221 | ||
13222 | /* | |
13223 | * Calculate watermark configuration details now that derived | |
13224 | * plane/crtc state is all properly updated. | |
13225 | */ | |
13226 | drm_for_each_crtc(crtc, dev) { | |
13227 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13228 | crtc->state; | |
13229 | ||
13230 | if (cstate->active) | |
13231 | intel_state->wm_config.num_pipes_active++; | |
13232 | } | |
13233 | drm_for_each_legacy_plane(plane, dev) { | |
13234 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13235 | plane->state; | |
13236 | ||
13237 | if (!to_intel_plane_state(pstate)->visible) | |
13238 | continue; | |
13239 | ||
13240 | intel_state->wm_config.sprites_enabled = true; | |
13241 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13242 | pstate->crtc_h != pstate->src_h >> 16) | |
13243 | intel_state->wm_config.sprites_scaled = true; | |
13244 | } | |
13245 | } | |
13246 | ||
74c090b1 ML |
13247 | /** |
13248 | * intel_atomic_check - validate state object | |
13249 | * @dev: drm device | |
13250 | * @state: state to validate | |
13251 | */ | |
13252 | static int intel_atomic_check(struct drm_device *dev, | |
13253 | struct drm_atomic_state *state) | |
c347a676 | 13254 | { |
dd8b3bdb | 13255 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13256 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13257 | struct drm_crtc *crtc; |
13258 | struct drm_crtc_state *crtc_state; | |
13259 | int ret, i; | |
61333b60 | 13260 | bool any_ms = false; |
c347a676 | 13261 | |
74c090b1 | 13262 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13263 | if (ret) |
13264 | return ret; | |
13265 | ||
c347a676 | 13266 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13267 | struct intel_crtc_state *pipe_config = |
13268 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13269 | |
ba8af3e5 ML |
13270 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13271 | sizeof(struct intel_crtc_atomic_commit)); | |
13272 | ||
1ed51de9 DV |
13273 | /* Catch I915_MODE_FLAG_INHERITED */ |
13274 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13275 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13276 | |
61333b60 ML |
13277 | if (!crtc_state->enable) { |
13278 | if (needs_modeset(crtc_state)) | |
13279 | any_ms = true; | |
c347a676 | 13280 | continue; |
61333b60 | 13281 | } |
c347a676 | 13282 | |
26495481 | 13283 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13284 | continue; |
13285 | ||
26495481 DV |
13286 | /* FIXME: For only active_changed we shouldn't need to do any |
13287 | * state recomputation at all. */ | |
13288 | ||
1ed51de9 DV |
13289 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13290 | if (ret) | |
13291 | return ret; | |
b359283a | 13292 | |
cfb23ed6 | 13293 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13294 | if (ret) |
13295 | return ret; | |
13296 | ||
73831236 | 13297 | if (i915.fastboot && |
dd8b3bdb | 13298 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13299 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13300 | pipe_config, true)) { |
26495481 | 13301 | crtc_state->mode_changed = false; |
bfd16b2a | 13302 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13303 | } |
13304 | ||
13305 | if (needs_modeset(crtc_state)) { | |
13306 | any_ms = true; | |
cfb23ed6 ML |
13307 | |
13308 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13309 | if (ret) | |
13310 | return ret; | |
13311 | } | |
61333b60 | 13312 | |
26495481 DV |
13313 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13314 | needs_modeset(crtc_state) ? | |
13315 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13316 | } |
13317 | ||
61333b60 ML |
13318 | if (any_ms) { |
13319 | ret = intel_modeset_checks(state); | |
13320 | ||
13321 | if (ret) | |
13322 | return ret; | |
27c329ed | 13323 | } else |
dd8b3bdb | 13324 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13325 | |
dd8b3bdb | 13326 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13327 | if (ret) |
13328 | return ret; | |
13329 | ||
f51be2e0 | 13330 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13331 | calc_watermark_data(state); |
13332 | ||
13333 | return 0; | |
054518dd ACO |
13334 | } |
13335 | ||
5008e874 ML |
13336 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13337 | struct drm_atomic_state *state, | |
13338 | bool async) | |
13339 | { | |
7580d774 ML |
13340 | struct drm_i915_private *dev_priv = dev->dev_private; |
13341 | struct drm_plane_state *plane_state; | |
5008e874 | 13342 | struct drm_crtc_state *crtc_state; |
7580d774 | 13343 | struct drm_plane *plane; |
5008e874 ML |
13344 | struct drm_crtc *crtc; |
13345 | int i, ret; | |
13346 | ||
13347 | if (async) { | |
13348 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13349 | return -EINVAL; | |
13350 | } | |
13351 | ||
13352 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13353 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13354 | if (ret) | |
13355 | return ret; | |
7580d774 ML |
13356 | |
13357 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13358 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13359 | } |
13360 | ||
f935675f ML |
13361 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13362 | if (ret) | |
13363 | return ret; | |
13364 | ||
5008e874 | 13365 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13366 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13367 | u32 reset_counter; | |
13368 | ||
13369 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13370 | mutex_unlock(&dev->struct_mutex); | |
13371 | ||
13372 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13373 | struct intel_plane_state *intel_plane_state = | |
13374 | to_intel_plane_state(plane_state); | |
13375 | ||
13376 | if (!intel_plane_state->wait_req) | |
13377 | continue; | |
13378 | ||
13379 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13380 | reset_counter, true, | |
13381 | NULL, NULL); | |
13382 | ||
13383 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13384 | if (ret == -EIO) | |
13385 | ret = 0; | |
13386 | ||
13387 | if (ret) | |
13388 | break; | |
13389 | } | |
13390 | ||
13391 | if (!ret) | |
13392 | return 0; | |
13393 | ||
13394 | mutex_lock(&dev->struct_mutex); | |
13395 | drm_atomic_helper_cleanup_planes(dev, state); | |
13396 | } | |
5008e874 | 13397 | |
f935675f | 13398 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13399 | return ret; |
13400 | } | |
13401 | ||
e8861675 ML |
13402 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13403 | struct drm_i915_private *dev_priv, | |
13404 | unsigned crtc_mask) | |
13405 | { | |
13406 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13407 | enum pipe pipe; | |
13408 | int ret; | |
13409 | ||
13410 | if (!crtc_mask) | |
13411 | return; | |
13412 | ||
13413 | for_each_pipe(dev_priv, pipe) { | |
13414 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13415 | ||
13416 | if (!((1 << pipe) & crtc_mask)) | |
13417 | continue; | |
13418 | ||
13419 | ret = drm_crtc_vblank_get(crtc); | |
13420 | if (WARN_ON(ret != 0)) { | |
13421 | crtc_mask &= ~(1 << pipe); | |
13422 | continue; | |
13423 | } | |
13424 | ||
13425 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13426 | } | |
13427 | ||
13428 | for_each_pipe(dev_priv, pipe) { | |
13429 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13430 | long lret; | |
13431 | ||
13432 | if (!((1 << pipe) & crtc_mask)) | |
13433 | continue; | |
13434 | ||
13435 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13436 | last_vblank_count[pipe] != | |
13437 | drm_crtc_vblank_count(crtc), | |
13438 | msecs_to_jiffies(50)); | |
13439 | ||
13440 | WARN_ON(!lret); | |
13441 | ||
13442 | drm_crtc_vblank_put(crtc); | |
13443 | } | |
13444 | } | |
13445 | ||
13446 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13447 | { | |
13448 | /* fb updated, need to unpin old fb */ | |
13449 | if (crtc_state->fb_changed) | |
13450 | return true; | |
13451 | ||
13452 | /* wm changes, need vblank before final wm's */ | |
13453 | if (crtc_state->wm_changed) | |
13454 | return true; | |
13455 | ||
13456 | /* | |
13457 | * cxsr is re-enabled after vblank. | |
13458 | * This is already handled by crtc_state->wm_changed, | |
13459 | * but added for clarity. | |
13460 | */ | |
13461 | if (crtc_state->disable_cxsr) | |
13462 | return true; | |
13463 | ||
13464 | return false; | |
13465 | } | |
13466 | ||
74c090b1 ML |
13467 | /** |
13468 | * intel_atomic_commit - commit validated state object | |
13469 | * @dev: DRM device | |
13470 | * @state: the top-level driver state object | |
13471 | * @async: asynchronous commit | |
13472 | * | |
13473 | * This function commits a top-level state object that has been validated | |
13474 | * with drm_atomic_helper_check(). | |
13475 | * | |
13476 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13477 | * we can only handle plane-related operations and do not yet support | |
13478 | * asynchronous commit. | |
13479 | * | |
13480 | * RETURNS | |
13481 | * Zero for success or -errno. | |
13482 | */ | |
13483 | static int intel_atomic_commit(struct drm_device *dev, | |
13484 | struct drm_atomic_state *state, | |
13485 | bool async) | |
a6778b3c | 13486 | { |
565602d7 | 13487 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13488 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13489 | struct drm_crtc_state *crtc_state; |
7580d774 | 13490 | struct drm_crtc *crtc; |
565602d7 ML |
13491 | int ret = 0, i; |
13492 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13493 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13494 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13495 | |
5008e874 | 13496 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13497 | if (ret) { |
13498 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13499 | return ret; |
7580d774 | 13500 | } |
d4afb8cc | 13501 | |
1c5e19f8 | 13502 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13503 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13504 | |
565602d7 ML |
13505 | if (intel_state->modeset) { |
13506 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13507 | sizeof(intel_state->min_pixclk)); | |
13508 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13509 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13510 | |
13511 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13512 | } |
13513 | ||
0a9ab303 | 13514 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13516 | ||
33c8df89 ML |
13517 | if (needs_modeset(crtc->state) || |
13518 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13519 | hw_check = true; | |
13520 | ||
13521 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13522 | modeset_get_crtc_power_domains(crtc, | |
13523 | to_intel_crtc_state(crtc->state)); | |
13524 | } | |
13525 | ||
61333b60 ML |
13526 | if (!needs_modeset(crtc->state)) |
13527 | continue; | |
13528 | ||
5c74cd73 | 13529 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13530 | |
a539205a ML |
13531 | if (crtc_state->active) { |
13532 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13533 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13534 | intel_crtc->active = false; |
58f9c0bc | 13535 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13536 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13537 | |
13538 | /* | |
13539 | * Underruns don't always raise | |
13540 | * interrupts, so check manually. | |
13541 | */ | |
13542 | intel_check_cpu_fifo_underruns(dev_priv); | |
13543 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13544 | |
13545 | if (!crtc->state->active) | |
13546 | intel_update_watermarks(crtc); | |
a539205a | 13547 | } |
b8cecdf5 | 13548 | } |
7758a113 | 13549 | |
ea9d758d DV |
13550 | /* Only after disabling all output pipelines that will be changed can we |
13551 | * update the the output configuration. */ | |
4740b0f2 | 13552 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13553 | |
565602d7 | 13554 | if (intel_state->modeset) { |
4740b0f2 ML |
13555 | intel_shared_dpll_commit(state); |
13556 | ||
13557 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
33c8df89 ML |
13558 | |
13559 | if (dev_priv->display.modeset_commit_cdclk && | |
13560 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13561 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13562 | } |
47fab737 | 13563 | |
a6778b3c | 13564 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13565 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13567 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13568 | struct intel_crtc_state *pipe_config = |
13569 | to_intel_crtc_state(crtc->state); | |
13570 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13571 | |
f6ac4b2a | 13572 | if (modeset && crtc->state->active) { |
a539205a ML |
13573 | update_scanline_offset(to_intel_crtc(crtc)); |
13574 | dev_priv->display.crtc_enable(crtc); | |
13575 | } | |
80715b2f | 13576 | |
f6ac4b2a | 13577 | if (!modeset) |
5c74cd73 | 13578 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13579 | |
49227c4a PZ |
13580 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13581 | intel_fbc_enable(intel_crtc); | |
13582 | ||
6173ee28 ML |
13583 | if (crtc->state->active && |
13584 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13585 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a | 13586 | |
e8861675 ML |
13587 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13588 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13589 | } |
a6778b3c | 13590 | |
a6778b3c | 13591 | /* FIXME: add subpixel order */ |
83a57153 | 13592 | |
e8861675 ML |
13593 | if (!state->legacy_cursor_update) |
13594 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13595 | |
33c8df89 | 13596 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
e8861675 ML |
13597 | intel_post_plane_update(to_intel_crtc(crtc)); |
13598 | ||
33c8df89 ML |
13599 | if (put_domains[i]) |
13600 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13601 | } | |
13602 | ||
13603 | if (intel_state->modeset) | |
13604 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13605 | ||
f935675f | 13606 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13607 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13608 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13609 | |
565602d7 | 13610 | if (hw_check) |
ee165b1a ML |
13611 | intel_modeset_check_state(dev, state); |
13612 | ||
13613 | drm_atomic_state_free(state); | |
f30da187 | 13614 | |
75714940 MK |
13615 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13616 | * of triggering bugs in unclaimed access. After we finish | |
13617 | * modesetting, see if an error has been flagged, and if so | |
13618 | * enable debugging for the next modeset - and hope we catch | |
13619 | * the culprit. | |
13620 | * | |
13621 | * XXX note that we assume display power is on at this point. | |
13622 | * This might hold true now but we need to add pm helper to check | |
13623 | * unclaimed only when the hardware is on, as atomic commits | |
13624 | * can happen also when the device is completely off. | |
13625 | */ | |
13626 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13627 | ||
74c090b1 | 13628 | return 0; |
7f27126e JB |
13629 | } |
13630 | ||
c0c36b94 CW |
13631 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13632 | { | |
83a57153 ACO |
13633 | struct drm_device *dev = crtc->dev; |
13634 | struct drm_atomic_state *state; | |
e694eb02 | 13635 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13636 | int ret; |
83a57153 ACO |
13637 | |
13638 | state = drm_atomic_state_alloc(dev); | |
13639 | if (!state) { | |
e694eb02 | 13640 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13641 | crtc->base.id); |
13642 | return; | |
13643 | } | |
13644 | ||
e694eb02 | 13645 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13646 | |
e694eb02 ML |
13647 | retry: |
13648 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13649 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13650 | if (!ret) { | |
13651 | if (!crtc_state->active) | |
13652 | goto out; | |
83a57153 | 13653 | |
e694eb02 | 13654 | crtc_state->mode_changed = true; |
74c090b1 | 13655 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13656 | } |
13657 | ||
e694eb02 ML |
13658 | if (ret == -EDEADLK) { |
13659 | drm_atomic_state_clear(state); | |
13660 | drm_modeset_backoff(state->acquire_ctx); | |
13661 | goto retry; | |
4ed9fb37 | 13662 | } |
4be07317 | 13663 | |
2bfb4627 | 13664 | if (ret) |
e694eb02 | 13665 | out: |
2bfb4627 | 13666 | drm_atomic_state_free(state); |
c0c36b94 CW |
13667 | } |
13668 | ||
25c5b266 DV |
13669 | #undef for_each_intel_crtc_masked |
13670 | ||
f6e5b160 | 13671 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13672 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13673 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13674 | .destroy = intel_crtc_destroy, |
13675 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13676 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13677 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13678 | }; |
13679 | ||
5358901f DV |
13680 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13681 | struct intel_shared_dpll *pll, | |
13682 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13683 | { |
5358901f | 13684 | uint32_t val; |
ee7b9f93 | 13685 | |
12fda387 | 13686 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13687 | return false; |
13688 | ||
5358901f | 13689 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13690 | hw_state->dpll = val; |
13691 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13692 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f | 13693 | |
12fda387 ID |
13694 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
13695 | ||
5358901f DV |
13696 | return val & DPLL_VCO_ENABLE; |
13697 | } | |
13698 | ||
15bdd4cf DV |
13699 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13700 | struct intel_shared_dpll *pll) | |
13701 | { | |
3e369b76 ACO |
13702 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13703 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13704 | } |
13705 | ||
e7b903d2 DV |
13706 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13707 | struct intel_shared_dpll *pll) | |
13708 | { | |
e7b903d2 | 13709 | /* PCH refclock must be enabled first */ |
89eff4be | 13710 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13711 | |
3e369b76 | 13712 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13713 | |
13714 | /* Wait for the clocks to stabilize. */ | |
13715 | POSTING_READ(PCH_DPLL(pll->id)); | |
13716 | udelay(150); | |
13717 | ||
13718 | /* The pixel multiplier can only be updated once the | |
13719 | * DPLL is enabled and the clocks are stable. | |
13720 | * | |
13721 | * So write it again. | |
13722 | */ | |
3e369b76 | 13723 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13724 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13725 | udelay(200); |
13726 | } | |
13727 | ||
13728 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13729 | struct intel_shared_dpll *pll) | |
13730 | { | |
13731 | struct drm_device *dev = dev_priv->dev; | |
13732 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13733 | |
13734 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13735 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13736 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13737 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13738 | } |
13739 | ||
15bdd4cf DV |
13740 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13741 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13742 | udelay(200); |
13743 | } | |
13744 | ||
46edb027 DV |
13745 | static char *ibx_pch_dpll_names[] = { |
13746 | "PCH DPLL A", | |
13747 | "PCH DPLL B", | |
13748 | }; | |
13749 | ||
7c74ade1 | 13750 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13751 | { |
e7b903d2 | 13752 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13753 | int i; |
13754 | ||
7c74ade1 | 13755 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13756 | |
e72f9fbf | 13757 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13758 | dev_priv->shared_dplls[i].id = i; |
13759 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13760 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13761 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13762 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13763 | dev_priv->shared_dplls[i].get_hw_state = |
13764 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13765 | } |
13766 | } | |
13767 | ||
7c74ade1 DV |
13768 | static void intel_shared_dpll_init(struct drm_device *dev) |
13769 | { | |
e7b903d2 | 13770 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13771 | |
9cd86933 DV |
13772 | if (HAS_DDI(dev)) |
13773 | intel_ddi_pll_init(dev); | |
13774 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13775 | ibx_pch_dpll_init(dev); |
13776 | else | |
13777 | dev_priv->num_shared_dpll = 0; | |
13778 | ||
13779 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13780 | } |
13781 | ||
6beb8c23 MR |
13782 | /** |
13783 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13784 | * @plane: drm plane to prepare for | |
13785 | * @fb: framebuffer to prepare for presentation | |
13786 | * | |
13787 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13788 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13789 | * bits. Some older platforms need special physical address handling for | |
13790 | * cursor planes. | |
13791 | * | |
f935675f ML |
13792 | * Must be called with struct_mutex held. |
13793 | * | |
6beb8c23 MR |
13794 | * Returns 0 on success, negative error code on failure. |
13795 | */ | |
13796 | int | |
13797 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13798 | const struct drm_plane_state *new_state) |
465c120c MR |
13799 | { |
13800 | struct drm_device *dev = plane->dev; | |
844f9111 | 13801 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13802 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13803 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13804 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13805 | int ret = 0; |
465c120c | 13806 | |
1ee49399 | 13807 | if (!obj && !old_obj) |
465c120c MR |
13808 | return 0; |
13809 | ||
5008e874 ML |
13810 | if (old_obj) { |
13811 | struct drm_crtc_state *crtc_state = | |
13812 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13813 | ||
13814 | /* Big Hammer, we also need to ensure that any pending | |
13815 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13816 | * current scanout is retired before unpinning the old | |
13817 | * framebuffer. Note that we rely on userspace rendering | |
13818 | * into the buffer attached to the pipe they are waiting | |
13819 | * on. If not, userspace generates a GPU hang with IPEHR | |
13820 | * point to the MI_WAIT_FOR_EVENT. | |
13821 | * | |
13822 | * This should only fail upon a hung GPU, in which case we | |
13823 | * can safely continue. | |
13824 | */ | |
13825 | if (needs_modeset(crtc_state)) | |
13826 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13827 | ||
13828 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13829 | if (ret && ret != -EIO) | |
f935675f | 13830 | return ret; |
5008e874 ML |
13831 | } |
13832 | ||
3c28ff22 AG |
13833 | /* For framebuffer backed by dmabuf, wait for fence */ |
13834 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13835 | long lret; |
13836 | ||
13837 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13838 | false, true, | |
13839 | MAX_SCHEDULE_TIMEOUT); | |
13840 | if (lret == -ERESTARTSYS) | |
13841 | return lret; | |
3c28ff22 | 13842 | |
bcf8be27 | 13843 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13844 | } |
13845 | ||
1ee49399 ML |
13846 | if (!obj) { |
13847 | ret = 0; | |
13848 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13849 | INTEL_INFO(dev)->cursor_needs_physical) { |
13850 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13851 | ret = i915_gem_object_attach_phys(obj, align); | |
13852 | if (ret) | |
13853 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13854 | } else { | |
7580d774 | 13855 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13856 | } |
465c120c | 13857 | |
7580d774 ML |
13858 | if (ret == 0) { |
13859 | if (obj) { | |
13860 | struct intel_plane_state *plane_state = | |
13861 | to_intel_plane_state(new_state); | |
13862 | ||
13863 | i915_gem_request_assign(&plane_state->wait_req, | |
13864 | obj->last_write_req); | |
13865 | } | |
13866 | ||
a9ff8714 | 13867 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13868 | } |
fdd508a6 | 13869 | |
6beb8c23 MR |
13870 | return ret; |
13871 | } | |
13872 | ||
38f3ce3a MR |
13873 | /** |
13874 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13875 | * @plane: drm plane to clean up for | |
13876 | * @fb: old framebuffer that was on plane | |
13877 | * | |
13878 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13879 | * |
13880 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13881 | */ |
13882 | void | |
13883 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13884 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13885 | { |
13886 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13887 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13888 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13889 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13890 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13891 | |
7580d774 ML |
13892 | old_intel_state = to_intel_plane_state(old_state); |
13893 | ||
1ee49399 | 13894 | if (!obj && !old_obj) |
38f3ce3a MR |
13895 | return; |
13896 | ||
1ee49399 ML |
13897 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13898 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13899 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13900 | |
13901 | /* prepare_fb aborted? */ | |
13902 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13903 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13904 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13905 | |
13906 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13907 | ||
465c120c MR |
13908 | } |
13909 | ||
6156a456 CK |
13910 | int |
13911 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13912 | { | |
13913 | int max_scale; | |
13914 | struct drm_device *dev; | |
13915 | struct drm_i915_private *dev_priv; | |
13916 | int crtc_clock, cdclk; | |
13917 | ||
bf8a0af0 | 13918 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13919 | return DRM_PLANE_HELPER_NO_SCALING; |
13920 | ||
13921 | dev = intel_crtc->base.dev; | |
13922 | dev_priv = dev->dev_private; | |
13923 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13924 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13925 | |
54bf1ce6 | 13926 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13927 | return DRM_PLANE_HELPER_NO_SCALING; |
13928 | ||
13929 | /* | |
13930 | * skl max scale is lower of: | |
13931 | * close to 3 but not 3, -1 is for that purpose | |
13932 | * or | |
13933 | * cdclk/crtc_clock | |
13934 | */ | |
13935 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13936 | ||
13937 | return max_scale; | |
13938 | } | |
13939 | ||
465c120c | 13940 | static int |
3c692a41 | 13941 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13942 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13943 | struct intel_plane_state *state) |
13944 | { | |
2b875c22 MR |
13945 | struct drm_crtc *crtc = state->base.crtc; |
13946 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13947 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13948 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13949 | bool can_position = false; | |
465c120c | 13950 | |
693bdc28 VS |
13951 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13952 | /* use scaler when colorkey is not required */ | |
13953 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13954 | min_scale = 1; | |
13955 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13956 | } | |
d8106366 | 13957 | can_position = true; |
6156a456 | 13958 | } |
d8106366 | 13959 | |
061e4b8d ML |
13960 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13961 | &state->dst, &state->clip, | |
da20eabd ML |
13962 | min_scale, max_scale, |
13963 | can_position, true, | |
13964 | &state->visible); | |
14af293f GP |
13965 | } |
13966 | ||
613d2b27 ML |
13967 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13968 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13969 | { |
32b7eeec | 13970 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13972 | struct intel_crtc_state *old_intel_state = |
13973 | to_intel_crtc_state(old_crtc_state); | |
13974 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13975 | |
c34c9ee4 | 13976 | /* Perform vblank evasion around commit operation */ |
62852622 | 13977 | intel_pipe_update_start(intel_crtc); |
0583236e | 13978 | |
bfd16b2a ML |
13979 | if (modeset) |
13980 | return; | |
13981 | ||
13982 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13983 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13984 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13985 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13986 | } |
13987 | ||
613d2b27 ML |
13988 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13989 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13990 | { |
32b7eeec | 13991 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13992 | |
62852622 | 13993 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13994 | } |
13995 | ||
cf4c7c12 | 13996 | /** |
4a3b8769 MR |
13997 | * intel_plane_destroy - destroy a plane |
13998 | * @plane: plane to destroy | |
cf4c7c12 | 13999 | * |
4a3b8769 MR |
14000 | * Common destruction function for all types of planes (primary, cursor, |
14001 | * sprite). | |
cf4c7c12 | 14002 | */ |
4a3b8769 | 14003 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14004 | { |
14005 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14006 | drm_plane_cleanup(plane); | |
14007 | kfree(intel_plane); | |
14008 | } | |
14009 | ||
65a3fea0 | 14010 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14011 | .update_plane = drm_atomic_helper_update_plane, |
14012 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14013 | .destroy = intel_plane_destroy, |
c196e1d6 | 14014 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14015 | .atomic_get_property = intel_plane_atomic_get_property, |
14016 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14017 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14018 | .atomic_destroy_state = intel_plane_destroy_state, | |
14019 | ||
465c120c MR |
14020 | }; |
14021 | ||
14022 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14023 | int pipe) | |
14024 | { | |
14025 | struct intel_plane *primary; | |
8e7d688b | 14026 | struct intel_plane_state *state; |
465c120c | 14027 | const uint32_t *intel_primary_formats; |
45e3743a | 14028 | unsigned int num_formats; |
465c120c MR |
14029 | |
14030 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14031 | if (primary == NULL) | |
14032 | return NULL; | |
14033 | ||
8e7d688b MR |
14034 | state = intel_create_plane_state(&primary->base); |
14035 | if (!state) { | |
ea2c67bb MR |
14036 | kfree(primary); |
14037 | return NULL; | |
14038 | } | |
8e7d688b | 14039 | primary->base.state = &state->base; |
ea2c67bb | 14040 | |
465c120c MR |
14041 | primary->can_scale = false; |
14042 | primary->max_downscale = 1; | |
6156a456 CK |
14043 | if (INTEL_INFO(dev)->gen >= 9) { |
14044 | primary->can_scale = true; | |
af99ceda | 14045 | state->scaler_id = -1; |
6156a456 | 14046 | } |
465c120c MR |
14047 | primary->pipe = pipe; |
14048 | primary->plane = pipe; | |
a9ff8714 | 14049 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14050 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14051 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14052 | primary->plane = !pipe; | |
14053 | ||
6c0fd451 DL |
14054 | if (INTEL_INFO(dev)->gen >= 9) { |
14055 | intel_primary_formats = skl_primary_formats; | |
14056 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14057 | |
14058 | primary->update_plane = skylake_update_primary_plane; | |
14059 | primary->disable_plane = skylake_disable_primary_plane; | |
14060 | } else if (HAS_PCH_SPLIT(dev)) { | |
14061 | intel_primary_formats = i965_primary_formats; | |
14062 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14063 | ||
14064 | primary->update_plane = ironlake_update_primary_plane; | |
14065 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14066 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14067 | intel_primary_formats = i965_primary_formats; |
14068 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14069 | |
14070 | primary->update_plane = i9xx_update_primary_plane; | |
14071 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14072 | } else { |
14073 | intel_primary_formats = i8xx_primary_formats; | |
14074 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14075 | |
14076 | primary->update_plane = i9xx_update_primary_plane; | |
14077 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14078 | } |
14079 | ||
14080 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14081 | &intel_plane_funcs, |
465c120c | 14082 | intel_primary_formats, num_formats, |
b0b3b795 | 14083 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14084 | |
3b7a5119 SJ |
14085 | if (INTEL_INFO(dev)->gen >= 4) |
14086 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14087 | |
ea2c67bb MR |
14088 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14089 | ||
465c120c MR |
14090 | return &primary->base; |
14091 | } | |
14092 | ||
3b7a5119 SJ |
14093 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14094 | { | |
14095 | if (!dev->mode_config.rotation_property) { | |
14096 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14097 | BIT(DRM_ROTATE_180); | |
14098 | ||
14099 | if (INTEL_INFO(dev)->gen >= 9) | |
14100 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14101 | ||
14102 | dev->mode_config.rotation_property = | |
14103 | drm_mode_create_rotation_property(dev, flags); | |
14104 | } | |
14105 | if (dev->mode_config.rotation_property) | |
14106 | drm_object_attach_property(&plane->base.base, | |
14107 | dev->mode_config.rotation_property, | |
14108 | plane->base.state->rotation); | |
14109 | } | |
14110 | ||
3d7d6510 | 14111 | static int |
852e787c | 14112 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14113 | struct intel_crtc_state *crtc_state, |
852e787c | 14114 | struct intel_plane_state *state) |
3d7d6510 | 14115 | { |
061e4b8d | 14116 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14117 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14118 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14119 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14120 | unsigned stride; |
14121 | int ret; | |
3d7d6510 | 14122 | |
061e4b8d ML |
14123 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14124 | &state->dst, &state->clip, | |
3d7d6510 MR |
14125 | DRM_PLANE_HELPER_NO_SCALING, |
14126 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14127 | true, true, &state->visible); |
757f9a3e GP |
14128 | if (ret) |
14129 | return ret; | |
14130 | ||
757f9a3e GP |
14131 | /* if we want to turn off the cursor ignore width and height */ |
14132 | if (!obj) | |
da20eabd | 14133 | return 0; |
757f9a3e | 14134 | |
757f9a3e | 14135 | /* Check for which cursor types we support */ |
061e4b8d | 14136 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14137 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14138 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14139 | return -EINVAL; |
14140 | } | |
14141 | ||
ea2c67bb MR |
14142 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14143 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14144 | DRM_DEBUG_KMS("buffer is too small\n"); |
14145 | return -ENOMEM; | |
14146 | } | |
14147 | ||
3a656b54 | 14148 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14149 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14150 | return -EINVAL; |
32b7eeec MR |
14151 | } |
14152 | ||
b29ec92c VS |
14153 | /* |
14154 | * There's something wrong with the cursor on CHV pipe C. | |
14155 | * If it straddles the left edge of the screen then | |
14156 | * moving it away from the edge or disabling it often | |
14157 | * results in a pipe underrun, and often that can lead to | |
14158 | * dead pipe (constant underrun reported, and it scans | |
14159 | * out just a solid color). To recover from that, the | |
14160 | * display power well must be turned off and on again. | |
14161 | * Refuse the put the cursor into that compromised position. | |
14162 | */ | |
14163 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14164 | state->visible && state->base.crtc_x < 0) { | |
14165 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14166 | return -EINVAL; | |
14167 | } | |
14168 | ||
da20eabd | 14169 | return 0; |
852e787c | 14170 | } |
3d7d6510 | 14171 | |
a8ad0d8e ML |
14172 | static void |
14173 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14174 | struct drm_crtc *crtc) |
a8ad0d8e | 14175 | { |
f2858021 ML |
14176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14177 | ||
14178 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14179 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14180 | } |
14181 | ||
f4a2cf29 | 14182 | static void |
55a08b3f ML |
14183 | intel_update_cursor_plane(struct drm_plane *plane, |
14184 | const struct intel_crtc_state *crtc_state, | |
14185 | const struct intel_plane_state *state) | |
852e787c | 14186 | { |
55a08b3f ML |
14187 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14189 | struct drm_device *dev = plane->dev; |
2b875c22 | 14190 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14191 | uint32_t addr; |
852e787c | 14192 | |
f4a2cf29 | 14193 | if (!obj) |
a912f12f | 14194 | addr = 0; |
f4a2cf29 | 14195 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14196 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14197 | else |
a912f12f | 14198 | addr = obj->phys_handle->busaddr; |
852e787c | 14199 | |
a912f12f | 14200 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14201 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14202 | } |
14203 | ||
3d7d6510 MR |
14204 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14205 | int pipe) | |
14206 | { | |
14207 | struct intel_plane *cursor; | |
8e7d688b | 14208 | struct intel_plane_state *state; |
3d7d6510 MR |
14209 | |
14210 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14211 | if (cursor == NULL) | |
14212 | return NULL; | |
14213 | ||
8e7d688b MR |
14214 | state = intel_create_plane_state(&cursor->base); |
14215 | if (!state) { | |
ea2c67bb MR |
14216 | kfree(cursor); |
14217 | return NULL; | |
14218 | } | |
8e7d688b | 14219 | cursor->base.state = &state->base; |
ea2c67bb | 14220 | |
3d7d6510 MR |
14221 | cursor->can_scale = false; |
14222 | cursor->max_downscale = 1; | |
14223 | cursor->pipe = pipe; | |
14224 | cursor->plane = pipe; | |
a9ff8714 | 14225 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14226 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14227 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14228 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14229 | |
14230 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14231 | &intel_plane_funcs, |
3d7d6510 MR |
14232 | intel_cursor_formats, |
14233 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14234 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14235 | |
14236 | if (INTEL_INFO(dev)->gen >= 4) { | |
14237 | if (!dev->mode_config.rotation_property) | |
14238 | dev->mode_config.rotation_property = | |
14239 | drm_mode_create_rotation_property(dev, | |
14240 | BIT(DRM_ROTATE_0) | | |
14241 | BIT(DRM_ROTATE_180)); | |
14242 | if (dev->mode_config.rotation_property) | |
14243 | drm_object_attach_property(&cursor->base.base, | |
14244 | dev->mode_config.rotation_property, | |
8e7d688b | 14245 | state->base.rotation); |
4398ad45 VS |
14246 | } |
14247 | ||
af99ceda CK |
14248 | if (INTEL_INFO(dev)->gen >=9) |
14249 | state->scaler_id = -1; | |
14250 | ||
ea2c67bb MR |
14251 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14252 | ||
3d7d6510 MR |
14253 | return &cursor->base; |
14254 | } | |
14255 | ||
549e2bfb CK |
14256 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14257 | struct intel_crtc_state *crtc_state) | |
14258 | { | |
14259 | int i; | |
14260 | struct intel_scaler *intel_scaler; | |
14261 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14262 | ||
14263 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14264 | intel_scaler = &scaler_state->scalers[i]; | |
14265 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14266 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14267 | } | |
14268 | ||
14269 | scaler_state->scaler_id = -1; | |
14270 | } | |
14271 | ||
b358d0a6 | 14272 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14273 | { |
fbee40df | 14274 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14275 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14276 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14277 | struct drm_plane *primary = NULL; |
14278 | struct drm_plane *cursor = NULL; | |
465c120c | 14279 | int i, ret; |
79e53945 | 14280 | |
955382f3 | 14281 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14282 | if (intel_crtc == NULL) |
14283 | return; | |
14284 | ||
f5de6e07 ACO |
14285 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14286 | if (!crtc_state) | |
14287 | goto fail; | |
550acefd ACO |
14288 | intel_crtc->config = crtc_state; |
14289 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14290 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14291 | |
549e2bfb CK |
14292 | /* initialize shared scalers */ |
14293 | if (INTEL_INFO(dev)->gen >= 9) { | |
14294 | if (pipe == PIPE_C) | |
14295 | intel_crtc->num_scalers = 1; | |
14296 | else | |
14297 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14298 | ||
14299 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14300 | } | |
14301 | ||
465c120c | 14302 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14303 | if (!primary) |
14304 | goto fail; | |
14305 | ||
14306 | cursor = intel_cursor_plane_create(dev, pipe); | |
14307 | if (!cursor) | |
14308 | goto fail; | |
14309 | ||
465c120c | 14310 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14311 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14312 | if (ret) |
14313 | goto fail; | |
79e53945 JB |
14314 | |
14315 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14316 | for (i = 0; i < 256; i++) { |
14317 | intel_crtc->lut_r[i] = i; | |
14318 | intel_crtc->lut_g[i] = i; | |
14319 | intel_crtc->lut_b[i] = i; | |
14320 | } | |
14321 | ||
1f1c2e24 VS |
14322 | /* |
14323 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14324 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14325 | */ |
80824003 JB |
14326 | intel_crtc->pipe = pipe; |
14327 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14328 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14329 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14330 | intel_crtc->plane = !pipe; |
80824003 JB |
14331 | } |
14332 | ||
4b0e333e CW |
14333 | intel_crtc->cursor_base = ~0; |
14334 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14335 | intel_crtc->cursor_size = ~0; |
8d7849db | 14336 | |
852eb00d VS |
14337 | intel_crtc->wm.cxsr_allowed = true; |
14338 | ||
22fd0fab JB |
14339 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14340 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14341 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14342 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14343 | ||
79e53945 | 14344 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14345 | |
14346 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14347 | return; |
14348 | ||
14349 | fail: | |
14350 | if (primary) | |
14351 | drm_plane_cleanup(primary); | |
14352 | if (cursor) | |
14353 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14354 | kfree(crtc_state); |
3d7d6510 | 14355 | kfree(intel_crtc); |
79e53945 JB |
14356 | } |
14357 | ||
752aa88a JB |
14358 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14359 | { | |
14360 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14361 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14362 | |
51fd371b | 14363 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14364 | |
d3babd3f | 14365 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14366 | return INVALID_PIPE; |
14367 | ||
14368 | return to_intel_crtc(encoder->crtc)->pipe; | |
14369 | } | |
14370 | ||
08d7b3d1 | 14371 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14372 | struct drm_file *file) |
08d7b3d1 | 14373 | { |
08d7b3d1 | 14374 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14375 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14376 | struct intel_crtc *crtc; |
08d7b3d1 | 14377 | |
7707e653 | 14378 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14379 | |
7707e653 | 14380 | if (!drmmode_crtc) { |
08d7b3d1 | 14381 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14382 | return -ENOENT; |
08d7b3d1 CW |
14383 | } |
14384 | ||
7707e653 | 14385 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14386 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14387 | |
c05422d5 | 14388 | return 0; |
08d7b3d1 CW |
14389 | } |
14390 | ||
66a9278e | 14391 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14392 | { |
66a9278e DV |
14393 | struct drm_device *dev = encoder->base.dev; |
14394 | struct intel_encoder *source_encoder; | |
79e53945 | 14395 | int index_mask = 0; |
79e53945 JB |
14396 | int entry = 0; |
14397 | ||
b2784e15 | 14398 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14399 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14400 | index_mask |= (1 << entry); |
14401 | ||
79e53945 JB |
14402 | entry++; |
14403 | } | |
4ef69c7a | 14404 | |
79e53945 JB |
14405 | return index_mask; |
14406 | } | |
14407 | ||
4d302442 CW |
14408 | static bool has_edp_a(struct drm_device *dev) |
14409 | { | |
14410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14411 | ||
14412 | if (!IS_MOBILE(dev)) | |
14413 | return false; | |
14414 | ||
14415 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14416 | return false; | |
14417 | ||
e3589908 | 14418 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14419 | return false; |
14420 | ||
14421 | return true; | |
14422 | } | |
14423 | ||
84b4e042 JB |
14424 | static bool intel_crt_present(struct drm_device *dev) |
14425 | { | |
14426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14427 | ||
884497ed DL |
14428 | if (INTEL_INFO(dev)->gen >= 9) |
14429 | return false; | |
14430 | ||
cf404ce4 | 14431 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14432 | return false; |
14433 | ||
14434 | if (IS_CHERRYVIEW(dev)) | |
14435 | return false; | |
14436 | ||
65e472e4 VS |
14437 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14438 | return false; | |
14439 | ||
70ac54d0 VS |
14440 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14441 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14442 | return false; | |
14443 | ||
e4abb733 | 14444 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14445 | return false; |
14446 | ||
14447 | return true; | |
14448 | } | |
14449 | ||
79e53945 JB |
14450 | static void intel_setup_outputs(struct drm_device *dev) |
14451 | { | |
725e30ad | 14452 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14453 | struct intel_encoder *encoder; |
cb0953d7 | 14454 | bool dpd_is_edp = false; |
79e53945 | 14455 | |
c9093354 | 14456 | intel_lvds_init(dev); |
79e53945 | 14457 | |
84b4e042 | 14458 | if (intel_crt_present(dev)) |
79935fca | 14459 | intel_crt_init(dev); |
cb0953d7 | 14460 | |
c776eb2e VK |
14461 | if (IS_BROXTON(dev)) { |
14462 | /* | |
14463 | * FIXME: Broxton doesn't support port detection via the | |
14464 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14465 | * detect the ports. | |
14466 | */ | |
14467 | intel_ddi_init(dev, PORT_A); | |
14468 | intel_ddi_init(dev, PORT_B); | |
14469 | intel_ddi_init(dev, PORT_C); | |
14470 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14471 | int found; |
14472 | ||
de31facd JB |
14473 | /* |
14474 | * Haswell uses DDI functions to detect digital outputs. | |
14475 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14476 | * it's there. | |
14477 | */ | |
77179400 | 14478 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14479 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14480 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14481 | intel_ddi_init(dev, PORT_A); |
14482 | ||
14483 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14484 | * register */ | |
14485 | found = I915_READ(SFUSE_STRAP); | |
14486 | ||
14487 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14488 | intel_ddi_init(dev, PORT_B); | |
14489 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14490 | intel_ddi_init(dev, PORT_C); | |
14491 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14492 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14493 | /* |
14494 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14495 | */ | |
ef11bdb3 | 14496 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14497 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14498 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14499 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14500 | intel_ddi_init(dev, PORT_E); | |
14501 | ||
0e72a5b5 | 14502 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14503 | int found; |
5d8a7752 | 14504 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14505 | |
14506 | if (has_edp_a(dev)) | |
14507 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14508 | |
dc0fa718 | 14509 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14510 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14511 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14512 | if (!found) |
e2debe91 | 14513 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14514 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14515 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14516 | } |
14517 | ||
dc0fa718 | 14518 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14519 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14520 | |
dc0fa718 | 14521 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14522 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14523 | |
5eb08b69 | 14524 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14525 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14526 | |
270b3042 | 14527 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14528 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14529 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14530 | /* |
14531 | * The DP_DETECTED bit is the latched state of the DDC | |
14532 | * SDA pin at boot. However since eDP doesn't require DDC | |
14533 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14534 | * eDP ports may have been muxed to an alternate function. | |
14535 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14536 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14537 | * detect eDP ports. | |
14538 | */ | |
e66eb81d | 14539 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14540 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14541 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14542 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14543 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14544 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14545 | |
e66eb81d | 14546 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14547 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14548 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14549 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14550 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14551 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14552 | |
9418c1f1 | 14553 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14554 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14555 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14556 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14557 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14558 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14559 | } |
14560 | ||
3cfca973 | 14561 | intel_dsi_init(dev); |
09da55dc | 14562 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14563 | bool found = false; |
7d57382e | 14564 | |
e2debe91 | 14565 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14566 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14567 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14568 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14569 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14570 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14571 | } |
27185ae1 | 14572 | |
3fec3d2f | 14573 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14574 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14575 | } |
13520b05 KH |
14576 | |
14577 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14578 | |
e2debe91 | 14579 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14580 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14581 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14582 | } |
27185ae1 | 14583 | |
e2debe91 | 14584 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14585 | |
3fec3d2f | 14586 | if (IS_G4X(dev)) { |
b01f2c3a | 14587 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14588 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14589 | } |
3fec3d2f | 14590 | if (IS_G4X(dev)) |
ab9d7c30 | 14591 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14592 | } |
27185ae1 | 14593 | |
3fec3d2f | 14594 | if (IS_G4X(dev) && |
e7281eab | 14595 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14596 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14597 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14598 | intel_dvo_init(dev); |
14599 | ||
103a196f | 14600 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14601 | intel_tv_init(dev); |
14602 | ||
0bc12bcb | 14603 | intel_psr_init(dev); |
7c8f8a70 | 14604 | |
b2784e15 | 14605 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14606 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14607 | encoder->base.possible_clones = | |
66a9278e | 14608 | intel_encoder_clones(encoder); |
79e53945 | 14609 | } |
47356eb6 | 14610 | |
dde86e2d | 14611 | intel_init_pch_refclk(dev); |
270b3042 DV |
14612 | |
14613 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14614 | } |
14615 | ||
14616 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14617 | { | |
60a5ca01 | 14618 | struct drm_device *dev = fb->dev; |
79e53945 | 14619 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14620 | |
ef2d633e | 14621 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14622 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14623 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14624 | drm_gem_object_unreference(&intel_fb->obj->base); |
14625 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14626 | kfree(intel_fb); |
14627 | } | |
14628 | ||
14629 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14630 | struct drm_file *file, |
79e53945 JB |
14631 | unsigned int *handle) |
14632 | { | |
14633 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14634 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14635 | |
cc917ab4 CW |
14636 | if (obj->userptr.mm) { |
14637 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14638 | return -EINVAL; | |
14639 | } | |
14640 | ||
05394f39 | 14641 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14642 | } |
14643 | ||
86c98588 RV |
14644 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14645 | struct drm_file *file, | |
14646 | unsigned flags, unsigned color, | |
14647 | struct drm_clip_rect *clips, | |
14648 | unsigned num_clips) | |
14649 | { | |
14650 | struct drm_device *dev = fb->dev; | |
14651 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14652 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14653 | ||
14654 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14655 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14656 | mutex_unlock(&dev->struct_mutex); |
14657 | ||
14658 | return 0; | |
14659 | } | |
14660 | ||
79e53945 JB |
14661 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14662 | .destroy = intel_user_framebuffer_destroy, | |
14663 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14664 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14665 | }; |
14666 | ||
b321803d DL |
14667 | static |
14668 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14669 | uint32_t pixel_format) | |
14670 | { | |
14671 | u32 gen = INTEL_INFO(dev)->gen; | |
14672 | ||
14673 | if (gen >= 9) { | |
ac484963 VS |
14674 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14675 | ||
b321803d DL |
14676 | /* "The stride in bytes must not exceed the of the size of 8K |
14677 | * pixels and 32K bytes." | |
14678 | */ | |
ac484963 | 14679 | return min(8192 * cpp, 32768); |
666a4537 | 14680 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14681 | return 32*1024; |
14682 | } else if (gen >= 4) { | |
14683 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14684 | return 16*1024; | |
14685 | else | |
14686 | return 32*1024; | |
14687 | } else if (gen >= 3) { | |
14688 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14689 | return 8*1024; | |
14690 | else | |
14691 | return 16*1024; | |
14692 | } else { | |
14693 | /* XXX DSPC is limited to 4k tiled */ | |
14694 | return 8*1024; | |
14695 | } | |
14696 | } | |
14697 | ||
b5ea642a DV |
14698 | static int intel_framebuffer_init(struct drm_device *dev, |
14699 | struct intel_framebuffer *intel_fb, | |
14700 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14701 | struct drm_i915_gem_object *obj) | |
79e53945 | 14702 | { |
7b49f948 | 14703 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14704 | unsigned int aligned_height; |
79e53945 | 14705 | int ret; |
b321803d | 14706 | u32 pitch_limit, stride_alignment; |
79e53945 | 14707 | |
dd4916c5 DV |
14708 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14709 | ||
2a80eada DV |
14710 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14711 | /* Enforce that fb modifier and tiling mode match, but only for | |
14712 | * X-tiled. This is needed for FBC. */ | |
14713 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14714 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14715 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14716 | return -EINVAL; | |
14717 | } | |
14718 | } else { | |
14719 | if (obj->tiling_mode == I915_TILING_X) | |
14720 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14721 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14722 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14723 | return -EINVAL; | |
14724 | } | |
14725 | } | |
14726 | ||
9a8f0a12 TU |
14727 | /* Passed in modifier sanity checking. */ |
14728 | switch (mode_cmd->modifier[0]) { | |
14729 | case I915_FORMAT_MOD_Y_TILED: | |
14730 | case I915_FORMAT_MOD_Yf_TILED: | |
14731 | if (INTEL_INFO(dev)->gen < 9) { | |
14732 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14733 | mode_cmd->modifier[0]); | |
14734 | return -EINVAL; | |
14735 | } | |
14736 | case DRM_FORMAT_MOD_NONE: | |
14737 | case I915_FORMAT_MOD_X_TILED: | |
14738 | break; | |
14739 | default: | |
c0f40428 JB |
14740 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14741 | mode_cmd->modifier[0]); | |
57cd6508 | 14742 | return -EINVAL; |
c16ed4be | 14743 | } |
57cd6508 | 14744 | |
7b49f948 VS |
14745 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14746 | mode_cmd->modifier[0], | |
b321803d DL |
14747 | mode_cmd->pixel_format); |
14748 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14749 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14750 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14751 | return -EINVAL; |
c16ed4be | 14752 | } |
57cd6508 | 14753 | |
b321803d DL |
14754 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14755 | mode_cmd->pixel_format); | |
a35cdaa0 | 14756 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14757 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14758 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14759 | "tiled" : "linear", |
a35cdaa0 | 14760 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14761 | return -EINVAL; |
c16ed4be | 14762 | } |
5d7bd705 | 14763 | |
2a80eada | 14764 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14765 | mode_cmd->pitches[0] != obj->stride) { |
14766 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14767 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14768 | return -EINVAL; |
c16ed4be | 14769 | } |
5d7bd705 | 14770 | |
57779d06 | 14771 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14772 | switch (mode_cmd->pixel_format) { |
57779d06 | 14773 | case DRM_FORMAT_C8: |
04b3924d VS |
14774 | case DRM_FORMAT_RGB565: |
14775 | case DRM_FORMAT_XRGB8888: | |
14776 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14777 | break; |
14778 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14779 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14780 | DRM_DEBUG("unsupported pixel format: %s\n", |
14781 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14782 | return -EINVAL; |
c16ed4be | 14783 | } |
57779d06 | 14784 | break; |
57779d06 | 14785 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14786 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14787 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14788 | DRM_DEBUG("unsupported pixel format: %s\n", |
14789 | drm_get_format_name(mode_cmd->pixel_format)); | |
14790 | return -EINVAL; | |
14791 | } | |
14792 | break; | |
14793 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14794 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14795 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14796 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14797 | DRM_DEBUG("unsupported pixel format: %s\n", |
14798 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14799 | return -EINVAL; |
c16ed4be | 14800 | } |
b5626747 | 14801 | break; |
7531208b | 14802 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14803 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14804 | DRM_DEBUG("unsupported pixel format: %s\n", |
14805 | drm_get_format_name(mode_cmd->pixel_format)); | |
14806 | return -EINVAL; | |
14807 | } | |
14808 | break; | |
04b3924d VS |
14809 | case DRM_FORMAT_YUYV: |
14810 | case DRM_FORMAT_UYVY: | |
14811 | case DRM_FORMAT_YVYU: | |
14812 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14813 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14814 | DRM_DEBUG("unsupported pixel format: %s\n", |
14815 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14816 | return -EINVAL; |
c16ed4be | 14817 | } |
57cd6508 CW |
14818 | break; |
14819 | default: | |
4ee62c76 VS |
14820 | DRM_DEBUG("unsupported pixel format: %s\n", |
14821 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14822 | return -EINVAL; |
14823 | } | |
14824 | ||
90f9a336 VS |
14825 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14826 | if (mode_cmd->offsets[0] != 0) | |
14827 | return -EINVAL; | |
14828 | ||
ec2c981e | 14829 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14830 | mode_cmd->pixel_format, |
14831 | mode_cmd->modifier[0]); | |
53155c0a DV |
14832 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14833 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14834 | return -EINVAL; | |
14835 | ||
c7d73f6a DV |
14836 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14837 | intel_fb->obj = obj; | |
14838 | ||
79e53945 JB |
14839 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14840 | if (ret) { | |
14841 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14842 | return ret; | |
14843 | } | |
14844 | ||
0b05e1e0 VS |
14845 | intel_fb->obj->framebuffer_references++; |
14846 | ||
79e53945 JB |
14847 | return 0; |
14848 | } | |
14849 | ||
79e53945 JB |
14850 | static struct drm_framebuffer * |
14851 | intel_user_framebuffer_create(struct drm_device *dev, | |
14852 | struct drm_file *filp, | |
1eb83451 | 14853 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14854 | { |
dcb1394e | 14855 | struct drm_framebuffer *fb; |
05394f39 | 14856 | struct drm_i915_gem_object *obj; |
76dc3769 | 14857 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14858 | |
308e5bcb | 14859 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14860 | mode_cmd.handles[0])); |
c8725226 | 14861 | if (&obj->base == NULL) |
cce13ff7 | 14862 | return ERR_PTR(-ENOENT); |
79e53945 | 14863 | |
92907cbb | 14864 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14865 | if (IS_ERR(fb)) |
14866 | drm_gem_object_unreference_unlocked(&obj->base); | |
14867 | ||
14868 | return fb; | |
79e53945 JB |
14869 | } |
14870 | ||
0695726e | 14871 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14872 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14873 | { |
14874 | } | |
14875 | #endif | |
14876 | ||
79e53945 | 14877 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14878 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14879 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14880 | .atomic_check = intel_atomic_check, |
14881 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14882 | .atomic_state_alloc = intel_atomic_state_alloc, |
14883 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14884 | }; |
14885 | ||
e70236a8 JB |
14886 | /* Set up chip specific display functions */ |
14887 | static void intel_init_display(struct drm_device *dev) | |
14888 | { | |
14889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14890 | ||
ee9300bb DV |
14891 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14892 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14893 | else if (IS_CHERRYVIEW(dev)) |
14894 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14895 | else if (IS_VALLEYVIEW(dev)) |
14896 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14897 | else if (IS_PINEVIEW(dev)) | |
14898 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14899 | else | |
14900 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14901 | ||
bc8d7dff DL |
14902 | if (INTEL_INFO(dev)->gen >= 9) { |
14903 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14904 | dev_priv->display.get_initial_plane_config = |
14905 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14906 | dev_priv->display.crtc_compute_clock = |
14907 | haswell_crtc_compute_clock; | |
14908 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14909 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14910 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14911 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14912 | dev_priv->display.get_initial_plane_config = |
14913 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14914 | dev_priv->display.crtc_compute_clock = |
14915 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14916 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14917 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14918 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14919 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14920 | dev_priv->display.get_initial_plane_config = |
14921 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14922 | dev_priv->display.crtc_compute_clock = |
14923 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14924 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14925 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 14926 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14927 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14928 | dev_priv->display.get_initial_plane_config = |
14929 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14930 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14931 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14932 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14933 | } else { |
0e8ffe1b | 14934 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14935 | dev_priv->display.get_initial_plane_config = |
14936 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14937 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14938 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14939 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14940 | } |
e70236a8 | 14941 | |
e70236a8 | 14942 | /* Returns the core display clock speed */ |
ef11bdb3 | 14943 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14944 | dev_priv->display.get_display_clock_speed = |
14945 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14946 | else if (IS_BROXTON(dev)) |
14947 | dev_priv->display.get_display_clock_speed = | |
14948 | broxton_get_display_clock_speed; | |
1652d19e VS |
14949 | else if (IS_BROADWELL(dev)) |
14950 | dev_priv->display.get_display_clock_speed = | |
14951 | broadwell_get_display_clock_speed; | |
14952 | else if (IS_HASWELL(dev)) | |
14953 | dev_priv->display.get_display_clock_speed = | |
14954 | haswell_get_display_clock_speed; | |
666a4537 | 14955 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14956 | dev_priv->display.get_display_clock_speed = |
14957 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14958 | else if (IS_GEN5(dev)) |
14959 | dev_priv->display.get_display_clock_speed = | |
14960 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14961 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14962 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14963 | dev_priv->display.get_display_clock_speed = |
14964 | i945_get_display_clock_speed; | |
34edce2f VS |
14965 | else if (IS_GM45(dev)) |
14966 | dev_priv->display.get_display_clock_speed = | |
14967 | gm45_get_display_clock_speed; | |
14968 | else if (IS_CRESTLINE(dev)) | |
14969 | dev_priv->display.get_display_clock_speed = | |
14970 | i965gm_get_display_clock_speed; | |
14971 | else if (IS_PINEVIEW(dev)) | |
14972 | dev_priv->display.get_display_clock_speed = | |
14973 | pnv_get_display_clock_speed; | |
14974 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14975 | dev_priv->display.get_display_clock_speed = | |
14976 | g33_get_display_clock_speed; | |
e70236a8 JB |
14977 | else if (IS_I915G(dev)) |
14978 | dev_priv->display.get_display_clock_speed = | |
14979 | i915_get_display_clock_speed; | |
257a7ffc | 14980 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14981 | dev_priv->display.get_display_clock_speed = |
14982 | i9xx_misc_get_display_clock_speed; | |
14983 | else if (IS_I915GM(dev)) | |
14984 | dev_priv->display.get_display_clock_speed = | |
14985 | i915gm_get_display_clock_speed; | |
14986 | else if (IS_I865G(dev)) | |
14987 | dev_priv->display.get_display_clock_speed = | |
14988 | i865_get_display_clock_speed; | |
f0f8a9ce | 14989 | else if (IS_I85X(dev)) |
e70236a8 | 14990 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14991 | i85x_get_display_clock_speed; |
623e01e5 VS |
14992 | else { /* 830 */ |
14993 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14994 | dev_priv->display.get_display_clock_speed = |
14995 | i830_get_display_clock_speed; | |
623e01e5 | 14996 | } |
e70236a8 | 14997 | |
7c10a2b5 | 14998 | if (IS_GEN5(dev)) { |
3bb11b53 | 14999 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15000 | } else if (IS_GEN6(dev)) { |
15001 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15002 | } else if (IS_IVYBRIDGE(dev)) { |
15003 | /* FIXME: detect B0+ stepping and use auto training */ | |
15004 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15005 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15006 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15007 | if (IS_BROADWELL(dev)) { |
15008 | dev_priv->display.modeset_commit_cdclk = | |
15009 | broadwell_modeset_commit_cdclk; | |
15010 | dev_priv->display.modeset_calc_cdclk = | |
15011 | broadwell_modeset_calc_cdclk; | |
15012 | } | |
666a4537 | 15013 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15014 | dev_priv->display.modeset_commit_cdclk = |
15015 | valleyview_modeset_commit_cdclk; | |
15016 | dev_priv->display.modeset_calc_cdclk = | |
15017 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15018 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15019 | dev_priv->display.modeset_commit_cdclk = |
15020 | broxton_modeset_commit_cdclk; | |
15021 | dev_priv->display.modeset_calc_cdclk = | |
15022 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15023 | } |
8c9f3aaf | 15024 | |
8c9f3aaf JB |
15025 | switch (INTEL_INFO(dev)->gen) { |
15026 | case 2: | |
15027 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15028 | break; | |
15029 | ||
15030 | case 3: | |
15031 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15032 | break; | |
15033 | ||
15034 | case 4: | |
15035 | case 5: | |
15036 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15037 | break; | |
15038 | ||
15039 | case 6: | |
15040 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15041 | break; | |
7c9017e5 | 15042 | case 7: |
4e0bbc31 | 15043 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15044 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15045 | break; | |
830c81db | 15046 | case 9: |
ba343e02 TU |
15047 | /* Drop through - unsupported since execlist only. */ |
15048 | default: | |
15049 | /* Default just returns -ENODEV to indicate unsupported */ | |
15050 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15051 | } |
7bd688cd | 15052 | |
e39b999a | 15053 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15054 | } |
15055 | ||
b690e96c JB |
15056 | /* |
15057 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15058 | * resume, or other times. This quirk makes sure that's the case for | |
15059 | * affected systems. | |
15060 | */ | |
0206e353 | 15061 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15062 | { |
15063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15064 | ||
15065 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15066 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15067 | } |
15068 | ||
b6b5d049 VS |
15069 | static void quirk_pipeb_force(struct drm_device *dev) |
15070 | { | |
15071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15072 | ||
15073 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15074 | DRM_INFO("applying pipe b force quirk\n"); | |
15075 | } | |
15076 | ||
435793df KP |
15077 | /* |
15078 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15079 | */ | |
15080 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15081 | { | |
15082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15083 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15084 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15085 | } |
15086 | ||
4dca20ef | 15087 | /* |
5a15ab5b CE |
15088 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15089 | * brightness value | |
4dca20ef CE |
15090 | */ |
15091 | static void quirk_invert_brightness(struct drm_device *dev) | |
15092 | { | |
15093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15094 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15095 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15096 | } |
15097 | ||
9c72cc6f SD |
15098 | /* Some VBT's incorrectly indicate no backlight is present */ |
15099 | static void quirk_backlight_present(struct drm_device *dev) | |
15100 | { | |
15101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15102 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15103 | DRM_INFO("applying backlight present quirk\n"); | |
15104 | } | |
15105 | ||
b690e96c JB |
15106 | struct intel_quirk { |
15107 | int device; | |
15108 | int subsystem_vendor; | |
15109 | int subsystem_device; | |
15110 | void (*hook)(struct drm_device *dev); | |
15111 | }; | |
15112 | ||
5f85f176 EE |
15113 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15114 | struct intel_dmi_quirk { | |
15115 | void (*hook)(struct drm_device *dev); | |
15116 | const struct dmi_system_id (*dmi_id_list)[]; | |
15117 | }; | |
15118 | ||
15119 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15120 | { | |
15121 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15122 | return 1; | |
15123 | } | |
15124 | ||
15125 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15126 | { | |
15127 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15128 | { | |
15129 | .callback = intel_dmi_reverse_brightness, | |
15130 | .ident = "NCR Corporation", | |
15131 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15132 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15133 | }, | |
15134 | }, | |
15135 | { } /* terminating entry */ | |
15136 | }, | |
15137 | .hook = quirk_invert_brightness, | |
15138 | }, | |
15139 | }; | |
15140 | ||
c43b5634 | 15141 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15142 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15143 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15144 | ||
b690e96c JB |
15145 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15146 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15147 | ||
5f080c0f VS |
15148 | /* 830 needs to leave pipe A & dpll A up */ |
15149 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15150 | ||
b6b5d049 VS |
15151 | /* 830 needs to leave pipe B & dpll B up */ |
15152 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15153 | ||
435793df KP |
15154 | /* Lenovo U160 cannot use SSC on LVDS */ |
15155 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15156 | |
15157 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15158 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15159 | |
be505f64 AH |
15160 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15161 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15162 | ||
15163 | /* Acer/eMachines G725 */ | |
15164 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15165 | ||
15166 | /* Acer/eMachines e725 */ | |
15167 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15168 | ||
15169 | /* Acer/Packard Bell NCL20 */ | |
15170 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15171 | ||
15172 | /* Acer Aspire 4736Z */ | |
15173 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15174 | |
15175 | /* Acer Aspire 5336 */ | |
15176 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15177 | |
15178 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15179 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15180 | |
dfb3d47b SD |
15181 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15182 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15183 | ||
b2a9601c | 15184 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15185 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15186 | ||
1b9448b0 JN |
15187 | /* Apple Macbook 4,1 */ |
15188 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15189 | ||
d4967d8c SD |
15190 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15191 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15192 | |
15193 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15194 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15195 | |
15196 | /* Dell Chromebook 11 */ | |
15197 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15198 | |
15199 | /* Dell Chromebook 11 (2015 version) */ | |
15200 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15201 | }; |
15202 | ||
15203 | static void intel_init_quirks(struct drm_device *dev) | |
15204 | { | |
15205 | struct pci_dev *d = dev->pdev; | |
15206 | int i; | |
15207 | ||
15208 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15209 | struct intel_quirk *q = &intel_quirks[i]; | |
15210 | ||
15211 | if (d->device == q->device && | |
15212 | (d->subsystem_vendor == q->subsystem_vendor || | |
15213 | q->subsystem_vendor == PCI_ANY_ID) && | |
15214 | (d->subsystem_device == q->subsystem_device || | |
15215 | q->subsystem_device == PCI_ANY_ID)) | |
15216 | q->hook(dev); | |
15217 | } | |
5f85f176 EE |
15218 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15219 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15220 | intel_dmi_quirks[i].hook(dev); | |
15221 | } | |
b690e96c JB |
15222 | } |
15223 | ||
9cce37f4 JB |
15224 | /* Disable the VGA plane that we never use */ |
15225 | static void i915_disable_vga(struct drm_device *dev) | |
15226 | { | |
15227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15228 | u8 sr1; | |
f0f59a00 | 15229 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15230 | |
2b37c616 | 15231 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15232 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15233 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15234 | sr1 = inb(VGA_SR_DATA); |
15235 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15236 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15237 | udelay(300); | |
15238 | ||
01f5a626 | 15239 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15240 | POSTING_READ(vga_reg); |
15241 | } | |
15242 | ||
f817586c DV |
15243 | void intel_modeset_init_hw(struct drm_device *dev) |
15244 | { | |
1a617b77 ML |
15245 | struct drm_i915_private *dev_priv = dev->dev_private; |
15246 | ||
b6283055 | 15247 | intel_update_cdclk(dev); |
1a617b77 ML |
15248 | |
15249 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15250 | ||
f817586c | 15251 | intel_init_clock_gating(dev); |
8090c6b9 | 15252 | intel_enable_gt_powersave(dev); |
f817586c DV |
15253 | } |
15254 | ||
d93c0372 MR |
15255 | /* |
15256 | * Calculate what we think the watermarks should be for the state we've read | |
15257 | * out of the hardware and then immediately program those watermarks so that | |
15258 | * we ensure the hardware settings match our internal state. | |
15259 | * | |
15260 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15261 | * current state (which was constructed during hardware readout) and running it | |
15262 | * through the atomic check code to calculate new watermark values in the | |
15263 | * state object. | |
15264 | */ | |
15265 | static void sanitize_watermarks(struct drm_device *dev) | |
15266 | { | |
15267 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15268 | struct drm_atomic_state *state; | |
15269 | struct drm_crtc *crtc; | |
15270 | struct drm_crtc_state *cstate; | |
15271 | struct drm_modeset_acquire_ctx ctx; | |
15272 | int ret; | |
15273 | int i; | |
15274 | ||
15275 | /* Only supported on platforms that use atomic watermark design */ | |
bf220452 | 15276 | if (!dev_priv->display.program_watermarks) |
d93c0372 MR |
15277 | return; |
15278 | ||
15279 | /* | |
15280 | * We need to hold connection_mutex before calling duplicate_state so | |
15281 | * that the connector loop is protected. | |
15282 | */ | |
15283 | drm_modeset_acquire_init(&ctx, 0); | |
15284 | retry: | |
0cd1262d | 15285 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15286 | if (ret == -EDEADLK) { |
15287 | drm_modeset_backoff(&ctx); | |
15288 | goto retry; | |
15289 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15290 | goto fail; |
d93c0372 MR |
15291 | } |
15292 | ||
15293 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15294 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15295 | goto fail; |
d93c0372 MR |
15296 | |
15297 | ret = intel_atomic_check(dev, state); | |
15298 | if (ret) { | |
15299 | /* | |
15300 | * If we fail here, it means that the hardware appears to be | |
15301 | * programmed in a way that shouldn't be possible, given our | |
15302 | * understanding of watermark requirements. This might mean a | |
15303 | * mistake in the hardware readout code or a mistake in the | |
15304 | * watermark calculations for a given platform. Raise a WARN | |
15305 | * so that this is noticeable. | |
15306 | * | |
15307 | * If this actually happens, we'll have to just leave the | |
15308 | * BIOS-programmed watermarks untouched and hope for the best. | |
15309 | */ | |
15310 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15311 | goto fail; |
d93c0372 MR |
15312 | } |
15313 | ||
15314 | /* Write calculated watermark values back */ | |
15315 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15316 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15317 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15318 | ||
bf220452 | 15319 | dev_priv->display.program_watermarks(cs); |
d93c0372 MR |
15320 | } |
15321 | ||
15322 | drm_atomic_state_free(state); | |
0cd1262d | 15323 | fail: |
d93c0372 MR |
15324 | drm_modeset_drop_locks(&ctx); |
15325 | drm_modeset_acquire_fini(&ctx); | |
15326 | } | |
15327 | ||
79e53945 JB |
15328 | void intel_modeset_init(struct drm_device *dev) |
15329 | { | |
652c393a | 15330 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15331 | int sprite, ret; |
8cc87b75 | 15332 | enum pipe pipe; |
46f297fb | 15333 | struct intel_crtc *crtc; |
79e53945 JB |
15334 | |
15335 | drm_mode_config_init(dev); | |
15336 | ||
15337 | dev->mode_config.min_width = 0; | |
15338 | dev->mode_config.min_height = 0; | |
15339 | ||
019d96cb DA |
15340 | dev->mode_config.preferred_depth = 24; |
15341 | dev->mode_config.prefer_shadow = 1; | |
15342 | ||
25bab385 TU |
15343 | dev->mode_config.allow_fb_modifiers = true; |
15344 | ||
e6ecefaa | 15345 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15346 | |
b690e96c JB |
15347 | intel_init_quirks(dev); |
15348 | ||
1fa61106 ED |
15349 | intel_init_pm(dev); |
15350 | ||
e3c74757 BW |
15351 | if (INTEL_INFO(dev)->num_pipes == 0) |
15352 | return; | |
15353 | ||
69f92f67 LW |
15354 | /* |
15355 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15356 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15357 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15358 | * indicates as much. | |
15359 | */ | |
15360 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15361 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15362 | DREF_SSC1_ENABLE); | |
15363 | ||
15364 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15365 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15366 | bios_lvds_use_ssc ? "en" : "dis", | |
15367 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15368 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15369 | } | |
15370 | } | |
15371 | ||
e70236a8 | 15372 | intel_init_display(dev); |
7c10a2b5 | 15373 | intel_init_audio(dev); |
e70236a8 | 15374 | |
a6c45cf0 CW |
15375 | if (IS_GEN2(dev)) { |
15376 | dev->mode_config.max_width = 2048; | |
15377 | dev->mode_config.max_height = 2048; | |
15378 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15379 | dev->mode_config.max_width = 4096; |
15380 | dev->mode_config.max_height = 4096; | |
79e53945 | 15381 | } else { |
a6c45cf0 CW |
15382 | dev->mode_config.max_width = 8192; |
15383 | dev->mode_config.max_height = 8192; | |
79e53945 | 15384 | } |
068be561 | 15385 | |
dc41c154 VS |
15386 | if (IS_845G(dev) || IS_I865G(dev)) { |
15387 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15388 | dev->mode_config.cursor_height = 1023; | |
15389 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15390 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15391 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15392 | } else { | |
15393 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15394 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15395 | } | |
15396 | ||
5d4545ae | 15397 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15398 | |
28c97730 | 15399 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15400 | INTEL_INFO(dev)->num_pipes, |
15401 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15402 | |
055e393f | 15403 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15404 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15405 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15406 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15407 | if (ret) |
06da8da2 | 15408 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15409 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15410 | } |
79e53945 JB |
15411 | } |
15412 | ||
bfa7df01 VS |
15413 | intel_update_czclk(dev_priv); |
15414 | intel_update_cdclk(dev); | |
15415 | ||
e72f9fbf | 15416 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15417 | |
9cce37f4 JB |
15418 | /* Just disable it once at startup */ |
15419 | i915_disable_vga(dev); | |
79e53945 | 15420 | intel_setup_outputs(dev); |
11be49eb | 15421 | |
6e9f798d | 15422 | drm_modeset_lock_all(dev); |
043e9bda | 15423 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15424 | drm_modeset_unlock_all(dev); |
46f297fb | 15425 | |
d3fcc808 | 15426 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15427 | struct intel_initial_plane_config plane_config = {}; |
15428 | ||
46f297fb JB |
15429 | if (!crtc->active) |
15430 | continue; | |
15431 | ||
46f297fb | 15432 | /* |
46f297fb JB |
15433 | * Note that reserving the BIOS fb up front prevents us |
15434 | * from stuffing other stolen allocations like the ring | |
15435 | * on top. This prevents some ugliness at boot time, and | |
15436 | * can even allow for smooth boot transitions if the BIOS | |
15437 | * fb is large enough for the active pipe configuration. | |
15438 | */ | |
eeebeac5 ML |
15439 | dev_priv->display.get_initial_plane_config(crtc, |
15440 | &plane_config); | |
15441 | ||
15442 | /* | |
15443 | * If the fb is shared between multiple heads, we'll | |
15444 | * just get the first one. | |
15445 | */ | |
15446 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15447 | } |
d93c0372 MR |
15448 | |
15449 | /* | |
15450 | * Make sure hardware watermarks really match the state we read out. | |
15451 | * Note that we need to do this after reconstructing the BIOS fb's | |
15452 | * since the watermark calculation done here will use pstate->fb. | |
15453 | */ | |
15454 | sanitize_watermarks(dev); | |
2c7111db CW |
15455 | } |
15456 | ||
7fad798e DV |
15457 | static void intel_enable_pipe_a(struct drm_device *dev) |
15458 | { | |
15459 | struct intel_connector *connector; | |
15460 | struct drm_connector *crt = NULL; | |
15461 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15462 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15463 | |
15464 | /* We can't just switch on the pipe A, we need to set things up with a | |
15465 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15466 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15467 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15468 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15469 | crt = &connector->base; | |
15470 | break; | |
15471 | } | |
15472 | } | |
15473 | ||
15474 | if (!crt) | |
15475 | return; | |
15476 | ||
208bf9fd | 15477 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15478 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15479 | } |
15480 | ||
fa555837 DV |
15481 | static bool |
15482 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15483 | { | |
7eb552ae BW |
15484 | struct drm_device *dev = crtc->base.dev; |
15485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15486 | u32 val; |
fa555837 | 15487 | |
7eb552ae | 15488 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15489 | return true; |
15490 | ||
649636ef | 15491 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15492 | |
15493 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15494 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15495 | return false; | |
15496 | ||
15497 | return true; | |
15498 | } | |
15499 | ||
02e93c35 VS |
15500 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15501 | { | |
15502 | struct drm_device *dev = crtc->base.dev; | |
15503 | struct intel_encoder *encoder; | |
15504 | ||
15505 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15506 | return true; | |
15507 | ||
15508 | return false; | |
15509 | } | |
15510 | ||
dd756198 VS |
15511 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15512 | { | |
15513 | struct drm_device *dev = encoder->base.dev; | |
15514 | struct intel_connector *connector; | |
15515 | ||
15516 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15517 | return true; | |
15518 | ||
15519 | return false; | |
15520 | } | |
15521 | ||
24929352 DV |
15522 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15523 | { | |
15524 | struct drm_device *dev = crtc->base.dev; | |
15525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15526 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15527 | |
24929352 | 15528 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15529 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15530 | ||
d3eaf884 | 15531 | /* restore vblank interrupts to correct state */ |
9625604c | 15532 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15533 | if (crtc->active) { |
f9cd7b88 VS |
15534 | struct intel_plane *plane; |
15535 | ||
9625604c | 15536 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15537 | |
15538 | /* Disable everything but the primary plane */ | |
15539 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15540 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15541 | continue; | |
15542 | ||
15543 | plane->disable_plane(&plane->base, &crtc->base); | |
15544 | } | |
9625604c | 15545 | } |
d3eaf884 | 15546 | |
24929352 | 15547 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15548 | * disable the crtc (and hence change the state) if it is wrong. Note |
15549 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15550 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15551 | bool plane; |
15552 | ||
24929352 DV |
15553 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15554 | crtc->base.base.id); | |
15555 | ||
15556 | /* Pipe has the wrong plane attached and the plane is active. | |
15557 | * Temporarily change the plane mapping and disable everything | |
15558 | * ... */ | |
15559 | plane = crtc->plane; | |
b70709a6 | 15560 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15561 | crtc->plane = !plane; |
b17d48e2 | 15562 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15563 | crtc->plane = plane; |
24929352 | 15564 | } |
24929352 | 15565 | |
7fad798e DV |
15566 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15567 | crtc->pipe == PIPE_A && !crtc->active) { | |
15568 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15569 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15570 | * call below we restore the pipe to the right state, but leave | |
15571 | * the required bits on. */ | |
15572 | intel_enable_pipe_a(dev); | |
15573 | } | |
15574 | ||
24929352 DV |
15575 | /* Adjust the state of the output pipe according to whether we |
15576 | * have active connectors/encoders. */ | |
02e93c35 | 15577 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15578 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15579 | |
53d9f4e9 | 15580 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15581 | struct intel_encoder *encoder; |
24929352 DV |
15582 | |
15583 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15584 | * functions or because of calls to intel_crtc_disable_noatomic, |
15585 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15586 | * pipe A quirk. */ |
15587 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15588 | crtc->base.base.id, | |
83d65738 | 15589 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15590 | crtc->active ? "enabled" : "disabled"); |
15591 | ||
4be40c98 | 15592 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15593 | crtc->base.state->active = crtc->active; |
24929352 | 15594 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15595 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15596 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15597 | |
15598 | /* Because we only establish the connector -> encoder -> | |
15599 | * crtc links if something is active, this means the | |
15600 | * crtc is now deactivated. Break the links. connector | |
15601 | * -> encoder links are only establish when things are | |
15602 | * actually up, hence no need to break them. */ | |
15603 | WARN_ON(crtc->active); | |
15604 | ||
2d406bb0 | 15605 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15606 | encoder->base.crtc = NULL; |
24929352 | 15607 | } |
c5ab3bc0 | 15608 | |
a3ed6aad | 15609 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15610 | /* |
15611 | * We start out with underrun reporting disabled to avoid races. | |
15612 | * For correct bookkeeping mark this on active crtcs. | |
15613 | * | |
c5ab3bc0 DV |
15614 | * Also on gmch platforms we dont have any hardware bits to |
15615 | * disable the underrun reporting. Which means we need to start | |
15616 | * out with underrun reporting disabled also on inactive pipes, | |
15617 | * since otherwise we'll complain about the garbage we read when | |
15618 | * e.g. coming up after runtime pm. | |
15619 | * | |
4cc31489 DV |
15620 | * No protection against concurrent access is required - at |
15621 | * worst a fifo underrun happens which also sets this to false. | |
15622 | */ | |
15623 | crtc->cpu_fifo_underrun_disabled = true; | |
15624 | crtc->pch_fifo_underrun_disabled = true; | |
15625 | } | |
24929352 DV |
15626 | } |
15627 | ||
15628 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15629 | { | |
15630 | struct intel_connector *connector; | |
15631 | struct drm_device *dev = encoder->base.dev; | |
15632 | ||
15633 | /* We need to check both for a crtc link (meaning that the | |
15634 | * encoder is active and trying to read from a pipe) and the | |
15635 | * pipe itself being active. */ | |
15636 | bool has_active_crtc = encoder->base.crtc && | |
15637 | to_intel_crtc(encoder->base.crtc)->active; | |
15638 | ||
dd756198 | 15639 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15640 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15641 | encoder->base.base.id, | |
8e329a03 | 15642 | encoder->base.name); |
24929352 DV |
15643 | |
15644 | /* Connector is active, but has no active pipe. This is | |
15645 | * fallout from our resume register restoring. Disable | |
15646 | * the encoder manually again. */ | |
15647 | if (encoder->base.crtc) { | |
15648 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15649 | encoder->base.base.id, | |
8e329a03 | 15650 | encoder->base.name); |
24929352 | 15651 | encoder->disable(encoder); |
a62d1497 VS |
15652 | if (encoder->post_disable) |
15653 | encoder->post_disable(encoder); | |
24929352 | 15654 | } |
7f1950fb | 15655 | encoder->base.crtc = NULL; |
24929352 DV |
15656 | |
15657 | /* Inconsistent output/port/pipe state happens presumably due to | |
15658 | * a bug in one of the get_hw_state functions. Or someplace else | |
15659 | * in our code, like the register restore mess on resume. Clamp | |
15660 | * things to off as a safer default. */ | |
3a3371ff | 15661 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15662 | if (connector->encoder != encoder) |
15663 | continue; | |
7f1950fb EE |
15664 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15665 | connector->base.encoder = NULL; | |
24929352 DV |
15666 | } |
15667 | } | |
15668 | /* Enabled encoders without active connectors will be fixed in | |
15669 | * the crtc fixup. */ | |
15670 | } | |
15671 | ||
04098753 | 15672 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15673 | { |
15674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15675 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15676 | |
04098753 ID |
15677 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15678 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15679 | i915_disable_vga(dev); | |
15680 | } | |
15681 | } | |
15682 | ||
15683 | void i915_redisable_vga(struct drm_device *dev) | |
15684 | { | |
15685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15686 | ||
8dc8a27c PZ |
15687 | /* This function can be called both from intel_modeset_setup_hw_state or |
15688 | * at a very early point in our resume sequence, where the power well | |
15689 | * structures are not yet restored. Since this function is at a very | |
15690 | * paranoid "someone might have enabled VGA while we were not looking" | |
15691 | * level, just check if the power well is enabled instead of trying to | |
15692 | * follow the "don't touch the power well if we don't need it" policy | |
15693 | * the rest of the driver uses. */ | |
6392f847 | 15694 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15695 | return; |
15696 | ||
04098753 | 15697 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15698 | |
15699 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15700 | } |
15701 | ||
f9cd7b88 | 15702 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15703 | { |
f9cd7b88 | 15704 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15705 | |
f9cd7b88 | 15706 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15707 | } |
15708 | ||
f9cd7b88 VS |
15709 | /* FIXME read out full plane state for all planes */ |
15710 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15711 | { |
b26d3ea3 | 15712 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15713 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15714 | to_intel_plane_state(primary->state); |
d032ffa0 | 15715 | |
19b8d387 | 15716 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15717 | primary_get_hw_state(to_intel_plane(primary)); |
15718 | ||
15719 | if (plane_state->visible) | |
15720 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15721 | } |
15722 | ||
30e984df | 15723 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15724 | { |
15725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15726 | enum pipe pipe; | |
24929352 DV |
15727 | struct intel_crtc *crtc; |
15728 | struct intel_encoder *encoder; | |
15729 | struct intel_connector *connector; | |
5358901f | 15730 | int i; |
24929352 | 15731 | |
565602d7 ML |
15732 | dev_priv->active_crtcs = 0; |
15733 | ||
d3fcc808 | 15734 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15735 | struct intel_crtc_state *crtc_state = crtc->config; |
15736 | int pixclk = 0; | |
3b117c8f | 15737 | |
565602d7 ML |
15738 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15739 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15740 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15741 | |
565602d7 ML |
15742 | crtc_state->base.active = crtc_state->base.enable = |
15743 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15744 | ||
15745 | crtc->base.enabled = crtc_state->base.enable; | |
15746 | crtc->active = crtc_state->base.active; | |
15747 | ||
15748 | if (crtc_state->base.active) { | |
15749 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15750 | ||
15751 | if (IS_BROADWELL(dev_priv)) { | |
15752 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15753 | ||
15754 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15755 | if (crtc_state->ips_enabled) | |
15756 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15757 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15758 | IS_CHERRYVIEW(dev_priv) || | |
15759 | IS_BROXTON(dev_priv)) | |
15760 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15761 | else | |
15762 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15763 | } | |
15764 | ||
15765 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15766 | |
f9cd7b88 | 15767 | readout_plane_state(crtc); |
24929352 DV |
15768 | |
15769 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15770 | crtc->base.base.id, | |
15771 | crtc->active ? "enabled" : "disabled"); | |
15772 | } | |
15773 | ||
5358901f DV |
15774 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15775 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15776 | ||
3e369b76 ACO |
15777 | pll->on = pll->get_hw_state(dev_priv, pll, |
15778 | &pll->config.hw_state); | |
5358901f | 15779 | pll->active = 0; |
3e369b76 | 15780 | pll->config.crtc_mask = 0; |
d3fcc808 | 15781 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15782 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15783 | pll->active++; |
3e369b76 | 15784 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15785 | } |
5358901f | 15786 | } |
5358901f | 15787 | |
1e6f2ddc | 15788 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15789 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15790 | |
3e369b76 | 15791 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15792 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15793 | } |
15794 | ||
b2784e15 | 15795 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15796 | pipe = 0; |
15797 | ||
15798 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15799 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15800 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15801 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15802 | } else { |
15803 | encoder->base.crtc = NULL; | |
15804 | } | |
15805 | ||
6f2bcceb | 15806 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15807 | encoder->base.base.id, |
8e329a03 | 15808 | encoder->base.name, |
24929352 | 15809 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15810 | pipe_name(pipe)); |
24929352 DV |
15811 | } |
15812 | ||
3a3371ff | 15813 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15814 | if (connector->get_hw_state(connector)) { |
15815 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15816 | |
15817 | encoder = connector->encoder; | |
15818 | connector->base.encoder = &encoder->base; | |
15819 | ||
15820 | if (encoder->base.crtc && | |
15821 | encoder->base.crtc->state->active) { | |
15822 | /* | |
15823 | * This has to be done during hardware readout | |
15824 | * because anything calling .crtc_disable may | |
15825 | * rely on the connector_mask being accurate. | |
15826 | */ | |
15827 | encoder->base.crtc->state->connector_mask |= | |
15828 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15829 | encoder->base.crtc->state->encoder_mask |= |
15830 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15831 | } |
15832 | ||
24929352 DV |
15833 | } else { |
15834 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15835 | connector->base.encoder = NULL; | |
15836 | } | |
15837 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15838 | connector->base.base.id, | |
c23cc417 | 15839 | connector->base.name, |
24929352 DV |
15840 | connector->base.encoder ? "enabled" : "disabled"); |
15841 | } | |
7f4c6284 VS |
15842 | |
15843 | for_each_intel_crtc(dev, crtc) { | |
15844 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15845 | ||
15846 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15847 | if (crtc->base.state->active) { | |
15848 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15849 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15850 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15851 | ||
15852 | /* | |
15853 | * The initial mode needs to be set in order to keep | |
15854 | * the atomic core happy. It wants a valid mode if the | |
15855 | * crtc's enabled, so we do the above call. | |
15856 | * | |
15857 | * At this point some state updated by the connectors | |
15858 | * in their ->detect() callback has not run yet, so | |
15859 | * no recalculation can be done yet. | |
15860 | * | |
15861 | * Even if we could do a recalculation and modeset | |
15862 | * right now it would cause a double modeset if | |
15863 | * fbdev or userspace chooses a different initial mode. | |
15864 | * | |
15865 | * If that happens, someone indicated they wanted a | |
15866 | * mode change, which means it's safe to do a full | |
15867 | * recalculation. | |
15868 | */ | |
15869 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15870 | |
15871 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15872 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15873 | } |
15874 | } | |
30e984df DV |
15875 | } |
15876 | ||
043e9bda ML |
15877 | /* Scan out the current hw modeset state, |
15878 | * and sanitizes it to the current state | |
15879 | */ | |
15880 | static void | |
15881 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15882 | { |
15883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15884 | enum pipe pipe; | |
30e984df DV |
15885 | struct intel_crtc *crtc; |
15886 | struct intel_encoder *encoder; | |
35c95375 | 15887 | int i; |
30e984df DV |
15888 | |
15889 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15890 | |
15891 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15892 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15893 | intel_sanitize_encoder(encoder); |
15894 | } | |
15895 | ||
055e393f | 15896 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15897 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15898 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15899 | intel_dump_pipe_config(crtc, crtc->config, |
15900 | "[setup_hw_state]"); | |
24929352 | 15901 | } |
9a935856 | 15902 | |
d29b2f9d ACO |
15903 | intel_modeset_update_connector_atomic_state(dev); |
15904 | ||
35c95375 DV |
15905 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15906 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15907 | ||
15908 | if (!pll->on || pll->active) | |
15909 | continue; | |
15910 | ||
15911 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15912 | ||
15913 | pll->disable(dev_priv, pll); | |
15914 | pll->on = false; | |
15915 | } | |
15916 | ||
666a4537 | 15917 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15918 | vlv_wm_get_hw_state(dev); |
15919 | else if (IS_GEN9(dev)) | |
3078999f PB |
15920 | skl_wm_get_hw_state(dev); |
15921 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15922 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15923 | |
15924 | for_each_intel_crtc(dev, crtc) { | |
15925 | unsigned long put_domains; | |
15926 | ||
74bff5f9 | 15927 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15928 | if (WARN_ON(put_domains)) |
15929 | modeset_put_power_domains(dev_priv, put_domains); | |
15930 | } | |
15931 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15932 | |
15933 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15934 | } |
7d0bc1ea | 15935 | |
043e9bda ML |
15936 | void intel_display_resume(struct drm_device *dev) |
15937 | { | |
e2c8b870 ML |
15938 | struct drm_i915_private *dev_priv = to_i915(dev); |
15939 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15940 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15941 | int ret; |
e2c8b870 | 15942 | bool setup = false; |
f30da187 | 15943 | |
e2c8b870 | 15944 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15945 | |
ea49c9ac ML |
15946 | /* |
15947 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15948 | * won't be taken. Unfortunately some probed state like | |
15949 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15950 | * it here for now. | |
15951 | */ | |
15952 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15953 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15954 | |
e2c8b870 ML |
15955 | retry: |
15956 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15957 | |
e2c8b870 ML |
15958 | if (ret == 0 && !setup) { |
15959 | setup = true; | |
043e9bda | 15960 | |
e2c8b870 ML |
15961 | intel_modeset_setup_hw_state(dev); |
15962 | i915_redisable_vga(dev); | |
45e2b5f6 | 15963 | } |
8af6cf88 | 15964 | |
e2c8b870 ML |
15965 | if (ret == 0 && state) { |
15966 | struct drm_crtc_state *crtc_state; | |
15967 | struct drm_crtc *crtc; | |
15968 | int i; | |
043e9bda | 15969 | |
e2c8b870 ML |
15970 | state->acquire_ctx = &ctx; |
15971 | ||
15972 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15973 | /* | |
15974 | * Force recalculation even if we restore | |
15975 | * current state. With fast modeset this may not result | |
15976 | * in a modeset when the state is compatible. | |
15977 | */ | |
15978 | crtc_state->mode_changed = true; | |
15979 | } | |
15980 | ||
15981 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15982 | } |
15983 | ||
e2c8b870 ML |
15984 | if (ret == -EDEADLK) { |
15985 | drm_modeset_backoff(&ctx); | |
15986 | goto retry; | |
15987 | } | |
043e9bda | 15988 | |
e2c8b870 ML |
15989 | drm_modeset_drop_locks(&ctx); |
15990 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15991 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15992 | |
e2c8b870 ML |
15993 | if (ret) { |
15994 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15995 | drm_atomic_state_free(state); | |
15996 | } | |
2c7111db CW |
15997 | } |
15998 | ||
15999 | void intel_modeset_gem_init(struct drm_device *dev) | |
16000 | { | |
484b41dd | 16001 | struct drm_crtc *c; |
2ff8fde1 | 16002 | struct drm_i915_gem_object *obj; |
e0d6149b | 16003 | int ret; |
484b41dd | 16004 | |
ae48434c | 16005 | intel_init_gt_powersave(dev); |
ae48434c | 16006 | |
1833b134 | 16007 | intel_modeset_init_hw(dev); |
02e792fb DV |
16008 | |
16009 | intel_setup_overlay(dev); | |
484b41dd JB |
16010 | |
16011 | /* | |
16012 | * Make sure any fbs we allocated at startup are properly | |
16013 | * pinned & fenced. When we do the allocation it's too early | |
16014 | * for this. | |
16015 | */ | |
70e1e0ec | 16016 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16017 | obj = intel_fb_obj(c->primary->fb); |
16018 | if (obj == NULL) | |
484b41dd JB |
16019 | continue; |
16020 | ||
e0d6149b TU |
16021 | mutex_lock(&dev->struct_mutex); |
16022 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
16023 | c->primary->fb, | |
7580d774 | 16024 | c->primary->state); |
e0d6149b TU |
16025 | mutex_unlock(&dev->struct_mutex); |
16026 | if (ret) { | |
484b41dd JB |
16027 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16028 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16029 | drm_framebuffer_unreference(c->primary->fb); |
16030 | c->primary->fb = NULL; | |
36750f28 | 16031 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16032 | update_state_fb(c->primary); |
36750f28 | 16033 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16034 | } |
16035 | } | |
0962c3c9 VS |
16036 | |
16037 | intel_backlight_register(dev); | |
79e53945 JB |
16038 | } |
16039 | ||
4932e2c3 ID |
16040 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16041 | { | |
16042 | struct drm_connector *connector = &intel_connector->base; | |
16043 | ||
16044 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16045 | drm_connector_unregister(connector); |
4932e2c3 ID |
16046 | } |
16047 | ||
79e53945 JB |
16048 | void intel_modeset_cleanup(struct drm_device *dev) |
16049 | { | |
652c393a | 16050 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16051 | struct intel_connector *connector; |
652c393a | 16052 | |
2eb5252e ID |
16053 | intel_disable_gt_powersave(dev); |
16054 | ||
0962c3c9 VS |
16055 | intel_backlight_unregister(dev); |
16056 | ||
fd0c0642 DV |
16057 | /* |
16058 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16059 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16060 | * experience fancy races otherwise. |
16061 | */ | |
2aeb7d3a | 16062 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16063 | |
fd0c0642 DV |
16064 | /* |
16065 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16066 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16067 | */ | |
f87ea761 | 16068 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16069 | |
723bfd70 JB |
16070 | intel_unregister_dsm_handler(); |
16071 | ||
c937ab3e | 16072 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16073 | |
1630fe75 CW |
16074 | /* flush any delayed tasks or pending work */ |
16075 | flush_scheduled_work(); | |
16076 | ||
db31af1d | 16077 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16078 | for_each_intel_connector(dev, connector) |
16079 | connector->unregister(connector); | |
d9255d57 | 16080 | |
79e53945 | 16081 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16082 | |
16083 | intel_cleanup_overlay(dev); | |
ae48434c | 16084 | |
ae48434c | 16085 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16086 | |
16087 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16088 | } |
16089 | ||
f1c79df3 ZW |
16090 | /* |
16091 | * Return which encoder is currently attached for connector. | |
16092 | */ | |
df0e9248 | 16093 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16094 | { |
df0e9248 CW |
16095 | return &intel_attached_encoder(connector)->base; |
16096 | } | |
f1c79df3 | 16097 | |
df0e9248 CW |
16098 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16099 | struct intel_encoder *encoder) | |
16100 | { | |
16101 | connector->encoder = encoder; | |
16102 | drm_mode_connector_attach_encoder(&connector->base, | |
16103 | &encoder->base); | |
79e53945 | 16104 | } |
28d52043 DA |
16105 | |
16106 | /* | |
16107 | * set vga decode state - true == enable VGA decode | |
16108 | */ | |
16109 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16110 | { | |
16111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16112 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16113 | u16 gmch_ctrl; |
16114 | ||
75fa041d CW |
16115 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16116 | DRM_ERROR("failed to read control word\n"); | |
16117 | return -EIO; | |
16118 | } | |
16119 | ||
c0cc8a55 CW |
16120 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16121 | return 0; | |
16122 | ||
28d52043 DA |
16123 | if (state) |
16124 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16125 | else | |
16126 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16127 | |
16128 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16129 | DRM_ERROR("failed to write control word\n"); | |
16130 | return -EIO; | |
16131 | } | |
16132 | ||
28d52043 DA |
16133 | return 0; |
16134 | } | |
c4a1d9e4 | 16135 | |
c4a1d9e4 | 16136 | struct intel_display_error_state { |
ff57f1b0 PZ |
16137 | |
16138 | u32 power_well_driver; | |
16139 | ||
63b66e5b CW |
16140 | int num_transcoders; |
16141 | ||
c4a1d9e4 CW |
16142 | struct intel_cursor_error_state { |
16143 | u32 control; | |
16144 | u32 position; | |
16145 | u32 base; | |
16146 | u32 size; | |
52331309 | 16147 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16148 | |
16149 | struct intel_pipe_error_state { | |
ddf9c536 | 16150 | bool power_domain_on; |
c4a1d9e4 | 16151 | u32 source; |
f301b1e1 | 16152 | u32 stat; |
52331309 | 16153 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16154 | |
16155 | struct intel_plane_error_state { | |
16156 | u32 control; | |
16157 | u32 stride; | |
16158 | u32 size; | |
16159 | u32 pos; | |
16160 | u32 addr; | |
16161 | u32 surface; | |
16162 | u32 tile_offset; | |
52331309 | 16163 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16164 | |
16165 | struct intel_transcoder_error_state { | |
ddf9c536 | 16166 | bool power_domain_on; |
63b66e5b CW |
16167 | enum transcoder cpu_transcoder; |
16168 | ||
16169 | u32 conf; | |
16170 | ||
16171 | u32 htotal; | |
16172 | u32 hblank; | |
16173 | u32 hsync; | |
16174 | u32 vtotal; | |
16175 | u32 vblank; | |
16176 | u32 vsync; | |
16177 | } transcoder[4]; | |
c4a1d9e4 CW |
16178 | }; |
16179 | ||
16180 | struct intel_display_error_state * | |
16181 | intel_display_capture_error_state(struct drm_device *dev) | |
16182 | { | |
fbee40df | 16183 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16184 | struct intel_display_error_state *error; |
63b66e5b CW |
16185 | int transcoders[] = { |
16186 | TRANSCODER_A, | |
16187 | TRANSCODER_B, | |
16188 | TRANSCODER_C, | |
16189 | TRANSCODER_EDP, | |
16190 | }; | |
c4a1d9e4 CW |
16191 | int i; |
16192 | ||
63b66e5b CW |
16193 | if (INTEL_INFO(dev)->num_pipes == 0) |
16194 | return NULL; | |
16195 | ||
9d1cb914 | 16196 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16197 | if (error == NULL) |
16198 | return NULL; | |
16199 | ||
190be112 | 16200 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16201 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16202 | ||
055e393f | 16203 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16204 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16205 | __intel_display_power_is_enabled(dev_priv, |
16206 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16207 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16208 | continue; |
16209 | ||
5efb3e28 VS |
16210 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16211 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16212 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16213 | |
16214 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16215 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16216 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16217 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16218 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16219 | } | |
ca291363 PZ |
16220 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16221 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16222 | if (INTEL_INFO(dev)->gen >= 4) { |
16223 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16224 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16225 | } | |
16226 | ||
c4a1d9e4 | 16227 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16228 | |
3abfce77 | 16229 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16230 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16231 | } |
16232 | ||
16233 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16234 | if (HAS_DDI(dev_priv->dev)) | |
16235 | error->num_transcoders++; /* Account for eDP. */ | |
16236 | ||
16237 | for (i = 0; i < error->num_transcoders; i++) { | |
16238 | enum transcoder cpu_transcoder = transcoders[i]; | |
16239 | ||
ddf9c536 | 16240 | error->transcoder[i].power_domain_on = |
f458ebbc | 16241 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16242 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16243 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16244 | continue; |
16245 | ||
63b66e5b CW |
16246 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16247 | ||
16248 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16249 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16250 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16251 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16252 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16253 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16254 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16255 | } |
16256 | ||
16257 | return error; | |
16258 | } | |
16259 | ||
edc3d884 MK |
16260 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16261 | ||
c4a1d9e4 | 16262 | void |
edc3d884 | 16263 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16264 | struct drm_device *dev, |
16265 | struct intel_display_error_state *error) | |
16266 | { | |
055e393f | 16267 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16268 | int i; |
16269 | ||
63b66e5b CW |
16270 | if (!error) |
16271 | return; | |
16272 | ||
edc3d884 | 16273 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16274 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16275 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16276 | error->power_well_driver); |
055e393f | 16277 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16278 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16279 | err_printf(m, " Power: %s\n", |
87ad3212 | 16280 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16281 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16282 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16283 | |
16284 | err_printf(m, "Plane [%d]:\n", i); | |
16285 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16286 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16287 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16288 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16289 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16290 | } |
4b71a570 | 16291 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16292 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16293 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16294 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16295 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16296 | } |
16297 | ||
edc3d884 MK |
16298 | err_printf(m, "Cursor [%d]:\n", i); |
16299 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16300 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16301 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16302 | } |
63b66e5b CW |
16303 | |
16304 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16305 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16306 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16307 | err_printf(m, " Power: %s\n", |
87ad3212 | 16308 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16309 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16310 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16311 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16312 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16313 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16314 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16315 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16316 | } | |
c4a1d9e4 | 16317 | } |