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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
8b99e68c CW |
348 | if (IS_GEN5(dev)) { |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
351 | } else | |
352 | return 27; | |
021357ac CW |
353 | } |
354 | ||
e4b36699 | 355 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
356 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
357 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
358 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
359 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
360 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
361 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
362 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
363 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
364 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
365 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 366 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
370 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
371 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
372 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
373 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
374 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
375 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
376 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
377 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
378 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
379 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 380 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
381 | }; |
382 | ||
383 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
384 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
385 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
386 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
387 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
388 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
389 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
390 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
391 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
392 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
393 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 394 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
395 | }; |
396 | ||
397 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
398 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
399 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
400 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
401 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
402 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
403 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
404 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
405 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
406 | /* The single-channel range is 25-112Mhz, and dual-channel | |
407 | * is 80-224Mhz. Prefer single channel as much as possible. | |
408 | */ | |
409 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
410 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 411 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
412 | }; |
413 | ||
044c7c41 | 414 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 415 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
416 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
417 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
418 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
419 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
420 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
421 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
422 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
423 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
424 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
425 | .p2_slow = G4X_P2_SDVO_SLOW, | |
426 | .p2_fast = G4X_P2_SDVO_FAST | |
427 | }, | |
d4906093 | 428 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
429 | }; |
430 | ||
431 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
432 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
433 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
434 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
435 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
436 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
437 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
438 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
439 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
440 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
441 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
442 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
443 | }, | |
d4906093 | 444 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
445 | }; |
446 | ||
447 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
448 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
449 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
450 | .vco = { .min = G4X_VCO_MIN, | |
451 | .max = G4X_VCO_MAX }, | |
452 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
453 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
454 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
455 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
456 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
457 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
458 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
459 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
460 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
461 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
462 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
463 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
464 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
465 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
466 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
467 | }, | |
d4906093 | 468 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
469 | }; |
470 | ||
471 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
472 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
473 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
474 | .vco = { .min = G4X_VCO_MIN, | |
475 | .max = G4X_VCO_MAX }, | |
476 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
477 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
478 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
479 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
480 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
481 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
482 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
483 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
484 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
485 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
486 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
487 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
488 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
489 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
490 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
491 | }, | |
d4906093 | 492 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
493 | }; |
494 | ||
495 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
496 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
497 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
498 | .vco = { .min = G4X_VCO_MIN, | |
499 | .max = G4X_VCO_MAX}, | |
500 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
501 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
502 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
503 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
504 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
505 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
506 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
507 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
508 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
509 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
510 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
511 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
512 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
513 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
514 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
515 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
516 | }; |
517 | ||
f2b115e6 | 518 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 519 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
520 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
521 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
522 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
523 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
524 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
525 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
526 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
527 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
528 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 529 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
530 | }; |
531 | ||
f2b115e6 | 532 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 533 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
534 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
535 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
536 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
537 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
538 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
539 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 540 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 541 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
542 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
543 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 544 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
545 | }; |
546 | ||
b91ad0ec | 547 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
548 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
549 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
550 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
551 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
552 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
553 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
554 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
555 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 556 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
557 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
558 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 559 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
560 | }; |
561 | ||
b91ad0ec | 562 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
563 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
564 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
565 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
566 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
567 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
568 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
569 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
570 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 571 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
572 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
573 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
574 | .find_pll = intel_g4x_find_best_PLL, | |
575 | }; | |
576 | ||
577 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
578 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
579 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
580 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
581 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
582 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
583 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
584 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
585 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
586 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
587 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
588 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
589 | .find_pll = intel_g4x_find_best_PLL, | |
590 | }; | |
591 | ||
592 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
593 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
594 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
595 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
596 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
597 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
598 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
599 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
600 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
601 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
602 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
603 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
604 | .find_pll = intel_g4x_find_best_PLL, | |
605 | }; | |
606 | ||
607 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
608 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
609 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
610 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
611 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
612 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
613 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
614 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
615 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
616 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
617 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
618 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
619 | .find_pll = intel_g4x_find_best_PLL, |
620 | }; | |
621 | ||
622 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
623 | .dot = { .min = IRONLAKE_DOT_MIN, | |
624 | .max = IRONLAKE_DOT_MAX }, | |
625 | .vco = { .min = IRONLAKE_VCO_MIN, | |
626 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
627 | .n = { .min = IRONLAKE_DP_N_MIN, |
628 | .max = IRONLAKE_DP_N_MAX }, | |
629 | .m = { .min = IRONLAKE_DP_M_MIN, | |
630 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
631 | .m1 = { .min = IRONLAKE_M1_MIN, |
632 | .max = IRONLAKE_M1_MAX }, | |
633 | .m2 = { .min = IRONLAKE_M2_MIN, | |
634 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
635 | .p = { .min = IRONLAKE_DP_P_MIN, |
636 | .max = IRONLAKE_DP_P_MAX }, | |
637 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
638 | .max = IRONLAKE_DP_P1_MAX}, | |
639 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
640 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
641 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 642 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
643 | }; |
644 | ||
1b894b59 CW |
645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
646 | int refclk) | |
2c07245f | 647 | { |
b91ad0ec ZW |
648 | struct drm_device *dev = crtc->dev; |
649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 650 | const intel_limit_t *limit; |
b91ad0ec ZW |
651 | |
652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
654 | LVDS_CLKB_POWER_UP) { | |
655 | /* LVDS dual channel */ | |
1b894b59 | 656 | if (refclk == 100000) |
b91ad0ec ZW |
657 | limit = &intel_limits_ironlake_dual_lvds_100m; |
658 | else | |
659 | limit = &intel_limits_ironlake_dual_lvds; | |
660 | } else { | |
1b894b59 | 661 | if (refclk == 100000) |
b91ad0ec ZW |
662 | limit = &intel_limits_ironlake_single_lvds_100m; |
663 | else | |
664 | limit = &intel_limits_ironlake_single_lvds; | |
665 | } | |
666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
667 | HAS_eDP) |
668 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 669 | else |
b91ad0ec | 670 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
671 | |
672 | return limit; | |
673 | } | |
674 | ||
044c7c41 ML |
675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
676 | { | |
677 | struct drm_device *dev = crtc->dev; | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | const intel_limit_t *limit; | |
680 | ||
681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
683 | LVDS_CLKB_POWER_UP) | |
684 | /* LVDS with dual channel */ | |
e4b36699 | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
686 | else |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 691 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 693 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 695 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 696 | } else /* The option is for other outputs */ |
e4b36699 | 697 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
698 | |
699 | return limit; | |
700 | } | |
701 | ||
1b894b59 | 702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
703 | { |
704 | struct drm_device *dev = crtc->dev; | |
705 | const intel_limit_t *limit; | |
706 | ||
bad720ff | 707 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 708 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 709 | else if (IS_G4X(dev)) { |
044c7c41 | 710 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 711 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 713 | limit = &intel_limits_pineview_lvds; |
2177832f | 714 | else |
f2b115e6 | 715 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
716 | } else if (!IS_GEN2(dev)) { |
717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
718 | limit = &intel_limits_i9xx_lvds; | |
719 | else | |
720 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
721 | } else { |
722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 723 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 724 | else |
e4b36699 | 725 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
726 | } |
727 | return limit; | |
728 | } | |
729 | ||
f2b115e6 AJ |
730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
731 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 732 | { |
2177832f SL |
733 | clock->m = clock->m2 + 2; |
734 | clock->p = clock->p1 * clock->p2; | |
735 | clock->vco = refclk * clock->m / clock->n; | |
736 | clock->dot = clock->vco / clock->p; | |
737 | } | |
738 | ||
739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
740 | { | |
f2b115e6 AJ |
741 | if (IS_PINEVIEW(dev)) { |
742 | pineview_clock(refclk, clock); | |
2177832f SL |
743 | return; |
744 | } | |
79e53945 JB |
745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
746 | clock->p = clock->p1 * clock->p2; | |
747 | clock->vco = refclk * clock->m / (clock->n + 2); | |
748 | clock->dot = clock->vco / clock->p; | |
749 | } | |
750 | ||
79e53945 JB |
751 | /** |
752 | * Returns whether any output on the specified pipe is of the specified type | |
753 | */ | |
4ef69c7a | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 755 | { |
4ef69c7a CW |
756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_mode_config *mode_config = &dev->mode_config; | |
758 | struct intel_encoder *encoder; | |
759 | ||
760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
761 | if (encoder->base.crtc == crtc && encoder->type == type) | |
762 | return true; | |
763 | ||
764 | return false; | |
79e53945 JB |
765 | } |
766 | ||
7c04d1d9 | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
768 | /** |
769 | * Returns whether the given set of divisors are valid for a given refclk with | |
770 | * the given connectors. | |
771 | */ | |
772 | ||
1b894b59 CW |
773 | static bool intel_PLL_is_valid(struct drm_device *dev, |
774 | const intel_limit_t *limit, | |
775 | const intel_clock_t *clock) | |
79e53945 | 776 | { |
79e53945 JB |
777 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
778 | INTELPllInvalid ("p1 out of range\n"); | |
779 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
780 | INTELPllInvalid ("p out of range\n"); | |
781 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
782 | INTELPllInvalid ("m2 out of range\n"); | |
783 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
784 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 785 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
786 | INTELPllInvalid ("m1 <= m2\n"); |
787 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
788 | INTELPllInvalid ("m out of range\n"); | |
789 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
790 | INTELPllInvalid ("n out of range\n"); | |
791 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
792 | INTELPllInvalid ("vco out of range\n"); | |
793 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
794 | * connector, etc., rather than just a single range. | |
795 | */ | |
796 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
797 | INTELPllInvalid ("dot out of range\n"); | |
798 | ||
799 | return true; | |
800 | } | |
801 | ||
d4906093 ML |
802 | static bool |
803 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
804 | int target, int refclk, intel_clock_t *best_clock) | |
805 | ||
79e53945 JB |
806 | { |
807 | struct drm_device *dev = crtc->dev; | |
808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
809 | intel_clock_t clock; | |
79e53945 JB |
810 | int err = target; |
811 | ||
bc5e5718 | 812 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 813 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
814 | /* |
815 | * For LVDS, if the panel is on, just rely on its current | |
816 | * settings for dual-channel. We haven't figured out how to | |
817 | * reliably set up different single/dual channel state, if we | |
818 | * even can. | |
819 | */ | |
820 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
821 | LVDS_CLKB_POWER_UP) | |
822 | clock.p2 = limit->p2.p2_fast; | |
823 | else | |
824 | clock.p2 = limit->p2.p2_slow; | |
825 | } else { | |
826 | if (target < limit->p2.dot_limit) | |
827 | clock.p2 = limit->p2.p2_slow; | |
828 | else | |
829 | clock.p2 = limit->p2.p2_fast; | |
830 | } | |
831 | ||
832 | memset (best_clock, 0, sizeof (*best_clock)); | |
833 | ||
42158660 ZY |
834 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
835 | clock.m1++) { | |
836 | for (clock.m2 = limit->m2.min; | |
837 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
838 | /* m1 is always 0 in Pineview */ |
839 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
840 | break; |
841 | for (clock.n = limit->n.min; | |
842 | clock.n <= limit->n.max; clock.n++) { | |
843 | for (clock.p1 = limit->p1.min; | |
844 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
845 | int this_err; |
846 | ||
2177832f | 847 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
848 | if (!intel_PLL_is_valid(dev, limit, |
849 | &clock)) | |
79e53945 JB |
850 | continue; |
851 | ||
852 | this_err = abs(clock.dot - target); | |
853 | if (this_err < err) { | |
854 | *best_clock = clock; | |
855 | err = this_err; | |
856 | } | |
857 | } | |
858 | } | |
859 | } | |
860 | } | |
861 | ||
862 | return (err != target); | |
863 | } | |
864 | ||
d4906093 ML |
865 | static bool |
866 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
867 | int target, int refclk, intel_clock_t *best_clock) | |
868 | { | |
869 | struct drm_device *dev = crtc->dev; | |
870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
871 | intel_clock_t clock; | |
872 | int max_n; | |
873 | bool found; | |
6ba770dc AJ |
874 | /* approximately equals target * 0.00585 */ |
875 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
876 | found = false; |
877 | ||
878 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
879 | int lvds_reg; |
880 | ||
c619eed4 | 881 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
882 | lvds_reg = PCH_LVDS; |
883 | else | |
884 | lvds_reg = LVDS; | |
885 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
886 | LVDS_CLKB_POWER_UP) |
887 | clock.p2 = limit->p2.p2_fast; | |
888 | else | |
889 | clock.p2 = limit->p2.p2_slow; | |
890 | } else { | |
891 | if (target < limit->p2.dot_limit) | |
892 | clock.p2 = limit->p2.p2_slow; | |
893 | else | |
894 | clock.p2 = limit->p2.p2_fast; | |
895 | } | |
896 | ||
897 | memset(best_clock, 0, sizeof(*best_clock)); | |
898 | max_n = limit->n.max; | |
f77f13e2 | 899 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 900 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 901 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
902 | for (clock.m1 = limit->m1.max; |
903 | clock.m1 >= limit->m1.min; clock.m1--) { | |
904 | for (clock.m2 = limit->m2.max; | |
905 | clock.m2 >= limit->m2.min; clock.m2--) { | |
906 | for (clock.p1 = limit->p1.max; | |
907 | clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | int this_err; | |
909 | ||
2177832f | 910 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | |
d4906093 | 913 | continue; |
1b894b59 CW |
914 | |
915 | this_err = abs(clock.dot - target); | |
d4906093 ML |
916 | if (this_err < err_most) { |
917 | *best_clock = clock; | |
918 | err_most = this_err; | |
919 | max_n = clock.n; | |
920 | found = true; | |
921 | } | |
922 | } | |
923 | } | |
924 | } | |
925 | } | |
2c07245f ZW |
926 | return found; |
927 | } | |
928 | ||
5eb08b69 | 929 | static bool |
f2b115e6 AJ |
930 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
931 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
932 | { |
933 | struct drm_device *dev = crtc->dev; | |
934 | intel_clock_t clock; | |
4547668a | 935 | |
5eb08b69 ZW |
936 | if (target < 200000) { |
937 | clock.n = 1; | |
938 | clock.p1 = 2; | |
939 | clock.p2 = 10; | |
940 | clock.m1 = 12; | |
941 | clock.m2 = 9; | |
942 | } else { | |
943 | clock.n = 2; | |
944 | clock.p1 = 1; | |
945 | clock.p2 = 10; | |
946 | clock.m1 = 14; | |
947 | clock.m2 = 8; | |
948 | } | |
949 | intel_clock(dev, refclk, &clock); | |
950 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
951 | return true; | |
952 | } | |
953 | ||
a4fc5ed6 KP |
954 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
955 | static bool | |
956 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
957 | int target, int refclk, intel_clock_t *best_clock) | |
958 | { | |
5eddb70b CW |
959 | intel_clock_t clock; |
960 | if (target < 200000) { | |
961 | clock.p1 = 2; | |
962 | clock.p2 = 10; | |
963 | clock.n = 2; | |
964 | clock.m1 = 23; | |
965 | clock.m2 = 8; | |
966 | } else { | |
967 | clock.p1 = 1; | |
968 | clock.p2 = 10; | |
969 | clock.n = 1; | |
970 | clock.m1 = 14; | |
971 | clock.m2 = 2; | |
972 | } | |
973 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
974 | clock.p = (clock.p1 * clock.p2); | |
975 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
976 | clock.vco = 0; | |
977 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
978 | return true; | |
a4fc5ed6 KP |
979 | } |
980 | ||
9d0498a2 JB |
981 | /** |
982 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
983 | * @dev: drm device | |
984 | * @pipe: pipe to wait for | |
985 | * | |
986 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
987 | * mode setting code. | |
988 | */ | |
989 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 990 | { |
9d0498a2 | 991 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 992 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 993 | |
300387c0 CW |
994 | /* Clear existing vblank status. Note this will clear any other |
995 | * sticky status fields as well. | |
996 | * | |
997 | * This races with i915_driver_irq_handler() with the result | |
998 | * that either function could miss a vblank event. Here it is not | |
999 | * fatal, as we will either wait upon the next vblank interrupt or | |
1000 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1001 | * called during modeset at which time the GPU should be idle and | |
1002 | * should *not* be performing page flips and thus not waiting on | |
1003 | * vblanks... | |
1004 | * Currently, the result of us stealing a vblank from the irq | |
1005 | * handler is that a single frame will be skipped during swapbuffers. | |
1006 | */ | |
1007 | I915_WRITE(pipestat_reg, | |
1008 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1009 | ||
9d0498a2 | 1010 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1011 | if (wait_for(I915_READ(pipestat_reg) & |
1012 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1013 | 50)) | |
9d0498a2 JB |
1014 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1015 | } | |
1016 | ||
ab7ad7f6 KP |
1017 | /* |
1018 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
1019 | * @dev: drm device |
1020 | * @pipe: pipe to wait for | |
1021 | * | |
1022 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1023 | * spinning on the vblank interrupt status bit, since we won't actually | |
1024 | * see an interrupt when the pipe is disabled. | |
1025 | * | |
ab7ad7f6 KP |
1026 | * On Gen4 and above: |
1027 | * wait for the pipe register state bit to turn off | |
1028 | * | |
1029 | * Otherwise: | |
1030 | * wait for the display line value to settle (it usually | |
1031 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1032 | * |
9d0498a2 | 1033 | */ |
58e10eb9 | 1034 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1035 | { |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1037 | |
1038 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1039 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1040 | |
1041 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1042 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1043 | 100)) | |
ab7ad7f6 KP |
1044 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1045 | } else { | |
1046 | u32 last_line; | |
58e10eb9 | 1047 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1048 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1049 | ||
1050 | /* Wait for the display line to settle */ | |
1051 | do { | |
58e10eb9 | 1052 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 1053 | mdelay(5); |
58e10eb9 | 1054 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
1055 | time_after(timeout, jiffies)); |
1056 | if (time_after(jiffies, timeout)) | |
1057 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1058 | } | |
79e53945 JB |
1059 | } |
1060 | ||
b24e7179 JB |
1061 | static const char *state_string(bool enabled) |
1062 | { | |
1063 | return enabled ? "on" : "off"; | |
1064 | } | |
1065 | ||
1066 | /* Only for pre-ILK configs */ | |
1067 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1068 | enum pipe pipe, bool state) | |
1069 | { | |
1070 | int reg; | |
1071 | u32 val; | |
1072 | bool cur_state; | |
1073 | ||
1074 | reg = DPLL(pipe); | |
1075 | val = I915_READ(reg); | |
1076 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1077 | WARN(cur_state != state, | |
1078 | "PLL state assertion failure (expected %s, current %s)\n", | |
1079 | state_string(state), state_string(cur_state)); | |
1080 | } | |
1081 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1082 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1083 | ||
040484af JB |
1084 | /* For ILK+ */ |
1085 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
1088 | int reg; | |
1089 | u32 val; | |
1090 | bool cur_state; | |
1091 | ||
1092 | reg = PCH_DPLL(pipe); | |
1093 | val = I915_READ(reg); | |
1094 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1095 | WARN(cur_state != state, | |
1096 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
1097 | state_string(state), state_string(cur_state)); | |
1098 | } | |
1099 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
1100 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
1101 | ||
1102 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1103 | enum pipe pipe, bool state) | |
1104 | { | |
1105 | int reg; | |
1106 | u32 val; | |
1107 | bool cur_state; | |
1108 | ||
1109 | reg = FDI_TX_CTL(pipe); | |
1110 | val = I915_READ(reg); | |
1111 | cur_state = !!(val & FDI_TX_ENABLE); | |
1112 | WARN(cur_state != state, | |
1113 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1114 | state_string(state), state_string(cur_state)); | |
1115 | } | |
1116 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1117 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1118 | ||
1119 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1120 | enum pipe pipe, bool state) | |
1121 | { | |
1122 | int reg; | |
1123 | u32 val; | |
1124 | bool cur_state; | |
1125 | ||
1126 | reg = FDI_RX_CTL(pipe); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & FDI_RX_ENABLE); | |
1129 | WARN(cur_state != state, | |
1130 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1131 | state_string(state), state_string(cur_state)); | |
1132 | } | |
1133 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1134 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1135 | ||
1136 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1137 | enum pipe pipe) | |
1138 | { | |
1139 | int reg; | |
1140 | u32 val; | |
1141 | ||
1142 | /* ILK FDI PLL is always enabled */ | |
1143 | if (dev_priv->info->gen == 5) | |
1144 | return; | |
1145 | ||
1146 | reg = FDI_TX_CTL(pipe); | |
1147 | val = I915_READ(reg); | |
1148 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1149 | } | |
1150 | ||
1151 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1152 | enum pipe pipe) | |
1153 | { | |
1154 | int reg; | |
1155 | u32 val; | |
1156 | ||
1157 | reg = FDI_RX_CTL(pipe); | |
1158 | val = I915_READ(reg); | |
1159 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1160 | } | |
1161 | ||
ea0760cf JB |
1162 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1163 | enum pipe pipe) | |
1164 | { | |
1165 | int pp_reg, lvds_reg; | |
1166 | u32 val; | |
1167 | enum pipe panel_pipe = PIPE_A; | |
1168 | bool locked = locked; | |
1169 | ||
1170 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1171 | pp_reg = PCH_PP_CONTROL; | |
1172 | lvds_reg = PCH_LVDS; | |
1173 | } else { | |
1174 | pp_reg = PP_CONTROL; | |
1175 | lvds_reg = LVDS; | |
1176 | } | |
1177 | ||
1178 | val = I915_READ(pp_reg); | |
1179 | if (!(val & PANEL_POWER_ON) || | |
1180 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1181 | locked = false; | |
1182 | ||
1183 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1184 | panel_pipe = PIPE_B; | |
1185 | ||
1186 | WARN(panel_pipe == pipe && locked, | |
1187 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1188 | pipe_name(pipe)); |
ea0760cf JB |
1189 | } |
1190 | ||
63d7bbe9 JB |
1191 | static void assert_pipe(struct drm_i915_private *dev_priv, |
1192 | enum pipe pipe, bool state) | |
b24e7179 JB |
1193 | { |
1194 | int reg; | |
1195 | u32 val; | |
63d7bbe9 | 1196 | bool cur_state; |
b24e7179 JB |
1197 | |
1198 | reg = PIPECONF(pipe); | |
1199 | val = I915_READ(reg); | |
63d7bbe9 JB |
1200 | cur_state = !!(val & PIPECONF_ENABLE); |
1201 | WARN(cur_state != state, | |
1202 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1203 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 | 1204 | } |
63d7bbe9 JB |
1205 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1206 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
b24e7179 JB |
1207 | |
1208 | static void assert_plane_enabled(struct drm_i915_private *dev_priv, | |
1209 | enum plane plane) | |
1210 | { | |
1211 | int reg; | |
1212 | u32 val; | |
1213 | ||
1214 | reg = DSPCNTR(plane); | |
1215 | val = I915_READ(reg); | |
1216 | WARN(!(val & DISPLAY_PLANE_ENABLE), | |
1217 | "plane %c assertion failure, should be active but is disabled\n", | |
9db4a9c7 | 1218 | plane_name(plane)); |
b24e7179 JB |
1219 | } |
1220 | ||
1221 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, | |
1222 | enum pipe pipe) | |
1223 | { | |
1224 | int reg, i; | |
1225 | u32 val; | |
1226 | int cur_pipe; | |
1227 | ||
19ec1358 JB |
1228 | /* Planes are fixed to pipes on ILK+ */ |
1229 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
1230 | return; | |
1231 | ||
b24e7179 JB |
1232 | /* Need to check both planes against the pipe */ |
1233 | for (i = 0; i < 2; i++) { | |
1234 | reg = DSPCNTR(i); | |
1235 | val = I915_READ(reg); | |
1236 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1237 | DISPPLANE_SEL_PIPE_SHIFT; | |
1238 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1239 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1240 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1241 | } |
1242 | } | |
1243 | ||
92f2584a JB |
1244 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1245 | { | |
1246 | u32 val; | |
1247 | bool enabled; | |
1248 | ||
1249 | val = I915_READ(PCH_DREF_CONTROL); | |
1250 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1251 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1252 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1253 | } | |
1254 | ||
1255 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1256 | enum pipe pipe) | |
1257 | { | |
1258 | int reg; | |
1259 | u32 val; | |
1260 | bool enabled; | |
1261 | ||
1262 | reg = TRANSCONF(pipe); | |
1263 | val = I915_READ(reg); | |
1264 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1265 | WARN(enabled, |
1266 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1267 | pipe_name(pipe)); | |
92f2584a JB |
1268 | } |
1269 | ||
291906f1 JB |
1270 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1271 | enum pipe pipe, int reg) | |
1272 | { | |
47a05eca JB |
1273 | u32 val = I915_READ(reg); |
1274 | WARN(DP_PIPE_ENABLED(val, pipe), | |
291906f1 | 1275 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1276 | reg, pipe_name(pipe)); |
291906f1 JB |
1277 | } |
1278 | ||
1279 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1280 | enum pipe pipe, int reg) | |
1281 | { | |
47a05eca JB |
1282 | u32 val = I915_READ(reg); |
1283 | WARN(HDMI_PIPE_ENABLED(val, pipe), | |
291906f1 | 1284 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1285 | reg, pipe_name(pipe)); |
291906f1 JB |
1286 | } |
1287 | ||
1288 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1289 | enum pipe pipe) | |
1290 | { | |
1291 | int reg; | |
1292 | u32 val; | |
291906f1 JB |
1293 | |
1294 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B); | |
1295 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C); | |
1296 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D); | |
1297 | ||
1298 | reg = PCH_ADPA; | |
1299 | val = I915_READ(reg); | |
47a05eca | 1300 | WARN(ADPA_PIPE_ENABLED(val, pipe), |
291906f1 | 1301 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1302 | pipe_name(pipe)); |
291906f1 JB |
1303 | |
1304 | reg = PCH_LVDS; | |
1305 | val = I915_READ(reg); | |
47a05eca | 1306 | WARN(LVDS_PIPE_ENABLED(val, pipe), |
291906f1 | 1307 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1308 | pipe_name(pipe)); |
291906f1 JB |
1309 | |
1310 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1311 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1312 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1313 | } | |
1314 | ||
63d7bbe9 JB |
1315 | /** |
1316 | * intel_enable_pll - enable a PLL | |
1317 | * @dev_priv: i915 private structure | |
1318 | * @pipe: pipe PLL to enable | |
1319 | * | |
1320 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1321 | * make sure the PLL reg is writable first though, since the panel write | |
1322 | * protect mechanism may be enabled. | |
1323 | * | |
1324 | * Note! This is for pre-ILK only. | |
1325 | */ | |
1326 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1327 | { | |
1328 | int reg; | |
1329 | u32 val; | |
1330 | ||
1331 | /* No really, not for ILK+ */ | |
1332 | BUG_ON(dev_priv->info->gen >= 5); | |
1333 | ||
1334 | /* PLL is protected by panel, make sure we can write it */ | |
1335 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1336 | assert_panel_unlocked(dev_priv, pipe); | |
1337 | ||
1338 | reg = DPLL(pipe); | |
1339 | val = I915_READ(reg); | |
1340 | val |= DPLL_VCO_ENABLE; | |
1341 | ||
1342 | /* We do this three times for luck */ | |
1343 | I915_WRITE(reg, val); | |
1344 | POSTING_READ(reg); | |
1345 | udelay(150); /* wait for warmup */ | |
1346 | I915_WRITE(reg, val); | |
1347 | POSTING_READ(reg); | |
1348 | udelay(150); /* wait for warmup */ | |
1349 | I915_WRITE(reg, val); | |
1350 | POSTING_READ(reg); | |
1351 | udelay(150); /* wait for warmup */ | |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * intel_disable_pll - disable a PLL | |
1356 | * @dev_priv: i915 private structure | |
1357 | * @pipe: pipe PLL to disable | |
1358 | * | |
1359 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1360 | * | |
1361 | * Note! This is for pre-ILK only. | |
1362 | */ | |
1363 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1364 | { | |
1365 | int reg; | |
1366 | u32 val; | |
1367 | ||
1368 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1369 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1370 | return; | |
1371 | ||
1372 | /* Make sure the pipe isn't still relying on us */ | |
1373 | assert_pipe_disabled(dev_priv, pipe); | |
1374 | ||
1375 | reg = DPLL(pipe); | |
1376 | val = I915_READ(reg); | |
1377 | val &= ~DPLL_VCO_ENABLE; | |
1378 | I915_WRITE(reg, val); | |
1379 | POSTING_READ(reg); | |
1380 | } | |
1381 | ||
92f2584a JB |
1382 | /** |
1383 | * intel_enable_pch_pll - enable PCH PLL | |
1384 | * @dev_priv: i915 private structure | |
1385 | * @pipe: pipe PLL to enable | |
1386 | * | |
1387 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1388 | * drives the transcoder clock. | |
1389 | */ | |
1390 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1391 | enum pipe pipe) | |
1392 | { | |
1393 | int reg; | |
1394 | u32 val; | |
1395 | ||
1396 | /* PCH only available on ILK+ */ | |
1397 | BUG_ON(dev_priv->info->gen < 5); | |
1398 | ||
1399 | /* PCH refclock must be enabled first */ | |
1400 | assert_pch_refclk_enabled(dev_priv); | |
1401 | ||
1402 | reg = PCH_DPLL(pipe); | |
1403 | val = I915_READ(reg); | |
1404 | val |= DPLL_VCO_ENABLE; | |
1405 | I915_WRITE(reg, val); | |
1406 | POSTING_READ(reg); | |
1407 | udelay(200); | |
1408 | } | |
1409 | ||
1410 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1411 | enum pipe pipe) | |
1412 | { | |
1413 | int reg; | |
1414 | u32 val; | |
1415 | ||
1416 | /* PCH only available on ILK+ */ | |
1417 | BUG_ON(dev_priv->info->gen < 5); | |
1418 | ||
1419 | /* Make sure transcoder isn't still depending on us */ | |
1420 | assert_transcoder_disabled(dev_priv, pipe); | |
1421 | ||
1422 | reg = PCH_DPLL(pipe); | |
1423 | val = I915_READ(reg); | |
1424 | val &= ~DPLL_VCO_ENABLE; | |
1425 | I915_WRITE(reg, val); | |
1426 | POSTING_READ(reg); | |
1427 | udelay(200); | |
1428 | } | |
1429 | ||
040484af JB |
1430 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1431 | enum pipe pipe) | |
1432 | { | |
1433 | int reg; | |
1434 | u32 val; | |
1435 | ||
1436 | /* PCH only available on ILK+ */ | |
1437 | BUG_ON(dev_priv->info->gen < 5); | |
1438 | ||
1439 | /* Make sure PCH DPLL is enabled */ | |
1440 | assert_pch_pll_enabled(dev_priv, pipe); | |
1441 | ||
1442 | /* FDI must be feeding us bits for PCH ports */ | |
1443 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1444 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1445 | ||
1446 | reg = TRANSCONF(pipe); | |
1447 | val = I915_READ(reg); | |
1448 | /* | |
1449 | * make the BPC in transcoder be consistent with | |
1450 | * that in pipeconf reg. | |
1451 | */ | |
1452 | val &= ~PIPE_BPC_MASK; | |
1453 | val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; | |
1454 | I915_WRITE(reg, val | TRANS_ENABLE); | |
1455 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1456 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1457 | } | |
1458 | ||
1459 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1460 | enum pipe pipe) | |
1461 | { | |
1462 | int reg; | |
1463 | u32 val; | |
1464 | ||
1465 | /* FDI relies on the transcoder */ | |
1466 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1467 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1468 | ||
291906f1 JB |
1469 | /* Ports must be off as well */ |
1470 | assert_pch_ports_disabled(dev_priv, pipe); | |
1471 | ||
040484af JB |
1472 | reg = TRANSCONF(pipe); |
1473 | val = I915_READ(reg); | |
1474 | val &= ~TRANS_ENABLE; | |
1475 | I915_WRITE(reg, val); | |
1476 | /* wait for PCH transcoder off, transcoder state */ | |
1477 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
1478 | DRM_ERROR("failed to disable transcoder\n"); | |
1479 | } | |
1480 | ||
b24e7179 | 1481 | /** |
309cfea8 | 1482 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1483 | * @dev_priv: i915 private structure |
1484 | * @pipe: pipe to enable | |
040484af | 1485 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1486 | * |
1487 | * Enable @pipe, making sure that various hardware specific requirements | |
1488 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1489 | * | |
1490 | * @pipe should be %PIPE_A or %PIPE_B. | |
1491 | * | |
1492 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1493 | * returning. | |
1494 | */ | |
040484af JB |
1495 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1496 | bool pch_port) | |
b24e7179 JB |
1497 | { |
1498 | int reg; | |
1499 | u32 val; | |
1500 | ||
1501 | /* | |
1502 | * A pipe without a PLL won't actually be able to drive bits from | |
1503 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1504 | * need the check. | |
1505 | */ | |
1506 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1507 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1508 | else { |
1509 | if (pch_port) { | |
1510 | /* if driving the PCH, we need FDI enabled */ | |
1511 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1512 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1513 | } | |
1514 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1515 | } | |
b24e7179 JB |
1516 | |
1517 | reg = PIPECONF(pipe); | |
1518 | val = I915_READ(reg); | |
00d70b15 CW |
1519 | if (val & PIPECONF_ENABLE) |
1520 | return; | |
1521 | ||
1522 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1523 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1524 | } | |
1525 | ||
1526 | /** | |
309cfea8 | 1527 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1528 | * @dev_priv: i915 private structure |
1529 | * @pipe: pipe to disable | |
1530 | * | |
1531 | * Disable @pipe, making sure that various hardware specific requirements | |
1532 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1533 | * | |
1534 | * @pipe should be %PIPE_A or %PIPE_B. | |
1535 | * | |
1536 | * Will wait until the pipe has shut down before returning. | |
1537 | */ | |
1538 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1539 | enum pipe pipe) | |
1540 | { | |
1541 | int reg; | |
1542 | u32 val; | |
1543 | ||
1544 | /* | |
1545 | * Make sure planes won't keep trying to pump pixels to us, | |
1546 | * or we might hang the display. | |
1547 | */ | |
1548 | assert_planes_disabled(dev_priv, pipe); | |
1549 | ||
1550 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1551 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1552 | return; | |
1553 | ||
1554 | reg = PIPECONF(pipe); | |
1555 | val = I915_READ(reg); | |
00d70b15 CW |
1556 | if ((val & PIPECONF_ENABLE) == 0) |
1557 | return; | |
1558 | ||
1559 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1560 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1561 | } | |
1562 | ||
1563 | /** | |
1564 | * intel_enable_plane - enable a display plane on a given pipe | |
1565 | * @dev_priv: i915 private structure | |
1566 | * @plane: plane to enable | |
1567 | * @pipe: pipe being fed | |
1568 | * | |
1569 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1570 | */ | |
1571 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1572 | enum plane plane, enum pipe pipe) | |
1573 | { | |
1574 | int reg; | |
1575 | u32 val; | |
1576 | ||
1577 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1578 | assert_pipe_enabled(dev_priv, pipe); | |
1579 | ||
1580 | reg = DSPCNTR(plane); | |
1581 | val = I915_READ(reg); | |
00d70b15 CW |
1582 | if (val & DISPLAY_PLANE_ENABLE) |
1583 | return; | |
1584 | ||
1585 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1586 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1587 | } | |
1588 | ||
1589 | /* | |
1590 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1591 | * trigger in order to latch. The display address reg provides this. | |
1592 | */ | |
1593 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1594 | enum plane plane) | |
1595 | { | |
1596 | u32 reg = DSPADDR(plane); | |
1597 | I915_WRITE(reg, I915_READ(reg)); | |
1598 | } | |
1599 | ||
1600 | /** | |
1601 | * intel_disable_plane - disable a display plane | |
1602 | * @dev_priv: i915 private structure | |
1603 | * @plane: plane to disable | |
1604 | * @pipe: pipe consuming the data | |
1605 | * | |
1606 | * Disable @plane; should be an independent operation. | |
1607 | */ | |
1608 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1609 | enum plane plane, enum pipe pipe) | |
1610 | { | |
1611 | int reg; | |
1612 | u32 val; | |
1613 | ||
1614 | reg = DSPCNTR(plane); | |
1615 | val = I915_READ(reg); | |
00d70b15 CW |
1616 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1617 | return; | |
1618 | ||
1619 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1620 | intel_flush_display_plane(dev_priv, plane); |
1621 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1622 | } | |
1623 | ||
47a05eca JB |
1624 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
1625 | enum pipe pipe, int reg) | |
1626 | { | |
1627 | u32 val = I915_READ(reg); | |
1628 | if (DP_PIPE_ENABLED(val, pipe)) | |
1629 | I915_WRITE(reg, val & ~DP_PORT_EN); | |
1630 | } | |
1631 | ||
1632 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1633 | enum pipe pipe, int reg) | |
1634 | { | |
1635 | u32 val = I915_READ(reg); | |
1636 | if (HDMI_PIPE_ENABLED(val, pipe)) | |
1637 | I915_WRITE(reg, val & ~PORT_ENABLE); | |
1638 | } | |
1639 | ||
1640 | /* Disable any ports connected to this transcoder */ | |
1641 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1642 | enum pipe pipe) | |
1643 | { | |
1644 | u32 reg, val; | |
1645 | ||
1646 | val = I915_READ(PCH_PP_CONTROL); | |
1647 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1648 | ||
1649 | disable_pch_dp(dev_priv, pipe, PCH_DP_B); | |
1650 | disable_pch_dp(dev_priv, pipe, PCH_DP_C); | |
1651 | disable_pch_dp(dev_priv, pipe, PCH_DP_D); | |
1652 | ||
1653 | reg = PCH_ADPA; | |
1654 | val = I915_READ(reg); | |
1655 | if (ADPA_PIPE_ENABLED(val, pipe)) | |
1656 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); | |
1657 | ||
1658 | reg = PCH_LVDS; | |
1659 | val = I915_READ(reg); | |
1660 | if (LVDS_PIPE_ENABLED(val, pipe)) { | |
1661 | I915_WRITE(reg, val & ~LVDS_PORT_EN); | |
1662 | POSTING_READ(reg); | |
1663 | udelay(100); | |
1664 | } | |
1665 | ||
1666 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1667 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1668 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1669 | } | |
1670 | ||
80824003 JB |
1671 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1672 | { | |
1673 | struct drm_device *dev = crtc->dev; | |
1674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1675 | struct drm_framebuffer *fb = crtc->fb; | |
1676 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1677 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 JB |
1678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1679 | int plane, i; | |
1680 | u32 fbc_ctl, fbc_ctl2; | |
1681 | ||
bed4a673 | 1682 | if (fb->pitch == dev_priv->cfb_pitch && |
05394f39 | 1683 | obj->fence_reg == dev_priv->cfb_fence && |
bed4a673 CW |
1684 | intel_crtc->plane == dev_priv->cfb_plane && |
1685 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1686 | return; | |
1687 | ||
1688 | i8xx_disable_fbc(dev); | |
1689 | ||
80824003 JB |
1690 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1691 | ||
1692 | if (fb->pitch < dev_priv->cfb_pitch) | |
1693 | dev_priv->cfb_pitch = fb->pitch; | |
1694 | ||
1695 | /* FBC_CTL wants 64B units */ | |
1696 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
05394f39 | 1697 | dev_priv->cfb_fence = obj->fence_reg; |
80824003 JB |
1698 | dev_priv->cfb_plane = intel_crtc->plane; |
1699 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1700 | ||
1701 | /* Clear old tags */ | |
1702 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1703 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1704 | ||
1705 | /* Set it up... */ | |
1706 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
05394f39 | 1707 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1708 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
1709 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1710 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1711 | ||
1712 | /* enable it... */ | |
1713 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1714 | if (IS_I945GM(dev)) |
49677901 | 1715 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1716 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1717 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
05394f39 | 1718 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1719 | fbc_ctl |= dev_priv->cfb_fence; |
1720 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1721 | ||
28c97730 | 1722 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1723 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1724 | } |
1725 | ||
1726 | void i8xx_disable_fbc(struct drm_device *dev) | |
1727 | { | |
1728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729 | u32 fbc_ctl; | |
1730 | ||
1731 | /* Disable compression */ | |
1732 | fbc_ctl = I915_READ(FBC_CONTROL); | |
a5cad620 CW |
1733 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
1734 | return; | |
1735 | ||
80824003 JB |
1736 | fbc_ctl &= ~FBC_CTL_EN; |
1737 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1738 | ||
1739 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1740 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1741 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1742 | return; | |
9517a92f | 1743 | } |
80824003 | 1744 | |
28c97730 | 1745 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1746 | } |
1747 | ||
ee5382ae | 1748 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1749 | { |
80824003 JB |
1750 | struct drm_i915_private *dev_priv = dev->dev_private; |
1751 | ||
1752 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1753 | } | |
1754 | ||
74dff282 JB |
1755 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1756 | { | |
1757 | struct drm_device *dev = crtc->dev; | |
1758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1759 | struct drm_framebuffer *fb = crtc->fb; | |
1760 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1761 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1763 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1764 | unsigned long stall_watermark = 200; |
1765 | u32 dpfc_ctl; | |
1766 | ||
bed4a673 CW |
1767 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1768 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1769 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1770 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 CW |
1771 | dev_priv->cfb_plane == intel_crtc->plane && |
1772 | dev_priv->cfb_y == crtc->y) | |
1773 | return; | |
1774 | ||
1775 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
bed4a673 CW |
1776 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
1777 | } | |
1778 | ||
74dff282 | 1779 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1780 | dev_priv->cfb_fence = obj->fence_reg; |
74dff282 | 1781 | dev_priv->cfb_plane = intel_crtc->plane; |
bed4a673 | 1782 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1783 | |
1784 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
05394f39 | 1785 | if (obj->tiling_mode != I915_TILING_NONE) { |
74dff282 JB |
1786 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
1787 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1788 | } else { | |
1789 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1790 | } | |
1791 | ||
74dff282 JB |
1792 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1793 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1794 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1795 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1796 | ||
1797 | /* enable it... */ | |
1798 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1799 | ||
28c97730 | 1800 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1801 | } |
1802 | ||
1803 | void g4x_disable_fbc(struct drm_device *dev) | |
1804 | { | |
1805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1806 | u32 dpfc_ctl; | |
1807 | ||
1808 | /* Disable compression */ | |
1809 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1810 | if (dpfc_ctl & DPFC_CTL_EN) { |
1811 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1812 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1813 | |
bed4a673 CW |
1814 | DRM_DEBUG_KMS("disabled FBC\n"); |
1815 | } | |
74dff282 JB |
1816 | } |
1817 | ||
ee5382ae | 1818 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1819 | { |
74dff282 JB |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
1821 | ||
1822 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1823 | } | |
1824 | ||
4efe0708 JB |
1825 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1826 | { | |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1828 | u32 blt_ecoskpd; | |
1829 | ||
1830 | /* Make sure blitter notifies FBC of writes */ | |
91355834 | 1831 | __gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1832 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1833 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1834 | GEN6_BLITTER_LOCK_SHIFT; | |
1835 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1836 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1837 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1838 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1839 | GEN6_BLITTER_LOCK_SHIFT); | |
1840 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1841 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
91355834 | 1842 | __gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1843 | } |
1844 | ||
b52eb4dc ZY |
1845 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1846 | { | |
1847 | struct drm_device *dev = crtc->dev; | |
1848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1849 | struct drm_framebuffer *fb = crtc->fb; | |
1850 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1851 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1852 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1853 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1854 | unsigned long stall_watermark = 200; |
1855 | u32 dpfc_ctl; | |
1856 | ||
bed4a673 CW |
1857 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1858 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1859 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1860 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 | 1861 | dev_priv->cfb_plane == intel_crtc->plane && |
05394f39 | 1862 | dev_priv->cfb_offset == obj->gtt_offset && |
bed4a673 CW |
1863 | dev_priv->cfb_y == crtc->y) |
1864 | return; | |
1865 | ||
1866 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
bed4a673 CW |
1867 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
1868 | } | |
1869 | ||
b52eb4dc | 1870 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1871 | dev_priv->cfb_fence = obj->fence_reg; |
b52eb4dc | 1872 | dev_priv->cfb_plane = intel_crtc->plane; |
05394f39 | 1873 | dev_priv->cfb_offset = obj->gtt_offset; |
bed4a673 | 1874 | dev_priv->cfb_y = crtc->y; |
b52eb4dc | 1875 | |
b52eb4dc ZY |
1876 | dpfc_ctl &= DPFC_RESERVED; |
1877 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
05394f39 | 1878 | if (obj->tiling_mode != I915_TILING_NONE) { |
b52eb4dc ZY |
1879 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
1880 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1881 | } else { | |
1882 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1883 | } | |
1884 | ||
b52eb4dc ZY |
1885 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1886 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1887 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1888 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1889 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1890 | /* enable it... */ |
bed4a673 | 1891 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1892 | |
9c04f015 YL |
1893 | if (IS_GEN6(dev)) { |
1894 | I915_WRITE(SNB_DPFC_CTL_SA, | |
1895 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); | |
1896 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
4efe0708 | 1897 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1898 | } |
1899 | ||
b52eb4dc ZY |
1900 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1901 | } | |
1902 | ||
1903 | void ironlake_disable_fbc(struct drm_device *dev) | |
1904 | { | |
1905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1906 | u32 dpfc_ctl; | |
1907 | ||
1908 | /* Disable compression */ | |
1909 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1910 | if (dpfc_ctl & DPFC_CTL_EN) { |
1911 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1912 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1913 | |
bed4a673 CW |
1914 | DRM_DEBUG_KMS("disabled FBC\n"); |
1915 | } | |
b52eb4dc ZY |
1916 | } |
1917 | ||
1918 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1919 | { | |
1920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1921 | ||
1922 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1923 | } | |
1924 | ||
ee5382ae AJ |
1925 | bool intel_fbc_enabled(struct drm_device *dev) |
1926 | { | |
1927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1928 | ||
1929 | if (!dev_priv->display.fbc_enabled) | |
1930 | return false; | |
1931 | ||
1932 | return dev_priv->display.fbc_enabled(dev); | |
1933 | } | |
1934 | ||
1935 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1936 | { | |
1937 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1938 | ||
1939 | if (!dev_priv->display.enable_fbc) | |
1940 | return; | |
1941 | ||
1942 | dev_priv->display.enable_fbc(crtc, interval); | |
1943 | } | |
1944 | ||
1945 | void intel_disable_fbc(struct drm_device *dev) | |
1946 | { | |
1947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1948 | ||
1949 | if (!dev_priv->display.disable_fbc) | |
1950 | return; | |
1951 | ||
1952 | dev_priv->display.disable_fbc(dev); | |
1953 | } | |
1954 | ||
80824003 JB |
1955 | /** |
1956 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1957 | * @dev: the drm_device |
80824003 JB |
1958 | * |
1959 | * Set up the framebuffer compression hardware at mode set time. We | |
1960 | * enable it if possible: | |
1961 | * - plane A only (on pre-965) | |
1962 | * - no pixel mulitply/line duplication | |
1963 | * - no alpha buffer discard | |
1964 | * - no dual wide | |
1965 | * - framebuffer <= 2048 in width, 1536 in height | |
1966 | * | |
1967 | * We can't assume that any compression will take place (worst case), | |
1968 | * so the compressed buffer has to be the same size as the uncompressed | |
1969 | * one. It also must reside (along with the line length buffer) in | |
1970 | * stolen memory. | |
1971 | * | |
1972 | * We need to enable/disable FBC on a global basis. | |
1973 | */ | |
bed4a673 | 1974 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1975 | { |
80824003 | 1976 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1977 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1978 | struct intel_crtc *intel_crtc; | |
1979 | struct drm_framebuffer *fb; | |
80824003 | 1980 | struct intel_framebuffer *intel_fb; |
05394f39 | 1981 | struct drm_i915_gem_object *obj; |
9c928d16 JB |
1982 | |
1983 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1984 | |
1985 | if (!i915_powersave) | |
1986 | return; | |
1987 | ||
ee5382ae | 1988 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1989 | return; |
1990 | ||
80824003 JB |
1991 | /* |
1992 | * If FBC is already on, we just have to verify that we can | |
1993 | * keep it that way... | |
1994 | * Need to disable if: | |
9c928d16 | 1995 | * - more than one pipe is active |
80824003 JB |
1996 | * - changing FBC params (stride, fence, mode) |
1997 | * - new fb is too large to fit in compressed buffer | |
1998 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1999 | */ | |
9c928d16 | 2000 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 2001 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
2002 | if (crtc) { |
2003 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
2004 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
2005 | goto out_disable; | |
2006 | } | |
2007 | crtc = tmp_crtc; | |
2008 | } | |
9c928d16 | 2009 | } |
bed4a673 CW |
2010 | |
2011 | if (!crtc || crtc->fb == NULL) { | |
2012 | DRM_DEBUG_KMS("no output, disabling\n"); | |
2013 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
2014 | goto out_disable; |
2015 | } | |
bed4a673 CW |
2016 | |
2017 | intel_crtc = to_intel_crtc(crtc); | |
2018 | fb = crtc->fb; | |
2019 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 2020 | obj = intel_fb->obj; |
bed4a673 | 2021 | |
05394f39 | 2022 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 2023 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 2024 | "compression\n"); |
b5e50c3f | 2025 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
2026 | goto out_disable; |
2027 | } | |
bed4a673 CW |
2028 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
2029 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 2030 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 2031 | "disabling\n"); |
b5e50c3f | 2032 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
2033 | goto out_disable; |
2034 | } | |
bed4a673 CW |
2035 | if ((crtc->mode.hdisplay > 2048) || |
2036 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 2037 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 2038 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
2039 | goto out_disable; |
2040 | } | |
bed4a673 | 2041 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 2042 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 2043 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
2044 | goto out_disable; |
2045 | } | |
05394f39 | 2046 | if (obj->tiling_mode != I915_TILING_X) { |
28c97730 | 2047 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 2048 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
2049 | goto out_disable; |
2050 | } | |
2051 | ||
c924b934 JW |
2052 | /* If the kernel debugger is active, always disable compression */ |
2053 | if (in_dbg_master()) | |
2054 | goto out_disable; | |
2055 | ||
bed4a673 | 2056 | intel_enable_fbc(crtc, 500); |
80824003 JB |
2057 | return; |
2058 | ||
2059 | out_disable: | |
80824003 | 2060 | /* Multiple disables should be harmless */ |
a939406f CW |
2061 | if (intel_fbc_enabled(dev)) { |
2062 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 2063 | intel_disable_fbc(dev); |
a939406f | 2064 | } |
80824003 JB |
2065 | } |
2066 | ||
127bd2ac | 2067 | int |
48b956c5 | 2068 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2069 | struct drm_i915_gem_object *obj, |
919926ae | 2070 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2071 | { |
ce453d81 | 2072 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2073 | u32 alignment; |
2074 | int ret; | |
2075 | ||
05394f39 | 2076 | switch (obj->tiling_mode) { |
6b95a207 | 2077 | case I915_TILING_NONE: |
534843da CW |
2078 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2079 | alignment = 128 * 1024; | |
a6c45cf0 | 2080 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2081 | alignment = 4 * 1024; |
2082 | else | |
2083 | alignment = 64 * 1024; | |
6b95a207 KH |
2084 | break; |
2085 | case I915_TILING_X: | |
2086 | /* pin() will align the object as required by fence */ | |
2087 | alignment = 0; | |
2088 | break; | |
2089 | case I915_TILING_Y: | |
2090 | /* FIXME: Is this true? */ | |
2091 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
2092 | return -EINVAL; | |
2093 | default: | |
2094 | BUG(); | |
2095 | } | |
2096 | ||
ce453d81 | 2097 | dev_priv->mm.interruptible = false; |
75e9e915 | 2098 | ret = i915_gem_object_pin(obj, alignment, true); |
48b956c5 | 2099 | if (ret) |
ce453d81 | 2100 | goto err_interruptible; |
6b95a207 | 2101 | |
48b956c5 CW |
2102 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
2103 | if (ret) | |
2104 | goto err_unpin; | |
7213342d | 2105 | |
6b95a207 KH |
2106 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2107 | * fence, whereas 965+ only requires a fence if using | |
2108 | * framebuffer compression. For simplicity, we always install | |
2109 | * a fence as the cost is not that onerous. | |
2110 | */ | |
05394f39 | 2111 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2112 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2113 | if (ret) |
2114 | goto err_unpin; | |
6b95a207 KH |
2115 | } |
2116 | ||
ce453d81 | 2117 | dev_priv->mm.interruptible = true; |
6b95a207 | 2118 | return 0; |
48b956c5 CW |
2119 | |
2120 | err_unpin: | |
2121 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2122 | err_interruptible: |
2123 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2124 | return ret; |
6b95a207 KH |
2125 | } |
2126 | ||
81255565 JB |
2127 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2128 | static int | |
2129 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
21c74a8e | 2130 | int x, int y, enum mode_set_atomic state) |
81255565 JB |
2131 | { |
2132 | struct drm_device *dev = crtc->dev; | |
2133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2135 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2136 | struct drm_i915_gem_object *obj; |
81255565 JB |
2137 | int plane = intel_crtc->plane; |
2138 | unsigned long Start, Offset; | |
81255565 | 2139 | u32 dspcntr; |
5eddb70b | 2140 | u32 reg; |
81255565 JB |
2141 | |
2142 | switch (plane) { | |
2143 | case 0: | |
2144 | case 1: | |
2145 | break; | |
2146 | default: | |
2147 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2148 | return -EINVAL; | |
2149 | } | |
2150 | ||
2151 | intel_fb = to_intel_framebuffer(fb); | |
2152 | obj = intel_fb->obj; | |
81255565 | 2153 | |
5eddb70b CW |
2154 | reg = DSPCNTR(plane); |
2155 | dspcntr = I915_READ(reg); | |
81255565 JB |
2156 | /* Mask out pixel format bits in case we change it */ |
2157 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2158 | switch (fb->bits_per_pixel) { | |
2159 | case 8: | |
2160 | dspcntr |= DISPPLANE_8BPP; | |
2161 | break; | |
2162 | case 16: | |
2163 | if (fb->depth == 15) | |
2164 | dspcntr |= DISPPLANE_15_16BPP; | |
2165 | else | |
2166 | dspcntr |= DISPPLANE_16BPP; | |
2167 | break; | |
2168 | case 24: | |
2169 | case 32: | |
2170 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2171 | break; | |
2172 | default: | |
2173 | DRM_ERROR("Unknown color depth\n"); | |
2174 | return -EINVAL; | |
2175 | } | |
a6c45cf0 | 2176 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2177 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2178 | dspcntr |= DISPPLANE_TILED; |
2179 | else | |
2180 | dspcntr &= ~DISPPLANE_TILED; | |
2181 | } | |
2182 | ||
4e6cfefc | 2183 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
2184 | /* must disable */ |
2185 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2186 | ||
5eddb70b | 2187 | I915_WRITE(reg, dspcntr); |
81255565 | 2188 | |
05394f39 | 2189 | Start = obj->gtt_offset; |
81255565 JB |
2190 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
2191 | ||
4e6cfefc CW |
2192 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2193 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 2194 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 2195 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2196 | I915_WRITE(DSPSURF(plane), Start); |
2197 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2198 | I915_WRITE(DSPADDR(plane), Offset); | |
2199 | } else | |
2200 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2201 | POSTING_READ(reg); | |
81255565 | 2202 | |
bed4a673 | 2203 | intel_update_fbc(dev); |
3dec0095 | 2204 | intel_increase_pllclock(crtc); |
81255565 JB |
2205 | |
2206 | return 0; | |
2207 | } | |
2208 | ||
5c3b82e2 | 2209 | static int |
3c4fdcfb KH |
2210 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2211 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2212 | { |
2213 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2214 | struct drm_i915_master_private *master_priv; |
2215 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2216 | int ret; |
79e53945 JB |
2217 | |
2218 | /* no fb bound */ | |
2219 | if (!crtc->fb) { | |
28c97730 | 2220 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
2221 | return 0; |
2222 | } | |
2223 | ||
265db958 | 2224 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2225 | case 0: |
2226 | case 1: | |
2227 | break; | |
2228 | default: | |
5c3b82e2 | 2229 | return -EINVAL; |
79e53945 JB |
2230 | } |
2231 | ||
5c3b82e2 | 2232 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2233 | ret = intel_pin_and_fence_fb_obj(dev, |
2234 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2235 | NULL); |
5c3b82e2 CW |
2236 | if (ret != 0) { |
2237 | mutex_unlock(&dev->struct_mutex); | |
2238 | return ret; | |
2239 | } | |
79e53945 | 2240 | |
265db958 | 2241 | if (old_fb) { |
e6c3a2a6 | 2242 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2243 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2244 | |
e6c3a2a6 | 2245 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2246 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2247 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2248 | |
2249 | /* Big Hammer, we also need to ensure that any pending | |
2250 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2251 | * current scanout is retired before unpinning the old | |
2252 | * framebuffer. | |
01eec727 CW |
2253 | * |
2254 | * This should only fail upon a hung GPU, in which case we | |
2255 | * can safely continue. | |
85345517 | 2256 | */ |
ce453d81 | 2257 | ret = i915_gem_object_flush_gpu(obj); |
01eec727 | 2258 | (void) ret; |
265db958 CW |
2259 | } |
2260 | ||
21c74a8e JW |
2261 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2262 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2263 | if (ret) { |
265db958 | 2264 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2265 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 2266 | return ret; |
79e53945 | 2267 | } |
3c4fdcfb | 2268 | |
b7f1de28 CW |
2269 | if (old_fb) { |
2270 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
265db958 | 2271 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2272 | } |
652c393a | 2273 | |
5c3b82e2 | 2274 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2275 | |
2276 | if (!dev->primary->master) | |
5c3b82e2 | 2277 | return 0; |
79e53945 JB |
2278 | |
2279 | master_priv = dev->primary->master->driver_priv; | |
2280 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2281 | return 0; |
79e53945 | 2282 | |
265db958 | 2283 | if (intel_crtc->pipe) { |
79e53945 JB |
2284 | master_priv->sarea_priv->pipeB_x = x; |
2285 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2286 | } else { |
2287 | master_priv->sarea_priv->pipeA_x = x; | |
2288 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2289 | } |
5c3b82e2 CW |
2290 | |
2291 | return 0; | |
79e53945 JB |
2292 | } |
2293 | ||
5eddb70b | 2294 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2295 | { |
2296 | struct drm_device *dev = crtc->dev; | |
2297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2298 | u32 dpa_ctl; | |
2299 | ||
28c97730 | 2300 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2301 | dpa_ctl = I915_READ(DP_A); |
2302 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2303 | ||
2304 | if (clock < 200000) { | |
2305 | u32 temp; | |
2306 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2307 | /* workaround for 160Mhz: | |
2308 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2309 | 2) program 0x46010 bit 0 = 1 | |
2310 | 3) program 0x46034 bit 24 = 1 | |
2311 | 4) program 0x64000 bit 14 = 1 | |
2312 | */ | |
2313 | temp = I915_READ(0x4600c); | |
2314 | temp &= 0xffff0000; | |
2315 | I915_WRITE(0x4600c, temp | 0x8124); | |
2316 | ||
2317 | temp = I915_READ(0x46010); | |
2318 | I915_WRITE(0x46010, temp | 1); | |
2319 | ||
2320 | temp = I915_READ(0x46034); | |
2321 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2322 | } else { | |
2323 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2324 | } | |
2325 | I915_WRITE(DP_A, dpa_ctl); | |
2326 | ||
5eddb70b | 2327 | POSTING_READ(DP_A); |
32f9d658 ZW |
2328 | udelay(500); |
2329 | } | |
2330 | ||
5e84e1a4 ZW |
2331 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2332 | { | |
2333 | struct drm_device *dev = crtc->dev; | |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2336 | int pipe = intel_crtc->pipe; | |
2337 | u32 reg, temp; | |
2338 | ||
2339 | /* enable normal train */ | |
2340 | reg = FDI_TX_CTL(pipe); | |
2341 | temp = I915_READ(reg); | |
2342 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2343 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
2344 | I915_WRITE(reg, temp); | |
2345 | ||
2346 | reg = FDI_RX_CTL(pipe); | |
2347 | temp = I915_READ(reg); | |
2348 | if (HAS_PCH_CPT(dev)) { | |
2349 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2350 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2351 | } else { | |
2352 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2353 | temp |= FDI_LINK_TRAIN_NONE; | |
2354 | } | |
2355 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2356 | ||
2357 | /* wait one idle pattern time */ | |
2358 | POSTING_READ(reg); | |
2359 | udelay(1000); | |
2360 | } | |
2361 | ||
8db9d77b ZW |
2362 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2363 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2364 | { | |
2365 | struct drm_device *dev = crtc->dev; | |
2366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2368 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2369 | int plane = intel_crtc->plane; |
5eddb70b | 2370 | u32 reg, temp, tries; |
8db9d77b | 2371 | |
0fc932b8 JB |
2372 | /* FDI needs bits from pipe & plane first */ |
2373 | assert_pipe_enabled(dev_priv, pipe); | |
2374 | assert_plane_enabled(dev_priv, plane); | |
2375 | ||
e1a44743 AJ |
2376 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2377 | for train result */ | |
5eddb70b CW |
2378 | reg = FDI_RX_IMR(pipe); |
2379 | temp = I915_READ(reg); | |
e1a44743 AJ |
2380 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2381 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2382 | I915_WRITE(reg, temp); |
2383 | I915_READ(reg); | |
e1a44743 AJ |
2384 | udelay(150); |
2385 | ||
8db9d77b | 2386 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2387 | reg = FDI_TX_CTL(pipe); |
2388 | temp = I915_READ(reg); | |
77ffb597 AJ |
2389 | temp &= ~(7 << 19); |
2390 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2391 | temp &= ~FDI_LINK_TRAIN_NONE; |
2392 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2393 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2394 | |
5eddb70b CW |
2395 | reg = FDI_RX_CTL(pipe); |
2396 | temp = I915_READ(reg); | |
8db9d77b ZW |
2397 | temp &= ~FDI_LINK_TRAIN_NONE; |
2398 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2399 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2400 | ||
2401 | POSTING_READ(reg); | |
8db9d77b ZW |
2402 | udelay(150); |
2403 | ||
5b2adf89 | 2404 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2405 | if (HAS_PCH_IBX(dev)) { |
2406 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2407 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2408 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2409 | } | |
5b2adf89 | 2410 | |
5eddb70b | 2411 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2412 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2413 | temp = I915_READ(reg); |
8db9d77b ZW |
2414 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2415 | ||
2416 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2417 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2418 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2419 | break; |
2420 | } | |
8db9d77b | 2421 | } |
e1a44743 | 2422 | if (tries == 5) |
5eddb70b | 2423 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2424 | |
2425 | /* Train 2 */ | |
5eddb70b CW |
2426 | reg = FDI_TX_CTL(pipe); |
2427 | temp = I915_READ(reg); | |
8db9d77b ZW |
2428 | temp &= ~FDI_LINK_TRAIN_NONE; |
2429 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2430 | I915_WRITE(reg, temp); |
8db9d77b | 2431 | |
5eddb70b CW |
2432 | reg = FDI_RX_CTL(pipe); |
2433 | temp = I915_READ(reg); | |
8db9d77b ZW |
2434 | temp &= ~FDI_LINK_TRAIN_NONE; |
2435 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2436 | I915_WRITE(reg, temp); |
8db9d77b | 2437 | |
5eddb70b CW |
2438 | POSTING_READ(reg); |
2439 | udelay(150); | |
8db9d77b | 2440 | |
5eddb70b | 2441 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2442 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2443 | temp = I915_READ(reg); |
8db9d77b ZW |
2444 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2445 | ||
2446 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2447 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2448 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2449 | break; | |
2450 | } | |
8db9d77b | 2451 | } |
e1a44743 | 2452 | if (tries == 5) |
5eddb70b | 2453 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2454 | |
2455 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2456 | |
8db9d77b ZW |
2457 | } |
2458 | ||
311bd68e | 2459 | static const int snb_b_fdi_train_param [] = { |
8db9d77b ZW |
2460 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2461 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2462 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2463 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2464 | }; | |
2465 | ||
2466 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2467 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2468 | { | |
2469 | struct drm_device *dev = crtc->dev; | |
2470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2472 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2473 | u32 reg, temp, i; |
8db9d77b | 2474 | |
e1a44743 AJ |
2475 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2476 | for train result */ | |
5eddb70b CW |
2477 | reg = FDI_RX_IMR(pipe); |
2478 | temp = I915_READ(reg); | |
e1a44743 AJ |
2479 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2480 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2481 | I915_WRITE(reg, temp); |
2482 | ||
2483 | POSTING_READ(reg); | |
e1a44743 AJ |
2484 | udelay(150); |
2485 | ||
8db9d77b | 2486 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2487 | reg = FDI_TX_CTL(pipe); |
2488 | temp = I915_READ(reg); | |
77ffb597 AJ |
2489 | temp &= ~(7 << 19); |
2490 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2491 | temp &= ~FDI_LINK_TRAIN_NONE; |
2492 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2493 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2494 | /* SNB-B */ | |
2495 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2496 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2497 | |
5eddb70b CW |
2498 | reg = FDI_RX_CTL(pipe); |
2499 | temp = I915_READ(reg); | |
8db9d77b ZW |
2500 | if (HAS_PCH_CPT(dev)) { |
2501 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2502 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2503 | } else { | |
2504 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2505 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2506 | } | |
5eddb70b CW |
2507 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2508 | ||
2509 | POSTING_READ(reg); | |
8db9d77b ZW |
2510 | udelay(150); |
2511 | ||
8db9d77b | 2512 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
2513 | reg = FDI_TX_CTL(pipe); |
2514 | temp = I915_READ(reg); | |
8db9d77b ZW |
2515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2516 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2517 | I915_WRITE(reg, temp); |
2518 | ||
2519 | POSTING_READ(reg); | |
8db9d77b ZW |
2520 | udelay(500); |
2521 | ||
5eddb70b CW |
2522 | reg = FDI_RX_IIR(pipe); |
2523 | temp = I915_READ(reg); | |
8db9d77b ZW |
2524 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2525 | ||
2526 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2527 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2528 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2529 | break; | |
2530 | } | |
2531 | } | |
2532 | if (i == 4) | |
5eddb70b | 2533 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2534 | |
2535 | /* Train 2 */ | |
5eddb70b CW |
2536 | reg = FDI_TX_CTL(pipe); |
2537 | temp = I915_READ(reg); | |
8db9d77b ZW |
2538 | temp &= ~FDI_LINK_TRAIN_NONE; |
2539 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2540 | if (IS_GEN6(dev)) { | |
2541 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2542 | /* SNB-B */ | |
2543 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2544 | } | |
5eddb70b | 2545 | I915_WRITE(reg, temp); |
8db9d77b | 2546 | |
5eddb70b CW |
2547 | reg = FDI_RX_CTL(pipe); |
2548 | temp = I915_READ(reg); | |
8db9d77b ZW |
2549 | if (HAS_PCH_CPT(dev)) { |
2550 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2551 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2552 | } else { | |
2553 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2554 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2555 | } | |
5eddb70b CW |
2556 | I915_WRITE(reg, temp); |
2557 | ||
2558 | POSTING_READ(reg); | |
8db9d77b ZW |
2559 | udelay(150); |
2560 | ||
2561 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
2562 | reg = FDI_TX_CTL(pipe); |
2563 | temp = I915_READ(reg); | |
8db9d77b ZW |
2564 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2565 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2566 | I915_WRITE(reg, temp); |
2567 | ||
2568 | POSTING_READ(reg); | |
8db9d77b ZW |
2569 | udelay(500); |
2570 | ||
5eddb70b CW |
2571 | reg = FDI_RX_IIR(pipe); |
2572 | temp = I915_READ(reg); | |
8db9d77b ZW |
2573 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2574 | ||
2575 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2576 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2577 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2578 | break; | |
2579 | } | |
2580 | } | |
2581 | if (i == 4) | |
5eddb70b | 2582 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2583 | |
2584 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2585 | } | |
2586 | ||
0e23b99d | 2587 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
2588 | { |
2589 | struct drm_device *dev = crtc->dev; | |
2590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2592 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2593 | u32 reg, temp; |
79e53945 | 2594 | |
c64e311e | 2595 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2596 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2597 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2598 | |
c98e9dcf | 2599 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2600 | reg = FDI_RX_CTL(pipe); |
2601 | temp = I915_READ(reg); | |
2602 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2603 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2604 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2605 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2606 | ||
2607 | POSTING_READ(reg); | |
c98e9dcf JB |
2608 | udelay(200); |
2609 | ||
2610 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2611 | temp = I915_READ(reg); |
2612 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2613 | ||
2614 | POSTING_READ(reg); | |
c98e9dcf JB |
2615 | udelay(200); |
2616 | ||
2617 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2618 | reg = FDI_TX_CTL(pipe); |
2619 | temp = I915_READ(reg); | |
c98e9dcf | 2620 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2621 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2622 | ||
2623 | POSTING_READ(reg); | |
c98e9dcf | 2624 | udelay(100); |
6be4a607 | 2625 | } |
0e23b99d JB |
2626 | } |
2627 | ||
0fc932b8 JB |
2628 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2629 | { | |
2630 | struct drm_device *dev = crtc->dev; | |
2631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2633 | int pipe = intel_crtc->pipe; | |
2634 | u32 reg, temp; | |
2635 | ||
2636 | /* disable CPU FDI tx and PCH FDI rx */ | |
2637 | reg = FDI_TX_CTL(pipe); | |
2638 | temp = I915_READ(reg); | |
2639 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2640 | POSTING_READ(reg); | |
2641 | ||
2642 | reg = FDI_RX_CTL(pipe); | |
2643 | temp = I915_READ(reg); | |
2644 | temp &= ~(0x7 << 16); | |
2645 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2646 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2647 | ||
2648 | POSTING_READ(reg); | |
2649 | udelay(100); | |
2650 | ||
2651 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2652 | if (HAS_PCH_IBX(dev)) { |
2653 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2654 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2655 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 JB |
2656 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
2657 | } | |
0fc932b8 JB |
2658 | |
2659 | /* still set train pattern 1 */ | |
2660 | reg = FDI_TX_CTL(pipe); | |
2661 | temp = I915_READ(reg); | |
2662 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2663 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2664 | I915_WRITE(reg, temp); | |
2665 | ||
2666 | reg = FDI_RX_CTL(pipe); | |
2667 | temp = I915_READ(reg); | |
2668 | if (HAS_PCH_CPT(dev)) { | |
2669 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2670 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2671 | } else { | |
2672 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2673 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2674 | } | |
2675 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2676 | temp &= ~(0x07 << 16); | |
2677 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2678 | I915_WRITE(reg, temp); | |
2679 | ||
2680 | POSTING_READ(reg); | |
2681 | udelay(100); | |
2682 | } | |
2683 | ||
6b383a7f CW |
2684 | /* |
2685 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2686 | * to avoid hanging the ring, which we assume we are waiting on. | |
2687 | */ | |
2688 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2689 | { | |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2691 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2692 | u32 tmp; |
2693 | ||
2694 | if (IS_GEN2(dev)) | |
2695 | /* Can't break the hang on i8xx */ | |
2696 | return; | |
2697 | ||
1ec14ad3 | 2698 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2699 | tmp = I915_READ_CTL(ring); |
2700 | if (tmp & RING_WAIT) | |
2701 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2702 | } |
2703 | ||
e6c3a2a6 CW |
2704 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2705 | { | |
05394f39 | 2706 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2707 | struct drm_i915_private *dev_priv; |
2708 | ||
2709 | if (crtc->fb == NULL) | |
2710 | return; | |
2711 | ||
05394f39 | 2712 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2713 | dev_priv = crtc->dev->dev_private; |
2714 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2715 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2716 | } |
2717 | ||
040484af JB |
2718 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2719 | { | |
2720 | struct drm_device *dev = crtc->dev; | |
2721 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2722 | struct intel_encoder *encoder; | |
2723 | ||
2724 | /* | |
2725 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2726 | * must be driven by its own crtc; no sharing is possible. | |
2727 | */ | |
2728 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2729 | if (encoder->base.crtc != crtc) | |
2730 | continue; | |
2731 | ||
2732 | switch (encoder->type) { | |
2733 | case INTEL_OUTPUT_EDP: | |
2734 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2735 | return false; | |
2736 | continue; | |
2737 | } | |
2738 | } | |
2739 | ||
2740 | return true; | |
2741 | } | |
2742 | ||
f67a559d JB |
2743 | /* |
2744 | * Enable PCH resources required for PCH ports: | |
2745 | * - PCH PLLs | |
2746 | * - FDI training & RX/TX | |
2747 | * - update transcoder timings | |
2748 | * - DP transcoding bits | |
2749 | * - transcoder | |
2750 | */ | |
2751 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2752 | { |
2753 | struct drm_device *dev = crtc->dev; | |
2754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2756 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2757 | u32 reg, temp; |
2c07245f | 2758 | |
c98e9dcf JB |
2759 | /* For PCH output, training FDI link */ |
2760 | if (IS_GEN6(dev)) | |
2761 | gen6_fdi_link_train(crtc); | |
2762 | else | |
2763 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2764 | |
92f2584a | 2765 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2766 | |
c98e9dcf JB |
2767 | if (HAS_PCH_CPT(dev)) { |
2768 | /* Be sure PCH DPLL SEL is set */ | |
2769 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2770 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2771 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2772 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2773 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2774 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2775 | } |
5eddb70b | 2776 | |
d9b6cb56 JB |
2777 | /* set transcoder timing, panel must allow it */ |
2778 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2779 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2780 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2781 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2782 | |
5eddb70b CW |
2783 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2784 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2785 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2786 | |
5e84e1a4 ZW |
2787 | intel_fdi_normal_train(crtc); |
2788 | ||
c98e9dcf JB |
2789 | /* For PCH DP, enable TRANS_DP_CTL */ |
2790 | if (HAS_PCH_CPT(dev) && | |
2791 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2792 | reg = TRANS_DP_CTL(pipe); |
2793 | temp = I915_READ(reg); | |
2794 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2795 | TRANS_DP_SYNC_MASK | |
2796 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2797 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2798 | TRANS_DP_ENH_FRAMING); | |
220cad3c | 2799 | temp |= TRANS_DP_8BPC; |
c98e9dcf JB |
2800 | |
2801 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2802 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2803 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2804 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2805 | |
2806 | switch (intel_trans_dp_port_sel(crtc)) { | |
2807 | case PCH_DP_B: | |
5eddb70b | 2808 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2809 | break; |
2810 | case PCH_DP_C: | |
5eddb70b | 2811 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2812 | break; |
2813 | case PCH_DP_D: | |
5eddb70b | 2814 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2815 | break; |
2816 | default: | |
2817 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2818 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2819 | break; |
32f9d658 | 2820 | } |
2c07245f | 2821 | |
5eddb70b | 2822 | I915_WRITE(reg, temp); |
6be4a607 | 2823 | } |
b52eb4dc | 2824 | |
040484af | 2825 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
2826 | } |
2827 | ||
2828 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | |
2829 | { | |
2830 | struct drm_device *dev = crtc->dev; | |
2831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2833 | int pipe = intel_crtc->pipe; | |
2834 | int plane = intel_crtc->plane; | |
2835 | u32 temp; | |
2836 | bool is_pch_port; | |
2837 | ||
2838 | if (intel_crtc->active) | |
2839 | return; | |
2840 | ||
2841 | intel_crtc->active = true; | |
2842 | intel_update_watermarks(dev); | |
2843 | ||
2844 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
2845 | temp = I915_READ(PCH_LVDS); | |
2846 | if ((temp & LVDS_PORT_EN) == 0) | |
2847 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
2848 | } | |
2849 | ||
2850 | is_pch_port = intel_crtc_driving_pch(crtc); | |
2851 | ||
2852 | if (is_pch_port) | |
2853 | ironlake_fdi_enable(crtc); | |
2854 | else | |
2855 | ironlake_fdi_disable(crtc); | |
2856 | ||
2857 | /* Enable panel fitting for LVDS */ | |
2858 | if (dev_priv->pch_pf_size && | |
2859 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
2860 | /* Force use of hard-coded filter coefficients | |
2861 | * as some pre-programmed values are broken, | |
2862 | * e.g. x201. | |
2863 | */ | |
9db4a9c7 JB |
2864 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
2865 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
2866 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
2867 | } |
2868 | ||
2869 | intel_enable_pipe(dev_priv, pipe, is_pch_port); | |
2870 | intel_enable_plane(dev_priv, plane, pipe); | |
2871 | ||
2872 | if (is_pch_port) | |
2873 | ironlake_pch_enable(crtc); | |
c98e9dcf | 2874 | |
6be4a607 | 2875 | intel_crtc_load_lut(crtc); |
bed4a673 | 2876 | intel_update_fbc(dev); |
6b383a7f | 2877 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2878 | } |
2879 | ||
2880 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2881 | { | |
2882 | struct drm_device *dev = crtc->dev; | |
2883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2885 | int pipe = intel_crtc->pipe; | |
2886 | int plane = intel_crtc->plane; | |
5eddb70b | 2887 | u32 reg, temp; |
b52eb4dc | 2888 | |
f7abfe8b CW |
2889 | if (!intel_crtc->active) |
2890 | return; | |
2891 | ||
e6c3a2a6 | 2892 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2893 | drm_vblank_off(dev, pipe); |
6b383a7f | 2894 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2895 | |
b24e7179 | 2896 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 2897 | |
6be4a607 JB |
2898 | if (dev_priv->cfb_plane == plane && |
2899 | dev_priv->display.disable_fbc) | |
2900 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2901 | |
b24e7179 | 2902 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 2903 | |
6be4a607 | 2904 | /* Disable PF */ |
9db4a9c7 JB |
2905 | I915_WRITE(PF_CTL(pipe), 0); |
2906 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 2907 | |
0fc932b8 | 2908 | ironlake_fdi_disable(crtc); |
2c07245f | 2909 | |
47a05eca JB |
2910 | /* This is a horrible layering violation; we should be doing this in |
2911 | * the connector/encoder ->prepare instead, but we don't always have | |
2912 | * enough information there about the config to know whether it will | |
2913 | * actually be necessary or just cause undesired flicker. | |
2914 | */ | |
2915 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 2916 | |
040484af | 2917 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 2918 | |
6be4a607 JB |
2919 | if (HAS_PCH_CPT(dev)) { |
2920 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2921 | reg = TRANS_DP_CTL(pipe); |
2922 | temp = I915_READ(reg); | |
2923 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 2924 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 2925 | I915_WRITE(reg, temp); |
6be4a607 JB |
2926 | |
2927 | /* disable DPLL_SEL */ | |
2928 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
2929 | switch (pipe) { |
2930 | case 0: | |
2931 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); | |
2932 | break; | |
2933 | case 1: | |
6be4a607 | 2934 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
2935 | break; |
2936 | case 2: | |
2937 | /* FIXME: manage transcoder PLLs? */ | |
2938 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); | |
2939 | break; | |
2940 | default: | |
2941 | BUG(); /* wtf */ | |
2942 | } | |
6be4a607 | 2943 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 2944 | } |
e3421a18 | 2945 | |
6be4a607 | 2946 | /* disable PCH DPLL */ |
92f2584a | 2947 | intel_disable_pch_pll(dev_priv, pipe); |
8db9d77b | 2948 | |
6be4a607 | 2949 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2950 | reg = FDI_RX_CTL(pipe); |
2951 | temp = I915_READ(reg); | |
2952 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2953 | |
6be4a607 | 2954 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2955 | reg = FDI_TX_CTL(pipe); |
2956 | temp = I915_READ(reg); | |
2957 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2958 | ||
2959 | POSTING_READ(reg); | |
6be4a607 | 2960 | udelay(100); |
8db9d77b | 2961 | |
5eddb70b CW |
2962 | reg = FDI_RX_CTL(pipe); |
2963 | temp = I915_READ(reg); | |
2964 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2965 | |
6be4a607 | 2966 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2967 | POSTING_READ(reg); |
6be4a607 | 2968 | udelay(100); |
6b383a7f | 2969 | |
f7abfe8b | 2970 | intel_crtc->active = false; |
6b383a7f CW |
2971 | intel_update_watermarks(dev); |
2972 | intel_update_fbc(dev); | |
2973 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2974 | } |
1b3c7a47 | 2975 | |
6be4a607 JB |
2976 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2977 | { | |
2978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2979 | int pipe = intel_crtc->pipe; | |
2980 | int plane = intel_crtc->plane; | |
8db9d77b | 2981 | |
6be4a607 JB |
2982 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2983 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2984 | */ | |
2985 | switch (mode) { | |
2986 | case DRM_MODE_DPMS_ON: | |
2987 | case DRM_MODE_DPMS_STANDBY: | |
2988 | case DRM_MODE_DPMS_SUSPEND: | |
2989 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2990 | ironlake_crtc_enable(crtc); | |
2991 | break; | |
1b3c7a47 | 2992 | |
6be4a607 JB |
2993 | case DRM_MODE_DPMS_OFF: |
2994 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2995 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2996 | break; |
2997 | } | |
2998 | } | |
2999 | ||
02e792fb DV |
3000 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3001 | { | |
02e792fb | 3002 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3003 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3004 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3005 | |
23f09ce3 | 3006 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3007 | dev_priv->mm.interruptible = false; |
3008 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3009 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3010 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3011 | } |
02e792fb | 3012 | |
5dcdbcb0 CW |
3013 | /* Let userspace switch the overlay on again. In most cases userspace |
3014 | * has to recompute where to put it anyway. | |
3015 | */ | |
02e792fb DV |
3016 | } |
3017 | ||
0b8765c6 | 3018 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3019 | { |
3020 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3021 | struct drm_i915_private *dev_priv = dev->dev_private; |
3022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3023 | int pipe = intel_crtc->pipe; | |
80824003 | 3024 | int plane = intel_crtc->plane; |
79e53945 | 3025 | |
f7abfe8b CW |
3026 | if (intel_crtc->active) |
3027 | return; | |
3028 | ||
3029 | intel_crtc->active = true; | |
6b383a7f CW |
3030 | intel_update_watermarks(dev); |
3031 | ||
63d7bbe9 | 3032 | intel_enable_pll(dev_priv, pipe); |
040484af | 3033 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3034 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3035 | |
0b8765c6 | 3036 | intel_crtc_load_lut(crtc); |
bed4a673 | 3037 | intel_update_fbc(dev); |
79e53945 | 3038 | |
0b8765c6 JB |
3039 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3040 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3041 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3042 | } |
79e53945 | 3043 | |
0b8765c6 JB |
3044 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3045 | { | |
3046 | struct drm_device *dev = crtc->dev; | |
3047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3049 | int pipe = intel_crtc->pipe; | |
3050 | int plane = intel_crtc->plane; | |
b690e96c | 3051 | |
f7abfe8b CW |
3052 | if (!intel_crtc->active) |
3053 | return; | |
3054 | ||
0b8765c6 | 3055 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3056 | intel_crtc_wait_for_pending_flips(crtc); |
3057 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3058 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3059 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
3060 | |
3061 | if (dev_priv->cfb_plane == plane && | |
3062 | dev_priv->display.disable_fbc) | |
3063 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 3064 | |
b24e7179 | 3065 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3066 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3067 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3068 | |
f7abfe8b | 3069 | intel_crtc->active = false; |
6b383a7f CW |
3070 | intel_update_fbc(dev); |
3071 | intel_update_watermarks(dev); | |
3072 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3073 | } |
3074 | ||
3075 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3076 | { | |
3077 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3078 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3079 | */ | |
3080 | switch (mode) { | |
3081 | case DRM_MODE_DPMS_ON: | |
3082 | case DRM_MODE_DPMS_STANDBY: | |
3083 | case DRM_MODE_DPMS_SUSPEND: | |
3084 | i9xx_crtc_enable(crtc); | |
3085 | break; | |
3086 | case DRM_MODE_DPMS_OFF: | |
3087 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3088 | break; |
3089 | } | |
2c07245f ZW |
3090 | } |
3091 | ||
3092 | /** | |
3093 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3094 | */ |
3095 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3096 | { | |
3097 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3098 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3099 | struct drm_i915_master_private *master_priv; |
3100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3101 | int pipe = intel_crtc->pipe; | |
3102 | bool enabled; | |
3103 | ||
032d2a0d CW |
3104 | if (intel_crtc->dpms_mode == mode) |
3105 | return; | |
3106 | ||
65655d4a | 3107 | intel_crtc->dpms_mode = mode; |
debcaddc | 3108 | |
e70236a8 | 3109 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3110 | |
3111 | if (!dev->primary->master) | |
3112 | return; | |
3113 | ||
3114 | master_priv = dev->primary->master->driver_priv; | |
3115 | if (!master_priv->sarea_priv) | |
3116 | return; | |
3117 | ||
3118 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3119 | ||
3120 | switch (pipe) { | |
3121 | case 0: | |
3122 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3123 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3124 | break; | |
3125 | case 1: | |
3126 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3127 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3128 | break; | |
3129 | default: | |
9db4a9c7 | 3130 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3131 | break; |
3132 | } | |
79e53945 JB |
3133 | } |
3134 | ||
cdd59983 CW |
3135 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3136 | { | |
3137 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3138 | struct drm_device *dev = crtc->dev; | |
3139 | ||
3140 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
3141 | ||
3142 | if (crtc->fb) { | |
3143 | mutex_lock(&dev->struct_mutex); | |
3144 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
3145 | mutex_unlock(&dev->struct_mutex); | |
3146 | } | |
3147 | } | |
3148 | ||
7e7d76c3 JB |
3149 | /* Prepare for a mode set. |
3150 | * | |
3151 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3152 | * will be enabled, which disabled (in short, how the config will changes) | |
3153 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3154 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3155 | * panel fitting is in the proper state, etc. | |
3156 | */ | |
3157 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3158 | { |
7e7d76c3 | 3159 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3160 | } |
3161 | ||
7e7d76c3 | 3162 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3163 | { |
7e7d76c3 | 3164 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3165 | } |
3166 | ||
3167 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3168 | { | |
7e7d76c3 | 3169 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3170 | } |
3171 | ||
3172 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3173 | { | |
7e7d76c3 | 3174 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3175 | } |
3176 | ||
3177 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
3178 | { | |
3179 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3180 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3181 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3182 | } | |
3183 | ||
3184 | void intel_encoder_commit (struct drm_encoder *encoder) | |
3185 | { | |
3186 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3187 | /* lvds has its own version of commit see intel_lvds_commit */ | |
3188 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
3189 | } | |
3190 | ||
ea5b213a CW |
3191 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3192 | { | |
4ef69c7a | 3193 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3194 | |
ea5b213a CW |
3195 | drm_encoder_cleanup(encoder); |
3196 | kfree(intel_encoder); | |
3197 | } | |
3198 | ||
79e53945 JB |
3199 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3200 | struct drm_display_mode *mode, | |
3201 | struct drm_display_mode *adjusted_mode) | |
3202 | { | |
2c07245f | 3203 | struct drm_device *dev = crtc->dev; |
89749350 | 3204 | |
bad720ff | 3205 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3206 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3207 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3208 | return false; | |
2c07245f | 3209 | } |
89749350 CW |
3210 | |
3211 | /* XXX some encoders set the crtcinfo, others don't. | |
3212 | * Obviously we need some form of conflict resolution here... | |
3213 | */ | |
3214 | if (adjusted_mode->crtc_htotal == 0) | |
3215 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
3216 | ||
79e53945 JB |
3217 | return true; |
3218 | } | |
3219 | ||
e70236a8 JB |
3220 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3221 | { | |
3222 | return 400000; | |
3223 | } | |
79e53945 | 3224 | |
e70236a8 | 3225 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3226 | { |
e70236a8 JB |
3227 | return 333000; |
3228 | } | |
79e53945 | 3229 | |
e70236a8 JB |
3230 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3231 | { | |
3232 | return 200000; | |
3233 | } | |
79e53945 | 3234 | |
e70236a8 JB |
3235 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3236 | { | |
3237 | u16 gcfgc = 0; | |
79e53945 | 3238 | |
e70236a8 JB |
3239 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3240 | ||
3241 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3242 | return 133000; | |
3243 | else { | |
3244 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3245 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3246 | return 333000; | |
3247 | default: | |
3248 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3249 | return 190000; | |
79e53945 | 3250 | } |
e70236a8 JB |
3251 | } |
3252 | } | |
3253 | ||
3254 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3255 | { | |
3256 | return 266000; | |
3257 | } | |
3258 | ||
3259 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3260 | { | |
3261 | u16 hpllcc = 0; | |
3262 | /* Assume that the hardware is in the high speed state. This | |
3263 | * should be the default. | |
3264 | */ | |
3265 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3266 | case GC_CLOCK_133_200: | |
3267 | case GC_CLOCK_100_200: | |
3268 | return 200000; | |
3269 | case GC_CLOCK_166_250: | |
3270 | return 250000; | |
3271 | case GC_CLOCK_100_133: | |
79e53945 | 3272 | return 133000; |
e70236a8 | 3273 | } |
79e53945 | 3274 | |
e70236a8 JB |
3275 | /* Shouldn't happen */ |
3276 | return 0; | |
3277 | } | |
79e53945 | 3278 | |
e70236a8 JB |
3279 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3280 | { | |
3281 | return 133000; | |
79e53945 JB |
3282 | } |
3283 | ||
2c07245f ZW |
3284 | struct fdi_m_n { |
3285 | u32 tu; | |
3286 | u32 gmch_m; | |
3287 | u32 gmch_n; | |
3288 | u32 link_m; | |
3289 | u32 link_n; | |
3290 | }; | |
3291 | ||
3292 | static void | |
3293 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3294 | { | |
3295 | while (*num > 0xffffff || *den > 0xffffff) { | |
3296 | *num >>= 1; | |
3297 | *den >>= 1; | |
3298 | } | |
3299 | } | |
3300 | ||
2c07245f | 3301 | static void |
f2b115e6 AJ |
3302 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3303 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3304 | { |
2c07245f ZW |
3305 | m_n->tu = 64; /* default size */ |
3306 | ||
22ed1113 CW |
3307 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3308 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3309 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3310 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3311 | ||
22ed1113 CW |
3312 | m_n->link_m = pixel_clock; |
3313 | m_n->link_n = link_clock; | |
2c07245f ZW |
3314 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3315 | } | |
3316 | ||
3317 | ||
7662c8bd SL |
3318 | struct intel_watermark_params { |
3319 | unsigned long fifo_size; | |
3320 | unsigned long max_wm; | |
3321 | unsigned long default_wm; | |
3322 | unsigned long guard_size; | |
3323 | unsigned long cacheline_size; | |
3324 | }; | |
3325 | ||
f2b115e6 | 3326 | /* Pineview has different values for various configs */ |
d210246a | 3327 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3328 | PINEVIEW_DISPLAY_FIFO, |
3329 | PINEVIEW_MAX_WM, | |
3330 | PINEVIEW_DFT_WM, | |
3331 | PINEVIEW_GUARD_WM, | |
3332 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3333 | }; |
d210246a | 3334 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3335 | PINEVIEW_DISPLAY_FIFO, |
3336 | PINEVIEW_MAX_WM, | |
3337 | PINEVIEW_DFT_HPLLOFF_WM, | |
3338 | PINEVIEW_GUARD_WM, | |
3339 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3340 | }; |
d210246a | 3341 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3342 | PINEVIEW_CURSOR_FIFO, |
3343 | PINEVIEW_CURSOR_MAX_WM, | |
3344 | PINEVIEW_CURSOR_DFT_WM, | |
3345 | PINEVIEW_CURSOR_GUARD_WM, | |
3346 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3347 | }; |
d210246a | 3348 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3349 | PINEVIEW_CURSOR_FIFO, |
3350 | PINEVIEW_CURSOR_MAX_WM, | |
3351 | PINEVIEW_CURSOR_DFT_WM, | |
3352 | PINEVIEW_CURSOR_GUARD_WM, | |
3353 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3354 | }; |
d210246a | 3355 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3356 | G4X_FIFO_SIZE, |
3357 | G4X_MAX_WM, | |
3358 | G4X_MAX_WM, | |
3359 | 2, | |
3360 | G4X_FIFO_LINE_SIZE, | |
3361 | }; | |
d210246a | 3362 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3363 | I965_CURSOR_FIFO, |
3364 | I965_CURSOR_MAX_WM, | |
3365 | I965_CURSOR_DFT_WM, | |
3366 | 2, | |
3367 | G4X_FIFO_LINE_SIZE, | |
3368 | }; | |
d210246a | 3369 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3370 | I965_CURSOR_FIFO, |
3371 | I965_CURSOR_MAX_WM, | |
3372 | I965_CURSOR_DFT_WM, | |
3373 | 2, | |
3374 | I915_FIFO_LINE_SIZE, | |
3375 | }; | |
d210246a | 3376 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3377 | I945_FIFO_SIZE, |
7662c8bd SL |
3378 | I915_MAX_WM, |
3379 | 1, | |
dff33cfc JB |
3380 | 2, |
3381 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3382 | }; |
d210246a | 3383 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3384 | I915_FIFO_SIZE, |
7662c8bd SL |
3385 | I915_MAX_WM, |
3386 | 1, | |
dff33cfc | 3387 | 2, |
7662c8bd SL |
3388 | I915_FIFO_LINE_SIZE |
3389 | }; | |
d210246a | 3390 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3391 | I855GM_FIFO_SIZE, |
3392 | I915_MAX_WM, | |
3393 | 1, | |
dff33cfc | 3394 | 2, |
7662c8bd SL |
3395 | I830_FIFO_LINE_SIZE |
3396 | }; | |
d210246a | 3397 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3398 | I830_FIFO_SIZE, |
3399 | I915_MAX_WM, | |
3400 | 1, | |
dff33cfc | 3401 | 2, |
7662c8bd SL |
3402 | I830_FIFO_LINE_SIZE |
3403 | }; | |
3404 | ||
d210246a | 3405 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3406 | ILK_DISPLAY_FIFO, |
3407 | ILK_DISPLAY_MAXWM, | |
3408 | ILK_DISPLAY_DFTWM, | |
3409 | 2, | |
3410 | ILK_FIFO_LINE_SIZE | |
3411 | }; | |
d210246a | 3412 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3413 | ILK_CURSOR_FIFO, |
3414 | ILK_CURSOR_MAXWM, | |
3415 | ILK_CURSOR_DFTWM, | |
3416 | 2, | |
3417 | ILK_FIFO_LINE_SIZE | |
3418 | }; | |
d210246a | 3419 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3420 | ILK_DISPLAY_SR_FIFO, |
3421 | ILK_DISPLAY_MAX_SRWM, | |
3422 | ILK_DISPLAY_DFT_SRWM, | |
3423 | 2, | |
3424 | ILK_FIFO_LINE_SIZE | |
3425 | }; | |
d210246a | 3426 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3427 | ILK_CURSOR_SR_FIFO, |
3428 | ILK_CURSOR_MAX_SRWM, | |
3429 | ILK_CURSOR_DFT_SRWM, | |
3430 | 2, | |
3431 | ILK_FIFO_LINE_SIZE | |
3432 | }; | |
3433 | ||
d210246a | 3434 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3435 | SNB_DISPLAY_FIFO, |
3436 | SNB_DISPLAY_MAXWM, | |
3437 | SNB_DISPLAY_DFTWM, | |
3438 | 2, | |
3439 | SNB_FIFO_LINE_SIZE | |
3440 | }; | |
d210246a | 3441 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3442 | SNB_CURSOR_FIFO, |
3443 | SNB_CURSOR_MAXWM, | |
3444 | SNB_CURSOR_DFTWM, | |
3445 | 2, | |
3446 | SNB_FIFO_LINE_SIZE | |
3447 | }; | |
d210246a | 3448 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3449 | SNB_DISPLAY_SR_FIFO, |
3450 | SNB_DISPLAY_MAX_SRWM, | |
3451 | SNB_DISPLAY_DFT_SRWM, | |
3452 | 2, | |
3453 | SNB_FIFO_LINE_SIZE | |
3454 | }; | |
d210246a | 3455 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3456 | SNB_CURSOR_SR_FIFO, |
3457 | SNB_CURSOR_MAX_SRWM, | |
3458 | SNB_CURSOR_DFT_SRWM, | |
3459 | 2, | |
3460 | SNB_FIFO_LINE_SIZE | |
3461 | }; | |
3462 | ||
3463 | ||
dff33cfc JB |
3464 | /** |
3465 | * intel_calculate_wm - calculate watermark level | |
3466 | * @clock_in_khz: pixel clock | |
3467 | * @wm: chip FIFO params | |
3468 | * @pixel_size: display pixel size | |
3469 | * @latency_ns: memory latency for the platform | |
3470 | * | |
3471 | * Calculate the watermark level (the level at which the display plane will | |
3472 | * start fetching from memory again). Each chip has a different display | |
3473 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3474 | * in the correct intel_watermark_params structure. | |
3475 | * | |
3476 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3477 | * on the pixel size. When it reaches the watermark level, it'll start | |
3478 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3479 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3480 | * will occur, and a display engine hang could result. | |
3481 | */ | |
7662c8bd | 3482 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3483 | const struct intel_watermark_params *wm, |
3484 | int fifo_size, | |
7662c8bd SL |
3485 | int pixel_size, |
3486 | unsigned long latency_ns) | |
3487 | { | |
390c4dd4 | 3488 | long entries_required, wm_size; |
dff33cfc | 3489 | |
d660467c JB |
3490 | /* |
3491 | * Note: we need to make sure we don't overflow for various clock & | |
3492 | * latency values. | |
3493 | * clocks go from a few thousand to several hundred thousand. | |
3494 | * latency is usually a few thousand | |
3495 | */ | |
3496 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3497 | 1000; | |
8de9b311 | 3498 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3499 | |
28c97730 | 3500 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc | 3501 | |
d210246a | 3502 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3503 | |
28c97730 | 3504 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 3505 | |
390c4dd4 JB |
3506 | /* Don't promote wm_size to unsigned... */ |
3507 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3508 | wm_size = wm->max_wm; |
c3add4b6 | 3509 | if (wm_size <= 0) |
7662c8bd SL |
3510 | wm_size = wm->default_wm; |
3511 | return wm_size; | |
3512 | } | |
3513 | ||
3514 | struct cxsr_latency { | |
3515 | int is_desktop; | |
95534263 | 3516 | int is_ddr3; |
7662c8bd SL |
3517 | unsigned long fsb_freq; |
3518 | unsigned long mem_freq; | |
3519 | unsigned long display_sr; | |
3520 | unsigned long display_hpll_disable; | |
3521 | unsigned long cursor_sr; | |
3522 | unsigned long cursor_hpll_disable; | |
3523 | }; | |
3524 | ||
403c89ff | 3525 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3526 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3527 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3528 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3529 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3530 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3531 | ||
3532 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3533 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3534 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3535 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3536 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3537 | ||
3538 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3539 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3540 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3541 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3542 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3543 | ||
3544 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3545 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3546 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3547 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3548 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3549 | ||
3550 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3551 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3552 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3553 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3554 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3555 | ||
3556 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3557 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3558 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3559 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3560 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3561 | }; |
3562 | ||
403c89ff CW |
3563 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3564 | int is_ddr3, | |
3565 | int fsb, | |
3566 | int mem) | |
7662c8bd | 3567 | { |
403c89ff | 3568 | const struct cxsr_latency *latency; |
7662c8bd | 3569 | int i; |
7662c8bd SL |
3570 | |
3571 | if (fsb == 0 || mem == 0) | |
3572 | return NULL; | |
3573 | ||
3574 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3575 | latency = &cxsr_latency_table[i]; | |
3576 | if (is_desktop == latency->is_desktop && | |
95534263 | 3577 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3578 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3579 | return latency; | |
7662c8bd | 3580 | } |
decbbcda | 3581 | |
28c97730 | 3582 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3583 | |
3584 | return NULL; | |
7662c8bd SL |
3585 | } |
3586 | ||
f2b115e6 | 3587 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3588 | { |
3589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3590 | |
3591 | /* deactivate cxsr */ | |
3e33d94d | 3592 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3593 | } |
3594 | ||
bcc24fb4 JB |
3595 | /* |
3596 | * Latency for FIFO fetches is dependent on several factors: | |
3597 | * - memory configuration (speed, channels) | |
3598 | * - chipset | |
3599 | * - current MCH state | |
3600 | * It can be fairly high in some situations, so here we assume a fairly | |
3601 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3602 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3603 | * and power consumption (set it too low to save power and we might see | |
3604 | * FIFO underruns and display "flicker"). | |
3605 | * | |
3606 | * A value of 5us seems to be a good balance; safe for very low end | |
3607 | * platforms but not overly aggressive on lower latency configs. | |
3608 | */ | |
69e302a9 | 3609 | static const int latency_ns = 5000; |
7662c8bd | 3610 | |
e70236a8 | 3611 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3612 | { |
3613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3614 | uint32_t dsparb = I915_READ(DSPARB); | |
3615 | int size; | |
3616 | ||
8de9b311 CW |
3617 | size = dsparb & 0x7f; |
3618 | if (plane) | |
3619 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3620 | |
28c97730 | 3621 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3622 | plane ? "B" : "A", size); |
dff33cfc JB |
3623 | |
3624 | return size; | |
3625 | } | |
7662c8bd | 3626 | |
e70236a8 JB |
3627 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3628 | { | |
3629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3630 | uint32_t dsparb = I915_READ(DSPARB); | |
3631 | int size; | |
3632 | ||
8de9b311 CW |
3633 | size = dsparb & 0x1ff; |
3634 | if (plane) | |
3635 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3636 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3637 | |
28c97730 | 3638 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3639 | plane ? "B" : "A", size); |
dff33cfc JB |
3640 | |
3641 | return size; | |
3642 | } | |
7662c8bd | 3643 | |
e70236a8 JB |
3644 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3645 | { | |
3646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3647 | uint32_t dsparb = I915_READ(DSPARB); | |
3648 | int size; | |
3649 | ||
3650 | size = dsparb & 0x7f; | |
3651 | size >>= 2; /* Convert to cachelines */ | |
3652 | ||
28c97730 | 3653 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3654 | plane ? "B" : "A", |
3655 | size); | |
e70236a8 JB |
3656 | |
3657 | return size; | |
3658 | } | |
3659 | ||
3660 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3661 | { | |
3662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3663 | uint32_t dsparb = I915_READ(DSPARB); | |
3664 | int size; | |
3665 | ||
3666 | size = dsparb & 0x7f; | |
3667 | size >>= 1; /* Convert to cachelines */ | |
3668 | ||
28c97730 | 3669 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3670 | plane ? "B" : "A", size); |
e70236a8 JB |
3671 | |
3672 | return size; | |
3673 | } | |
3674 | ||
d210246a CW |
3675 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3676 | { | |
3677 | struct drm_crtc *crtc, *enabled = NULL; | |
3678 | ||
3679 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3680 | if (crtc->enabled && crtc->fb) { | |
3681 | if (enabled) | |
3682 | return NULL; | |
3683 | enabled = crtc; | |
3684 | } | |
3685 | } | |
3686 | ||
3687 | return enabled; | |
3688 | } | |
3689 | ||
3690 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3691 | { |
3692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3693 | struct drm_crtc *crtc; |
403c89ff | 3694 | const struct cxsr_latency *latency; |
d4294342 ZY |
3695 | u32 reg; |
3696 | unsigned long wm; | |
d4294342 | 3697 | |
403c89ff | 3698 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3699 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3700 | if (!latency) { |
3701 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3702 | pineview_disable_cxsr(dev); | |
3703 | return; | |
3704 | } | |
3705 | ||
d210246a CW |
3706 | crtc = single_enabled_crtc(dev); |
3707 | if (crtc) { | |
3708 | int clock = crtc->mode.clock; | |
3709 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3710 | |
3711 | /* Display SR */ | |
d210246a CW |
3712 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3713 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3714 | pixel_size, latency->display_sr); |
3715 | reg = I915_READ(DSPFW1); | |
3716 | reg &= ~DSPFW_SR_MASK; | |
3717 | reg |= wm << DSPFW_SR_SHIFT; | |
3718 | I915_WRITE(DSPFW1, reg); | |
3719 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3720 | ||
3721 | /* cursor SR */ | |
d210246a CW |
3722 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3723 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3724 | pixel_size, latency->cursor_sr); |
3725 | reg = I915_READ(DSPFW3); | |
3726 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3727 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3728 | I915_WRITE(DSPFW3, reg); | |
3729 | ||
3730 | /* Display HPLL off SR */ | |
d210246a CW |
3731 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
3732 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3733 | pixel_size, latency->display_hpll_disable); |
3734 | reg = I915_READ(DSPFW3); | |
3735 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3736 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3737 | I915_WRITE(DSPFW3, reg); | |
3738 | ||
3739 | /* cursor HPLL off SR */ | |
d210246a CW |
3740 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
3741 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3742 | pixel_size, latency->cursor_hpll_disable); |
3743 | reg = I915_READ(DSPFW3); | |
3744 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3745 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3746 | I915_WRITE(DSPFW3, reg); | |
3747 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3748 | ||
3749 | /* activate cxsr */ | |
3e33d94d CW |
3750 | I915_WRITE(DSPFW3, |
3751 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3752 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3753 | } else { | |
3754 | pineview_disable_cxsr(dev); | |
3755 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3756 | } | |
3757 | } | |
3758 | ||
417ae147 CW |
3759 | static bool g4x_compute_wm0(struct drm_device *dev, |
3760 | int plane, | |
3761 | const struct intel_watermark_params *display, | |
3762 | int display_latency_ns, | |
3763 | const struct intel_watermark_params *cursor, | |
3764 | int cursor_latency_ns, | |
3765 | int *plane_wm, | |
3766 | int *cursor_wm) | |
3767 | { | |
3768 | struct drm_crtc *crtc; | |
3769 | int htotal, hdisplay, clock, pixel_size; | |
3770 | int line_time_us, line_count; | |
3771 | int entries, tlb_miss; | |
3772 | ||
3773 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
3774 | if (crtc->fb == NULL || !crtc->enabled) { |
3775 | *cursor_wm = cursor->guard_size; | |
3776 | *plane_wm = display->guard_size; | |
417ae147 | 3777 | return false; |
5c72d064 | 3778 | } |
417ae147 CW |
3779 | |
3780 | htotal = crtc->mode.htotal; | |
3781 | hdisplay = crtc->mode.hdisplay; | |
3782 | clock = crtc->mode.clock; | |
3783 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3784 | ||
3785 | /* Use the small buffer method to calculate plane watermark */ | |
3786 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
3787 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
3788 | if (tlb_miss > 0) | |
3789 | entries += tlb_miss; | |
3790 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
3791 | *plane_wm = entries + display->guard_size; | |
3792 | if (*plane_wm > (int)display->max_wm) | |
3793 | *plane_wm = display->max_wm; | |
3794 | ||
3795 | /* Use the large buffer method to calculate cursor watermark */ | |
3796 | line_time_us = ((htotal * 1000) / clock); | |
3797 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
3798 | entries = line_count * 64 * pixel_size; | |
3799 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
3800 | if (tlb_miss > 0) | |
3801 | entries += tlb_miss; | |
3802 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
3803 | *cursor_wm = entries + cursor->guard_size; | |
3804 | if (*cursor_wm > (int)cursor->max_wm) | |
3805 | *cursor_wm = (int)cursor->max_wm; | |
3806 | ||
3807 | return true; | |
3808 | } | |
3809 | ||
3810 | /* | |
3811 | * Check the wm result. | |
3812 | * | |
3813 | * If any calculated watermark values is larger than the maximum value that | |
3814 | * can be programmed into the associated watermark register, that watermark | |
3815 | * must be disabled. | |
3816 | */ | |
3817 | static bool g4x_check_srwm(struct drm_device *dev, | |
3818 | int display_wm, int cursor_wm, | |
3819 | const struct intel_watermark_params *display, | |
3820 | const struct intel_watermark_params *cursor) | |
652c393a | 3821 | { |
417ae147 CW |
3822 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
3823 | display_wm, cursor_wm); | |
652c393a | 3824 | |
417ae147 CW |
3825 | if (display_wm > display->max_wm) { |
3826 | DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n", | |
3827 | display_wm, display->max_wm); | |
3828 | return false; | |
3829 | } | |
0e442c60 | 3830 | |
417ae147 CW |
3831 | if (cursor_wm > cursor->max_wm) { |
3832 | DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n", | |
3833 | cursor_wm, cursor->max_wm); | |
3834 | return false; | |
3835 | } | |
0e442c60 | 3836 | |
417ae147 CW |
3837 | if (!(display_wm || cursor_wm)) { |
3838 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
3839 | return false; | |
3840 | } | |
0e442c60 | 3841 | |
417ae147 CW |
3842 | return true; |
3843 | } | |
0e442c60 | 3844 | |
417ae147 | 3845 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
3846 | int plane, |
3847 | int latency_ns, | |
417ae147 CW |
3848 | const struct intel_watermark_params *display, |
3849 | const struct intel_watermark_params *cursor, | |
3850 | int *display_wm, int *cursor_wm) | |
3851 | { | |
d210246a CW |
3852 | struct drm_crtc *crtc; |
3853 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
3854 | unsigned long line_time_us; |
3855 | int line_count, line_size; | |
3856 | int small, large; | |
3857 | int entries; | |
0e442c60 | 3858 | |
417ae147 CW |
3859 | if (!latency_ns) { |
3860 | *display_wm = *cursor_wm = 0; | |
3861 | return false; | |
3862 | } | |
0e442c60 | 3863 | |
d210246a CW |
3864 | crtc = intel_get_crtc_for_plane(dev, plane); |
3865 | hdisplay = crtc->mode.hdisplay; | |
3866 | htotal = crtc->mode.htotal; | |
3867 | clock = crtc->mode.clock; | |
3868 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3869 | ||
417ae147 CW |
3870 | line_time_us = (htotal * 1000) / clock; |
3871 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
3872 | line_size = hdisplay * pixel_size; | |
0e442c60 | 3873 | |
417ae147 CW |
3874 | /* Use the minimum of the small and large buffer method for primary */ |
3875 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
3876 | large = line_count * line_size; | |
0e442c60 | 3877 | |
417ae147 CW |
3878 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
3879 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 3880 | |
417ae147 CW |
3881 | /* calculate the self-refresh watermark for display cursor */ |
3882 | entries = line_count * pixel_size * 64; | |
3883 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
3884 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 3885 | |
417ae147 CW |
3886 | return g4x_check_srwm(dev, |
3887 | *display_wm, *cursor_wm, | |
3888 | display, cursor); | |
3889 | } | |
4fe5e611 | 3890 | |
7ccb4a53 | 3891 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
3892 | |
3893 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
3894 | { |
3895 | static const int sr_latency_ns = 12000; | |
3896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3897 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
3898 | int plane_sr, cursor_sr; |
3899 | unsigned int enabled = 0; | |
417ae147 CW |
3900 | |
3901 | if (g4x_compute_wm0(dev, 0, | |
3902 | &g4x_wm_info, latency_ns, | |
3903 | &g4x_cursor_wm_info, latency_ns, | |
3904 | &planea_wm, &cursora_wm)) | |
d210246a | 3905 | enabled |= 1; |
417ae147 CW |
3906 | |
3907 | if (g4x_compute_wm0(dev, 1, | |
3908 | &g4x_wm_info, latency_ns, | |
3909 | &g4x_cursor_wm_info, latency_ns, | |
3910 | &planeb_wm, &cursorb_wm)) | |
d210246a | 3911 | enabled |= 2; |
417ae147 CW |
3912 | |
3913 | plane_sr = cursor_sr = 0; | |
d210246a CW |
3914 | if (single_plane_enabled(enabled) && |
3915 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
3916 | sr_latency_ns, | |
417ae147 CW |
3917 | &g4x_wm_info, |
3918 | &g4x_cursor_wm_info, | |
3919 | &plane_sr, &cursor_sr)) | |
0e442c60 | 3920 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
3921 | else |
3922 | I915_WRITE(FW_BLC_SELF, | |
3923 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 3924 | |
308977ac CW |
3925 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
3926 | planea_wm, cursora_wm, | |
3927 | planeb_wm, cursorb_wm, | |
3928 | plane_sr, cursor_sr); | |
0e442c60 | 3929 | |
417ae147 CW |
3930 | I915_WRITE(DSPFW1, |
3931 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 3932 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
3933 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
3934 | planea_wm); | |
3935 | I915_WRITE(DSPFW2, | |
3936 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
3937 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
3938 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
3939 | I915_WRITE(DSPFW3, |
3940 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 3941 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
3942 | } |
3943 | ||
d210246a | 3944 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
3945 | { |
3946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
3947 | struct drm_crtc *crtc; |
3948 | int srwm = 1; | |
4fe5e611 | 3949 | int cursor_sr = 16; |
1dc7546d JB |
3950 | |
3951 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
3952 | crtc = single_enabled_crtc(dev); |
3953 | if (crtc) { | |
1dc7546d | 3954 | /* self-refresh has much higher latency */ |
69e302a9 | 3955 | static const int sr_latency_ns = 12000; |
d210246a CW |
3956 | int clock = crtc->mode.clock; |
3957 | int htotal = crtc->mode.htotal; | |
3958 | int hdisplay = crtc->mode.hdisplay; | |
3959 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
3960 | unsigned long line_time_us; | |
3961 | int entries; | |
1dc7546d | 3962 | |
d210246a | 3963 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
3964 | |
3965 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
3966 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
3967 | pixel_size * hdisplay; | |
3968 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 3969 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
3970 | if (srwm < 0) |
3971 | srwm = 1; | |
1b07e04e | 3972 | srwm &= 0x1ff; |
308977ac CW |
3973 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
3974 | entries, srwm); | |
4fe5e611 | 3975 | |
d210246a | 3976 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3977 | pixel_size * 64; |
d210246a | 3978 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 3979 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 3980 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 3981 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3982 | |
3983 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3984 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3985 | ||
3986 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3987 | "cursor %d\n", srwm, cursor_sr); | |
3988 | ||
a6c45cf0 | 3989 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3990 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3991 | } else { |
3992 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3993 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3994 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3995 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3996 | } |
7662c8bd | 3997 | |
1dc7546d JB |
3998 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3999 | srwm); | |
7662c8bd SL |
4000 | |
4001 | /* 965 has limitations... */ | |
417ae147 CW |
4002 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4003 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4004 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4005 | /* update cursor SR watermark */ |
4006 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4007 | } |
4008 | ||
d210246a | 4009 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4010 | { |
4011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4012 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4013 | uint32_t fwater_lo; |
4014 | uint32_t fwater_hi; | |
d210246a CW |
4015 | int cwm, srwm = 1; |
4016 | int fifo_size; | |
dff33cfc | 4017 | int planea_wm, planeb_wm; |
d210246a | 4018 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4019 | |
72557b4f | 4020 | if (IS_I945GM(dev)) |
d210246a | 4021 | wm_info = &i945_wm_info; |
a6c45cf0 | 4022 | else if (!IS_GEN2(dev)) |
d210246a | 4023 | wm_info = &i915_wm_info; |
7662c8bd | 4024 | else |
d210246a CW |
4025 | wm_info = &i855_wm_info; |
4026 | ||
4027 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4028 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4029 | if (crtc->enabled && crtc->fb) { | |
4030 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4031 | wm_info, fifo_size, | |
4032 | crtc->fb->bits_per_pixel / 8, | |
4033 | latency_ns); | |
4034 | enabled = crtc; | |
4035 | } else | |
4036 | planea_wm = fifo_size - wm_info->guard_size; | |
4037 | ||
4038 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4039 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4040 | if (crtc->enabled && crtc->fb) { | |
4041 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4042 | wm_info, fifo_size, | |
4043 | crtc->fb->bits_per_pixel / 8, | |
4044 | latency_ns); | |
4045 | if (enabled == NULL) | |
4046 | enabled = crtc; | |
4047 | else | |
4048 | enabled = NULL; | |
4049 | } else | |
4050 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4051 | |
28c97730 | 4052 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4053 | |
4054 | /* | |
4055 | * Overlay gets an aggressive default since video jitter is bad. | |
4056 | */ | |
4057 | cwm = 2; | |
4058 | ||
18b2190c AL |
4059 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4060 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4061 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4062 | else if (IS_I915GM(dev)) | |
4063 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4064 | ||
dff33cfc | 4065 | /* Calc sr entries for one plane configs */ |
d210246a | 4066 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4067 | /* self-refresh has much higher latency */ |
69e302a9 | 4068 | static const int sr_latency_ns = 6000; |
d210246a CW |
4069 | int clock = enabled->mode.clock; |
4070 | int htotal = enabled->mode.htotal; | |
4071 | int hdisplay = enabled->mode.hdisplay; | |
4072 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4073 | unsigned long line_time_us; | |
4074 | int entries; | |
dff33cfc | 4075 | |
d210246a | 4076 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4077 | |
4078 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4079 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4080 | pixel_size * hdisplay; | |
4081 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4082 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4083 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4084 | if (srwm < 0) |
4085 | srwm = 1; | |
ee980b80 LP |
4086 | |
4087 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4088 | I915_WRITE(FW_BLC_SELF, |
4089 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4090 | else if (IS_I915GM(dev)) | |
ee980b80 | 4091 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4092 | } |
4093 | ||
28c97730 | 4094 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4095 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4096 | |
dff33cfc JB |
4097 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4098 | fwater_hi = (cwm & 0x1f); | |
4099 | ||
4100 | /* Set request length to 8 cachelines per fetch */ | |
4101 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4102 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4103 | |
4104 | I915_WRITE(FW_BLC, fwater_lo); | |
4105 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4106 | |
d210246a CW |
4107 | if (HAS_FW_BLC(dev)) { |
4108 | if (enabled) { | |
4109 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4110 | I915_WRITE(FW_BLC_SELF, | |
4111 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4112 | else if (IS_I915GM(dev)) | |
4113 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4114 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4115 | } else | |
4116 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4117 | } | |
7662c8bd SL |
4118 | } |
4119 | ||
d210246a | 4120 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4121 | { |
4122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4123 | struct drm_crtc *crtc; |
4124 | uint32_t fwater_lo; | |
dff33cfc | 4125 | int planea_wm; |
7662c8bd | 4126 | |
d210246a CW |
4127 | crtc = single_enabled_crtc(dev); |
4128 | if (crtc == NULL) | |
4129 | return; | |
7662c8bd | 4130 | |
d210246a CW |
4131 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4132 | dev_priv->display.get_fifo_size(dev, 0), | |
4133 | crtc->fb->bits_per_pixel / 8, | |
4134 | latency_ns); | |
4135 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4136 | fwater_lo |= (3<<8) | planea_wm; |
4137 | ||
28c97730 | 4138 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4139 | |
4140 | I915_WRITE(FW_BLC, fwater_lo); | |
4141 | } | |
4142 | ||
7f8a8569 | 4143 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4144 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4145 | |
4ed765f9 CW |
4146 | static bool ironlake_compute_wm0(struct drm_device *dev, |
4147 | int pipe, | |
1398261a | 4148 | const struct intel_watermark_params *display, |
a0fa62d3 | 4149 | int display_latency_ns, |
1398261a | 4150 | const struct intel_watermark_params *cursor, |
a0fa62d3 | 4151 | int cursor_latency_ns, |
4ed765f9 CW |
4152 | int *plane_wm, |
4153 | int *cursor_wm) | |
7f8a8569 | 4154 | { |
c936f44d | 4155 | struct drm_crtc *crtc; |
db66e37d CW |
4156 | int htotal, hdisplay, clock, pixel_size; |
4157 | int line_time_us, line_count; | |
4158 | int entries, tlb_miss; | |
c936f44d | 4159 | |
4ed765f9 CW |
4160 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
4161 | if (crtc->fb == NULL || !crtc->enabled) | |
4162 | return false; | |
7f8a8569 | 4163 | |
4ed765f9 CW |
4164 | htotal = crtc->mode.htotal; |
4165 | hdisplay = crtc->mode.hdisplay; | |
4166 | clock = crtc->mode.clock; | |
4167 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4168 | ||
4169 | /* Use the small buffer method to calculate plane watermark */ | |
a0fa62d3 | 4170 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
db66e37d CW |
4171 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
4172 | if (tlb_miss > 0) | |
4173 | entries += tlb_miss; | |
1398261a YL |
4174 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
4175 | *plane_wm = entries + display->guard_size; | |
4176 | if (*plane_wm > (int)display->max_wm) | |
4177 | *plane_wm = display->max_wm; | |
4ed765f9 CW |
4178 | |
4179 | /* Use the large buffer method to calculate cursor watermark */ | |
4180 | line_time_us = ((htotal * 1000) / clock); | |
a0fa62d3 | 4181 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
4ed765f9 | 4182 | entries = line_count * 64 * pixel_size; |
db66e37d CW |
4183 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
4184 | if (tlb_miss > 0) | |
4185 | entries += tlb_miss; | |
1398261a YL |
4186 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4187 | *cursor_wm = entries + cursor->guard_size; | |
4188 | if (*cursor_wm > (int)cursor->max_wm) | |
4189 | *cursor_wm = (int)cursor->max_wm; | |
7f8a8569 | 4190 | |
4ed765f9 CW |
4191 | return true; |
4192 | } | |
c936f44d | 4193 | |
1398261a YL |
4194 | /* |
4195 | * Check the wm result. | |
4196 | * | |
4197 | * If any calculated watermark values is larger than the maximum value that | |
4198 | * can be programmed into the associated watermark register, that watermark | |
4199 | * must be disabled. | |
1398261a | 4200 | */ |
b79d4990 JB |
4201 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4202 | int fbc_wm, int display_wm, int cursor_wm, | |
4203 | const struct intel_watermark_params *display, | |
4204 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4205 | { |
4206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4207 | ||
4208 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4209 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4210 | ||
4211 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4212 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4213 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4214 | |
4215 | /* fbc has it's own way to disable FBC WM */ | |
4216 | I915_WRITE(DISP_ARB_CTL, | |
4217 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4218 | return false; | |
4219 | } | |
4220 | ||
b79d4990 | 4221 | if (display_wm > display->max_wm) { |
1398261a | 4222 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4223 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4224 | return false; |
4225 | } | |
4226 | ||
b79d4990 | 4227 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4228 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4229 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4230 | return false; |
4231 | } | |
4232 | ||
4233 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4234 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4235 | return false; | |
4236 | } | |
4237 | ||
4238 | return true; | |
4239 | } | |
4240 | ||
4241 | /* | |
4242 | * Compute watermark values of WM[1-3], | |
4243 | */ | |
d210246a CW |
4244 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4245 | int latency_ns, | |
b79d4990 JB |
4246 | const struct intel_watermark_params *display, |
4247 | const struct intel_watermark_params *cursor, | |
4248 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4249 | { |
d210246a | 4250 | struct drm_crtc *crtc; |
1398261a | 4251 | unsigned long line_time_us; |
d210246a | 4252 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4253 | int line_count, line_size; |
1398261a YL |
4254 | int small, large; |
4255 | int entries; | |
1398261a YL |
4256 | |
4257 | if (!latency_ns) { | |
4258 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4259 | return false; | |
4260 | } | |
4261 | ||
d210246a CW |
4262 | crtc = intel_get_crtc_for_plane(dev, plane); |
4263 | hdisplay = crtc->mode.hdisplay; | |
4264 | htotal = crtc->mode.htotal; | |
4265 | clock = crtc->mode.clock; | |
4266 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4267 | ||
1398261a YL |
4268 | line_time_us = (htotal * 1000) / clock; |
4269 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4270 | line_size = hdisplay * pixel_size; | |
4271 | ||
4272 | /* Use the minimum of the small and large buffer method for primary */ | |
4273 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4274 | large = line_count * line_size; | |
4275 | ||
b79d4990 JB |
4276 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4277 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4278 | |
4279 | /* | |
b79d4990 | 4280 | * Spec says: |
1398261a YL |
4281 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4282 | */ | |
4283 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4284 | ||
4285 | /* calculate the self-refresh watermark for display cursor */ | |
4286 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4287 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4288 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4289 | |
b79d4990 JB |
4290 | return ironlake_check_srwm(dev, level, |
4291 | *fbc_wm, *display_wm, *cursor_wm, | |
4292 | display, cursor); | |
4293 | } | |
4294 | ||
d210246a | 4295 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4296 | { |
4297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4298 | int fbc_wm, plane_wm, cursor_wm; |
4299 | unsigned int enabled; | |
b79d4990 JB |
4300 | |
4301 | enabled = 0; | |
4302 | if (ironlake_compute_wm0(dev, 0, | |
4303 | &ironlake_display_wm_info, | |
4304 | ILK_LP0_PLANE_LATENCY, | |
4305 | &ironlake_cursor_wm_info, | |
4306 | ILK_LP0_CURSOR_LATENCY, | |
4307 | &plane_wm, &cursor_wm)) { | |
4308 | I915_WRITE(WM0_PIPEA_ILK, | |
4309 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4310 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4311 | " plane %d, " "cursor: %d\n", | |
4312 | plane_wm, cursor_wm); | |
d210246a | 4313 | enabled |= 1; |
b79d4990 JB |
4314 | } |
4315 | ||
4316 | if (ironlake_compute_wm0(dev, 1, | |
4317 | &ironlake_display_wm_info, | |
4318 | ILK_LP0_PLANE_LATENCY, | |
4319 | &ironlake_cursor_wm_info, | |
4320 | ILK_LP0_CURSOR_LATENCY, | |
4321 | &plane_wm, &cursor_wm)) { | |
4322 | I915_WRITE(WM0_PIPEB_ILK, | |
4323 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4324 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4325 | " plane %d, cursor: %d\n", | |
4326 | plane_wm, cursor_wm); | |
d210246a | 4327 | enabled |= 2; |
b79d4990 JB |
4328 | } |
4329 | ||
4330 | /* | |
4331 | * Calculate and update the self-refresh watermark only when one | |
4332 | * display plane is used. | |
4333 | */ | |
4334 | I915_WRITE(WM3_LP_ILK, 0); | |
4335 | I915_WRITE(WM2_LP_ILK, 0); | |
4336 | I915_WRITE(WM1_LP_ILK, 0); | |
4337 | ||
d210246a | 4338 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4339 | return; |
d210246a | 4340 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4341 | |
4342 | /* WM1 */ | |
d210246a CW |
4343 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4344 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4345 | &ironlake_display_srwm_info, |
4346 | &ironlake_cursor_srwm_info, | |
4347 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4348 | return; | |
4349 | ||
4350 | I915_WRITE(WM1_LP_ILK, | |
4351 | WM1_LP_SR_EN | | |
4352 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4353 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4354 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4355 | cursor_wm); | |
4356 | ||
4357 | /* WM2 */ | |
d210246a CW |
4358 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4359 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4360 | &ironlake_display_srwm_info, |
4361 | &ironlake_cursor_srwm_info, | |
4362 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4363 | return; | |
4364 | ||
4365 | I915_WRITE(WM2_LP_ILK, | |
4366 | WM2_LP_EN | | |
4367 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4368 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4369 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4370 | cursor_wm); | |
4371 | ||
4372 | /* | |
4373 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4374 | * data for that power state | |
4375 | */ | |
1398261a YL |
4376 | } |
4377 | ||
d210246a | 4378 | static void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4379 | { |
4380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4381 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
d210246a CW |
4382 | int fbc_wm, plane_wm, cursor_wm; |
4383 | unsigned int enabled; | |
1398261a YL |
4384 | |
4385 | enabled = 0; | |
4386 | if (ironlake_compute_wm0(dev, 0, | |
4387 | &sandybridge_display_wm_info, latency, | |
4388 | &sandybridge_cursor_wm_info, latency, | |
4389 | &plane_wm, &cursor_wm)) { | |
4390 | I915_WRITE(WM0_PIPEA_ILK, | |
4391 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4392 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4393 | " plane %d, " "cursor: %d\n", | |
4394 | plane_wm, cursor_wm); | |
d210246a | 4395 | enabled |= 1; |
1398261a YL |
4396 | } |
4397 | ||
4398 | if (ironlake_compute_wm0(dev, 1, | |
4399 | &sandybridge_display_wm_info, latency, | |
4400 | &sandybridge_cursor_wm_info, latency, | |
4401 | &plane_wm, &cursor_wm)) { | |
4402 | I915_WRITE(WM0_PIPEB_ILK, | |
4403 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4404 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4405 | " plane %d, cursor: %d\n", | |
4406 | plane_wm, cursor_wm); | |
d210246a | 4407 | enabled |= 2; |
1398261a YL |
4408 | } |
4409 | ||
4410 | /* | |
4411 | * Calculate and update the self-refresh watermark only when one | |
4412 | * display plane is used. | |
4413 | * | |
4414 | * SNB support 3 levels of watermark. | |
4415 | * | |
4416 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4417 | * and disabled in the descending order | |
4418 | * | |
4419 | */ | |
4420 | I915_WRITE(WM3_LP_ILK, 0); | |
4421 | I915_WRITE(WM2_LP_ILK, 0); | |
4422 | I915_WRITE(WM1_LP_ILK, 0); | |
4423 | ||
d210246a | 4424 | if (!single_plane_enabled(enabled)) |
1398261a | 4425 | return; |
d210246a | 4426 | enabled = ffs(enabled) - 1; |
1398261a YL |
4427 | |
4428 | /* WM1 */ | |
d210246a CW |
4429 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4430 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4431 | &sandybridge_display_srwm_info, |
4432 | &sandybridge_cursor_srwm_info, | |
4433 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4434 | return; |
4435 | ||
4436 | I915_WRITE(WM1_LP_ILK, | |
4437 | WM1_LP_SR_EN | | |
4438 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4439 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4440 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4441 | cursor_wm); | |
4442 | ||
4443 | /* WM2 */ | |
d210246a CW |
4444 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4445 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4446 | &sandybridge_display_srwm_info, |
4447 | &sandybridge_cursor_srwm_info, | |
4448 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4449 | return; |
4450 | ||
4451 | I915_WRITE(WM2_LP_ILK, | |
4452 | WM2_LP_EN | | |
4453 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4454 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4455 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4456 | cursor_wm); | |
4457 | ||
4458 | /* WM3 */ | |
d210246a CW |
4459 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4460 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4461 | &sandybridge_display_srwm_info, |
4462 | &sandybridge_cursor_srwm_info, | |
4463 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4464 | return; |
4465 | ||
4466 | I915_WRITE(WM3_LP_ILK, | |
4467 | WM3_LP_EN | | |
4468 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4469 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4470 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4471 | cursor_wm); | |
4472 | } | |
4473 | ||
7662c8bd SL |
4474 | /** |
4475 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4476 | * | |
4477 | * Calculate watermark values for the various WM regs based on current mode | |
4478 | * and plane configuration. | |
4479 | * | |
4480 | * There are several cases to deal with here: | |
4481 | * - normal (i.e. non-self-refresh) | |
4482 | * - self-refresh (SR) mode | |
4483 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4484 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4485 | * lines), so need to account for TLB latency | |
4486 | * | |
4487 | * The normal calculation is: | |
4488 | * watermark = dotclock * bytes per pixel * latency | |
4489 | * where latency is platform & configuration dependent (we assume pessimal | |
4490 | * values here). | |
4491 | * | |
4492 | * The SR calculation is: | |
4493 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4494 | * bytes per pixel | |
4495 | * where | |
4496 | * line time = htotal / dotclock | |
fa143215 | 4497 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4498 | * and latency is assumed to be high, as above. |
4499 | * | |
4500 | * The final value programmed to the register should always be rounded up, | |
4501 | * and include an extra 2 entries to account for clock crossings. | |
4502 | * | |
4503 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4504 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4505 | */ |
7662c8bd SL |
4506 | static void intel_update_watermarks(struct drm_device *dev) |
4507 | { | |
e70236a8 | 4508 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4509 | |
d210246a CW |
4510 | if (dev_priv->display.update_wm) |
4511 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4512 | } |
4513 | ||
a7615030 CW |
4514 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4515 | { | |
4516 | return dev_priv->lvds_use_ssc && i915_panel_use_ssc; | |
4517 | } | |
4518 | ||
f564048e EA |
4519 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4520 | struct drm_display_mode *mode, | |
4521 | struct drm_display_mode *adjusted_mode, | |
4522 | int x, int y, | |
4523 | struct drm_framebuffer *old_fb) | |
4524 | { | |
4525 | struct drm_device *dev = crtc->dev; | |
4526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4527 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4528 | int pipe = intel_crtc->pipe; | |
4529 | int plane = intel_crtc->plane; | |
4530 | u32 fp_reg, dpll_reg; | |
4531 | int refclk, num_connectors = 0; | |
4532 | intel_clock_t clock, reduced_clock; | |
4533 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; | |
4534 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; | |
4535 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; | |
4536 | struct intel_encoder *has_edp_encoder = NULL; | |
4537 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4538 | struct intel_encoder *encoder; | |
4539 | const intel_limit_t *limit; | |
4540 | int ret; | |
4541 | struct fdi_m_n m_n = {0}; | |
4542 | u32 reg, temp; | |
4543 | u32 lvds_sync = 0; | |
4544 | int target_clock; | |
4545 | ||
f564048e EA |
4546 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
4547 | if (encoder->base.crtc != crtc) | |
4548 | continue; | |
4549 | ||
4550 | switch (encoder->type) { | |
4551 | case INTEL_OUTPUT_LVDS: | |
4552 | is_lvds = true; | |
4553 | break; | |
4554 | case INTEL_OUTPUT_SDVO: | |
4555 | case INTEL_OUTPUT_HDMI: | |
4556 | is_sdvo = true; | |
4557 | if (encoder->needs_tv_clock) | |
4558 | is_tv = true; | |
4559 | break; | |
4560 | case INTEL_OUTPUT_DVO: | |
4561 | is_dvo = true; | |
4562 | break; | |
4563 | case INTEL_OUTPUT_TVOUT: | |
4564 | is_tv = true; | |
4565 | break; | |
4566 | case INTEL_OUTPUT_ANALOG: | |
4567 | is_crt = true; | |
4568 | break; | |
4569 | case INTEL_OUTPUT_DISPLAYPORT: | |
4570 | is_dp = true; | |
4571 | break; | |
4572 | case INTEL_OUTPUT_EDP: | |
4573 | has_edp_encoder = encoder; | |
4574 | break; | |
4575 | } | |
4576 | ||
4577 | num_connectors++; | |
4578 | } | |
4579 | ||
4580 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
4581 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4582 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4583 | refclk / 1000); | |
4584 | } else if (!IS_GEN2(dev)) { | |
4585 | refclk = 96000; | |
4586 | if (HAS_PCH_SPLIT(dev) && | |
4587 | (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base))) | |
4588 | refclk = 120000; /* 120Mhz refclk */ | |
4589 | } else { | |
4590 | refclk = 48000; | |
4591 | } | |
4592 | ||
4593 | /* | |
4594 | * Returns a set of divisors for the desired target clock with the given | |
4595 | * refclk, or FALSE. The returned values represent the clock equation: | |
4596 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4597 | */ | |
4598 | limit = intel_limit(crtc, refclk); | |
4599 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
4600 | if (!ok) { | |
4601 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
f564048e EA |
4602 | return -EINVAL; |
4603 | } | |
4604 | ||
4605 | /* Ensure that the cursor is valid for the new mode before changing... */ | |
4606 | intel_crtc_update_cursor(crtc, true); | |
4607 | ||
4608 | if (is_lvds && dev_priv->lvds_downclock_avail) { | |
4609 | has_reduced_clock = limit->find_pll(limit, crtc, | |
4610 | dev_priv->lvds_downclock, | |
4611 | refclk, | |
4612 | &reduced_clock); | |
4613 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { | |
4614 | /* | |
4615 | * If the different P is found, it means that we can't | |
4616 | * switch the display clock by using the FP0/FP1. | |
4617 | * In such case we will disable the LVDS downclock | |
4618 | * feature. | |
4619 | */ | |
4620 | DRM_DEBUG_KMS("Different P is found for " | |
4621 | "LVDS clock/downclock\n"); | |
4622 | has_reduced_clock = 0; | |
4623 | } | |
4624 | } | |
4625 | /* SDVO TV has fixed PLL values depend on its clock range, | |
4626 | this mirrors vbios setting. */ | |
4627 | if (is_sdvo && is_tv) { | |
4628 | if (adjusted_mode->clock >= 100000 | |
4629 | && adjusted_mode->clock < 140500) { | |
4630 | clock.p1 = 2; | |
4631 | clock.p2 = 10; | |
4632 | clock.n = 3; | |
4633 | clock.m1 = 16; | |
4634 | clock.m2 = 8; | |
4635 | } else if (adjusted_mode->clock >= 140500 | |
4636 | && adjusted_mode->clock <= 200000) { | |
4637 | clock.p1 = 1; | |
4638 | clock.p2 = 10; | |
4639 | clock.n = 6; | |
4640 | clock.m1 = 12; | |
4641 | clock.m2 = 8; | |
4642 | } | |
4643 | } | |
4644 | ||
4645 | /* FDI link */ | |
4646 | if (HAS_PCH_SPLIT(dev)) { | |
4647 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4648 | int lane = 0, link_bw, bpp; | |
4649 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
4650 | according to current link config */ | |
4651 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
4652 | target_clock = mode->clock; | |
4653 | intel_edp_link_config(has_edp_encoder, | |
4654 | &lane, &link_bw); | |
4655 | } else { | |
4656 | /* [e]DP over FDI requires target mode clock | |
4657 | instead of link clock */ | |
4658 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
4659 | target_clock = mode->clock; | |
4660 | else | |
4661 | target_clock = adjusted_mode->clock; | |
4662 | ||
4663 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
4664 | * each output octet as 10 bits. The actual frequency | |
4665 | * is stored as a divider into a 100MHz clock, and the | |
4666 | * mode pixel clock is stored in units of 1KHz. | |
4667 | * Hence the bw of each lane in terms of the mode signal | |
4668 | * is: | |
4669 | */ | |
4670 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4671 | } | |
4672 | ||
4673 | /* determine panel color depth */ | |
4674 | temp = I915_READ(PIPECONF(pipe)); | |
4675 | temp &= ~PIPE_BPC_MASK; | |
4676 | if (is_lvds) { | |
4677 | /* the BPC will be 6 if it is 18-bit LVDS panel */ | |
4678 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) | |
4679 | temp |= PIPE_8BPC; | |
4680 | else | |
4681 | temp |= PIPE_6BPC; | |
4682 | } else if (has_edp_encoder) { | |
4683 | switch (dev_priv->edp.bpp/3) { | |
4684 | case 8: | |
4685 | temp |= PIPE_8BPC; | |
4686 | break; | |
4687 | case 10: | |
4688 | temp |= PIPE_10BPC; | |
4689 | break; | |
4690 | case 6: | |
4691 | temp |= PIPE_6BPC; | |
4692 | break; | |
4693 | case 12: | |
4694 | temp |= PIPE_12BPC; | |
4695 | break; | |
4696 | } | |
4697 | } else | |
4698 | temp |= PIPE_8BPC; | |
4699 | I915_WRITE(PIPECONF(pipe), temp); | |
4700 | ||
4701 | switch (temp & PIPE_BPC_MASK) { | |
4702 | case PIPE_8BPC: | |
4703 | bpp = 24; | |
4704 | break; | |
4705 | case PIPE_10BPC: | |
4706 | bpp = 30; | |
4707 | break; | |
4708 | case PIPE_6BPC: | |
4709 | bpp = 18; | |
4710 | break; | |
4711 | case PIPE_12BPC: | |
4712 | bpp = 36; | |
4713 | break; | |
4714 | default: | |
4715 | DRM_ERROR("unknown pipe bpc value\n"); | |
4716 | bpp = 24; | |
4717 | } | |
4718 | ||
4719 | if (!lane) { | |
4720 | /* | |
4721 | * Account for spread spectrum to avoid | |
4722 | * oversubscribing the link. Max center spread | |
4723 | * is 2.5%; use 5% for safety's sake. | |
4724 | */ | |
4725 | u32 bps = target_clock * bpp * 21 / 20; | |
4726 | lane = bps / (link_bw * 8) + 1; | |
4727 | } | |
4728 | ||
4729 | intel_crtc->fdi_lanes = lane; | |
4730 | ||
4731 | if (pixel_multiplier > 1) | |
4732 | link_bw *= pixel_multiplier; | |
4733 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); | |
4734 | } | |
4735 | ||
4736 | /* Ironlake: try to setup display ref clock before DPLL | |
4737 | * enabling. This is only under driver's control after | |
4738 | * PCH B stepping, previous chipset stepping should be | |
4739 | * ignoring this setting. | |
4740 | */ | |
4741 | if (HAS_PCH_SPLIT(dev)) { | |
4742 | temp = I915_READ(PCH_DREF_CONTROL); | |
4743 | /* Always enable nonspread source */ | |
4744 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
4745 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
4746 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4747 | temp |= DREF_SSC_SOURCE_ENABLE; | |
4748 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4749 | ||
4750 | POSTING_READ(PCH_DREF_CONTROL); | |
4751 | udelay(200); | |
4752 | ||
4753 | if (has_edp_encoder) { | |
4754 | if (intel_panel_use_ssc(dev_priv)) { | |
4755 | temp |= DREF_SSC1_ENABLE; | |
4756 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4757 | ||
4758 | POSTING_READ(PCH_DREF_CONTROL); | |
4759 | udelay(200); | |
4760 | } | |
4761 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4762 | ||
4763 | /* Enable CPU source on CPU attached eDP */ | |
4764 | if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
4765 | if (intel_panel_use_ssc(dev_priv)) | |
4766 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
4767 | else | |
4768 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
4769 | } else { | |
4770 | /* Enable SSC on PCH eDP if needed */ | |
4771 | if (intel_panel_use_ssc(dev_priv)) { | |
4772 | DRM_ERROR("enabling SSC on PCH\n"); | |
4773 | temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; | |
4774 | } | |
4775 | } | |
4776 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4777 | POSTING_READ(PCH_DREF_CONTROL); | |
4778 | udelay(200); | |
4779 | } | |
4780 | } | |
4781 | ||
4782 | if (IS_PINEVIEW(dev)) { | |
4783 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | |
4784 | if (has_reduced_clock) | |
4785 | fp2 = (1 << reduced_clock.n) << 16 | | |
4786 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
4787 | } else { | |
4788 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
4789 | if (has_reduced_clock) | |
4790 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4791 | reduced_clock.m2; | |
4792 | } | |
4793 | ||
4794 | /* Enable autotuning of the PLL clock (if permissible) */ | |
4795 | if (HAS_PCH_SPLIT(dev)) { | |
4796 | int factor = 21; | |
4797 | ||
4798 | if (is_lvds) { | |
4799 | if ((intel_panel_use_ssc(dev_priv) && | |
4800 | dev_priv->lvds_ssc_freq == 100) || | |
4801 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4802 | factor = 25; | |
4803 | } else if (is_sdvo && is_tv) | |
4804 | factor = 20; | |
4805 | ||
4806 | if (clock.m1 < factor * clock.n) | |
4807 | fp |= FP_CB_TUNE; | |
4808 | } | |
4809 | ||
4810 | dpll = 0; | |
4811 | if (!HAS_PCH_SPLIT(dev)) | |
4812 | dpll = DPLL_VGA_MODE_DIS; | |
4813 | ||
4814 | if (!IS_GEN2(dev)) { | |
4815 | if (is_lvds) | |
4816 | dpll |= DPLLB_MODE_LVDS; | |
4817 | else | |
4818 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4819 | if (is_sdvo) { | |
4820 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4821 | if (pixel_multiplier > 1) { | |
4822 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4823 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4824 | else if (HAS_PCH_SPLIT(dev)) | |
4825 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
4826 | } | |
4827 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4828 | } | |
4829 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
4830 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4831 | ||
4832 | /* compute bitmask from p1 value */ | |
4833 | if (IS_PINEVIEW(dev)) | |
4834 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4835 | else { | |
4836 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4837 | /* also FPA1 */ | |
4838 | if (HAS_PCH_SPLIT(dev)) | |
4839 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4840 | if (IS_G4X(dev) && has_reduced_clock) | |
4841 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4842 | } | |
4843 | switch (clock.p2) { | |
4844 | case 5: | |
4845 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4846 | break; | |
4847 | case 7: | |
4848 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4849 | break; | |
4850 | case 10: | |
4851 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4852 | break; | |
4853 | case 14: | |
4854 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4855 | break; | |
4856 | } | |
4857 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) | |
4858 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4859 | } else { | |
4860 | if (is_lvds) { | |
4861 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4862 | } else { | |
4863 | if (clock.p1 == 2) | |
4864 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4865 | else | |
4866 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4867 | if (clock.p2 == 4) | |
4868 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4869 | } | |
4870 | } | |
4871 | ||
4872 | if (is_sdvo && is_tv) | |
4873 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4874 | else if (is_tv) | |
4875 | /* XXX: just matching BIOS for now */ | |
4876 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4877 | dpll |= 3; | |
4878 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4879 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4880 | else | |
4881 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4882 | ||
4883 | /* setup pipeconf */ | |
4884 | pipeconf = I915_READ(PIPECONF(pipe)); | |
4885 | ||
4886 | /* Set up the display plane register */ | |
4887 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4888 | ||
4889 | /* Ironlake's plane is forced to pipe, bit 24 is to | |
4890 | enable color space conversion */ | |
4891 | if (!HAS_PCH_SPLIT(dev)) { | |
4892 | if (pipe == 0) | |
4893 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4894 | else | |
4895 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4896 | } | |
4897 | ||
4898 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { | |
4899 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
4900 | * core speed. | |
4901 | * | |
4902 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4903 | * pipe == 0 check? | |
4904 | */ | |
4905 | if (mode->clock > | |
4906 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
4907 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
4908 | else | |
4909 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; | |
4910 | } | |
4911 | ||
4912 | if (!HAS_PCH_SPLIT(dev)) | |
4913 | dpll |= DPLL_VCO_ENABLE; | |
4914 | ||
4915 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
4916 | drm_mode_debug_printmodeline(mode); | |
4917 | ||
4918 | /* assign to Ironlake registers */ | |
4919 | if (HAS_PCH_SPLIT(dev)) { | |
4920 | fp_reg = PCH_FP0(pipe); | |
4921 | dpll_reg = PCH_DPLL(pipe); | |
4922 | } else { | |
4923 | fp_reg = FP0(pipe); | |
4924 | dpll_reg = DPLL(pipe); | |
4925 | } | |
4926 | ||
4927 | /* PCH eDP needs FDI, but CPU eDP does not */ | |
4928 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
4929 | I915_WRITE(fp_reg, fp); | |
4930 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
4931 | ||
4932 | POSTING_READ(dpll_reg); | |
4933 | udelay(150); | |
4934 | } | |
4935 | ||
4936 | /* enable transcoder DPLL */ | |
4937 | if (HAS_PCH_CPT(dev)) { | |
4938 | temp = I915_READ(PCH_DPLL_SEL); | |
4939 | switch (pipe) { | |
4940 | case 0: | |
4941 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
4942 | break; | |
4943 | case 1: | |
4944 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; | |
4945 | break; | |
4946 | case 2: | |
4947 | /* FIXME: manage transcoder PLLs? */ | |
4948 | temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL; | |
4949 | break; | |
4950 | default: | |
4951 | BUG(); | |
4952 | } | |
4953 | I915_WRITE(PCH_DPLL_SEL, temp); | |
4954 | ||
4955 | POSTING_READ(PCH_DPLL_SEL); | |
4956 | udelay(150); | |
4957 | } | |
4958 | ||
4959 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4960 | * This is an exception to the general rule that mode_set doesn't turn | |
4961 | * things on. | |
4962 | */ | |
4963 | if (is_lvds) { | |
4964 | reg = LVDS; | |
4965 | if (HAS_PCH_SPLIT(dev)) | |
4966 | reg = PCH_LVDS; | |
4967 | ||
4968 | temp = I915_READ(reg); | |
4969 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
4970 | if (pipe == 1) { | |
4971 | if (HAS_PCH_CPT(dev)) | |
4972 | temp |= PORT_TRANS_B_SEL_CPT; | |
4973 | else | |
4974 | temp |= LVDS_PIPEB_SELECT; | |
4975 | } else { | |
4976 | if (HAS_PCH_CPT(dev)) | |
4977 | temp &= ~PORT_TRANS_SEL_MASK; | |
4978 | else | |
4979 | temp &= ~LVDS_PIPEB_SELECT; | |
4980 | } | |
4981 | /* set the corresponsding LVDS_BORDER bit */ | |
4982 | temp |= dev_priv->lvds_border_bits; | |
4983 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
4984 | * set the DPLLs for dual-channel mode or not. | |
4985 | */ | |
4986 | if (clock.p2 == 7) | |
4987 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
4988 | else | |
4989 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
4990 | ||
4991 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4992 | * appropriately here, but we need to look more thoroughly into how | |
4993 | * panels behave in the two modes. | |
4994 | */ | |
4995 | /* set the dithering flag on non-PCH LVDS as needed */ | |
4996 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { | |
4997 | if (dev_priv->lvds_dither) | |
4998 | temp |= LVDS_ENABLE_DITHER; | |
4999 | else | |
5000 | temp &= ~LVDS_ENABLE_DITHER; | |
5001 | } | |
5002 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
5003 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5004 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5005 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5006 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5007 | != lvds_sync) { | |
5008 | char flags[2] = "-+"; | |
5009 | DRM_INFO("Changing LVDS panel from " | |
5010 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5011 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5012 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5013 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5014 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5015 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5016 | temp |= lvds_sync; | |
5017 | } | |
5018 | I915_WRITE(reg, temp); | |
5019 | } | |
5020 | ||
5021 | /* set the dithering flag and clear for anything other than a panel. */ | |
5022 | if (HAS_PCH_SPLIT(dev)) { | |
5023 | pipeconf &= ~PIPECONF_DITHER_EN; | |
5024 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5025 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
5026 | pipeconf |= PIPECONF_DITHER_EN; | |
5027 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
5028 | } | |
5029 | } | |
5030 | ||
5031 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5032 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
5033 | } else if (HAS_PCH_SPLIT(dev)) { | |
5034 | /* For non-DP output, clear any trans DP clock recovery setting.*/ | |
5035 | I915_WRITE(TRANSDATA_M1(pipe), 0); | |
5036 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5037 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5038 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
5039 | } | |
5040 | ||
5041 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5042 | I915_WRITE(dpll_reg, dpll); | |
5043 | ||
5044 | /* Wait for the clocks to stabilize. */ | |
5045 | POSTING_READ(dpll_reg); | |
5046 | udelay(150); | |
5047 | ||
5048 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { | |
5049 | temp = 0; | |
5050 | if (is_sdvo) { | |
5051 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5052 | if (temp > 1) | |
5053 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5054 | else | |
5055 | temp = 0; | |
5056 | } | |
5057 | I915_WRITE(DPLL_MD(pipe), temp); | |
5058 | } else { | |
5059 | /* The pixel multiplier can only be updated once the | |
5060 | * DPLL is enabled and the clocks are stable. | |
5061 | * | |
5062 | * So write it again. | |
5063 | */ | |
5064 | I915_WRITE(dpll_reg, dpll); | |
5065 | } | |
5066 | } | |
5067 | ||
5068 | intel_crtc->lowfreq_avail = false; | |
5069 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
5070 | I915_WRITE(fp_reg + 4, fp2); | |
5071 | intel_crtc->lowfreq_avail = true; | |
5072 | if (HAS_PIPE_CXSR(dev)) { | |
5073 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5074 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5075 | } | |
5076 | } else { | |
5077 | I915_WRITE(fp_reg + 4, fp); | |
5078 | if (HAS_PIPE_CXSR(dev)) { | |
5079 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
5080 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
5081 | } | |
5082 | } | |
5083 | ||
5084 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5085 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5086 | /* the chip adds 2 halflines automatically */ | |
5087 | adjusted_mode->crtc_vdisplay -= 1; | |
5088 | adjusted_mode->crtc_vtotal -= 1; | |
5089 | adjusted_mode->crtc_vblank_start -= 1; | |
5090 | adjusted_mode->crtc_vblank_end -= 1; | |
5091 | adjusted_mode->crtc_vsync_end -= 1; | |
5092 | adjusted_mode->crtc_vsync_start -= 1; | |
5093 | } else | |
5094 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5095 | ||
5096 | I915_WRITE(HTOTAL(pipe), | |
5097 | (adjusted_mode->crtc_hdisplay - 1) | | |
5098 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
5099 | I915_WRITE(HBLANK(pipe), | |
5100 | (adjusted_mode->crtc_hblank_start - 1) | | |
5101 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
5102 | I915_WRITE(HSYNC(pipe), | |
5103 | (adjusted_mode->crtc_hsync_start - 1) | | |
5104 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5105 | ||
5106 | I915_WRITE(VTOTAL(pipe), | |
5107 | (adjusted_mode->crtc_vdisplay - 1) | | |
5108 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
5109 | I915_WRITE(VBLANK(pipe), | |
5110 | (adjusted_mode->crtc_vblank_start - 1) | | |
5111 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
5112 | I915_WRITE(VSYNC(pipe), | |
5113 | (adjusted_mode->crtc_vsync_start - 1) | | |
5114 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5115 | ||
5116 | /* pipesrc and dspsize control the size that is scaled from, | |
5117 | * which should always be the user's requested size. | |
5118 | */ | |
5119 | if (!HAS_PCH_SPLIT(dev)) { | |
5120 | I915_WRITE(DSPSIZE(plane), | |
5121 | ((mode->vdisplay - 1) << 16) | | |
5122 | (mode->hdisplay - 1)); | |
5123 | I915_WRITE(DSPPOS(plane), 0); | |
5124 | } | |
5125 | I915_WRITE(PIPESRC(pipe), | |
5126 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
5127 | ||
5128 | if (HAS_PCH_SPLIT(dev)) { | |
5129 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); | |
5130 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
5131 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
5132 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
5133 | ||
5134 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5135 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
5136 | } | |
5137 | } | |
5138 | ||
5139 | I915_WRITE(PIPECONF(pipe), pipeconf); | |
5140 | POSTING_READ(PIPECONF(pipe)); | |
5141 | if (!HAS_PCH_SPLIT(dev)) | |
5142 | intel_enable_pipe(dev_priv, pipe, false); | |
5143 | ||
5144 | intel_wait_for_vblank(dev, pipe); | |
5145 | ||
5146 | if (IS_GEN5(dev)) { | |
5147 | /* enable address swizzle for tiling buffer */ | |
5148 | temp = I915_READ(DISP_ARB_CTL); | |
5149 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
5150 | } | |
5151 | ||
5152 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
5153 | POSTING_READ(DSPCNTR(plane)); | |
5154 | ||
5155 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5156 | ||
5157 | intel_update_watermarks(dev); | |
5158 | ||
f564048e EA |
5159 | return ret; |
5160 | } | |
5161 | ||
5162 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
5163 | struct drm_display_mode *mode, | |
5164 | struct drm_display_mode *adjusted_mode, | |
5165 | int x, int y, | |
5166 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5167 | { |
5168 | struct drm_device *dev = crtc->dev; | |
5169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5171 | int pipe = intel_crtc->pipe; | |
80824003 | 5172 | int plane = intel_crtc->plane; |
5eddb70b | 5173 | u32 fp_reg, dpll_reg; |
c751ce4f | 5174 | int refclk, num_connectors = 0; |
652c393a | 5175 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5176 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 5177 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 5178 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5179 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5180 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5181 | struct intel_encoder *encoder; |
d4906093 | 5182 | const intel_limit_t *limit; |
5c3b82e2 | 5183 | int ret; |
2c07245f | 5184 | struct fdi_m_n m_n = {0}; |
5eddb70b | 5185 | u32 reg, temp; |
aa9b500d | 5186 | u32 lvds_sync = 0; |
5eb08b69 | 5187 | int target_clock; |
79e53945 | 5188 | |
5eddb70b CW |
5189 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5190 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5191 | continue; |
5192 | ||
5eddb70b | 5193 | switch (encoder->type) { |
79e53945 JB |
5194 | case INTEL_OUTPUT_LVDS: |
5195 | is_lvds = true; | |
5196 | break; | |
5197 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5198 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5199 | is_sdvo = true; |
5eddb70b | 5200 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5201 | is_tv = true; |
79e53945 JB |
5202 | break; |
5203 | case INTEL_OUTPUT_DVO: | |
5204 | is_dvo = true; | |
5205 | break; | |
5206 | case INTEL_OUTPUT_TVOUT: | |
5207 | is_tv = true; | |
5208 | break; | |
5209 | case INTEL_OUTPUT_ANALOG: | |
5210 | is_crt = true; | |
5211 | break; | |
a4fc5ed6 KP |
5212 | case INTEL_OUTPUT_DISPLAYPORT: |
5213 | is_dp = true; | |
5214 | break; | |
32f9d658 | 5215 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5216 | has_edp_encoder = encoder; |
32f9d658 | 5217 | break; |
79e53945 | 5218 | } |
43565a06 | 5219 | |
c751ce4f | 5220 | num_connectors++; |
79e53945 JB |
5221 | } |
5222 | ||
a7615030 | 5223 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
43565a06 | 5224 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 5225 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 5226 | refclk / 1000); |
a6c45cf0 | 5227 | } else if (!IS_GEN2(dev)) { |
79e53945 | 5228 | refclk = 96000; |
1cb1b75e JB |
5229 | if (HAS_PCH_SPLIT(dev) && |
5230 | (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base))) | |
2c07245f | 5231 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
5232 | } else { |
5233 | refclk = 48000; | |
5234 | } | |
5235 | ||
d4906093 ML |
5236 | /* |
5237 | * Returns a set of divisors for the desired target clock with the given | |
5238 | * refclk, or FALSE. The returned values represent the clock equation: | |
5239 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5240 | */ | |
1b894b59 | 5241 | limit = intel_limit(crtc, refclk); |
d4906093 | 5242 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
5243 | if (!ok) { |
5244 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5245 | return -EINVAL; |
79e53945 JB |
5246 | } |
5247 | ||
cda4b7d3 | 5248 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5249 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5250 | |
ddc9003c ZY |
5251 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5252 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
5253 | dev_priv->lvds_downclock, |
5254 | refclk, | |
5255 | &reduced_clock); | |
18f9ed12 ZY |
5256 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
5257 | /* | |
5258 | * If the different P is found, it means that we can't | |
5259 | * switch the display clock by using the FP0/FP1. | |
5260 | * In such case we will disable the LVDS downclock | |
5261 | * feature. | |
5262 | */ | |
5263 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 5264 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
5265 | has_reduced_clock = 0; |
5266 | } | |
652c393a | 5267 | } |
7026d4ac ZW |
5268 | /* SDVO TV has fixed PLL values depend on its clock range, |
5269 | this mirrors vbios setting. */ | |
5270 | if (is_sdvo && is_tv) { | |
5271 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5272 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5273 | clock.p1 = 2; |
5274 | clock.p2 = 10; | |
5275 | clock.n = 3; | |
5276 | clock.m1 = 16; | |
5277 | clock.m2 = 8; | |
5278 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5279 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5280 | clock.p1 = 1; |
5281 | clock.p2 = 10; | |
5282 | clock.n = 6; | |
5283 | clock.m1 = 12; | |
5284 | clock.m2 = 8; | |
5285 | } | |
5286 | } | |
5287 | ||
2c07245f | 5288 | /* FDI link */ |
bad720ff | 5289 | if (HAS_PCH_SPLIT(dev)) { |
49078f7d | 5290 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
77ffb597 | 5291 | int lane = 0, link_bw, bpp; |
5c5313c8 | 5292 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
32f9d658 | 5293 | according to current link config */ |
858bc21f | 5294 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
5eb08b69 | 5295 | target_clock = mode->clock; |
8e647a27 CW |
5296 | intel_edp_link_config(has_edp_encoder, |
5297 | &lane, &link_bw); | |
32f9d658 | 5298 | } else { |
5c5313c8 | 5299 | /* [e]DP over FDI requires target mode clock |
32f9d658 | 5300 | instead of link clock */ |
5c5313c8 | 5301 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
32f9d658 ZW |
5302 | target_clock = mode->clock; |
5303 | else | |
5304 | target_clock = adjusted_mode->clock; | |
021357ac CW |
5305 | |
5306 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5307 | * each output octet as 10 bits. The actual frequency | |
5308 | * is stored as a divider into a 100MHz clock, and the | |
5309 | * mode pixel clock is stored in units of 1KHz. | |
5310 | * Hence the bw of each lane in terms of the mode signal | |
5311 | * is: | |
5312 | */ | |
5313 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 5314 | } |
58a27471 ZW |
5315 | |
5316 | /* determine panel color depth */ | |
5eddb70b | 5317 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
5318 | temp &= ~PIPE_BPC_MASK; |
5319 | if (is_lvds) { | |
e5a95eb7 | 5320 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 5321 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
5322 | temp |= PIPE_8BPC; |
5323 | else | |
5324 | temp |= PIPE_6BPC; | |
1d850362 | 5325 | } else if (has_edp_encoder) { |
5ceb0f9b | 5326 | switch (dev_priv->edp.bpp/3) { |
885a5fb5 ZW |
5327 | case 8: |
5328 | temp |= PIPE_8BPC; | |
5329 | break; | |
5330 | case 10: | |
5331 | temp |= PIPE_10BPC; | |
5332 | break; | |
5333 | case 6: | |
5334 | temp |= PIPE_6BPC; | |
5335 | break; | |
5336 | case 12: | |
5337 | temp |= PIPE_12BPC; | |
5338 | break; | |
5339 | } | |
e5a95eb7 ZY |
5340 | } else |
5341 | temp |= PIPE_8BPC; | |
5eddb70b | 5342 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
5343 | |
5344 | switch (temp & PIPE_BPC_MASK) { | |
5345 | case PIPE_8BPC: | |
5346 | bpp = 24; | |
5347 | break; | |
5348 | case PIPE_10BPC: | |
5349 | bpp = 30; | |
5350 | break; | |
5351 | case PIPE_6BPC: | |
5352 | bpp = 18; | |
5353 | break; | |
5354 | case PIPE_12BPC: | |
5355 | bpp = 36; | |
5356 | break; | |
5357 | default: | |
5358 | DRM_ERROR("unknown pipe bpc value\n"); | |
5359 | bpp = 24; | |
5360 | } | |
5361 | ||
77ffb597 AJ |
5362 | if (!lane) { |
5363 | /* | |
5364 | * Account for spread spectrum to avoid | |
5365 | * oversubscribing the link. Max center spread | |
5366 | * is 2.5%; use 5% for safety's sake. | |
5367 | */ | |
5368 | u32 bps = target_clock * bpp * 21 / 20; | |
5369 | lane = bps / (link_bw * 8) + 1; | |
5370 | } | |
5371 | ||
5372 | intel_crtc->fdi_lanes = lane; | |
5373 | ||
49078f7d CW |
5374 | if (pixel_multiplier > 1) |
5375 | link_bw *= pixel_multiplier; | |
f2b115e6 | 5376 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 5377 | } |
2c07245f | 5378 | |
c038e51e ZW |
5379 | /* Ironlake: try to setup display ref clock before DPLL |
5380 | * enabling. This is only under driver's control after | |
5381 | * PCH B stepping, previous chipset stepping should be | |
5382 | * ignoring this setting. | |
5383 | */ | |
fc9a2228 CW |
5384 | if (HAS_PCH_SPLIT(dev)) { |
5385 | temp = I915_READ(PCH_DREF_CONTROL); | |
5386 | /* Always enable nonspread source */ | |
5387 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5388 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5389 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5390 | temp |= DREF_SSC_SOURCE_ENABLE; | |
5391 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5392 | ||
5393 | POSTING_READ(PCH_DREF_CONTROL); | |
5394 | udelay(200); | |
5395 | ||
5396 | if (has_edp_encoder) { | |
5397 | if (intel_panel_use_ssc(dev_priv)) { | |
5398 | temp |= DREF_SSC1_ENABLE; | |
5399 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5400 | ||
5401 | POSTING_READ(PCH_DREF_CONTROL); | |
5402 | udelay(200); | |
5403 | } | |
5404 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5405 | ||
5406 | /* Enable CPU source on CPU attached eDP */ | |
5407 | if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5408 | if (intel_panel_use_ssc(dev_priv)) | |
5409 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5410 | else | |
5411 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5412 | } else { | |
5413 | /* Enable SSC on PCH eDP if needed */ | |
5414 | if (intel_panel_use_ssc(dev_priv)) { | |
5415 | DRM_ERROR("enabling SSC on PCH\n"); | |
5416 | temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; | |
5417 | } | |
5418 | } | |
5419 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5420 | POSTING_READ(PCH_DREF_CONTROL); | |
5421 | udelay(200); | |
5422 | } | |
5423 | } | |
c038e51e | 5424 | |
f2b115e6 | 5425 | if (IS_PINEVIEW(dev)) { |
2177832f | 5426 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
5427 | if (has_reduced_clock) |
5428 | fp2 = (1 << reduced_clock.n) << 16 | | |
5429 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
5430 | } else { | |
2177832f | 5431 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
5432 | if (has_reduced_clock) |
5433 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5434 | reduced_clock.m2; | |
5435 | } | |
79e53945 | 5436 | |
c1858123 CW |
5437 | /* Enable autotuning of the PLL clock (if permissible) */ |
5438 | if (HAS_PCH_SPLIT(dev)) { | |
5439 | int factor = 21; | |
5440 | ||
5441 | if (is_lvds) { | |
a7615030 | 5442 | if ((intel_panel_use_ssc(dev_priv) && |
c1858123 CW |
5443 | dev_priv->lvds_ssc_freq == 100) || |
5444 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5445 | factor = 25; | |
5446 | } else if (is_sdvo && is_tv) | |
5447 | factor = 20; | |
5448 | ||
5449 | if (clock.m1 < factor * clock.n) | |
5450 | fp |= FP_CB_TUNE; | |
5451 | } | |
5452 | ||
5eddb70b | 5453 | dpll = 0; |
bad720ff | 5454 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
5455 | dpll = DPLL_VGA_MODE_DIS; |
5456 | ||
a6c45cf0 | 5457 | if (!IS_GEN2(dev)) { |
79e53945 JB |
5458 | if (is_lvds) |
5459 | dpll |= DPLLB_MODE_LVDS; | |
5460 | else | |
5461 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5462 | if (is_sdvo) { | |
6c9547ff CW |
5463 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5464 | if (pixel_multiplier > 1) { | |
5465 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
5466 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
5467 | else if (HAS_PCH_SPLIT(dev)) | |
5468 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
5469 | } | |
79e53945 | 5470 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5471 | } |
83240120 | 5472 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
a4fc5ed6 | 5473 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
5474 | |
5475 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
5476 | if (IS_PINEVIEW(dev)) |
5477 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 5478 | else { |
2177832f | 5479 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 5480 | /* also FPA1 */ |
bad720ff | 5481 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 5482 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
5483 | if (IS_G4X(dev) && has_reduced_clock) |
5484 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 5485 | } |
79e53945 JB |
5486 | switch (clock.p2) { |
5487 | case 5: | |
5488 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5489 | break; | |
5490 | case 7: | |
5491 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5492 | break; | |
5493 | case 10: | |
5494 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5495 | break; | |
5496 | case 14: | |
5497 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5498 | break; | |
5499 | } | |
a6c45cf0 | 5500 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
5501 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5502 | } else { | |
5503 | if (is_lvds) { | |
5504 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5505 | } else { | |
5506 | if (clock.p1 == 2) | |
5507 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5508 | else | |
5509 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5510 | if (clock.p2 == 4) | |
5511 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5512 | } | |
5513 | } | |
5514 | ||
43565a06 KH |
5515 | if (is_sdvo && is_tv) |
5516 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5517 | else if (is_tv) | |
79e53945 | 5518 | /* XXX: just matching BIOS for now */ |
43565a06 | 5519 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5520 | dpll |= 3; |
a7615030 | 5521 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5522 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5523 | else |
5524 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5525 | ||
5526 | /* setup pipeconf */ | |
5eddb70b | 5527 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5528 | |
5529 | /* Set up the display plane register */ | |
5530 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5531 | ||
f2b115e6 | 5532 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 5533 | enable color space conversion */ |
bad720ff | 5534 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 5535 | if (pipe == 0) |
80824003 | 5536 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
5537 | else |
5538 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5539 | } | |
79e53945 | 5540 | |
a6c45cf0 | 5541 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
5542 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
5543 | * core speed. | |
5544 | * | |
5545 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
5546 | * pipe == 0 check? | |
5547 | */ | |
e70236a8 JB |
5548 | if (mode->clock > |
5549 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 5550 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 5551 | else |
5eddb70b | 5552 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
5553 | } |
5554 | ||
b24e7179 | 5555 | if (!HAS_PCH_SPLIT(dev)) |
65993d64 | 5556 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 5557 | |
28c97730 | 5558 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5559 | drm_mode_debug_printmodeline(mode); |
5560 | ||
f2b115e6 | 5561 | /* assign to Ironlake registers */ |
bad720ff | 5562 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
5563 | fp_reg = PCH_FP0(pipe); |
5564 | dpll_reg = PCH_DPLL(pipe); | |
5565 | } else { | |
5566 | fp_reg = FP0(pipe); | |
5567 | dpll_reg = DPLL(pipe); | |
2c07245f | 5568 | } |
79e53945 | 5569 | |
5c5313c8 JB |
5570 | /* PCH eDP needs FDI, but CPU eDP does not */ |
5571 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
79e53945 JB |
5572 | I915_WRITE(fp_reg, fp); |
5573 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
5574 | |
5575 | POSTING_READ(dpll_reg); | |
79e53945 JB |
5576 | udelay(150); |
5577 | } | |
5578 | ||
8db9d77b ZW |
5579 | /* enable transcoder DPLL */ |
5580 | if (HAS_PCH_CPT(dev)) { | |
5581 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
5582 | switch (pipe) { |
5583 | case 0: | |
5eddb70b | 5584 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; |
9db4a9c7 JB |
5585 | break; |
5586 | case 1: | |
5eddb70b | 5587 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
9db4a9c7 JB |
5588 | break; |
5589 | case 2: | |
5590 | /* FIXME: manage transcoder PLLs? */ | |
5591 | temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL; | |
5592 | break; | |
5593 | default: | |
5594 | BUG(); | |
5595 | } | |
8db9d77b | 5596 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
5597 | |
5598 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
5599 | udelay(150); |
5600 | } | |
5601 | ||
79e53945 JB |
5602 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5603 | * This is an exception to the general rule that mode_set doesn't turn | |
5604 | * things on. | |
5605 | */ | |
5606 | if (is_lvds) { | |
5eddb70b | 5607 | reg = LVDS; |
bad720ff | 5608 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 5609 | reg = PCH_LVDS; |
541998a1 | 5610 | |
5eddb70b CW |
5611 | temp = I915_READ(reg); |
5612 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
5613 | if (pipe == 1) { |
5614 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 5615 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 5616 | else |
5eddb70b | 5617 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
5618 | } else { |
5619 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 5620 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 5621 | else |
5eddb70b | 5622 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5623 | } |
a3e17eb8 | 5624 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5625 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5626 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5627 | * set the DPLLs for dual-channel mode or not. | |
5628 | */ | |
5629 | if (clock.p2 == 7) | |
5eddb70b | 5630 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5631 | else |
5eddb70b | 5632 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5633 | |
5634 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5635 | * appropriately here, but we need to look more thoroughly into how | |
5636 | * panels behave in the two modes. | |
5637 | */ | |
434ed097 | 5638 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 5639 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 5640 | if (dev_priv->lvds_dither) |
5eddb70b | 5641 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 5642 | else |
5eddb70b | 5643 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 5644 | } |
aa9b500d BF |
5645 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5646 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5647 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5648 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5649 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5650 | != lvds_sync) { | |
5651 | char flags[2] = "-+"; | |
5652 | DRM_INFO("Changing LVDS panel from " | |
5653 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5654 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5655 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5656 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5657 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5658 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5659 | temp |= lvds_sync; | |
5660 | } | |
5eddb70b | 5661 | I915_WRITE(reg, temp); |
79e53945 | 5662 | } |
434ed097 JB |
5663 | |
5664 | /* set the dithering flag and clear for anything other than a panel. */ | |
5665 | if (HAS_PCH_SPLIT(dev)) { | |
5666 | pipeconf &= ~PIPECONF_DITHER_EN; | |
5667 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5668 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
5669 | pipeconf |= PIPECONF_DITHER_EN; | |
5670 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
5671 | } | |
5672 | } | |
5673 | ||
5c5313c8 | 5674 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5675 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5c5313c8 | 5676 | } else if (HAS_PCH_SPLIT(dev)) { |
8db9d77b | 5677 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5678 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5679 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5680 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5681 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5682 | } |
79e53945 | 5683 | |
5c5313c8 | 5684 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
79e53945 | 5685 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 5686 | |
32f9d658 | 5687 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 5688 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
5689 | udelay(150); |
5690 | ||
a6c45cf0 | 5691 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 5692 | temp = 0; |
bb66c512 | 5693 | if (is_sdvo) { |
5eddb70b CW |
5694 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
5695 | if (temp > 1) | |
5696 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 5697 | else |
5eddb70b CW |
5698 | temp = 0; |
5699 | } | |
5700 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 | 5701 | } else { |
a589b9f4 CW |
5702 | /* The pixel multiplier can only be updated once the |
5703 | * DPLL is enabled and the clocks are stable. | |
5704 | * | |
5705 | * So write it again. | |
5706 | */ | |
32f9d658 ZW |
5707 | I915_WRITE(dpll_reg, dpll); |
5708 | } | |
79e53945 | 5709 | } |
79e53945 | 5710 | |
5eddb70b | 5711 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
5712 | if (is_lvds && has_reduced_clock && i915_powersave) { |
5713 | I915_WRITE(fp_reg + 4, fp2); | |
5714 | intel_crtc->lowfreq_avail = true; | |
5715 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 5716 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
5717 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5718 | } | |
5719 | } else { | |
5720 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 5721 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 5722 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5723 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5724 | } | |
5725 | } | |
5726 | ||
734b4157 KH |
5727 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5728 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5729 | /* the chip adds 2 halflines automatically */ | |
5730 | adjusted_mode->crtc_vdisplay -= 1; | |
5731 | adjusted_mode->crtc_vtotal -= 1; | |
5732 | adjusted_mode->crtc_vblank_start -= 1; | |
5733 | adjusted_mode->crtc_vblank_end -= 1; | |
5734 | adjusted_mode->crtc_vsync_end -= 1; | |
5735 | adjusted_mode->crtc_vsync_start -= 1; | |
5736 | } else | |
5737 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5738 | ||
5eddb70b CW |
5739 | I915_WRITE(HTOTAL(pipe), |
5740 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5741 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5742 | I915_WRITE(HBLANK(pipe), |
5743 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5744 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5745 | I915_WRITE(HSYNC(pipe), |
5746 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5747 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5748 | |
5749 | I915_WRITE(VTOTAL(pipe), | |
5750 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5751 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5752 | I915_WRITE(VBLANK(pipe), |
5753 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5754 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5755 | I915_WRITE(VSYNC(pipe), |
5756 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5757 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5758 | |
5759 | /* pipesrc and dspsize control the size that is scaled from, | |
5760 | * which should always be the user's requested size. | |
79e53945 | 5761 | */ |
bad720ff | 5762 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
5763 | I915_WRITE(DSPSIZE(plane), |
5764 | ((mode->vdisplay - 1) << 16) | | |
5765 | (mode->hdisplay - 1)); | |
5766 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 5767 | } |
5eddb70b CW |
5768 | I915_WRITE(PIPESRC(pipe), |
5769 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5770 | |
bad720ff | 5771 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
5772 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5773 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
5774 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
5775 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 5776 | |
5c5313c8 | 5777 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
f2b115e6 | 5778 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 | 5779 | } |
2c07245f ZW |
5780 | } |
5781 | ||
5eddb70b CW |
5782 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5783 | POSTING_READ(PIPECONF(pipe)); | |
b24e7179 | 5784 | if (!HAS_PCH_SPLIT(dev)) |
040484af | 5785 | intel_enable_pipe(dev_priv, pipe, false); |
79e53945 | 5786 | |
9d0498a2 | 5787 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5788 | |
f00a3ddf | 5789 | if (IS_GEN5(dev)) { |
553bd149 ZW |
5790 | /* enable address swizzle for tiling buffer */ |
5791 | temp = I915_READ(DISP_ARB_CTL); | |
5792 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
5793 | } | |
5794 | ||
5eddb70b | 5795 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 5796 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5797 | |
5c3b82e2 | 5798 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
5799 | |
5800 | intel_update_watermarks(dev); | |
5801 | ||
1f803ee5 | 5802 | return ret; |
79e53945 JB |
5803 | } |
5804 | ||
f564048e EA |
5805 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5806 | struct drm_display_mode *mode, | |
5807 | struct drm_display_mode *adjusted_mode, | |
5808 | int x, int y, | |
5809 | struct drm_framebuffer *old_fb) | |
5810 | { | |
5811 | struct drm_device *dev = crtc->dev; | |
5812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
5813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5814 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5815 | int ret; |
5816 | ||
0b701d27 EA |
5817 | drm_vblank_pre_modeset(dev, pipe); |
5818 | ||
f564048e EA |
5819 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
5820 | x, y, old_fb); | |
5821 | ||
0b701d27 EA |
5822 | drm_vblank_post_modeset(dev, pipe); |
5823 | ||
f564048e EA |
5824 | return ret; |
5825 | } | |
5826 | ||
79e53945 JB |
5827 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5828 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5829 | { | |
5830 | struct drm_device *dev = crtc->dev; | |
5831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5833 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5834 | int i; |
5835 | ||
5836 | /* The clocks have to be on to load the palette. */ | |
5837 | if (!crtc->enabled) | |
5838 | return; | |
5839 | ||
f2b115e6 | 5840 | /* use legacy palette for Ironlake */ |
bad720ff | 5841 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5842 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5843 | |
79e53945 JB |
5844 | for (i = 0; i < 256; i++) { |
5845 | I915_WRITE(palreg + 4 * i, | |
5846 | (intel_crtc->lut_r[i] << 16) | | |
5847 | (intel_crtc->lut_g[i] << 8) | | |
5848 | intel_crtc->lut_b[i]); | |
5849 | } | |
5850 | } | |
5851 | ||
560b85bb CW |
5852 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5853 | { | |
5854 | struct drm_device *dev = crtc->dev; | |
5855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5857 | bool visible = base != 0; | |
5858 | u32 cntl; | |
5859 | ||
5860 | if (intel_crtc->cursor_visible == visible) | |
5861 | return; | |
5862 | ||
9db4a9c7 | 5863 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5864 | if (visible) { |
5865 | /* On these chipsets we can only modify the base whilst | |
5866 | * the cursor is disabled. | |
5867 | */ | |
9db4a9c7 | 5868 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5869 | |
5870 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5871 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5872 | cntl |= CURSOR_ENABLE | | |
5873 | CURSOR_GAMMA_ENABLE | | |
5874 | CURSOR_FORMAT_ARGB; | |
5875 | } else | |
5876 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5877 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5878 | |
5879 | intel_crtc->cursor_visible = visible; | |
5880 | } | |
5881 | ||
5882 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5883 | { | |
5884 | struct drm_device *dev = crtc->dev; | |
5885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5887 | int pipe = intel_crtc->pipe; | |
5888 | bool visible = base != 0; | |
5889 | ||
5890 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5891 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5892 | if (base) { |
5893 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5894 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5895 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5896 | } else { | |
5897 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5898 | cntl |= CURSOR_MODE_DISABLE; | |
5899 | } | |
9db4a9c7 | 5900 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5901 | |
5902 | intel_crtc->cursor_visible = visible; | |
5903 | } | |
5904 | /* and commit changes on next vblank */ | |
9db4a9c7 | 5905 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
5906 | } |
5907 | ||
cda4b7d3 | 5908 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
5909 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5910 | bool on) | |
cda4b7d3 CW |
5911 | { |
5912 | struct drm_device *dev = crtc->dev; | |
5913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5915 | int pipe = intel_crtc->pipe; | |
5916 | int x = intel_crtc->cursor_x; | |
5917 | int y = intel_crtc->cursor_y; | |
560b85bb | 5918 | u32 base, pos; |
cda4b7d3 CW |
5919 | bool visible; |
5920 | ||
5921 | pos = 0; | |
5922 | ||
6b383a7f | 5923 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
5924 | base = intel_crtc->cursor_addr; |
5925 | if (x > (int) crtc->fb->width) | |
5926 | base = 0; | |
5927 | ||
5928 | if (y > (int) crtc->fb->height) | |
5929 | base = 0; | |
5930 | } else | |
5931 | base = 0; | |
5932 | ||
5933 | if (x < 0) { | |
5934 | if (x + intel_crtc->cursor_width < 0) | |
5935 | base = 0; | |
5936 | ||
5937 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
5938 | x = -x; | |
5939 | } | |
5940 | pos |= x << CURSOR_X_SHIFT; | |
5941 | ||
5942 | if (y < 0) { | |
5943 | if (y + intel_crtc->cursor_height < 0) | |
5944 | base = 0; | |
5945 | ||
5946 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
5947 | y = -y; | |
5948 | } | |
5949 | pos |= y << CURSOR_Y_SHIFT; | |
5950 | ||
5951 | visible = base != 0; | |
560b85bb | 5952 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
5953 | return; |
5954 | ||
9db4a9c7 | 5955 | I915_WRITE(CURPOS(pipe), pos); |
560b85bb CW |
5956 | if (IS_845G(dev) || IS_I865G(dev)) |
5957 | i845_update_cursor(crtc, base); | |
5958 | else | |
5959 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
5960 | |
5961 | if (visible) | |
5962 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
5963 | } | |
5964 | ||
79e53945 | 5965 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 5966 | struct drm_file *file, |
79e53945 JB |
5967 | uint32_t handle, |
5968 | uint32_t width, uint32_t height) | |
5969 | { | |
5970 | struct drm_device *dev = crtc->dev; | |
5971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 5973 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 5974 | uint32_t addr; |
3f8bc370 | 5975 | int ret; |
79e53945 | 5976 | |
28c97730 | 5977 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
5978 | |
5979 | /* if we want to turn off the cursor ignore width and height */ | |
5980 | if (!handle) { | |
28c97730 | 5981 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 5982 | addr = 0; |
05394f39 | 5983 | obj = NULL; |
5004417d | 5984 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 5985 | goto finish; |
79e53945 JB |
5986 | } |
5987 | ||
5988 | /* Currently we only support 64x64 cursors */ | |
5989 | if (width != 64 || height != 64) { | |
5990 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
5991 | return -EINVAL; | |
5992 | } | |
5993 | ||
05394f39 | 5994 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 5995 | if (&obj->base == NULL) |
79e53945 JB |
5996 | return -ENOENT; |
5997 | ||
05394f39 | 5998 | if (obj->base.size < width * height * 4) { |
79e53945 | 5999 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6000 | ret = -ENOMEM; |
6001 | goto fail; | |
79e53945 JB |
6002 | } |
6003 | ||
71acb5eb | 6004 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6005 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6006 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6007 | if (obj->tiling_mode) { |
6008 | DRM_ERROR("cursor cannot be tiled\n"); | |
6009 | ret = -EINVAL; | |
6010 | goto fail_locked; | |
6011 | } | |
6012 | ||
05394f39 | 6013 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
71acb5eb DA |
6014 | if (ret) { |
6015 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 6016 | goto fail_locked; |
71acb5eb | 6017 | } |
e7b526bb | 6018 | |
05394f39 | 6019 | ret = i915_gem_object_set_to_gtt_domain(obj, 0); |
e7b526bb CW |
6020 | if (ret) { |
6021 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
6022 | goto fail_unpin; | |
6023 | } | |
6024 | ||
d9e86c0e CW |
6025 | ret = i915_gem_object_put_fence(obj); |
6026 | if (ret) { | |
6027 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
6028 | goto fail_unpin; | |
6029 | } | |
6030 | ||
05394f39 | 6031 | addr = obj->gtt_offset; |
71acb5eb | 6032 | } else { |
6eeefaf3 | 6033 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6034 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6035 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6036 | align); | |
71acb5eb DA |
6037 | if (ret) { |
6038 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6039 | goto fail_locked; |
71acb5eb | 6040 | } |
05394f39 | 6041 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6042 | } |
6043 | ||
a6c45cf0 | 6044 | if (IS_GEN2(dev)) |
14b60391 JB |
6045 | I915_WRITE(CURSIZE, (height << 12) | width); |
6046 | ||
3f8bc370 | 6047 | finish: |
3f8bc370 | 6048 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6049 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6050 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6051 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6052 | } else | |
6053 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6054 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6055 | } |
80824003 | 6056 | |
7f9872e0 | 6057 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6058 | |
6059 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6060 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6061 | intel_crtc->cursor_width = width; |
6062 | intel_crtc->cursor_height = height; | |
6063 | ||
6b383a7f | 6064 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6065 | |
79e53945 | 6066 | return 0; |
e7b526bb | 6067 | fail_unpin: |
05394f39 | 6068 | i915_gem_object_unpin(obj); |
7f9872e0 | 6069 | fail_locked: |
34b8686e | 6070 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6071 | fail: |
05394f39 | 6072 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6073 | return ret; |
79e53945 JB |
6074 | } |
6075 | ||
6076 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6077 | { | |
79e53945 | 6078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6079 | |
cda4b7d3 CW |
6080 | intel_crtc->cursor_x = x; |
6081 | intel_crtc->cursor_y = y; | |
652c393a | 6082 | |
6b383a7f | 6083 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6084 | |
6085 | return 0; | |
6086 | } | |
6087 | ||
6088 | /** Sets the color ramps on behalf of RandR */ | |
6089 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6090 | u16 blue, int regno) | |
6091 | { | |
6092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6093 | ||
6094 | intel_crtc->lut_r[regno] = red >> 8; | |
6095 | intel_crtc->lut_g[regno] = green >> 8; | |
6096 | intel_crtc->lut_b[regno] = blue >> 8; | |
6097 | } | |
6098 | ||
b8c00ac5 DA |
6099 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6100 | u16 *blue, int regno) | |
6101 | { | |
6102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6103 | ||
6104 | *red = intel_crtc->lut_r[regno] << 8; | |
6105 | *green = intel_crtc->lut_g[regno] << 8; | |
6106 | *blue = intel_crtc->lut_b[regno] << 8; | |
6107 | } | |
6108 | ||
79e53945 | 6109 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6110 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6111 | { |
7203425a | 6112 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6113 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6114 | |
7203425a | 6115 | for (i = start; i < end; i++) { |
79e53945 JB |
6116 | intel_crtc->lut_r[i] = red[i] >> 8; |
6117 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6118 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6119 | } | |
6120 | ||
6121 | intel_crtc_load_lut(crtc); | |
6122 | } | |
6123 | ||
6124 | /** | |
6125 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6126 | * detection. | |
6127 | * | |
6128 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6129 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6130 | * |
c751ce4f | 6131 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6132 | * configured for it. In the future, it could choose to temporarily disable |
6133 | * some outputs to free up a pipe for its use. | |
6134 | * | |
6135 | * \return crtc, or NULL if no pipes are available. | |
6136 | */ | |
6137 | ||
6138 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6139 | static struct drm_display_mode load_detect_mode = { | |
6140 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6141 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6142 | }; | |
6143 | ||
d2dff872 CW |
6144 | static struct drm_framebuffer * |
6145 | intel_framebuffer_create(struct drm_device *dev, | |
6146 | struct drm_mode_fb_cmd *mode_cmd, | |
6147 | struct drm_i915_gem_object *obj) | |
6148 | { | |
6149 | struct intel_framebuffer *intel_fb; | |
6150 | int ret; | |
6151 | ||
6152 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6153 | if (!intel_fb) { | |
6154 | drm_gem_object_unreference_unlocked(&obj->base); | |
6155 | return ERR_PTR(-ENOMEM); | |
6156 | } | |
6157 | ||
6158 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6159 | if (ret) { | |
6160 | drm_gem_object_unreference_unlocked(&obj->base); | |
6161 | kfree(intel_fb); | |
6162 | return ERR_PTR(ret); | |
6163 | } | |
6164 | ||
6165 | return &intel_fb->base; | |
6166 | } | |
6167 | ||
6168 | static u32 | |
6169 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6170 | { | |
6171 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6172 | return ALIGN(pitch, 64); | |
6173 | } | |
6174 | ||
6175 | static u32 | |
6176 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6177 | { | |
6178 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6179 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6180 | } | |
6181 | ||
6182 | static struct drm_framebuffer * | |
6183 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6184 | struct drm_display_mode *mode, | |
6185 | int depth, int bpp) | |
6186 | { | |
6187 | struct drm_i915_gem_object *obj; | |
6188 | struct drm_mode_fb_cmd mode_cmd; | |
6189 | ||
6190 | obj = i915_gem_alloc_object(dev, | |
6191 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6192 | if (obj == NULL) | |
6193 | return ERR_PTR(-ENOMEM); | |
6194 | ||
6195 | mode_cmd.width = mode->hdisplay; | |
6196 | mode_cmd.height = mode->vdisplay; | |
6197 | mode_cmd.depth = depth; | |
6198 | mode_cmd.bpp = bpp; | |
6199 | mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); | |
6200 | ||
6201 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6202 | } | |
6203 | ||
6204 | static struct drm_framebuffer * | |
6205 | mode_fits_in_fbdev(struct drm_device *dev, | |
6206 | struct drm_display_mode *mode) | |
6207 | { | |
6208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6209 | struct drm_i915_gem_object *obj; | |
6210 | struct drm_framebuffer *fb; | |
6211 | ||
6212 | if (dev_priv->fbdev == NULL) | |
6213 | return NULL; | |
6214 | ||
6215 | obj = dev_priv->fbdev->ifb.obj; | |
6216 | if (obj == NULL) | |
6217 | return NULL; | |
6218 | ||
6219 | fb = &dev_priv->fbdev->ifb.base; | |
6220 | if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay, | |
6221 | fb->bits_per_pixel)) | |
6222 | return NULL; | |
6223 | ||
6224 | if (obj->base.size < mode->vdisplay * fb->pitch) | |
6225 | return NULL; | |
6226 | ||
6227 | return fb; | |
6228 | } | |
6229 | ||
7173188d CW |
6230 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6231 | struct drm_connector *connector, | |
6232 | struct drm_display_mode *mode, | |
8261b191 | 6233 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6234 | { |
6235 | struct intel_crtc *intel_crtc; | |
6236 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6237 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6238 | struct drm_crtc *crtc = NULL; |
6239 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6240 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6241 | int i = -1; |
6242 | ||
d2dff872 CW |
6243 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6244 | connector->base.id, drm_get_connector_name(connector), | |
6245 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6246 | ||
79e53945 JB |
6247 | /* |
6248 | * Algorithm gets a little messy: | |
7a5e4805 | 6249 | * |
79e53945 JB |
6250 | * - if the connector already has an assigned crtc, use it (but make |
6251 | * sure it's on first) | |
7a5e4805 | 6252 | * |
79e53945 JB |
6253 | * - try to find the first unused crtc that can drive this connector, |
6254 | * and use that if we find one | |
79e53945 JB |
6255 | */ |
6256 | ||
6257 | /* See if we already have a CRTC for this connector */ | |
6258 | if (encoder->crtc) { | |
6259 | crtc = encoder->crtc; | |
8261b191 | 6260 | |
79e53945 | 6261 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6262 | old->dpms_mode = intel_crtc->dpms_mode; |
6263 | old->load_detect_temp = false; | |
6264 | ||
6265 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6266 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6267 | struct drm_encoder_helper_funcs *encoder_funcs; |
6268 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6269 | ||
79e53945 JB |
6270 | crtc_funcs = crtc->helper_private; |
6271 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6272 | |
6273 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6274 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6275 | } | |
8261b191 | 6276 | |
7173188d | 6277 | return true; |
79e53945 JB |
6278 | } |
6279 | ||
6280 | /* Find an unused one (if possible) */ | |
6281 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6282 | i++; | |
6283 | if (!(encoder->possible_crtcs & (1 << i))) | |
6284 | continue; | |
6285 | if (!possible_crtc->enabled) { | |
6286 | crtc = possible_crtc; | |
6287 | break; | |
6288 | } | |
79e53945 JB |
6289 | } |
6290 | ||
6291 | /* | |
6292 | * If we didn't find an unused CRTC, don't use any. | |
6293 | */ | |
6294 | if (!crtc) { | |
7173188d CW |
6295 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6296 | return false; | |
79e53945 JB |
6297 | } |
6298 | ||
6299 | encoder->crtc = crtc; | |
c1c43977 | 6300 | connector->encoder = encoder; |
79e53945 JB |
6301 | |
6302 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6303 | old->dpms_mode = intel_crtc->dpms_mode; |
6304 | old->load_detect_temp = true; | |
d2dff872 | 6305 | old->release_fb = NULL; |
79e53945 | 6306 | |
6492711d CW |
6307 | if (!mode) |
6308 | mode = &load_detect_mode; | |
79e53945 | 6309 | |
d2dff872 CW |
6310 | old_fb = crtc->fb; |
6311 | ||
6312 | /* We need a framebuffer large enough to accommodate all accesses | |
6313 | * that the plane may generate whilst we perform load detection. | |
6314 | * We can not rely on the fbcon either being present (we get called | |
6315 | * during its initialisation to detect all boot displays, or it may | |
6316 | * not even exist) or that it is large enough to satisfy the | |
6317 | * requested mode. | |
6318 | */ | |
6319 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6320 | if (crtc->fb == NULL) { | |
6321 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6322 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6323 | old->release_fb = crtc->fb; | |
6324 | } else | |
6325 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6326 | if (IS_ERR(crtc->fb)) { | |
6327 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6328 | crtc->fb = old_fb; | |
6329 | return false; | |
6330 | } | |
6331 | ||
6332 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { | |
6492711d | 6333 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6334 | if (old->release_fb) |
6335 | old->release_fb->funcs->destroy(old->release_fb); | |
6336 | crtc->fb = old_fb; | |
6492711d | 6337 | return false; |
79e53945 | 6338 | } |
7173188d | 6339 | |
79e53945 | 6340 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6341 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6342 | |
7173188d | 6343 | return true; |
79e53945 JB |
6344 | } |
6345 | ||
c1c43977 | 6346 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6347 | struct drm_connector *connector, |
6348 | struct intel_load_detect_pipe *old) | |
79e53945 | 6349 | { |
4ef69c7a | 6350 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6351 | struct drm_device *dev = encoder->dev; |
6352 | struct drm_crtc *crtc = encoder->crtc; | |
6353 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6354 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6355 | ||
d2dff872 CW |
6356 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6357 | connector->base.id, drm_get_connector_name(connector), | |
6358 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6359 | ||
8261b191 | 6360 | if (old->load_detect_temp) { |
c1c43977 | 6361 | connector->encoder = NULL; |
79e53945 | 6362 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6363 | |
6364 | if (old->release_fb) | |
6365 | old->release_fb->funcs->destroy(old->release_fb); | |
6366 | ||
0622a53c | 6367 | return; |
79e53945 JB |
6368 | } |
6369 | ||
c751ce4f | 6370 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6371 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6372 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6373 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6374 | } |
6375 | } | |
6376 | ||
6377 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6378 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6379 | { | |
6380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6381 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6382 | int pipe = intel_crtc->pipe; | |
548f245b | 6383 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6384 | u32 fp; |
6385 | intel_clock_t clock; | |
6386 | ||
6387 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6388 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6389 | else |
39adb7a5 | 6390 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6391 | |
6392 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6393 | if (IS_PINEVIEW(dev)) { |
6394 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6395 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6396 | } else { |
6397 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6398 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6399 | } | |
6400 | ||
a6c45cf0 | 6401 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6402 | if (IS_PINEVIEW(dev)) |
6403 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6404 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6405 | else |
6406 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6407 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6408 | ||
6409 | switch (dpll & DPLL_MODE_MASK) { | |
6410 | case DPLLB_MODE_DAC_SERIAL: | |
6411 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6412 | 5 : 10; | |
6413 | break; | |
6414 | case DPLLB_MODE_LVDS: | |
6415 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6416 | 7 : 14; | |
6417 | break; | |
6418 | default: | |
28c97730 | 6419 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6420 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6421 | return 0; | |
6422 | } | |
6423 | ||
6424 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6425 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6426 | } else { |
6427 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6428 | ||
6429 | if (is_lvds) { | |
6430 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6431 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6432 | clock.p2 = 14; | |
6433 | ||
6434 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6435 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6436 | /* XXX: might not be 66MHz */ | |
2177832f | 6437 | intel_clock(dev, 66000, &clock); |
79e53945 | 6438 | } else |
2177832f | 6439 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6440 | } else { |
6441 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6442 | clock.p1 = 2; | |
6443 | else { | |
6444 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6445 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6446 | } | |
6447 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6448 | clock.p2 = 4; | |
6449 | else | |
6450 | clock.p2 = 2; | |
6451 | ||
2177832f | 6452 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6453 | } |
6454 | } | |
6455 | ||
6456 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6457 | * i830PllIsValid() because it relies on the xf86_config connector | |
6458 | * configuration being accurate, which it isn't necessarily. | |
6459 | */ | |
6460 | ||
6461 | return clock.dot; | |
6462 | } | |
6463 | ||
6464 | /** Returns the currently programmed mode of the given pipe. */ | |
6465 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6466 | struct drm_crtc *crtc) | |
6467 | { | |
548f245b | 6468 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6470 | int pipe = intel_crtc->pipe; | |
6471 | struct drm_display_mode *mode; | |
548f245b JB |
6472 | int htot = I915_READ(HTOTAL(pipe)); |
6473 | int hsync = I915_READ(HSYNC(pipe)); | |
6474 | int vtot = I915_READ(VTOTAL(pipe)); | |
6475 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6476 | |
6477 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6478 | if (!mode) | |
6479 | return NULL; | |
6480 | ||
6481 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6482 | mode->hdisplay = (htot & 0xffff) + 1; | |
6483 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6484 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6485 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6486 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6487 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6488 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6489 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6490 | ||
6491 | drm_mode_set_name(mode); | |
6492 | drm_mode_set_crtcinfo(mode, 0); | |
6493 | ||
6494 | return mode; | |
6495 | } | |
6496 | ||
652c393a JB |
6497 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6498 | ||
6499 | /* When this timer fires, we've been idle for awhile */ | |
6500 | static void intel_gpu_idle_timer(unsigned long arg) | |
6501 | { | |
6502 | struct drm_device *dev = (struct drm_device *)arg; | |
6503 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6504 | ||
ff7ea4c0 CW |
6505 | if (!list_empty(&dev_priv->mm.active_list)) { |
6506 | /* Still processing requests, so just re-arm the timer. */ | |
6507 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6508 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6509 | return; | |
6510 | } | |
652c393a | 6511 | |
ff7ea4c0 | 6512 | dev_priv->busy = false; |
01dfba93 | 6513 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6514 | } |
6515 | ||
652c393a JB |
6516 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
6517 | ||
6518 | static void intel_crtc_idle_timer(unsigned long arg) | |
6519 | { | |
6520 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
6521 | struct drm_crtc *crtc = &intel_crtc->base; | |
6522 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 6523 | struct intel_framebuffer *intel_fb; |
652c393a | 6524 | |
ff7ea4c0 CW |
6525 | intel_fb = to_intel_framebuffer(crtc->fb); |
6526 | if (intel_fb && intel_fb->obj->active) { | |
6527 | /* The framebuffer is still being accessed by the GPU. */ | |
6528 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6529 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6530 | return; | |
6531 | } | |
652c393a | 6532 | |
ff7ea4c0 | 6533 | intel_crtc->busy = false; |
01dfba93 | 6534 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6535 | } |
6536 | ||
3dec0095 | 6537 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6538 | { |
6539 | struct drm_device *dev = crtc->dev; | |
6540 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6542 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6543 | int dpll_reg = DPLL(pipe); |
6544 | int dpll; | |
652c393a | 6545 | |
bad720ff | 6546 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6547 | return; |
6548 | ||
6549 | if (!dev_priv->lvds_downclock_avail) | |
6550 | return; | |
6551 | ||
dbdc6479 | 6552 | dpll = I915_READ(dpll_reg); |
652c393a | 6553 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6554 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
6555 | |
6556 | /* Unlock panel regs */ | |
dbdc6479 JB |
6557 | I915_WRITE(PP_CONTROL, |
6558 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
6559 | |
6560 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6561 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6562 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6563 | |
652c393a JB |
6564 | dpll = I915_READ(dpll_reg); |
6565 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6566 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
6567 | |
6568 | /* ...and lock them again */ | |
6569 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6570 | } | |
6571 | ||
6572 | /* Schedule downclock */ | |
3dec0095 DV |
6573 | mod_timer(&intel_crtc->idle_timer, jiffies + |
6574 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
6575 | } |
6576 | ||
6577 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6578 | { | |
6579 | struct drm_device *dev = crtc->dev; | |
6580 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6582 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 6583 | int dpll_reg = DPLL(pipe); |
652c393a JB |
6584 | int dpll = I915_READ(dpll_reg); |
6585 | ||
bad720ff | 6586 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6587 | return; |
6588 | ||
6589 | if (!dev_priv->lvds_downclock_avail) | |
6590 | return; | |
6591 | ||
6592 | /* | |
6593 | * Since this is called by a timer, we should never get here in | |
6594 | * the manual case. | |
6595 | */ | |
6596 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 6597 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
6598 | |
6599 | /* Unlock panel regs */ | |
4a655f04 JB |
6600 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
6601 | PANEL_UNLOCK_REGS); | |
652c393a JB |
6602 | |
6603 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
6604 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6605 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6606 | dpll = I915_READ(dpll_reg); |
6607 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6608 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6609 | |
6610 | /* ...and lock them again */ | |
6611 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6612 | } | |
6613 | ||
6614 | } | |
6615 | ||
6616 | /** | |
6617 | * intel_idle_update - adjust clocks for idleness | |
6618 | * @work: work struct | |
6619 | * | |
6620 | * Either the GPU or display (or both) went idle. Check the busy status | |
6621 | * here and adjust the CRTC and GPU clocks as necessary. | |
6622 | */ | |
6623 | static void intel_idle_update(struct work_struct *work) | |
6624 | { | |
6625 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
6626 | idle_work); | |
6627 | struct drm_device *dev = dev_priv->dev; | |
6628 | struct drm_crtc *crtc; | |
6629 | struct intel_crtc *intel_crtc; | |
6630 | ||
6631 | if (!i915_powersave) | |
6632 | return; | |
6633 | ||
6634 | mutex_lock(&dev->struct_mutex); | |
6635 | ||
7648fa99 JB |
6636 | i915_update_gfx_val(dev_priv); |
6637 | ||
652c393a JB |
6638 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6639 | /* Skip inactive CRTCs */ | |
6640 | if (!crtc->fb) | |
6641 | continue; | |
6642 | ||
6643 | intel_crtc = to_intel_crtc(crtc); | |
6644 | if (!intel_crtc->busy) | |
6645 | intel_decrease_pllclock(crtc); | |
6646 | } | |
6647 | ||
45ac22c8 | 6648 | |
652c393a JB |
6649 | mutex_unlock(&dev->struct_mutex); |
6650 | } | |
6651 | ||
6652 | /** | |
6653 | * intel_mark_busy - mark the GPU and possibly the display busy | |
6654 | * @dev: drm device | |
6655 | * @obj: object we're operating on | |
6656 | * | |
6657 | * Callers can use this function to indicate that the GPU is busy processing | |
6658 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
6659 | * buffer), we'll also mark the display as busy, so we know to increase its | |
6660 | * clock frequency. | |
6661 | */ | |
05394f39 | 6662 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
6663 | { |
6664 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6665 | struct drm_crtc *crtc = NULL; | |
6666 | struct intel_framebuffer *intel_fb; | |
6667 | struct intel_crtc *intel_crtc; | |
6668 | ||
5e17ee74 ZW |
6669 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6670 | return; | |
6671 | ||
18b2190c | 6672 | if (!dev_priv->busy) |
28cf798f | 6673 | dev_priv->busy = true; |
18b2190c | 6674 | else |
28cf798f CW |
6675 | mod_timer(&dev_priv->idle_timer, jiffies + |
6676 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
6677 | |
6678 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6679 | if (!crtc->fb) | |
6680 | continue; | |
6681 | ||
6682 | intel_crtc = to_intel_crtc(crtc); | |
6683 | intel_fb = to_intel_framebuffer(crtc->fb); | |
6684 | if (intel_fb->obj == obj) { | |
6685 | if (!intel_crtc->busy) { | |
6686 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 6687 | intel_increase_pllclock(crtc); |
652c393a JB |
6688 | intel_crtc->busy = true; |
6689 | } else { | |
6690 | /* Busy -> busy, put off timer */ | |
6691 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6692 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6693 | } | |
6694 | } | |
6695 | } | |
6696 | } | |
6697 | ||
79e53945 JB |
6698 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6699 | { | |
6700 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6701 | struct drm_device *dev = crtc->dev; |
6702 | struct intel_unpin_work *work; | |
6703 | unsigned long flags; | |
6704 | ||
6705 | spin_lock_irqsave(&dev->event_lock, flags); | |
6706 | work = intel_crtc->unpin_work; | |
6707 | intel_crtc->unpin_work = NULL; | |
6708 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6709 | ||
6710 | if (work) { | |
6711 | cancel_work_sync(&work->work); | |
6712 | kfree(work); | |
6713 | } | |
79e53945 JB |
6714 | |
6715 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6716 | |
79e53945 JB |
6717 | kfree(intel_crtc); |
6718 | } | |
6719 | ||
6b95a207 KH |
6720 | static void intel_unpin_work_fn(struct work_struct *__work) |
6721 | { | |
6722 | struct intel_unpin_work *work = | |
6723 | container_of(__work, struct intel_unpin_work, work); | |
6724 | ||
6725 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 6726 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
6727 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6728 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6729 | |
6b95a207 KH |
6730 | mutex_unlock(&work->dev->struct_mutex); |
6731 | kfree(work); | |
6732 | } | |
6733 | ||
1afe3e9d | 6734 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6735 | struct drm_crtc *crtc) |
6b95a207 KH |
6736 | { |
6737 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6739 | struct intel_unpin_work *work; | |
05394f39 | 6740 | struct drm_i915_gem_object *obj; |
6b95a207 | 6741 | struct drm_pending_vblank_event *e; |
49b14a5c | 6742 | struct timeval tnow, tvbl; |
6b95a207 KH |
6743 | unsigned long flags; |
6744 | ||
6745 | /* Ignore early vblank irqs */ | |
6746 | if (intel_crtc == NULL) | |
6747 | return; | |
6748 | ||
49b14a5c MK |
6749 | do_gettimeofday(&tnow); |
6750 | ||
6b95a207 KH |
6751 | spin_lock_irqsave(&dev->event_lock, flags); |
6752 | work = intel_crtc->unpin_work; | |
6753 | if (work == NULL || !work->pending) { | |
6754 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6755 | return; | |
6756 | } | |
6757 | ||
6758 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
6759 | |
6760 | if (work->event) { | |
6761 | e = work->event; | |
49b14a5c | 6762 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
6763 | |
6764 | /* Called before vblank count and timestamps have | |
6765 | * been updated for the vblank interval of flip | |
6766 | * completion? Need to increment vblank count and | |
6767 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
6768 | * to account for this. We assume this happened if we |
6769 | * get called over 0.9 frame durations after the last | |
6770 | * timestamped vblank. | |
6771 | * | |
6772 | * This calculation can not be used with vrefresh rates | |
6773 | * below 5Hz (10Hz to be on the safe side) without | |
6774 | * promoting to 64 integers. | |
0af7e4df | 6775 | */ |
49b14a5c MK |
6776 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
6777 | 9 * crtc->framedur_ns) { | |
0af7e4df | 6778 | e->event.sequence++; |
49b14a5c MK |
6779 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
6780 | crtc->framedur_ns); | |
0af7e4df MK |
6781 | } |
6782 | ||
49b14a5c MK |
6783 | e->event.tv_sec = tvbl.tv_sec; |
6784 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 6785 | |
6b95a207 KH |
6786 | list_add_tail(&e->base.link, |
6787 | &e->base.file_priv->event_list); | |
6788 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
6789 | } | |
6790 | ||
0af7e4df MK |
6791 | drm_vblank_put(dev, intel_crtc->pipe); |
6792 | ||
6b95a207 KH |
6793 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6794 | ||
05394f39 | 6795 | obj = work->old_fb_obj; |
d9e86c0e | 6796 | |
e59f2bac | 6797 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
6798 | &obj->pending_flip.counter); |
6799 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 6800 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 6801 | |
6b95a207 | 6802 | schedule_work(&work->work); |
e5510fac JB |
6803 | |
6804 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6805 | } |
6806 | ||
1afe3e9d JB |
6807 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6808 | { | |
6809 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6810 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6811 | ||
49b14a5c | 6812 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6813 | } |
6814 | ||
6815 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6816 | { | |
6817 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6818 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6819 | ||
49b14a5c | 6820 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6821 | } |
6822 | ||
6b95a207 KH |
6823 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6824 | { | |
6825 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6826 | struct intel_crtc *intel_crtc = | |
6827 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6828 | unsigned long flags; | |
6829 | ||
6830 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6831 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6832 | if ((++intel_crtc->unpin_work->pending) > 1) |
6833 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6834 | } else { |
6835 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6836 | } | |
6b95a207 KH |
6837 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6838 | } | |
6839 | ||
6840 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
6841 | struct drm_framebuffer *fb, | |
6842 | struct drm_pending_vblank_event *event) | |
6843 | { | |
6844 | struct drm_device *dev = crtc->dev; | |
6845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6846 | struct intel_framebuffer *intel_fb; | |
05394f39 | 6847 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6849 | struct intel_unpin_work *work; | |
be9a3dbf | 6850 | unsigned long flags, offset; |
52e68630 | 6851 | int pipe = intel_crtc->pipe; |
20f0cd55 | 6852 | u32 pf, pipesrc; |
52e68630 | 6853 | int ret; |
6b95a207 KH |
6854 | |
6855 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
6856 | if (work == NULL) | |
6857 | return -ENOMEM; | |
6858 | ||
6b95a207 KH |
6859 | work->event = event; |
6860 | work->dev = crtc->dev; | |
6861 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 6862 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
6863 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6864 | ||
6865 | /* We borrow the event spin lock for protecting unpin_work */ | |
6866 | spin_lock_irqsave(&dev->event_lock, flags); | |
6867 | if (intel_crtc->unpin_work) { | |
6868 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6869 | kfree(work); | |
468f0b44 CW |
6870 | |
6871 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
6872 | return -EBUSY; |
6873 | } | |
6874 | intel_crtc->unpin_work = work; | |
6875 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6876 | ||
6877 | intel_fb = to_intel_framebuffer(fb); | |
6878 | obj = intel_fb->obj; | |
6879 | ||
468f0b44 | 6880 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 | 6881 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
96b099fd CW |
6882 | if (ret) |
6883 | goto cleanup_work; | |
6b95a207 | 6884 | |
75dfca80 | 6885 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
6886 | drm_gem_object_reference(&work->old_fb_obj->base); |
6887 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
6888 | |
6889 | crtc->fb = fb; | |
96b099fd CW |
6890 | |
6891 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
6892 | if (ret) | |
6893 | goto cleanup_objs; | |
6894 | ||
c7f9f9a8 CW |
6895 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
6896 | u32 flip_mask; | |
48b956c5 | 6897 | |
c7f9f9a8 CW |
6898 | /* Can't queue multiple flips, so wait for the previous |
6899 | * one to finish before executing the next. | |
6900 | */ | |
e1f99ce6 CW |
6901 | ret = BEGIN_LP_RING(2); |
6902 | if (ret) | |
6903 | goto cleanup_objs; | |
6904 | ||
c7f9f9a8 CW |
6905 | if (intel_crtc->plane) |
6906 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6907 | else | |
6908 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6909 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
6910 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
6911 | ADVANCE_LP_RING(); |
6912 | } | |
83f7fd05 | 6913 | |
e1f99ce6 | 6914 | work->pending_flip_obj = obj; |
e1f99ce6 | 6915 | |
4e5359cd SF |
6916 | work->enable_stall_check = true; |
6917 | ||
be9a3dbf | 6918 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 6919 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 6920 | |
e1f99ce6 CW |
6921 | ret = BEGIN_LP_RING(4); |
6922 | if (ret) | |
6923 | goto cleanup_objs; | |
6924 | ||
6925 | /* Block clients from rendering to the new back buffer until | |
6926 | * the flip occurs and the object is no longer visible. | |
6927 | */ | |
05394f39 | 6928 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 CW |
6929 | |
6930 | switch (INTEL_INFO(dev)->gen) { | |
52e68630 | 6931 | case 2: |
1afe3e9d JB |
6932 | OUT_RING(MI_DISPLAY_FLIP | |
6933 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6934 | OUT_RING(fb->pitch); | |
05394f39 | 6935 | OUT_RING(obj->gtt_offset + offset); |
52e68630 CW |
6936 | OUT_RING(MI_NOOP); |
6937 | break; | |
6938 | ||
6939 | case 3: | |
1afe3e9d JB |
6940 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
6941 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6942 | OUT_RING(fb->pitch); | |
05394f39 | 6943 | OUT_RING(obj->gtt_offset + offset); |
22fd0fab | 6944 | OUT_RING(MI_NOOP); |
52e68630 CW |
6945 | break; |
6946 | ||
6947 | case 4: | |
6948 | case 5: | |
6949 | /* i965+ uses the linear or tiled offsets from the | |
6950 | * Display Registers (which do not change across a page-flip) | |
6951 | * so we need only reprogram the base address. | |
6952 | */ | |
69d0b96c DV |
6953 | OUT_RING(MI_DISPLAY_FLIP | |
6954 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6955 | OUT_RING(fb->pitch); | |
05394f39 | 6956 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
52e68630 CW |
6957 | |
6958 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6959 | * untested on non-native modes, so ignore it for now. | |
6960 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6961 | */ | |
6962 | pf = 0; | |
9db4a9c7 | 6963 | pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff; |
52e68630 CW |
6964 | OUT_RING(pf | pipesrc); |
6965 | break; | |
6966 | ||
6967 | case 6: | |
6968 | OUT_RING(MI_DISPLAY_FLIP | | |
6969 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
05394f39 CW |
6970 | OUT_RING(fb->pitch | obj->tiling_mode); |
6971 | OUT_RING(obj->gtt_offset); | |
52e68630 | 6972 | |
9db4a9c7 JB |
6973 | pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE; |
6974 | pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff; | |
52e68630 CW |
6975 | OUT_RING(pf | pipesrc); |
6976 | break; | |
22fd0fab | 6977 | } |
6b95a207 KH |
6978 | ADVANCE_LP_RING(); |
6979 | ||
6980 | mutex_unlock(&dev->struct_mutex); | |
6981 | ||
e5510fac JB |
6982 | trace_i915_flip_request(intel_crtc->plane, obj); |
6983 | ||
6b95a207 | 6984 | return 0; |
96b099fd CW |
6985 | |
6986 | cleanup_objs: | |
05394f39 CW |
6987 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6988 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
6989 | cleanup_work: |
6990 | mutex_unlock(&dev->struct_mutex); | |
6991 | ||
6992 | spin_lock_irqsave(&dev->event_lock, flags); | |
6993 | intel_crtc->unpin_work = NULL; | |
6994 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6995 | ||
6996 | kfree(work); | |
6997 | ||
6998 | return ret; | |
6b95a207 KH |
6999 | } |
7000 | ||
47f1c6c9 CW |
7001 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7002 | int pipe, int plane) | |
7003 | { | |
7004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7005 | u32 reg, val; | |
7006 | ||
7007 | if (HAS_PCH_SPLIT(dev)) | |
7008 | return; | |
7009 | ||
7010 | /* Who knows what state these registers were left in by the BIOS or | |
7011 | * grub? | |
7012 | * | |
7013 | * If we leave the registers in a conflicting state (e.g. with the | |
7014 | * display plane reading from the other pipe than the one we intend | |
7015 | * to use) then when we attempt to teardown the active mode, we will | |
7016 | * not disable the pipes and planes in the correct order -- leaving | |
7017 | * a plane reading from a disabled pipe and possibly leading to | |
7018 | * undefined behaviour. | |
7019 | */ | |
7020 | ||
7021 | reg = DSPCNTR(plane); | |
7022 | val = I915_READ(reg); | |
7023 | ||
7024 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7025 | return; | |
7026 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7027 | return; | |
7028 | ||
7029 | /* This display plane is active and attached to the other CPU pipe. */ | |
7030 | pipe = !pipe; | |
7031 | ||
7032 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7033 | intel_disable_plane(dev_priv, plane, pipe); |
7034 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7035 | } |
79e53945 | 7036 | |
f6e5b160 CW |
7037 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7038 | { | |
7039 | struct drm_device *dev = crtc->dev; | |
7040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7041 | ||
7042 | /* Reset flags back to the 'unknown' status so that they | |
7043 | * will be correctly set on the initial modeset. | |
7044 | */ | |
7045 | intel_crtc->dpms_mode = -1; | |
7046 | ||
7047 | /* We need to fix up any BIOS configuration that conflicts with | |
7048 | * our expectations. | |
7049 | */ | |
7050 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7051 | } | |
7052 | ||
7053 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7054 | .dpms = intel_crtc_dpms, | |
7055 | .mode_fixup = intel_crtc_mode_fixup, | |
7056 | .mode_set = intel_crtc_mode_set, | |
7057 | .mode_set_base = intel_pipe_set_base, | |
7058 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7059 | .load_lut = intel_crtc_load_lut, | |
7060 | .disable = intel_crtc_disable, | |
7061 | }; | |
7062 | ||
7063 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7064 | .reset = intel_crtc_reset, | |
7065 | .cursor_set = intel_crtc_cursor_set, | |
7066 | .cursor_move = intel_crtc_cursor_move, | |
7067 | .gamma_set = intel_crtc_gamma_set, | |
7068 | .set_config = drm_crtc_helper_set_config, | |
7069 | .destroy = intel_crtc_destroy, | |
7070 | .page_flip = intel_crtc_page_flip, | |
7071 | }; | |
7072 | ||
b358d0a6 | 7073 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7074 | { |
22fd0fab | 7075 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7076 | struct intel_crtc *intel_crtc; |
7077 | int i; | |
7078 | ||
7079 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7080 | if (intel_crtc == NULL) | |
7081 | return; | |
7082 | ||
7083 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7084 | ||
7085 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7086 | for (i = 0; i < 256; i++) { |
7087 | intel_crtc->lut_r[i] = i; | |
7088 | intel_crtc->lut_g[i] = i; | |
7089 | intel_crtc->lut_b[i] = i; | |
7090 | } | |
7091 | ||
80824003 JB |
7092 | /* Swap pipes & planes for FBC on pre-965 */ |
7093 | intel_crtc->pipe = pipe; | |
7094 | intel_crtc->plane = pipe; | |
e2e767ab | 7095 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7096 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7097 | intel_crtc->plane = !pipe; |
80824003 JB |
7098 | } |
7099 | ||
22fd0fab JB |
7100 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7101 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7102 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7103 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7104 | ||
5d1d0cc8 | 7105 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7106 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
7107 | |
7108 | if (HAS_PCH_SPLIT(dev)) { | |
7109 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
7110 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7111 | } else { | |
7112 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7113 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7114 | } | |
7115 | ||
79e53945 JB |
7116 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7117 | ||
652c393a JB |
7118 | intel_crtc->busy = false; |
7119 | ||
7120 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7121 | (unsigned long)intel_crtc); | |
79e53945 JB |
7122 | } |
7123 | ||
08d7b3d1 | 7124 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7125 | struct drm_file *file) |
08d7b3d1 CW |
7126 | { |
7127 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7128 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7129 | struct drm_mode_object *drmmode_obj; |
7130 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7131 | |
7132 | if (!dev_priv) { | |
7133 | DRM_ERROR("called with no initialization\n"); | |
7134 | return -EINVAL; | |
7135 | } | |
7136 | ||
c05422d5 DV |
7137 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7138 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7139 | |
c05422d5 | 7140 | if (!drmmode_obj) { |
08d7b3d1 CW |
7141 | DRM_ERROR("no such CRTC id\n"); |
7142 | return -EINVAL; | |
7143 | } | |
7144 | ||
c05422d5 DV |
7145 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7146 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7147 | |
c05422d5 | 7148 | return 0; |
08d7b3d1 CW |
7149 | } |
7150 | ||
c5e4df33 | 7151 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7152 | { |
4ef69c7a | 7153 | struct intel_encoder *encoder; |
79e53945 | 7154 | int index_mask = 0; |
79e53945 JB |
7155 | int entry = 0; |
7156 | ||
4ef69c7a CW |
7157 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7158 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7159 | index_mask |= (1 << entry); |
7160 | entry++; | |
7161 | } | |
4ef69c7a | 7162 | |
79e53945 JB |
7163 | return index_mask; |
7164 | } | |
7165 | ||
4d302442 CW |
7166 | static bool has_edp_a(struct drm_device *dev) |
7167 | { | |
7168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7169 | ||
7170 | if (!IS_MOBILE(dev)) | |
7171 | return false; | |
7172 | ||
7173 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7174 | return false; | |
7175 | ||
7176 | if (IS_GEN5(dev) && | |
7177 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7178 | return false; | |
7179 | ||
7180 | return true; | |
7181 | } | |
7182 | ||
79e53945 JB |
7183 | static void intel_setup_outputs(struct drm_device *dev) |
7184 | { | |
725e30ad | 7185 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7186 | struct intel_encoder *encoder; |
cb0953d7 | 7187 | bool dpd_is_edp = false; |
c5d1b51d | 7188 | bool has_lvds = false; |
79e53945 | 7189 | |
541998a1 | 7190 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
7191 | has_lvds = intel_lvds_init(dev); |
7192 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
7193 | /* disable the panel fitter on everything but LVDS */ | |
7194 | I915_WRITE(PFIT_CONTROL, 0); | |
7195 | } | |
79e53945 | 7196 | |
bad720ff | 7197 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7198 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7199 | |
4d302442 | 7200 | if (has_edp_a(dev)) |
32f9d658 ZW |
7201 | intel_dp_init(dev, DP_A); |
7202 | ||
cb0953d7 AJ |
7203 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7204 | intel_dp_init(dev, PCH_DP_D); | |
7205 | } | |
7206 | ||
7207 | intel_crt_init(dev); | |
7208 | ||
7209 | if (HAS_PCH_SPLIT(dev)) { | |
7210 | int found; | |
7211 | ||
30ad48b7 | 7212 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
7213 | /* PCH SDVOB multiplex with HDMIB */ |
7214 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
7215 | if (!found) |
7216 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7217 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7218 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7219 | } |
7220 | ||
7221 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7222 | intel_hdmi_init(dev, HDMIC); | |
7223 | ||
7224 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7225 | intel_hdmi_init(dev, HDMID); | |
7226 | ||
5eb08b69 ZW |
7227 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7228 | intel_dp_init(dev, PCH_DP_C); | |
7229 | ||
cb0953d7 | 7230 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7231 | intel_dp_init(dev, PCH_DP_D); |
7232 | ||
103a196f | 7233 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7234 | bool found = false; |
7d57382e | 7235 | |
725e30ad | 7236 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7237 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 7238 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
7239 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7240 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7241 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7242 | } |
27185ae1 | 7243 | |
b01f2c3a JB |
7244 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7245 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7246 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7247 | } |
725e30ad | 7248 | } |
13520b05 KH |
7249 | |
7250 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7251 | |
b01f2c3a JB |
7252 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7253 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 7254 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 7255 | } |
27185ae1 ML |
7256 | |
7257 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7258 | ||
b01f2c3a JB |
7259 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7260 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7261 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7262 | } |
7263 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7264 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7265 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7266 | } |
725e30ad | 7267 | } |
27185ae1 | 7268 | |
b01f2c3a JB |
7269 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7270 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7271 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7272 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7273 | } |
bad720ff | 7274 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7275 | intel_dvo_init(dev); |
7276 | ||
103a196f | 7277 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7278 | intel_tv_init(dev); |
7279 | ||
4ef69c7a CW |
7280 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7281 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7282 | encoder->base.possible_clones = | |
7283 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7284 | } |
47356eb6 CW |
7285 | |
7286 | intel_panel_setup_backlight(dev); | |
79e53945 JB |
7287 | } |
7288 | ||
7289 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7290 | { | |
7291 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7292 | |
7293 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7294 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7295 | |
7296 | kfree(intel_fb); | |
7297 | } | |
7298 | ||
7299 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7300 | struct drm_file *file, |
79e53945 JB |
7301 | unsigned int *handle) |
7302 | { | |
7303 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7304 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7305 | |
05394f39 | 7306 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7307 | } |
7308 | ||
7309 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7310 | .destroy = intel_user_framebuffer_destroy, | |
7311 | .create_handle = intel_user_framebuffer_create_handle, | |
7312 | }; | |
7313 | ||
38651674 DA |
7314 | int intel_framebuffer_init(struct drm_device *dev, |
7315 | struct intel_framebuffer *intel_fb, | |
7316 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 7317 | struct drm_i915_gem_object *obj) |
79e53945 | 7318 | { |
79e53945 JB |
7319 | int ret; |
7320 | ||
05394f39 | 7321 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7322 | return -EINVAL; |
7323 | ||
7324 | if (mode_cmd->pitch & 63) | |
7325 | return -EINVAL; | |
7326 | ||
7327 | switch (mode_cmd->bpp) { | |
7328 | case 8: | |
7329 | case 16: | |
7330 | case 24: | |
7331 | case 32: | |
7332 | break; | |
7333 | default: | |
7334 | return -EINVAL; | |
7335 | } | |
7336 | ||
79e53945 JB |
7337 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7338 | if (ret) { | |
7339 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7340 | return ret; | |
7341 | } | |
7342 | ||
7343 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7344 | intel_fb->obj = obj; |
79e53945 JB |
7345 | return 0; |
7346 | } | |
7347 | ||
79e53945 JB |
7348 | static struct drm_framebuffer * |
7349 | intel_user_framebuffer_create(struct drm_device *dev, | |
7350 | struct drm_file *filp, | |
7351 | struct drm_mode_fb_cmd *mode_cmd) | |
7352 | { | |
05394f39 | 7353 | struct drm_i915_gem_object *obj; |
79e53945 | 7354 | |
05394f39 | 7355 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
c8725226 | 7356 | if (&obj->base == NULL) |
cce13ff7 | 7357 | return ERR_PTR(-ENOENT); |
79e53945 | 7358 | |
d2dff872 | 7359 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7360 | } |
7361 | ||
79e53945 | 7362 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7363 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7364 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7365 | }; |
7366 | ||
05394f39 | 7367 | static struct drm_i915_gem_object * |
aa40d6bb | 7368 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7369 | { |
05394f39 | 7370 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7371 | int ret; |
7372 | ||
aa40d6bb ZN |
7373 | ctx = i915_gem_alloc_object(dev, 4096); |
7374 | if (!ctx) { | |
9ea8d059 CW |
7375 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7376 | return NULL; | |
7377 | } | |
7378 | ||
7379 | mutex_lock(&dev->struct_mutex); | |
75e9e915 | 7380 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7381 | if (ret) { |
7382 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7383 | goto err_unref; | |
7384 | } | |
7385 | ||
aa40d6bb | 7386 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
7387 | if (ret) { |
7388 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
7389 | goto err_unpin; | |
7390 | } | |
7391 | mutex_unlock(&dev->struct_mutex); | |
7392 | ||
aa40d6bb | 7393 | return ctx; |
9ea8d059 CW |
7394 | |
7395 | err_unpin: | |
aa40d6bb | 7396 | i915_gem_object_unpin(ctx); |
9ea8d059 | 7397 | err_unref: |
05394f39 | 7398 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
7399 | mutex_unlock(&dev->struct_mutex); |
7400 | return NULL; | |
7401 | } | |
7402 | ||
7648fa99 JB |
7403 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
7404 | { | |
7405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7406 | u16 rgvswctl; | |
7407 | ||
7408 | rgvswctl = I915_READ16(MEMSWCTL); | |
7409 | if (rgvswctl & MEMCTL_CMD_STS) { | |
7410 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
7411 | return false; /* still busy with another command */ | |
7412 | } | |
7413 | ||
7414 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
7415 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
7416 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7417 | POSTING_READ16(MEMSWCTL); | |
7418 | ||
7419 | rgvswctl |= MEMCTL_CMD_STS; | |
7420 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7421 | ||
7422 | return true; | |
7423 | } | |
7424 | ||
f97108d1 JB |
7425 | void ironlake_enable_drps(struct drm_device *dev) |
7426 | { | |
7427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7428 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 7429 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 7430 | |
ea056c14 JB |
7431 | /* Enable temp reporting */ |
7432 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
7433 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
7434 | ||
f97108d1 JB |
7435 | /* 100ms RC evaluation intervals */ |
7436 | I915_WRITE(RCUPEI, 100000); | |
7437 | I915_WRITE(RCDNEI, 100000); | |
7438 | ||
7439 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
7440 | I915_WRITE(RCBMAXAVG, 90000); | |
7441 | I915_WRITE(RCBMINAVG, 80000); | |
7442 | ||
7443 | I915_WRITE(MEMIHYST, 1); | |
7444 | ||
7445 | /* Set up min, max, and cur for interrupt handling */ | |
7446 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
7447 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
7448 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
7449 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 7450 | |
f97108d1 JB |
7451 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
7452 | PXVFREQ_PX_SHIFT; | |
7453 | ||
80dbf4b7 | 7454 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
7455 | dev_priv->fstart = fstart; |
7456 | ||
80dbf4b7 | 7457 | dev_priv->max_delay = fstart; |
f97108d1 JB |
7458 | dev_priv->min_delay = fmin; |
7459 | dev_priv->cur_delay = fstart; | |
7460 | ||
80dbf4b7 JB |
7461 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
7462 | fmax, fmin, fstart); | |
7648fa99 | 7463 | |
f97108d1 JB |
7464 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
7465 | ||
7466 | /* | |
7467 | * Interrupts will be enabled in ironlake_irq_postinstall | |
7468 | */ | |
7469 | ||
7470 | I915_WRITE(VIDSTART, vstart); | |
7471 | POSTING_READ(VIDSTART); | |
7472 | ||
7473 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
7474 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
7475 | ||
481b6af3 | 7476 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 7477 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
7478 | msleep(1); |
7479 | ||
7648fa99 | 7480 | ironlake_set_drps(dev, fstart); |
f97108d1 | 7481 | |
7648fa99 JB |
7482 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
7483 | I915_READ(0x112e0); | |
7484 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
7485 | dev_priv->last_count2 = I915_READ(0x112f4); | |
7486 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
7487 | } |
7488 | ||
7489 | void ironlake_disable_drps(struct drm_device *dev) | |
7490 | { | |
7491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7492 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
7493 | |
7494 | /* Ack interrupts, disable EFC interrupt */ | |
7495 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
7496 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
7497 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
7498 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
7499 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
7500 | ||
7501 | /* Go back to the starting frequency */ | |
7648fa99 | 7502 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
7503 | msleep(1); |
7504 | rgvswctl |= MEMCTL_CMD_STS; | |
7505 | I915_WRITE(MEMSWCTL, rgvswctl); | |
7506 | msleep(1); | |
7507 | ||
7508 | } | |
7509 | ||
3b8d8d91 JB |
7510 | void gen6_set_rps(struct drm_device *dev, u8 val) |
7511 | { | |
7512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7513 | u32 swreq; | |
7514 | ||
7515 | swreq = (val & 0x3ff) << 25; | |
7516 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
7517 | } | |
7518 | ||
7519 | void gen6_disable_rps(struct drm_device *dev) | |
7520 | { | |
7521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7522 | ||
7523 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
7524 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
7525 | I915_WRITE(GEN6_PMIER, 0); | |
7526 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); | |
7527 | } | |
7528 | ||
7648fa99 JB |
7529 | static unsigned long intel_pxfreq(u32 vidfreq) |
7530 | { | |
7531 | unsigned long freq; | |
7532 | int div = (vidfreq & 0x3f0000) >> 16; | |
7533 | int post = (vidfreq & 0x3000) >> 12; | |
7534 | int pre = (vidfreq & 0x7); | |
7535 | ||
7536 | if (!pre) | |
7537 | return 0; | |
7538 | ||
7539 | freq = ((div * 133333) / ((1<<post) * pre)); | |
7540 | ||
7541 | return freq; | |
7542 | } | |
7543 | ||
7544 | void intel_init_emon(struct drm_device *dev) | |
7545 | { | |
7546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7547 | u32 lcfuse; | |
7548 | u8 pxw[16]; | |
7549 | int i; | |
7550 | ||
7551 | /* Disable to program */ | |
7552 | I915_WRITE(ECR, 0); | |
7553 | POSTING_READ(ECR); | |
7554 | ||
7555 | /* Program energy weights for various events */ | |
7556 | I915_WRITE(SDEW, 0x15040d00); | |
7557 | I915_WRITE(CSIEW0, 0x007f0000); | |
7558 | I915_WRITE(CSIEW1, 0x1e220004); | |
7559 | I915_WRITE(CSIEW2, 0x04000004); | |
7560 | ||
7561 | for (i = 0; i < 5; i++) | |
7562 | I915_WRITE(PEW + (i * 4), 0); | |
7563 | for (i = 0; i < 3; i++) | |
7564 | I915_WRITE(DEW + (i * 4), 0); | |
7565 | ||
7566 | /* Program P-state weights to account for frequency power adjustment */ | |
7567 | for (i = 0; i < 16; i++) { | |
7568 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
7569 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
7570 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
7571 | PXVFREQ_PX_SHIFT; | |
7572 | unsigned long val; | |
7573 | ||
7574 | val = vid * vid; | |
7575 | val *= (freq / 1000); | |
7576 | val *= 255; | |
7577 | val /= (127*127*900); | |
7578 | if (val > 0xff) | |
7579 | DRM_ERROR("bad pxval: %ld\n", val); | |
7580 | pxw[i] = val; | |
7581 | } | |
7582 | /* Render standby states get 0 weight */ | |
7583 | pxw[14] = 0; | |
7584 | pxw[15] = 0; | |
7585 | ||
7586 | for (i = 0; i < 4; i++) { | |
7587 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
7588 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
7589 | I915_WRITE(PXW + (i * 4), val); | |
7590 | } | |
7591 | ||
7592 | /* Adjust magic regs to magic values (more experimental results) */ | |
7593 | I915_WRITE(OGW0, 0); | |
7594 | I915_WRITE(OGW1, 0); | |
7595 | I915_WRITE(EG0, 0x00007f00); | |
7596 | I915_WRITE(EG1, 0x0000000e); | |
7597 | I915_WRITE(EG2, 0x000e0000); | |
7598 | I915_WRITE(EG3, 0x68000300); | |
7599 | I915_WRITE(EG4, 0x42000000); | |
7600 | I915_WRITE(EG5, 0x00140031); | |
7601 | I915_WRITE(EG6, 0); | |
7602 | I915_WRITE(EG7, 0); | |
7603 | ||
7604 | for (i = 0; i < 8; i++) | |
7605 | I915_WRITE(PXWL + (i * 4), 0); | |
7606 | ||
7607 | /* Enable PMON + select events */ | |
7608 | I915_WRITE(ECR, 0x80000019); | |
7609 | ||
7610 | lcfuse = I915_READ(LCFUSE02); | |
7611 | ||
7612 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
7613 | } | |
7614 | ||
3b8d8d91 | 7615 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 7616 | { |
a6044e23 JB |
7617 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
7618 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7619 | u32 pcu_mbox; | |
7620 | int cur_freq, min_freq, max_freq; | |
8fd26859 CW |
7621 | int i; |
7622 | ||
7623 | /* Here begins a magic sequence of register writes to enable | |
7624 | * auto-downclocking. | |
7625 | * | |
7626 | * Perhaps there might be some value in exposing these to | |
7627 | * userspace... | |
7628 | */ | |
7629 | I915_WRITE(GEN6_RC_STATE, 0); | |
91355834 | 7630 | __gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 7631 | |
3b8d8d91 | 7632 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
7633 | I915_WRITE(GEN6_RC_CONTROL, 0); |
7634 | ||
7635 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
7636 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
7637 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
7638 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
7639 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
7640 | ||
7641 | for (i = 0; i < I915_NUM_RINGS; i++) | |
7642 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
7643 | ||
7644 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
7645 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
7646 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
7647 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
7648 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
7649 | ||
7650 | I915_WRITE(GEN6_RC_CONTROL, | |
7651 | GEN6_RC_CTL_RC6p_ENABLE | | |
7652 | GEN6_RC_CTL_RC6_ENABLE | | |
9c3d2f7f | 7653 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
7654 | GEN6_RC_CTL_HW_ENABLE); |
7655 | ||
3b8d8d91 | 7656 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
7657 | GEN6_FREQUENCY(10) | |
7658 | GEN6_OFFSET(0) | | |
7659 | GEN6_AGGRESSIVE_TURBO); | |
7660 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
7661 | GEN6_FREQUENCY(12)); | |
7662 | ||
7663 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
7664 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
7665 | 18 << 24 | | |
7666 | 6 << 16); | |
ccab5c82 JB |
7667 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
7668 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 7669 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 7670 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
7671 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
7672 | I915_WRITE(GEN6_RP_CONTROL, | |
7673 | GEN6_RP_MEDIA_TURBO | | |
7674 | GEN6_RP_USE_NORMAL_FREQ | | |
7675 | GEN6_RP_MEDIA_IS_GFX | | |
7676 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
7677 | GEN6_RP_UP_BUSY_AVG | |
7678 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
7679 | |
7680 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7681 | 500)) | |
7682 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7683 | ||
7684 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7685 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
7686 | GEN6_PCODE_READY | | |
7687 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
7688 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7689 | 500)) | |
7690 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7691 | ||
a6044e23 JB |
7692 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
7693 | max_freq = rp_state_cap & 0xff; | |
7694 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
7695 | ||
7696 | /* Check for overclock support */ | |
7697 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7698 | 500)) | |
7699 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7700 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
7701 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
7702 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7703 | 500)) | |
7704 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7705 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
7706 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 7707 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
7708 | } |
7709 | ||
7710 | /* In units of 100MHz */ | |
7711 | dev_priv->max_delay = max_freq; | |
7712 | dev_priv->min_delay = min_freq; | |
7713 | dev_priv->cur_delay = cur_freq; | |
7714 | ||
8fd26859 CW |
7715 | /* requires MSI enabled */ |
7716 | I915_WRITE(GEN6_PMIER, | |
7717 | GEN6_PM_MBOX_EVENT | | |
7718 | GEN6_PM_THERMAL_EVENT | | |
7719 | GEN6_PM_RP_DOWN_TIMEOUT | | |
7720 | GEN6_PM_RP_UP_THRESHOLD | | |
7721 | GEN6_PM_RP_DOWN_THRESHOLD | | |
7722 | GEN6_PM_RP_UP_EI_EXPIRED | | |
7723 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
3b8d8d91 JB |
7724 | I915_WRITE(GEN6_PMIMR, 0); |
7725 | /* enable all PM interrupts */ | |
7726 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 7727 | |
91355834 | 7728 | __gen6_gt_force_wake_put(dev_priv); |
8fd26859 CW |
7729 | } |
7730 | ||
0cdab21f | 7731 | void intel_enable_clock_gating(struct drm_device *dev) |
652c393a JB |
7732 | { |
7733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 7734 | int pipe; |
652c393a JB |
7735 | |
7736 | /* | |
7737 | * Disable clock gating reported to work incorrectly according to the | |
7738 | * specs, but enable as much else as we can. | |
7739 | */ | |
bad720ff | 7740 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
7741 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
7742 | ||
f00a3ddf | 7743 | if (IS_GEN5(dev)) { |
8956c8bb | 7744 | /* Required for FBC */ |
1ffa325b JB |
7745 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
7746 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
7747 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8956c8bb EA |
7748 | /* Required for CxSR */ |
7749 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
7750 | ||
7751 | I915_WRITE(PCH_3DCGDIS0, | |
7752 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7753 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
06f37751 EA |
7754 | I915_WRITE(PCH_3DCGDIS1, |
7755 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8956c8bb EA |
7756 | } |
7757 | ||
7758 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 | 7759 | |
382b0936 JB |
7760 | /* |
7761 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7762 | * gating for the panel power sequencer or it will fail to | |
7763 | * start up when no ports are active. | |
7764 | */ | |
7765 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
7766 | ||
7f8a8569 ZW |
7767 | /* |
7768 | * According to the spec the following bits should be set in | |
7769 | * order to enable memory self-refresh | |
7770 | * The bit 22/21 of 0x42004 | |
7771 | * The bit 5 of 0x42020 | |
7772 | * The bit 15 of 0x45000 | |
7773 | */ | |
f00a3ddf | 7774 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
7775 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
7776 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7777 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
7778 | I915_WRITE(ILK_DSPCLK_GATE, | |
7779 | (I915_READ(ILK_DSPCLK_GATE) | | |
7780 | ILK_DPARB_CLK_GATE)); | |
7781 | I915_WRITE(DISP_ARB_CTL, | |
7782 | (I915_READ(DISP_ARB_CTL) | | |
7783 | DISP_FBC_WM_DIS)); | |
1398261a YL |
7784 | I915_WRITE(WM3_LP_ILK, 0); |
7785 | I915_WRITE(WM2_LP_ILK, 0); | |
7786 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 7787 | } |
b52eb4dc ZY |
7788 | /* |
7789 | * Based on the document from hardware guys the following bits | |
7790 | * should be set unconditionally in order to enable FBC. | |
7791 | * The bit 22 of 0x42000 | |
7792 | * The bit 22 of 0x42004 | |
7793 | * The bit 7,8,9 of 0x42020. | |
7794 | */ | |
7795 | if (IS_IRONLAKE_M(dev)) { | |
7796 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
7797 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7798 | ILK_FBCQ_DIS); | |
7799 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7800 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7801 | ILK_DPARB_GATE); | |
7802 | I915_WRITE(ILK_DSPCLK_GATE, | |
7803 | I915_READ(ILK_DSPCLK_GATE) | | |
7804 | ILK_DPFC_DIS1 | | |
7805 | ILK_DPFC_DIS2 | | |
7806 | ILK_CLK_FBC); | |
7807 | } | |
de6e2eaf | 7808 | |
67e92af0 EA |
7809 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
7810 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7811 | ILK_ELPIN_409_SELECT); | |
7812 | ||
de6e2eaf EA |
7813 | if (IS_GEN5(dev)) { |
7814 | I915_WRITE(_3D_CHICKEN2, | |
7815 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
7816 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
7817 | } | |
8fd26859 | 7818 | |
1398261a YL |
7819 | if (IS_GEN6(dev)) { |
7820 | I915_WRITE(WM3_LP_ILK, 0); | |
7821 | I915_WRITE(WM2_LP_ILK, 0); | |
7822 | I915_WRITE(WM1_LP_ILK, 0); | |
7823 | ||
7824 | /* | |
7825 | * According to the spec the following bits should be | |
7826 | * set in order to enable memory self-refresh and fbc: | |
7827 | * The bit21 and bit22 of 0x42000 | |
7828 | * The bit21 and bit22 of 0x42004 | |
7829 | * The bit5 and bit7 of 0x42020 | |
7830 | * The bit14 of 0x70180 | |
7831 | * The bit14 of 0x71180 | |
7832 | */ | |
7833 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
7834 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7835 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
7836 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7837 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7838 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
7839 | I915_WRITE(ILK_DSPCLK_GATE, | |
7840 | I915_READ(ILK_DSPCLK_GATE) | | |
7841 | ILK_DPARB_CLK_GATE | | |
7842 | ILK_DPFD_CLK_GATE); | |
7843 | ||
9db4a9c7 JB |
7844 | for_each_pipe(pipe) |
7845 | I915_WRITE(DSPCNTR(pipe), | |
7846 | I915_READ(DSPCNTR(pipe)) | | |
7847 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1398261a | 7848 | } |
c03342fa | 7849 | } else if (IS_G4X(dev)) { |
652c393a JB |
7850 | uint32_t dspclk_gate; |
7851 | I915_WRITE(RENCLK_GATE_D1, 0); | |
7852 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
7853 | GS_UNIT_CLOCK_GATE_DISABLE | | |
7854 | CL_UNIT_CLOCK_GATE_DISABLE); | |
7855 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7856 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
7857 | OVRUNIT_CLOCK_GATE_DISABLE | | |
7858 | OVCUNIT_CLOCK_GATE_DISABLE; | |
7859 | if (IS_GM45(dev)) | |
7860 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
7861 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 7862 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
7863 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
7864 | I915_WRITE(RENCLK_GATE_D2, 0); | |
7865 | I915_WRITE(DSPCLK_GATE_D, 0); | |
7866 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7867 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 7868 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
7869 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
7870 | I965_RCC_CLOCK_GATE_DISABLE | | |
7871 | I965_RCPB_CLOCK_GATE_DISABLE | | |
7872 | I965_ISC_CLOCK_GATE_DISABLE | | |
7873 | I965_FBC_CLOCK_GATE_DISABLE); | |
7874 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 7875 | } else if (IS_GEN3(dev)) { |
652c393a JB |
7876 | u32 dstate = I915_READ(D_STATE); |
7877 | ||
7878 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
7879 | DSTATE_DOT_CLOCK_GATING; | |
7880 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 7881 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
7882 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
7883 | } else if (IS_I830(dev)) { | |
7884 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
7885 | } | |
7886 | } | |
7887 | ||
ac668088 | 7888 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
7889 | { |
7890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7891 | ||
7892 | if (dev_priv->renderctx) { | |
ac668088 CW |
7893 | i915_gem_object_unpin(dev_priv->renderctx); |
7894 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
7895 | dev_priv->renderctx = NULL; |
7896 | } | |
7897 | ||
7898 | if (dev_priv->pwrctx) { | |
ac668088 CW |
7899 | i915_gem_object_unpin(dev_priv->pwrctx); |
7900 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
7901 | dev_priv->pwrctx = NULL; | |
7902 | } | |
7903 | } | |
7904 | ||
7905 | static void ironlake_disable_rc6(struct drm_device *dev) | |
7906 | { | |
7907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7908 | ||
7909 | if (I915_READ(PWRCTXA)) { | |
7910 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
7911 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
7912 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
7913 | 50); | |
0cdab21f CW |
7914 | |
7915 | I915_WRITE(PWRCTXA, 0); | |
7916 | POSTING_READ(PWRCTXA); | |
7917 | ||
ac668088 CW |
7918 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
7919 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 7920 | } |
ac668088 | 7921 | |
99507307 | 7922 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
7923 | } |
7924 | ||
ac668088 | 7925 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
7926 | { |
7927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7928 | ||
ac668088 CW |
7929 | if (dev_priv->renderctx == NULL) |
7930 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
7931 | if (!dev_priv->renderctx) | |
7932 | return -ENOMEM; | |
7933 | ||
7934 | if (dev_priv->pwrctx == NULL) | |
7935 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
7936 | if (!dev_priv->pwrctx) { | |
7937 | ironlake_teardown_rc6(dev); | |
7938 | return -ENOMEM; | |
7939 | } | |
7940 | ||
7941 | return 0; | |
d5bb081b JB |
7942 | } |
7943 | ||
7944 | void ironlake_enable_rc6(struct drm_device *dev) | |
7945 | { | |
7946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7947 | int ret; | |
7948 | ||
ac668088 CW |
7949 | /* rc6 disabled by default due to repeated reports of hanging during |
7950 | * boot and resume. | |
7951 | */ | |
7952 | if (!i915_enable_rc6) | |
7953 | return; | |
7954 | ||
7955 | ret = ironlake_setup_rc6(dev); | |
7956 | if (ret) | |
7957 | return; | |
7958 | ||
d5bb081b JB |
7959 | /* |
7960 | * GPU can automatically power down the render unit if given a page | |
7961 | * to save state. | |
7962 | */ | |
7963 | ret = BEGIN_LP_RING(6); | |
7964 | if (ret) { | |
ac668088 | 7965 | ironlake_teardown_rc6(dev); |
d5bb081b JB |
7966 | return; |
7967 | } | |
ac668088 | 7968 | |
d5bb081b JB |
7969 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
7970 | OUT_RING(MI_SET_CONTEXT); | |
7971 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
7972 | MI_MM_SPACE_GTT | | |
7973 | MI_SAVE_EXT_STATE_EN | | |
7974 | MI_RESTORE_EXT_STATE_EN | | |
7975 | MI_RESTORE_INHIBIT); | |
7976 | OUT_RING(MI_SUSPEND_FLUSH); | |
7977 | OUT_RING(MI_NOOP); | |
7978 | OUT_RING(MI_FLUSH); | |
7979 | ADVANCE_LP_RING(); | |
7980 | ||
7981 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); | |
7982 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
7983 | } | |
7984 | ||
ac668088 | 7985 | |
e70236a8 JB |
7986 | /* Set up chip specific display functions */ |
7987 | static void intel_init_display(struct drm_device *dev) | |
7988 | { | |
7989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7990 | ||
7991 | /* We always want a DPMS function */ | |
f564048e | 7992 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 7993 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e EA |
7994 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
7995 | } else { | |
e70236a8 | 7996 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e EA |
7997 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
7998 | } | |
e70236a8 | 7999 | |
ee5382ae | 8000 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8001 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8002 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8003 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8004 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8005 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8006 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8007 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8008 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8009 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8010 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8011 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8012 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8013 | } | |
74dff282 | 8014 | /* 855GM needs testing */ |
e70236a8 JB |
8015 | } |
8016 | ||
8017 | /* Returns the core display clock speed */ | |
f2b115e6 | 8018 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8019 | dev_priv->display.get_display_clock_speed = |
8020 | i945_get_display_clock_speed; | |
8021 | else if (IS_I915G(dev)) | |
8022 | dev_priv->display.get_display_clock_speed = | |
8023 | i915_get_display_clock_speed; | |
f2b115e6 | 8024 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8025 | dev_priv->display.get_display_clock_speed = |
8026 | i9xx_misc_get_display_clock_speed; | |
8027 | else if (IS_I915GM(dev)) | |
8028 | dev_priv->display.get_display_clock_speed = | |
8029 | i915gm_get_display_clock_speed; | |
8030 | else if (IS_I865G(dev)) | |
8031 | dev_priv->display.get_display_clock_speed = | |
8032 | i865_get_display_clock_speed; | |
f0f8a9ce | 8033 | else if (IS_I85X(dev)) |
e70236a8 JB |
8034 | dev_priv->display.get_display_clock_speed = |
8035 | i855_get_display_clock_speed; | |
8036 | else /* 852, 830 */ | |
8037 | dev_priv->display.get_display_clock_speed = | |
8038 | i830_get_display_clock_speed; | |
8039 | ||
8040 | /* For FIFO watermark updates */ | |
7f8a8569 | 8041 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 8042 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8043 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8044 | dev_priv->display.update_wm = ironlake_update_wm; | |
8045 | else { | |
8046 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8047 | "Disable CxSR\n"); | |
8048 | dev_priv->display.update_wm = NULL; | |
1398261a YL |
8049 | } |
8050 | } else if (IS_GEN6(dev)) { | |
8051 | if (SNB_READ_WM0_LATENCY()) { | |
8052 | dev_priv->display.update_wm = sandybridge_update_wm; | |
8053 | } else { | |
8054 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8055 | "Disable CxSR\n"); | |
8056 | dev_priv->display.update_wm = NULL; | |
7f8a8569 ZW |
8057 | } |
8058 | } else | |
8059 | dev_priv->display.update_wm = NULL; | |
8060 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8061 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8062 | dev_priv->is_ddr3, |
d4294342 ZY |
8063 | dev_priv->fsb_freq, |
8064 | dev_priv->mem_freq)) { | |
8065 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8066 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8067 | "disabling CxSR\n", |
95534263 | 8068 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
8069 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8070 | /* Disable CxSR and never update its watermark again */ | |
8071 | pineview_disable_cxsr(dev); | |
8072 | dev_priv->display.update_wm = NULL; | |
8073 | } else | |
8074 | dev_priv->display.update_wm = pineview_update_wm; | |
8075 | } else if (IS_G4X(dev)) | |
e70236a8 | 8076 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 8077 | else if (IS_GEN4(dev)) |
e70236a8 | 8078 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 8079 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
8080 | dev_priv->display.update_wm = i9xx_update_wm; |
8081 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
8082 | } else if (IS_I85X(dev)) { |
8083 | dev_priv->display.update_wm = i9xx_update_wm; | |
8084 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 8085 | } else { |
8f4695ed AJ |
8086 | dev_priv->display.update_wm = i830_update_wm; |
8087 | if (IS_845G(dev)) | |
e70236a8 JB |
8088 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8089 | else | |
8090 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
8091 | } |
8092 | } | |
8093 | ||
b690e96c JB |
8094 | /* |
8095 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8096 | * resume, or other times. This quirk makes sure that's the case for | |
8097 | * affected systems. | |
8098 | */ | |
8099 | static void quirk_pipea_force (struct drm_device *dev) | |
8100 | { | |
8101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8102 | ||
8103 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
8104 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
8105 | } | |
8106 | ||
8107 | struct intel_quirk { | |
8108 | int device; | |
8109 | int subsystem_vendor; | |
8110 | int subsystem_device; | |
8111 | void (*hook)(struct drm_device *dev); | |
8112 | }; | |
8113 | ||
8114 | struct intel_quirk intel_quirks[] = { | |
8115 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
8116 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
8117 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
8118 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
8119 | ||
8120 | /* Thinkpad R31 needs pipe A force quirk */ | |
8121 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
8122 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
8123 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8124 | ||
8125 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
8126 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
8127 | /* ThinkPad X40 needs pipe A force quirk */ | |
8128 | ||
8129 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
8130 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8131 | ||
8132 | /* 855 & before need to leave pipe A & dpll A up */ | |
8133 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
8134 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
8135 | }; | |
8136 | ||
8137 | static void intel_init_quirks(struct drm_device *dev) | |
8138 | { | |
8139 | struct pci_dev *d = dev->pdev; | |
8140 | int i; | |
8141 | ||
8142 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8143 | struct intel_quirk *q = &intel_quirks[i]; | |
8144 | ||
8145 | if (d->device == q->device && | |
8146 | (d->subsystem_vendor == q->subsystem_vendor || | |
8147 | q->subsystem_vendor == PCI_ANY_ID) && | |
8148 | (d->subsystem_device == q->subsystem_device || | |
8149 | q->subsystem_device == PCI_ANY_ID)) | |
8150 | q->hook(dev); | |
8151 | } | |
8152 | } | |
8153 | ||
9cce37f4 JB |
8154 | /* Disable the VGA plane that we never use */ |
8155 | static void i915_disable_vga(struct drm_device *dev) | |
8156 | { | |
8157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8158 | u8 sr1; | |
8159 | u32 vga_reg; | |
8160 | ||
8161 | if (HAS_PCH_SPLIT(dev)) | |
8162 | vga_reg = CPU_VGACNTRL; | |
8163 | else | |
8164 | vga_reg = VGACNTRL; | |
8165 | ||
8166 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8167 | outb(1, VGA_SR_INDEX); | |
8168 | sr1 = inb(VGA_SR_DATA); | |
8169 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8170 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8171 | udelay(300); | |
8172 | ||
8173 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8174 | POSTING_READ(vga_reg); | |
8175 | } | |
8176 | ||
79e53945 JB |
8177 | void intel_modeset_init(struct drm_device *dev) |
8178 | { | |
652c393a | 8179 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
8180 | int i; |
8181 | ||
8182 | drm_mode_config_init(dev); | |
8183 | ||
8184 | dev->mode_config.min_width = 0; | |
8185 | dev->mode_config.min_height = 0; | |
8186 | ||
8187 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
8188 | ||
b690e96c JB |
8189 | intel_init_quirks(dev); |
8190 | ||
e70236a8 JB |
8191 | intel_init_display(dev); |
8192 | ||
a6c45cf0 CW |
8193 | if (IS_GEN2(dev)) { |
8194 | dev->mode_config.max_width = 2048; | |
8195 | dev->mode_config.max_height = 2048; | |
8196 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8197 | dev->mode_config.max_width = 4096; |
8198 | dev->mode_config.max_height = 4096; | |
79e53945 | 8199 | } else { |
a6c45cf0 CW |
8200 | dev->mode_config.max_width = 8192; |
8201 | dev->mode_config.max_height = 8192; | |
79e53945 | 8202 | } |
35c3047a | 8203 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 8204 | |
28c97730 | 8205 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8206 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8207 | |
a3524f1b | 8208 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
8209 | intel_crtc_init(dev, i); |
8210 | } | |
8211 | ||
8212 | intel_setup_outputs(dev); | |
652c393a | 8213 | |
0cdab21f | 8214 | intel_enable_clock_gating(dev); |
652c393a | 8215 | |
9cce37f4 JB |
8216 | /* Just disable it once at startup */ |
8217 | i915_disable_vga(dev); | |
8218 | ||
7648fa99 | 8219 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 8220 | ironlake_enable_drps(dev); |
7648fa99 JB |
8221 | intel_init_emon(dev); |
8222 | } | |
f97108d1 | 8223 | |
3b8d8d91 JB |
8224 | if (IS_GEN6(dev)) |
8225 | gen6_enable_rps(dev_priv); | |
8226 | ||
ac668088 | 8227 | if (IS_IRONLAKE_M(dev)) |
d5bb081b | 8228 | ironlake_enable_rc6(dev); |
d5bb081b | 8229 | |
652c393a JB |
8230 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
8231 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
8232 | (unsigned long)dev); | |
02e792fb DV |
8233 | |
8234 | intel_setup_overlay(dev); | |
79e53945 JB |
8235 | } |
8236 | ||
8237 | void intel_modeset_cleanup(struct drm_device *dev) | |
8238 | { | |
652c393a JB |
8239 | struct drm_i915_private *dev_priv = dev->dev_private; |
8240 | struct drm_crtc *crtc; | |
8241 | struct intel_crtc *intel_crtc; | |
8242 | ||
f87ea761 | 8243 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
8244 | mutex_lock(&dev->struct_mutex); |
8245 | ||
723bfd70 JB |
8246 | intel_unregister_dsm_handler(); |
8247 | ||
8248 | ||
652c393a JB |
8249 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8250 | /* Skip inactive CRTCs */ | |
8251 | if (!crtc->fb) | |
8252 | continue; | |
8253 | ||
8254 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 8255 | intel_increase_pllclock(crtc); |
652c393a JB |
8256 | } |
8257 | ||
e70236a8 JB |
8258 | if (dev_priv->display.disable_fbc) |
8259 | dev_priv->display.disable_fbc(dev); | |
8260 | ||
f97108d1 JB |
8261 | if (IS_IRONLAKE_M(dev)) |
8262 | ironlake_disable_drps(dev); | |
3b8d8d91 JB |
8263 | if (IS_GEN6(dev)) |
8264 | gen6_disable_rps(dev); | |
f97108d1 | 8265 | |
d5bb081b JB |
8266 | if (IS_IRONLAKE_M(dev)) |
8267 | ironlake_disable_rc6(dev); | |
0cdab21f | 8268 | |
69341a5e KH |
8269 | mutex_unlock(&dev->struct_mutex); |
8270 | ||
6c0d9350 DV |
8271 | /* Disable the irq before mode object teardown, for the irq might |
8272 | * enqueue unpin/hotplug work. */ | |
8273 | drm_irq_uninstall(dev); | |
8274 | cancel_work_sync(&dev_priv->hotplug_work); | |
8275 | ||
3dec0095 DV |
8276 | /* Shut off idle work before the crtcs get freed. */ |
8277 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
8278 | intel_crtc = to_intel_crtc(crtc); | |
8279 | del_timer_sync(&intel_crtc->idle_timer); | |
8280 | } | |
8281 | del_timer_sync(&dev_priv->idle_timer); | |
8282 | cancel_work_sync(&dev_priv->idle_work); | |
8283 | ||
79e53945 JB |
8284 | drm_mode_config_cleanup(dev); |
8285 | } | |
8286 | ||
f1c79df3 ZW |
8287 | /* |
8288 | * Return which encoder is currently attached for connector. | |
8289 | */ | |
df0e9248 | 8290 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 8291 | { |
df0e9248 CW |
8292 | return &intel_attached_encoder(connector)->base; |
8293 | } | |
f1c79df3 | 8294 | |
df0e9248 CW |
8295 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8296 | struct intel_encoder *encoder) | |
8297 | { | |
8298 | connector->encoder = encoder; | |
8299 | drm_mode_connector_attach_encoder(&connector->base, | |
8300 | &encoder->base); | |
79e53945 | 8301 | } |
28d52043 DA |
8302 | |
8303 | /* | |
8304 | * set vga decode state - true == enable VGA decode | |
8305 | */ | |
8306 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
8307 | { | |
8308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8309 | u16 gmch_ctrl; | |
8310 | ||
8311 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
8312 | if (state) | |
8313 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
8314 | else | |
8315 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
8316 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
8317 | return 0; | |
8318 | } | |
c4a1d9e4 CW |
8319 | |
8320 | #ifdef CONFIG_DEBUG_FS | |
8321 | #include <linux/seq_file.h> | |
8322 | ||
8323 | struct intel_display_error_state { | |
8324 | struct intel_cursor_error_state { | |
8325 | u32 control; | |
8326 | u32 position; | |
8327 | u32 base; | |
8328 | u32 size; | |
8329 | } cursor[2]; | |
8330 | ||
8331 | struct intel_pipe_error_state { | |
8332 | u32 conf; | |
8333 | u32 source; | |
8334 | ||
8335 | u32 htotal; | |
8336 | u32 hblank; | |
8337 | u32 hsync; | |
8338 | u32 vtotal; | |
8339 | u32 vblank; | |
8340 | u32 vsync; | |
8341 | } pipe[2]; | |
8342 | ||
8343 | struct intel_plane_error_state { | |
8344 | u32 control; | |
8345 | u32 stride; | |
8346 | u32 size; | |
8347 | u32 pos; | |
8348 | u32 addr; | |
8349 | u32 surface; | |
8350 | u32 tile_offset; | |
8351 | } plane[2]; | |
8352 | }; | |
8353 | ||
8354 | struct intel_display_error_state * | |
8355 | intel_display_capture_error_state(struct drm_device *dev) | |
8356 | { | |
8357 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8358 | struct intel_display_error_state *error; | |
8359 | int i; | |
8360 | ||
8361 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
8362 | if (error == NULL) | |
8363 | return NULL; | |
8364 | ||
8365 | for (i = 0; i < 2; i++) { | |
8366 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
8367 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
8368 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
8369 | ||
8370 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
8371 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
8372 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
8373 | error->plane[i].pos= I915_READ(DSPPOS(i)); | |
8374 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
8375 | if (INTEL_INFO(dev)->gen >= 4) { | |
8376 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
8377 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
8378 | } | |
8379 | ||
8380 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
8381 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
8382 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
8383 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
8384 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
8385 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
8386 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
8387 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
8388 | } | |
8389 | ||
8390 | return error; | |
8391 | } | |
8392 | ||
8393 | void | |
8394 | intel_display_print_error_state(struct seq_file *m, | |
8395 | struct drm_device *dev, | |
8396 | struct intel_display_error_state *error) | |
8397 | { | |
8398 | int i; | |
8399 | ||
8400 | for (i = 0; i < 2; i++) { | |
8401 | seq_printf(m, "Pipe [%d]:\n", i); | |
8402 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
8403 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
8404 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
8405 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
8406 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
8407 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
8408 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
8409 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
8410 | ||
8411 | seq_printf(m, "Plane [%d]:\n", i); | |
8412 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
8413 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
8414 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
8415 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
8416 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
8417 | if (INTEL_INFO(dev)->gen >= 4) { | |
8418 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
8419 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
8420 | } | |
8421 | ||
8422 | seq_printf(m, "Cursor [%d]:\n", i); | |
8423 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
8424 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
8425 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
8426 | } | |
8427 | } | |
8428 | #endif |