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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 47 | |
f1f644dc JB |
48 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
49 | struct intel_crtc_config *pipe_config); | |
50 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, | |
51 | struct intel_crtc_config *pipe_config); | |
52 | ||
e7457a9a DL |
53 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
54 | int x, int y, struct drm_framebuffer *old_fb); | |
55 | ||
56 | ||
79e53945 | 57 | typedef struct { |
0206e353 | 58 | int min, max; |
79e53945 JB |
59 | } intel_range_t; |
60 | ||
61 | typedef struct { | |
0206e353 AJ |
62 | int dot_limit; |
63 | int p2_slow, p2_fast; | |
79e53945 JB |
64 | } intel_p2_t; |
65 | ||
d4906093 ML |
66 | typedef struct intel_limit intel_limit_t; |
67 | struct intel_limit { | |
0206e353 AJ |
68 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
69 | intel_p2_t p2; | |
d4906093 | 70 | }; |
79e53945 | 71 | |
2377b741 JB |
72 | /* FDI */ |
73 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
74 | ||
d2acd215 DV |
75 | int |
76 | intel_pch_rawclk(struct drm_device *dev) | |
77 | { | |
78 | struct drm_i915_private *dev_priv = dev->dev_private; | |
79 | ||
80 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
81 | ||
82 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
83 | } | |
84 | ||
021357ac CW |
85 | static inline u32 /* units of 100MHz */ |
86 | intel_fdi_link_freq(struct drm_device *dev) | |
87 | { | |
8b99e68c CW |
88 | if (IS_GEN5(dev)) { |
89 | struct drm_i915_private *dev_priv = dev->dev_private; | |
90 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
91 | } else | |
92 | return 27; | |
021357ac CW |
93 | } |
94 | ||
5d536e28 | 95 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 AJ |
96 | .dot = { .min = 25000, .max = 350000 }, |
97 | .vco = { .min = 930000, .max = 1400000 }, | |
98 | .n = { .min = 3, .max = 16 }, | |
99 | .m = { .min = 96, .max = 140 }, | |
100 | .m1 = { .min = 18, .max = 26 }, | |
101 | .m2 = { .min = 6, .max = 16 }, | |
102 | .p = { .min = 4, .max = 128 }, | |
103 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
104 | .p2 = { .dot_limit = 165000, |
105 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
106 | }; |
107 | ||
5d536e28 DV |
108 | static const intel_limit_t intel_limits_i8xx_dvo = { |
109 | .dot = { .min = 25000, .max = 350000 }, | |
110 | .vco = { .min = 930000, .max = 1400000 }, | |
111 | .n = { .min = 3, .max = 16 }, | |
112 | .m = { .min = 96, .max = 140 }, | |
113 | .m1 = { .min = 18, .max = 26 }, | |
114 | .m2 = { .min = 6, .max = 16 }, | |
115 | .p = { .min = 4, .max = 128 }, | |
116 | .p1 = { .min = 2, .max = 33 }, | |
117 | .p2 = { .dot_limit = 165000, | |
118 | .p2_slow = 4, .p2_fast = 4 }, | |
119 | }; | |
120 | ||
e4b36699 | 121 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 AJ |
122 | .dot = { .min = 25000, .max = 350000 }, |
123 | .vco = { .min = 930000, .max = 1400000 }, | |
124 | .n = { .min = 3, .max = 16 }, | |
125 | .m = { .min = 96, .max = 140 }, | |
126 | .m1 = { .min = 18, .max = 26 }, | |
127 | .m2 = { .min = 6, .max = 16 }, | |
128 | .p = { .min = 4, .max = 128 }, | |
129 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
130 | .p2 = { .dot_limit = 165000, |
131 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 132 | }; |
273e27ca | 133 | |
e4b36699 | 134 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
135 | .dot = { .min = 20000, .max = 400000 }, |
136 | .vco = { .min = 1400000, .max = 2800000 }, | |
137 | .n = { .min = 1, .max = 6 }, | |
138 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
139 | .m1 = { .min = 8, .max = 18 }, |
140 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
141 | .p = { .min = 5, .max = 80 }, |
142 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
143 | .p2 = { .dot_limit = 200000, |
144 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
145 | }; |
146 | ||
147 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
148 | .dot = { .min = 20000, .max = 400000 }, |
149 | .vco = { .min = 1400000, .max = 2800000 }, | |
150 | .n = { .min = 1, .max = 6 }, | |
151 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
152 | .m1 = { .min = 8, .max = 18 }, |
153 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
154 | .p = { .min = 7, .max = 98 }, |
155 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
156 | .p2 = { .dot_limit = 112000, |
157 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
158 | }; |
159 | ||
273e27ca | 160 | |
e4b36699 | 161 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
162 | .dot = { .min = 25000, .max = 270000 }, |
163 | .vco = { .min = 1750000, .max = 3500000}, | |
164 | .n = { .min = 1, .max = 4 }, | |
165 | .m = { .min = 104, .max = 138 }, | |
166 | .m1 = { .min = 17, .max = 23 }, | |
167 | .m2 = { .min = 5, .max = 11 }, | |
168 | .p = { .min = 10, .max = 30 }, | |
169 | .p1 = { .min = 1, .max = 3}, | |
170 | .p2 = { .dot_limit = 270000, | |
171 | .p2_slow = 10, | |
172 | .p2_fast = 10 | |
044c7c41 | 173 | }, |
e4b36699 KP |
174 | }; |
175 | ||
176 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
177 | .dot = { .min = 22000, .max = 400000 }, |
178 | .vco = { .min = 1750000, .max = 3500000}, | |
179 | .n = { .min = 1, .max = 4 }, | |
180 | .m = { .min = 104, .max = 138 }, | |
181 | .m1 = { .min = 16, .max = 23 }, | |
182 | .m2 = { .min = 5, .max = 11 }, | |
183 | .p = { .min = 5, .max = 80 }, | |
184 | .p1 = { .min = 1, .max = 8}, | |
185 | .p2 = { .dot_limit = 165000, | |
186 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
187 | }; |
188 | ||
189 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
190 | .dot = { .min = 20000, .max = 115000 }, |
191 | .vco = { .min = 1750000, .max = 3500000 }, | |
192 | .n = { .min = 1, .max = 3 }, | |
193 | .m = { .min = 104, .max = 138 }, | |
194 | .m1 = { .min = 17, .max = 23 }, | |
195 | .m2 = { .min = 5, .max = 11 }, | |
196 | .p = { .min = 28, .max = 112 }, | |
197 | .p1 = { .min = 2, .max = 8 }, | |
198 | .p2 = { .dot_limit = 0, | |
199 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 200 | }, |
e4b36699 KP |
201 | }; |
202 | ||
203 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
204 | .dot = { .min = 80000, .max = 224000 }, |
205 | .vco = { .min = 1750000, .max = 3500000 }, | |
206 | .n = { .min = 1, .max = 3 }, | |
207 | .m = { .min = 104, .max = 138 }, | |
208 | .m1 = { .min = 17, .max = 23 }, | |
209 | .m2 = { .min = 5, .max = 11 }, | |
210 | .p = { .min = 14, .max = 42 }, | |
211 | .p1 = { .min = 2, .max = 6 }, | |
212 | .p2 = { .dot_limit = 0, | |
213 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 214 | }, |
e4b36699 KP |
215 | }; |
216 | ||
f2b115e6 | 217 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
218 | .dot = { .min = 20000, .max = 400000}, |
219 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 220 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
221 | .n = { .min = 3, .max = 6 }, |
222 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 223 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
224 | .m1 = { .min = 0, .max = 0 }, |
225 | .m2 = { .min = 0, .max = 254 }, | |
226 | .p = { .min = 5, .max = 80 }, | |
227 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
228 | .p2 = { .dot_limit = 200000, |
229 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
230 | }; |
231 | ||
f2b115e6 | 232 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
233 | .dot = { .min = 20000, .max = 400000 }, |
234 | .vco = { .min = 1700000, .max = 3500000 }, | |
235 | .n = { .min = 3, .max = 6 }, | |
236 | .m = { .min = 2, .max = 256 }, | |
237 | .m1 = { .min = 0, .max = 0 }, | |
238 | .m2 = { .min = 0, .max = 254 }, | |
239 | .p = { .min = 7, .max = 112 }, | |
240 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
241 | .p2 = { .dot_limit = 112000, |
242 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
243 | }; |
244 | ||
273e27ca EA |
245 | /* Ironlake / Sandybridge |
246 | * | |
247 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
248 | * the range value for them is (actual_value - 2). | |
249 | */ | |
b91ad0ec | 250 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
251 | .dot = { .min = 25000, .max = 350000 }, |
252 | .vco = { .min = 1760000, .max = 3510000 }, | |
253 | .n = { .min = 1, .max = 5 }, | |
254 | .m = { .min = 79, .max = 127 }, | |
255 | .m1 = { .min = 12, .max = 22 }, | |
256 | .m2 = { .min = 5, .max = 9 }, | |
257 | .p = { .min = 5, .max = 80 }, | |
258 | .p1 = { .min = 1, .max = 8 }, | |
259 | .p2 = { .dot_limit = 225000, | |
260 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
261 | }; |
262 | ||
b91ad0ec | 263 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
264 | .dot = { .min = 25000, .max = 350000 }, |
265 | .vco = { .min = 1760000, .max = 3510000 }, | |
266 | .n = { .min = 1, .max = 3 }, | |
267 | .m = { .min = 79, .max = 118 }, | |
268 | .m1 = { .min = 12, .max = 22 }, | |
269 | .m2 = { .min = 5, .max = 9 }, | |
270 | .p = { .min = 28, .max = 112 }, | |
271 | .p1 = { .min = 2, .max = 8 }, | |
272 | .p2 = { .dot_limit = 225000, | |
273 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
274 | }; |
275 | ||
276 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
277 | .dot = { .min = 25000, .max = 350000 }, |
278 | .vco = { .min = 1760000, .max = 3510000 }, | |
279 | .n = { .min = 1, .max = 3 }, | |
280 | .m = { .min = 79, .max = 127 }, | |
281 | .m1 = { .min = 12, .max = 22 }, | |
282 | .m2 = { .min = 5, .max = 9 }, | |
283 | .p = { .min = 14, .max = 56 }, | |
284 | .p1 = { .min = 2, .max = 8 }, | |
285 | .p2 = { .dot_limit = 225000, | |
286 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
287 | }; |
288 | ||
273e27ca | 289 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 290 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
291 | .dot = { .min = 25000, .max = 350000 }, |
292 | .vco = { .min = 1760000, .max = 3510000 }, | |
293 | .n = { .min = 1, .max = 2 }, | |
294 | .m = { .min = 79, .max = 126 }, | |
295 | .m1 = { .min = 12, .max = 22 }, | |
296 | .m2 = { .min = 5, .max = 9 }, | |
297 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 298 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
299 | .p2 = { .dot_limit = 225000, |
300 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
301 | }; |
302 | ||
303 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 350000 }, |
305 | .vco = { .min = 1760000, .max = 3510000 }, | |
306 | .n = { .min = 1, .max = 3 }, | |
307 | .m = { .min = 79, .max = 126 }, | |
308 | .m1 = { .min = 12, .max = 22 }, | |
309 | .m2 = { .min = 5, .max = 9 }, | |
310 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 311 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
312 | .p2 = { .dot_limit = 225000, |
313 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
314 | }; |
315 | ||
a0c4da24 JB |
316 | static const intel_limit_t intel_limits_vlv_dac = { |
317 | .dot = { .min = 25000, .max = 270000 }, | |
318 | .vco = { .min = 4000000, .max = 6000000 }, | |
319 | .n = { .min = 1, .max = 7 }, | |
320 | .m = { .min = 22, .max = 450 }, /* guess */ | |
321 | .m1 = { .min = 2, .max = 3 }, | |
322 | .m2 = { .min = 11, .max = 156 }, | |
323 | .p = { .min = 10, .max = 30 }, | |
75e53986 | 324 | .p1 = { .min = 1, .max = 3 }, |
a0c4da24 JB |
325 | .p2 = { .dot_limit = 270000, |
326 | .p2_slow = 2, .p2_fast = 20 }, | |
a0c4da24 JB |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
75e53986 DV |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 JB |
332 | .n = { .min = 1, .max = 7 }, |
333 | .m = { .min = 60, .max = 300 }, /* guess */ | |
334 | .m1 = { .min = 2, .max = 3 }, | |
335 | .m2 = { .min = 11, .max = 156 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 2, .max = 3 }, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 2, .p2_fast = 20 }, | |
a0c4da24 JB |
340 | }; |
341 | ||
342 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
343 | .dot = { .min = 25000, .max = 270000 }, |
344 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 345 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 346 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
347 | .m1 = { .min = 2, .max = 3 }, |
348 | .m2 = { .min = 11, .max = 156 }, | |
349 | .p = { .min = 10, .max = 30 }, | |
75e53986 | 350 | .p1 = { .min = 1, .max = 3 }, |
a0c4da24 JB |
351 | .p2 = { .dot_limit = 270000, |
352 | .p2_slow = 2, .p2_fast = 20 }, | |
a0c4da24 JB |
353 | }; |
354 | ||
1b894b59 CW |
355 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
356 | int refclk) | |
2c07245f | 357 | { |
b91ad0ec | 358 | struct drm_device *dev = crtc->dev; |
2c07245f | 359 | const intel_limit_t *limit; |
b91ad0ec ZW |
360 | |
361 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 362 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 363 | if (refclk == 100000) |
b91ad0ec ZW |
364 | limit = &intel_limits_ironlake_dual_lvds_100m; |
365 | else | |
366 | limit = &intel_limits_ironlake_dual_lvds; | |
367 | } else { | |
1b894b59 | 368 | if (refclk == 100000) |
b91ad0ec ZW |
369 | limit = &intel_limits_ironlake_single_lvds_100m; |
370 | else | |
371 | limit = &intel_limits_ironlake_single_lvds; | |
372 | } | |
c6bb3538 | 373 | } else |
b91ad0ec | 374 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
375 | |
376 | return limit; | |
377 | } | |
378 | ||
044c7c41 ML |
379 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
380 | { | |
381 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
382 | const intel_limit_t *limit; |
383 | ||
384 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 385 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 386 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 387 | else |
e4b36699 | 388 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
389 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
390 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 391 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 392 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 393 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 394 | } else /* The option is for other outputs */ |
e4b36699 | 395 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
396 | |
397 | return limit; | |
398 | } | |
399 | ||
1b894b59 | 400 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
401 | { |
402 | struct drm_device *dev = crtc->dev; | |
403 | const intel_limit_t *limit; | |
404 | ||
bad720ff | 405 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 406 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 407 | else if (IS_G4X(dev)) { |
044c7c41 | 408 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 409 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 410 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 411 | limit = &intel_limits_pineview_lvds; |
2177832f | 412 | else |
f2b115e6 | 413 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
414 | } else if (IS_VALLEYVIEW(dev)) { |
415 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
416 | limit = &intel_limits_vlv_dac; | |
417 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
418 | limit = &intel_limits_vlv_hdmi; | |
419 | else | |
420 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
421 | } else if (!IS_GEN2(dev)) { |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
423 | limit = &intel_limits_i9xx_lvds; | |
424 | else | |
425 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
426 | } else { |
427 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 428 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 429 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 430 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
431 | else |
432 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
433 | } |
434 | return limit; | |
435 | } | |
436 | ||
f2b115e6 AJ |
437 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
438 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 439 | { |
2177832f SL |
440 | clock->m = clock->m2 + 2; |
441 | clock->p = clock->p1 * clock->p2; | |
442 | clock->vco = refclk * clock->m / clock->n; | |
443 | clock->dot = clock->vco / clock->p; | |
444 | } | |
445 | ||
7429e9d4 DV |
446 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
447 | { | |
448 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
449 | } | |
450 | ||
ac58c3f0 | 451 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 452 | { |
7429e9d4 | 453 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 JB |
454 | clock->p = clock->p1 * clock->p2; |
455 | clock->vco = refclk * clock->m / (clock->n + 2); | |
456 | clock->dot = clock->vco / clock->p; | |
457 | } | |
458 | ||
79e53945 JB |
459 | /** |
460 | * Returns whether any output on the specified pipe is of the specified type | |
461 | */ | |
4ef69c7a | 462 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 463 | { |
4ef69c7a | 464 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
465 | struct intel_encoder *encoder; |
466 | ||
6c2b7c12 DV |
467 | for_each_encoder_on_crtc(dev, crtc, encoder) |
468 | if (encoder->type == type) | |
4ef69c7a CW |
469 | return true; |
470 | ||
471 | return false; | |
79e53945 JB |
472 | } |
473 | ||
7c04d1d9 | 474 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
475 | /** |
476 | * Returns whether the given set of divisors are valid for a given refclk with | |
477 | * the given connectors. | |
478 | */ | |
479 | ||
1b894b59 CW |
480 | static bool intel_PLL_is_valid(struct drm_device *dev, |
481 | const intel_limit_t *limit, | |
482 | const intel_clock_t *clock) | |
79e53945 | 483 | { |
79e53945 | 484 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 485 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 486 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 487 | INTELPllInvalid("p out of range\n"); |
79e53945 | 488 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 489 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 490 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 491 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 492 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 493 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 494 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 495 | INTELPllInvalid("m out of range\n"); |
79e53945 | 496 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 497 | INTELPllInvalid("n out of range\n"); |
79e53945 | 498 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 499 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
500 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
501 | * connector, etc., rather than just a single range. | |
502 | */ | |
503 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 504 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
505 | |
506 | return true; | |
507 | } | |
508 | ||
d4906093 | 509 | static bool |
ee9300bb | 510 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
511 | int target, int refclk, intel_clock_t *match_clock, |
512 | intel_clock_t *best_clock) | |
79e53945 JB |
513 | { |
514 | struct drm_device *dev = crtc->dev; | |
79e53945 | 515 | intel_clock_t clock; |
79e53945 JB |
516 | int err = target; |
517 | ||
a210b028 | 518 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 519 | /* |
a210b028 DV |
520 | * For LVDS just rely on its current settings for dual-channel. |
521 | * We haven't figured out how to reliably set up different | |
522 | * single/dual channel state, if we even can. | |
79e53945 | 523 | */ |
1974cad0 | 524 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
525 | clock.p2 = limit->p2.p2_fast; |
526 | else | |
527 | clock.p2 = limit->p2.p2_slow; | |
528 | } else { | |
529 | if (target < limit->p2.dot_limit) | |
530 | clock.p2 = limit->p2.p2_slow; | |
531 | else | |
532 | clock.p2 = limit->p2.p2_fast; | |
533 | } | |
534 | ||
0206e353 | 535 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 536 | |
42158660 ZY |
537 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
538 | clock.m1++) { | |
539 | for (clock.m2 = limit->m2.min; | |
540 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 541 | if (clock.m2 >= clock.m1) |
42158660 ZY |
542 | break; |
543 | for (clock.n = limit->n.min; | |
544 | clock.n <= limit->n.max; clock.n++) { | |
545 | for (clock.p1 = limit->p1.min; | |
546 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
547 | int this_err; |
548 | ||
ac58c3f0 DV |
549 | i9xx_clock(refclk, &clock); |
550 | if (!intel_PLL_is_valid(dev, limit, | |
551 | &clock)) | |
552 | continue; | |
553 | if (match_clock && | |
554 | clock.p != match_clock->p) | |
555 | continue; | |
556 | ||
557 | this_err = abs(clock.dot - target); | |
558 | if (this_err < err) { | |
559 | *best_clock = clock; | |
560 | err = this_err; | |
561 | } | |
562 | } | |
563 | } | |
564 | } | |
565 | } | |
566 | ||
567 | return (err != target); | |
568 | } | |
569 | ||
570 | static bool | |
ee9300bb DV |
571 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
572 | int target, int refclk, intel_clock_t *match_clock, | |
573 | intel_clock_t *best_clock) | |
79e53945 JB |
574 | { |
575 | struct drm_device *dev = crtc->dev; | |
79e53945 | 576 | intel_clock_t clock; |
79e53945 JB |
577 | int err = target; |
578 | ||
a210b028 | 579 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 580 | /* |
a210b028 DV |
581 | * For LVDS just rely on its current settings for dual-channel. |
582 | * We haven't figured out how to reliably set up different | |
583 | * single/dual channel state, if we even can. | |
79e53945 | 584 | */ |
1974cad0 | 585 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
586 | clock.p2 = limit->p2.p2_fast; |
587 | else | |
588 | clock.p2 = limit->p2.p2_slow; | |
589 | } else { | |
590 | if (target < limit->p2.dot_limit) | |
591 | clock.p2 = limit->p2.p2_slow; | |
592 | else | |
593 | clock.p2 = limit->p2.p2_fast; | |
594 | } | |
595 | ||
0206e353 | 596 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 597 | |
42158660 ZY |
598 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
599 | clock.m1++) { | |
600 | for (clock.m2 = limit->m2.min; | |
601 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
602 | for (clock.n = limit->n.min; |
603 | clock.n <= limit->n.max; clock.n++) { | |
604 | for (clock.p1 = limit->p1.min; | |
605 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
606 | int this_err; |
607 | ||
ac58c3f0 | 608 | pineview_clock(refclk, &clock); |
1b894b59 CW |
609 | if (!intel_PLL_is_valid(dev, limit, |
610 | &clock)) | |
79e53945 | 611 | continue; |
cec2f356 SP |
612 | if (match_clock && |
613 | clock.p != match_clock->p) | |
614 | continue; | |
79e53945 JB |
615 | |
616 | this_err = abs(clock.dot - target); | |
617 | if (this_err < err) { | |
618 | *best_clock = clock; | |
619 | err = this_err; | |
620 | } | |
621 | } | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
626 | return (err != target); | |
627 | } | |
628 | ||
d4906093 | 629 | static bool |
ee9300bb DV |
630 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
631 | int target, int refclk, intel_clock_t *match_clock, | |
632 | intel_clock_t *best_clock) | |
d4906093 ML |
633 | { |
634 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
635 | intel_clock_t clock; |
636 | int max_n; | |
637 | bool found; | |
6ba770dc AJ |
638 | /* approximately equals target * 0.00585 */ |
639 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
640 | found = false; |
641 | ||
642 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 643 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
644 | clock.p2 = limit->p2.p2_fast; |
645 | else | |
646 | clock.p2 = limit->p2.p2_slow; | |
647 | } else { | |
648 | if (target < limit->p2.dot_limit) | |
649 | clock.p2 = limit->p2.p2_slow; | |
650 | else | |
651 | clock.p2 = limit->p2.p2_fast; | |
652 | } | |
653 | ||
654 | memset(best_clock, 0, sizeof(*best_clock)); | |
655 | max_n = limit->n.max; | |
f77f13e2 | 656 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 657 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 658 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
659 | for (clock.m1 = limit->m1.max; |
660 | clock.m1 >= limit->m1.min; clock.m1--) { | |
661 | for (clock.m2 = limit->m2.max; | |
662 | clock.m2 >= limit->m2.min; clock.m2--) { | |
663 | for (clock.p1 = limit->p1.max; | |
664 | clock.p1 >= limit->p1.min; clock.p1--) { | |
665 | int this_err; | |
666 | ||
ac58c3f0 | 667 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
668 | if (!intel_PLL_is_valid(dev, limit, |
669 | &clock)) | |
d4906093 | 670 | continue; |
1b894b59 CW |
671 | |
672 | this_err = abs(clock.dot - target); | |
d4906093 ML |
673 | if (this_err < err_most) { |
674 | *best_clock = clock; | |
675 | err_most = this_err; | |
676 | max_n = clock.n; | |
677 | found = true; | |
678 | } | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
2c07245f ZW |
683 | return found; |
684 | } | |
685 | ||
a0c4da24 | 686 | static bool |
ee9300bb DV |
687 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
688 | int target, int refclk, intel_clock_t *match_clock, | |
689 | intel_clock_t *best_clock) | |
a0c4da24 JB |
690 | { |
691 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
692 | u32 m, n, fastclk; | |
f3f08572 | 693 | u32 updrate, minupdate, p; |
a0c4da24 JB |
694 | unsigned long bestppm, ppm, absppm; |
695 | int dotclk, flag; | |
696 | ||
af447bd3 | 697 | flag = 0; |
a0c4da24 JB |
698 | dotclk = target * 1000; |
699 | bestppm = 1000000; | |
700 | ppm = absppm = 0; | |
701 | fastclk = dotclk / (2*100); | |
702 | updrate = 0; | |
703 | minupdate = 19200; | |
a0c4da24 JB |
704 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
705 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
706 | ||
707 | /* based on hardware requirement, prefer smaller n to precision */ | |
708 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
709 | updrate = refclk / n; | |
710 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
711 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
712 | if (p2 > 10) | |
713 | p2 = p2 - 1; | |
714 | p = p1 * p2; | |
715 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
716 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
717 | m2 = (((2*(fastclk * p * n / m1 )) + | |
718 | refclk) / (2*refclk)); | |
719 | m = m1 * m2; | |
720 | vco = updrate * m; | |
721 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
722 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
723 | absppm = (ppm > 0) ? ppm : (-ppm); | |
724 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
725 | bestppm = 0; | |
726 | flag = 1; | |
727 | } | |
728 | if (absppm < bestppm - 10) { | |
729 | bestppm = absppm; | |
730 | flag = 1; | |
731 | } | |
732 | if (flag) { | |
733 | bestn = n; | |
734 | bestm1 = m1; | |
735 | bestm2 = m2; | |
736 | bestp1 = p1; | |
737 | bestp2 = p2; | |
738 | flag = 0; | |
739 | } | |
740 | } | |
741 | } | |
742 | } | |
743 | } | |
744 | } | |
745 | best_clock->n = bestn; | |
746 | best_clock->m1 = bestm1; | |
747 | best_clock->m2 = bestm2; | |
748 | best_clock->p1 = bestp1; | |
749 | best_clock->p2 = bestp2; | |
750 | ||
751 | return true; | |
752 | } | |
a4fc5ed6 | 753 | |
a5c961d1 PZ |
754 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
755 | enum pipe pipe) | |
756 | { | |
757 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
759 | ||
3b117c8f | 760 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
761 | } |
762 | ||
a928d536 PZ |
763 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
764 | { | |
765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
767 | ||
768 | frame = I915_READ(frame_reg); | |
769 | ||
770 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
771 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
772 | } | |
773 | ||
9d0498a2 JB |
774 | /** |
775 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
776 | * @dev: drm device | |
777 | * @pipe: pipe to wait for | |
778 | * | |
779 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
780 | * mode setting code. | |
781 | */ | |
782 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 783 | { |
9d0498a2 | 784 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 785 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 786 | |
a928d536 PZ |
787 | if (INTEL_INFO(dev)->gen >= 5) { |
788 | ironlake_wait_for_vblank(dev, pipe); | |
789 | return; | |
790 | } | |
791 | ||
300387c0 CW |
792 | /* Clear existing vblank status. Note this will clear any other |
793 | * sticky status fields as well. | |
794 | * | |
795 | * This races with i915_driver_irq_handler() with the result | |
796 | * that either function could miss a vblank event. Here it is not | |
797 | * fatal, as we will either wait upon the next vblank interrupt or | |
798 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
799 | * called during modeset at which time the GPU should be idle and | |
800 | * should *not* be performing page flips and thus not waiting on | |
801 | * vblanks... | |
802 | * Currently, the result of us stealing a vblank from the irq | |
803 | * handler is that a single frame will be skipped during swapbuffers. | |
804 | */ | |
805 | I915_WRITE(pipestat_reg, | |
806 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
807 | ||
9d0498a2 | 808 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
809 | if (wait_for(I915_READ(pipestat_reg) & |
810 | PIPE_VBLANK_INTERRUPT_STATUS, | |
811 | 50)) | |
9d0498a2 JB |
812 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
813 | } | |
814 | ||
ab7ad7f6 KP |
815 | /* |
816 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
817 | * @dev: drm device |
818 | * @pipe: pipe to wait for | |
819 | * | |
820 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
821 | * spinning on the vblank interrupt status bit, since we won't actually | |
822 | * see an interrupt when the pipe is disabled. | |
823 | * | |
ab7ad7f6 KP |
824 | * On Gen4 and above: |
825 | * wait for the pipe register state bit to turn off | |
826 | * | |
827 | * Otherwise: | |
828 | * wait for the display line value to settle (it usually | |
829 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 830 | * |
9d0498a2 | 831 | */ |
58e10eb9 | 832 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
833 | { |
834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
835 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
836 | pipe); | |
ab7ad7f6 KP |
837 | |
838 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 839 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
840 | |
841 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
842 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
843 | 100)) | |
284637d9 | 844 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 845 | } else { |
837ba00f | 846 | u32 last_line, line_mask; |
58e10eb9 | 847 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
848 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
849 | ||
837ba00f PZ |
850 | if (IS_GEN2(dev)) |
851 | line_mask = DSL_LINEMASK_GEN2; | |
852 | else | |
853 | line_mask = DSL_LINEMASK_GEN3; | |
854 | ||
ab7ad7f6 KP |
855 | /* Wait for the display line to settle */ |
856 | do { | |
837ba00f | 857 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 858 | mdelay(5); |
837ba00f | 859 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
860 | time_after(timeout, jiffies)); |
861 | if (time_after(jiffies, timeout)) | |
284637d9 | 862 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 863 | } |
79e53945 JB |
864 | } |
865 | ||
b0ea7d37 DL |
866 | /* |
867 | * ibx_digital_port_connected - is the specified port connected? | |
868 | * @dev_priv: i915 private structure | |
869 | * @port: the port to test | |
870 | * | |
871 | * Returns true if @port is connected, false otherwise. | |
872 | */ | |
873 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
874 | struct intel_digital_port *port) | |
875 | { | |
876 | u32 bit; | |
877 | ||
c36346e3 DL |
878 | if (HAS_PCH_IBX(dev_priv->dev)) { |
879 | switch(port->port) { | |
880 | case PORT_B: | |
881 | bit = SDE_PORTB_HOTPLUG; | |
882 | break; | |
883 | case PORT_C: | |
884 | bit = SDE_PORTC_HOTPLUG; | |
885 | break; | |
886 | case PORT_D: | |
887 | bit = SDE_PORTD_HOTPLUG; | |
888 | break; | |
889 | default: | |
890 | return true; | |
891 | } | |
892 | } else { | |
893 | switch(port->port) { | |
894 | case PORT_B: | |
895 | bit = SDE_PORTB_HOTPLUG_CPT; | |
896 | break; | |
897 | case PORT_C: | |
898 | bit = SDE_PORTC_HOTPLUG_CPT; | |
899 | break; | |
900 | case PORT_D: | |
901 | bit = SDE_PORTD_HOTPLUG_CPT; | |
902 | break; | |
903 | default: | |
904 | return true; | |
905 | } | |
b0ea7d37 DL |
906 | } |
907 | ||
908 | return I915_READ(SDEISR) & bit; | |
909 | } | |
910 | ||
b24e7179 JB |
911 | static const char *state_string(bool enabled) |
912 | { | |
913 | return enabled ? "on" : "off"; | |
914 | } | |
915 | ||
916 | /* Only for pre-ILK configs */ | |
55607e8a DV |
917 | void assert_pll(struct drm_i915_private *dev_priv, |
918 | enum pipe pipe, bool state) | |
b24e7179 JB |
919 | { |
920 | int reg; | |
921 | u32 val; | |
922 | bool cur_state; | |
923 | ||
924 | reg = DPLL(pipe); | |
925 | val = I915_READ(reg); | |
926 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
927 | WARN(cur_state != state, | |
928 | "PLL state assertion failure (expected %s, current %s)\n", | |
929 | state_string(state), state_string(cur_state)); | |
930 | } | |
b24e7179 | 931 | |
55607e8a | 932 | struct intel_shared_dpll * |
e2b78267 DV |
933 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
934 | { | |
935 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
936 | ||
a43f6e0f | 937 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
938 | return NULL; |
939 | ||
a43f6e0f | 940 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
941 | } |
942 | ||
040484af | 943 | /* For ILK+ */ |
55607e8a DV |
944 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
945 | struct intel_shared_dpll *pll, | |
946 | bool state) | |
040484af | 947 | { |
040484af | 948 | bool cur_state; |
5358901f | 949 | struct intel_dpll_hw_state hw_state; |
040484af | 950 | |
9d82aa17 ED |
951 | if (HAS_PCH_LPT(dev_priv->dev)) { |
952 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
953 | return; | |
954 | } | |
955 | ||
92b27b08 | 956 | if (WARN (!pll, |
46edb027 | 957 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 958 | return; |
ee7b9f93 | 959 | |
5358901f | 960 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 961 | WARN(cur_state != state, |
5358901f DV |
962 | "%s assertion failure (expected %s, current %s)\n", |
963 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 964 | } |
040484af JB |
965 | |
966 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
967 | enum pipe pipe, bool state) | |
968 | { | |
969 | int reg; | |
970 | u32 val; | |
971 | bool cur_state; | |
ad80a810 PZ |
972 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
973 | pipe); | |
040484af | 974 | |
affa9354 PZ |
975 | if (HAS_DDI(dev_priv->dev)) { |
976 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 977 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 978 | val = I915_READ(reg); |
ad80a810 | 979 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
980 | } else { |
981 | reg = FDI_TX_CTL(pipe); | |
982 | val = I915_READ(reg); | |
983 | cur_state = !!(val & FDI_TX_ENABLE); | |
984 | } | |
040484af JB |
985 | WARN(cur_state != state, |
986 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
987 | state_string(state), state_string(cur_state)); | |
988 | } | |
989 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
990 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
991 | ||
992 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
993 | enum pipe pipe, bool state) | |
994 | { | |
995 | int reg; | |
996 | u32 val; | |
997 | bool cur_state; | |
998 | ||
d63fa0dc PZ |
999 | reg = FDI_RX_CTL(pipe); |
1000 | val = I915_READ(reg); | |
1001 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1007 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | ||
1015 | /* ILK FDI PLL is always enabled */ | |
1016 | if (dev_priv->info->gen == 5) | |
1017 | return; | |
1018 | ||
bf507ef7 | 1019 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1020 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1021 | return; |
1022 | ||
040484af JB |
1023 | reg = FDI_TX_CTL(pipe); |
1024 | val = I915_READ(reg); | |
1025 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1026 | } | |
1027 | ||
55607e8a DV |
1028 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1029 | enum pipe pipe, bool state) | |
040484af JB |
1030 | { |
1031 | int reg; | |
1032 | u32 val; | |
55607e8a | 1033 | bool cur_state; |
040484af JB |
1034 | |
1035 | reg = FDI_RX_CTL(pipe); | |
1036 | val = I915_READ(reg); | |
55607e8a DV |
1037 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1038 | WARN(cur_state != state, | |
1039 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1040 | state_string(state), state_string(cur_state)); | |
040484af JB |
1041 | } |
1042 | ||
ea0760cf JB |
1043 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1044 | enum pipe pipe) | |
1045 | { | |
1046 | int pp_reg, lvds_reg; | |
1047 | u32 val; | |
1048 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1049 | bool locked = true; |
ea0760cf JB |
1050 | |
1051 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1052 | pp_reg = PCH_PP_CONTROL; | |
1053 | lvds_reg = PCH_LVDS; | |
1054 | } else { | |
1055 | pp_reg = PP_CONTROL; | |
1056 | lvds_reg = LVDS; | |
1057 | } | |
1058 | ||
1059 | val = I915_READ(pp_reg); | |
1060 | if (!(val & PANEL_POWER_ON) || | |
1061 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1062 | locked = false; | |
1063 | ||
1064 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1065 | panel_pipe = PIPE_B; | |
1066 | ||
1067 | WARN(panel_pipe == pipe && locked, | |
1068 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1069 | pipe_name(pipe)); |
ea0760cf JB |
1070 | } |
1071 | ||
b840d907 JB |
1072 | void assert_pipe(struct drm_i915_private *dev_priv, |
1073 | enum pipe pipe, bool state) | |
b24e7179 JB |
1074 | { |
1075 | int reg; | |
1076 | u32 val; | |
63d7bbe9 | 1077 | bool cur_state; |
702e7a56 PZ |
1078 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1079 | pipe); | |
b24e7179 | 1080 | |
8e636784 DV |
1081 | /* if we need the pipe A quirk it must be always on */ |
1082 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1083 | state = true; | |
1084 | ||
b97186f0 PZ |
1085 | if (!intel_display_power_enabled(dev_priv->dev, |
1086 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1087 | cur_state = false; |
1088 | } else { | |
1089 | reg = PIPECONF(cpu_transcoder); | |
1090 | val = I915_READ(reg); | |
1091 | cur_state = !!(val & PIPECONF_ENABLE); | |
1092 | } | |
1093 | ||
63d7bbe9 JB |
1094 | WARN(cur_state != state, |
1095 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1096 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1097 | } |
1098 | ||
931872fc CW |
1099 | static void assert_plane(struct drm_i915_private *dev_priv, |
1100 | enum plane plane, bool state) | |
b24e7179 JB |
1101 | { |
1102 | int reg; | |
1103 | u32 val; | |
931872fc | 1104 | bool cur_state; |
b24e7179 JB |
1105 | |
1106 | reg = DSPCNTR(plane); | |
1107 | val = I915_READ(reg); | |
931872fc CW |
1108 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1109 | WARN(cur_state != state, | |
1110 | "plane %c assertion failure (expected %s, current %s)\n", | |
1111 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1112 | } |
1113 | ||
931872fc CW |
1114 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1115 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1116 | ||
b24e7179 JB |
1117 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe) | |
1119 | { | |
653e1026 | 1120 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1121 | int reg, i; |
1122 | u32 val; | |
1123 | int cur_pipe; | |
1124 | ||
653e1026 VS |
1125 | /* Primary planes are fixed to pipes on gen4+ */ |
1126 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1127 | reg = DSPCNTR(pipe); |
1128 | val = I915_READ(reg); | |
1129 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1130 | "plane %c assertion failure, should be disabled but not\n", | |
1131 | plane_name(pipe)); | |
19ec1358 | 1132 | return; |
28c05794 | 1133 | } |
19ec1358 | 1134 | |
b24e7179 | 1135 | /* Need to check both planes against the pipe */ |
08e2a7de | 1136 | for_each_pipe(i) { |
b24e7179 JB |
1137 | reg = DSPCNTR(i); |
1138 | val = I915_READ(reg); | |
1139 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1140 | DISPPLANE_SEL_PIPE_SHIFT; | |
1141 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1142 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1143 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1144 | } |
1145 | } | |
1146 | ||
19332d7a JB |
1147 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1148 | enum pipe pipe) | |
1149 | { | |
20674eef | 1150 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1151 | int reg, i; |
1152 | u32 val; | |
1153 | ||
20674eef VS |
1154 | if (IS_VALLEYVIEW(dev)) { |
1155 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1156 | reg = SPCNTR(pipe, i); | |
1157 | val = I915_READ(reg); | |
1158 | WARN((val & SP_ENABLE), | |
1159 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1160 | sprite_name(pipe, i), pipe_name(pipe)); | |
1161 | } | |
1162 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1163 | reg = SPRCTL(pipe); | |
19332d7a | 1164 | val = I915_READ(reg); |
20674eef | 1165 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1166 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1167 | plane_name(pipe), pipe_name(pipe)); |
1168 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1169 | reg = DVSCNTR(pipe); | |
19332d7a | 1170 | val = I915_READ(reg); |
20674eef | 1171 | WARN((val & DVS_ENABLE), |
06da8da2 | 1172 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1173 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1174 | } |
1175 | } | |
1176 | ||
92f2584a JB |
1177 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1178 | { | |
1179 | u32 val; | |
1180 | bool enabled; | |
1181 | ||
9d82aa17 ED |
1182 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1183 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1184 | return; | |
1185 | } | |
1186 | ||
92f2584a JB |
1187 | val = I915_READ(PCH_DREF_CONTROL); |
1188 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1189 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1190 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1191 | } | |
1192 | ||
ab9412ba DV |
1193 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1194 | enum pipe pipe) | |
92f2584a JB |
1195 | { |
1196 | int reg; | |
1197 | u32 val; | |
1198 | bool enabled; | |
1199 | ||
ab9412ba | 1200 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1201 | val = I915_READ(reg); |
1202 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1203 | WARN(enabled, |
1204 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1205 | pipe_name(pipe)); | |
92f2584a JB |
1206 | } |
1207 | ||
4e634389 KP |
1208 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1209 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1210 | { |
1211 | if ((val & DP_PORT_EN) == 0) | |
1212 | return false; | |
1213 | ||
1214 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1215 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1216 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1217 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1218 | return false; | |
1219 | } else { | |
1220 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1221 | return false; | |
1222 | } | |
1223 | return true; | |
1224 | } | |
1225 | ||
1519b995 KP |
1226 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1227 | enum pipe pipe, u32 val) | |
1228 | { | |
dc0fa718 | 1229 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1230 | return false; |
1231 | ||
1232 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1233 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1234 | return false; |
1235 | } else { | |
dc0fa718 | 1236 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1237 | return false; |
1238 | } | |
1239 | return true; | |
1240 | } | |
1241 | ||
1242 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1243 | enum pipe pipe, u32 val) | |
1244 | { | |
1245 | if ((val & LVDS_PORT_EN) == 0) | |
1246 | return false; | |
1247 | ||
1248 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1249 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1250 | return false; | |
1251 | } else { | |
1252 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1253 | return false; | |
1254 | } | |
1255 | return true; | |
1256 | } | |
1257 | ||
1258 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1259 | enum pipe pipe, u32 val) | |
1260 | { | |
1261 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1262 | return false; | |
1263 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1264 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1265 | return false; | |
1266 | } else { | |
1267 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1268 | return false; | |
1269 | } | |
1270 | return true; | |
1271 | } | |
1272 | ||
291906f1 | 1273 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1274 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1275 | { |
47a05eca | 1276 | u32 val = I915_READ(reg); |
4e634389 | 1277 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1278 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1279 | reg, pipe_name(pipe)); |
de9a35ab | 1280 | |
75c5da27 DV |
1281 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1282 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1283 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1284 | } |
1285 | ||
1286 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1287 | enum pipe pipe, int reg) | |
1288 | { | |
47a05eca | 1289 | u32 val = I915_READ(reg); |
b70ad586 | 1290 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1291 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1292 | reg, pipe_name(pipe)); |
de9a35ab | 1293 | |
dc0fa718 | 1294 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1295 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1296 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1297 | } |
1298 | ||
1299 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1300 | enum pipe pipe) | |
1301 | { | |
1302 | int reg; | |
1303 | u32 val; | |
291906f1 | 1304 | |
f0575e92 KP |
1305 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1306 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1307 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1308 | |
1309 | reg = PCH_ADPA; | |
1310 | val = I915_READ(reg); | |
b70ad586 | 1311 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1312 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1313 | pipe_name(pipe)); |
291906f1 JB |
1314 | |
1315 | reg = PCH_LVDS; | |
1316 | val = I915_READ(reg); | |
b70ad586 | 1317 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1318 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
291906f1 | 1320 | |
e2debe91 PZ |
1321 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1322 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1323 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1324 | } |
1325 | ||
426115cf | 1326 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1327 | { |
426115cf DV |
1328 | struct drm_device *dev = crtc->base.dev; |
1329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1330 | int reg = DPLL(crtc->pipe); | |
1331 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1332 | |
426115cf | 1333 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1334 | |
1335 | /* No really, not for ILK+ */ | |
1336 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1337 | ||
1338 | /* PLL is protected by panel, make sure we can write it */ | |
1339 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1340 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1341 | |
426115cf DV |
1342 | I915_WRITE(reg, dpll); |
1343 | POSTING_READ(reg); | |
1344 | udelay(150); | |
1345 | ||
1346 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1347 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1348 | ||
1349 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1350 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1351 | |
1352 | /* We do this three times for luck */ | |
426115cf | 1353 | I915_WRITE(reg, dpll); |
87442f73 DV |
1354 | POSTING_READ(reg); |
1355 | udelay(150); /* wait for warmup */ | |
426115cf | 1356 | I915_WRITE(reg, dpll); |
87442f73 DV |
1357 | POSTING_READ(reg); |
1358 | udelay(150); /* wait for warmup */ | |
426115cf | 1359 | I915_WRITE(reg, dpll); |
87442f73 DV |
1360 | POSTING_READ(reg); |
1361 | udelay(150); /* wait for warmup */ | |
1362 | } | |
1363 | ||
66e3d5c0 | 1364 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1365 | { |
66e3d5c0 DV |
1366 | struct drm_device *dev = crtc->base.dev; |
1367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1368 | int reg = DPLL(crtc->pipe); | |
1369 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1370 | |
66e3d5c0 | 1371 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1372 | |
63d7bbe9 | 1373 | /* No really, not for ILK+ */ |
87442f73 | 1374 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1375 | |
1376 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1377 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1378 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1379 | |
66e3d5c0 DV |
1380 | I915_WRITE(reg, dpll); |
1381 | ||
1382 | /* Wait for the clocks to stabilize. */ | |
1383 | POSTING_READ(reg); | |
1384 | udelay(150); | |
1385 | ||
1386 | if (INTEL_INFO(dev)->gen >= 4) { | |
1387 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1388 | crtc->config.dpll_hw_state.dpll_md); | |
1389 | } else { | |
1390 | /* The pixel multiplier can only be updated once the | |
1391 | * DPLL is enabled and the clocks are stable. | |
1392 | * | |
1393 | * So write it again. | |
1394 | */ | |
1395 | I915_WRITE(reg, dpll); | |
1396 | } | |
63d7bbe9 JB |
1397 | |
1398 | /* We do this three times for luck */ | |
66e3d5c0 | 1399 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1400 | POSTING_READ(reg); |
1401 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1402 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1403 | POSTING_READ(reg); |
1404 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1405 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ | |
1408 | } | |
1409 | ||
1410 | /** | |
50b44a44 | 1411 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1412 | * @dev_priv: i915 private structure |
1413 | * @pipe: pipe PLL to disable | |
1414 | * | |
1415 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1416 | * | |
1417 | * Note! This is for pre-ILK only. | |
1418 | */ | |
50b44a44 | 1419 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1420 | { |
63d7bbe9 JB |
1421 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1422 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1423 | return; | |
1424 | ||
1425 | /* Make sure the pipe isn't still relying on us */ | |
1426 | assert_pipe_disabled(dev_priv, pipe); | |
1427 | ||
50b44a44 DV |
1428 | I915_WRITE(DPLL(pipe), 0); |
1429 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1430 | } |
1431 | ||
89b667f8 JB |
1432 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1433 | { | |
1434 | u32 port_mask; | |
1435 | ||
1436 | if (!port) | |
1437 | port_mask = DPLL_PORTB_READY_MASK; | |
1438 | else | |
1439 | port_mask = DPLL_PORTC_READY_MASK; | |
1440 | ||
1441 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1442 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
1443 | 'B' + port, I915_READ(DPLL(0))); | |
1444 | } | |
1445 | ||
92f2584a | 1446 | /** |
e72f9fbf | 1447 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1448 | * @dev_priv: i915 private structure |
1449 | * @pipe: pipe PLL to enable | |
1450 | * | |
1451 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1452 | * drives the transcoder clock. | |
1453 | */ | |
e2b78267 | 1454 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1455 | { |
e2b78267 DV |
1456 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1457 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1458 | |
48da64a8 | 1459 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1460 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1461 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1462 | return; |
1463 | ||
1464 | if (WARN_ON(pll->refcount == 0)) | |
1465 | return; | |
ee7b9f93 | 1466 | |
46edb027 DV |
1467 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1468 | pll->name, pll->active, pll->on, | |
e2b78267 | 1469 | crtc->base.base.id); |
92f2584a | 1470 | |
cdbd2316 DV |
1471 | if (pll->active++) { |
1472 | WARN_ON(!pll->on); | |
e9d6944e | 1473 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1474 | return; |
1475 | } | |
f4a091c7 | 1476 | WARN_ON(pll->on); |
ee7b9f93 | 1477 | |
46edb027 | 1478 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1479 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1480 | pll->on = true; |
92f2584a JB |
1481 | } |
1482 | ||
e2b78267 | 1483 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1484 | { |
e2b78267 DV |
1485 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1486 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1487 | |
92f2584a JB |
1488 | /* PCH only available on ILK+ */ |
1489 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1490 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1491 | return; |
92f2584a | 1492 | |
48da64a8 CW |
1493 | if (WARN_ON(pll->refcount == 0)) |
1494 | return; | |
7a419866 | 1495 | |
46edb027 DV |
1496 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1497 | pll->name, pll->active, pll->on, | |
e2b78267 | 1498 | crtc->base.base.id); |
7a419866 | 1499 | |
48da64a8 | 1500 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1501 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1502 | return; |
1503 | } | |
1504 | ||
e9d6944e | 1505 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1506 | WARN_ON(!pll->on); |
cdbd2316 | 1507 | if (--pll->active) |
7a419866 | 1508 | return; |
ee7b9f93 | 1509 | |
46edb027 | 1510 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1511 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1512 | pll->on = false; |
92f2584a JB |
1513 | } |
1514 | ||
b8a4f404 PZ |
1515 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1516 | enum pipe pipe) | |
040484af | 1517 | { |
23670b32 | 1518 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1519 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1521 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1522 | |
1523 | /* PCH only available on ILK+ */ | |
1524 | BUG_ON(dev_priv->info->gen < 5); | |
1525 | ||
1526 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1527 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1528 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1529 | |
1530 | /* FDI must be feeding us bits for PCH ports */ | |
1531 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1532 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1533 | ||
23670b32 DV |
1534 | if (HAS_PCH_CPT(dev)) { |
1535 | /* Workaround: Set the timing override bit before enabling the | |
1536 | * pch transcoder. */ | |
1537 | reg = TRANS_CHICKEN2(pipe); | |
1538 | val = I915_READ(reg); | |
1539 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1540 | I915_WRITE(reg, val); | |
59c859d6 | 1541 | } |
23670b32 | 1542 | |
ab9412ba | 1543 | reg = PCH_TRANSCONF(pipe); |
040484af | 1544 | val = I915_READ(reg); |
5f7f726d | 1545 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1546 | |
1547 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1548 | /* | |
1549 | * make the BPC in transcoder be consistent with | |
1550 | * that in pipeconf reg. | |
1551 | */ | |
dfd07d72 DV |
1552 | val &= ~PIPECONF_BPC_MASK; |
1553 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1554 | } |
5f7f726d PZ |
1555 | |
1556 | val &= ~TRANS_INTERLACE_MASK; | |
1557 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1558 | if (HAS_PCH_IBX(dev_priv->dev) && |
1559 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1560 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1561 | else | |
1562 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1563 | else |
1564 | val |= TRANS_PROGRESSIVE; | |
1565 | ||
040484af JB |
1566 | I915_WRITE(reg, val | TRANS_ENABLE); |
1567 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1568 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1569 | } |
1570 | ||
8fb033d7 | 1571 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1572 | enum transcoder cpu_transcoder) |
040484af | 1573 | { |
8fb033d7 | 1574 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1575 | |
1576 | /* PCH only available on ILK+ */ | |
1577 | BUG_ON(dev_priv->info->gen < 5); | |
1578 | ||
8fb033d7 | 1579 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1580 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1581 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1582 | |
223a6fdf PZ |
1583 | /* Workaround: set timing override bit. */ |
1584 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1585 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1586 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1587 | ||
25f3ef11 | 1588 | val = TRANS_ENABLE; |
937bb610 | 1589 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1590 | |
9a76b1c6 PZ |
1591 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1592 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1593 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1594 | else |
1595 | val |= TRANS_PROGRESSIVE; | |
1596 | ||
ab9412ba DV |
1597 | I915_WRITE(LPT_TRANSCONF, val); |
1598 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1599 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1600 | } |
1601 | ||
b8a4f404 PZ |
1602 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1603 | enum pipe pipe) | |
040484af | 1604 | { |
23670b32 DV |
1605 | struct drm_device *dev = dev_priv->dev; |
1606 | uint32_t reg, val; | |
040484af JB |
1607 | |
1608 | /* FDI relies on the transcoder */ | |
1609 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1610 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1611 | ||
291906f1 JB |
1612 | /* Ports must be off as well */ |
1613 | assert_pch_ports_disabled(dev_priv, pipe); | |
1614 | ||
ab9412ba | 1615 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1616 | val = I915_READ(reg); |
1617 | val &= ~TRANS_ENABLE; | |
1618 | I915_WRITE(reg, val); | |
1619 | /* wait for PCH transcoder off, transcoder state */ | |
1620 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1621 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1622 | |
1623 | if (!HAS_PCH_IBX(dev)) { | |
1624 | /* Workaround: Clear the timing override chicken bit again. */ | |
1625 | reg = TRANS_CHICKEN2(pipe); | |
1626 | val = I915_READ(reg); | |
1627 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1628 | I915_WRITE(reg, val); | |
1629 | } | |
040484af JB |
1630 | } |
1631 | ||
ab4d966c | 1632 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1633 | { |
8fb033d7 PZ |
1634 | u32 val; |
1635 | ||
ab9412ba | 1636 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1637 | val &= ~TRANS_ENABLE; |
ab9412ba | 1638 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1639 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1640 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1641 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1642 | |
1643 | /* Workaround: clear timing override bit. */ | |
1644 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1645 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1646 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1647 | } |
1648 | ||
b24e7179 | 1649 | /** |
309cfea8 | 1650 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1651 | * @dev_priv: i915 private structure |
1652 | * @pipe: pipe to enable | |
040484af | 1653 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1654 | * |
1655 | * Enable @pipe, making sure that various hardware specific requirements | |
1656 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1657 | * | |
1658 | * @pipe should be %PIPE_A or %PIPE_B. | |
1659 | * | |
1660 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1661 | * returning. | |
1662 | */ | |
040484af JB |
1663 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1664 | bool pch_port) | |
b24e7179 | 1665 | { |
702e7a56 PZ |
1666 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1667 | pipe); | |
1a240d4d | 1668 | enum pipe pch_transcoder; |
b24e7179 JB |
1669 | int reg; |
1670 | u32 val; | |
1671 | ||
58c6eaa2 DV |
1672 | assert_planes_disabled(dev_priv, pipe); |
1673 | assert_sprites_disabled(dev_priv, pipe); | |
1674 | ||
681e5811 | 1675 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1676 | pch_transcoder = TRANSCODER_A; |
1677 | else | |
1678 | pch_transcoder = pipe; | |
1679 | ||
b24e7179 JB |
1680 | /* |
1681 | * A pipe without a PLL won't actually be able to drive bits from | |
1682 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1683 | * need the check. | |
1684 | */ | |
1685 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1686 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1687 | else { |
1688 | if (pch_port) { | |
1689 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1690 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1691 | assert_fdi_tx_pll_enabled(dev_priv, |
1692 | (enum pipe) cpu_transcoder); | |
040484af JB |
1693 | } |
1694 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1695 | } | |
b24e7179 | 1696 | |
702e7a56 | 1697 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1698 | val = I915_READ(reg); |
00d70b15 CW |
1699 | if (val & PIPECONF_ENABLE) |
1700 | return; | |
1701 | ||
1702 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1703 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1704 | } | |
1705 | ||
1706 | /** | |
309cfea8 | 1707 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1708 | * @dev_priv: i915 private structure |
1709 | * @pipe: pipe to disable | |
1710 | * | |
1711 | * Disable @pipe, making sure that various hardware specific requirements | |
1712 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1713 | * | |
1714 | * @pipe should be %PIPE_A or %PIPE_B. | |
1715 | * | |
1716 | * Will wait until the pipe has shut down before returning. | |
1717 | */ | |
1718 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1719 | enum pipe pipe) | |
1720 | { | |
702e7a56 PZ |
1721 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1722 | pipe); | |
b24e7179 JB |
1723 | int reg; |
1724 | u32 val; | |
1725 | ||
1726 | /* | |
1727 | * Make sure planes won't keep trying to pump pixels to us, | |
1728 | * or we might hang the display. | |
1729 | */ | |
1730 | assert_planes_disabled(dev_priv, pipe); | |
19332d7a | 1731 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1732 | |
1733 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1734 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1735 | return; | |
1736 | ||
702e7a56 | 1737 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1738 | val = I915_READ(reg); |
00d70b15 CW |
1739 | if ((val & PIPECONF_ENABLE) == 0) |
1740 | return; | |
1741 | ||
1742 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1743 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1744 | } | |
1745 | ||
d74362c9 KP |
1746 | /* |
1747 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1748 | * trigger in order to latch. The display address reg provides this. | |
1749 | */ | |
6f1d69b0 | 1750 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1751 | enum plane plane) |
1752 | { | |
14f86147 DL |
1753 | if (dev_priv->info->gen >= 4) |
1754 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1755 | else | |
1756 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1757 | } |
1758 | ||
b24e7179 JB |
1759 | /** |
1760 | * intel_enable_plane - enable a display plane on a given pipe | |
1761 | * @dev_priv: i915 private structure | |
1762 | * @plane: plane to enable | |
1763 | * @pipe: pipe being fed | |
1764 | * | |
1765 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1766 | */ | |
1767 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1768 | enum plane plane, enum pipe pipe) | |
1769 | { | |
1770 | int reg; | |
1771 | u32 val; | |
1772 | ||
1773 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1774 | assert_pipe_enabled(dev_priv, pipe); | |
1775 | ||
1776 | reg = DSPCNTR(plane); | |
1777 | val = I915_READ(reg); | |
00d70b15 CW |
1778 | if (val & DISPLAY_PLANE_ENABLE) |
1779 | return; | |
1780 | ||
1781 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1782 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1783 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1784 | } | |
1785 | ||
b24e7179 JB |
1786 | /** |
1787 | * intel_disable_plane - disable a display plane | |
1788 | * @dev_priv: i915 private structure | |
1789 | * @plane: plane to disable | |
1790 | * @pipe: pipe consuming the data | |
1791 | * | |
1792 | * Disable @plane; should be an independent operation. | |
1793 | */ | |
1794 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1795 | enum plane plane, enum pipe pipe) | |
1796 | { | |
1797 | int reg; | |
1798 | u32 val; | |
1799 | ||
1800 | reg = DSPCNTR(plane); | |
1801 | val = I915_READ(reg); | |
00d70b15 CW |
1802 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1803 | return; | |
1804 | ||
1805 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1806 | intel_flush_display_plane(dev_priv, plane); |
1807 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1808 | } | |
1809 | ||
693db184 CW |
1810 | static bool need_vtd_wa(struct drm_device *dev) |
1811 | { | |
1812 | #ifdef CONFIG_INTEL_IOMMU | |
1813 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1814 | return true; | |
1815 | #endif | |
1816 | return false; | |
1817 | } | |
1818 | ||
127bd2ac | 1819 | int |
48b956c5 | 1820 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1821 | struct drm_i915_gem_object *obj, |
919926ae | 1822 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1823 | { |
ce453d81 | 1824 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1825 | u32 alignment; |
1826 | int ret; | |
1827 | ||
05394f39 | 1828 | switch (obj->tiling_mode) { |
6b95a207 | 1829 | case I915_TILING_NONE: |
534843da CW |
1830 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1831 | alignment = 128 * 1024; | |
a6c45cf0 | 1832 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1833 | alignment = 4 * 1024; |
1834 | else | |
1835 | alignment = 64 * 1024; | |
6b95a207 KH |
1836 | break; |
1837 | case I915_TILING_X: | |
1838 | /* pin() will align the object as required by fence */ | |
1839 | alignment = 0; | |
1840 | break; | |
1841 | case I915_TILING_Y: | |
8bb6e959 DV |
1842 | /* Despite that we check this in framebuffer_init userspace can |
1843 | * screw us over and change the tiling after the fact. Only | |
1844 | * pinned buffers can't change their tiling. */ | |
1845 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); | |
6b95a207 KH |
1846 | return -EINVAL; |
1847 | default: | |
1848 | BUG(); | |
1849 | } | |
1850 | ||
693db184 CW |
1851 | /* Note that the w/a also requires 64 PTE of padding following the |
1852 | * bo. We currently fill all unused PTE with the shadow page and so | |
1853 | * we should always have valid PTE following the scanout preventing | |
1854 | * the VT-d warning. | |
1855 | */ | |
1856 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1857 | alignment = 256 * 1024; | |
1858 | ||
ce453d81 | 1859 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1860 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1861 | if (ret) |
ce453d81 | 1862 | goto err_interruptible; |
6b95a207 KH |
1863 | |
1864 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1865 | * fence, whereas 965+ only requires a fence if using | |
1866 | * framebuffer compression. For simplicity, we always install | |
1867 | * a fence as the cost is not that onerous. | |
1868 | */ | |
06d98131 | 1869 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1870 | if (ret) |
1871 | goto err_unpin; | |
1690e1eb | 1872 | |
9a5a53b3 | 1873 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1874 | |
ce453d81 | 1875 | dev_priv->mm.interruptible = true; |
6b95a207 | 1876 | return 0; |
48b956c5 CW |
1877 | |
1878 | err_unpin: | |
cc98b413 | 1879 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1880 | err_interruptible: |
1881 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1882 | return ret; |
6b95a207 KH |
1883 | } |
1884 | ||
1690e1eb CW |
1885 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1886 | { | |
1887 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1888 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1889 | } |
1890 | ||
c2c75131 DV |
1891 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1892 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1893 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1894 | unsigned int tiling_mode, | |
1895 | unsigned int cpp, | |
1896 | unsigned int pitch) | |
c2c75131 | 1897 | { |
bc752862 CW |
1898 | if (tiling_mode != I915_TILING_NONE) { |
1899 | unsigned int tile_rows, tiles; | |
c2c75131 | 1900 | |
bc752862 CW |
1901 | tile_rows = *y / 8; |
1902 | *y %= 8; | |
c2c75131 | 1903 | |
bc752862 CW |
1904 | tiles = *x / (512/cpp); |
1905 | *x %= 512/cpp; | |
1906 | ||
1907 | return tile_rows * pitch * 8 + tiles * 4096; | |
1908 | } else { | |
1909 | unsigned int offset; | |
1910 | ||
1911 | offset = *y * pitch + *x * cpp; | |
1912 | *y = 0; | |
1913 | *x = (offset & 4095) / cpp; | |
1914 | return offset & -4096; | |
1915 | } | |
c2c75131 DV |
1916 | } |
1917 | ||
17638cd6 JB |
1918 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1919 | int x, int y) | |
81255565 JB |
1920 | { |
1921 | struct drm_device *dev = crtc->dev; | |
1922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1924 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1925 | struct drm_i915_gem_object *obj; |
81255565 | 1926 | int plane = intel_crtc->plane; |
e506a0c6 | 1927 | unsigned long linear_offset; |
81255565 | 1928 | u32 dspcntr; |
5eddb70b | 1929 | u32 reg; |
81255565 JB |
1930 | |
1931 | switch (plane) { | |
1932 | case 0: | |
1933 | case 1: | |
1934 | break; | |
1935 | default: | |
84f44ce7 | 1936 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
1937 | return -EINVAL; |
1938 | } | |
1939 | ||
1940 | intel_fb = to_intel_framebuffer(fb); | |
1941 | obj = intel_fb->obj; | |
81255565 | 1942 | |
5eddb70b CW |
1943 | reg = DSPCNTR(plane); |
1944 | dspcntr = I915_READ(reg); | |
81255565 JB |
1945 | /* Mask out pixel format bits in case we change it */ |
1946 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
1947 | switch (fb->pixel_format) { |
1948 | case DRM_FORMAT_C8: | |
81255565 JB |
1949 | dspcntr |= DISPPLANE_8BPP; |
1950 | break; | |
57779d06 VS |
1951 | case DRM_FORMAT_XRGB1555: |
1952 | case DRM_FORMAT_ARGB1555: | |
1953 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 1954 | break; |
57779d06 VS |
1955 | case DRM_FORMAT_RGB565: |
1956 | dspcntr |= DISPPLANE_BGRX565; | |
1957 | break; | |
1958 | case DRM_FORMAT_XRGB8888: | |
1959 | case DRM_FORMAT_ARGB8888: | |
1960 | dspcntr |= DISPPLANE_BGRX888; | |
1961 | break; | |
1962 | case DRM_FORMAT_XBGR8888: | |
1963 | case DRM_FORMAT_ABGR8888: | |
1964 | dspcntr |= DISPPLANE_RGBX888; | |
1965 | break; | |
1966 | case DRM_FORMAT_XRGB2101010: | |
1967 | case DRM_FORMAT_ARGB2101010: | |
1968 | dspcntr |= DISPPLANE_BGRX101010; | |
1969 | break; | |
1970 | case DRM_FORMAT_XBGR2101010: | |
1971 | case DRM_FORMAT_ABGR2101010: | |
1972 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
1973 | break; |
1974 | default: | |
baba133a | 1975 | BUG(); |
81255565 | 1976 | } |
57779d06 | 1977 | |
a6c45cf0 | 1978 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 1979 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
1980 | dspcntr |= DISPPLANE_TILED; |
1981 | else | |
1982 | dspcntr &= ~DISPPLANE_TILED; | |
1983 | } | |
1984 | ||
de1aa629 VS |
1985 | if (IS_G4X(dev)) |
1986 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1987 | ||
5eddb70b | 1988 | I915_WRITE(reg, dspcntr); |
81255565 | 1989 | |
e506a0c6 | 1990 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 1991 | |
c2c75131 DV |
1992 | if (INTEL_INFO(dev)->gen >= 4) { |
1993 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
1994 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
1995 | fb->bits_per_pixel / 8, | |
1996 | fb->pitches[0]); | |
c2c75131 DV |
1997 | linear_offset -= intel_crtc->dspaddr_offset; |
1998 | } else { | |
e506a0c6 | 1999 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2000 | } |
e506a0c6 | 2001 | |
f343c5f6 BW |
2002 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2003 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2004 | fb->pitches[0]); | |
01f2c773 | 2005 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2006 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2007 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2008 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2009 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2010 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2011 | } else |
f343c5f6 | 2012 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2013 | POSTING_READ(reg); |
81255565 | 2014 | |
17638cd6 JB |
2015 | return 0; |
2016 | } | |
2017 | ||
2018 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2019 | struct drm_framebuffer *fb, int x, int y) | |
2020 | { | |
2021 | struct drm_device *dev = crtc->dev; | |
2022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2024 | struct intel_framebuffer *intel_fb; | |
2025 | struct drm_i915_gem_object *obj; | |
2026 | int plane = intel_crtc->plane; | |
e506a0c6 | 2027 | unsigned long linear_offset; |
17638cd6 JB |
2028 | u32 dspcntr; |
2029 | u32 reg; | |
2030 | ||
2031 | switch (plane) { | |
2032 | case 0: | |
2033 | case 1: | |
27f8227b | 2034 | case 2: |
17638cd6 JB |
2035 | break; |
2036 | default: | |
84f44ce7 | 2037 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2038 | return -EINVAL; |
2039 | } | |
2040 | ||
2041 | intel_fb = to_intel_framebuffer(fb); | |
2042 | obj = intel_fb->obj; | |
2043 | ||
2044 | reg = DSPCNTR(plane); | |
2045 | dspcntr = I915_READ(reg); | |
2046 | /* Mask out pixel format bits in case we change it */ | |
2047 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2048 | switch (fb->pixel_format) { |
2049 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2050 | dspcntr |= DISPPLANE_8BPP; |
2051 | break; | |
57779d06 VS |
2052 | case DRM_FORMAT_RGB565: |
2053 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2054 | break; |
57779d06 VS |
2055 | case DRM_FORMAT_XRGB8888: |
2056 | case DRM_FORMAT_ARGB8888: | |
2057 | dspcntr |= DISPPLANE_BGRX888; | |
2058 | break; | |
2059 | case DRM_FORMAT_XBGR8888: | |
2060 | case DRM_FORMAT_ABGR8888: | |
2061 | dspcntr |= DISPPLANE_RGBX888; | |
2062 | break; | |
2063 | case DRM_FORMAT_XRGB2101010: | |
2064 | case DRM_FORMAT_ARGB2101010: | |
2065 | dspcntr |= DISPPLANE_BGRX101010; | |
2066 | break; | |
2067 | case DRM_FORMAT_XBGR2101010: | |
2068 | case DRM_FORMAT_ABGR2101010: | |
2069 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2070 | break; |
2071 | default: | |
baba133a | 2072 | BUG(); |
17638cd6 JB |
2073 | } |
2074 | ||
2075 | if (obj->tiling_mode != I915_TILING_NONE) | |
2076 | dspcntr |= DISPPLANE_TILED; | |
2077 | else | |
2078 | dspcntr &= ~DISPPLANE_TILED; | |
2079 | ||
1f5d76db PZ |
2080 | if (IS_HASWELL(dev)) |
2081 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; | |
2082 | else | |
2083 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2084 | |
2085 | I915_WRITE(reg, dspcntr); | |
2086 | ||
e506a0c6 | 2087 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2088 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2089 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2090 | fb->bits_per_pixel / 8, | |
2091 | fb->pitches[0]); | |
c2c75131 | 2092 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2093 | |
f343c5f6 BW |
2094 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2095 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2096 | fb->pitches[0]); | |
01f2c773 | 2097 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2098 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2099 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
bc1c91eb DL |
2100 | if (IS_HASWELL(dev)) { |
2101 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2102 | } else { | |
2103 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2104 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2105 | } | |
17638cd6 JB |
2106 | POSTING_READ(reg); |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2112 | static int | |
2113 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2114 | int x, int y, enum mode_set_atomic state) | |
2115 | { | |
2116 | struct drm_device *dev = crtc->dev; | |
2117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2118 | |
6b8e6ed0 CW |
2119 | if (dev_priv->display.disable_fbc) |
2120 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2121 | intel_increase_pllclock(crtc); |
81255565 | 2122 | |
6b8e6ed0 | 2123 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2124 | } |
2125 | ||
96a02917 VS |
2126 | void intel_display_handle_reset(struct drm_device *dev) |
2127 | { | |
2128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2129 | struct drm_crtc *crtc; | |
2130 | ||
2131 | /* | |
2132 | * Flips in the rings have been nuked by the reset, | |
2133 | * so complete all pending flips so that user space | |
2134 | * will get its events and not get stuck. | |
2135 | * | |
2136 | * Also update the base address of all primary | |
2137 | * planes to the the last fb to make sure we're | |
2138 | * showing the correct fb after a reset. | |
2139 | * | |
2140 | * Need to make two loops over the crtcs so that we | |
2141 | * don't try to grab a crtc mutex before the | |
2142 | * pending_flip_queue really got woken up. | |
2143 | */ | |
2144 | ||
2145 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2147 | enum plane plane = intel_crtc->plane; | |
2148 | ||
2149 | intel_prepare_page_flip(dev, plane); | |
2150 | intel_finish_page_flip_plane(dev, plane); | |
2151 | } | |
2152 | ||
2153 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2155 | ||
2156 | mutex_lock(&crtc->mutex); | |
2157 | if (intel_crtc->active) | |
2158 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2159 | crtc->x, crtc->y); | |
2160 | mutex_unlock(&crtc->mutex); | |
2161 | } | |
2162 | } | |
2163 | ||
14667a4b CW |
2164 | static int |
2165 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2166 | { | |
2167 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2168 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2169 | bool was_interruptible = dev_priv->mm.interruptible; | |
2170 | int ret; | |
2171 | ||
14667a4b CW |
2172 | /* Big Hammer, we also need to ensure that any pending |
2173 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2174 | * current scanout is retired before unpinning the old | |
2175 | * framebuffer. | |
2176 | * | |
2177 | * This should only fail upon a hung GPU, in which case we | |
2178 | * can safely continue. | |
2179 | */ | |
2180 | dev_priv->mm.interruptible = false; | |
2181 | ret = i915_gem_object_finish_gpu(obj); | |
2182 | dev_priv->mm.interruptible = was_interruptible; | |
2183 | ||
2184 | return ret; | |
2185 | } | |
2186 | ||
198598d0 VS |
2187 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2188 | { | |
2189 | struct drm_device *dev = crtc->dev; | |
2190 | struct drm_i915_master_private *master_priv; | |
2191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2192 | ||
2193 | if (!dev->primary->master) | |
2194 | return; | |
2195 | ||
2196 | master_priv = dev->primary->master->driver_priv; | |
2197 | if (!master_priv->sarea_priv) | |
2198 | return; | |
2199 | ||
2200 | switch (intel_crtc->pipe) { | |
2201 | case 0: | |
2202 | master_priv->sarea_priv->pipeA_x = x; | |
2203 | master_priv->sarea_priv->pipeA_y = y; | |
2204 | break; | |
2205 | case 1: | |
2206 | master_priv->sarea_priv->pipeB_x = x; | |
2207 | master_priv->sarea_priv->pipeB_y = y; | |
2208 | break; | |
2209 | default: | |
2210 | break; | |
2211 | } | |
2212 | } | |
2213 | ||
5c3b82e2 | 2214 | static int |
3c4fdcfb | 2215 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2216 | struct drm_framebuffer *fb) |
79e53945 JB |
2217 | { |
2218 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2219 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2221 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2222 | int ret; |
79e53945 JB |
2223 | |
2224 | /* no fb bound */ | |
94352cf9 | 2225 | if (!fb) { |
a5071c2f | 2226 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2227 | return 0; |
2228 | } | |
2229 | ||
7eb552ae | 2230 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2231 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2232 | plane_name(intel_crtc->plane), | |
2233 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2234 | return -EINVAL; |
79e53945 JB |
2235 | } |
2236 | ||
5c3b82e2 | 2237 | mutex_lock(&dev->struct_mutex); |
265db958 | 2238 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2239 | to_intel_framebuffer(fb)->obj, |
919926ae | 2240 | NULL); |
5c3b82e2 CW |
2241 | if (ret != 0) { |
2242 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2243 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2244 | return ret; |
2245 | } | |
79e53945 | 2246 | |
4d6a3e63 JB |
2247 | /* Update pipe size and adjust fitter if needed */ |
2248 | if (i915_fastboot) { | |
2249 | I915_WRITE(PIPESRC(intel_crtc->pipe), | |
2250 | ((crtc->mode.hdisplay - 1) << 16) | | |
2251 | (crtc->mode.vdisplay - 1)); | |
fd4daa9c | 2252 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2253 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2254 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2255 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2256 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2257 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2258 | } | |
2259 | } | |
2260 | ||
94352cf9 | 2261 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2262 | if (ret) { |
94352cf9 | 2263 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2264 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2265 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2266 | return ret; |
79e53945 | 2267 | } |
3c4fdcfb | 2268 | |
94352cf9 DV |
2269 | old_fb = crtc->fb; |
2270 | crtc->fb = fb; | |
6c4c86f5 DV |
2271 | crtc->x = x; |
2272 | crtc->y = y; | |
94352cf9 | 2273 | |
b7f1de28 | 2274 | if (old_fb) { |
d7697eea DV |
2275 | if (intel_crtc->active && old_fb != fb) |
2276 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2277 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2278 | } |
652c393a | 2279 | |
6b8e6ed0 | 2280 | intel_update_fbc(dev); |
4906557e | 2281 | intel_edp_psr_update(dev); |
5c3b82e2 | 2282 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2283 | |
198598d0 | 2284 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2285 | |
2286 | return 0; | |
79e53945 JB |
2287 | } |
2288 | ||
5e84e1a4 ZW |
2289 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2290 | { | |
2291 | struct drm_device *dev = crtc->dev; | |
2292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2294 | int pipe = intel_crtc->pipe; | |
2295 | u32 reg, temp; | |
2296 | ||
2297 | /* enable normal train */ | |
2298 | reg = FDI_TX_CTL(pipe); | |
2299 | temp = I915_READ(reg); | |
61e499bf | 2300 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2301 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2302 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2303 | } else { |
2304 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2305 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2306 | } |
5e84e1a4 ZW |
2307 | I915_WRITE(reg, temp); |
2308 | ||
2309 | reg = FDI_RX_CTL(pipe); | |
2310 | temp = I915_READ(reg); | |
2311 | if (HAS_PCH_CPT(dev)) { | |
2312 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2313 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2314 | } else { | |
2315 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2316 | temp |= FDI_LINK_TRAIN_NONE; | |
2317 | } | |
2318 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2319 | ||
2320 | /* wait one idle pattern time */ | |
2321 | POSTING_READ(reg); | |
2322 | udelay(1000); | |
357555c0 JB |
2323 | |
2324 | /* IVB wants error correction enabled */ | |
2325 | if (IS_IVYBRIDGE(dev)) | |
2326 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2327 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2328 | } |
2329 | ||
1e833f40 DV |
2330 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2331 | { | |
2332 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; | |
2333 | } | |
2334 | ||
01a415fd DV |
2335 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2336 | { | |
2337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2338 | struct intel_crtc *pipe_B_crtc = | |
2339 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2340 | struct intel_crtc *pipe_C_crtc = | |
2341 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2342 | uint32_t temp; | |
2343 | ||
1e833f40 DV |
2344 | /* |
2345 | * When everything is off disable fdi C so that we could enable fdi B | |
2346 | * with all lanes. Note that we don't care about enabled pipes without | |
2347 | * an enabled pch encoder. | |
2348 | */ | |
2349 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2350 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2351 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2352 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2353 | ||
2354 | temp = I915_READ(SOUTH_CHICKEN1); | |
2355 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2356 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2357 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2358 | } | |
2359 | } | |
2360 | ||
8db9d77b ZW |
2361 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2362 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2363 | { | |
2364 | struct drm_device *dev = crtc->dev; | |
2365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2367 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2368 | int plane = intel_crtc->plane; |
5eddb70b | 2369 | u32 reg, temp, tries; |
8db9d77b | 2370 | |
0fc932b8 JB |
2371 | /* FDI needs bits from pipe & plane first */ |
2372 | assert_pipe_enabled(dev_priv, pipe); | |
2373 | assert_plane_enabled(dev_priv, plane); | |
2374 | ||
e1a44743 AJ |
2375 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2376 | for train result */ | |
5eddb70b CW |
2377 | reg = FDI_RX_IMR(pipe); |
2378 | temp = I915_READ(reg); | |
e1a44743 AJ |
2379 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2380 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2381 | I915_WRITE(reg, temp); |
2382 | I915_READ(reg); | |
e1a44743 AJ |
2383 | udelay(150); |
2384 | ||
8db9d77b | 2385 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2386 | reg = FDI_TX_CTL(pipe); |
2387 | temp = I915_READ(reg); | |
627eb5a3 DV |
2388 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2389 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2390 | temp &= ~FDI_LINK_TRAIN_NONE; |
2391 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2392 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2393 | |
5eddb70b CW |
2394 | reg = FDI_RX_CTL(pipe); |
2395 | temp = I915_READ(reg); | |
8db9d77b ZW |
2396 | temp &= ~FDI_LINK_TRAIN_NONE; |
2397 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2398 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2399 | ||
2400 | POSTING_READ(reg); | |
8db9d77b ZW |
2401 | udelay(150); |
2402 | ||
5b2adf89 | 2403 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2404 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2405 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2406 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2407 | |
5eddb70b | 2408 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2409 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2410 | temp = I915_READ(reg); |
8db9d77b ZW |
2411 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2412 | ||
2413 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2414 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2415 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2416 | break; |
2417 | } | |
8db9d77b | 2418 | } |
e1a44743 | 2419 | if (tries == 5) |
5eddb70b | 2420 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2421 | |
2422 | /* Train 2 */ | |
5eddb70b CW |
2423 | reg = FDI_TX_CTL(pipe); |
2424 | temp = I915_READ(reg); | |
8db9d77b ZW |
2425 | temp &= ~FDI_LINK_TRAIN_NONE; |
2426 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2427 | I915_WRITE(reg, temp); |
8db9d77b | 2428 | |
5eddb70b CW |
2429 | reg = FDI_RX_CTL(pipe); |
2430 | temp = I915_READ(reg); | |
8db9d77b ZW |
2431 | temp &= ~FDI_LINK_TRAIN_NONE; |
2432 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2433 | I915_WRITE(reg, temp); |
8db9d77b | 2434 | |
5eddb70b CW |
2435 | POSTING_READ(reg); |
2436 | udelay(150); | |
8db9d77b | 2437 | |
5eddb70b | 2438 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2439 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2440 | temp = I915_READ(reg); |
8db9d77b ZW |
2441 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2442 | ||
2443 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2444 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2445 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2446 | break; | |
2447 | } | |
8db9d77b | 2448 | } |
e1a44743 | 2449 | if (tries == 5) |
5eddb70b | 2450 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2451 | |
2452 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2453 | |
8db9d77b ZW |
2454 | } |
2455 | ||
0206e353 | 2456 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2457 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2458 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2459 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2460 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2461 | }; | |
2462 | ||
2463 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2464 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2465 | { | |
2466 | struct drm_device *dev = crtc->dev; | |
2467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2469 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2470 | u32 reg, temp, i, retry; |
8db9d77b | 2471 | |
e1a44743 AJ |
2472 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2473 | for train result */ | |
5eddb70b CW |
2474 | reg = FDI_RX_IMR(pipe); |
2475 | temp = I915_READ(reg); | |
e1a44743 AJ |
2476 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2477 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2478 | I915_WRITE(reg, temp); |
2479 | ||
2480 | POSTING_READ(reg); | |
e1a44743 AJ |
2481 | udelay(150); |
2482 | ||
8db9d77b | 2483 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2484 | reg = FDI_TX_CTL(pipe); |
2485 | temp = I915_READ(reg); | |
627eb5a3 DV |
2486 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2487 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2488 | temp &= ~FDI_LINK_TRAIN_NONE; |
2489 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2490 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2491 | /* SNB-B */ | |
2492 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2493 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2494 | |
d74cf324 DV |
2495 | I915_WRITE(FDI_RX_MISC(pipe), |
2496 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2497 | ||
5eddb70b CW |
2498 | reg = FDI_RX_CTL(pipe); |
2499 | temp = I915_READ(reg); | |
8db9d77b ZW |
2500 | if (HAS_PCH_CPT(dev)) { |
2501 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2502 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2503 | } else { | |
2504 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2505 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2506 | } | |
5eddb70b CW |
2507 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2508 | ||
2509 | POSTING_READ(reg); | |
8db9d77b ZW |
2510 | udelay(150); |
2511 | ||
0206e353 | 2512 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2513 | reg = FDI_TX_CTL(pipe); |
2514 | temp = I915_READ(reg); | |
8db9d77b ZW |
2515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2516 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2517 | I915_WRITE(reg, temp); |
2518 | ||
2519 | POSTING_READ(reg); | |
8db9d77b ZW |
2520 | udelay(500); |
2521 | ||
fa37d39e SP |
2522 | for (retry = 0; retry < 5; retry++) { |
2523 | reg = FDI_RX_IIR(pipe); | |
2524 | temp = I915_READ(reg); | |
2525 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2526 | if (temp & FDI_RX_BIT_LOCK) { | |
2527 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2528 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2529 | break; | |
2530 | } | |
2531 | udelay(50); | |
8db9d77b | 2532 | } |
fa37d39e SP |
2533 | if (retry < 5) |
2534 | break; | |
8db9d77b ZW |
2535 | } |
2536 | if (i == 4) | |
5eddb70b | 2537 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2538 | |
2539 | /* Train 2 */ | |
5eddb70b CW |
2540 | reg = FDI_TX_CTL(pipe); |
2541 | temp = I915_READ(reg); | |
8db9d77b ZW |
2542 | temp &= ~FDI_LINK_TRAIN_NONE; |
2543 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2544 | if (IS_GEN6(dev)) { | |
2545 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2546 | /* SNB-B */ | |
2547 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2548 | } | |
5eddb70b | 2549 | I915_WRITE(reg, temp); |
8db9d77b | 2550 | |
5eddb70b CW |
2551 | reg = FDI_RX_CTL(pipe); |
2552 | temp = I915_READ(reg); | |
8db9d77b ZW |
2553 | if (HAS_PCH_CPT(dev)) { |
2554 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2555 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2556 | } else { | |
2557 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2558 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2559 | } | |
5eddb70b CW |
2560 | I915_WRITE(reg, temp); |
2561 | ||
2562 | POSTING_READ(reg); | |
8db9d77b ZW |
2563 | udelay(150); |
2564 | ||
0206e353 | 2565 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2566 | reg = FDI_TX_CTL(pipe); |
2567 | temp = I915_READ(reg); | |
8db9d77b ZW |
2568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2569 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2570 | I915_WRITE(reg, temp); |
2571 | ||
2572 | POSTING_READ(reg); | |
8db9d77b ZW |
2573 | udelay(500); |
2574 | ||
fa37d39e SP |
2575 | for (retry = 0; retry < 5; retry++) { |
2576 | reg = FDI_RX_IIR(pipe); | |
2577 | temp = I915_READ(reg); | |
2578 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2579 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2580 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2581 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2582 | break; | |
2583 | } | |
2584 | udelay(50); | |
8db9d77b | 2585 | } |
fa37d39e SP |
2586 | if (retry < 5) |
2587 | break; | |
8db9d77b ZW |
2588 | } |
2589 | if (i == 4) | |
5eddb70b | 2590 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2591 | |
2592 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2593 | } | |
2594 | ||
357555c0 JB |
2595 | /* Manual link training for Ivy Bridge A0 parts */ |
2596 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2597 | { | |
2598 | struct drm_device *dev = crtc->dev; | |
2599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2601 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2602 | u32 reg, temp, i, j; |
357555c0 JB |
2603 | |
2604 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2605 | for train result */ | |
2606 | reg = FDI_RX_IMR(pipe); | |
2607 | temp = I915_READ(reg); | |
2608 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2609 | temp &= ~FDI_RX_BIT_LOCK; | |
2610 | I915_WRITE(reg, temp); | |
2611 | ||
2612 | POSTING_READ(reg); | |
2613 | udelay(150); | |
2614 | ||
01a415fd DV |
2615 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2616 | I915_READ(FDI_RX_IIR(pipe))); | |
2617 | ||
139ccd3f JB |
2618 | /* Try each vswing and preemphasis setting twice before moving on */ |
2619 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2620 | /* disable first in case we need to retry */ | |
2621 | reg = FDI_TX_CTL(pipe); | |
2622 | temp = I915_READ(reg); | |
2623 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2624 | temp &= ~FDI_TX_ENABLE; | |
2625 | I915_WRITE(reg, temp); | |
357555c0 | 2626 | |
139ccd3f JB |
2627 | reg = FDI_RX_CTL(pipe); |
2628 | temp = I915_READ(reg); | |
2629 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2630 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2631 | temp &= ~FDI_RX_ENABLE; | |
2632 | I915_WRITE(reg, temp); | |
357555c0 | 2633 | |
139ccd3f | 2634 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2635 | reg = FDI_TX_CTL(pipe); |
2636 | temp = I915_READ(reg); | |
139ccd3f JB |
2637 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2638 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2639 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2640 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2641 | temp |= snb_b_fdi_train_param[j/2]; |
2642 | temp |= FDI_COMPOSITE_SYNC; | |
2643 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2644 | |
139ccd3f JB |
2645 | I915_WRITE(FDI_RX_MISC(pipe), |
2646 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2647 | |
139ccd3f | 2648 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2649 | temp = I915_READ(reg); |
139ccd3f JB |
2650 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2651 | temp |= FDI_COMPOSITE_SYNC; | |
2652 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2653 | |
139ccd3f JB |
2654 | POSTING_READ(reg); |
2655 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2656 | |
139ccd3f JB |
2657 | for (i = 0; i < 4; i++) { |
2658 | reg = FDI_RX_IIR(pipe); | |
2659 | temp = I915_READ(reg); | |
2660 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2661 | |
139ccd3f JB |
2662 | if (temp & FDI_RX_BIT_LOCK || |
2663 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2664 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2665 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2666 | i); | |
2667 | break; | |
2668 | } | |
2669 | udelay(1); /* should be 0.5us */ | |
2670 | } | |
2671 | if (i == 4) { | |
2672 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2673 | continue; | |
2674 | } | |
357555c0 | 2675 | |
139ccd3f | 2676 | /* Train 2 */ |
357555c0 JB |
2677 | reg = FDI_TX_CTL(pipe); |
2678 | temp = I915_READ(reg); | |
139ccd3f JB |
2679 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2680 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2681 | I915_WRITE(reg, temp); | |
2682 | ||
2683 | reg = FDI_RX_CTL(pipe); | |
2684 | temp = I915_READ(reg); | |
2685 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2686 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2687 | I915_WRITE(reg, temp); |
2688 | ||
2689 | POSTING_READ(reg); | |
139ccd3f | 2690 | udelay(2); /* should be 1.5us */ |
357555c0 | 2691 | |
139ccd3f JB |
2692 | for (i = 0; i < 4; i++) { |
2693 | reg = FDI_RX_IIR(pipe); | |
2694 | temp = I915_READ(reg); | |
2695 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2696 | |
139ccd3f JB |
2697 | if (temp & FDI_RX_SYMBOL_LOCK || |
2698 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2699 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2700 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2701 | i); | |
2702 | goto train_done; | |
2703 | } | |
2704 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2705 | } |
139ccd3f JB |
2706 | if (i == 4) |
2707 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2708 | } |
357555c0 | 2709 | |
139ccd3f | 2710 | train_done: |
357555c0 JB |
2711 | DRM_DEBUG_KMS("FDI train done.\n"); |
2712 | } | |
2713 | ||
88cefb6c | 2714 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2715 | { |
88cefb6c | 2716 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2717 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2718 | int pipe = intel_crtc->pipe; |
5eddb70b | 2719 | u32 reg, temp; |
79e53945 | 2720 | |
c64e311e | 2721 | |
c98e9dcf | 2722 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2723 | reg = FDI_RX_CTL(pipe); |
2724 | temp = I915_READ(reg); | |
627eb5a3 DV |
2725 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2726 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2727 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2728 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2729 | ||
2730 | POSTING_READ(reg); | |
c98e9dcf JB |
2731 | udelay(200); |
2732 | ||
2733 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2734 | temp = I915_READ(reg); |
2735 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2736 | ||
2737 | POSTING_READ(reg); | |
c98e9dcf JB |
2738 | udelay(200); |
2739 | ||
20749730 PZ |
2740 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2741 | reg = FDI_TX_CTL(pipe); | |
2742 | temp = I915_READ(reg); | |
2743 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2744 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2745 | |
20749730 PZ |
2746 | POSTING_READ(reg); |
2747 | udelay(100); | |
6be4a607 | 2748 | } |
0e23b99d JB |
2749 | } |
2750 | ||
88cefb6c DV |
2751 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2752 | { | |
2753 | struct drm_device *dev = intel_crtc->base.dev; | |
2754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2755 | int pipe = intel_crtc->pipe; | |
2756 | u32 reg, temp; | |
2757 | ||
2758 | /* Switch from PCDclk to Rawclk */ | |
2759 | reg = FDI_RX_CTL(pipe); | |
2760 | temp = I915_READ(reg); | |
2761 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2762 | ||
2763 | /* Disable CPU FDI TX PLL */ | |
2764 | reg = FDI_TX_CTL(pipe); | |
2765 | temp = I915_READ(reg); | |
2766 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2767 | ||
2768 | POSTING_READ(reg); | |
2769 | udelay(100); | |
2770 | ||
2771 | reg = FDI_RX_CTL(pipe); | |
2772 | temp = I915_READ(reg); | |
2773 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2774 | ||
2775 | /* Wait for the clocks to turn off. */ | |
2776 | POSTING_READ(reg); | |
2777 | udelay(100); | |
2778 | } | |
2779 | ||
0fc932b8 JB |
2780 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2781 | { | |
2782 | struct drm_device *dev = crtc->dev; | |
2783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2785 | int pipe = intel_crtc->pipe; | |
2786 | u32 reg, temp; | |
2787 | ||
2788 | /* disable CPU FDI tx and PCH FDI rx */ | |
2789 | reg = FDI_TX_CTL(pipe); | |
2790 | temp = I915_READ(reg); | |
2791 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2792 | POSTING_READ(reg); | |
2793 | ||
2794 | reg = FDI_RX_CTL(pipe); | |
2795 | temp = I915_READ(reg); | |
2796 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2797 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2798 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2799 | ||
2800 | POSTING_READ(reg); | |
2801 | udelay(100); | |
2802 | ||
2803 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2804 | if (HAS_PCH_IBX(dev)) { |
2805 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2806 | } |
0fc932b8 JB |
2807 | |
2808 | /* still set train pattern 1 */ | |
2809 | reg = FDI_TX_CTL(pipe); | |
2810 | temp = I915_READ(reg); | |
2811 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2812 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2813 | I915_WRITE(reg, temp); | |
2814 | ||
2815 | reg = FDI_RX_CTL(pipe); | |
2816 | temp = I915_READ(reg); | |
2817 | if (HAS_PCH_CPT(dev)) { | |
2818 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2819 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2820 | } else { | |
2821 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2822 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2823 | } | |
2824 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2825 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2826 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2827 | I915_WRITE(reg, temp); |
2828 | ||
2829 | POSTING_READ(reg); | |
2830 | udelay(100); | |
2831 | } | |
2832 | ||
5bb61643 CW |
2833 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2834 | { | |
2835 | struct drm_device *dev = crtc->dev; | |
2836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2838 | unsigned long flags; |
2839 | bool pending; | |
2840 | ||
10d83730 VS |
2841 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2842 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2843 | return false; |
2844 | ||
2845 | spin_lock_irqsave(&dev->event_lock, flags); | |
2846 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2847 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2848 | ||
2849 | return pending; | |
2850 | } | |
2851 | ||
e6c3a2a6 CW |
2852 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2853 | { | |
0f91128d | 2854 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2855 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2856 | |
2857 | if (crtc->fb == NULL) | |
2858 | return; | |
2859 | ||
2c10d571 DV |
2860 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2861 | ||
5bb61643 CW |
2862 | wait_event(dev_priv->pending_flip_queue, |
2863 | !intel_crtc_has_pending_flip(crtc)); | |
2864 | ||
0f91128d CW |
2865 | mutex_lock(&dev->struct_mutex); |
2866 | intel_finish_fb(crtc->fb); | |
2867 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2868 | } |
2869 | ||
e615efe4 ED |
2870 | /* Program iCLKIP clock to the desired frequency */ |
2871 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2872 | { | |
2873 | struct drm_device *dev = crtc->dev; | |
2874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2875 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2876 | u32 temp; | |
2877 | ||
09153000 DV |
2878 | mutex_lock(&dev_priv->dpio_lock); |
2879 | ||
e615efe4 ED |
2880 | /* It is necessary to ungate the pixclk gate prior to programming |
2881 | * the divisors, and gate it back when it is done. | |
2882 | */ | |
2883 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2884 | ||
2885 | /* Disable SSCCTL */ | |
2886 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2887 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2888 | SBI_SSCCTL_DISABLE, | |
2889 | SBI_ICLK); | |
e615efe4 ED |
2890 | |
2891 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2892 | if (crtc->mode.clock == 20000) { | |
2893 | auxdiv = 1; | |
2894 | divsel = 0x41; | |
2895 | phaseinc = 0x20; | |
2896 | } else { | |
2897 | /* The iCLK virtual clock root frequency is in MHz, | |
2898 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2899 | * it is necessary to divide one by another, so we | |
2900 | * convert the virtual clock precision to KHz here for higher | |
2901 | * precision. | |
2902 | */ | |
2903 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2904 | u32 iclk_pi_range = 64; | |
2905 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2906 | ||
2907 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2908 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2909 | pi_value = desired_divisor % iclk_pi_range; | |
2910 | ||
2911 | auxdiv = 0; | |
2912 | divsel = msb_divisor_value - 2; | |
2913 | phaseinc = pi_value; | |
2914 | } | |
2915 | ||
2916 | /* This should not happen with any sane values */ | |
2917 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2918 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2919 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2920 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2921 | ||
2922 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2923 | crtc->mode.clock, | |
2924 | auxdiv, | |
2925 | divsel, | |
2926 | phasedir, | |
2927 | phaseinc); | |
2928 | ||
2929 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2930 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2931 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2932 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2933 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2934 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2935 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2936 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 2937 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
2938 | |
2939 | /* Program SSCAUXDIV */ | |
988d6ee8 | 2940 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
2941 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2942 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 2943 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
2944 | |
2945 | /* Enable modulator and associated divider */ | |
988d6ee8 | 2946 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 2947 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 2948 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
2949 | |
2950 | /* Wait for initialization time */ | |
2951 | udelay(24); | |
2952 | ||
2953 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
2954 | |
2955 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
2956 | } |
2957 | ||
275f01b2 DV |
2958 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2959 | enum pipe pch_transcoder) | |
2960 | { | |
2961 | struct drm_device *dev = crtc->base.dev; | |
2962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2963 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2964 | ||
2965 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
2966 | I915_READ(HTOTAL(cpu_transcoder))); | |
2967 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
2968 | I915_READ(HBLANK(cpu_transcoder))); | |
2969 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
2970 | I915_READ(HSYNC(cpu_transcoder))); | |
2971 | ||
2972 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
2973 | I915_READ(VTOTAL(cpu_transcoder))); | |
2974 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
2975 | I915_READ(VBLANK(cpu_transcoder))); | |
2976 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
2977 | I915_READ(VSYNC(cpu_transcoder))); | |
2978 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
2979 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
2980 | } | |
2981 | ||
f67a559d JB |
2982 | /* |
2983 | * Enable PCH resources required for PCH ports: | |
2984 | * - PCH PLLs | |
2985 | * - FDI training & RX/TX | |
2986 | * - update transcoder timings | |
2987 | * - DP transcoding bits | |
2988 | * - transcoder | |
2989 | */ | |
2990 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2991 | { |
2992 | struct drm_device *dev = crtc->dev; | |
2993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2995 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 2996 | u32 reg, temp; |
2c07245f | 2997 | |
ab9412ba | 2998 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 2999 | |
cd986abb DV |
3000 | /* Write the TU size bits before fdi link training, so that error |
3001 | * detection works. */ | |
3002 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3003 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3004 | ||
c98e9dcf | 3005 | /* For PCH output, training FDI link */ |
674cf967 | 3006 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3007 | |
3ad8a208 DV |
3008 | /* We need to program the right clock selection before writing the pixel |
3009 | * mutliplier into the DPLL. */ | |
303b81e0 | 3010 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3011 | u32 sel; |
4b645f14 | 3012 | |
c98e9dcf | 3013 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3014 | temp |= TRANS_DPLL_ENABLE(pipe); |
3015 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3016 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3017 | temp |= sel; |
3018 | else | |
3019 | temp &= ~sel; | |
c98e9dcf | 3020 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3021 | } |
5eddb70b | 3022 | |
3ad8a208 DV |
3023 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3024 | * transcoder, and we actually should do this to not upset any PCH | |
3025 | * transcoder that already use the clock when we share it. | |
3026 | * | |
3027 | * Note that enable_shared_dpll tries to do the right thing, but | |
3028 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3029 | * the right LVDS enable sequence. */ | |
3030 | ironlake_enable_shared_dpll(intel_crtc); | |
3031 | ||
d9b6cb56 JB |
3032 | /* set transcoder timing, panel must allow it */ |
3033 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3034 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3035 | |
303b81e0 | 3036 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3037 | |
c98e9dcf JB |
3038 | /* For PCH DP, enable TRANS_DP_CTL */ |
3039 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3040 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3041 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3042 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3043 | reg = TRANS_DP_CTL(pipe); |
3044 | temp = I915_READ(reg); | |
3045 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3046 | TRANS_DP_SYNC_MASK | |
3047 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3048 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3049 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3050 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3051 | |
3052 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3053 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3054 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3055 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3056 | |
3057 | switch (intel_trans_dp_port_sel(crtc)) { | |
3058 | case PCH_DP_B: | |
5eddb70b | 3059 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3060 | break; |
3061 | case PCH_DP_C: | |
5eddb70b | 3062 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3063 | break; |
3064 | case PCH_DP_D: | |
5eddb70b | 3065 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3066 | break; |
3067 | default: | |
e95d41e1 | 3068 | BUG(); |
32f9d658 | 3069 | } |
2c07245f | 3070 | |
5eddb70b | 3071 | I915_WRITE(reg, temp); |
6be4a607 | 3072 | } |
b52eb4dc | 3073 | |
b8a4f404 | 3074 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3075 | } |
3076 | ||
1507e5bd PZ |
3077 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3078 | { | |
3079 | struct drm_device *dev = crtc->dev; | |
3080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3082 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3083 | |
ab9412ba | 3084 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3085 | |
8c52b5e8 | 3086 | lpt_program_iclkip(crtc); |
1507e5bd | 3087 | |
0540e488 | 3088 | /* Set transcoder timing. */ |
275f01b2 | 3089 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3090 | |
937bb610 | 3091 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3092 | } |
3093 | ||
e2b78267 | 3094 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3095 | { |
e2b78267 | 3096 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3097 | |
3098 | if (pll == NULL) | |
3099 | return; | |
3100 | ||
3101 | if (pll->refcount == 0) { | |
46edb027 | 3102 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3103 | return; |
3104 | } | |
3105 | ||
f4a091c7 DV |
3106 | if (--pll->refcount == 0) { |
3107 | WARN_ON(pll->on); | |
3108 | WARN_ON(pll->active); | |
3109 | } | |
3110 | ||
a43f6e0f | 3111 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3112 | } |
3113 | ||
b89a1d39 | 3114 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3115 | { |
e2b78267 DV |
3116 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3117 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3118 | enum intel_dpll_id i; | |
ee7b9f93 | 3119 | |
ee7b9f93 | 3120 | if (pll) { |
46edb027 DV |
3121 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3122 | crtc->base.base.id, pll->name); | |
e2b78267 | 3123 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3124 | } |
3125 | ||
98b6bd99 DV |
3126 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3127 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3128 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3129 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3130 | |
46edb027 DV |
3131 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3132 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3133 | |
3134 | goto found; | |
3135 | } | |
3136 | ||
e72f9fbf DV |
3137 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3138 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3139 | |
3140 | /* Only want to check enabled timings first */ | |
3141 | if (pll->refcount == 0) | |
3142 | continue; | |
3143 | ||
b89a1d39 DV |
3144 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3145 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3146 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3147 | crtc->base.base.id, |
46edb027 | 3148 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3149 | |
3150 | goto found; | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3155 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3156 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3157 | if (pll->refcount == 0) { |
46edb027 DV |
3158 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3159 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3160 | goto found; |
3161 | } | |
3162 | } | |
3163 | ||
3164 | return NULL; | |
3165 | ||
3166 | found: | |
a43f6e0f | 3167 | crtc->config.shared_dpll = i; |
46edb027 DV |
3168 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3169 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3170 | |
cdbd2316 | 3171 | if (pll->active == 0) { |
66e985c0 DV |
3172 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3173 | sizeof(pll->hw_state)); | |
3174 | ||
46edb027 | 3175 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3176 | WARN_ON(pll->on); |
e9d6944e | 3177 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3178 | |
15bdd4cf | 3179 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3180 | } |
3181 | pll->refcount++; | |
e04c7350 | 3182 | |
ee7b9f93 JB |
3183 | return pll; |
3184 | } | |
3185 | ||
a1520318 | 3186 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3187 | { |
3188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3189 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3190 | u32 temp; |
3191 | ||
3192 | temp = I915_READ(dslreg); | |
3193 | udelay(500); | |
3194 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3195 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3196 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3197 | } |
3198 | } | |
3199 | ||
b074cec8 JB |
3200 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3201 | { | |
3202 | struct drm_device *dev = crtc->base.dev; | |
3203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3204 | int pipe = crtc->pipe; | |
3205 | ||
fd4daa9c | 3206 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3207 | /* Force use of hard-coded filter coefficients |
3208 | * as some pre-programmed values are broken, | |
3209 | * e.g. x201. | |
3210 | */ | |
3211 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3212 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3213 | PF_PIPE_SEL_IVB(pipe)); | |
3214 | else | |
3215 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3216 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3217 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3218 | } |
3219 | } | |
3220 | ||
bb53d4ae VS |
3221 | static void intel_enable_planes(struct drm_crtc *crtc) |
3222 | { | |
3223 | struct drm_device *dev = crtc->dev; | |
3224 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3225 | struct intel_plane *intel_plane; | |
3226 | ||
3227 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3228 | if (intel_plane->pipe == pipe) | |
3229 | intel_plane_restore(&intel_plane->base); | |
3230 | } | |
3231 | ||
3232 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3233 | { | |
3234 | struct drm_device *dev = crtc->dev; | |
3235 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3236 | struct intel_plane *intel_plane; | |
3237 | ||
3238 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3239 | if (intel_plane->pipe == pipe) | |
3240 | intel_plane_disable(&intel_plane->base); | |
3241 | } | |
3242 | ||
f67a559d JB |
3243 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3244 | { | |
3245 | struct drm_device *dev = crtc->dev; | |
3246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3248 | struct intel_encoder *encoder; |
f67a559d JB |
3249 | int pipe = intel_crtc->pipe; |
3250 | int plane = intel_crtc->plane; | |
f67a559d | 3251 | |
08a48469 DV |
3252 | WARN_ON(!crtc->enabled); |
3253 | ||
f67a559d JB |
3254 | if (intel_crtc->active) |
3255 | return; | |
3256 | ||
3257 | intel_crtc->active = true; | |
8664281b PZ |
3258 | |
3259 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3260 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3261 | ||
f67a559d JB |
3262 | intel_update_watermarks(dev); |
3263 | ||
f6736a1a | 3264 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3265 | if (encoder->pre_enable) |
3266 | encoder->pre_enable(encoder); | |
f67a559d | 3267 | |
5bfe2ac0 | 3268 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3269 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3270 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3271 | * enabling. */ | |
88cefb6c | 3272 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3273 | } else { |
3274 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3275 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3276 | } | |
f67a559d | 3277 | |
b074cec8 | 3278 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3279 | |
9c54c0dd JB |
3280 | /* |
3281 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3282 | * clocks enabled | |
3283 | */ | |
3284 | intel_crtc_load_lut(crtc); | |
3285 | ||
5bfe2ac0 DV |
3286 | intel_enable_pipe(dev_priv, pipe, |
3287 | intel_crtc->config.has_pch_encoder); | |
f67a559d | 3288 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3289 | intel_enable_planes(crtc); |
5c38d48c | 3290 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3291 | |
5bfe2ac0 | 3292 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3293 | ironlake_pch_enable(crtc); |
c98e9dcf | 3294 | |
d1ebd816 | 3295 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3296 | intel_update_fbc(dev); |
d1ebd816 BW |
3297 | mutex_unlock(&dev->struct_mutex); |
3298 | ||
fa5c73b1 DV |
3299 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3300 | encoder->enable(encoder); | |
61b77ddd DV |
3301 | |
3302 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3303 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3304 | |
3305 | /* | |
3306 | * There seems to be a race in PCH platform hw (at least on some | |
3307 | * outputs) where an enabled pipe still completes any pageflip right | |
3308 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3309 | * as the first vblank happend, everything works as expected. Hence just | |
3310 | * wait for one vblank before returning to avoid strange things | |
3311 | * happening. | |
3312 | */ | |
3313 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3314 | } |
3315 | ||
42db64ef PZ |
3316 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3317 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3318 | { | |
f5adf94e | 3319 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3320 | } |
3321 | ||
3322 | static void hsw_enable_ips(struct intel_crtc *crtc) | |
3323 | { | |
3324 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3325 | ||
3326 | if (!crtc->config.ips_enabled) | |
3327 | return; | |
3328 | ||
3329 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3330 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3331 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3332 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3333 | assert_plane_enabled(dev_priv, crtc->plane); | |
3334 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3335 | } | |
3336 | ||
3337 | static void hsw_disable_ips(struct intel_crtc *crtc) | |
3338 | { | |
3339 | struct drm_device *dev = crtc->base.dev; | |
3340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3341 | ||
3342 | if (!crtc->config.ips_enabled) | |
3343 | return; | |
3344 | ||
3345 | assert_plane_enabled(dev_priv, crtc->plane); | |
3346 | I915_WRITE(IPS_CTL, 0); | |
3347 | ||
3348 | /* We need to wait for a vblank before we can disable the plane. */ | |
3349 | intel_wait_for_vblank(dev, crtc->pipe); | |
3350 | } | |
3351 | ||
4f771f10 PZ |
3352 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3353 | { | |
3354 | struct drm_device *dev = crtc->dev; | |
3355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3357 | struct intel_encoder *encoder; | |
3358 | int pipe = intel_crtc->pipe; | |
3359 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3360 | |
3361 | WARN_ON(!crtc->enabled); | |
3362 | ||
3363 | if (intel_crtc->active) | |
3364 | return; | |
3365 | ||
3366 | intel_crtc->active = true; | |
8664281b PZ |
3367 | |
3368 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3369 | if (intel_crtc->config.has_pch_encoder) | |
3370 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3371 | ||
4f771f10 PZ |
3372 | intel_update_watermarks(dev); |
3373 | ||
5bfe2ac0 | 3374 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3375 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3376 | |
3377 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3378 | if (encoder->pre_enable) | |
3379 | encoder->pre_enable(encoder); | |
3380 | ||
1f544388 | 3381 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3382 | |
b074cec8 | 3383 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3384 | |
3385 | /* | |
3386 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3387 | * clocks enabled | |
3388 | */ | |
3389 | intel_crtc_load_lut(crtc); | |
3390 | ||
1f544388 | 3391 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3392 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3393 | |
5bfe2ac0 DV |
3394 | intel_enable_pipe(dev_priv, pipe, |
3395 | intel_crtc->config.has_pch_encoder); | |
4f771f10 | 3396 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3397 | intel_enable_planes(crtc); |
5c38d48c | 3398 | intel_crtc_update_cursor(crtc, true); |
4f771f10 | 3399 | |
42db64ef PZ |
3400 | hsw_enable_ips(intel_crtc); |
3401 | ||
5bfe2ac0 | 3402 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3403 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3404 | |
3405 | mutex_lock(&dev->struct_mutex); | |
3406 | intel_update_fbc(dev); | |
3407 | mutex_unlock(&dev->struct_mutex); | |
3408 | ||
4f771f10 PZ |
3409 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3410 | encoder->enable(encoder); | |
3411 | ||
4f771f10 PZ |
3412 | /* |
3413 | * There seems to be a race in PCH platform hw (at least on some | |
3414 | * outputs) where an enabled pipe still completes any pageflip right | |
3415 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3416 | * as the first vblank happend, everything works as expected. Hence just | |
3417 | * wait for one vblank before returning to avoid strange things | |
3418 | * happening. | |
3419 | */ | |
3420 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3421 | } | |
3422 | ||
3f8dce3a DV |
3423 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3424 | { | |
3425 | struct drm_device *dev = crtc->base.dev; | |
3426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3427 | int pipe = crtc->pipe; | |
3428 | ||
3429 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3430 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3431 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3432 | I915_WRITE(PF_CTL(pipe), 0); |
3433 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3434 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3435 | } | |
3436 | } | |
3437 | ||
6be4a607 JB |
3438 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3439 | { | |
3440 | struct drm_device *dev = crtc->dev; | |
3441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3443 | struct intel_encoder *encoder; |
6be4a607 JB |
3444 | int pipe = intel_crtc->pipe; |
3445 | int plane = intel_crtc->plane; | |
5eddb70b | 3446 | u32 reg, temp; |
b52eb4dc | 3447 | |
ef9c3aee | 3448 | |
f7abfe8b CW |
3449 | if (!intel_crtc->active) |
3450 | return; | |
3451 | ||
ea9d758d DV |
3452 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3453 | encoder->disable(encoder); | |
3454 | ||
e6c3a2a6 | 3455 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3456 | drm_vblank_off(dev, pipe); |
913d8d11 | 3457 | |
5c3fe8b0 | 3458 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3459 | intel_disable_fbc(dev); |
2c07245f | 3460 | |
0d5b8c61 | 3461 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3462 | intel_disable_planes(crtc); |
0d5b8c61 VS |
3463 | intel_disable_plane(dev_priv, plane, pipe); |
3464 | ||
d925c59a DV |
3465 | if (intel_crtc->config.has_pch_encoder) |
3466 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3467 | ||
b24e7179 | 3468 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3469 | |
3f8dce3a | 3470 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3471 | |
bf49ec8c DV |
3472 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3473 | if (encoder->post_disable) | |
3474 | encoder->post_disable(encoder); | |
2c07245f | 3475 | |
d925c59a DV |
3476 | if (intel_crtc->config.has_pch_encoder) { |
3477 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3478 | |
d925c59a DV |
3479 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3480 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3481 | |
d925c59a DV |
3482 | if (HAS_PCH_CPT(dev)) { |
3483 | /* disable TRANS_DP_CTL */ | |
3484 | reg = TRANS_DP_CTL(pipe); | |
3485 | temp = I915_READ(reg); | |
3486 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3487 | TRANS_DP_PORT_SEL_MASK); | |
3488 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3489 | I915_WRITE(reg, temp); | |
3490 | ||
3491 | /* disable DPLL_SEL */ | |
3492 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3493 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3494 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3495 | } |
e3421a18 | 3496 | |
d925c59a | 3497 | /* disable PCH DPLL */ |
e72f9fbf | 3498 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3499 | |
d925c59a DV |
3500 | ironlake_fdi_pll_disable(intel_crtc); |
3501 | } | |
6b383a7f | 3502 | |
f7abfe8b | 3503 | intel_crtc->active = false; |
6b383a7f | 3504 | intel_update_watermarks(dev); |
d1ebd816 BW |
3505 | |
3506 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3507 | intel_update_fbc(dev); |
d1ebd816 | 3508 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3509 | } |
1b3c7a47 | 3510 | |
4f771f10 | 3511 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3512 | { |
4f771f10 PZ |
3513 | struct drm_device *dev = crtc->dev; |
3514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3516 | struct intel_encoder *encoder; |
3517 | int pipe = intel_crtc->pipe; | |
3518 | int plane = intel_crtc->plane; | |
3b117c8f | 3519 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3520 | |
4f771f10 PZ |
3521 | if (!intel_crtc->active) |
3522 | return; | |
3523 | ||
3524 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3525 | encoder->disable(encoder); | |
3526 | ||
3527 | intel_crtc_wait_for_pending_flips(crtc); | |
3528 | drm_vblank_off(dev, pipe); | |
4f771f10 | 3529 | |
891348b2 | 3530 | /* FBC must be disabled before disabling the plane on HSW. */ |
5c3fe8b0 | 3531 | if (dev_priv->fbc.plane == plane) |
4f771f10 PZ |
3532 | intel_disable_fbc(dev); |
3533 | ||
42db64ef PZ |
3534 | hsw_disable_ips(intel_crtc); |
3535 | ||
0d5b8c61 | 3536 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3537 | intel_disable_planes(crtc); |
891348b2 RV |
3538 | intel_disable_plane(dev_priv, plane, pipe); |
3539 | ||
8664281b PZ |
3540 | if (intel_crtc->config.has_pch_encoder) |
3541 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3542 | intel_disable_pipe(dev_priv, pipe); |
3543 | ||
ad80a810 | 3544 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3545 | |
3f8dce3a | 3546 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3547 | |
1f544388 | 3548 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3549 | |
3550 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3551 | if (encoder->post_disable) | |
3552 | encoder->post_disable(encoder); | |
3553 | ||
88adfff1 | 3554 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3555 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3556 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3557 | intel_ddi_fdi_disable(crtc); |
83616634 | 3558 | } |
4f771f10 PZ |
3559 | |
3560 | intel_crtc->active = false; | |
3561 | intel_update_watermarks(dev); | |
3562 | ||
3563 | mutex_lock(&dev->struct_mutex); | |
3564 | intel_update_fbc(dev); | |
3565 | mutex_unlock(&dev->struct_mutex); | |
3566 | } | |
3567 | ||
ee7b9f93 JB |
3568 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3569 | { | |
3570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3571 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3572 | } |
3573 | ||
6441ab5f PZ |
3574 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3575 | { | |
3576 | intel_ddi_put_crtc_pll(crtc); | |
3577 | } | |
3578 | ||
02e792fb DV |
3579 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3580 | { | |
02e792fb | 3581 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3582 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3583 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3584 | |
23f09ce3 | 3585 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3586 | dev_priv->mm.interruptible = false; |
3587 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3588 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3589 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3590 | } |
02e792fb | 3591 | |
5dcdbcb0 CW |
3592 | /* Let userspace switch the overlay on again. In most cases userspace |
3593 | * has to recompute where to put it anyway. | |
3594 | */ | |
02e792fb DV |
3595 | } |
3596 | ||
61bc95c1 EE |
3597 | /** |
3598 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3599 | * cursor plane briefly if not already running after enabling the display | |
3600 | * plane. | |
3601 | * This workaround avoids occasional blank screens when self refresh is | |
3602 | * enabled. | |
3603 | */ | |
3604 | static void | |
3605 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3606 | { | |
3607 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3608 | ||
3609 | if ((cntl & CURSOR_MODE) == 0) { | |
3610 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3611 | ||
3612 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3613 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3614 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3615 | I915_WRITE(CURCNTR(pipe), cntl); | |
3616 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3617 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3618 | } | |
3619 | } | |
3620 | ||
2dd24552 JB |
3621 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3622 | { | |
3623 | struct drm_device *dev = crtc->base.dev; | |
3624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3625 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3626 | ||
328d8e82 | 3627 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3628 | return; |
3629 | ||
2dd24552 | 3630 | /* |
c0b03411 DV |
3631 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3632 | * according to register description and PRM. | |
2dd24552 | 3633 | */ |
c0b03411 DV |
3634 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3635 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3636 | |
b074cec8 JB |
3637 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3638 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3639 | |
3640 | /* Border color in case we don't scale up to the full screen. Black by | |
3641 | * default, change to something else for debugging. */ | |
3642 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3643 | } |
3644 | ||
89b667f8 JB |
3645 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3646 | { | |
3647 | struct drm_device *dev = crtc->dev; | |
3648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3650 | struct intel_encoder *encoder; | |
3651 | int pipe = intel_crtc->pipe; | |
3652 | int plane = intel_crtc->plane; | |
3653 | ||
3654 | WARN_ON(!crtc->enabled); | |
3655 | ||
3656 | if (intel_crtc->active) | |
3657 | return; | |
3658 | ||
3659 | intel_crtc->active = true; | |
3660 | intel_update_watermarks(dev); | |
3661 | ||
89b667f8 JB |
3662 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3663 | if (encoder->pre_pll_enable) | |
3664 | encoder->pre_pll_enable(encoder); | |
3665 | ||
426115cf | 3666 | vlv_enable_pll(intel_crtc); |
89b667f8 JB |
3667 | |
3668 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3669 | if (encoder->pre_enable) | |
3670 | encoder->pre_enable(encoder); | |
3671 | ||
2dd24552 JB |
3672 | i9xx_pfit_enable(intel_crtc); |
3673 | ||
63cbb074 VS |
3674 | intel_crtc_load_lut(crtc); |
3675 | ||
89b667f8 JB |
3676 | intel_enable_pipe(dev_priv, pipe, false); |
3677 | intel_enable_plane(dev_priv, plane, pipe); | |
bb53d4ae | 3678 | intel_enable_planes(crtc); |
5c38d48c | 3679 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 3680 | |
89b667f8 | 3681 | intel_update_fbc(dev); |
5004945f JN |
3682 | |
3683 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3684 | encoder->enable(encoder); | |
89b667f8 JB |
3685 | } |
3686 | ||
0b8765c6 | 3687 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3688 | { |
3689 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; |
3691 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3692 | struct intel_encoder *encoder; |
79e53945 | 3693 | int pipe = intel_crtc->pipe; |
80824003 | 3694 | int plane = intel_crtc->plane; |
79e53945 | 3695 | |
08a48469 DV |
3696 | WARN_ON(!crtc->enabled); |
3697 | ||
f7abfe8b CW |
3698 | if (intel_crtc->active) |
3699 | return; | |
3700 | ||
3701 | intel_crtc->active = true; | |
6b383a7f CW |
3702 | intel_update_watermarks(dev); |
3703 | ||
9d6d9f19 MK |
3704 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3705 | if (encoder->pre_enable) | |
3706 | encoder->pre_enable(encoder); | |
3707 | ||
f6736a1a DV |
3708 | i9xx_enable_pll(intel_crtc); |
3709 | ||
2dd24552 JB |
3710 | i9xx_pfit_enable(intel_crtc); |
3711 | ||
63cbb074 VS |
3712 | intel_crtc_load_lut(crtc); |
3713 | ||
040484af | 3714 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3715 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3716 | intel_enable_planes(crtc); |
22e407d7 | 3717 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
3718 | if (IS_G4X(dev)) |
3719 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 3720 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 3721 | |
0b8765c6 JB |
3722 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3723 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 3724 | |
f440eb13 | 3725 | intel_update_fbc(dev); |
ef9c3aee | 3726 | |
fa5c73b1 DV |
3727 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3728 | encoder->enable(encoder); | |
0b8765c6 | 3729 | } |
79e53945 | 3730 | |
87476d63 DV |
3731 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3732 | { | |
3733 | struct drm_device *dev = crtc->base.dev; | |
3734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 3735 | |
328d8e82 DV |
3736 | if (!crtc->config.gmch_pfit.control) |
3737 | return; | |
87476d63 | 3738 | |
328d8e82 | 3739 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 3740 | |
328d8e82 DV |
3741 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3742 | I915_READ(PFIT_CONTROL)); | |
3743 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
3744 | } |
3745 | ||
0b8765c6 JB |
3746 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3747 | { | |
3748 | struct drm_device *dev = crtc->dev; | |
3749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3751 | struct intel_encoder *encoder; |
0b8765c6 JB |
3752 | int pipe = intel_crtc->pipe; |
3753 | int plane = intel_crtc->plane; | |
ef9c3aee | 3754 | |
f7abfe8b CW |
3755 | if (!intel_crtc->active) |
3756 | return; | |
3757 | ||
ea9d758d DV |
3758 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3759 | encoder->disable(encoder); | |
3760 | ||
0b8765c6 | 3761 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3762 | intel_crtc_wait_for_pending_flips(crtc); |
3763 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3764 | |
5c3fe8b0 | 3765 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3766 | intel_disable_fbc(dev); |
79e53945 | 3767 | |
0d5b8c61 VS |
3768 | intel_crtc_dpms_overlay(intel_crtc, false); |
3769 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 3770 | intel_disable_planes(crtc); |
b24e7179 | 3771 | intel_disable_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3772 | |
b24e7179 | 3773 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 3774 | |
87476d63 | 3775 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 3776 | |
89b667f8 JB |
3777 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3778 | if (encoder->post_disable) | |
3779 | encoder->post_disable(encoder); | |
3780 | ||
50b44a44 | 3781 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 3782 | |
f7abfe8b | 3783 | intel_crtc->active = false; |
6b383a7f CW |
3784 | intel_update_fbc(dev); |
3785 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3786 | } |
3787 | ||
ee7b9f93 JB |
3788 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3789 | { | |
3790 | } | |
3791 | ||
976f8a20 DV |
3792 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3793 | bool enabled) | |
2c07245f ZW |
3794 | { |
3795 | struct drm_device *dev = crtc->dev; | |
3796 | struct drm_i915_master_private *master_priv; | |
3797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3798 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3799 | |
3800 | if (!dev->primary->master) | |
3801 | return; | |
3802 | ||
3803 | master_priv = dev->primary->master->driver_priv; | |
3804 | if (!master_priv->sarea_priv) | |
3805 | return; | |
3806 | ||
79e53945 JB |
3807 | switch (pipe) { |
3808 | case 0: | |
3809 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3810 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3811 | break; | |
3812 | case 1: | |
3813 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3814 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3815 | break; | |
3816 | default: | |
9db4a9c7 | 3817 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3818 | break; |
3819 | } | |
79e53945 JB |
3820 | } |
3821 | ||
976f8a20 DV |
3822 | /** |
3823 | * Sets the power management mode of the pipe and plane. | |
3824 | */ | |
3825 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3826 | { | |
3827 | struct drm_device *dev = crtc->dev; | |
3828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3829 | struct intel_encoder *intel_encoder; | |
3830 | bool enable = false; | |
3831 | ||
3832 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3833 | enable |= intel_encoder->connectors_active; | |
3834 | ||
3835 | if (enable) | |
3836 | dev_priv->display.crtc_enable(crtc); | |
3837 | else | |
3838 | dev_priv->display.crtc_disable(crtc); | |
3839 | ||
3840 | intel_crtc_update_sarea(crtc, enable); | |
3841 | } | |
3842 | ||
cdd59983 CW |
3843 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3844 | { | |
cdd59983 | 3845 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3846 | struct drm_connector *connector; |
ee7b9f93 | 3847 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 3848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 3849 | |
976f8a20 DV |
3850 | /* crtc should still be enabled when we disable it. */ |
3851 | WARN_ON(!crtc->enabled); | |
3852 | ||
3853 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 3854 | intel_crtc->eld_vld = false; |
976f8a20 | 3855 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
3856 | dev_priv->display.off(crtc); |
3857 | ||
931872fc CW |
3858 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3859 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3860 | |
3861 | if (crtc->fb) { | |
3862 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3863 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3864 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3865 | crtc->fb = NULL; |
3866 | } | |
3867 | ||
3868 | /* Update computed state. */ | |
3869 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3870 | if (!connector->encoder || !connector->encoder->crtc) | |
3871 | continue; | |
3872 | ||
3873 | if (connector->encoder->crtc != crtc) | |
3874 | continue; | |
3875 | ||
3876 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3877 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3878 | } |
3879 | } | |
3880 | ||
ea5b213a | 3881 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3882 | { |
4ef69c7a | 3883 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3884 | |
ea5b213a CW |
3885 | drm_encoder_cleanup(encoder); |
3886 | kfree(intel_encoder); | |
7e7d76c3 JB |
3887 | } |
3888 | ||
9237329d | 3889 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
3890 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3891 | * state of the entire output pipe. */ | |
9237329d | 3892 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 3893 | { |
5ab432ef DV |
3894 | if (mode == DRM_MODE_DPMS_ON) { |
3895 | encoder->connectors_active = true; | |
3896 | ||
b2cabb0e | 3897 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3898 | } else { |
3899 | encoder->connectors_active = false; | |
3900 | ||
b2cabb0e | 3901 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3902 | } |
79e53945 JB |
3903 | } |
3904 | ||
0a91ca29 DV |
3905 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3906 | * internal consistency). */ | |
b980514c | 3907 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3908 | { |
0a91ca29 DV |
3909 | if (connector->get_hw_state(connector)) { |
3910 | struct intel_encoder *encoder = connector->encoder; | |
3911 | struct drm_crtc *crtc; | |
3912 | bool encoder_enabled; | |
3913 | enum pipe pipe; | |
3914 | ||
3915 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3916 | connector->base.base.id, | |
3917 | drm_get_connector_name(&connector->base)); | |
3918 | ||
3919 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3920 | "wrong connector dpms state\n"); | |
3921 | WARN(connector->base.encoder != &encoder->base, | |
3922 | "active connector not linked to encoder\n"); | |
3923 | WARN(!encoder->connectors_active, | |
3924 | "encoder->connectors_active not set\n"); | |
3925 | ||
3926 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3927 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3928 | if (WARN_ON(!encoder->base.crtc)) | |
3929 | return; | |
3930 | ||
3931 | crtc = encoder->base.crtc; | |
3932 | ||
3933 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3934 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3935 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3936 | "encoder active on the wrong pipe\n"); | |
3937 | } | |
79e53945 JB |
3938 | } |
3939 | ||
5ab432ef DV |
3940 | /* Even simpler default implementation, if there's really no special case to |
3941 | * consider. */ | |
3942 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3943 | { |
5ab432ef | 3944 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3945 | |
5ab432ef DV |
3946 | /* All the simple cases only support two dpms states. */ |
3947 | if (mode != DRM_MODE_DPMS_ON) | |
3948 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3949 | |
5ab432ef DV |
3950 | if (mode == connector->dpms) |
3951 | return; | |
3952 | ||
3953 | connector->dpms = mode; | |
3954 | ||
3955 | /* Only need to change hw state when actually enabled */ | |
3956 | if (encoder->base.crtc) | |
3957 | intel_encoder_dpms(encoder, mode); | |
3958 | else | |
8af6cf88 | 3959 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3960 | |
b980514c | 3961 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3962 | } |
3963 | ||
f0947c37 DV |
3964 | /* Simple connector->get_hw_state implementation for encoders that support only |
3965 | * one connector and no cloning and hence the encoder state determines the state | |
3966 | * of the connector. */ | |
3967 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3968 | { |
24929352 | 3969 | enum pipe pipe = 0; |
f0947c37 | 3970 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3971 | |
f0947c37 | 3972 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3973 | } |
3974 | ||
1857e1da DV |
3975 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
3976 | struct intel_crtc_config *pipe_config) | |
3977 | { | |
3978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3979 | struct intel_crtc *pipe_B_crtc = | |
3980 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
3981 | ||
3982 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
3983 | pipe_name(pipe), pipe_config->fdi_lanes); | |
3984 | if (pipe_config->fdi_lanes > 4) { | |
3985 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
3986 | pipe_name(pipe), pipe_config->fdi_lanes); | |
3987 | return false; | |
3988 | } | |
3989 | ||
3990 | if (IS_HASWELL(dev)) { | |
3991 | if (pipe_config->fdi_lanes > 2) { | |
3992 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
3993 | pipe_config->fdi_lanes); | |
3994 | return false; | |
3995 | } else { | |
3996 | return true; | |
3997 | } | |
3998 | } | |
3999 | ||
4000 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4001 | return true; | |
4002 | ||
4003 | /* Ivybridge 3 pipe is really complicated */ | |
4004 | switch (pipe) { | |
4005 | case PIPE_A: | |
4006 | return true; | |
4007 | case PIPE_B: | |
4008 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4009 | pipe_config->fdi_lanes > 2) { | |
4010 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4011 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4012 | return false; | |
4013 | } | |
4014 | return true; | |
4015 | case PIPE_C: | |
1e833f40 | 4016 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4017 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4018 | if (pipe_config->fdi_lanes > 2) { | |
4019 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4020 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4021 | return false; | |
4022 | } | |
4023 | } else { | |
4024 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4025 | return false; | |
4026 | } | |
4027 | return true; | |
4028 | default: | |
4029 | BUG(); | |
4030 | } | |
4031 | } | |
4032 | ||
e29c22c0 DV |
4033 | #define RETRY 1 |
4034 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4035 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4036 | { |
1857e1da | 4037 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4038 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4039 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4040 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4041 | |
e29c22c0 | 4042 | retry: |
877d48d5 DV |
4043 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4044 | * each output octet as 10 bits. The actual frequency | |
4045 | * is stored as a divider into a 100MHz clock, and the | |
4046 | * mode pixel clock is stored in units of 1KHz. | |
4047 | * Hence the bw of each lane in terms of the mode signal | |
4048 | * is: | |
4049 | */ | |
4050 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4051 | ||
ff9a6750 | 4052 | fdi_dotclock = adjusted_mode->clock; |
ef1b460d | 4053 | fdi_dotclock /= pipe_config->pixel_multiplier; |
877d48d5 | 4054 | |
2bd89a07 | 4055 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4056 | pipe_config->pipe_bpp); |
4057 | ||
4058 | pipe_config->fdi_lanes = lane; | |
4059 | ||
2bd89a07 | 4060 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4061 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4062 | |
e29c22c0 DV |
4063 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4064 | intel_crtc->pipe, pipe_config); | |
4065 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4066 | pipe_config->pipe_bpp -= 2*3; | |
4067 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4068 | pipe_config->pipe_bpp); | |
4069 | needs_recompute = true; | |
4070 | pipe_config->bw_constrained = true; | |
4071 | ||
4072 | goto retry; | |
4073 | } | |
4074 | ||
4075 | if (needs_recompute) | |
4076 | return RETRY; | |
4077 | ||
4078 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4079 | } |
4080 | ||
42db64ef PZ |
4081 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4082 | struct intel_crtc_config *pipe_config) | |
4083 | { | |
3c4ca58c PZ |
4084 | pipe_config->ips_enabled = i915_enable_ips && |
4085 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4086 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4087 | } |
4088 | ||
a43f6e0f | 4089 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4090 | struct intel_crtc_config *pipe_config) |
79e53945 | 4091 | { |
a43f6e0f | 4092 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4093 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4094 | |
bad720ff | 4095 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 4096 | /* FDI link clock is fixed at 2.7G */ |
b8cecdf5 DV |
4097 | if (pipe_config->requested_mode.clock * 3 |
4098 | > IRONLAKE_FDI_FREQ * 4) | |
e29c22c0 | 4099 | return -EINVAL; |
2c07245f | 4100 | } |
89749350 | 4101 | |
8693a824 DL |
4102 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4103 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4104 | */ |
4105 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4106 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4107 | return -EINVAL; |
44f46b42 | 4108 | |
bd080ee5 | 4109 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4110 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4111 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4112 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4113 | * for lvds. */ | |
4114 | pipe_config->pipe_bpp = 8*3; | |
4115 | } | |
4116 | ||
f5adf94e | 4117 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4118 | hsw_compute_ips_config(crtc, pipe_config); |
4119 | ||
4120 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4121 | * clock survives for now. */ | |
4122 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4123 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4124 | |
877d48d5 | 4125 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4126 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4127 | |
e29c22c0 | 4128 | return 0; |
79e53945 JB |
4129 | } |
4130 | ||
25eb05fc JB |
4131 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4132 | { | |
4133 | return 400000; /* FIXME */ | |
4134 | } | |
4135 | ||
e70236a8 JB |
4136 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4137 | { | |
4138 | return 400000; | |
4139 | } | |
79e53945 | 4140 | |
e70236a8 | 4141 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4142 | { |
e70236a8 JB |
4143 | return 333000; |
4144 | } | |
79e53945 | 4145 | |
e70236a8 JB |
4146 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4147 | { | |
4148 | return 200000; | |
4149 | } | |
79e53945 | 4150 | |
257a7ffc DV |
4151 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4152 | { | |
4153 | u16 gcfgc = 0; | |
4154 | ||
4155 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4156 | ||
4157 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4158 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4159 | return 267000; | |
4160 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4161 | return 333000; | |
4162 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4163 | return 444000; | |
4164 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4165 | return 200000; | |
4166 | default: | |
4167 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4168 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4169 | return 133000; | |
4170 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4171 | return 167000; | |
4172 | } | |
4173 | } | |
4174 | ||
e70236a8 JB |
4175 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4176 | { | |
4177 | u16 gcfgc = 0; | |
79e53945 | 4178 | |
e70236a8 JB |
4179 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4180 | ||
4181 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4182 | return 133000; | |
4183 | else { | |
4184 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4185 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4186 | return 333000; | |
4187 | default: | |
4188 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4189 | return 190000; | |
79e53945 | 4190 | } |
e70236a8 JB |
4191 | } |
4192 | } | |
4193 | ||
4194 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4195 | { | |
4196 | return 266000; | |
4197 | } | |
4198 | ||
4199 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4200 | { | |
4201 | u16 hpllcc = 0; | |
4202 | /* Assume that the hardware is in the high speed state. This | |
4203 | * should be the default. | |
4204 | */ | |
4205 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4206 | case GC_CLOCK_133_200: | |
4207 | case GC_CLOCK_100_200: | |
4208 | return 200000; | |
4209 | case GC_CLOCK_166_250: | |
4210 | return 250000; | |
4211 | case GC_CLOCK_100_133: | |
79e53945 | 4212 | return 133000; |
e70236a8 | 4213 | } |
79e53945 | 4214 | |
e70236a8 JB |
4215 | /* Shouldn't happen */ |
4216 | return 0; | |
4217 | } | |
79e53945 | 4218 | |
e70236a8 JB |
4219 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4220 | { | |
4221 | return 133000; | |
79e53945 JB |
4222 | } |
4223 | ||
2c07245f | 4224 | static void |
a65851af | 4225 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4226 | { |
a65851af VS |
4227 | while (*num > DATA_LINK_M_N_MASK || |
4228 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4229 | *num >>= 1; |
4230 | *den >>= 1; | |
4231 | } | |
4232 | } | |
4233 | ||
a65851af VS |
4234 | static void compute_m_n(unsigned int m, unsigned int n, |
4235 | uint32_t *ret_m, uint32_t *ret_n) | |
4236 | { | |
4237 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4238 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4239 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4240 | } | |
4241 | ||
e69d0bc1 DV |
4242 | void |
4243 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4244 | int pixel_clock, int link_clock, | |
4245 | struct intel_link_m_n *m_n) | |
2c07245f | 4246 | { |
e69d0bc1 | 4247 | m_n->tu = 64; |
a65851af VS |
4248 | |
4249 | compute_m_n(bits_per_pixel * pixel_clock, | |
4250 | link_clock * nlanes * 8, | |
4251 | &m_n->gmch_m, &m_n->gmch_n); | |
4252 | ||
4253 | compute_m_n(pixel_clock, link_clock, | |
4254 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4255 | } |
4256 | ||
a7615030 CW |
4257 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4258 | { | |
72bbe58c KP |
4259 | if (i915_panel_use_ssc >= 0) |
4260 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4261 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4262 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4263 | } |
4264 | ||
a0c4da24 JB |
4265 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4266 | { | |
4267 | struct drm_device *dev = crtc->dev; | |
4268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4269 | int refclk = 27000; /* for DP & HDMI */ | |
4270 | ||
4271 | return 100000; /* only one validated so far */ | |
4272 | ||
4273 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4274 | refclk = 96000; | |
4275 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4276 | if (intel_panel_use_ssc(dev_priv)) | |
4277 | refclk = 100000; | |
4278 | else | |
4279 | refclk = 96000; | |
4280 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4281 | refclk = 100000; | |
4282 | } | |
4283 | ||
4284 | return refclk; | |
4285 | } | |
4286 | ||
c65d77d8 JB |
4287 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4288 | { | |
4289 | struct drm_device *dev = crtc->dev; | |
4290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4291 | int refclk; | |
4292 | ||
a0c4da24 JB |
4293 | if (IS_VALLEYVIEW(dev)) { |
4294 | refclk = vlv_get_refclk(crtc); | |
4295 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 | 4296 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4297 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4298 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4299 | refclk / 1000); | |
4300 | } else if (!IS_GEN2(dev)) { | |
4301 | refclk = 96000; | |
4302 | } else { | |
4303 | refclk = 48000; | |
4304 | } | |
4305 | ||
4306 | return refclk; | |
4307 | } | |
4308 | ||
7429e9d4 | 4309 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4310 | { |
7df00d7a | 4311 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4312 | } |
f47709a9 | 4313 | |
7429e9d4 DV |
4314 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4315 | { | |
4316 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4317 | } |
4318 | ||
f47709a9 | 4319 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4320 | intel_clock_t *reduced_clock) |
4321 | { | |
f47709a9 | 4322 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4323 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4324 | int pipe = crtc->pipe; |
a7516a05 JB |
4325 | u32 fp, fp2 = 0; |
4326 | ||
4327 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4328 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4329 | if (reduced_clock) |
7429e9d4 | 4330 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4331 | } else { |
7429e9d4 | 4332 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4333 | if (reduced_clock) |
7429e9d4 | 4334 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4335 | } |
4336 | ||
4337 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4338 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4339 | |
f47709a9 DV |
4340 | crtc->lowfreq_avail = false; |
4341 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4342 | reduced_clock && i915_powersave) { |
4343 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4344 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4345 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4346 | } else { |
4347 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4348 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4349 | } |
4350 | } | |
4351 | ||
89b667f8 JB |
4352 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4353 | { | |
4354 | u32 reg_val; | |
4355 | ||
4356 | /* | |
4357 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4358 | * and set it to a reasonable value instead. | |
4359 | */ | |
ae99258f | 4360 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
89b667f8 JB |
4361 | reg_val &= 0xffffff00; |
4362 | reg_val |= 0x00000030; | |
ae99258f | 4363 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
89b667f8 | 4364 | |
ae99258f | 4365 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
89b667f8 JB |
4366 | reg_val &= 0x8cffffff; |
4367 | reg_val = 0x8c000000; | |
ae99258f | 4368 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
89b667f8 | 4369 | |
ae99258f | 4370 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1)); |
89b667f8 | 4371 | reg_val &= 0xffffff00; |
ae99258f | 4372 | vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val); |
89b667f8 | 4373 | |
ae99258f | 4374 | reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION); |
89b667f8 JB |
4375 | reg_val &= 0x00ffffff; |
4376 | reg_val |= 0xb0000000; | |
ae99258f | 4377 | vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); |
89b667f8 JB |
4378 | } |
4379 | ||
b551842d DV |
4380 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4381 | struct intel_link_m_n *m_n) | |
4382 | { | |
4383 | struct drm_device *dev = crtc->base.dev; | |
4384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4385 | int pipe = crtc->pipe; | |
4386 | ||
e3b95f1e DV |
4387 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4388 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4389 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4390 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4391 | } |
4392 | ||
4393 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4394 | struct intel_link_m_n *m_n) | |
4395 | { | |
4396 | struct drm_device *dev = crtc->base.dev; | |
4397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4398 | int pipe = crtc->pipe; | |
4399 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4400 | ||
4401 | if (INTEL_INFO(dev)->gen >= 5) { | |
4402 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4403 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4404 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4405 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4406 | } else { | |
e3b95f1e DV |
4407 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4408 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4409 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4410 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4411 | } |
4412 | } | |
4413 | ||
03afc4a2 DV |
4414 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4415 | { | |
4416 | if (crtc->config.has_pch_encoder) | |
4417 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4418 | else | |
4419 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4420 | } | |
4421 | ||
f47709a9 | 4422 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4423 | { |
f47709a9 | 4424 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4425 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4426 | int pipe = crtc->pipe; |
89b667f8 | 4427 | u32 dpll, mdiv; |
a0c4da24 | 4428 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4429 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4430 | |
09153000 DV |
4431 | mutex_lock(&dev_priv->dpio_lock); |
4432 | ||
f47709a9 DV |
4433 | bestn = crtc->config.dpll.n; |
4434 | bestm1 = crtc->config.dpll.m1; | |
4435 | bestm2 = crtc->config.dpll.m2; | |
4436 | bestp1 = crtc->config.dpll.p1; | |
4437 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4438 | |
89b667f8 JB |
4439 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4440 | ||
4441 | /* PLL B needs special handling */ | |
4442 | if (pipe) | |
4443 | vlv_pllb_recal_opamp(dev_priv); | |
4444 | ||
4445 | /* Set up Tx target for periodic Rcomp update */ | |
ae99258f | 4446 | vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); |
89b667f8 JB |
4447 | |
4448 | /* Disable target IRef on PLL */ | |
ae99258f | 4449 | reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); |
89b667f8 | 4450 | reg_val &= 0x00ffffff; |
ae99258f | 4451 | vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); |
89b667f8 JB |
4452 | |
4453 | /* Disable fast lock */ | |
ae99258f | 4454 | vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); |
89b667f8 JB |
4455 | |
4456 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4457 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4458 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4459 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4460 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4461 | |
4462 | /* | |
4463 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4464 | * but we don't support that). | |
4465 | * Note: don't use the DAC post divider as it seems unstable. | |
4466 | */ | |
4467 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ae99258f | 4468 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4469 | |
a0c4da24 | 4470 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ae99258f | 4471 | vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4472 | |
89b667f8 | 4473 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4474 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4475 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4476 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
4abb2c39 | 4477 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
885b0120 | 4478 | 0x009f0003); |
89b667f8 | 4479 | else |
4abb2c39 | 4480 | vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), |
89b667f8 JB |
4481 | 0x00d0000f); |
4482 | ||
4483 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4484 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4485 | /* Use SSC source */ | |
4486 | if (!pipe) | |
ae99258f | 4487 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
89b667f8 JB |
4488 | 0x0df40000); |
4489 | else | |
ae99258f | 4490 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
89b667f8 JB |
4491 | 0x0df70000); |
4492 | } else { /* HDMI or VGA */ | |
4493 | /* Use bend source */ | |
4494 | if (!pipe) | |
ae99258f | 4495 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
89b667f8 JB |
4496 | 0x0df70000); |
4497 | else | |
ae99258f | 4498 | vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe), |
89b667f8 JB |
4499 | 0x0df40000); |
4500 | } | |
a0c4da24 | 4501 | |
ae99258f | 4502 | coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
89b667f8 JB |
4503 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4504 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4505 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4506 | coreclk |= 0x01000000; | |
ae99258f | 4507 | vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); |
a0c4da24 | 4508 | |
ae99258f | 4509 | vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
a0c4da24 | 4510 | |
89b667f8 JB |
4511 | /* Enable DPIO clock input */ |
4512 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4513 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
4514 | if (pipe) | |
4515 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
a0c4da24 JB |
4516 | |
4517 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
4518 | crtc->config.dpll_hw_state.dpll = dpll; |
4519 | ||
ef1b460d DV |
4520 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4521 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4522 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4523 | ||
89b667f8 JB |
4524 | if (crtc->config.has_dp_encoder) |
4525 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4526 | |
4527 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4528 | } |
4529 | ||
f47709a9 DV |
4530 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4531 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4532 | int num_connectors) |
4533 | { | |
f47709a9 | 4534 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4535 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
4536 | u32 dpll; |
4537 | bool is_sdvo; | |
f47709a9 | 4538 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4539 | |
f47709a9 | 4540 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4541 | |
f47709a9 DV |
4542 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4543 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4544 | |
4545 | dpll = DPLL_VGA_MODE_DIS; | |
4546 | ||
f47709a9 | 4547 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
4548 | dpll |= DPLLB_MODE_LVDS; |
4549 | else | |
4550 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 4551 | |
ef1b460d | 4552 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
4553 | dpll |= (crtc->config.pixel_multiplier - 1) |
4554 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 4555 | } |
198a037f DV |
4556 | |
4557 | if (is_sdvo) | |
4a33e48d | 4558 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 4559 | |
f47709a9 | 4560 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 4561 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
4562 | |
4563 | /* compute bitmask from p1 value */ | |
4564 | if (IS_PINEVIEW(dev)) | |
4565 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4566 | else { | |
4567 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4568 | if (IS_G4X(dev) && reduced_clock) | |
4569 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4570 | } | |
4571 | switch (clock->p2) { | |
4572 | case 5: | |
4573 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4574 | break; | |
4575 | case 7: | |
4576 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4577 | break; | |
4578 | case 10: | |
4579 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4580 | break; | |
4581 | case 14: | |
4582 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4583 | break; | |
4584 | } | |
4585 | if (INTEL_INFO(dev)->gen >= 4) | |
4586 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4587 | ||
09ede541 | 4588 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 4589 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 4590 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4591 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4592 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4593 | else | |
4594 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4595 | ||
4596 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
4597 | crtc->config.dpll_hw_state.dpll = dpll; |
4598 | ||
eb1cbe48 | 4599 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
4600 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4601 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 4602 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 4603 | } |
66e3d5c0 DV |
4604 | |
4605 | if (crtc->config.has_dp_encoder) | |
4606 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
4607 | } |
4608 | ||
f47709a9 | 4609 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 4610 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4611 | int num_connectors) |
4612 | { | |
f47709a9 | 4613 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4614 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 4615 | u32 dpll; |
f47709a9 | 4616 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4617 | |
f47709a9 | 4618 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4619 | |
eb1cbe48 DV |
4620 | dpll = DPLL_VGA_MODE_DIS; |
4621 | ||
f47709a9 | 4622 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
4623 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4624 | } else { | |
4625 | if (clock->p1 == 2) | |
4626 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4627 | else | |
4628 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4629 | if (clock->p2 == 4) | |
4630 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4631 | } | |
4632 | ||
4a33e48d DV |
4633 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4634 | dpll |= DPLL_DVO_2X_MODE; | |
4635 | ||
f47709a9 | 4636 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4637 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4638 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4639 | else | |
4640 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4641 | ||
4642 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 4643 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
4644 | } |
4645 | ||
8a654f3b | 4646 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
4647 | { |
4648 | struct drm_device *dev = intel_crtc->base.dev; | |
4649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4650 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 4651 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
4652 | struct drm_display_mode *adjusted_mode = |
4653 | &intel_crtc->config.adjusted_mode; | |
4654 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
4d8a62ea DV |
4655 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4656 | ||
4657 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
4658 | * the hw state checker will get angry at the mismatch. */ | |
4659 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
4660 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
4661 | |
4662 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4663 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
4664 | crtc_vtotal -= 1; |
4665 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
4666 | vsyncshift = adjusted_mode->crtc_hsync_start |
4667 | - adjusted_mode->crtc_htotal / 2; | |
4668 | } else { | |
4669 | vsyncshift = 0; | |
4670 | } | |
4671 | ||
4672 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4673 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4674 | |
fe2b8f9d | 4675 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4676 | (adjusted_mode->crtc_hdisplay - 1) | |
4677 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4678 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4679 | (adjusted_mode->crtc_hblank_start - 1) | |
4680 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4681 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4682 | (adjusted_mode->crtc_hsync_start - 1) | |
4683 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4684 | ||
fe2b8f9d | 4685 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 4686 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 4687 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 4688 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 4689 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 4690 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 4691 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4692 | (adjusted_mode->crtc_vsync_start - 1) | |
4693 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4694 | ||
b5e508d4 PZ |
4695 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4696 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4697 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4698 | * bits. */ | |
4699 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4700 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4701 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4702 | ||
b0e77b9c PZ |
4703 | /* pipesrc controls the size that is scaled from, which should |
4704 | * always be the user's requested size. | |
4705 | */ | |
4706 | I915_WRITE(PIPESRC(pipe), | |
4707 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4708 | } | |
4709 | ||
1bd1bd80 DV |
4710 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4711 | struct intel_crtc_config *pipe_config) | |
4712 | { | |
4713 | struct drm_device *dev = crtc->base.dev; | |
4714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4715 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
4716 | uint32_t tmp; | |
4717 | ||
4718 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
4719 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
4720 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
4721 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
4722 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
4723 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4724 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
4725 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
4726 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4727 | ||
4728 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
4729 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
4730 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
4731 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
4732 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
4733 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4734 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
4735 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
4736 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4737 | ||
4738 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
4739 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
4740 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
4741 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
4742 | } | |
4743 | ||
4744 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
4745 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; | |
4746 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; | |
4747 | } | |
4748 | ||
babea61d JB |
4749 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4750 | struct intel_crtc_config *pipe_config) | |
4751 | { | |
4752 | struct drm_crtc *crtc = &intel_crtc->base; | |
4753 | ||
4754 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
4755 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
4756 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
4757 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
4758 | ||
4759 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
4760 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
4761 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
4762 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
4763 | ||
4764 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
4765 | ||
4766 | crtc->mode.clock = pipe_config->adjusted_mode.clock; | |
4767 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; | |
4768 | } | |
4769 | ||
84b046f3 DV |
4770 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4771 | { | |
4772 | struct drm_device *dev = intel_crtc->base.dev; | |
4773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4774 | uint32_t pipeconf; | |
4775 | ||
9f11a9e4 | 4776 | pipeconf = 0; |
84b046f3 DV |
4777 | |
4778 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { | |
4779 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
4780 | * core speed. | |
4781 | * | |
4782 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4783 | * pipe == 0 check? | |
4784 | */ | |
4785 | if (intel_crtc->config.requested_mode.clock > | |
4786 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
4787 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 DV |
4788 | } |
4789 | ||
ff9ce46e DV |
4790 | /* only g4x and later have fancy bpc/dither controls */ |
4791 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
4792 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4793 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
4794 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 4795 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 4796 | |
ff9ce46e DV |
4797 | switch (intel_crtc->config.pipe_bpp) { |
4798 | case 18: | |
4799 | pipeconf |= PIPECONF_6BPC; | |
4800 | break; | |
4801 | case 24: | |
4802 | pipeconf |= PIPECONF_8BPC; | |
4803 | break; | |
4804 | case 30: | |
4805 | pipeconf |= PIPECONF_10BPC; | |
4806 | break; | |
4807 | default: | |
4808 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
4809 | BUG(); | |
84b046f3 DV |
4810 | } |
4811 | } | |
4812 | ||
4813 | if (HAS_PIPE_CXSR(dev)) { | |
4814 | if (intel_crtc->lowfreq_avail) { | |
4815 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4816 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4817 | } else { | |
4818 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
4819 | } |
4820 | } | |
4821 | ||
84b046f3 DV |
4822 | if (!IS_GEN2(dev) && |
4823 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
4824 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4825 | else | |
4826 | pipeconf |= PIPECONF_PROGRESSIVE; | |
4827 | ||
9f11a9e4 DV |
4828 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4829 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 4830 | |
84b046f3 DV |
4831 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4832 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
4833 | } | |
4834 | ||
f564048e | 4835 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 4836 | int x, int y, |
94352cf9 | 4837 | struct drm_framebuffer *fb) |
79e53945 JB |
4838 | { |
4839 | struct drm_device *dev = crtc->dev; | |
4840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 | 4842 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
79e53945 | 4843 | int pipe = intel_crtc->pipe; |
80824003 | 4844 | int plane = intel_crtc->plane; |
c751ce4f | 4845 | int refclk, num_connectors = 0; |
652c393a | 4846 | intel_clock_t clock, reduced_clock; |
84b046f3 | 4847 | u32 dspcntr; |
a16af721 DV |
4848 | bool ok, has_reduced_clock = false; |
4849 | bool is_lvds = false; | |
5eddb70b | 4850 | struct intel_encoder *encoder; |
d4906093 | 4851 | const intel_limit_t *limit; |
5c3b82e2 | 4852 | int ret; |
79e53945 | 4853 | |
6c2b7c12 | 4854 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4855 | switch (encoder->type) { |
79e53945 JB |
4856 | case INTEL_OUTPUT_LVDS: |
4857 | is_lvds = true; | |
4858 | break; | |
79e53945 | 4859 | } |
43565a06 | 4860 | |
c751ce4f | 4861 | num_connectors++; |
79e53945 JB |
4862 | } |
4863 | ||
c65d77d8 | 4864 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4865 | |
d4906093 ML |
4866 | /* |
4867 | * Returns a set of divisors for the desired target clock with the given | |
4868 | * refclk, or FALSE. The returned values represent the clock equation: | |
4869 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4870 | */ | |
1b894b59 | 4871 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
4872 | ok = dev_priv->display.find_dpll(limit, crtc, |
4873 | intel_crtc->config.port_clock, | |
ee9300bb DV |
4874 | refclk, NULL, &clock); |
4875 | if (!ok && !intel_crtc->config.clock_set) { | |
79e53945 | 4876 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5c3b82e2 | 4877 | return -EINVAL; |
79e53945 JB |
4878 | } |
4879 | ||
ddc9003c | 4880 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4881 | /* |
4882 | * Ensure we match the reduced clock's P to the target clock. | |
4883 | * If the clocks don't match, we can't switch the display clock | |
4884 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4885 | * downclock feature. | |
4886 | */ | |
ee9300bb DV |
4887 | has_reduced_clock = |
4888 | dev_priv->display.find_dpll(limit, crtc, | |
5eddb70b | 4889 | dev_priv->lvds_downclock, |
ee9300bb | 4890 | refclk, &clock, |
5eddb70b | 4891 | &reduced_clock); |
7026d4ac | 4892 | } |
f47709a9 DV |
4893 | /* Compat-code for transition, will disappear. */ |
4894 | if (!intel_crtc->config.clock_set) { | |
4895 | intel_crtc->config.dpll.n = clock.n; | |
4896 | intel_crtc->config.dpll.m1 = clock.m1; | |
4897 | intel_crtc->config.dpll.m2 = clock.m2; | |
4898 | intel_crtc->config.dpll.p1 = clock.p1; | |
4899 | intel_crtc->config.dpll.p2 = clock.p2; | |
4900 | } | |
7026d4ac | 4901 | |
eb1cbe48 | 4902 | if (IS_GEN2(dev)) |
8a654f3b | 4903 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
4904 | has_reduced_clock ? &reduced_clock : NULL, |
4905 | num_connectors); | |
a0c4da24 | 4906 | else if (IS_VALLEYVIEW(dev)) |
f47709a9 | 4907 | vlv_update_pll(intel_crtc); |
79e53945 | 4908 | else |
f47709a9 | 4909 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 4910 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 4911 | num_connectors); |
79e53945 | 4912 | |
79e53945 JB |
4913 | /* Set up the display plane register */ |
4914 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4915 | ||
da6ecc5d JB |
4916 | if (!IS_VALLEYVIEW(dev)) { |
4917 | if (pipe == 0) | |
4918 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4919 | else | |
4920 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4921 | } | |
79e53945 | 4922 | |
8a654f3b | 4923 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
4924 | |
4925 | /* pipesrc and dspsize control the size that is scaled from, | |
4926 | * which should always be the user's requested size. | |
79e53945 | 4927 | */ |
929c77fb EA |
4928 | I915_WRITE(DSPSIZE(plane), |
4929 | ((mode->vdisplay - 1) << 16) | | |
4930 | (mode->hdisplay - 1)); | |
4931 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4932 | |
84b046f3 DV |
4933 | i9xx_set_pipeconf(intel_crtc); |
4934 | ||
f564048e EA |
4935 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4936 | POSTING_READ(DSPCNTR(plane)); | |
4937 | ||
94352cf9 | 4938 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4939 | |
4940 | intel_update_watermarks(dev); | |
4941 | ||
f564048e EA |
4942 | return ret; |
4943 | } | |
4944 | ||
2fa2fe9a DV |
4945 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
4946 | struct intel_crtc_config *pipe_config) | |
4947 | { | |
4948 | struct drm_device *dev = crtc->base.dev; | |
4949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4950 | uint32_t tmp; | |
4951 | ||
4952 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
4953 | if (!(tmp & PFIT_ENABLE)) |
4954 | return; | |
2fa2fe9a | 4955 | |
06922821 | 4956 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
4957 | if (INTEL_INFO(dev)->gen < 4) { |
4958 | if (crtc->pipe != PIPE_B) | |
4959 | return; | |
2fa2fe9a DV |
4960 | } else { |
4961 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
4962 | return; | |
4963 | } | |
4964 | ||
06922821 | 4965 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
4966 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
4967 | if (INTEL_INFO(dev)->gen < 5) | |
4968 | pipe_config->gmch_pfit.lvds_border_bits = | |
4969 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
4970 | } | |
4971 | ||
0e8ffe1b DV |
4972 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
4973 | struct intel_crtc_config *pipe_config) | |
4974 | { | |
4975 | struct drm_device *dev = crtc->base.dev; | |
4976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4977 | uint32_t tmp; | |
4978 | ||
e143a21c | 4979 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 4980 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 4981 | |
0e8ffe1b DV |
4982 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
4983 | if (!(tmp & PIPECONF_ENABLE)) | |
4984 | return false; | |
4985 | ||
1bd1bd80 DV |
4986 | intel_get_pipe_timings(crtc, pipe_config); |
4987 | ||
2fa2fe9a DV |
4988 | i9xx_get_pfit_config(crtc, pipe_config); |
4989 | ||
6c49f241 DV |
4990 | if (INTEL_INFO(dev)->gen >= 4) { |
4991 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
4992 | pipe_config->pixel_multiplier = | |
4993 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
4994 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 4995 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
4996 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
4997 | tmp = I915_READ(DPLL(crtc->pipe)); | |
4998 | pipe_config->pixel_multiplier = | |
4999 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5000 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5001 | } else { | |
5002 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5003 | * port and will be fixed up in the encoder->get_config | |
5004 | * function. */ | |
5005 | pipe_config->pixel_multiplier = 1; | |
5006 | } | |
8bcc2795 DV |
5007 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5008 | if (!IS_VALLEYVIEW(dev)) { | |
5009 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5010 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5011 | } else { |
5012 | /* Mask out read-only status bits. */ | |
5013 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5014 | DPLL_PORTC_READY_MASK | | |
5015 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5016 | } |
6c49f241 | 5017 | |
0e8ffe1b DV |
5018 | return true; |
5019 | } | |
5020 | ||
dde86e2d | 5021 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5022 | { |
5023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5024 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5025 | struct intel_encoder *encoder; |
74cfd7ac | 5026 | u32 val, final; |
13d83a67 | 5027 | bool has_lvds = false; |
199e5d79 | 5028 | bool has_cpu_edp = false; |
199e5d79 | 5029 | bool has_panel = false; |
99eb6a01 KP |
5030 | bool has_ck505 = false; |
5031 | bool can_ssc = false; | |
13d83a67 JB |
5032 | |
5033 | /* We need to take the global config into account */ | |
199e5d79 KP |
5034 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5035 | base.head) { | |
5036 | switch (encoder->type) { | |
5037 | case INTEL_OUTPUT_LVDS: | |
5038 | has_panel = true; | |
5039 | has_lvds = true; | |
5040 | break; | |
5041 | case INTEL_OUTPUT_EDP: | |
5042 | has_panel = true; | |
2de6905f | 5043 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5044 | has_cpu_edp = true; |
5045 | break; | |
13d83a67 JB |
5046 | } |
5047 | } | |
5048 | ||
99eb6a01 | 5049 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5050 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5051 | can_ssc = has_ck505; |
5052 | } else { | |
5053 | has_ck505 = false; | |
5054 | can_ssc = true; | |
5055 | } | |
5056 | ||
2de6905f ID |
5057 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5058 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5059 | |
5060 | /* Ironlake: try to setup display ref clock before DPLL | |
5061 | * enabling. This is only under driver's control after | |
5062 | * PCH B stepping, previous chipset stepping should be | |
5063 | * ignoring this setting. | |
5064 | */ | |
74cfd7ac CW |
5065 | val = I915_READ(PCH_DREF_CONTROL); |
5066 | ||
5067 | /* As we must carefully and slowly disable/enable each source in turn, | |
5068 | * compute the final state we want first and check if we need to | |
5069 | * make any changes at all. | |
5070 | */ | |
5071 | final = val; | |
5072 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5073 | if (has_ck505) | |
5074 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5075 | else | |
5076 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5077 | ||
5078 | final &= ~DREF_SSC_SOURCE_MASK; | |
5079 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5080 | final &= ~DREF_SSC1_ENABLE; | |
5081 | ||
5082 | if (has_panel) { | |
5083 | final |= DREF_SSC_SOURCE_ENABLE; | |
5084 | ||
5085 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5086 | final |= DREF_SSC1_ENABLE; | |
5087 | ||
5088 | if (has_cpu_edp) { | |
5089 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5090 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5091 | else | |
5092 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5093 | } else | |
5094 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5095 | } else { | |
5096 | final |= DREF_SSC_SOURCE_DISABLE; | |
5097 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5098 | } | |
5099 | ||
5100 | if (final == val) | |
5101 | return; | |
5102 | ||
13d83a67 | 5103 | /* Always enable nonspread source */ |
74cfd7ac | 5104 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5105 | |
99eb6a01 | 5106 | if (has_ck505) |
74cfd7ac | 5107 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5108 | else |
74cfd7ac | 5109 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5110 | |
199e5d79 | 5111 | if (has_panel) { |
74cfd7ac CW |
5112 | val &= ~DREF_SSC_SOURCE_MASK; |
5113 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5114 | |
199e5d79 | 5115 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5116 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5117 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5118 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5119 | } else |
74cfd7ac | 5120 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5121 | |
5122 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5123 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5124 | POSTING_READ(PCH_DREF_CONTROL); |
5125 | udelay(200); | |
5126 | ||
74cfd7ac | 5127 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5128 | |
5129 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5130 | if (has_cpu_edp) { |
99eb6a01 | 5131 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5132 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5133 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5134 | } |
13d83a67 | 5135 | else |
74cfd7ac | 5136 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5137 | } else |
74cfd7ac | 5138 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5139 | |
74cfd7ac | 5140 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5141 | POSTING_READ(PCH_DREF_CONTROL); |
5142 | udelay(200); | |
5143 | } else { | |
5144 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5145 | ||
74cfd7ac | 5146 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5147 | |
5148 | /* Turn off CPU output */ | |
74cfd7ac | 5149 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5150 | |
74cfd7ac | 5151 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5152 | POSTING_READ(PCH_DREF_CONTROL); |
5153 | udelay(200); | |
5154 | ||
5155 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5156 | val &= ~DREF_SSC_SOURCE_MASK; |
5157 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5158 | |
5159 | /* Turn off SSC1 */ | |
74cfd7ac | 5160 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5161 | |
74cfd7ac | 5162 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5163 | POSTING_READ(PCH_DREF_CONTROL); |
5164 | udelay(200); | |
5165 | } | |
74cfd7ac CW |
5166 | |
5167 | BUG_ON(val != final); | |
13d83a67 JB |
5168 | } |
5169 | ||
f31f2d55 | 5170 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5171 | { |
f31f2d55 | 5172 | uint32_t tmp; |
dde86e2d | 5173 | |
0ff066a9 PZ |
5174 | tmp = I915_READ(SOUTH_CHICKEN2); |
5175 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5176 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5177 | |
0ff066a9 PZ |
5178 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5179 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5180 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5181 | |
0ff066a9 PZ |
5182 | tmp = I915_READ(SOUTH_CHICKEN2); |
5183 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5184 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5185 | |
0ff066a9 PZ |
5186 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5187 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5188 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5189 | } |
5190 | ||
5191 | /* WaMPhyProgramming:hsw */ | |
5192 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5193 | { | |
5194 | uint32_t tmp; | |
dde86e2d PZ |
5195 | |
5196 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5197 | tmp &= ~(0xFF << 24); | |
5198 | tmp |= (0x12 << 24); | |
5199 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5200 | ||
dde86e2d PZ |
5201 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5202 | tmp |= (1 << 11); | |
5203 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5204 | ||
5205 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5206 | tmp |= (1 << 11); | |
5207 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5208 | ||
dde86e2d PZ |
5209 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5210 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5211 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5212 | ||
5213 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5214 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5215 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5216 | ||
0ff066a9 PZ |
5217 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5218 | tmp &= ~(7 << 13); | |
5219 | tmp |= (5 << 13); | |
5220 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5221 | |
0ff066a9 PZ |
5222 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5223 | tmp &= ~(7 << 13); | |
5224 | tmp |= (5 << 13); | |
5225 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5226 | |
5227 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5228 | tmp &= ~0xFF; | |
5229 | tmp |= 0x1C; | |
5230 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5231 | ||
5232 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5233 | tmp &= ~0xFF; | |
5234 | tmp |= 0x1C; | |
5235 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5236 | ||
5237 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5238 | tmp &= ~(0xFF << 16); | |
5239 | tmp |= (0x1C << 16); | |
5240 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5241 | ||
5242 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5243 | tmp &= ~(0xFF << 16); | |
5244 | tmp |= (0x1C << 16); | |
5245 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5246 | ||
0ff066a9 PZ |
5247 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5248 | tmp |= (1 << 27); | |
5249 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5250 | |
0ff066a9 PZ |
5251 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5252 | tmp |= (1 << 27); | |
5253 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5254 | |
0ff066a9 PZ |
5255 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5256 | tmp &= ~(0xF << 28); | |
5257 | tmp |= (4 << 28); | |
5258 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5259 | |
0ff066a9 PZ |
5260 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5261 | tmp &= ~(0xF << 28); | |
5262 | tmp |= (4 << 28); | |
5263 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5264 | } |
5265 | ||
2fa86a1f PZ |
5266 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5267 | * Programming" based on the parameters passed: | |
5268 | * - Sequence to enable CLKOUT_DP | |
5269 | * - Sequence to enable CLKOUT_DP without spread | |
5270 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5271 | */ | |
5272 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5273 | bool with_fdi) | |
f31f2d55 PZ |
5274 | { |
5275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5276 | uint32_t reg, tmp; |
5277 | ||
5278 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5279 | with_spread = true; | |
5280 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5281 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5282 | with_fdi = false; | |
f31f2d55 PZ |
5283 | |
5284 | mutex_lock(&dev_priv->dpio_lock); | |
5285 | ||
5286 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5287 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5288 | tmp |= SBI_SSCCTL_PATHALT; | |
5289 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5290 | ||
5291 | udelay(24); | |
5292 | ||
2fa86a1f PZ |
5293 | if (with_spread) { |
5294 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5295 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5296 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5297 | |
2fa86a1f PZ |
5298 | if (with_fdi) { |
5299 | lpt_reset_fdi_mphy(dev_priv); | |
5300 | lpt_program_fdi_mphy(dev_priv); | |
5301 | } | |
5302 | } | |
dde86e2d | 5303 | |
2fa86a1f PZ |
5304 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5305 | SBI_GEN0 : SBI_DBUFF0; | |
5306 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5307 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5308 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5309 | |
5310 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5311 | } |
5312 | ||
47701c3b PZ |
5313 | /* Sequence to disable CLKOUT_DP */ |
5314 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5315 | { | |
5316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5317 | uint32_t reg, tmp; | |
5318 | ||
5319 | mutex_lock(&dev_priv->dpio_lock); | |
5320 | ||
5321 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5322 | SBI_GEN0 : SBI_DBUFF0; | |
5323 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5324 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5325 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5326 | ||
5327 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5328 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5329 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5330 | tmp |= SBI_SSCCTL_PATHALT; | |
5331 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5332 | udelay(32); | |
5333 | } | |
5334 | tmp |= SBI_SSCCTL_DISABLE; | |
5335 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5336 | } | |
5337 | ||
5338 | mutex_unlock(&dev_priv->dpio_lock); | |
5339 | } | |
5340 | ||
bf8fa3d3 PZ |
5341 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5342 | { | |
5343 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5344 | struct intel_encoder *encoder; | |
5345 | bool has_vga = false; | |
5346 | ||
5347 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5348 | switch (encoder->type) { | |
5349 | case INTEL_OUTPUT_ANALOG: | |
5350 | has_vga = true; | |
5351 | break; | |
5352 | } | |
5353 | } | |
5354 | ||
47701c3b PZ |
5355 | if (has_vga) |
5356 | lpt_enable_clkout_dp(dev, true, true); | |
5357 | else | |
5358 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5359 | } |
5360 | ||
dde86e2d PZ |
5361 | /* |
5362 | * Initialize reference clocks when the driver loads | |
5363 | */ | |
5364 | void intel_init_pch_refclk(struct drm_device *dev) | |
5365 | { | |
5366 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5367 | ironlake_init_pch_refclk(dev); | |
5368 | else if (HAS_PCH_LPT(dev)) | |
5369 | lpt_init_pch_refclk(dev); | |
5370 | } | |
5371 | ||
d9d444cb JB |
5372 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5373 | { | |
5374 | struct drm_device *dev = crtc->dev; | |
5375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5376 | struct intel_encoder *encoder; | |
d9d444cb JB |
5377 | int num_connectors = 0; |
5378 | bool is_lvds = false; | |
5379 | ||
6c2b7c12 | 5380 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5381 | switch (encoder->type) { |
5382 | case INTEL_OUTPUT_LVDS: | |
5383 | is_lvds = true; | |
5384 | break; | |
d9d444cb JB |
5385 | } |
5386 | num_connectors++; | |
5387 | } | |
5388 | ||
5389 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5390 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5391 | dev_priv->vbt.lvds_ssc_freq); |
5392 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5393 | } |
5394 | ||
5395 | return 120000; | |
5396 | } | |
5397 | ||
6ff93609 | 5398 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5399 | { |
c8203565 | 5400 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5402 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5403 | uint32_t val; |
5404 | ||
78114071 | 5405 | val = 0; |
c8203565 | 5406 | |
965e0c48 | 5407 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5408 | case 18: |
dfd07d72 | 5409 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5410 | break; |
5411 | case 24: | |
dfd07d72 | 5412 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5413 | break; |
5414 | case 30: | |
dfd07d72 | 5415 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5416 | break; |
5417 | case 36: | |
dfd07d72 | 5418 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5419 | break; |
5420 | default: | |
cc769b62 PZ |
5421 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5422 | BUG(); | |
c8203565 PZ |
5423 | } |
5424 | ||
d8b32247 | 5425 | if (intel_crtc->config.dither) |
c8203565 PZ |
5426 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5427 | ||
6ff93609 | 5428 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5429 | val |= PIPECONF_INTERLACED_ILK; |
5430 | else | |
5431 | val |= PIPECONF_PROGRESSIVE; | |
5432 | ||
50f3b016 | 5433 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5434 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5435 | |
c8203565 PZ |
5436 | I915_WRITE(PIPECONF(pipe), val); |
5437 | POSTING_READ(PIPECONF(pipe)); | |
5438 | } | |
5439 | ||
86d3efce VS |
5440 | /* |
5441 | * Set up the pipe CSC unit. | |
5442 | * | |
5443 | * Currently only full range RGB to limited range RGB conversion | |
5444 | * is supported, but eventually this should handle various | |
5445 | * RGB<->YCbCr scenarios as well. | |
5446 | */ | |
50f3b016 | 5447 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5448 | { |
5449 | struct drm_device *dev = crtc->dev; | |
5450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5451 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5452 | int pipe = intel_crtc->pipe; | |
5453 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5454 | ||
5455 | /* | |
5456 | * TODO: Check what kind of values actually come out of the pipe | |
5457 | * with these coeff/postoff values and adjust to get the best | |
5458 | * accuracy. Perhaps we even need to take the bpc value into | |
5459 | * consideration. | |
5460 | */ | |
5461 | ||
50f3b016 | 5462 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5463 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5464 | ||
5465 | /* | |
5466 | * GY/GU and RY/RU should be the other way around according | |
5467 | * to BSpec, but reality doesn't agree. Just set them up in | |
5468 | * a way that results in the correct picture. | |
5469 | */ | |
5470 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5471 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5472 | ||
5473 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5474 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5475 | ||
5476 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5477 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5478 | ||
5479 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5480 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5481 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5482 | ||
5483 | if (INTEL_INFO(dev)->gen > 6) { | |
5484 | uint16_t postoff = 0; | |
5485 | ||
50f3b016 | 5486 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5487 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5488 | ||
5489 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5490 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5491 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5492 | ||
5493 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
5494 | } else { | |
5495 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
5496 | ||
50f3b016 | 5497 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5498 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5499 | ||
5500 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
5501 | } | |
5502 | } | |
5503 | ||
6ff93609 | 5504 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 PZ |
5505 | { |
5506 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 5508 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
5509 | uint32_t val; |
5510 | ||
3eff4faa | 5511 | val = 0; |
ee2b0b38 | 5512 | |
d8b32247 | 5513 | if (intel_crtc->config.dither) |
ee2b0b38 PZ |
5514 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5515 | ||
6ff93609 | 5516 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
5517 | val |= PIPECONF_INTERLACED_ILK; |
5518 | else | |
5519 | val |= PIPECONF_PROGRESSIVE; | |
5520 | ||
702e7a56 PZ |
5521 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5522 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
5523 | |
5524 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
5525 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
ee2b0b38 PZ |
5526 | } |
5527 | ||
6591c6e4 | 5528 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
5529 | intel_clock_t *clock, |
5530 | bool *has_reduced_clock, | |
5531 | intel_clock_t *reduced_clock) | |
5532 | { | |
5533 | struct drm_device *dev = crtc->dev; | |
5534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5535 | struct intel_encoder *intel_encoder; | |
5536 | int refclk; | |
d4906093 | 5537 | const intel_limit_t *limit; |
a16af721 | 5538 | bool ret, is_lvds = false; |
79e53945 | 5539 | |
6591c6e4 PZ |
5540 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5541 | switch (intel_encoder->type) { | |
79e53945 JB |
5542 | case INTEL_OUTPUT_LVDS: |
5543 | is_lvds = true; | |
5544 | break; | |
79e53945 JB |
5545 | } |
5546 | } | |
5547 | ||
d9d444cb | 5548 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5549 | |
d4906093 ML |
5550 | /* |
5551 | * Returns a set of divisors for the desired target clock with the given | |
5552 | * refclk, or FALSE. The returned values represent the clock equation: | |
5553 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5554 | */ | |
1b894b59 | 5555 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
5556 | ret = dev_priv->display.find_dpll(limit, crtc, |
5557 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 5558 | refclk, NULL, clock); |
6591c6e4 PZ |
5559 | if (!ret) |
5560 | return false; | |
cda4b7d3 | 5561 | |
ddc9003c | 5562 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5563 | /* |
5564 | * Ensure we match the reduced clock's P to the target clock. | |
5565 | * If the clocks don't match, we can't switch the display clock | |
5566 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5567 | * downclock feature. | |
5568 | */ | |
ee9300bb DV |
5569 | *has_reduced_clock = |
5570 | dev_priv->display.find_dpll(limit, crtc, | |
5571 | dev_priv->lvds_downclock, | |
5572 | refclk, clock, | |
5573 | reduced_clock); | |
652c393a | 5574 | } |
61e9653f | 5575 | |
6591c6e4 PZ |
5576 | return true; |
5577 | } | |
5578 | ||
01a415fd DV |
5579 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5580 | { | |
5581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5582 | uint32_t temp; | |
5583 | ||
5584 | temp = I915_READ(SOUTH_CHICKEN1); | |
5585 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5586 | return; | |
5587 | ||
5588 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5589 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5590 | ||
5591 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5592 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5593 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5594 | POSTING_READ(SOUTH_CHICKEN1); | |
5595 | } | |
5596 | ||
ebfd86fd | 5597 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
01a415fd DV |
5598 | { |
5599 | struct drm_device *dev = intel_crtc->base.dev; | |
5600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01a415fd DV |
5601 | |
5602 | switch (intel_crtc->pipe) { | |
5603 | case PIPE_A: | |
ebfd86fd | 5604 | break; |
01a415fd | 5605 | case PIPE_B: |
ebfd86fd | 5606 | if (intel_crtc->config.fdi_lanes > 2) |
01a415fd DV |
5607 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
5608 | else | |
5609 | cpt_enable_fdi_bc_bifurcation(dev); | |
5610 | ||
ebfd86fd | 5611 | break; |
01a415fd | 5612 | case PIPE_C: |
01a415fd DV |
5613 | cpt_enable_fdi_bc_bifurcation(dev); |
5614 | ||
ebfd86fd | 5615 | break; |
01a415fd DV |
5616 | default: |
5617 | BUG(); | |
5618 | } | |
5619 | } | |
5620 | ||
d4b1931c PZ |
5621 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5622 | { | |
5623 | /* | |
5624 | * Account for spread spectrum to avoid | |
5625 | * oversubscribing the link. Max center spread | |
5626 | * is 2.5%; use 5% for safety's sake. | |
5627 | */ | |
5628 | u32 bps = target_clock * bpp * 21 / 20; | |
5629 | return bps / (link_bw * 8) + 1; | |
5630 | } | |
5631 | ||
7429e9d4 | 5632 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 5633 | { |
7429e9d4 | 5634 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
5635 | } |
5636 | ||
de13a2e3 | 5637 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 5638 | u32 *fp, |
9a7c7890 | 5639 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 5640 | { |
de13a2e3 | 5641 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5642 | struct drm_device *dev = crtc->dev; |
5643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5644 | struct intel_encoder *intel_encoder; |
5645 | uint32_t dpll; | |
6cc5f341 | 5646 | int factor, num_connectors = 0; |
09ede541 | 5647 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 5648 | |
de13a2e3 PZ |
5649 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5650 | switch (intel_encoder->type) { | |
79e53945 JB |
5651 | case INTEL_OUTPUT_LVDS: |
5652 | is_lvds = true; | |
5653 | break; | |
5654 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5655 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5656 | is_sdvo = true; |
79e53945 | 5657 | break; |
79e53945 | 5658 | } |
43565a06 | 5659 | |
c751ce4f | 5660 | num_connectors++; |
79e53945 | 5661 | } |
79e53945 | 5662 | |
c1858123 | 5663 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5664 | factor = 21; |
5665 | if (is_lvds) { | |
5666 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 5667 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 5668 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 5669 | factor = 25; |
09ede541 | 5670 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 5671 | factor = 20; |
c1858123 | 5672 | |
7429e9d4 | 5673 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 5674 | *fp |= FP_CB_TUNE; |
2c07245f | 5675 | |
9a7c7890 DV |
5676 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5677 | *fp2 |= FP_CB_TUNE; | |
5678 | ||
5eddb70b | 5679 | dpll = 0; |
2c07245f | 5680 | |
a07d6787 EA |
5681 | if (is_lvds) |
5682 | dpll |= DPLLB_MODE_LVDS; | |
5683 | else | |
5684 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 5685 | |
ef1b460d DV |
5686 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5687 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
5688 | |
5689 | if (is_sdvo) | |
4a33e48d | 5690 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 5691 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 5692 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 5693 | |
a07d6787 | 5694 | /* compute bitmask from p1 value */ |
7429e9d4 | 5695 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5696 | /* also FPA1 */ |
7429e9d4 | 5697 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5698 | |
7429e9d4 | 5699 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
5700 | case 5: |
5701 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5702 | break; | |
5703 | case 7: | |
5704 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5705 | break; | |
5706 | case 10: | |
5707 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5708 | break; | |
5709 | case 14: | |
5710 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5711 | break; | |
79e53945 JB |
5712 | } |
5713 | ||
b4c09f3b | 5714 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5715 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5716 | else |
5717 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5718 | ||
959e16d6 | 5719 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
5720 | } |
5721 | ||
5722 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
5723 | int x, int y, |
5724 | struct drm_framebuffer *fb) | |
5725 | { | |
5726 | struct drm_device *dev = crtc->dev; | |
5727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5729 | int pipe = intel_crtc->pipe; | |
5730 | int plane = intel_crtc->plane; | |
5731 | int num_connectors = 0; | |
5732 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 5733 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 5734 | bool ok, has_reduced_clock = false; |
8b47047b | 5735 | bool is_lvds = false; |
de13a2e3 | 5736 | struct intel_encoder *encoder; |
e2b78267 | 5737 | struct intel_shared_dpll *pll; |
de13a2e3 | 5738 | int ret; |
de13a2e3 PZ |
5739 | |
5740 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5741 | switch (encoder->type) { | |
5742 | case INTEL_OUTPUT_LVDS: | |
5743 | is_lvds = true; | |
5744 | break; | |
de13a2e3 PZ |
5745 | } |
5746 | ||
5747 | num_connectors++; | |
a07d6787 | 5748 | } |
79e53945 | 5749 | |
5dc5298b PZ |
5750 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5751 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5752 | |
ff9a6750 | 5753 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 5754 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 5755 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
5756 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5757 | return -EINVAL; | |
79e53945 | 5758 | } |
f47709a9 DV |
5759 | /* Compat-code for transition, will disappear. */ |
5760 | if (!intel_crtc->config.clock_set) { | |
5761 | intel_crtc->config.dpll.n = clock.n; | |
5762 | intel_crtc->config.dpll.m1 = clock.m1; | |
5763 | intel_crtc->config.dpll.m2 = clock.m2; | |
5764 | intel_crtc->config.dpll.p1 = clock.p1; | |
5765 | intel_crtc->config.dpll.p2 = clock.p2; | |
5766 | } | |
79e53945 | 5767 | |
5dc5298b | 5768 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 5769 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 5770 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 5771 | if (has_reduced_clock) |
7429e9d4 | 5772 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 5773 | |
7429e9d4 | 5774 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
5775 | &fp, &reduced_clock, |
5776 | has_reduced_clock ? &fp2 : NULL); | |
5777 | ||
959e16d6 | 5778 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
5779 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5780 | if (has_reduced_clock) | |
5781 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
5782 | else | |
5783 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
5784 | ||
b89a1d39 | 5785 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 5786 | if (pll == NULL) { |
84f44ce7 VS |
5787 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5788 | pipe_name(pipe)); | |
4b645f14 JB |
5789 | return -EINVAL; |
5790 | } | |
ee7b9f93 | 5791 | } else |
e72f9fbf | 5792 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 5793 | |
03afc4a2 DV |
5794 | if (intel_crtc->config.has_dp_encoder) |
5795 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 5796 | |
bcd644e0 DV |
5797 | if (is_lvds && has_reduced_clock && i915_powersave) |
5798 | intel_crtc->lowfreq_avail = true; | |
5799 | else | |
5800 | intel_crtc->lowfreq_avail = false; | |
e2b78267 DV |
5801 | |
5802 | if (intel_crtc->config.has_pch_encoder) { | |
5803 | pll = intel_crtc_to_shared_dpll(intel_crtc); | |
5804 | ||
652c393a JB |
5805 | } |
5806 | ||
8a654f3b | 5807 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 5808 | |
ca3a0ff8 | 5809 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
5810 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5811 | &intel_crtc->config.fdi_m_n); | |
5812 | } | |
2c07245f | 5813 | |
ebfd86fd DV |
5814 | if (IS_IVYBRIDGE(dev)) |
5815 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
79e53945 | 5816 | |
6ff93609 | 5817 | ironlake_set_pipeconf(crtc); |
79e53945 | 5818 | |
a1f9e77e PZ |
5819 | /* Set up the display plane register */ |
5820 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5821 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5822 | |
94352cf9 | 5823 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5824 | |
5825 | intel_update_watermarks(dev); | |
5826 | ||
1857e1da | 5827 | return ret; |
79e53945 JB |
5828 | } |
5829 | ||
72419203 DV |
5830 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5831 | struct intel_crtc_config *pipe_config) | |
5832 | { | |
5833 | struct drm_device *dev = crtc->base.dev; | |
5834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5835 | enum transcoder transcoder = pipe_config->cpu_transcoder; | |
5836 | ||
5837 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
5838 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
5839 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
5840 | & ~TU_SIZE_MASK; | |
5841 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
5842 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
5843 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
5844 | } | |
5845 | ||
2fa2fe9a DV |
5846 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5847 | struct intel_crtc_config *pipe_config) | |
5848 | { | |
5849 | struct drm_device *dev = crtc->base.dev; | |
5850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5851 | uint32_t tmp; | |
5852 | ||
5853 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
5854 | ||
5855 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 5856 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
5857 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5858 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
5859 | |
5860 | /* We currently do not free assignements of panel fitters on | |
5861 | * ivb/hsw (since we don't use the higher upscaling modes which | |
5862 | * differentiates them) so just WARN about this case for now. */ | |
5863 | if (IS_GEN7(dev)) { | |
5864 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
5865 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
5866 | } | |
2fa2fe9a | 5867 | } |
79e53945 JB |
5868 | } |
5869 | ||
0e8ffe1b DV |
5870 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5871 | struct intel_crtc_config *pipe_config) | |
5872 | { | |
5873 | struct drm_device *dev = crtc->base.dev; | |
5874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5875 | uint32_t tmp; | |
5876 | ||
e143a21c | 5877 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5878 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5879 | |
0e8ffe1b DV |
5880 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5881 | if (!(tmp & PIPECONF_ENABLE)) | |
5882 | return false; | |
5883 | ||
ab9412ba | 5884 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
5885 | struct intel_shared_dpll *pll; |
5886 | ||
88adfff1 DV |
5887 | pipe_config->has_pch_encoder = true; |
5888 | ||
627eb5a3 DV |
5889 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5890 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
5891 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
5892 | |
5893 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 5894 | |
c0d43d62 | 5895 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
5896 | pipe_config->shared_dpll = |
5897 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
5898 | } else { |
5899 | tmp = I915_READ(PCH_DPLL_SEL); | |
5900 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
5901 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
5902 | else | |
5903 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
5904 | } | |
66e985c0 DV |
5905 | |
5906 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
5907 | ||
5908 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
5909 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
5910 | |
5911 | tmp = pipe_config->dpll_hw_state.dpll; | |
5912 | pipe_config->pixel_multiplier = | |
5913 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
5914 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
6c49f241 DV |
5915 | } else { |
5916 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
5917 | } |
5918 | ||
1bd1bd80 DV |
5919 | intel_get_pipe_timings(crtc, pipe_config); |
5920 | ||
2fa2fe9a DV |
5921 | ironlake_get_pfit_config(crtc, pipe_config); |
5922 | ||
0e8ffe1b DV |
5923 | return true; |
5924 | } | |
5925 | ||
be256dc7 PZ |
5926 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
5927 | { | |
5928 | struct drm_device *dev = dev_priv->dev; | |
5929 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
5930 | struct intel_crtc *crtc; | |
5931 | unsigned long irqflags; | |
bd633a7c | 5932 | uint32_t val; |
be256dc7 PZ |
5933 | |
5934 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
5935 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | |
5936 | pipe_name(crtc->pipe)); | |
5937 | ||
5938 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
5939 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
5940 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
5941 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
5942 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
5943 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
5944 | "CPU PWM1 enabled\n"); | |
5945 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
5946 | "CPU PWM2 enabled\n"); | |
5947 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
5948 | "PCH PWM1 enabled\n"); | |
5949 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
5950 | "Utility pin enabled\n"); | |
5951 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
5952 | ||
5953 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
5954 | val = I915_READ(DEIMR); | |
5955 | WARN((val & ~DE_PCH_EVENT_IVB) != val, | |
5956 | "Unexpected DEIMR bits enabled: 0x%x\n", val); | |
5957 | val = I915_READ(SDEIMR); | |
bd633a7c | 5958 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
5959 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
5960 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
5961 | } | |
5962 | ||
5963 | /* | |
5964 | * This function implements pieces of two sequences from BSpec: | |
5965 | * - Sequence for display software to disable LCPLL | |
5966 | * - Sequence for display software to allow package C8+ | |
5967 | * The steps implemented here are just the steps that actually touch the LCPLL | |
5968 | * register. Callers should take care of disabling all the display engine | |
5969 | * functions, doing the mode unset, fixing interrupts, etc. | |
5970 | */ | |
5971 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, | |
5972 | bool switch_to_fclk, bool allow_power_down) | |
5973 | { | |
5974 | uint32_t val; | |
5975 | ||
5976 | assert_can_disable_lcpll(dev_priv); | |
5977 | ||
5978 | val = I915_READ(LCPLL_CTL); | |
5979 | ||
5980 | if (switch_to_fclk) { | |
5981 | val |= LCPLL_CD_SOURCE_FCLK; | |
5982 | I915_WRITE(LCPLL_CTL, val); | |
5983 | ||
5984 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
5985 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
5986 | DRM_ERROR("Switching to FCLK failed\n"); | |
5987 | ||
5988 | val = I915_READ(LCPLL_CTL); | |
5989 | } | |
5990 | ||
5991 | val |= LCPLL_PLL_DISABLE; | |
5992 | I915_WRITE(LCPLL_CTL, val); | |
5993 | POSTING_READ(LCPLL_CTL); | |
5994 | ||
5995 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
5996 | DRM_ERROR("LCPLL still locked\n"); | |
5997 | ||
5998 | val = I915_READ(D_COMP); | |
5999 | val |= D_COMP_COMP_DISABLE; | |
6000 | I915_WRITE(D_COMP, val); | |
6001 | POSTING_READ(D_COMP); | |
6002 | ndelay(100); | |
6003 | ||
6004 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6005 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6006 | ||
6007 | if (allow_power_down) { | |
6008 | val = I915_READ(LCPLL_CTL); | |
6009 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6010 | I915_WRITE(LCPLL_CTL, val); | |
6011 | POSTING_READ(LCPLL_CTL); | |
6012 | } | |
6013 | } | |
6014 | ||
6015 | /* | |
6016 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6017 | * source. | |
6018 | */ | |
6019 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |
6020 | { | |
6021 | uint32_t val; | |
6022 | ||
6023 | val = I915_READ(LCPLL_CTL); | |
6024 | ||
6025 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6026 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6027 | return; | |
6028 | ||
215733fa PZ |
6029 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6030 | * we'll hang the machine! */ | |
6031 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
6032 | ||
be256dc7 PZ |
6033 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6034 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6035 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6036 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6037 | } |
6038 | ||
6039 | val = I915_READ(D_COMP); | |
6040 | val |= D_COMP_COMP_FORCE; | |
6041 | val &= ~D_COMP_COMP_DISABLE; | |
6042 | I915_WRITE(D_COMP, val); | |
35d8f2eb | 6043 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6044 | |
6045 | val = I915_READ(LCPLL_CTL); | |
6046 | val &= ~LCPLL_PLL_DISABLE; | |
6047 | I915_WRITE(LCPLL_CTL, val); | |
6048 | ||
6049 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6050 | DRM_ERROR("LCPLL not locked yet\n"); | |
6051 | ||
6052 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6053 | val = I915_READ(LCPLL_CTL); | |
6054 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6055 | I915_WRITE(LCPLL_CTL, val); | |
6056 | ||
6057 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6058 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6059 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6060 | } | |
215733fa PZ |
6061 | |
6062 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
be256dc7 PZ |
6063 | } |
6064 | ||
c67a470b PZ |
6065 | void hsw_enable_pc8_work(struct work_struct *__work) |
6066 | { | |
6067 | struct drm_i915_private *dev_priv = | |
6068 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6069 | pc8.enable_work); | |
6070 | struct drm_device *dev = dev_priv->dev; | |
6071 | uint32_t val; | |
6072 | ||
6073 | if (dev_priv->pc8.enabled) | |
6074 | return; | |
6075 | ||
6076 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6077 | ||
6078 | dev_priv->pc8.enabled = true; | |
6079 | ||
6080 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6081 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6082 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6083 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6084 | } | |
6085 | ||
6086 | lpt_disable_clkout_dp(dev); | |
6087 | hsw_pc8_disable_interrupts(dev); | |
6088 | hsw_disable_lcpll(dev_priv, true, true); | |
6089 | } | |
6090 | ||
6091 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6092 | { | |
6093 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6094 | WARN(dev_priv->pc8.disable_count < 1, | |
6095 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6096 | ||
6097 | dev_priv->pc8.disable_count--; | |
6098 | if (dev_priv->pc8.disable_count != 0) | |
6099 | return; | |
6100 | ||
6101 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6102 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6103 | } |
6104 | ||
6105 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6106 | { | |
6107 | struct drm_device *dev = dev_priv->dev; | |
6108 | uint32_t val; | |
6109 | ||
6110 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6111 | WARN(dev_priv->pc8.disable_count < 0, | |
6112 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6113 | ||
6114 | dev_priv->pc8.disable_count++; | |
6115 | if (dev_priv->pc8.disable_count != 1) | |
6116 | return; | |
6117 | ||
6118 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); | |
6119 | if (!dev_priv->pc8.enabled) | |
6120 | return; | |
6121 | ||
6122 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6123 | ||
6124 | hsw_restore_lcpll(dev_priv); | |
6125 | hsw_pc8_restore_interrupts(dev); | |
6126 | lpt_init_pch_refclk(dev); | |
6127 | ||
6128 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6129 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6130 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6131 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6132 | } | |
6133 | ||
6134 | intel_prepare_ddi(dev); | |
6135 | i915_gem_init_swizzling(dev); | |
6136 | mutex_lock(&dev_priv->rps.hw_lock); | |
6137 | gen6_update_ring_freq(dev); | |
6138 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6139 | dev_priv->pc8.enabled = false; | |
6140 | } | |
6141 | ||
6142 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6143 | { | |
6144 | mutex_lock(&dev_priv->pc8.lock); | |
6145 | __hsw_enable_package_c8(dev_priv); | |
6146 | mutex_unlock(&dev_priv->pc8.lock); | |
6147 | } | |
6148 | ||
6149 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6150 | { | |
6151 | mutex_lock(&dev_priv->pc8.lock); | |
6152 | __hsw_disable_package_c8(dev_priv); | |
6153 | mutex_unlock(&dev_priv->pc8.lock); | |
6154 | } | |
6155 | ||
6156 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6157 | { | |
6158 | struct drm_device *dev = dev_priv->dev; | |
6159 | struct intel_crtc *crtc; | |
6160 | uint32_t val; | |
6161 | ||
6162 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6163 | if (crtc->base.enabled) | |
6164 | return false; | |
6165 | ||
6166 | /* This case is still possible since we have the i915.disable_power_well | |
6167 | * parameter and also the KVMr or something else might be requesting the | |
6168 | * power well. */ | |
6169 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6170 | if (val != 0) { | |
6171 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6172 | return false; | |
6173 | } | |
6174 | ||
6175 | return true; | |
6176 | } | |
6177 | ||
6178 | /* Since we're called from modeset_global_resources there's no way to | |
6179 | * symmetrically increase and decrease the refcount, so we use | |
6180 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6181 | * or not. | |
6182 | */ | |
6183 | static void hsw_update_package_c8(struct drm_device *dev) | |
6184 | { | |
6185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6186 | bool allow; | |
6187 | ||
6188 | if (!i915_enable_pc8) | |
6189 | return; | |
6190 | ||
6191 | mutex_lock(&dev_priv->pc8.lock); | |
6192 | ||
6193 | allow = hsw_can_enable_package_c8(dev_priv); | |
6194 | ||
6195 | if (allow == dev_priv->pc8.requirements_met) | |
6196 | goto done; | |
6197 | ||
6198 | dev_priv->pc8.requirements_met = allow; | |
6199 | ||
6200 | if (allow) | |
6201 | __hsw_enable_package_c8(dev_priv); | |
6202 | else | |
6203 | __hsw_disable_package_c8(dev_priv); | |
6204 | ||
6205 | done: | |
6206 | mutex_unlock(&dev_priv->pc8.lock); | |
6207 | } | |
6208 | ||
6209 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6210 | { | |
6211 | if (!dev_priv->pc8.gpu_idle) { | |
6212 | dev_priv->pc8.gpu_idle = true; | |
6213 | hsw_enable_package_c8(dev_priv); | |
6214 | } | |
6215 | } | |
6216 | ||
6217 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6218 | { | |
6219 | if (dev_priv->pc8.gpu_idle) { | |
6220 | dev_priv->pc8.gpu_idle = false; | |
6221 | hsw_disable_package_c8(dev_priv); | |
6222 | } | |
be256dc7 PZ |
6223 | } |
6224 | ||
d6dd9eb1 DV |
6225 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6226 | { | |
d6dd9eb1 DV |
6227 | bool enable = false; |
6228 | struct intel_crtc *crtc; | |
d6dd9eb1 DV |
6229 | |
6230 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
e7a639c4 DV |
6231 | if (!crtc->base.enabled) |
6232 | continue; | |
d6dd9eb1 | 6233 | |
fd4daa9c | 6234 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
e7a639c4 | 6235 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
d6dd9eb1 DV |
6236 | enable = true; |
6237 | } | |
6238 | ||
d6dd9eb1 | 6239 | intel_set_power_well(dev, enable); |
c67a470b PZ |
6240 | |
6241 | hsw_update_package_c8(dev); | |
d6dd9eb1 DV |
6242 | } |
6243 | ||
09b4ddf9 | 6244 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6245 | int x, int y, |
6246 | struct drm_framebuffer *fb) | |
6247 | { | |
6248 | struct drm_device *dev = crtc->dev; | |
6249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6251 | int plane = intel_crtc->plane; |
09b4ddf9 | 6252 | int ret; |
09b4ddf9 | 6253 | |
ff9a6750 | 6254 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6255 | return -EINVAL; |
6256 | ||
03afc4a2 DV |
6257 | if (intel_crtc->config.has_dp_encoder) |
6258 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6259 | |
6260 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6261 | |
8a654f3b | 6262 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6263 | |
ca3a0ff8 | 6264 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6265 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6266 | &intel_crtc->config.fdi_m_n); | |
6267 | } | |
09b4ddf9 | 6268 | |
6ff93609 | 6269 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6270 | |
50f3b016 | 6271 | intel_set_pipe_csc(crtc); |
86d3efce | 6272 | |
09b4ddf9 | 6273 | /* Set up the display plane register */ |
86d3efce | 6274 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6275 | POSTING_READ(DSPCNTR(plane)); |
6276 | ||
6277 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6278 | ||
6279 | intel_update_watermarks(dev); | |
6280 | ||
1f803ee5 | 6281 | return ret; |
79e53945 JB |
6282 | } |
6283 | ||
0e8ffe1b DV |
6284 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6285 | struct intel_crtc_config *pipe_config) | |
6286 | { | |
6287 | struct drm_device *dev = crtc->base.dev; | |
6288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6289 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6290 | uint32_t tmp; |
6291 | ||
e143a21c | 6292 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6293 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6294 | ||
eccb140b DV |
6295 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6296 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6297 | enum pipe trans_edp_pipe; | |
6298 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6299 | default: | |
6300 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6301 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6302 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6303 | trans_edp_pipe = PIPE_A; | |
6304 | break; | |
6305 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6306 | trans_edp_pipe = PIPE_B; | |
6307 | break; | |
6308 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6309 | trans_edp_pipe = PIPE_C; | |
6310 | break; | |
6311 | } | |
6312 | ||
6313 | if (trans_edp_pipe == crtc->pipe) | |
6314 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6315 | } | |
6316 | ||
b97186f0 | 6317 | if (!intel_display_power_enabled(dev, |
eccb140b | 6318 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6319 | return false; |
6320 | ||
eccb140b | 6321 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6322 | if (!(tmp & PIPECONF_ENABLE)) |
6323 | return false; | |
6324 | ||
88adfff1 | 6325 | /* |
f196e6be | 6326 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6327 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6328 | * the PCH transcoder is on. | |
6329 | */ | |
eccb140b | 6330 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6331 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6332 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6333 | pipe_config->has_pch_encoder = true; |
6334 | ||
627eb5a3 DV |
6335 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6336 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6337 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6338 | |
6339 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6340 | } |
6341 | ||
1bd1bd80 DV |
6342 | intel_get_pipe_timings(crtc, pipe_config); |
6343 | ||
2fa2fe9a DV |
6344 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6345 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6346 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6347 | |
42db64ef PZ |
6348 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6349 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
6350 | ||
6c49f241 DV |
6351 | pipe_config->pixel_multiplier = 1; |
6352 | ||
0e8ffe1b DV |
6353 | return true; |
6354 | } | |
6355 | ||
f564048e | 6356 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6357 | int x, int y, |
94352cf9 | 6358 | struct drm_framebuffer *fb) |
f564048e EA |
6359 | { |
6360 | struct drm_device *dev = crtc->dev; | |
6361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 6362 | struct intel_encoder *encoder; |
0b701d27 | 6363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 6364 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 6365 | int pipe = intel_crtc->pipe; |
f564048e EA |
6366 | int ret; |
6367 | ||
0b701d27 | 6368 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6369 | |
b8cecdf5 DV |
6370 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6371 | ||
79e53945 | 6372 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6373 | |
9256aa19 DV |
6374 | if (ret != 0) |
6375 | return ret; | |
6376 | ||
6377 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6378 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6379 | encoder->base.base.id, | |
6380 | drm_get_encoder_name(&encoder->base), | |
6381 | mode->base.id, mode->name); | |
36f2d1f1 | 6382 | encoder->mode_set(encoder); |
9256aa19 DV |
6383 | } |
6384 | ||
6385 | return 0; | |
79e53945 JB |
6386 | } |
6387 | ||
3a9627f4 WF |
6388 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6389 | int reg_eldv, uint32_t bits_eldv, | |
6390 | int reg_elda, uint32_t bits_elda, | |
6391 | int reg_edid) | |
6392 | { | |
6393 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6394 | uint8_t *eld = connector->eld; | |
6395 | uint32_t i; | |
6396 | ||
6397 | i = I915_READ(reg_eldv); | |
6398 | i &= bits_eldv; | |
6399 | ||
6400 | if (!eld[0]) | |
6401 | return !i; | |
6402 | ||
6403 | if (!i) | |
6404 | return false; | |
6405 | ||
6406 | i = I915_READ(reg_elda); | |
6407 | i &= ~bits_elda; | |
6408 | I915_WRITE(reg_elda, i); | |
6409 | ||
6410 | for (i = 0; i < eld[2]; i++) | |
6411 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6412 | return false; | |
6413 | ||
6414 | return true; | |
6415 | } | |
6416 | ||
e0dac65e WF |
6417 | static void g4x_write_eld(struct drm_connector *connector, |
6418 | struct drm_crtc *crtc) | |
6419 | { | |
6420 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6421 | uint8_t *eld = connector->eld; | |
6422 | uint32_t eldv; | |
6423 | uint32_t len; | |
6424 | uint32_t i; | |
6425 | ||
6426 | i = I915_READ(G4X_AUD_VID_DID); | |
6427 | ||
6428 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6429 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6430 | else | |
6431 | eldv = G4X_ELDV_DEVCTG; | |
6432 | ||
3a9627f4 WF |
6433 | if (intel_eld_uptodate(connector, |
6434 | G4X_AUD_CNTL_ST, eldv, | |
6435 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6436 | G4X_HDMIW_HDMIEDID)) | |
6437 | return; | |
6438 | ||
e0dac65e WF |
6439 | i = I915_READ(G4X_AUD_CNTL_ST); |
6440 | i &= ~(eldv | G4X_ELD_ADDR); | |
6441 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6442 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6443 | ||
6444 | if (!eld[0]) | |
6445 | return; | |
6446 | ||
6447 | len = min_t(uint8_t, eld[2], len); | |
6448 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6449 | for (i = 0; i < len; i++) | |
6450 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6451 | ||
6452 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6453 | i |= eldv; | |
6454 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6455 | } | |
6456 | ||
83358c85 WX |
6457 | static void haswell_write_eld(struct drm_connector *connector, |
6458 | struct drm_crtc *crtc) | |
6459 | { | |
6460 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6461 | uint8_t *eld = connector->eld; | |
6462 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 6463 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
6464 | uint32_t eldv; |
6465 | uint32_t i; | |
6466 | int len; | |
6467 | int pipe = to_intel_crtc(crtc)->pipe; | |
6468 | int tmp; | |
6469 | ||
6470 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
6471 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
6472 | int aud_config = HSW_AUD_CFG(pipe); | |
6473 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
6474 | ||
6475 | ||
6476 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
6477 | ||
6478 | /* Audio output enable */ | |
6479 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
6480 | tmp = I915_READ(aud_cntrl_st2); | |
6481 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
6482 | I915_WRITE(aud_cntrl_st2, tmp); | |
6483 | ||
6484 | /* Wait for 1 vertical blank */ | |
6485 | intel_wait_for_vblank(dev, pipe); | |
6486 | ||
6487 | /* Set ELD valid state */ | |
6488 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6489 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6490 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6491 | I915_WRITE(aud_cntrl_st2, tmp); | |
6492 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6493 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6494 | |
6495 | /* Enable HDMI mode */ | |
6496 | tmp = I915_READ(aud_config); | |
7e7cb34f | 6497 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
6498 | /* clear N_programing_enable and N_value_index */ |
6499 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
6500 | I915_WRITE(aud_config, tmp); | |
6501 | ||
6502 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
6503 | ||
6504 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 6505 | intel_crtc->eld_vld = true; |
83358c85 WX |
6506 | |
6507 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
6508 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6509 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
6510 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
6511 | } else | |
6512 | I915_WRITE(aud_config, 0); | |
6513 | ||
6514 | if (intel_eld_uptodate(connector, | |
6515 | aud_cntrl_st2, eldv, | |
6516 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6517 | hdmiw_hdmiedid)) | |
6518 | return; | |
6519 | ||
6520 | i = I915_READ(aud_cntrl_st2); | |
6521 | i &= ~eldv; | |
6522 | I915_WRITE(aud_cntrl_st2, i); | |
6523 | ||
6524 | if (!eld[0]) | |
6525 | return; | |
6526 | ||
6527 | i = I915_READ(aud_cntl_st); | |
6528 | i &= ~IBX_ELD_ADDRESS; | |
6529 | I915_WRITE(aud_cntl_st, i); | |
6530 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
6531 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
6532 | ||
6533 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6534 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6535 | for (i = 0; i < len; i++) | |
6536 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6537 | ||
6538 | i = I915_READ(aud_cntrl_st2); | |
6539 | i |= eldv; | |
6540 | I915_WRITE(aud_cntrl_st2, i); | |
6541 | ||
6542 | } | |
6543 | ||
e0dac65e WF |
6544 | static void ironlake_write_eld(struct drm_connector *connector, |
6545 | struct drm_crtc *crtc) | |
6546 | { | |
6547 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6548 | uint8_t *eld = connector->eld; | |
6549 | uint32_t eldv; | |
6550 | uint32_t i; | |
6551 | int len; | |
6552 | int hdmiw_hdmiedid; | |
b6daa025 | 6553 | int aud_config; |
e0dac65e WF |
6554 | int aud_cntl_st; |
6555 | int aud_cntrl_st2; | |
9b138a83 | 6556 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 6557 | |
b3f33cbf | 6558 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
6559 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6560 | aud_config = IBX_AUD_CFG(pipe); | |
6561 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6562 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 6563 | } else { |
9b138a83 WX |
6564 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6565 | aud_config = CPT_AUD_CFG(pipe); | |
6566 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6567 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
6568 | } |
6569 | ||
9b138a83 | 6570 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
6571 | |
6572 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 6573 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
6574 | if (!i) { |
6575 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6576 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6577 | eldv = IBX_ELD_VALIDB; |
6578 | eldv |= IBX_ELD_VALIDB << 4; | |
6579 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 6580 | } else { |
2582a850 | 6581 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 6582 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6583 | } |
6584 | ||
3a9627f4 WF |
6585 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6586 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6587 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6588 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6589 | } else | |
6590 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6591 | |
3a9627f4 WF |
6592 | if (intel_eld_uptodate(connector, |
6593 | aud_cntrl_st2, eldv, | |
6594 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6595 | hdmiw_hdmiedid)) | |
6596 | return; | |
6597 | ||
e0dac65e WF |
6598 | i = I915_READ(aud_cntrl_st2); |
6599 | i &= ~eldv; | |
6600 | I915_WRITE(aud_cntrl_st2, i); | |
6601 | ||
6602 | if (!eld[0]) | |
6603 | return; | |
6604 | ||
e0dac65e | 6605 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6606 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6607 | I915_WRITE(aud_cntl_st, i); |
6608 | ||
6609 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6610 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6611 | for (i = 0; i < len; i++) | |
6612 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6613 | ||
6614 | i = I915_READ(aud_cntrl_st2); | |
6615 | i |= eldv; | |
6616 | I915_WRITE(aud_cntrl_st2, i); | |
6617 | } | |
6618 | ||
6619 | void intel_write_eld(struct drm_encoder *encoder, | |
6620 | struct drm_display_mode *mode) | |
6621 | { | |
6622 | struct drm_crtc *crtc = encoder->crtc; | |
6623 | struct drm_connector *connector; | |
6624 | struct drm_device *dev = encoder->dev; | |
6625 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6626 | ||
6627 | connector = drm_select_eld(encoder, mode); | |
6628 | if (!connector) | |
6629 | return; | |
6630 | ||
6631 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6632 | connector->base.id, | |
6633 | drm_get_connector_name(connector), | |
6634 | connector->encoder->base.id, | |
6635 | drm_get_encoder_name(connector->encoder)); | |
6636 | ||
6637 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6638 | ||
6639 | if (dev_priv->display.write_eld) | |
6640 | dev_priv->display.write_eld(connector, crtc); | |
6641 | } | |
6642 | ||
79e53945 JB |
6643 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6644 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6645 | { | |
6646 | struct drm_device *dev = crtc->dev; | |
6647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
42db64ef PZ |
6649 | enum pipe pipe = intel_crtc->pipe; |
6650 | int palreg = PALETTE(pipe); | |
79e53945 | 6651 | int i; |
42db64ef | 6652 | bool reenable_ips = false; |
79e53945 JB |
6653 | |
6654 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6655 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6656 | return; |
6657 | ||
14420bd0 VS |
6658 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
6659 | assert_pll_enabled(dev_priv, pipe); | |
6660 | ||
f2b115e6 | 6661 | /* use legacy palette for Ironlake */ |
bad720ff | 6662 | if (HAS_PCH_SPLIT(dev)) |
42db64ef PZ |
6663 | palreg = LGC_PALETTE(pipe); |
6664 | ||
6665 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
6666 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6667 | */ | |
6668 | if (intel_crtc->config.ips_enabled && | |
6669 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
6670 | GAMMA_MODE_MODE_SPLIT)) { | |
6671 | hsw_disable_ips(intel_crtc); | |
6672 | reenable_ips = true; | |
6673 | } | |
2c07245f | 6674 | |
79e53945 JB |
6675 | for (i = 0; i < 256; i++) { |
6676 | I915_WRITE(palreg + 4 * i, | |
6677 | (intel_crtc->lut_r[i] << 16) | | |
6678 | (intel_crtc->lut_g[i] << 8) | | |
6679 | intel_crtc->lut_b[i]); | |
6680 | } | |
42db64ef PZ |
6681 | |
6682 | if (reenable_ips) | |
6683 | hsw_enable_ips(intel_crtc); | |
79e53945 JB |
6684 | } |
6685 | ||
560b85bb CW |
6686 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6687 | { | |
6688 | struct drm_device *dev = crtc->dev; | |
6689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6691 | bool visible = base != 0; | |
6692 | u32 cntl; | |
6693 | ||
6694 | if (intel_crtc->cursor_visible == visible) | |
6695 | return; | |
6696 | ||
9db4a9c7 | 6697 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6698 | if (visible) { |
6699 | /* On these chipsets we can only modify the base whilst | |
6700 | * the cursor is disabled. | |
6701 | */ | |
9db4a9c7 | 6702 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6703 | |
6704 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6705 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6706 | cntl |= CURSOR_ENABLE | | |
6707 | CURSOR_GAMMA_ENABLE | | |
6708 | CURSOR_FORMAT_ARGB; | |
6709 | } else | |
6710 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6711 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6712 | |
6713 | intel_crtc->cursor_visible = visible; | |
6714 | } | |
6715 | ||
6716 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6717 | { | |
6718 | struct drm_device *dev = crtc->dev; | |
6719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6721 | int pipe = intel_crtc->pipe; | |
6722 | bool visible = base != 0; | |
6723 | ||
6724 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6725 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6726 | if (base) { |
6727 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6728 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6729 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6730 | } else { | |
6731 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6732 | cntl |= CURSOR_MODE_DISABLE; | |
6733 | } | |
9db4a9c7 | 6734 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6735 | |
6736 | intel_crtc->cursor_visible = visible; | |
6737 | } | |
6738 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6739 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6740 | } |
6741 | ||
65a21cd6 JB |
6742 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6743 | { | |
6744 | struct drm_device *dev = crtc->dev; | |
6745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6747 | int pipe = intel_crtc->pipe; | |
6748 | bool visible = base != 0; | |
6749 | ||
6750 | if (intel_crtc->cursor_visible != visible) { | |
6751 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6752 | if (base) { | |
6753 | cntl &= ~CURSOR_MODE; | |
6754 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6755 | } else { | |
6756 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6757 | cntl |= CURSOR_MODE_DISABLE; | |
6758 | } | |
1f5d76db | 6759 | if (IS_HASWELL(dev)) { |
86d3efce | 6760 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
6761 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6762 | } | |
65a21cd6 JB |
6763 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6764 | ||
6765 | intel_crtc->cursor_visible = visible; | |
6766 | } | |
6767 | /* and commit changes on next vblank */ | |
6768 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6769 | } | |
6770 | ||
cda4b7d3 | 6771 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6772 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6773 | bool on) | |
cda4b7d3 CW |
6774 | { |
6775 | struct drm_device *dev = crtc->dev; | |
6776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6778 | int pipe = intel_crtc->pipe; | |
6779 | int x = intel_crtc->cursor_x; | |
6780 | int y = intel_crtc->cursor_y; | |
560b85bb | 6781 | u32 base, pos; |
cda4b7d3 CW |
6782 | bool visible; |
6783 | ||
6784 | pos = 0; | |
6785 | ||
6b383a7f | 6786 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6787 | base = intel_crtc->cursor_addr; |
6788 | if (x > (int) crtc->fb->width) | |
6789 | base = 0; | |
6790 | ||
6791 | if (y > (int) crtc->fb->height) | |
6792 | base = 0; | |
6793 | } else | |
6794 | base = 0; | |
6795 | ||
6796 | if (x < 0) { | |
6797 | if (x + intel_crtc->cursor_width < 0) | |
6798 | base = 0; | |
6799 | ||
6800 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6801 | x = -x; | |
6802 | } | |
6803 | pos |= x << CURSOR_X_SHIFT; | |
6804 | ||
6805 | if (y < 0) { | |
6806 | if (y + intel_crtc->cursor_height < 0) | |
6807 | base = 0; | |
6808 | ||
6809 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6810 | y = -y; | |
6811 | } | |
6812 | pos |= y << CURSOR_Y_SHIFT; | |
6813 | ||
6814 | visible = base != 0; | |
560b85bb | 6815 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6816 | return; |
6817 | ||
0cd83aa9 | 6818 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6819 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6820 | ivb_update_cursor(crtc, base); | |
6821 | } else { | |
6822 | I915_WRITE(CURPOS(pipe), pos); | |
6823 | if (IS_845G(dev) || IS_I865G(dev)) | |
6824 | i845_update_cursor(crtc, base); | |
6825 | else | |
6826 | i9xx_update_cursor(crtc, base); | |
6827 | } | |
cda4b7d3 CW |
6828 | } |
6829 | ||
79e53945 | 6830 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6831 | struct drm_file *file, |
79e53945 JB |
6832 | uint32_t handle, |
6833 | uint32_t width, uint32_t height) | |
6834 | { | |
6835 | struct drm_device *dev = crtc->dev; | |
6836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6838 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6839 | uint32_t addr; |
3f8bc370 | 6840 | int ret; |
79e53945 | 6841 | |
79e53945 JB |
6842 | /* if we want to turn off the cursor ignore width and height */ |
6843 | if (!handle) { | |
28c97730 | 6844 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6845 | addr = 0; |
05394f39 | 6846 | obj = NULL; |
5004417d | 6847 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6848 | goto finish; |
79e53945 JB |
6849 | } |
6850 | ||
6851 | /* Currently we only support 64x64 cursors */ | |
6852 | if (width != 64 || height != 64) { | |
6853 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6854 | return -EINVAL; | |
6855 | } | |
6856 | ||
05394f39 | 6857 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6858 | if (&obj->base == NULL) |
79e53945 JB |
6859 | return -ENOENT; |
6860 | ||
05394f39 | 6861 | if (obj->base.size < width * height * 4) { |
79e53945 | 6862 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6863 | ret = -ENOMEM; |
6864 | goto fail; | |
79e53945 JB |
6865 | } |
6866 | ||
71acb5eb | 6867 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6868 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6869 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
6870 | unsigned alignment; |
6871 | ||
d9e86c0e CW |
6872 | if (obj->tiling_mode) { |
6873 | DRM_ERROR("cursor cannot be tiled\n"); | |
6874 | ret = -EINVAL; | |
6875 | goto fail_locked; | |
6876 | } | |
6877 | ||
693db184 CW |
6878 | /* Note that the w/a also requires 2 PTE of padding following |
6879 | * the bo. We currently fill all unused PTE with the shadow | |
6880 | * page and so we should always have valid PTE following the | |
6881 | * cursor preventing the VT-d warning. | |
6882 | */ | |
6883 | alignment = 0; | |
6884 | if (need_vtd_wa(dev)) | |
6885 | alignment = 64*1024; | |
6886 | ||
6887 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
6888 | if (ret) { |
6889 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6890 | goto fail_locked; |
e7b526bb CW |
6891 | } |
6892 | ||
d9e86c0e CW |
6893 | ret = i915_gem_object_put_fence(obj); |
6894 | if (ret) { | |
2da3b9b9 | 6895 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6896 | goto fail_unpin; |
6897 | } | |
6898 | ||
f343c5f6 | 6899 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 6900 | } else { |
6eeefaf3 | 6901 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6902 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6903 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6904 | align); | |
71acb5eb DA |
6905 | if (ret) { |
6906 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6907 | goto fail_locked; |
71acb5eb | 6908 | } |
05394f39 | 6909 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6910 | } |
6911 | ||
a6c45cf0 | 6912 | if (IS_GEN2(dev)) |
14b60391 JB |
6913 | I915_WRITE(CURSIZE, (height << 12) | width); |
6914 | ||
3f8bc370 | 6915 | finish: |
3f8bc370 | 6916 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6917 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6918 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6919 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6920 | } else | |
cc98b413 | 6921 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 6922 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6923 | } |
80824003 | 6924 | |
7f9872e0 | 6925 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6926 | |
6927 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6928 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6929 | intel_crtc->cursor_width = width; |
6930 | intel_crtc->cursor_height = height; | |
6931 | ||
f2f5f771 VS |
6932 | if (intel_crtc->active) |
6933 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 6934 | |
79e53945 | 6935 | return 0; |
e7b526bb | 6936 | fail_unpin: |
cc98b413 | 6937 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 6938 | fail_locked: |
34b8686e | 6939 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6940 | fail: |
05394f39 | 6941 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6942 | return ret; |
79e53945 JB |
6943 | } |
6944 | ||
6945 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6946 | { | |
79e53945 | 6947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6948 | |
cda4b7d3 CW |
6949 | intel_crtc->cursor_x = x; |
6950 | intel_crtc->cursor_y = y; | |
652c393a | 6951 | |
f2f5f771 VS |
6952 | if (intel_crtc->active) |
6953 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
6954 | |
6955 | return 0; | |
6956 | } | |
6957 | ||
6958 | /** Sets the color ramps on behalf of RandR */ | |
6959 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6960 | u16 blue, int regno) | |
6961 | { | |
6962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6963 | ||
6964 | intel_crtc->lut_r[regno] = red >> 8; | |
6965 | intel_crtc->lut_g[regno] = green >> 8; | |
6966 | intel_crtc->lut_b[regno] = blue >> 8; | |
6967 | } | |
6968 | ||
b8c00ac5 DA |
6969 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6970 | u16 *blue, int regno) | |
6971 | { | |
6972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6973 | ||
6974 | *red = intel_crtc->lut_r[regno] << 8; | |
6975 | *green = intel_crtc->lut_g[regno] << 8; | |
6976 | *blue = intel_crtc->lut_b[regno] << 8; | |
6977 | } | |
6978 | ||
79e53945 | 6979 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6980 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6981 | { |
7203425a | 6982 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6984 | |
7203425a | 6985 | for (i = start; i < end; i++) { |
79e53945 JB |
6986 | intel_crtc->lut_r[i] = red[i] >> 8; |
6987 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6988 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6989 | } | |
6990 | ||
6991 | intel_crtc_load_lut(crtc); | |
6992 | } | |
6993 | ||
79e53945 JB |
6994 | /* VESA 640x480x72Hz mode to set on the pipe */ |
6995 | static struct drm_display_mode load_detect_mode = { | |
6996 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6997 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6998 | }; | |
6999 | ||
d2dff872 CW |
7000 | static struct drm_framebuffer * |
7001 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7002 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7003 | struct drm_i915_gem_object *obj) |
7004 | { | |
7005 | struct intel_framebuffer *intel_fb; | |
7006 | int ret; | |
7007 | ||
7008 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7009 | if (!intel_fb) { | |
7010 | drm_gem_object_unreference_unlocked(&obj->base); | |
7011 | return ERR_PTR(-ENOMEM); | |
7012 | } | |
7013 | ||
7014 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
7015 | if (ret) { | |
7016 | drm_gem_object_unreference_unlocked(&obj->base); | |
7017 | kfree(intel_fb); | |
7018 | return ERR_PTR(ret); | |
7019 | } | |
7020 | ||
7021 | return &intel_fb->base; | |
7022 | } | |
7023 | ||
7024 | static u32 | |
7025 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7026 | { | |
7027 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7028 | return ALIGN(pitch, 64); | |
7029 | } | |
7030 | ||
7031 | static u32 | |
7032 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7033 | { | |
7034 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7035 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7036 | } | |
7037 | ||
7038 | static struct drm_framebuffer * | |
7039 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7040 | struct drm_display_mode *mode, | |
7041 | int depth, int bpp) | |
7042 | { | |
7043 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7044 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7045 | |
7046 | obj = i915_gem_alloc_object(dev, | |
7047 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7048 | if (obj == NULL) | |
7049 | return ERR_PTR(-ENOMEM); | |
7050 | ||
7051 | mode_cmd.width = mode->hdisplay; | |
7052 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7053 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7054 | bpp); | |
5ca0c34a | 7055 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7056 | |
7057 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7058 | } | |
7059 | ||
7060 | static struct drm_framebuffer * | |
7061 | mode_fits_in_fbdev(struct drm_device *dev, | |
7062 | struct drm_display_mode *mode) | |
7063 | { | |
7064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7065 | struct drm_i915_gem_object *obj; | |
7066 | struct drm_framebuffer *fb; | |
7067 | ||
7068 | if (dev_priv->fbdev == NULL) | |
7069 | return NULL; | |
7070 | ||
7071 | obj = dev_priv->fbdev->ifb.obj; | |
7072 | if (obj == NULL) | |
7073 | return NULL; | |
7074 | ||
7075 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7076 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7077 | fb->bits_per_pixel)) | |
d2dff872 CW |
7078 | return NULL; |
7079 | ||
01f2c773 | 7080 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7081 | return NULL; |
7082 | ||
7083 | return fb; | |
7084 | } | |
7085 | ||
d2434ab7 | 7086 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7087 | struct drm_display_mode *mode, |
8261b191 | 7088 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7089 | { |
7090 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7091 | struct intel_encoder *intel_encoder = |
7092 | intel_attached_encoder(connector); | |
79e53945 | 7093 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7094 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7095 | struct drm_crtc *crtc = NULL; |
7096 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7097 | struct drm_framebuffer *fb; |
79e53945 JB |
7098 | int i = -1; |
7099 | ||
d2dff872 CW |
7100 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7101 | connector->base.id, drm_get_connector_name(connector), | |
7102 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7103 | ||
79e53945 JB |
7104 | /* |
7105 | * Algorithm gets a little messy: | |
7a5e4805 | 7106 | * |
79e53945 JB |
7107 | * - if the connector already has an assigned crtc, use it (but make |
7108 | * sure it's on first) | |
7a5e4805 | 7109 | * |
79e53945 JB |
7110 | * - try to find the first unused crtc that can drive this connector, |
7111 | * and use that if we find one | |
79e53945 JB |
7112 | */ |
7113 | ||
7114 | /* See if we already have a CRTC for this connector */ | |
7115 | if (encoder->crtc) { | |
7116 | crtc = encoder->crtc; | |
8261b191 | 7117 | |
7b24056b DV |
7118 | mutex_lock(&crtc->mutex); |
7119 | ||
24218aac | 7120 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7121 | old->load_detect_temp = false; |
7122 | ||
7123 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7124 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7125 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7126 | |
7173188d | 7127 | return true; |
79e53945 JB |
7128 | } |
7129 | ||
7130 | /* Find an unused one (if possible) */ | |
7131 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7132 | i++; | |
7133 | if (!(encoder->possible_crtcs & (1 << i))) | |
7134 | continue; | |
7135 | if (!possible_crtc->enabled) { | |
7136 | crtc = possible_crtc; | |
7137 | break; | |
7138 | } | |
79e53945 JB |
7139 | } |
7140 | ||
7141 | /* | |
7142 | * If we didn't find an unused CRTC, don't use any. | |
7143 | */ | |
7144 | if (!crtc) { | |
7173188d CW |
7145 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7146 | return false; | |
79e53945 JB |
7147 | } |
7148 | ||
7b24056b | 7149 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7150 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7151 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7152 | |
7153 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7154 | old->dpms_mode = connector->dpms; |
8261b191 | 7155 | old->load_detect_temp = true; |
d2dff872 | 7156 | old->release_fb = NULL; |
79e53945 | 7157 | |
6492711d CW |
7158 | if (!mode) |
7159 | mode = &load_detect_mode; | |
79e53945 | 7160 | |
d2dff872 CW |
7161 | /* We need a framebuffer large enough to accommodate all accesses |
7162 | * that the plane may generate whilst we perform load detection. | |
7163 | * We can not rely on the fbcon either being present (we get called | |
7164 | * during its initialisation to detect all boot displays, or it may | |
7165 | * not even exist) or that it is large enough to satisfy the | |
7166 | * requested mode. | |
7167 | */ | |
94352cf9 DV |
7168 | fb = mode_fits_in_fbdev(dev, mode); |
7169 | if (fb == NULL) { | |
d2dff872 | 7170 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7171 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7172 | old->release_fb = fb; | |
d2dff872 CW |
7173 | } else |
7174 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7175 | if (IS_ERR(fb)) { |
d2dff872 | 7176 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7177 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7178 | return false; |
79e53945 | 7179 | } |
79e53945 | 7180 | |
c0c36b94 | 7181 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7182 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7183 | if (old->release_fb) |
7184 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7185 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7186 | return false; |
79e53945 | 7187 | } |
7173188d | 7188 | |
79e53945 | 7189 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7190 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7191 | return true; |
79e53945 JB |
7192 | } |
7193 | ||
d2434ab7 | 7194 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7195 | struct intel_load_detect_pipe *old) |
79e53945 | 7196 | { |
d2434ab7 DV |
7197 | struct intel_encoder *intel_encoder = |
7198 | intel_attached_encoder(connector); | |
4ef69c7a | 7199 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7200 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7201 | |
d2dff872 CW |
7202 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7203 | connector->base.id, drm_get_connector_name(connector), | |
7204 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7205 | ||
8261b191 | 7206 | if (old->load_detect_temp) { |
fc303101 DV |
7207 | to_intel_connector(connector)->new_encoder = NULL; |
7208 | intel_encoder->new_crtc = NULL; | |
7209 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7210 | |
36206361 DV |
7211 | if (old->release_fb) { |
7212 | drm_framebuffer_unregister_private(old->release_fb); | |
7213 | drm_framebuffer_unreference(old->release_fb); | |
7214 | } | |
d2dff872 | 7215 | |
67c96400 | 7216 | mutex_unlock(&crtc->mutex); |
0622a53c | 7217 | return; |
79e53945 JB |
7218 | } |
7219 | ||
c751ce4f | 7220 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7221 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7222 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7223 | |
7224 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7225 | } |
7226 | ||
7227 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
f1f644dc JB |
7228 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7229 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7230 | { |
f1f644dc | 7231 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7232 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7233 | int pipe = pipe_config->cpu_transcoder; |
548f245b | 7234 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
7235 | u32 fp; |
7236 | intel_clock_t clock; | |
7237 | ||
7238 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 7239 | fp = I915_READ(FP0(pipe)); |
79e53945 | 7240 | else |
39adb7a5 | 7241 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
7242 | |
7243 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7244 | if (IS_PINEVIEW(dev)) { |
7245 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7246 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7247 | } else { |
7248 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7249 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7250 | } | |
7251 | ||
a6c45cf0 | 7252 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7253 | if (IS_PINEVIEW(dev)) |
7254 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7255 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7256 | else |
7257 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7258 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7259 | ||
7260 | switch (dpll & DPLL_MODE_MASK) { | |
7261 | case DPLLB_MODE_DAC_SERIAL: | |
7262 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7263 | 5 : 10; | |
7264 | break; | |
7265 | case DPLLB_MODE_LVDS: | |
7266 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7267 | 7 : 14; | |
7268 | break; | |
7269 | default: | |
28c97730 | 7270 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7271 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc JB |
7272 | pipe_config->adjusted_mode.clock = 0; |
7273 | return; | |
79e53945 JB |
7274 | } |
7275 | ||
ac58c3f0 DV |
7276 | if (IS_PINEVIEW(dev)) |
7277 | pineview_clock(96000, &clock); | |
7278 | else | |
7279 | i9xx_clock(96000, &clock); | |
79e53945 JB |
7280 | } else { |
7281 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7282 | ||
7283 | if (is_lvds) { | |
7284 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7285 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7286 | clock.p2 = 14; | |
7287 | ||
7288 | if ((dpll & PLL_REF_INPUT_MASK) == | |
7289 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7290 | /* XXX: might not be 66MHz */ | |
ac58c3f0 | 7291 | i9xx_clock(66000, &clock); |
79e53945 | 7292 | } else |
ac58c3f0 | 7293 | i9xx_clock(48000, &clock); |
79e53945 JB |
7294 | } else { |
7295 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7296 | clock.p1 = 2; | |
7297 | else { | |
7298 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7299 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7300 | } | |
7301 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7302 | clock.p2 = 4; | |
7303 | else | |
7304 | clock.p2 = 2; | |
7305 | ||
ac58c3f0 | 7306 | i9xx_clock(48000, &clock); |
79e53945 JB |
7307 | } |
7308 | } | |
7309 | ||
a2dc53e7 | 7310 | pipe_config->adjusted_mode.clock = clock.dot; |
f1f644dc JB |
7311 | } |
7312 | ||
7313 | static void ironlake_crtc_clock_get(struct intel_crtc *crtc, | |
7314 | struct intel_crtc_config *pipe_config) | |
7315 | { | |
7316 | struct drm_device *dev = crtc->base.dev; | |
7317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7318 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7319 | int link_freq, repeat; | |
7320 | u64 clock; | |
7321 | u32 link_m, link_n; | |
7322 | ||
7323 | repeat = pipe_config->pixel_multiplier; | |
7324 | ||
7325 | /* | |
7326 | * The calculation for the data clock is: | |
7327 | * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp | |
7328 | * But we want to avoid losing precison if possible, so: | |
7329 | * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp)) | |
7330 | * | |
7331 | * and the link clock is simpler: | |
7332 | * link_clock = (m * link_clock * repeat) / n | |
7333 | */ | |
7334 | ||
7335 | /* | |
7336 | * We need to get the FDI or DP link clock here to derive | |
7337 | * the M/N dividers. | |
7338 | * | |
7339 | * For FDI, we read it from the BIOS or use a fixed 2.7GHz. | |
7340 | * For DP, it's either 1.62GHz or 2.7GHz. | |
7341 | * We do our calculations in 10*MHz since we don't need much precison. | |
79e53945 | 7342 | */ |
f1f644dc JB |
7343 | if (pipe_config->has_pch_encoder) |
7344 | link_freq = intel_fdi_link_freq(dev) * 10000; | |
7345 | else | |
7346 | link_freq = pipe_config->port_clock; | |
7347 | ||
7348 | link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); | |
7349 | link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder)); | |
7350 | ||
7351 | if (!link_m || !link_n) | |
7352 | return; | |
79e53945 | 7353 | |
f1f644dc JB |
7354 | clock = ((u64)link_m * (u64)link_freq * (u64)repeat); |
7355 | do_div(clock, link_n); | |
7356 | ||
7357 | pipe_config->adjusted_mode.clock = clock; | |
79e53945 JB |
7358 | } |
7359 | ||
7360 | /** Returns the currently programmed mode of the given pipe. */ | |
7361 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7362 | struct drm_crtc *crtc) | |
7363 | { | |
548f245b | 7364 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7366 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7367 | struct drm_display_mode *mode; |
f1f644dc | 7368 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
7369 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7370 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7371 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7372 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
7373 | |
7374 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7375 | if (!mode) | |
7376 | return NULL; | |
7377 | ||
f1f644dc JB |
7378 | /* |
7379 | * Construct a pipe_config sufficient for getting the clock info | |
7380 | * back out of crtc_clock_get. | |
7381 | * | |
7382 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
7383 | * to use a real value here instead. | |
7384 | */ | |
e143a21c | 7385 | pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
f1f644dc JB |
7386 | pipe_config.pixel_multiplier = 1; |
7387 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); | |
7388 | ||
7389 | mode->clock = pipe_config.adjusted_mode.clock; | |
79e53945 JB |
7390 | mode->hdisplay = (htot & 0xffff) + 1; |
7391 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
7392 | mode->hsync_start = (hsync & 0xffff) + 1; | |
7393 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
7394 | mode->vdisplay = (vtot & 0xffff) + 1; | |
7395 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
7396 | mode->vsync_start = (vsync & 0xffff) + 1; | |
7397 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
7398 | ||
7399 | drm_mode_set_name(mode); | |
79e53945 JB |
7400 | |
7401 | return mode; | |
7402 | } | |
7403 | ||
3dec0095 | 7404 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7405 | { |
7406 | struct drm_device *dev = crtc->dev; | |
7407 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7409 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7410 | int dpll_reg = DPLL(pipe); |
7411 | int dpll; | |
652c393a | 7412 | |
bad720ff | 7413 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7414 | return; |
7415 | ||
7416 | if (!dev_priv->lvds_downclock_avail) | |
7417 | return; | |
7418 | ||
dbdc6479 | 7419 | dpll = I915_READ(dpll_reg); |
652c393a | 7420 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7421 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7422 | |
8ac5a6d5 | 7423 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7424 | |
7425 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7426 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7427 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7428 | |
652c393a JB |
7429 | dpll = I915_READ(dpll_reg); |
7430 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7431 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 7432 | } |
652c393a JB |
7433 | } |
7434 | ||
7435 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7436 | { | |
7437 | struct drm_device *dev = crtc->dev; | |
7438 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 7440 | |
bad720ff | 7441 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7442 | return; |
7443 | ||
7444 | if (!dev_priv->lvds_downclock_avail) | |
7445 | return; | |
7446 | ||
7447 | /* | |
7448 | * Since this is called by a timer, we should never get here in | |
7449 | * the manual case. | |
7450 | */ | |
7451 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
7452 | int pipe = intel_crtc->pipe; |
7453 | int dpll_reg = DPLL(pipe); | |
7454 | int dpll; | |
f6e5b160 | 7455 | |
44d98a61 | 7456 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7457 | |
8ac5a6d5 | 7458 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 7459 | |
dc257cf1 | 7460 | dpll = I915_READ(dpll_reg); |
652c393a JB |
7461 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7462 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7463 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7464 | dpll = I915_READ(dpll_reg); |
7465 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7466 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7467 | } |
7468 | ||
7469 | } | |
7470 | ||
f047e395 CW |
7471 | void intel_mark_busy(struct drm_device *dev) |
7472 | { | |
c67a470b PZ |
7473 | struct drm_i915_private *dev_priv = dev->dev_private; |
7474 | ||
7475 | hsw_package_c8_gpu_busy(dev_priv); | |
7476 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
7477 | } |
7478 | ||
7479 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 7480 | { |
c67a470b | 7481 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 7482 | struct drm_crtc *crtc; |
652c393a | 7483 | |
c67a470b PZ |
7484 | hsw_package_c8_gpu_idle(dev_priv); |
7485 | ||
652c393a JB |
7486 | if (!i915_powersave) |
7487 | return; | |
7488 | ||
652c393a | 7489 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
7490 | if (!crtc->fb) |
7491 | continue; | |
7492 | ||
725a5b54 | 7493 | intel_decrease_pllclock(crtc); |
652c393a | 7494 | } |
652c393a JB |
7495 | } |
7496 | ||
c65355bb CW |
7497 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7498 | struct intel_ring_buffer *ring) | |
652c393a | 7499 | { |
f047e395 CW |
7500 | struct drm_device *dev = obj->base.dev; |
7501 | struct drm_crtc *crtc; | |
652c393a | 7502 | |
f047e395 | 7503 | if (!i915_powersave) |
acb87dfb CW |
7504 | return; |
7505 | ||
652c393a JB |
7506 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7507 | if (!crtc->fb) | |
7508 | continue; | |
7509 | ||
c65355bb CW |
7510 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7511 | continue; | |
7512 | ||
7513 | intel_increase_pllclock(crtc); | |
7514 | if (ring && intel_fbc_enabled(dev)) | |
7515 | ring->fbc_dirty = true; | |
652c393a JB |
7516 | } |
7517 | } | |
7518 | ||
79e53945 JB |
7519 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7520 | { | |
7521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7522 | struct drm_device *dev = crtc->dev; |
7523 | struct intel_unpin_work *work; | |
7524 | unsigned long flags; | |
7525 | ||
7526 | spin_lock_irqsave(&dev->event_lock, flags); | |
7527 | work = intel_crtc->unpin_work; | |
7528 | intel_crtc->unpin_work = NULL; | |
7529 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7530 | ||
7531 | if (work) { | |
7532 | cancel_work_sync(&work->work); | |
7533 | kfree(work); | |
7534 | } | |
79e53945 | 7535 | |
40ccc72b MK |
7536 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
7537 | ||
79e53945 | 7538 | drm_crtc_cleanup(crtc); |
67e77c5a | 7539 | |
79e53945 JB |
7540 | kfree(intel_crtc); |
7541 | } | |
7542 | ||
6b95a207 KH |
7543 | static void intel_unpin_work_fn(struct work_struct *__work) |
7544 | { | |
7545 | struct intel_unpin_work *work = | |
7546 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 7547 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 7548 | |
b4a98e57 | 7549 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 7550 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7551 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7552 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7553 | |
b4a98e57 CW |
7554 | intel_update_fbc(dev); |
7555 | mutex_unlock(&dev->struct_mutex); | |
7556 | ||
7557 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
7558 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
7559 | ||
6b95a207 KH |
7560 | kfree(work); |
7561 | } | |
7562 | ||
1afe3e9d | 7563 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7564 | struct drm_crtc *crtc) |
6b95a207 KH |
7565 | { |
7566 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7568 | struct intel_unpin_work *work; | |
6b95a207 KH |
7569 | unsigned long flags; |
7570 | ||
7571 | /* Ignore early vblank irqs */ | |
7572 | if (intel_crtc == NULL) | |
7573 | return; | |
7574 | ||
7575 | spin_lock_irqsave(&dev->event_lock, flags); | |
7576 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
7577 | |
7578 | /* Ensure we don't miss a work->pending update ... */ | |
7579 | smp_rmb(); | |
7580 | ||
7581 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
7582 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7583 | return; | |
7584 | } | |
7585 | ||
e7d841ca CW |
7586 | /* and that the unpin work is consistent wrt ->pending. */ |
7587 | smp_rmb(); | |
7588 | ||
6b95a207 | 7589 | intel_crtc->unpin_work = NULL; |
6b95a207 | 7590 | |
45a066eb RC |
7591 | if (work->event) |
7592 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 7593 | |
0af7e4df MK |
7594 | drm_vblank_put(dev, intel_crtc->pipe); |
7595 | ||
6b95a207 KH |
7596 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7597 | ||
2c10d571 | 7598 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
7599 | |
7600 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
7601 | |
7602 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7603 | } |
7604 | ||
1afe3e9d JB |
7605 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7606 | { | |
7607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7608 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7609 | ||
49b14a5c | 7610 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7611 | } |
7612 | ||
7613 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7614 | { | |
7615 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7616 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7617 | ||
49b14a5c | 7618 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7619 | } |
7620 | ||
6b95a207 KH |
7621 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7622 | { | |
7623 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7624 | struct intel_crtc *intel_crtc = | |
7625 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7626 | unsigned long flags; | |
7627 | ||
e7d841ca CW |
7628 | /* NB: An MMIO update of the plane base pointer will also |
7629 | * generate a page-flip completion irq, i.e. every modeset | |
7630 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
7631 | */ | |
6b95a207 | 7632 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
7633 | if (intel_crtc->unpin_work) |
7634 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
7635 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7636 | } | |
7637 | ||
e7d841ca CW |
7638 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7639 | { | |
7640 | /* Ensure that the work item is consistent when activating it ... */ | |
7641 | smp_wmb(); | |
7642 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
7643 | /* and that it is marked active as soon as the irq could fire. */ | |
7644 | smp_wmb(); | |
7645 | } | |
7646 | ||
8c9f3aaf JB |
7647 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7648 | struct drm_crtc *crtc, | |
7649 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7650 | struct drm_i915_gem_object *obj, |
7651 | uint32_t flags) | |
8c9f3aaf JB |
7652 | { |
7653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7655 | u32 flip_mask; |
6d90c952 | 7656 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7657 | int ret; |
7658 | ||
6d90c952 | 7659 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7660 | if (ret) |
83d4092b | 7661 | goto err; |
8c9f3aaf | 7662 | |
6d90c952 | 7663 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7664 | if (ret) |
83d4092b | 7665 | goto err_unpin; |
8c9f3aaf JB |
7666 | |
7667 | /* Can't queue multiple flips, so wait for the previous | |
7668 | * one to finish before executing the next. | |
7669 | */ | |
7670 | if (intel_crtc->plane) | |
7671 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7672 | else | |
7673 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7674 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7675 | intel_ring_emit(ring, MI_NOOP); | |
7676 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
7677 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7678 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7679 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 7680 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
7681 | |
7682 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7683 | intel_ring_advance(ring); |
83d4092b CW |
7684 | return 0; |
7685 | ||
7686 | err_unpin: | |
7687 | intel_unpin_fb_obj(obj); | |
7688 | err: | |
8c9f3aaf JB |
7689 | return ret; |
7690 | } | |
7691 | ||
7692 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7693 | struct drm_crtc *crtc, | |
7694 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7695 | struct drm_i915_gem_object *obj, |
7696 | uint32_t flags) | |
8c9f3aaf JB |
7697 | { |
7698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7700 | u32 flip_mask; |
6d90c952 | 7701 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7702 | int ret; |
7703 | ||
6d90c952 | 7704 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7705 | if (ret) |
83d4092b | 7706 | goto err; |
8c9f3aaf | 7707 | |
6d90c952 | 7708 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7709 | if (ret) |
83d4092b | 7710 | goto err_unpin; |
8c9f3aaf JB |
7711 | |
7712 | if (intel_crtc->plane) | |
7713 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7714 | else | |
7715 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7716 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7717 | intel_ring_emit(ring, MI_NOOP); | |
7718 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
7719 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7720 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7721 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
7722 | intel_ring_emit(ring, MI_NOOP); |
7723 | ||
e7d841ca | 7724 | intel_mark_page_flip_active(intel_crtc); |
6d90c952 | 7725 | intel_ring_advance(ring); |
83d4092b CW |
7726 | return 0; |
7727 | ||
7728 | err_unpin: | |
7729 | intel_unpin_fb_obj(obj); | |
7730 | err: | |
8c9f3aaf JB |
7731 | return ret; |
7732 | } | |
7733 | ||
7734 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7735 | struct drm_crtc *crtc, | |
7736 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7737 | struct drm_i915_gem_object *obj, |
7738 | uint32_t flags) | |
8c9f3aaf JB |
7739 | { |
7740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7742 | uint32_t pf, pipesrc; | |
6d90c952 | 7743 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7744 | int ret; |
7745 | ||
6d90c952 | 7746 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7747 | if (ret) |
83d4092b | 7748 | goto err; |
8c9f3aaf | 7749 | |
6d90c952 | 7750 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7751 | if (ret) |
83d4092b | 7752 | goto err_unpin; |
8c9f3aaf JB |
7753 | |
7754 | /* i965+ uses the linear or tiled offsets from the | |
7755 | * Display Registers (which do not change across a page-flip) | |
7756 | * so we need only reprogram the base address. | |
7757 | */ | |
6d90c952 DV |
7758 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7759 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7760 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 7761 | intel_ring_emit(ring, |
f343c5f6 | 7762 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 7763 | obj->tiling_mode); |
8c9f3aaf JB |
7764 | |
7765 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7766 | * untested on non-native modes, so ignore it for now. | |
7767 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7768 | */ | |
7769 | pf = 0; | |
7770 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7771 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7772 | |
7773 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7774 | intel_ring_advance(ring); |
83d4092b CW |
7775 | return 0; |
7776 | ||
7777 | err_unpin: | |
7778 | intel_unpin_fb_obj(obj); | |
7779 | err: | |
8c9f3aaf JB |
7780 | return ret; |
7781 | } | |
7782 | ||
7783 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7784 | struct drm_crtc *crtc, | |
7785 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7786 | struct drm_i915_gem_object *obj, |
7787 | uint32_t flags) | |
8c9f3aaf JB |
7788 | { |
7789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7791 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7792 | uint32_t pf, pipesrc; |
7793 | int ret; | |
7794 | ||
6d90c952 | 7795 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7796 | if (ret) |
83d4092b | 7797 | goto err; |
8c9f3aaf | 7798 | |
6d90c952 | 7799 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7800 | if (ret) |
83d4092b | 7801 | goto err_unpin; |
8c9f3aaf | 7802 | |
6d90c952 DV |
7803 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7804 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7805 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 7806 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7807 | |
dc257cf1 DV |
7808 | /* Contrary to the suggestions in the documentation, |
7809 | * "Enable Panel Fitter" does not seem to be required when page | |
7810 | * flipping with a non-native mode, and worse causes a normal | |
7811 | * modeset to fail. | |
7812 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7813 | */ | |
7814 | pf = 0; | |
8c9f3aaf | 7815 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7816 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7817 | |
7818 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7819 | intel_ring_advance(ring); |
83d4092b CW |
7820 | return 0; |
7821 | ||
7822 | err_unpin: | |
7823 | intel_unpin_fb_obj(obj); | |
7824 | err: | |
8c9f3aaf JB |
7825 | return ret; |
7826 | } | |
7827 | ||
7c9017e5 JB |
7828 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7829 | struct drm_crtc *crtc, | |
7830 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7831 | struct drm_i915_gem_object *obj, |
7832 | uint32_t flags) | |
7c9017e5 JB |
7833 | { |
7834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 7836 | struct intel_ring_buffer *ring; |
cb05d8de | 7837 | uint32_t plane_bit = 0; |
ffe74d75 CW |
7838 | int len, ret; |
7839 | ||
7840 | ring = obj->ring; | |
1c5fd085 | 7841 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 7842 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
7843 | |
7844 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7845 | if (ret) | |
83d4092b | 7846 | goto err; |
7c9017e5 | 7847 | |
cb05d8de DV |
7848 | switch(intel_crtc->plane) { |
7849 | case PLANE_A: | |
7850 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
7851 | break; | |
7852 | case PLANE_B: | |
7853 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
7854 | break; | |
7855 | case PLANE_C: | |
7856 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
7857 | break; | |
7858 | default: | |
7859 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
7860 | ret = -ENODEV; | |
ab3951eb | 7861 | goto err_unpin; |
cb05d8de DV |
7862 | } |
7863 | ||
ffe74d75 CW |
7864 | len = 4; |
7865 | if (ring->id == RCS) | |
7866 | len += 6; | |
7867 | ||
7868 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 7869 | if (ret) |
83d4092b | 7870 | goto err_unpin; |
7c9017e5 | 7871 | |
ffe74d75 CW |
7872 | /* Unmask the flip-done completion message. Note that the bspec says that |
7873 | * we should do this for both the BCS and RCS, and that we must not unmask | |
7874 | * more than one flip event at any time (or ensure that one flip message | |
7875 | * can be sent by waiting for flip-done prior to queueing new flips). | |
7876 | * Experimentation says that BCS works despite DERRMR masking all | |
7877 | * flip-done completion events and that unmasking all planes at once | |
7878 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
7879 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
7880 | */ | |
7881 | if (ring->id == RCS) { | |
7882 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
7883 | intel_ring_emit(ring, DERRMR); | |
7884 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
7885 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
7886 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
7887 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
7888 | intel_ring_emit(ring, DERRMR); | |
7889 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
7890 | } | |
7891 | ||
cb05d8de | 7892 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 7893 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 7894 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 7895 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
7896 | |
7897 | intel_mark_page_flip_active(intel_crtc); | |
7c9017e5 | 7898 | intel_ring_advance(ring); |
83d4092b CW |
7899 | return 0; |
7900 | ||
7901 | err_unpin: | |
7902 | intel_unpin_fb_obj(obj); | |
7903 | err: | |
7c9017e5 JB |
7904 | return ret; |
7905 | } | |
7906 | ||
8c9f3aaf JB |
7907 | static int intel_default_queue_flip(struct drm_device *dev, |
7908 | struct drm_crtc *crtc, | |
7909 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7910 | struct drm_i915_gem_object *obj, |
7911 | uint32_t flags) | |
8c9f3aaf JB |
7912 | { |
7913 | return -ENODEV; | |
7914 | } | |
7915 | ||
6b95a207 KH |
7916 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7917 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7918 | struct drm_pending_vblank_event *event, |
7919 | uint32_t page_flip_flags) | |
6b95a207 KH |
7920 | { |
7921 | struct drm_device *dev = crtc->dev; | |
7922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
7923 | struct drm_framebuffer *old_fb = crtc->fb; |
7924 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
7925 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7926 | struct intel_unpin_work *work; | |
8c9f3aaf | 7927 | unsigned long flags; |
52e68630 | 7928 | int ret; |
6b95a207 | 7929 | |
e6a595d2 VS |
7930 | /* Can't change pixel format via MI display flips. */ |
7931 | if (fb->pixel_format != crtc->fb->pixel_format) | |
7932 | return -EINVAL; | |
7933 | ||
7934 | /* | |
7935 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
7936 | * Note that pitch changes could also affect these register. | |
7937 | */ | |
7938 | if (INTEL_INFO(dev)->gen > 3 && | |
7939 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
7940 | fb->pitches[0] != crtc->fb->pitches[0])) | |
7941 | return -EINVAL; | |
7942 | ||
6b95a207 KH |
7943 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7944 | if (work == NULL) | |
7945 | return -ENOMEM; | |
7946 | ||
6b95a207 | 7947 | work->event = event; |
b4a98e57 | 7948 | work->crtc = crtc; |
4a35f83b | 7949 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
7950 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7951 | ||
7317c75e JB |
7952 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7953 | if (ret) | |
7954 | goto free_work; | |
7955 | ||
6b95a207 KH |
7956 | /* We borrow the event spin lock for protecting unpin_work */ |
7957 | spin_lock_irqsave(&dev->event_lock, flags); | |
7958 | if (intel_crtc->unpin_work) { | |
7959 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7960 | kfree(work); | |
7317c75e | 7961 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7962 | |
7963 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7964 | return -EBUSY; |
7965 | } | |
7966 | intel_crtc->unpin_work = work; | |
7967 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7968 | ||
b4a98e57 CW |
7969 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7970 | flush_workqueue(dev_priv->wq); | |
7971 | ||
79158103 CW |
7972 | ret = i915_mutex_lock_interruptible(dev); |
7973 | if (ret) | |
7974 | goto cleanup; | |
6b95a207 | 7975 | |
75dfca80 | 7976 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7977 | drm_gem_object_reference(&work->old_fb_obj->base); |
7978 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7979 | |
7980 | crtc->fb = fb; | |
96b099fd | 7981 | |
e1f99ce6 | 7982 | work->pending_flip_obj = obj; |
e1f99ce6 | 7983 | |
4e5359cd SF |
7984 | work->enable_stall_check = true; |
7985 | ||
b4a98e57 | 7986 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 7987 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 7988 | |
ed8d1975 | 7989 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
7990 | if (ret) |
7991 | goto cleanup_pending; | |
6b95a207 | 7992 | |
7782de3b | 7993 | intel_disable_fbc(dev); |
c65355bb | 7994 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
7995 | mutex_unlock(&dev->struct_mutex); |
7996 | ||
e5510fac JB |
7997 | trace_i915_flip_request(intel_crtc->plane, obj); |
7998 | ||
6b95a207 | 7999 | return 0; |
96b099fd | 8000 | |
8c9f3aaf | 8001 | cleanup_pending: |
b4a98e57 | 8002 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8003 | crtc->fb = old_fb; |
05394f39 CW |
8004 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8005 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8006 | mutex_unlock(&dev->struct_mutex); |
8007 | ||
79158103 | 8008 | cleanup: |
96b099fd CW |
8009 | spin_lock_irqsave(&dev->event_lock, flags); |
8010 | intel_crtc->unpin_work = NULL; | |
8011 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8012 | ||
7317c75e JB |
8013 | drm_vblank_put(dev, intel_crtc->pipe); |
8014 | free_work: | |
96b099fd CW |
8015 | kfree(work); |
8016 | ||
8017 | return ret; | |
6b95a207 KH |
8018 | } |
8019 | ||
f6e5b160 | 8020 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8021 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8022 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8023 | }; |
8024 | ||
50f56119 DV |
8025 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8026 | struct drm_crtc *crtc) | |
8027 | { | |
8028 | struct drm_device *dev; | |
8029 | struct drm_crtc *tmp; | |
8030 | int crtc_mask = 1; | |
47f1c6c9 | 8031 | |
50f56119 | 8032 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8033 | |
50f56119 | 8034 | dev = crtc->dev; |
47f1c6c9 | 8035 | |
50f56119 DV |
8036 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8037 | if (tmp == crtc) | |
8038 | break; | |
8039 | crtc_mask <<= 1; | |
8040 | } | |
47f1c6c9 | 8041 | |
50f56119 DV |
8042 | if (encoder->possible_crtcs & crtc_mask) |
8043 | return true; | |
8044 | return false; | |
47f1c6c9 | 8045 | } |
79e53945 | 8046 | |
9a935856 DV |
8047 | /** |
8048 | * intel_modeset_update_staged_output_state | |
8049 | * | |
8050 | * Updates the staged output configuration state, e.g. after we've read out the | |
8051 | * current hw state. | |
8052 | */ | |
8053 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8054 | { |
9a935856 DV |
8055 | struct intel_encoder *encoder; |
8056 | struct intel_connector *connector; | |
f6e5b160 | 8057 | |
9a935856 DV |
8058 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8059 | base.head) { | |
8060 | connector->new_encoder = | |
8061 | to_intel_encoder(connector->base.encoder); | |
8062 | } | |
f6e5b160 | 8063 | |
9a935856 DV |
8064 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8065 | base.head) { | |
8066 | encoder->new_crtc = | |
8067 | to_intel_crtc(encoder->base.crtc); | |
8068 | } | |
f6e5b160 CW |
8069 | } |
8070 | ||
9a935856 DV |
8071 | /** |
8072 | * intel_modeset_commit_output_state | |
8073 | * | |
8074 | * This function copies the stage display pipe configuration to the real one. | |
8075 | */ | |
8076 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8077 | { | |
8078 | struct intel_encoder *encoder; | |
8079 | struct intel_connector *connector; | |
f6e5b160 | 8080 | |
9a935856 DV |
8081 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8082 | base.head) { | |
8083 | connector->base.encoder = &connector->new_encoder->base; | |
8084 | } | |
f6e5b160 | 8085 | |
9a935856 DV |
8086 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8087 | base.head) { | |
8088 | encoder->base.crtc = &encoder->new_crtc->base; | |
8089 | } | |
8090 | } | |
8091 | ||
050f7aeb DV |
8092 | static void |
8093 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8094 | struct intel_crtc_config *pipe_config) | |
8095 | { | |
8096 | int bpp = pipe_config->pipe_bpp; | |
8097 | ||
8098 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8099 | connector->base.base.id, | |
8100 | drm_get_connector_name(&connector->base)); | |
8101 | ||
8102 | /* Don't use an invalid EDID bpc value */ | |
8103 | if (connector->base.display_info.bpc && | |
8104 | connector->base.display_info.bpc * 3 < bpp) { | |
8105 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8106 | bpp, connector->base.display_info.bpc*3); | |
8107 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8108 | } | |
8109 | ||
8110 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8111 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8112 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8113 | bpp); | |
8114 | pipe_config->pipe_bpp = 24; | |
8115 | } | |
8116 | } | |
8117 | ||
4e53c2e0 | 8118 | static int |
050f7aeb DV |
8119 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8120 | struct drm_framebuffer *fb, | |
8121 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8122 | { |
050f7aeb DV |
8123 | struct drm_device *dev = crtc->base.dev; |
8124 | struct intel_connector *connector; | |
4e53c2e0 DV |
8125 | int bpp; |
8126 | ||
d42264b1 DV |
8127 | switch (fb->pixel_format) { |
8128 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8129 | bpp = 8*3; /* since we go through a colormap */ |
8130 | break; | |
d42264b1 DV |
8131 | case DRM_FORMAT_XRGB1555: |
8132 | case DRM_FORMAT_ARGB1555: | |
8133 | /* checked in intel_framebuffer_init already */ | |
8134 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8135 | return -EINVAL; | |
8136 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8137 | bpp = 6*3; /* min is 18bpp */ |
8138 | break; | |
d42264b1 DV |
8139 | case DRM_FORMAT_XBGR8888: |
8140 | case DRM_FORMAT_ABGR8888: | |
8141 | /* checked in intel_framebuffer_init already */ | |
8142 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8143 | return -EINVAL; | |
8144 | case DRM_FORMAT_XRGB8888: | |
8145 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8146 | bpp = 8*3; |
8147 | break; | |
d42264b1 DV |
8148 | case DRM_FORMAT_XRGB2101010: |
8149 | case DRM_FORMAT_ARGB2101010: | |
8150 | case DRM_FORMAT_XBGR2101010: | |
8151 | case DRM_FORMAT_ABGR2101010: | |
8152 | /* checked in intel_framebuffer_init already */ | |
8153 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8154 | return -EINVAL; |
4e53c2e0 DV |
8155 | bpp = 10*3; |
8156 | break; | |
baba133a | 8157 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8158 | default: |
8159 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8160 | return -EINVAL; | |
8161 | } | |
8162 | ||
4e53c2e0 DV |
8163 | pipe_config->pipe_bpp = bpp; |
8164 | ||
8165 | /* Clamp display bpp to EDID value */ | |
8166 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8167 | base.head) { |
1b829e05 DV |
8168 | if (!connector->new_encoder || |
8169 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8170 | continue; |
8171 | ||
050f7aeb | 8172 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8173 | } |
8174 | ||
8175 | return bpp; | |
8176 | } | |
8177 | ||
c0b03411 DV |
8178 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8179 | struct intel_crtc_config *pipe_config, | |
8180 | const char *context) | |
8181 | { | |
8182 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8183 | context, pipe_name(crtc->pipe)); | |
8184 | ||
8185 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8186 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8187 | pipe_config->pipe_bpp, pipe_config->dither); | |
8188 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8189 | pipe_config->has_pch_encoder, | |
8190 | pipe_config->fdi_lanes, | |
8191 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8192 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8193 | pipe_config->fdi_m_n.tu); | |
8194 | DRM_DEBUG_KMS("requested mode:\n"); | |
8195 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8196 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8197 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
8198 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
8199 | pipe_config->gmch_pfit.control, | |
8200 | pipe_config->gmch_pfit.pgm_ratios, | |
8201 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8202 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8203 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8204 | pipe_config->pch_pfit.size, |
8205 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8206 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
c0b03411 DV |
8207 | } |
8208 | ||
accfc0c5 DV |
8209 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8210 | { | |
8211 | int num_encoders = 0; | |
8212 | bool uncloneable_encoders = false; | |
8213 | struct intel_encoder *encoder; | |
8214 | ||
8215 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8216 | base.head) { | |
8217 | if (&encoder->new_crtc->base != crtc) | |
8218 | continue; | |
8219 | ||
8220 | num_encoders++; | |
8221 | if (!encoder->cloneable) | |
8222 | uncloneable_encoders = true; | |
8223 | } | |
8224 | ||
8225 | return !(num_encoders > 1 && uncloneable_encoders); | |
8226 | } | |
8227 | ||
b8cecdf5 DV |
8228 | static struct intel_crtc_config * |
8229 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8230 | struct drm_framebuffer *fb, |
b8cecdf5 | 8231 | struct drm_display_mode *mode) |
ee7b9f93 | 8232 | { |
7758a113 | 8233 | struct drm_device *dev = crtc->dev; |
7758a113 | 8234 | struct intel_encoder *encoder; |
b8cecdf5 | 8235 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8236 | int plane_bpp, ret = -EINVAL; |
8237 | bool retry = true; | |
ee7b9f93 | 8238 | |
accfc0c5 DV |
8239 | if (!check_encoder_cloning(crtc)) { |
8240 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8241 | return ERR_PTR(-EINVAL); | |
8242 | } | |
8243 | ||
b8cecdf5 DV |
8244 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8245 | if (!pipe_config) | |
7758a113 DV |
8246 | return ERR_PTR(-ENOMEM); |
8247 | ||
b8cecdf5 DV |
8248 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8249 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
e143a21c DV |
8250 | pipe_config->cpu_transcoder = |
8251 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8252 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8253 | |
2960bc9c ID |
8254 | /* |
8255 | * Sanitize sync polarity flags based on requested ones. If neither | |
8256 | * positive or negative polarity is requested, treat this as meaning | |
8257 | * negative polarity. | |
8258 | */ | |
8259 | if (!(pipe_config->adjusted_mode.flags & | |
8260 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8261 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8262 | ||
8263 | if (!(pipe_config->adjusted_mode.flags & | |
8264 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8265 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8266 | ||
050f7aeb DV |
8267 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8268 | * plane pixel format and any sink constraints into account. Returns the | |
8269 | * source plane bpp so that dithering can be selected on mismatches | |
8270 | * after encoders and crtc also have had their say. */ | |
8271 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8272 | fb, pipe_config); | |
4e53c2e0 DV |
8273 | if (plane_bpp < 0) |
8274 | goto fail; | |
8275 | ||
e29c22c0 | 8276 | encoder_retry: |
ef1b460d | 8277 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8278 | pipe_config->port_clock = 0; |
ef1b460d | 8279 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8280 | |
135c81b8 DV |
8281 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8282 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); | |
8283 | ||
7758a113 DV |
8284 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8285 | * adjust it according to limitations or connector properties, and also | |
8286 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8287 | */ |
7758a113 DV |
8288 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8289 | base.head) { | |
47f1c6c9 | 8290 | |
7758a113 DV |
8291 | if (&encoder->new_crtc->base != crtc) |
8292 | continue; | |
7ae89233 | 8293 | |
efea6e8e DV |
8294 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8295 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
8296 | goto fail; |
8297 | } | |
ee7b9f93 | 8298 | } |
47f1c6c9 | 8299 | |
ff9a6750 DV |
8300 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8301 | * done afterwards in case the encoder adjusts the mode. */ | |
8302 | if (!pipe_config->port_clock) | |
8303 | pipe_config->port_clock = pipe_config->adjusted_mode.clock; | |
8304 | ||
a43f6e0f | 8305 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 8306 | if (ret < 0) { |
7758a113 DV |
8307 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8308 | goto fail; | |
ee7b9f93 | 8309 | } |
e29c22c0 DV |
8310 | |
8311 | if (ret == RETRY) { | |
8312 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
8313 | ret = -EINVAL; | |
8314 | goto fail; | |
8315 | } | |
8316 | ||
8317 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
8318 | retry = false; | |
8319 | goto encoder_retry; | |
8320 | } | |
8321 | ||
4e53c2e0 DV |
8322 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8323 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
8324 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
8325 | ||
b8cecdf5 | 8326 | return pipe_config; |
7758a113 | 8327 | fail: |
b8cecdf5 | 8328 | kfree(pipe_config); |
e29c22c0 | 8329 | return ERR_PTR(ret); |
ee7b9f93 | 8330 | } |
47f1c6c9 | 8331 | |
e2e1ed41 DV |
8332 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8333 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
8334 | static void | |
8335 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
8336 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
8337 | { |
8338 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
8339 | struct drm_device *dev = crtc->dev; |
8340 | struct intel_encoder *encoder; | |
8341 | struct intel_connector *connector; | |
8342 | struct drm_crtc *tmp_crtc; | |
79e53945 | 8343 | |
e2e1ed41 | 8344 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 8345 | |
e2e1ed41 DV |
8346 | /* Check which crtcs have changed outputs connected to them, these need |
8347 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
8348 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
8349 | * bit set at most. */ | |
8350 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8351 | base.head) { | |
8352 | if (connector->base.encoder == &connector->new_encoder->base) | |
8353 | continue; | |
79e53945 | 8354 | |
e2e1ed41 DV |
8355 | if (connector->base.encoder) { |
8356 | tmp_crtc = connector->base.encoder->crtc; | |
8357 | ||
8358 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8359 | } | |
8360 | ||
8361 | if (connector->new_encoder) | |
8362 | *prepare_pipes |= | |
8363 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
8364 | } |
8365 | ||
e2e1ed41 DV |
8366 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8367 | base.head) { | |
8368 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
8369 | continue; | |
8370 | ||
8371 | if (encoder->base.crtc) { | |
8372 | tmp_crtc = encoder->base.crtc; | |
8373 | ||
8374 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8375 | } | |
8376 | ||
8377 | if (encoder->new_crtc) | |
8378 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
8379 | } |
8380 | ||
e2e1ed41 DV |
8381 | /* Check for any pipes that will be fully disabled ... */ |
8382 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8383 | base.head) { | |
8384 | bool used = false; | |
22fd0fab | 8385 | |
e2e1ed41 DV |
8386 | /* Don't try to disable disabled crtcs. */ |
8387 | if (!intel_crtc->base.enabled) | |
8388 | continue; | |
7e7d76c3 | 8389 | |
e2e1ed41 DV |
8390 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8391 | base.head) { | |
8392 | if (encoder->new_crtc == intel_crtc) | |
8393 | used = true; | |
8394 | } | |
8395 | ||
8396 | if (!used) | |
8397 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
8398 | } |
8399 | ||
e2e1ed41 DV |
8400 | |
8401 | /* set_mode is also used to update properties on life display pipes. */ | |
8402 | intel_crtc = to_intel_crtc(crtc); | |
8403 | if (crtc->enabled) | |
8404 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
8405 | ||
b6c5164d DV |
8406 | /* |
8407 | * For simplicity do a full modeset on any pipe where the output routing | |
8408 | * changed. We could be more clever, but that would require us to be | |
8409 | * more careful with calling the relevant encoder->mode_set functions. | |
8410 | */ | |
e2e1ed41 DV |
8411 | if (*prepare_pipes) |
8412 | *modeset_pipes = *prepare_pipes; | |
8413 | ||
8414 | /* ... and mask these out. */ | |
8415 | *modeset_pipes &= ~(*disable_pipes); | |
8416 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
8417 | |
8418 | /* | |
8419 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
8420 | * obies this rule, but the modeset restore mode of | |
8421 | * intel_modeset_setup_hw_state does not. | |
8422 | */ | |
8423 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
8424 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
8425 | |
8426 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
8427 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 8428 | } |
79e53945 | 8429 | |
ea9d758d | 8430 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 8431 | { |
ea9d758d | 8432 | struct drm_encoder *encoder; |
f6e5b160 | 8433 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 8434 | |
ea9d758d DV |
8435 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8436 | if (encoder->crtc == crtc) | |
8437 | return true; | |
8438 | ||
8439 | return false; | |
8440 | } | |
8441 | ||
8442 | static void | |
8443 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
8444 | { | |
8445 | struct intel_encoder *intel_encoder; | |
8446 | struct intel_crtc *intel_crtc; | |
8447 | struct drm_connector *connector; | |
8448 | ||
8449 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
8450 | base.head) { | |
8451 | if (!intel_encoder->base.crtc) | |
8452 | continue; | |
8453 | ||
8454 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
8455 | ||
8456 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
8457 | intel_encoder->connectors_active = false; | |
8458 | } | |
8459 | ||
8460 | intel_modeset_commit_output_state(dev); | |
8461 | ||
8462 | /* Update computed state. */ | |
8463 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8464 | base.head) { | |
8465 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
8466 | } | |
8467 | ||
8468 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
8469 | if (!connector->encoder || !connector->encoder->crtc) | |
8470 | continue; | |
8471 | ||
8472 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
8473 | ||
8474 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
8475 | struct drm_property *dpms_property = |
8476 | dev->mode_config.dpms_property; | |
8477 | ||
ea9d758d | 8478 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 8479 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
8480 | dpms_property, |
8481 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
8482 | |
8483 | intel_encoder = to_intel_encoder(connector->encoder); | |
8484 | intel_encoder->connectors_active = true; | |
8485 | } | |
8486 | } | |
8487 | ||
8488 | } | |
8489 | ||
f1f644dc JB |
8490 | static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur, |
8491 | struct intel_crtc_config *new) | |
8492 | { | |
8493 | int clock1, clock2, diff; | |
8494 | ||
8495 | clock1 = cur->adjusted_mode.clock; | |
8496 | clock2 = new->adjusted_mode.clock; | |
8497 | ||
8498 | if (clock1 == clock2) | |
8499 | return true; | |
8500 | ||
8501 | if (!clock1 || !clock2) | |
8502 | return false; | |
8503 | ||
8504 | diff = abs(clock1 - clock2); | |
8505 | ||
8506 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
8507 | return true; | |
8508 | ||
8509 | return false; | |
8510 | } | |
8511 | ||
25c5b266 DV |
8512 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8513 | list_for_each_entry((intel_crtc), \ | |
8514 | &(dev)->mode_config.crtc_list, \ | |
8515 | base.head) \ | |
0973f18f | 8516 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 8517 | |
0e8ffe1b | 8518 | static bool |
2fa2fe9a DV |
8519 | intel_pipe_config_compare(struct drm_device *dev, |
8520 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
8521 | struct intel_crtc_config *pipe_config) |
8522 | { | |
66e985c0 DV |
8523 | #define PIPE_CONF_CHECK_X(name) \ |
8524 | if (current_config->name != pipe_config->name) { \ | |
8525 | DRM_ERROR("mismatch in " #name " " \ | |
8526 | "(expected 0x%08x, found 0x%08x)\n", \ | |
8527 | current_config->name, \ | |
8528 | pipe_config->name); \ | |
8529 | return false; \ | |
8530 | } | |
8531 | ||
08a24034 DV |
8532 | #define PIPE_CONF_CHECK_I(name) \ |
8533 | if (current_config->name != pipe_config->name) { \ | |
8534 | DRM_ERROR("mismatch in " #name " " \ | |
8535 | "(expected %i, found %i)\n", \ | |
8536 | current_config->name, \ | |
8537 | pipe_config->name); \ | |
8538 | return false; \ | |
88adfff1 DV |
8539 | } |
8540 | ||
1bd1bd80 DV |
8541 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8542 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 8543 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
8544 | "(expected %i, found %i)\n", \ |
8545 | current_config->name & (mask), \ | |
8546 | pipe_config->name & (mask)); \ | |
8547 | return false; \ | |
8548 | } | |
8549 | ||
bb760063 DV |
8550 | #define PIPE_CONF_QUIRK(quirk) \ |
8551 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
8552 | ||
eccb140b DV |
8553 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8554 | ||
08a24034 DV |
8555 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8556 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
8557 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8558 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
8559 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
8560 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
8561 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 8562 | |
1bd1bd80 DV |
8563 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8564 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
8565 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
8566 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
8567 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
8568 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
8569 | ||
8570 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
8571 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
8572 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
8573 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
8574 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
8575 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
8576 | ||
c93f54cf | 8577 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 8578 | |
1bd1bd80 DV |
8579 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8580 | DRM_MODE_FLAG_INTERLACE); | |
8581 | ||
bb760063 DV |
8582 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8583 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8584 | DRM_MODE_FLAG_PHSYNC); | |
8585 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8586 | DRM_MODE_FLAG_NHSYNC); | |
8587 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8588 | DRM_MODE_FLAG_PVSYNC); | |
8589 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8590 | DRM_MODE_FLAG_NVSYNC); | |
8591 | } | |
045ac3b5 | 8592 | |
1bd1bd80 DV |
8593 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); |
8594 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); | |
8595 | ||
2fa2fe9a DV |
8596 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8597 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
8598 | if (INTEL_INFO(dev)->gen < 4) | |
8599 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
8600 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
8601 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8602 | if (current_config->pch_pfit.enabled) { | |
8603 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
8604 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
8605 | } | |
2fa2fe9a | 8606 | |
42db64ef PZ |
8607 | PIPE_CONF_CHECK_I(ips_enabled); |
8608 | ||
c0d43d62 | 8609 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 8610 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 8611 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
8612 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8613 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 8614 | |
66e985c0 | 8615 | #undef PIPE_CONF_CHECK_X |
08a24034 | 8616 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 8617 | #undef PIPE_CONF_CHECK_FLAGS |
bb760063 | 8618 | #undef PIPE_CONF_QUIRK |
88adfff1 | 8619 | |
f1f644dc JB |
8620 | if (!IS_HASWELL(dev)) { |
8621 | if (!intel_fuzzy_clock_check(current_config, pipe_config)) { | |
6f02488e | 8622 | DRM_ERROR("mismatch in clock (expected %d, found %d)\n", |
f1f644dc JB |
8623 | current_config->adjusted_mode.clock, |
8624 | pipe_config->adjusted_mode.clock); | |
8625 | return false; | |
8626 | } | |
8627 | } | |
8628 | ||
0e8ffe1b DV |
8629 | return true; |
8630 | } | |
8631 | ||
91d1b4bd DV |
8632 | static void |
8633 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 8634 | { |
8af6cf88 DV |
8635 | struct intel_connector *connector; |
8636 | ||
8637 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8638 | base.head) { | |
8639 | /* This also checks the encoder/connector hw state with the | |
8640 | * ->get_hw_state callbacks. */ | |
8641 | intel_connector_check_state(connector); | |
8642 | ||
8643 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
8644 | "connector's staged encoder doesn't match current encoder\n"); | |
8645 | } | |
91d1b4bd DV |
8646 | } |
8647 | ||
8648 | static void | |
8649 | check_encoder_state(struct drm_device *dev) | |
8650 | { | |
8651 | struct intel_encoder *encoder; | |
8652 | struct intel_connector *connector; | |
8af6cf88 DV |
8653 | |
8654 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8655 | base.head) { | |
8656 | bool enabled = false; | |
8657 | bool active = false; | |
8658 | enum pipe pipe, tracked_pipe; | |
8659 | ||
8660 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
8661 | encoder->base.base.id, | |
8662 | drm_get_encoder_name(&encoder->base)); | |
8663 | ||
8664 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
8665 | "encoder's stage crtc doesn't match current crtc\n"); | |
8666 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
8667 | "encoder's active_connectors set, but no crtc\n"); | |
8668 | ||
8669 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8670 | base.head) { | |
8671 | if (connector->base.encoder != &encoder->base) | |
8672 | continue; | |
8673 | enabled = true; | |
8674 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
8675 | active = true; | |
8676 | } | |
8677 | WARN(!!encoder->base.crtc != enabled, | |
8678 | "encoder's enabled state mismatch " | |
8679 | "(expected %i, found %i)\n", | |
8680 | !!encoder->base.crtc, enabled); | |
8681 | WARN(active && !encoder->base.crtc, | |
8682 | "active encoder with no crtc\n"); | |
8683 | ||
8684 | WARN(encoder->connectors_active != active, | |
8685 | "encoder's computed active state doesn't match tracked active state " | |
8686 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
8687 | ||
8688 | active = encoder->get_hw_state(encoder, &pipe); | |
8689 | WARN(active != encoder->connectors_active, | |
8690 | "encoder's hw state doesn't match sw tracking " | |
8691 | "(expected %i, found %i)\n", | |
8692 | encoder->connectors_active, active); | |
8693 | ||
8694 | if (!encoder->base.crtc) | |
8695 | continue; | |
8696 | ||
8697 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
8698 | WARN(active && pipe != tracked_pipe, | |
8699 | "active encoder's pipe doesn't match" | |
8700 | "(expected %i, found %i)\n", | |
8701 | tracked_pipe, pipe); | |
8702 | ||
8703 | } | |
91d1b4bd DV |
8704 | } |
8705 | ||
8706 | static void | |
8707 | check_crtc_state(struct drm_device *dev) | |
8708 | { | |
8709 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8710 | struct intel_crtc *crtc; | |
8711 | struct intel_encoder *encoder; | |
8712 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
8713 | |
8714 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8715 | base.head) { | |
8716 | bool enabled = false; | |
8717 | bool active = false; | |
8718 | ||
045ac3b5 JB |
8719 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8720 | ||
8af6cf88 DV |
8721 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8722 | crtc->base.base.id); | |
8723 | ||
8724 | WARN(crtc->active && !crtc->base.enabled, | |
8725 | "active crtc, but not enabled in sw tracking\n"); | |
8726 | ||
8727 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8728 | base.head) { | |
8729 | if (encoder->base.crtc != &crtc->base) | |
8730 | continue; | |
8731 | enabled = true; | |
8732 | if (encoder->connectors_active) | |
8733 | active = true; | |
8734 | } | |
6c49f241 | 8735 | |
8af6cf88 DV |
8736 | WARN(active != crtc->active, |
8737 | "crtc's computed active state doesn't match tracked active state " | |
8738 | "(expected %i, found %i)\n", active, crtc->active); | |
8739 | WARN(enabled != crtc->base.enabled, | |
8740 | "crtc's computed enabled state doesn't match tracked enabled state " | |
8741 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
8742 | ||
0e8ffe1b DV |
8743 | active = dev_priv->display.get_pipe_config(crtc, |
8744 | &pipe_config); | |
d62cf62a DV |
8745 | |
8746 | /* hw state is inconsistent with the pipe A quirk */ | |
8747 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
8748 | active = crtc->active; | |
8749 | ||
6c49f241 DV |
8750 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8751 | base.head) { | |
3eaba51c | 8752 | enum pipe pipe; |
6c49f241 DV |
8753 | if (encoder->base.crtc != &crtc->base) |
8754 | continue; | |
3eaba51c VS |
8755 | if (encoder->get_config && |
8756 | encoder->get_hw_state(encoder, &pipe)) | |
6c49f241 DV |
8757 | encoder->get_config(encoder, &pipe_config); |
8758 | } | |
8759 | ||
510d5f2f JB |
8760 | if (dev_priv->display.get_clock) |
8761 | dev_priv->display.get_clock(crtc, &pipe_config); | |
8762 | ||
0e8ffe1b DV |
8763 | WARN(crtc->active != active, |
8764 | "crtc active state doesn't match with hw state " | |
8765 | "(expected %i, found %i)\n", crtc->active, active); | |
8766 | ||
c0b03411 DV |
8767 | if (active && |
8768 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
8769 | WARN(1, "pipe state doesn't match!\n"); | |
8770 | intel_dump_pipe_config(crtc, &pipe_config, | |
8771 | "[hw state]"); | |
8772 | intel_dump_pipe_config(crtc, &crtc->config, | |
8773 | "[sw state]"); | |
8774 | } | |
8af6cf88 DV |
8775 | } |
8776 | } | |
8777 | ||
91d1b4bd DV |
8778 | static void |
8779 | check_shared_dpll_state(struct drm_device *dev) | |
8780 | { | |
8781 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8782 | struct intel_crtc *crtc; | |
8783 | struct intel_dpll_hw_state dpll_hw_state; | |
8784 | int i; | |
5358901f DV |
8785 | |
8786 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8787 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
8788 | int enabled_crtcs = 0, active_crtcs = 0; | |
8789 | bool active; | |
8790 | ||
8791 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
8792 | ||
8793 | DRM_DEBUG_KMS("%s\n", pll->name); | |
8794 | ||
8795 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
8796 | ||
8797 | WARN(pll->active > pll->refcount, | |
8798 | "more active pll users than references: %i vs %i\n", | |
8799 | pll->active, pll->refcount); | |
8800 | WARN(pll->active && !pll->on, | |
8801 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
8802 | WARN(pll->on && !pll->active, |
8803 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
8804 | WARN(pll->on != active, |
8805 | "pll on state mismatch (expected %i, found %i)\n", | |
8806 | pll->on, active); | |
8807 | ||
8808 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8809 | base.head) { | |
8810 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
8811 | enabled_crtcs++; | |
8812 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
8813 | active_crtcs++; | |
8814 | } | |
8815 | WARN(pll->active != active_crtcs, | |
8816 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
8817 | pll->active, active_crtcs); | |
8818 | WARN(pll->refcount != enabled_crtcs, | |
8819 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
8820 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
8821 | |
8822 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
8823 | sizeof(dpll_hw_state)), | |
8824 | "pll hw state mismatch\n"); | |
5358901f | 8825 | } |
8af6cf88 DV |
8826 | } |
8827 | ||
91d1b4bd DV |
8828 | void |
8829 | intel_modeset_check_state(struct drm_device *dev) | |
8830 | { | |
8831 | check_connector_state(dev); | |
8832 | check_encoder_state(dev); | |
8833 | check_crtc_state(dev); | |
8834 | check_shared_dpll_state(dev); | |
8835 | } | |
8836 | ||
f30da187 DV |
8837 | static int __intel_set_mode(struct drm_crtc *crtc, |
8838 | struct drm_display_mode *mode, | |
8839 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
8840 | { |
8841 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 8842 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
8843 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8844 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
8845 | struct intel_crtc *intel_crtc; |
8846 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 8847 | int ret = 0; |
a6778b3c | 8848 | |
3ac18232 | 8849 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
8850 | if (!saved_mode) |
8851 | return -ENOMEM; | |
3ac18232 | 8852 | saved_hwmode = saved_mode + 1; |
a6778b3c | 8853 | |
e2e1ed41 | 8854 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
8855 | &prepare_pipes, &disable_pipes); |
8856 | ||
3ac18232 TG |
8857 | *saved_hwmode = crtc->hwmode; |
8858 | *saved_mode = crtc->mode; | |
a6778b3c | 8859 | |
25c5b266 DV |
8860 | /* Hack: Because we don't (yet) support global modeset on multiple |
8861 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
8862 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
8863 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
8864 | * changing their mode at the same time. */ | |
25c5b266 | 8865 | if (modeset_pipes) { |
4e53c2e0 | 8866 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
8867 | if (IS_ERR(pipe_config)) { |
8868 | ret = PTR_ERR(pipe_config); | |
8869 | pipe_config = NULL; | |
8870 | ||
3ac18232 | 8871 | goto out; |
25c5b266 | 8872 | } |
c0b03411 DV |
8873 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
8874 | "[modeset]"); | |
25c5b266 | 8875 | } |
a6778b3c | 8876 | |
460da916 DV |
8877 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8878 | intel_crtc_disable(&intel_crtc->base); | |
8879 | ||
ea9d758d DV |
8880 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8881 | if (intel_crtc->base.enabled) | |
8882 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
8883 | } | |
a6778b3c | 8884 | |
6c4c86f5 DV |
8885 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8886 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 8887 | */ |
b8cecdf5 | 8888 | if (modeset_pipes) { |
25c5b266 | 8889 | crtc->mode = *mode; |
b8cecdf5 DV |
8890 | /* mode_set/enable/disable functions rely on a correct pipe |
8891 | * config. */ | |
8892 | to_intel_crtc(crtc)->config = *pipe_config; | |
8893 | } | |
7758a113 | 8894 | |
ea9d758d DV |
8895 | /* Only after disabling all output pipelines that will be changed can we |
8896 | * update the the output configuration. */ | |
8897 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 8898 | |
47fab737 DV |
8899 | if (dev_priv->display.modeset_global_resources) |
8900 | dev_priv->display.modeset_global_resources(dev); | |
8901 | ||
a6778b3c DV |
8902 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8903 | * on the DPLL. | |
f6e5b160 | 8904 | */ |
25c5b266 | 8905 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 8906 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
8907 | x, y, fb); |
8908 | if (ret) | |
8909 | goto done; | |
a6778b3c DV |
8910 | } |
8911 | ||
8912 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
8913 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8914 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 8915 | |
25c5b266 DV |
8916 | if (modeset_pipes) { |
8917 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 8918 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 8919 | |
25c5b266 DV |
8920 | /* Calculate and store various constants which |
8921 | * are later needed by vblank and swap-completion | |
8922 | * timestamping. They are derived from true hwmode. | |
8923 | */ | |
8924 | drm_calc_timestamping_constants(crtc); | |
8925 | } | |
a6778b3c DV |
8926 | |
8927 | /* FIXME: add subpixel order */ | |
8928 | done: | |
c0c36b94 | 8929 | if (ret && crtc->enabled) { |
3ac18232 TG |
8930 | crtc->hwmode = *saved_hwmode; |
8931 | crtc->mode = *saved_mode; | |
a6778b3c DV |
8932 | } |
8933 | ||
3ac18232 | 8934 | out: |
b8cecdf5 | 8935 | kfree(pipe_config); |
3ac18232 | 8936 | kfree(saved_mode); |
a6778b3c | 8937 | return ret; |
f6e5b160 CW |
8938 | } |
8939 | ||
e7457a9a DL |
8940 | static int intel_set_mode(struct drm_crtc *crtc, |
8941 | struct drm_display_mode *mode, | |
8942 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
8943 | { |
8944 | int ret; | |
8945 | ||
8946 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
8947 | ||
8948 | if (ret == 0) | |
8949 | intel_modeset_check_state(crtc->dev); | |
8950 | ||
8951 | return ret; | |
8952 | } | |
8953 | ||
c0c36b94 CW |
8954 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
8955 | { | |
8956 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
8957 | } | |
8958 | ||
25c5b266 DV |
8959 | #undef for_each_intel_crtc_masked |
8960 | ||
d9e55608 DV |
8961 | static void intel_set_config_free(struct intel_set_config *config) |
8962 | { | |
8963 | if (!config) | |
8964 | return; | |
8965 | ||
1aa4b628 DV |
8966 | kfree(config->save_connector_encoders); |
8967 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
8968 | kfree(config); |
8969 | } | |
8970 | ||
85f9eb71 DV |
8971 | static int intel_set_config_save_state(struct drm_device *dev, |
8972 | struct intel_set_config *config) | |
8973 | { | |
85f9eb71 DV |
8974 | struct drm_encoder *encoder; |
8975 | struct drm_connector *connector; | |
8976 | int count; | |
8977 | ||
1aa4b628 DV |
8978 | config->save_encoder_crtcs = |
8979 | kcalloc(dev->mode_config.num_encoder, | |
8980 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
8981 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
8982 | return -ENOMEM; |
8983 | ||
1aa4b628 DV |
8984 | config->save_connector_encoders = |
8985 | kcalloc(dev->mode_config.num_connector, | |
8986 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
8987 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
8988 | return -ENOMEM; |
8989 | ||
8990 | /* Copy data. Note that driver private data is not affected. | |
8991 | * Should anything bad happen only the expected state is | |
8992 | * restored, not the drivers personal bookkeeping. | |
8993 | */ | |
85f9eb71 DV |
8994 | count = 0; |
8995 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 8996 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
8997 | } |
8998 | ||
8999 | count = 0; | |
9000 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9001 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9002 | } |
9003 | ||
9004 | return 0; | |
9005 | } | |
9006 | ||
9007 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9008 | struct intel_set_config *config) | |
9009 | { | |
9a935856 DV |
9010 | struct intel_encoder *encoder; |
9011 | struct intel_connector *connector; | |
85f9eb71 DV |
9012 | int count; |
9013 | ||
85f9eb71 | 9014 | count = 0; |
9a935856 DV |
9015 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9016 | encoder->new_crtc = | |
9017 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9018 | } |
9019 | ||
9020 | count = 0; | |
9a935856 DV |
9021 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9022 | connector->new_encoder = | |
9023 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9024 | } |
9025 | } | |
9026 | ||
e3de42b6 | 9027 | static bool |
2e57f47d | 9028 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9029 | { |
9030 | int i; | |
9031 | ||
2e57f47d CW |
9032 | if (set->num_connectors == 0) |
9033 | return false; | |
9034 | ||
9035 | if (WARN_ON(set->connectors == NULL)) | |
9036 | return false; | |
9037 | ||
9038 | for (i = 0; i < set->num_connectors; i++) | |
9039 | if (set->connectors[i]->encoder && | |
9040 | set->connectors[i]->encoder->crtc == set->crtc && | |
9041 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9042 | return true; |
9043 | ||
9044 | return false; | |
9045 | } | |
9046 | ||
5e2b584e DV |
9047 | static void |
9048 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9049 | struct intel_set_config *config) | |
9050 | { | |
9051 | ||
9052 | /* We should be able to check here if the fb has the same properties | |
9053 | * and then just flip_or_move it */ | |
2e57f47d CW |
9054 | if (is_crtc_connector_off(set)) { |
9055 | config->mode_changed = true; | |
e3de42b6 | 9056 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9057 | /* If we have no fb then treat it as a full mode set */ |
9058 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9059 | struct intel_crtc *intel_crtc = |
9060 | to_intel_crtc(set->crtc); | |
9061 | ||
9062 | if (intel_crtc->active && i915_fastboot) { | |
9063 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9064 | config->fb_changed = true; | |
9065 | } else { | |
9066 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9067 | config->mode_changed = true; | |
9068 | } | |
5e2b584e DV |
9069 | } else if (set->fb == NULL) { |
9070 | config->mode_changed = true; | |
72f4901e DV |
9071 | } else if (set->fb->pixel_format != |
9072 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9073 | config->mode_changed = true; |
e3de42b6 | 9074 | } else { |
5e2b584e | 9075 | config->fb_changed = true; |
e3de42b6 | 9076 | } |
5e2b584e DV |
9077 | } |
9078 | ||
835c5873 | 9079 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9080 | config->fb_changed = true; |
9081 | ||
9082 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9083 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9084 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9085 | drm_mode_debug_printmodeline(set->mode); | |
9086 | config->mode_changed = true; | |
9087 | } | |
a1d95703 CW |
9088 | |
9089 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9090 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9091 | } |
9092 | ||
2e431051 | 9093 | static int |
9a935856 DV |
9094 | intel_modeset_stage_output_state(struct drm_device *dev, |
9095 | struct drm_mode_set *set, | |
9096 | struct intel_set_config *config) | |
50f56119 | 9097 | { |
85f9eb71 | 9098 | struct drm_crtc *new_crtc; |
9a935856 DV |
9099 | struct intel_connector *connector; |
9100 | struct intel_encoder *encoder; | |
f3f08572 | 9101 | int ro; |
50f56119 | 9102 | |
9abdda74 | 9103 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9104 | * of connectors. For paranoia, double-check this. */ |
9105 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9106 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9107 | ||
9a935856 DV |
9108 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9109 | base.head) { | |
9110 | /* Otherwise traverse passed in connector list and get encoders | |
9111 | * for them. */ | |
50f56119 | 9112 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9113 | if (set->connectors[ro] == &connector->base) { |
9114 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9115 | break; |
9116 | } | |
9117 | } | |
9118 | ||
9a935856 DV |
9119 | /* If we disable the crtc, disable all its connectors. Also, if |
9120 | * the connector is on the changing crtc but not on the new | |
9121 | * connector list, disable it. */ | |
9122 | if ((!set->fb || ro == set->num_connectors) && | |
9123 | connector->base.encoder && | |
9124 | connector->base.encoder->crtc == set->crtc) { | |
9125 | connector->new_encoder = NULL; | |
9126 | ||
9127 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9128 | connector->base.base.id, | |
9129 | drm_get_connector_name(&connector->base)); | |
9130 | } | |
9131 | ||
9132 | ||
9133 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9134 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9135 | config->mode_changed = true; |
50f56119 DV |
9136 | } |
9137 | } | |
9a935856 | 9138 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9139 | |
9a935856 | 9140 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9141 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9142 | base.head) { | |
9143 | if (!connector->new_encoder) | |
50f56119 DV |
9144 | continue; |
9145 | ||
9a935856 | 9146 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9147 | |
9148 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9149 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9150 | new_crtc = set->crtc; |
9151 | } | |
9152 | ||
9153 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9154 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9155 | new_crtc)) { | |
5e2b584e | 9156 | return -EINVAL; |
50f56119 | 9157 | } |
9a935856 DV |
9158 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9159 | ||
9160 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9161 | connector->base.base.id, | |
9162 | drm_get_connector_name(&connector->base), | |
9163 | new_crtc->base.id); | |
9164 | } | |
9165 | ||
9166 | /* Check for any encoders that needs to be disabled. */ | |
9167 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9168 | base.head) { | |
9169 | list_for_each_entry(connector, | |
9170 | &dev->mode_config.connector_list, | |
9171 | base.head) { | |
9172 | if (connector->new_encoder == encoder) { | |
9173 | WARN_ON(!connector->new_encoder->new_crtc); | |
9174 | ||
9175 | goto next_encoder; | |
9176 | } | |
9177 | } | |
9178 | encoder->new_crtc = NULL; | |
9179 | next_encoder: | |
9180 | /* Only now check for crtc changes so we don't miss encoders | |
9181 | * that will be disabled. */ | |
9182 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9183 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9184 | config->mode_changed = true; |
50f56119 DV |
9185 | } |
9186 | } | |
9a935856 | 9187 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9188 | |
2e431051 DV |
9189 | return 0; |
9190 | } | |
9191 | ||
9192 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9193 | { | |
9194 | struct drm_device *dev; | |
2e431051 DV |
9195 | struct drm_mode_set save_set; |
9196 | struct intel_set_config *config; | |
9197 | int ret; | |
2e431051 | 9198 | |
8d3e375e DV |
9199 | BUG_ON(!set); |
9200 | BUG_ON(!set->crtc); | |
9201 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9202 | |
7e53f3a4 DV |
9203 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9204 | BUG_ON(!set->mode && set->fb); | |
9205 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9206 | |
2e431051 DV |
9207 | if (set->fb) { |
9208 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9209 | set->crtc->base.id, set->fb->base.id, | |
9210 | (int)set->num_connectors, set->x, set->y); | |
9211 | } else { | |
9212 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9213 | } |
9214 | ||
9215 | dev = set->crtc->dev; | |
9216 | ||
9217 | ret = -ENOMEM; | |
9218 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9219 | if (!config) | |
9220 | goto out_config; | |
9221 | ||
9222 | ret = intel_set_config_save_state(dev, config); | |
9223 | if (ret) | |
9224 | goto out_config; | |
9225 | ||
9226 | save_set.crtc = set->crtc; | |
9227 | save_set.mode = &set->crtc->mode; | |
9228 | save_set.x = set->crtc->x; | |
9229 | save_set.y = set->crtc->y; | |
9230 | save_set.fb = set->crtc->fb; | |
9231 | ||
9232 | /* Compute whether we need a full modeset, only an fb base update or no | |
9233 | * change at all. In the future we might also check whether only the | |
9234 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9235 | * such cases. */ | |
9236 | intel_set_config_compute_mode_changes(set, config); | |
9237 | ||
9a935856 | 9238 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9239 | if (ret) |
9240 | goto fail; | |
9241 | ||
5e2b584e | 9242 | if (config->mode_changed) { |
c0c36b94 CW |
9243 | ret = intel_set_mode(set->crtc, set->mode, |
9244 | set->x, set->y, set->fb); | |
5e2b584e | 9245 | } else if (config->fb_changed) { |
4878cae2 VS |
9246 | intel_crtc_wait_for_pending_flips(set->crtc); |
9247 | ||
4f660f49 | 9248 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9249 | set->x, set->y, set->fb); |
50f56119 DV |
9250 | } |
9251 | ||
2d05eae1 | 9252 | if (ret) { |
bf67dfeb DV |
9253 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9254 | set->crtc->base.id, ret); | |
50f56119 | 9255 | fail: |
2d05eae1 | 9256 | intel_set_config_restore_state(dev, config); |
50f56119 | 9257 | |
2d05eae1 CW |
9258 | /* Try to restore the config */ |
9259 | if (config->mode_changed && | |
9260 | intel_set_mode(save_set.crtc, save_set.mode, | |
9261 | save_set.x, save_set.y, save_set.fb)) | |
9262 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
9263 | } | |
50f56119 | 9264 | |
d9e55608 DV |
9265 | out_config: |
9266 | intel_set_config_free(config); | |
50f56119 DV |
9267 | return ret; |
9268 | } | |
f6e5b160 CW |
9269 | |
9270 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
9271 | .cursor_set = intel_crtc_cursor_set, |
9272 | .cursor_move = intel_crtc_cursor_move, | |
9273 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 9274 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
9275 | .destroy = intel_crtc_destroy, |
9276 | .page_flip = intel_crtc_page_flip, | |
9277 | }; | |
9278 | ||
79f689aa PZ |
9279 | static void intel_cpu_pll_init(struct drm_device *dev) |
9280 | { | |
affa9354 | 9281 | if (HAS_DDI(dev)) |
79f689aa PZ |
9282 | intel_ddi_pll_init(dev); |
9283 | } | |
9284 | ||
5358901f DV |
9285 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9286 | struct intel_shared_dpll *pll, | |
9287 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 9288 | { |
5358901f | 9289 | uint32_t val; |
ee7b9f93 | 9290 | |
5358901f | 9291 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
9292 | hw_state->dpll = val; |
9293 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
9294 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
9295 | |
9296 | return val & DPLL_VCO_ENABLE; | |
9297 | } | |
9298 | ||
15bdd4cf DV |
9299 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9300 | struct intel_shared_dpll *pll) | |
9301 | { | |
9302 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
9303 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
9304 | } | |
9305 | ||
e7b903d2 DV |
9306 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9307 | struct intel_shared_dpll *pll) | |
9308 | { | |
e7b903d2 DV |
9309 | /* PCH refclock must be enabled first */ |
9310 | assert_pch_refclk_enabled(dev_priv); | |
9311 | ||
15bdd4cf DV |
9312 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9313 | ||
9314 | /* Wait for the clocks to stabilize. */ | |
9315 | POSTING_READ(PCH_DPLL(pll->id)); | |
9316 | udelay(150); | |
9317 | ||
9318 | /* The pixel multiplier can only be updated once the | |
9319 | * DPLL is enabled and the clocks are stable. | |
9320 | * | |
9321 | * So write it again. | |
9322 | */ | |
9323 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
9324 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9325 | udelay(200); |
9326 | } | |
9327 | ||
9328 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
9329 | struct intel_shared_dpll *pll) | |
9330 | { | |
9331 | struct drm_device *dev = dev_priv->dev; | |
9332 | struct intel_crtc *crtc; | |
e7b903d2 DV |
9333 | |
9334 | /* Make sure no transcoder isn't still depending on us. */ | |
9335 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9336 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
9337 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
9338 | } |
9339 | ||
15bdd4cf DV |
9340 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9341 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9342 | udelay(200); |
9343 | } | |
9344 | ||
46edb027 DV |
9345 | static char *ibx_pch_dpll_names[] = { |
9346 | "PCH DPLL A", | |
9347 | "PCH DPLL B", | |
9348 | }; | |
9349 | ||
7c74ade1 | 9350 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 9351 | { |
e7b903d2 | 9352 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
9353 | int i; |
9354 | ||
7c74ade1 | 9355 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 9356 | |
e72f9fbf | 9357 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
9358 | dev_priv->shared_dplls[i].id = i; |
9359 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 9360 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
9361 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9362 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
9363 | dev_priv->shared_dplls[i].get_hw_state = |
9364 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
9365 | } |
9366 | } | |
9367 | ||
7c74ade1 DV |
9368 | static void intel_shared_dpll_init(struct drm_device *dev) |
9369 | { | |
e7b903d2 | 9370 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
9371 | |
9372 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
9373 | ibx_pch_dpll_init(dev); | |
9374 | else | |
9375 | dev_priv->num_shared_dpll = 0; | |
9376 | ||
9377 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
9378 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
9379 | dev_priv->num_shared_dpll); | |
9380 | } | |
9381 | ||
b358d0a6 | 9382 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 9383 | { |
22fd0fab | 9384 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
9385 | struct intel_crtc *intel_crtc; |
9386 | int i; | |
9387 | ||
9388 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
9389 | if (intel_crtc == NULL) | |
9390 | return; | |
9391 | ||
9392 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
9393 | ||
9394 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
9395 | for (i = 0; i < 256; i++) { |
9396 | intel_crtc->lut_r[i] = i; | |
9397 | intel_crtc->lut_g[i] = i; | |
9398 | intel_crtc->lut_b[i] = i; | |
9399 | } | |
9400 | ||
80824003 JB |
9401 | /* Swap pipes & planes for FBC on pre-965 */ |
9402 | intel_crtc->pipe = pipe; | |
9403 | intel_crtc->plane = pipe; | |
e2e767ab | 9404 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 9405 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 9406 | intel_crtc->plane = !pipe; |
80824003 JB |
9407 | } |
9408 | ||
22fd0fab JB |
9409 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9410 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
9411 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
9412 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
9413 | ||
79e53945 | 9414 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
9415 | } |
9416 | ||
08d7b3d1 | 9417 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 9418 | struct drm_file *file) |
08d7b3d1 | 9419 | { |
08d7b3d1 | 9420 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
9421 | struct drm_mode_object *drmmode_obj; |
9422 | struct intel_crtc *crtc; | |
08d7b3d1 | 9423 | |
1cff8f6b DV |
9424 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9425 | return -ENODEV; | |
08d7b3d1 | 9426 | |
c05422d5 DV |
9427 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9428 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 9429 | |
c05422d5 | 9430 | if (!drmmode_obj) { |
08d7b3d1 CW |
9431 | DRM_ERROR("no such CRTC id\n"); |
9432 | return -EINVAL; | |
9433 | } | |
9434 | ||
c05422d5 DV |
9435 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9436 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 9437 | |
c05422d5 | 9438 | return 0; |
08d7b3d1 CW |
9439 | } |
9440 | ||
66a9278e | 9441 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 9442 | { |
66a9278e DV |
9443 | struct drm_device *dev = encoder->base.dev; |
9444 | struct intel_encoder *source_encoder; | |
79e53945 | 9445 | int index_mask = 0; |
79e53945 JB |
9446 | int entry = 0; |
9447 | ||
66a9278e DV |
9448 | list_for_each_entry(source_encoder, |
9449 | &dev->mode_config.encoder_list, base.head) { | |
9450 | ||
9451 | if (encoder == source_encoder) | |
79e53945 | 9452 | index_mask |= (1 << entry); |
66a9278e DV |
9453 | |
9454 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
9455 | if (encoder->cloneable && source_encoder->cloneable) | |
9456 | index_mask |= (1 << entry); | |
9457 | ||
79e53945 JB |
9458 | entry++; |
9459 | } | |
4ef69c7a | 9460 | |
79e53945 JB |
9461 | return index_mask; |
9462 | } | |
9463 | ||
4d302442 CW |
9464 | static bool has_edp_a(struct drm_device *dev) |
9465 | { | |
9466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9467 | ||
9468 | if (!IS_MOBILE(dev)) | |
9469 | return false; | |
9470 | ||
9471 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
9472 | return false; | |
9473 | ||
9474 | if (IS_GEN5(dev) && | |
9475 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
9476 | return false; | |
9477 | ||
9478 | return true; | |
9479 | } | |
9480 | ||
79e53945 JB |
9481 | static void intel_setup_outputs(struct drm_device *dev) |
9482 | { | |
725e30ad | 9483 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 9484 | struct intel_encoder *encoder; |
cb0953d7 | 9485 | bool dpd_is_edp = false; |
79e53945 | 9486 | |
c9093354 | 9487 | intel_lvds_init(dev); |
79e53945 | 9488 | |
c40c0f5b | 9489 | if (!IS_ULT(dev)) |
79935fca | 9490 | intel_crt_init(dev); |
cb0953d7 | 9491 | |
affa9354 | 9492 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
9493 | int found; |
9494 | ||
9495 | /* Haswell uses DDI functions to detect digital outputs */ | |
9496 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
9497 | /* DDI A only supports eDP */ | |
9498 | if (found) | |
9499 | intel_ddi_init(dev, PORT_A); | |
9500 | ||
9501 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
9502 | * register */ | |
9503 | found = I915_READ(SFUSE_STRAP); | |
9504 | ||
9505 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
9506 | intel_ddi_init(dev, PORT_B); | |
9507 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
9508 | intel_ddi_init(dev, PORT_C); | |
9509 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
9510 | intel_ddi_init(dev, PORT_D); | |
9511 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 9512 | int found; |
270b3042 DV |
9513 | dpd_is_edp = intel_dpd_is_edp(dev); |
9514 | ||
9515 | if (has_edp_a(dev)) | |
9516 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 9517 | |
dc0fa718 | 9518 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 9519 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 9520 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 9521 | if (!found) |
e2debe91 | 9522 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 9523 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 9524 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
9525 | } |
9526 | ||
dc0fa718 | 9527 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 9528 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 9529 | |
dc0fa718 | 9530 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 9531 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 9532 | |
5eb08b69 | 9533 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 9534 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 9535 | |
270b3042 | 9536 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 9537 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 9538 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 9539 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
6f6005a5 JB |
9540 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9541 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
9542 | PORT_C); | |
9543 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
9544 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
9545 | PORT_C); | |
9546 | } | |
19c03924 | 9547 | |
dc0fa718 | 9548 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
e2debe91 PZ |
9549 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9550 | PORT_B); | |
67cfc203 VS |
9551 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9552 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d | 9553 | } |
103a196f | 9554 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 9555 | bool found = false; |
7d57382e | 9556 | |
e2debe91 | 9557 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9558 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 9559 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
9560 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9561 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 9562 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 9563 | } |
27185ae1 | 9564 | |
e7281eab | 9565 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9566 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 9567 | } |
13520b05 KH |
9568 | |
9569 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 9570 | |
e2debe91 | 9571 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9572 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 9573 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 9574 | } |
27185ae1 | 9575 | |
e2debe91 | 9576 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 9577 | |
b01f2c3a JB |
9578 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9579 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 9580 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 9581 | } |
e7281eab | 9582 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9583 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 9584 | } |
27185ae1 | 9585 | |
b01f2c3a | 9586 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 9587 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 9588 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 9589 | } else if (IS_GEN2(dev)) |
79e53945 JB |
9590 | intel_dvo_init(dev); |
9591 | ||
103a196f | 9592 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
9593 | intel_tv_init(dev); |
9594 | ||
4ef69c7a CW |
9595 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9596 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
9597 | encoder->base.possible_clones = | |
66a9278e | 9598 | intel_encoder_clones(encoder); |
79e53945 | 9599 | } |
47356eb6 | 9600 | |
dde86e2d | 9601 | intel_init_pch_refclk(dev); |
270b3042 DV |
9602 | |
9603 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
9604 | } |
9605 | ||
ddfe1567 CW |
9606 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
9607 | { | |
9608 | drm_framebuffer_cleanup(&fb->base); | |
9609 | drm_gem_object_unreference_unlocked(&fb->obj->base); | |
9610 | } | |
9611 | ||
79e53945 JB |
9612 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
9613 | { | |
9614 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 9615 | |
ddfe1567 | 9616 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
9617 | kfree(intel_fb); |
9618 | } | |
9619 | ||
9620 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 9621 | struct drm_file *file, |
79e53945 JB |
9622 | unsigned int *handle) |
9623 | { | |
9624 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 9625 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 9626 | |
05394f39 | 9627 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
9628 | } |
9629 | ||
9630 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
9631 | .destroy = intel_user_framebuffer_destroy, | |
9632 | .create_handle = intel_user_framebuffer_create_handle, | |
9633 | }; | |
9634 | ||
38651674 DA |
9635 | int intel_framebuffer_init(struct drm_device *dev, |
9636 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 9637 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 9638 | struct drm_i915_gem_object *obj) |
79e53945 | 9639 | { |
a35cdaa0 | 9640 | int pitch_limit; |
79e53945 JB |
9641 | int ret; |
9642 | ||
c16ed4be CW |
9643 | if (obj->tiling_mode == I915_TILING_Y) { |
9644 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 9645 | return -EINVAL; |
c16ed4be | 9646 | } |
57cd6508 | 9647 | |
c16ed4be CW |
9648 | if (mode_cmd->pitches[0] & 63) { |
9649 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
9650 | mode_cmd->pitches[0]); | |
57cd6508 | 9651 | return -EINVAL; |
c16ed4be | 9652 | } |
57cd6508 | 9653 | |
a35cdaa0 CW |
9654 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9655 | pitch_limit = 32*1024; | |
9656 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
9657 | if (obj->tiling_mode) | |
9658 | pitch_limit = 16*1024; | |
9659 | else | |
9660 | pitch_limit = 32*1024; | |
9661 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
9662 | if (obj->tiling_mode) | |
9663 | pitch_limit = 8*1024; | |
9664 | else | |
9665 | pitch_limit = 16*1024; | |
9666 | } else | |
9667 | /* XXX DSPC is limited to 4k tiled */ | |
9668 | pitch_limit = 8*1024; | |
9669 | ||
9670 | if (mode_cmd->pitches[0] > pitch_limit) { | |
9671 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
9672 | obj->tiling_mode ? "tiled" : "linear", | |
9673 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 9674 | return -EINVAL; |
c16ed4be | 9675 | } |
5d7bd705 VS |
9676 | |
9677 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
9678 | mode_cmd->pitches[0] != obj->stride) { |
9679 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
9680 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 9681 | return -EINVAL; |
c16ed4be | 9682 | } |
5d7bd705 | 9683 | |
57779d06 | 9684 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 9685 | switch (mode_cmd->pixel_format) { |
57779d06 | 9686 | case DRM_FORMAT_C8: |
04b3924d VS |
9687 | case DRM_FORMAT_RGB565: |
9688 | case DRM_FORMAT_XRGB8888: | |
9689 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
9690 | break; |
9691 | case DRM_FORMAT_XRGB1555: | |
9692 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 9693 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
9694 | DRM_DEBUG("unsupported pixel format: %s\n", |
9695 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9696 | return -EINVAL; |
c16ed4be | 9697 | } |
57779d06 VS |
9698 | break; |
9699 | case DRM_FORMAT_XBGR8888: | |
9700 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
9701 | case DRM_FORMAT_XRGB2101010: |
9702 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
9703 | case DRM_FORMAT_XBGR2101010: |
9704 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 9705 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
9706 | DRM_DEBUG("unsupported pixel format: %s\n", |
9707 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9708 | return -EINVAL; |
c16ed4be | 9709 | } |
b5626747 | 9710 | break; |
04b3924d VS |
9711 | case DRM_FORMAT_YUYV: |
9712 | case DRM_FORMAT_UYVY: | |
9713 | case DRM_FORMAT_YVYU: | |
9714 | case DRM_FORMAT_VYUY: | |
c16ed4be | 9715 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
9716 | DRM_DEBUG("unsupported pixel format: %s\n", |
9717 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9718 | return -EINVAL; |
c16ed4be | 9719 | } |
57cd6508 CW |
9720 | break; |
9721 | default: | |
4ee62c76 VS |
9722 | DRM_DEBUG("unsupported pixel format: %s\n", |
9723 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
9724 | return -EINVAL; |
9725 | } | |
9726 | ||
90f9a336 VS |
9727 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9728 | if (mode_cmd->offsets[0] != 0) | |
9729 | return -EINVAL; | |
9730 | ||
c7d73f6a DV |
9731 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9732 | intel_fb->obj = obj; | |
9733 | ||
79e53945 JB |
9734 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9735 | if (ret) { | |
9736 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
9737 | return ret; | |
9738 | } | |
9739 | ||
79e53945 JB |
9740 | return 0; |
9741 | } | |
9742 | ||
79e53945 JB |
9743 | static struct drm_framebuffer * |
9744 | intel_user_framebuffer_create(struct drm_device *dev, | |
9745 | struct drm_file *filp, | |
308e5bcb | 9746 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 9747 | { |
05394f39 | 9748 | struct drm_i915_gem_object *obj; |
79e53945 | 9749 | |
308e5bcb JB |
9750 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
9751 | mode_cmd->handles[0])); | |
c8725226 | 9752 | if (&obj->base == NULL) |
cce13ff7 | 9753 | return ERR_PTR(-ENOENT); |
79e53945 | 9754 | |
d2dff872 | 9755 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
9756 | } |
9757 | ||
79e53945 | 9758 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 9759 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 9760 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
9761 | }; |
9762 | ||
e70236a8 JB |
9763 | /* Set up chip specific display functions */ |
9764 | static void intel_init_display(struct drm_device *dev) | |
9765 | { | |
9766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9767 | ||
ee9300bb DV |
9768 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9769 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
9770 | else if (IS_VALLEYVIEW(dev)) | |
9771 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
9772 | else if (IS_PINEVIEW(dev)) | |
9773 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
9774 | else | |
9775 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
9776 | ||
affa9354 | 9777 | if (HAS_DDI(dev)) { |
0e8ffe1b | 9778 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 9779 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
9780 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9781 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 9782 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
9783 | dev_priv->display.update_plane = ironlake_update_plane; |
9784 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 9785 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f1f644dc | 9786 | dev_priv->display.get_clock = ironlake_crtc_clock_get; |
f564048e | 9787 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
9788 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9789 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 9790 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 9791 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
9792 | } else if (IS_VALLEYVIEW(dev)) { |
9793 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
f1f644dc | 9794 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
89b667f8 JB |
9795 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
9796 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
9797 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
9798 | dev_priv->display.off = i9xx_crtc_off; | |
9799 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 9800 | } else { |
0e8ffe1b | 9801 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f1f644dc | 9802 | dev_priv->display.get_clock = i9xx_crtc_clock_get; |
f564048e | 9803 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
9804 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9805 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 9806 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 9807 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 9808 | } |
e70236a8 | 9809 | |
e70236a8 | 9810 | /* Returns the core display clock speed */ |
25eb05fc JB |
9811 | if (IS_VALLEYVIEW(dev)) |
9812 | dev_priv->display.get_display_clock_speed = | |
9813 | valleyview_get_display_clock_speed; | |
9814 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
9815 | dev_priv->display.get_display_clock_speed = |
9816 | i945_get_display_clock_speed; | |
9817 | else if (IS_I915G(dev)) | |
9818 | dev_priv->display.get_display_clock_speed = | |
9819 | i915_get_display_clock_speed; | |
257a7ffc | 9820 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
9821 | dev_priv->display.get_display_clock_speed = |
9822 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
9823 | else if (IS_PINEVIEW(dev)) |
9824 | dev_priv->display.get_display_clock_speed = | |
9825 | pnv_get_display_clock_speed; | |
e70236a8 JB |
9826 | else if (IS_I915GM(dev)) |
9827 | dev_priv->display.get_display_clock_speed = | |
9828 | i915gm_get_display_clock_speed; | |
9829 | else if (IS_I865G(dev)) | |
9830 | dev_priv->display.get_display_clock_speed = | |
9831 | i865_get_display_clock_speed; | |
f0f8a9ce | 9832 | else if (IS_I85X(dev)) |
e70236a8 JB |
9833 | dev_priv->display.get_display_clock_speed = |
9834 | i855_get_display_clock_speed; | |
9835 | else /* 852, 830 */ | |
9836 | dev_priv->display.get_display_clock_speed = | |
9837 | i830_get_display_clock_speed; | |
9838 | ||
7f8a8569 | 9839 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 9840 | if (IS_GEN5(dev)) { |
674cf967 | 9841 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 9842 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 9843 | } else if (IS_GEN6(dev)) { |
674cf967 | 9844 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 9845 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
9846 | } else if (IS_IVYBRIDGE(dev)) { |
9847 | /* FIXME: detect B0+ stepping and use auto training */ | |
9848 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 9849 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
9850 | dev_priv->display.modeset_global_resources = |
9851 | ivb_modeset_global_resources; | |
c82e4d26 ED |
9852 | } else if (IS_HASWELL(dev)) { |
9853 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 9854 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
9855 | dev_priv->display.modeset_global_resources = |
9856 | haswell_modeset_global_resources; | |
a0e63c22 | 9857 | } |
6067aaea | 9858 | } else if (IS_G4X(dev)) { |
e0dac65e | 9859 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 9860 | } |
8c9f3aaf JB |
9861 | |
9862 | /* Default just returns -ENODEV to indicate unsupported */ | |
9863 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
9864 | ||
9865 | switch (INTEL_INFO(dev)->gen) { | |
9866 | case 2: | |
9867 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
9868 | break; | |
9869 | ||
9870 | case 3: | |
9871 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
9872 | break; | |
9873 | ||
9874 | case 4: | |
9875 | case 5: | |
9876 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
9877 | break; | |
9878 | ||
9879 | case 6: | |
9880 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
9881 | break; | |
7c9017e5 JB |
9882 | case 7: |
9883 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
9884 | break; | |
8c9f3aaf | 9885 | } |
e70236a8 JB |
9886 | } |
9887 | ||
b690e96c JB |
9888 | /* |
9889 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
9890 | * resume, or other times. This quirk makes sure that's the case for | |
9891 | * affected systems. | |
9892 | */ | |
0206e353 | 9893 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
9894 | { |
9895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9896 | ||
9897 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 9898 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
9899 | } |
9900 | ||
435793df KP |
9901 | /* |
9902 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
9903 | */ | |
9904 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9905 | { | |
9906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9907 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 9908 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
9909 | } |
9910 | ||
4dca20ef | 9911 | /* |
5a15ab5b CE |
9912 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9913 | * brightness value | |
4dca20ef CE |
9914 | */ |
9915 | static void quirk_invert_brightness(struct drm_device *dev) | |
9916 | { | |
9917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9918 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 9919 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
9920 | } |
9921 | ||
e85843be KM |
9922 | /* |
9923 | * Some machines (Dell XPS13) suffer broken backlight controls if | |
9924 | * BLM_PCH_PWM_ENABLE is set. | |
9925 | */ | |
9926 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) | |
9927 | { | |
9928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9929 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; | |
9930 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); | |
9931 | } | |
9932 | ||
b690e96c JB |
9933 | struct intel_quirk { |
9934 | int device; | |
9935 | int subsystem_vendor; | |
9936 | int subsystem_device; | |
9937 | void (*hook)(struct drm_device *dev); | |
9938 | }; | |
9939 | ||
5f85f176 EE |
9940 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9941 | struct intel_dmi_quirk { | |
9942 | void (*hook)(struct drm_device *dev); | |
9943 | const struct dmi_system_id (*dmi_id_list)[]; | |
9944 | }; | |
9945 | ||
9946 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
9947 | { | |
9948 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
9949 | return 1; | |
9950 | } | |
9951 | ||
9952 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
9953 | { | |
9954 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
9955 | { | |
9956 | .callback = intel_dmi_reverse_brightness, | |
9957 | .ident = "NCR Corporation", | |
9958 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
9959 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
9960 | }, | |
9961 | }, | |
9962 | { } /* terminating entry */ | |
9963 | }, | |
9964 | .hook = quirk_invert_brightness, | |
9965 | }, | |
9966 | }; | |
9967 | ||
c43b5634 | 9968 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 9969 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 9970 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 9971 | |
b690e96c JB |
9972 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9973 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9974 | ||
b690e96c JB |
9975 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9976 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9977 | ||
ccd0d36e | 9978 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 9979 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 9980 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
9981 | |
9982 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9983 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9984 | |
9985 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9986 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
9987 | |
9988 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
9989 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
1ffff603 JN |
9990 | |
9991 | /* Acer/eMachines G725 */ | |
9992 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
01e3a8fe JN |
9993 | |
9994 | /* Acer/eMachines e725 */ | |
9995 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
5559ecad JN |
9996 | |
9997 | /* Acer/Packard Bell NCL20 */ | |
9998 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
ac4199e0 DV |
9999 | |
10000 | /* Acer Aspire 4736Z */ | |
10001 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
e85843be KM |
10002 | |
10003 | /* Dell XPS13 HD Sandy Bridge */ | |
10004 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, | |
10005 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ | |
10006 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, | |
b690e96c JB |
10007 | }; |
10008 | ||
10009 | static void intel_init_quirks(struct drm_device *dev) | |
10010 | { | |
10011 | struct pci_dev *d = dev->pdev; | |
10012 | int i; | |
10013 | ||
10014 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10015 | struct intel_quirk *q = &intel_quirks[i]; | |
10016 | ||
10017 | if (d->device == q->device && | |
10018 | (d->subsystem_vendor == q->subsystem_vendor || | |
10019 | q->subsystem_vendor == PCI_ANY_ID) && | |
10020 | (d->subsystem_device == q->subsystem_device || | |
10021 | q->subsystem_device == PCI_ANY_ID)) | |
10022 | q->hook(dev); | |
10023 | } | |
5f85f176 EE |
10024 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10025 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10026 | intel_dmi_quirks[i].hook(dev); | |
10027 | } | |
b690e96c JB |
10028 | } |
10029 | ||
9cce37f4 JB |
10030 | /* Disable the VGA plane that we never use */ |
10031 | static void i915_disable_vga(struct drm_device *dev) | |
10032 | { | |
10033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10034 | u8 sr1; | |
766aa1c4 | 10035 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10036 | |
10037 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10038 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10039 | sr1 = inb(VGA_SR_DATA); |
10040 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10041 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10042 | udelay(300); | |
10043 | ||
10044 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10045 | POSTING_READ(vga_reg); | |
10046 | } | |
10047 | ||
6e1b4fda | 10048 | static void i915_enable_vga_mem(struct drm_device *dev) |
81b5c7bc AW |
10049 | { |
10050 | /* Enable VGA memory on Intel HD */ | |
10051 | if (HAS_PCH_SPLIT(dev)) { | |
10052 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10053 | outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10054 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10055 | VGA_RSRC_LEGACY_MEM | | |
10056 | VGA_RSRC_NORMAL_IO | | |
10057 | VGA_RSRC_NORMAL_MEM); | |
10058 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10059 | } | |
10060 | } | |
10061 | ||
6e1b4fda VS |
10062 | void i915_disable_vga_mem(struct drm_device *dev) |
10063 | { | |
10064 | /* Disable VGA memory on Intel HD */ | |
10065 | if (HAS_PCH_SPLIT(dev)) { | |
10066 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10067 | outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10068 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10069 | VGA_RSRC_NORMAL_IO | | |
10070 | VGA_RSRC_NORMAL_MEM); | |
10071 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10072 | } | |
10073 | } | |
10074 | ||
f817586c DV |
10075 | void intel_modeset_init_hw(struct drm_device *dev) |
10076 | { | |
fa42e23c | 10077 | intel_init_power_well(dev); |
0232e927 | 10078 | |
a8f78b58 ED |
10079 | intel_prepare_ddi(dev); |
10080 | ||
f817586c DV |
10081 | intel_init_clock_gating(dev); |
10082 | ||
79f5b2c7 | 10083 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10084 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10085 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10086 | } |
10087 | ||
7d708ee4 ID |
10088 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10089 | { | |
10090 | intel_suspend_hw(dev); | |
10091 | } | |
10092 | ||
79e53945 JB |
10093 | void intel_modeset_init(struct drm_device *dev) |
10094 | { | |
652c393a | 10095 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10096 | int i, j, ret; |
79e53945 JB |
10097 | |
10098 | drm_mode_config_init(dev); | |
10099 | ||
10100 | dev->mode_config.min_width = 0; | |
10101 | dev->mode_config.min_height = 0; | |
10102 | ||
019d96cb DA |
10103 | dev->mode_config.preferred_depth = 24; |
10104 | dev->mode_config.prefer_shadow = 1; | |
10105 | ||
e6ecefaa | 10106 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10107 | |
b690e96c JB |
10108 | intel_init_quirks(dev); |
10109 | ||
1fa61106 ED |
10110 | intel_init_pm(dev); |
10111 | ||
e3c74757 BW |
10112 | if (INTEL_INFO(dev)->num_pipes == 0) |
10113 | return; | |
10114 | ||
e70236a8 JB |
10115 | intel_init_display(dev); |
10116 | ||
a6c45cf0 CW |
10117 | if (IS_GEN2(dev)) { |
10118 | dev->mode_config.max_width = 2048; | |
10119 | dev->mode_config.max_height = 2048; | |
10120 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10121 | dev->mode_config.max_width = 4096; |
10122 | dev->mode_config.max_height = 4096; | |
79e53945 | 10123 | } else { |
a6c45cf0 CW |
10124 | dev->mode_config.max_width = 8192; |
10125 | dev->mode_config.max_height = 8192; | |
79e53945 | 10126 | } |
5d4545ae | 10127 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10128 | |
28c97730 | 10129 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10130 | INTEL_INFO(dev)->num_pipes, |
10131 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10132 | |
08e2a7de | 10133 | for_each_pipe(i) { |
79e53945 | 10134 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10135 | for (j = 0; j < dev_priv->num_plane; j++) { |
10136 | ret = intel_plane_init(dev, i, j); | |
10137 | if (ret) | |
06da8da2 VS |
10138 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10139 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10140 | } |
79e53945 JB |
10141 | } |
10142 | ||
79f689aa | 10143 | intel_cpu_pll_init(dev); |
e72f9fbf | 10144 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10145 | |
9cce37f4 JB |
10146 | /* Just disable it once at startup */ |
10147 | i915_disable_vga(dev); | |
79e53945 | 10148 | intel_setup_outputs(dev); |
11be49eb CW |
10149 | |
10150 | /* Just in case the BIOS is doing something questionable. */ | |
10151 | intel_disable_fbc(dev); | |
2c7111db CW |
10152 | } |
10153 | ||
24929352 DV |
10154 | static void |
10155 | intel_connector_break_all_links(struct intel_connector *connector) | |
10156 | { | |
10157 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10158 | connector->base.encoder = NULL; | |
10159 | connector->encoder->connectors_active = false; | |
10160 | connector->encoder->base.crtc = NULL; | |
10161 | } | |
10162 | ||
7fad798e DV |
10163 | static void intel_enable_pipe_a(struct drm_device *dev) |
10164 | { | |
10165 | struct intel_connector *connector; | |
10166 | struct drm_connector *crt = NULL; | |
10167 | struct intel_load_detect_pipe load_detect_temp; | |
10168 | ||
10169 | /* We can't just switch on the pipe A, we need to set things up with a | |
10170 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10171 | * by enabling the load detect pipe once. */ | |
10172 | list_for_each_entry(connector, | |
10173 | &dev->mode_config.connector_list, | |
10174 | base.head) { | |
10175 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10176 | crt = &connector->base; | |
10177 | break; | |
10178 | } | |
10179 | } | |
10180 | ||
10181 | if (!crt) | |
10182 | return; | |
10183 | ||
10184 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10185 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10186 | ||
652c393a | 10187 | |
7fad798e DV |
10188 | } |
10189 | ||
fa555837 DV |
10190 | static bool |
10191 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10192 | { | |
7eb552ae BW |
10193 | struct drm_device *dev = crtc->base.dev; |
10194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10195 | u32 reg, val; |
10196 | ||
7eb552ae | 10197 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10198 | return true; |
10199 | ||
10200 | reg = DSPCNTR(!crtc->plane); | |
10201 | val = I915_READ(reg); | |
10202 | ||
10203 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10204 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10205 | return false; | |
10206 | ||
10207 | return true; | |
10208 | } | |
10209 | ||
24929352 DV |
10210 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10211 | { | |
10212 | struct drm_device *dev = crtc->base.dev; | |
10213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10214 | u32 reg; |
24929352 | 10215 | |
24929352 | 10216 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10217 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10218 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10219 | ||
10220 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10221 | * disable the crtc (and hence change the state) if it is wrong. Note |
10222 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10223 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10224 | struct intel_connector *connector; |
10225 | bool plane; | |
10226 | ||
24929352 DV |
10227 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10228 | crtc->base.base.id); | |
10229 | ||
10230 | /* Pipe has the wrong plane attached and the plane is active. | |
10231 | * Temporarily change the plane mapping and disable everything | |
10232 | * ... */ | |
10233 | plane = crtc->plane; | |
10234 | crtc->plane = !plane; | |
10235 | dev_priv->display.crtc_disable(&crtc->base); | |
10236 | crtc->plane = plane; | |
10237 | ||
10238 | /* ... and break all links. */ | |
10239 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10240 | base.head) { | |
10241 | if (connector->encoder->base.crtc != &crtc->base) | |
10242 | continue; | |
10243 | ||
10244 | intel_connector_break_all_links(connector); | |
10245 | } | |
10246 | ||
10247 | WARN_ON(crtc->active); | |
10248 | crtc->base.enabled = false; | |
10249 | } | |
24929352 | 10250 | |
7fad798e DV |
10251 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10252 | crtc->pipe == PIPE_A && !crtc->active) { | |
10253 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10254 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10255 | * call below we restore the pipe to the right state, but leave | |
10256 | * the required bits on. */ | |
10257 | intel_enable_pipe_a(dev); | |
10258 | } | |
10259 | ||
24929352 DV |
10260 | /* Adjust the state of the output pipe according to whether we |
10261 | * have active connectors/encoders. */ | |
10262 | intel_crtc_update_dpms(&crtc->base); | |
10263 | ||
10264 | if (crtc->active != crtc->base.enabled) { | |
10265 | struct intel_encoder *encoder; | |
10266 | ||
10267 | /* This can happen either due to bugs in the get_hw_state | |
10268 | * functions or because the pipe is force-enabled due to the | |
10269 | * pipe A quirk. */ | |
10270 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
10271 | crtc->base.base.id, | |
10272 | crtc->base.enabled ? "enabled" : "disabled", | |
10273 | crtc->active ? "enabled" : "disabled"); | |
10274 | ||
10275 | crtc->base.enabled = crtc->active; | |
10276 | ||
10277 | /* Because we only establish the connector -> encoder -> | |
10278 | * crtc links if something is active, this means the | |
10279 | * crtc is now deactivated. Break the links. connector | |
10280 | * -> encoder links are only establish when things are | |
10281 | * actually up, hence no need to break them. */ | |
10282 | WARN_ON(crtc->active); | |
10283 | ||
10284 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
10285 | WARN_ON(encoder->connectors_active); | |
10286 | encoder->base.crtc = NULL; | |
10287 | } | |
10288 | } | |
10289 | } | |
10290 | ||
10291 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
10292 | { | |
10293 | struct intel_connector *connector; | |
10294 | struct drm_device *dev = encoder->base.dev; | |
10295 | ||
10296 | /* We need to check both for a crtc link (meaning that the | |
10297 | * encoder is active and trying to read from a pipe) and the | |
10298 | * pipe itself being active. */ | |
10299 | bool has_active_crtc = encoder->base.crtc && | |
10300 | to_intel_crtc(encoder->base.crtc)->active; | |
10301 | ||
10302 | if (encoder->connectors_active && !has_active_crtc) { | |
10303 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
10304 | encoder->base.base.id, | |
10305 | drm_get_encoder_name(&encoder->base)); | |
10306 | ||
10307 | /* Connector is active, but has no active pipe. This is | |
10308 | * fallout from our resume register restoring. Disable | |
10309 | * the encoder manually again. */ | |
10310 | if (encoder->base.crtc) { | |
10311 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
10312 | encoder->base.base.id, | |
10313 | drm_get_encoder_name(&encoder->base)); | |
10314 | encoder->disable(encoder); | |
10315 | } | |
10316 | ||
10317 | /* Inconsistent output/port/pipe state happens presumably due to | |
10318 | * a bug in one of the get_hw_state functions. Or someplace else | |
10319 | * in our code, like the register restore mess on resume. Clamp | |
10320 | * things to off as a safer default. */ | |
10321 | list_for_each_entry(connector, | |
10322 | &dev->mode_config.connector_list, | |
10323 | base.head) { | |
10324 | if (connector->encoder != encoder) | |
10325 | continue; | |
10326 | ||
10327 | intel_connector_break_all_links(connector); | |
10328 | } | |
10329 | } | |
10330 | /* Enabled encoders without active connectors will be fixed in | |
10331 | * the crtc fixup. */ | |
10332 | } | |
10333 | ||
44cec740 | 10334 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
10335 | { |
10336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 10337 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 10338 | |
8dc8a27c PZ |
10339 | /* This function can be called both from intel_modeset_setup_hw_state or |
10340 | * at a very early point in our resume sequence, where the power well | |
10341 | * structures are not yet restored. Since this function is at a very | |
10342 | * paranoid "someone might have enabled VGA while we were not looking" | |
10343 | * level, just check if the power well is enabled instead of trying to | |
10344 | * follow the "don't touch the power well if we don't need it" policy | |
10345 | * the rest of the driver uses. */ | |
10346 | if (HAS_POWER_WELL(dev) && | |
6aedd1f5 | 10347 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
10348 | return; |
10349 | ||
0fde901f KM |
10350 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10351 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 10352 | i915_disable_vga(dev); |
6e1b4fda | 10353 | i915_disable_vga_mem(dev); |
0fde901f KM |
10354 | } |
10355 | } | |
10356 | ||
30e984df | 10357 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
10358 | { |
10359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10360 | enum pipe pipe; | |
24929352 DV |
10361 | struct intel_crtc *crtc; |
10362 | struct intel_encoder *encoder; | |
10363 | struct intel_connector *connector; | |
5358901f | 10364 | int i; |
24929352 | 10365 | |
0e8ffe1b DV |
10366 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10367 | base.head) { | |
88adfff1 | 10368 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 10369 | |
0e8ffe1b DV |
10370 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10371 | &crtc->config); | |
24929352 DV |
10372 | |
10373 | crtc->base.enabled = crtc->active; | |
10374 | ||
10375 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
10376 | crtc->base.base.id, | |
10377 | crtc->active ? "enabled" : "disabled"); | |
10378 | } | |
10379 | ||
5358901f | 10380 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 10381 | if (HAS_DDI(dev)) |
6441ab5f PZ |
10382 | intel_ddi_setup_hw_pll_state(dev); |
10383 | ||
5358901f DV |
10384 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10385 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10386 | ||
10387 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
10388 | pll->active = 0; | |
10389 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10390 | base.head) { | |
10391 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10392 | pll->active++; | |
10393 | } | |
10394 | pll->refcount = pll->active; | |
10395 | ||
35c95375 DV |
10396 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10397 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
10398 | } |
10399 | ||
24929352 DV |
10400 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10401 | base.head) { | |
10402 | pipe = 0; | |
10403 | ||
10404 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
10405 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10406 | encoder->base.crtc = &crtc->base; | |
510d5f2f | 10407 | if (encoder->get_config) |
045ac3b5 | 10408 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
10409 | } else { |
10410 | encoder->base.crtc = NULL; | |
10411 | } | |
10412 | ||
10413 | encoder->connectors_active = false; | |
10414 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
10415 | encoder->base.base.id, | |
10416 | drm_get_encoder_name(&encoder->base), | |
10417 | encoder->base.crtc ? "enabled" : "disabled", | |
10418 | pipe); | |
10419 | } | |
10420 | ||
510d5f2f JB |
10421 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10422 | base.head) { | |
10423 | if (!crtc->active) | |
10424 | continue; | |
10425 | if (dev_priv->display.get_clock) | |
10426 | dev_priv->display.get_clock(crtc, | |
10427 | &crtc->config); | |
10428 | } | |
10429 | ||
24929352 DV |
10430 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10431 | base.head) { | |
10432 | if (connector->get_hw_state(connector)) { | |
10433 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
10434 | connector->encoder->connectors_active = true; | |
10435 | connector->base.encoder = &connector->encoder->base; | |
10436 | } else { | |
10437 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10438 | connector->base.encoder = NULL; | |
10439 | } | |
10440 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
10441 | connector->base.base.id, | |
10442 | drm_get_connector_name(&connector->base), | |
10443 | connector->base.encoder ? "enabled" : "disabled"); | |
10444 | } | |
30e984df DV |
10445 | } |
10446 | ||
10447 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
10448 | * and i915 state tracking structures. */ | |
10449 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
10450 | bool force_restore) | |
10451 | { | |
10452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10453 | enum pipe pipe; | |
10454 | struct drm_plane *plane; | |
10455 | struct intel_crtc *crtc; | |
10456 | struct intel_encoder *encoder; | |
35c95375 | 10457 | int i; |
30e984df DV |
10458 | |
10459 | intel_modeset_readout_hw_state(dev); | |
24929352 | 10460 | |
babea61d JB |
10461 | /* |
10462 | * Now that we have the config, copy it to each CRTC struct | |
10463 | * Note that this could go away if we move to using crtc_config | |
10464 | * checking everywhere. | |
10465 | */ | |
10466 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10467 | base.head) { | |
10468 | if (crtc->active && i915_fastboot) { | |
10469 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
10470 | ||
10471 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
10472 | crtc->base.base.id); | |
10473 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
10474 | } | |
10475 | } | |
10476 | ||
24929352 DV |
10477 | /* HW state is read out, now we need to sanitize this mess. */ |
10478 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10479 | base.head) { | |
10480 | intel_sanitize_encoder(encoder); | |
10481 | } | |
10482 | ||
10483 | for_each_pipe(pipe) { | |
10484 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
10485 | intel_sanitize_crtc(crtc); | |
c0b03411 | 10486 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 10487 | } |
9a935856 | 10488 | |
35c95375 DV |
10489 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10490 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10491 | ||
10492 | if (!pll->on || pll->active) | |
10493 | continue; | |
10494 | ||
10495 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
10496 | ||
10497 | pll->disable(dev_priv, pll); | |
10498 | pll->on = false; | |
10499 | } | |
10500 | ||
45e2b5f6 | 10501 | if (force_restore) { |
f30da187 DV |
10502 | /* |
10503 | * We need to use raw interfaces for restoring state to avoid | |
10504 | * checking (bogus) intermediate states. | |
10505 | */ | |
45e2b5f6 | 10506 | for_each_pipe(pipe) { |
b5644d05 JB |
10507 | struct drm_crtc *crtc = |
10508 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
10509 | |
10510 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
10511 | crtc->fb); | |
45e2b5f6 | 10512 | } |
b5644d05 JB |
10513 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10514 | intel_plane_restore(plane); | |
0fde901f KM |
10515 | |
10516 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
10517 | } else { |
10518 | intel_modeset_update_staged_output_state(dev); | |
10519 | } | |
8af6cf88 DV |
10520 | |
10521 | intel_modeset_check_state(dev); | |
2e938892 DV |
10522 | |
10523 | drm_mode_config_reset(dev); | |
2c7111db CW |
10524 | } |
10525 | ||
10526 | void intel_modeset_gem_init(struct drm_device *dev) | |
10527 | { | |
1833b134 | 10528 | intel_modeset_init_hw(dev); |
02e792fb DV |
10529 | |
10530 | intel_setup_overlay(dev); | |
24929352 | 10531 | |
45e2b5f6 | 10532 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
10533 | } |
10534 | ||
10535 | void intel_modeset_cleanup(struct drm_device *dev) | |
10536 | { | |
652c393a JB |
10537 | struct drm_i915_private *dev_priv = dev->dev_private; |
10538 | struct drm_crtc *crtc; | |
652c393a | 10539 | |
fd0c0642 DV |
10540 | /* |
10541 | * Interrupts and polling as the first thing to avoid creating havoc. | |
10542 | * Too much stuff here (turning of rps, connectors, ...) would | |
10543 | * experience fancy races otherwise. | |
10544 | */ | |
10545 | drm_irq_uninstall(dev); | |
10546 | cancel_work_sync(&dev_priv->hotplug_work); | |
10547 | /* | |
10548 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
10549 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
10550 | */ | |
f87ea761 | 10551 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 10552 | |
652c393a JB |
10553 | mutex_lock(&dev->struct_mutex); |
10554 | ||
723bfd70 JB |
10555 | intel_unregister_dsm_handler(); |
10556 | ||
652c393a JB |
10557 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10558 | /* Skip inactive CRTCs */ | |
10559 | if (!crtc->fb) | |
10560 | continue; | |
10561 | ||
3dec0095 | 10562 | intel_increase_pllclock(crtc); |
652c393a JB |
10563 | } |
10564 | ||
973d04f9 | 10565 | intel_disable_fbc(dev); |
e70236a8 | 10566 | |
6e1b4fda | 10567 | i915_enable_vga_mem(dev); |
81b5c7bc | 10568 | |
8090c6b9 | 10569 | intel_disable_gt_powersave(dev); |
0cdab21f | 10570 | |
930ebb46 DV |
10571 | ironlake_teardown_rc6(dev); |
10572 | ||
69341a5e KH |
10573 | mutex_unlock(&dev->struct_mutex); |
10574 | ||
1630fe75 CW |
10575 | /* flush any delayed tasks or pending work */ |
10576 | flush_scheduled_work(); | |
10577 | ||
dc652f90 JN |
10578 | /* destroy backlight, if any, before the connectors */ |
10579 | intel_panel_destroy_backlight(dev); | |
10580 | ||
79e53945 | 10581 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
10582 | |
10583 | intel_cleanup_overlay(dev); | |
79e53945 JB |
10584 | } |
10585 | ||
f1c79df3 ZW |
10586 | /* |
10587 | * Return which encoder is currently attached for connector. | |
10588 | */ | |
df0e9248 | 10589 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 10590 | { |
df0e9248 CW |
10591 | return &intel_attached_encoder(connector)->base; |
10592 | } | |
f1c79df3 | 10593 | |
df0e9248 CW |
10594 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10595 | struct intel_encoder *encoder) | |
10596 | { | |
10597 | connector->encoder = encoder; | |
10598 | drm_mode_connector_attach_encoder(&connector->base, | |
10599 | &encoder->base); | |
79e53945 | 10600 | } |
28d52043 DA |
10601 | |
10602 | /* | |
10603 | * set vga decode state - true == enable VGA decode | |
10604 | */ | |
10605 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
10606 | { | |
10607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10608 | u16 gmch_ctrl; | |
10609 | ||
10610 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
10611 | if (state) | |
10612 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
10613 | else | |
10614 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
10615 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
10616 | return 0; | |
10617 | } | |
c4a1d9e4 | 10618 | |
c4a1d9e4 | 10619 | struct intel_display_error_state { |
ff57f1b0 PZ |
10620 | |
10621 | u32 power_well_driver; | |
10622 | ||
63b66e5b CW |
10623 | int num_transcoders; |
10624 | ||
c4a1d9e4 CW |
10625 | struct intel_cursor_error_state { |
10626 | u32 control; | |
10627 | u32 position; | |
10628 | u32 base; | |
10629 | u32 size; | |
52331309 | 10630 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10631 | |
10632 | struct intel_pipe_error_state { | |
c4a1d9e4 | 10633 | u32 source; |
52331309 | 10634 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10635 | |
10636 | struct intel_plane_error_state { | |
10637 | u32 control; | |
10638 | u32 stride; | |
10639 | u32 size; | |
10640 | u32 pos; | |
10641 | u32 addr; | |
10642 | u32 surface; | |
10643 | u32 tile_offset; | |
52331309 | 10644 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
10645 | |
10646 | struct intel_transcoder_error_state { | |
10647 | enum transcoder cpu_transcoder; | |
10648 | ||
10649 | u32 conf; | |
10650 | ||
10651 | u32 htotal; | |
10652 | u32 hblank; | |
10653 | u32 hsync; | |
10654 | u32 vtotal; | |
10655 | u32 vblank; | |
10656 | u32 vsync; | |
10657 | } transcoder[4]; | |
c4a1d9e4 CW |
10658 | }; |
10659 | ||
10660 | struct intel_display_error_state * | |
10661 | intel_display_capture_error_state(struct drm_device *dev) | |
10662 | { | |
0206e353 | 10663 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 10664 | struct intel_display_error_state *error; |
63b66e5b CW |
10665 | int transcoders[] = { |
10666 | TRANSCODER_A, | |
10667 | TRANSCODER_B, | |
10668 | TRANSCODER_C, | |
10669 | TRANSCODER_EDP, | |
10670 | }; | |
c4a1d9e4 CW |
10671 | int i; |
10672 | ||
63b66e5b CW |
10673 | if (INTEL_INFO(dev)->num_pipes == 0) |
10674 | return NULL; | |
10675 | ||
c4a1d9e4 CW |
10676 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10677 | if (error == NULL) | |
10678 | return NULL; | |
10679 | ||
ff57f1b0 PZ |
10680 | if (HAS_POWER_WELL(dev)) |
10681 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
10682 | ||
52331309 | 10683 | for_each_pipe(i) { |
a18c4c3d PZ |
10684 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10685 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
10686 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
10687 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
10688 | } else { | |
10689 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
10690 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
10691 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
10692 | } | |
c4a1d9e4 CW |
10693 | |
10694 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
10695 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 10696 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 10697 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
10698 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10699 | } | |
ca291363 PZ |
10700 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10701 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
10702 | if (INTEL_INFO(dev)->gen >= 4) { |
10703 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
10704 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
10705 | } | |
10706 | ||
c4a1d9e4 | 10707 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
10708 | } |
10709 | ||
10710 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
10711 | if (HAS_DDI(dev_priv->dev)) | |
10712 | error->num_transcoders++; /* Account for eDP. */ | |
10713 | ||
10714 | for (i = 0; i < error->num_transcoders; i++) { | |
10715 | enum transcoder cpu_transcoder = transcoders[i]; | |
10716 | ||
10717 | error->transcoder[i].cpu_transcoder = cpu_transcoder; | |
10718 | ||
10719 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
10720 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
10721 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
10722 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10723 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
10724 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
10725 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
10726 | } |
10727 | ||
12d217c7 PZ |
10728 | /* In the code above we read the registers without checking if the power |
10729 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to | |
10730 | * prevent the next I915_WRITE from detecting it and printing an error | |
10731 | * message. */ | |
907b28c5 | 10732 | intel_uncore_clear_errors(dev); |
12d217c7 | 10733 | |
c4a1d9e4 CW |
10734 | return error; |
10735 | } | |
10736 | ||
edc3d884 MK |
10737 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10738 | ||
c4a1d9e4 | 10739 | void |
edc3d884 | 10740 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
10741 | struct drm_device *dev, |
10742 | struct intel_display_error_state *error) | |
10743 | { | |
10744 | int i; | |
10745 | ||
63b66e5b CW |
10746 | if (!error) |
10747 | return; | |
10748 | ||
edc3d884 | 10749 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
ff57f1b0 | 10750 | if (HAS_POWER_WELL(dev)) |
edc3d884 | 10751 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 10752 | error->power_well_driver); |
52331309 | 10753 | for_each_pipe(i) { |
edc3d884 | 10754 | err_printf(m, "Pipe [%d]:\n", i); |
edc3d884 | 10755 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
10756 | |
10757 | err_printf(m, "Plane [%d]:\n", i); | |
10758 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
10759 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 10760 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
10761 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10762 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 10763 | } |
4b71a570 | 10764 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 10765 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 10766 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
10767 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10768 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
10769 | } |
10770 | ||
edc3d884 MK |
10771 | err_printf(m, "Cursor [%d]:\n", i); |
10772 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
10773 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
10774 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 10775 | } |
63b66e5b CW |
10776 | |
10777 | for (i = 0; i < error->num_transcoders; i++) { | |
10778 | err_printf(m, " CPU transcoder: %c\n", | |
10779 | transcoder_name(error->transcoder[i].cpu_transcoder)); | |
10780 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
10781 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
10782 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
10783 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
10784 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
10785 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
10786 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
10787 | } | |
c4a1d9e4 | 10788 | } |