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drivers: i915: Fix BLC PWM register setup
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179
JB		 938
939 reg = PIPECONF(pipe);
940 val = I915_READ(reg);
63d7bbe9
JB		 941 cur_state = !!(val & PIPECONF_ENABLE);
942 WARN(cur_state != state,
943 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 944 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 945}
946
931872fc
CW		 947static void assert_plane(struct drm_i915_private *dev_priv,
948 enum plane plane, bool state)
b24e7179
JB		 949{
950 int reg;
951 u32 val;
931872fc 952 bool cur_state;
b24e7179
JB		 953
954 reg = DSPCNTR(plane);
955 val = I915_READ(reg);
931872fc
CW		 956 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
957 WARN(cur_state != state,
958 "plane %c assertion failure (expected %s, current %s)\n",
959 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 960}
961
931872fc
CW		 962#define assert_plane_enabled(d, p) assert_plane(d, p, true)
963#define assert_plane_disabled(d, p) assert_plane(d, p, false)
964
b24e7179
JB		 965static void assert_planes_disabled(struct drm_i915_private *dev_priv,
966 enum pipe pipe)
967{
968 int reg, i;
969 u32 val;
970 int cur_pipe;
971
19ec1358
JB		 972 /* Planes are fixed to pipes on ILK+ */
973 if (HAS_PCH_SPLIT(dev_priv->dev))
974 return;
975
b24e7179
JB		 976 /* Need to check both planes against the pipe */
977 for (i = 0; i < 2; i++) {
978 reg = DSPCNTR(i);
979 val = I915_READ(reg);
980 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
981 DISPPLANE_SEL_PIPE_SHIFT;
982 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 983 "plane %c assertion failure, should be off on pipe %c but is still active\n",
984 plane_name(i), pipe_name(pipe));
b24e7179
JB		 985 }
986}
987
92f2584a
JB		 988static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
989{
990 u32 val;
991 bool enabled;
992
993 val = I915_READ(PCH_DREF_CONTROL);
994 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
995 DREF_SUPERSPREAD_SOURCE_MASK));
996 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
997}
998
999static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 int reg;
1003 u32 val;
1004 bool enabled;
1005
1006 reg = TRANSCONF(pipe);
1007 val = I915_READ(reg);
1008 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1009 WARN(enabled,
1010 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1011 pipe_name(pipe));
92f2584a
JB		 1012}
1013
4e634389
KP		 1014static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1015 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1016{
1017 if ((val & DP_PORT_EN) == 0)
1018 return false;
1019
1020 if (HAS_PCH_CPT(dev_priv->dev)) {
1021 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1022 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1023 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1024 return false;
1025 } else {
1026 if ((val & DP_PIPE_MASK) != (pipe << 30))
1027 return false;
1028 }
1029 return true;
1030}
1031
1519b995
KP		 1032static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1033 enum pipe pipe, u32 val)
1034{
1035 if ((val & PORT_ENABLE) == 0)
1036 return false;
1037
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 return false;
1041 } else {
1042 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1043 return false;
1044 }
1045 return true;
1046}
1047
1048static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, u32 val)
1050{
1051 if ((val & LVDS_PORT_EN) == 0)
1052 return false;
1053
1054 if (HAS_PCH_CPT(dev_priv->dev)) {
1055 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1056 return false;
1057 } else {
1058 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1059 return false;
1060 }
1061 return true;
1062}
1063
1064static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, u32 val)
1066{
1067 if ((val & ADPA_DAC_ENABLE) == 0)
1068 return false;
1069 if (HAS_PCH_CPT(dev_priv->dev)) {
1070 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1071 return false;
1072 } else {
1073 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1074 return false;
1075 }
1076 return true;
1077}
1078
291906f1 1079static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1080 enum pipe pipe, int reg, u32 port_sel)
291906f1 1081{
47a05eca 1082 u32 val = I915_READ(reg);
4e634389 1083 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1084 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1085 reg, pipe_name(pipe));
291906f1
JB		 1086}
1087
1088static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, int reg)
1090{
47a05eca 1091 u32 val = I915_READ(reg);
1519b995 1092 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1093 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1094 reg, pipe_name(pipe));
291906f1
JB		 1095}
1096
1097static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1098 enum pipe pipe)
1099{
1100 int reg;
1101 u32 val;
291906f1 1102
f0575e92
KP		 1103 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1104 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1105 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1106
1107 reg = PCH_ADPA;
1108 val = I915_READ(reg);
1519b995 1109 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1110 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1111 pipe_name(pipe));
291906f1
JB		 1112
1113 reg = PCH_LVDS;
1114 val = I915_READ(reg);
1519b995 1115 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1116 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1117 pipe_name(pipe));
291906f1
JB		 1118
1119 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1120 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1121 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1122}
1123
63d7bbe9
JB		 1124/**
1125 * intel_enable_pll - enable a PLL
1126 * @dev_priv: i915 private structure
1127 * @pipe: pipe PLL to enable
1128 *
1129 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1130 * make sure the PLL reg is writable first though, since the panel write
1131 * protect mechanism may be enabled.
1132 *
1133 * Note! This is for pre-ILK only.
1134 */
1135static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1136{
1137 int reg;
1138 u32 val;
1139
1140 /* No really, not for ILK+ */
1141 BUG_ON(dev_priv->info->gen >= 5);
1142
1143 /* PLL is protected by panel, make sure we can write it */
1144 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1145 assert_panel_unlocked(dev_priv, pipe);
1146
1147 reg = DPLL(pipe);
1148 val = I915_READ(reg);
1149 val |= DPLL_VCO_ENABLE;
1150
1151 /* We do this three times for luck */
1152 I915_WRITE(reg, val);
1153 POSTING_READ(reg);
1154 udelay(150); /* wait for warmup */
1155 I915_WRITE(reg, val);
1156 POSTING_READ(reg);
1157 udelay(150); /* wait for warmup */
1158 I915_WRITE(reg, val);
1159 POSTING_READ(reg);
1160 udelay(150); /* wait for warmup */
1161}
1162
1163/**
1164 * intel_disable_pll - disable a PLL
1165 * @dev_priv: i915 private structure
1166 * @pipe: pipe PLL to disable
1167 *
1168 * Disable the PLL for @pipe, making sure the pipe is off first.
1169 *
1170 * Note! This is for pre-ILK only.
1171 */
1172static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1173{
1174 int reg;
1175 u32 val;
1176
1177 /* Don't disable pipe A or pipe A PLLs if needed */
1178 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1179 return;
1180
1181 /* Make sure the pipe isn't still relying on us */
1182 assert_pipe_disabled(dev_priv, pipe);
1183
1184 reg = DPLL(pipe);
1185 val = I915_READ(reg);
1186 val &= ~DPLL_VCO_ENABLE;
1187 I915_WRITE(reg, val);
1188 POSTING_READ(reg);
1189}
1190
92f2584a
JB		 1191/**
1192 * intel_enable_pch_pll - enable PCH PLL
1193 * @dev_priv: i915 private structure
1194 * @pipe: pipe PLL to enable
1195 *
1196 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1197 * drives the transcoder clock.
1198 */
1199static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1200 enum pipe pipe)
1201{
1202 int reg;
1203 u32 val;
1204
4c609cb8
JB		 1205 if (pipe > 1)
1206 return;
1207
92f2584a
JB		 1208 /* PCH only available on ILK+ */
1209 BUG_ON(dev_priv->info->gen < 5);
1210
1211 /* PCH refclock must be enabled first */
1212 assert_pch_refclk_enabled(dev_priv);
1213
1214 reg = PCH_DPLL(pipe);
1215 val = I915_READ(reg);
1216 val |= DPLL_VCO_ENABLE;
1217 I915_WRITE(reg, val);
1218 POSTING_READ(reg);
1219 udelay(200);
1220}
1221
1222static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1223 enum pipe pipe)
1224{
1225 int reg;
7a419866
JB		 1226 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1227 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1228
4c609cb8
JB		 1229 if (pipe > 1)
1230 return;
1231
92f2584a
JB		 1232 /* PCH only available on ILK+ */
1233 BUG_ON(dev_priv->info->gen < 5);
1234
1235 /* Make sure transcoder isn't still depending on us */
1236 assert_transcoder_disabled(dev_priv, pipe);
1237
7a419866
JB		 1238 if (pipe == 0)
1239 pll_sel |= TRANSC_DPLLA_SEL;
1240 else if (pipe == 1)
1241 pll_sel |= TRANSC_DPLLB_SEL;
1242
1243
1244 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1245 return;
1246
92f2584a
JB		 1247 reg = PCH_DPLL(pipe);
1248 val = I915_READ(reg);
1249 val &= ~DPLL_VCO_ENABLE;
1250 I915_WRITE(reg, val);
1251 POSTING_READ(reg);
1252 udelay(200);
1253}
1254
040484af
JB		 1255static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257{
1258 int reg;
1259 u32 val;
1260
1261 /* PCH only available on ILK+ */
1262 BUG_ON(dev_priv->info->gen < 5);
1263
1264 /* Make sure PCH DPLL is enabled */
1265 assert_pch_pll_enabled(dev_priv, pipe);
1266
1267 /* FDI must be feeding us bits for PCH ports */
1268 assert_fdi_tx_enabled(dev_priv, pipe);
1269 assert_fdi_rx_enabled(dev_priv, pipe);
1270
1271 reg = TRANSCONF(pipe);
1272 val = I915_READ(reg);
e9bcff5c
JB		 1273
1274 if (HAS_PCH_IBX(dev_priv->dev)) {
1275 /*
1276 * make the BPC in transcoder be consistent with
1277 * that in pipeconf reg.
1278 */
1279 val &= ~PIPE_BPC_MASK;
1280 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1281 }
040484af
JB		 1282 I915_WRITE(reg, val | TRANS_ENABLE);
1283 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1284 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1285}
1286
1287static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* FDI relies on the transcoder */
1294 assert_fdi_tx_disabled(dev_priv, pipe);
1295 assert_fdi_rx_disabled(dev_priv, pipe);
1296
291906f1
JB		 1297 /* Ports must be off as well */
1298 assert_pch_ports_disabled(dev_priv, pipe);
1299
040484af
JB		 1300 reg = TRANSCONF(pipe);
1301 val = I915_READ(reg);
1302 val &= ~TRANS_ENABLE;
1303 I915_WRITE(reg, val);
1304 /* wait for PCH transcoder off, transcoder state */
1305 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1306 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1307}
1308
b24e7179 1309/**
309cfea8 1310 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1311 * @dev_priv: i915 private structure
1312 * @pipe: pipe to enable
040484af 1313 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1314 *
1315 * Enable @pipe, making sure that various hardware specific requirements
1316 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1317 *
1318 * @pipe should be %PIPE_A or %PIPE_B.
1319 *
1320 * Will wait until the pipe is actually running (i.e. first vblank) before
1321 * returning.
1322 */
040484af
JB		 1323static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1324 bool pch_port)
b24e7179
JB		 1325{
1326 int reg;
1327 u32 val;
1328
1329 /*
1330 * A pipe without a PLL won't actually be able to drive bits from
1331 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1332 * need the check.
1333 */
1334 if (!HAS_PCH_SPLIT(dev_priv->dev))
1335 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1336 else {
1337 if (pch_port) {
1338 /* if driving the PCH, we need FDI enabled */
1339 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1340 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1341 }
1342 /* FIXME: assert CPU port conditions for SNB+ */
1343 }
b24e7179
JB		 1344
1345 reg = PIPECONF(pipe);
1346 val = I915_READ(reg);
00d70b15
CW		 1347 if (val & PIPECONF_ENABLE)
1348 return;
1349
1350 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1351 intel_wait_for_vblank(dev_priv->dev, pipe);
1352}
1353
1354/**
309cfea8 1355 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe to disable
1358 *
1359 * Disable @pipe, making sure that various hardware specific requirements
1360 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1361 *
1362 * @pipe should be %PIPE_A or %PIPE_B.
1363 *
1364 * Will wait until the pipe has shut down before returning.
1365 */
1366static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1367 enum pipe pipe)
1368{
1369 int reg;
1370 u32 val;
1371
1372 /*
1373 * Make sure planes won't keep trying to pump pixels to us,
1374 * or we might hang the display.
1375 */
1376 assert_planes_disabled(dev_priv, pipe);
1377
1378 /* Don't disable pipe A or pipe A PLLs if needed */
1379 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1380 return;
1381
1382 reg = PIPECONF(pipe);
1383 val = I915_READ(reg);
00d70b15
CW		 1384 if ((val & PIPECONF_ENABLE) == 0)
1385 return;
1386
1387 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1388 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1389}
1390
d74362c9
KP		 1391/*
1392 * Plane regs are double buffered, going from enabled->disabled needs a
1393 * trigger in order to latch. The display address reg provides this.
1394 */
1395static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1396 enum plane plane)
1397{
1398 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1399 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1400}
1401
b24e7179
JB		 1402/**
1403 * intel_enable_plane - enable a display plane on a given pipe
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to enable
1406 * @pipe: pipe being fed
1407 *
1408 * Enable @plane on @pipe, making sure that @pipe is running first.
1409 */
1410static void intel_enable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1417 assert_pipe_enabled(dev_priv, pipe);
1418
1419 reg = DSPCNTR(plane);
1420 val = I915_READ(reg);
00d70b15
CW		 1421 if (val & DISPLAY_PLANE_ENABLE)
1422 return;
1423
1424 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1425 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1426 intel_wait_for_vblank(dev_priv->dev, pipe);
1427}
1428
b24e7179
JB		 1429/**
1430 * intel_disable_plane - disable a display plane
1431 * @dev_priv: i915 private structure
1432 * @plane: plane to disable
1433 * @pipe: pipe consuming the data
1434 *
1435 * Disable @plane; should be an independent operation.
1436 */
1437static void intel_disable_plane(struct drm_i915_private *dev_priv,
1438 enum plane plane, enum pipe pipe)
1439{
1440 int reg;
1441 u32 val;
1442
1443 reg = DSPCNTR(plane);
1444 val = I915_READ(reg);
00d70b15
CW		 1445 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1446 return;
1447
1448 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1449 intel_flush_display_plane(dev_priv, plane);
1450 intel_wait_for_vblank(dev_priv->dev, pipe);
1451}
1452
47a05eca 1453static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1454 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1455{
1456 u32 val = I915_READ(reg);
4e634389 1457 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1458 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1459 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1460 }
47a05eca
JB		 1461}
1462
1463static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg)
1465{
1466 u32 val = I915_READ(reg);
1519b995 1467 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1468 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1469 reg, pipe);
47a05eca 1470 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1471 }
47a05eca
JB		 1472}
1473
1474/* Disable any ports connected to this transcoder */
1475static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1476 enum pipe pipe)
1477{
1478 u32 reg, val;
1479
1480 val = I915_READ(PCH_PP_CONTROL);
1481 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1482
f0575e92
KP		 1483 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1484 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1485 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1486
1487 reg = PCH_ADPA;
1488 val = I915_READ(reg);
1519b995 1489 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1490 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1491
1492 reg = PCH_LVDS;
1493 val = I915_READ(reg);
1519b995
KP		 1494 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1495 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1496 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1497 POSTING_READ(reg);
1498 udelay(100);
1499 }
1500
1501 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1502 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1503 disable_pch_hdmi(dev_priv, pipe, HDMID);
1504}
1505
43a9539f
CW		 1506static void i8xx_disable_fbc(struct drm_device *dev)
1507{
1508 struct drm_i915_private *dev_priv = dev->dev_private;
1509 u32 fbc_ctl;
1510
1511 /* Disable compression */
1512 fbc_ctl = I915_READ(FBC_CONTROL);
1513 if ((fbc_ctl & FBC_CTL_EN) == 0)
1514 return;
1515
1516 fbc_ctl &= ~FBC_CTL_EN;
1517 I915_WRITE(FBC_CONTROL, fbc_ctl);
1518
1519 /* Wait for compressing bit to clear */
1520 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1521 DRM_DEBUG_KMS("FBC idle timed out\n");
1522 return;
1523 }
1524
1525 DRM_DEBUG_KMS("disabled FBC\n");
1526}
1527
80824003
JB		 1528static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1529{
1530 struct drm_device *dev = crtc->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct drm_framebuffer *fb = crtc->fb;
1533 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1534 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1536 int cfb_pitch;
80824003
JB		 1537 int plane, i;
1538 u32 fbc_ctl, fbc_ctl2;
1539
016b9b61 1540 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1541 if (fb->pitches[0] < cfb_pitch)
1542 cfb_pitch = fb->pitches[0];
80824003
JB		 1543
1544 /* FBC_CTL wants 64B units */
016b9b61
CW		 1545 cfb_pitch = (cfb_pitch / 64) - 1;
1546 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1547
1548 /* Clear old tags */
1549 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1550 I915_WRITE(FBC_TAG + (i * 4), 0);
1551
1552 /* Set it up... */
de568510
CW		 1553 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1554 fbc_ctl2 |= plane;
80824003
JB		 1555 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1556 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1557
1558 /* enable it... */
1559 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1560 if (IS_I945GM(dev))
49677901 1561 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1562 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1563 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1564 fbc_ctl |= obj->fence_reg;
80824003
JB		 1565 I915_WRITE(FBC_CONTROL, fbc_ctl);
1566
016b9b61
CW		 1567 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1568 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1569}
1570
ee5382ae 1571static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1572{
80824003
JB		 1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574
1575 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1576}
1577
74dff282
JB		 1578static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1579{
1580 struct drm_device *dev = crtc->dev;
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct drm_framebuffer *fb = crtc->fb;
1583 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1584 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1586 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1587 unsigned long stall_watermark = 200;
1588 u32 dpfc_ctl;
1589
74dff282 1590 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1591 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1592 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1593
74dff282
JB		 1594 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1595 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1596 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1597 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1598
1599 /* enable it... */
1600 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1601
28c97730 1602 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1603}
1604
43a9539f 1605static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1606{
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 u32 dpfc_ctl;
1609
1610 /* Disable compression */
1611 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1612 if (dpfc_ctl & DPFC_CTL_EN) {
1613 dpfc_ctl &= ~DPFC_CTL_EN;
1614 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1615
bed4a673
CW		 1616 DRM_DEBUG_KMS("disabled FBC\n");
1617 }
74dff282
JB		 1618}
1619
ee5382ae 1620static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1621{
74dff282
JB		 1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1625}
1626
4efe0708
JB		 1627static void sandybridge_blit_fbc_update(struct drm_device *dev)
1628{
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 u32 blt_ecoskpd;
1631
1632 /* Make sure blitter notifies FBC of writes */
fcca7926 1633 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1634 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1635 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1636 GEN6_BLITTER_LOCK_SHIFT;
1637 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1638 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1639 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1640 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1641 GEN6_BLITTER_LOCK_SHIFT);
1642 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1643 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1644 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1645}
1646
b52eb4dc
ZY		 1647static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648{
1649 struct drm_device *dev = crtc->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 struct drm_framebuffer *fb = crtc->fb;
1652 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1653 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1655 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1656 unsigned long stall_watermark = 200;
1657 u32 dpfc_ctl;
1658
bed4a673 1659 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1660 dpfc_ctl &= DPFC_RESERVED;
1661 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1662 /* Set persistent mode for front-buffer rendering, ala X. */
1663 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1664 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1665 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1666
b52eb4dc
ZY		 1667 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1668 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1669 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1670 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1671 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1672 /* enable it... */
bed4a673 1673 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1674
9c04f015
YL		 1675 if (IS_GEN6(dev)) {
1676 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1677 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1678 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1679 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1680 }
1681
b52eb4dc
ZY		 1682 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1683}
1684
43a9539f 1685static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1686{
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 u32 dpfc_ctl;
1689
1690 /* Disable compression */
1691 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1692 if (dpfc_ctl & DPFC_CTL_EN) {
1693 dpfc_ctl &= ~DPFC_CTL_EN;
1694 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1695
bed4a673
CW		 1696 DRM_DEBUG_KMS("disabled FBC\n");
1697 }
b52eb4dc
ZY		 1698}
1699
1700static bool ironlake_fbc_enabled(struct drm_device *dev)
1701{
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703
1704 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1705}
1706
ee5382ae
AJ		 1707bool intel_fbc_enabled(struct drm_device *dev)
1708{
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710
1711 if (!dev_priv->display.fbc_enabled)
1712 return false;
1713
1714 return dev_priv->display.fbc_enabled(dev);
1715}
1716
1630fe75
CW		 1717static void intel_fbc_work_fn(struct work_struct *__work)
1718{
1719 struct intel_fbc_work *work =
1720 container_of(to_delayed_work(__work),
1721 struct intel_fbc_work, work);
1722 struct drm_device *dev = work->crtc->dev;
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724
1725 mutex_lock(&dev->struct_mutex);
1726 if (work == dev_priv->fbc_work) {
1727 /* Double check that we haven't switched fb without cancelling
1728 * the prior work.
1729 */
016b9b61 1730 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1731 dev_priv->display.enable_fbc(work->crtc,
1732 work->interval);
1733
016b9b61
CW		 1734 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1735 dev_priv->cfb_fb = work->crtc->fb->base.id;
1736 dev_priv->cfb_y = work->crtc->y;
1737 }
1738
1630fe75
CW		 1739 dev_priv->fbc_work = NULL;
1740 }
1741 mutex_unlock(&dev->struct_mutex);
1742
1743 kfree(work);
1744}
1745
1746static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1747{
1748 if (dev_priv->fbc_work == NULL)
1749 return;
1750
1751 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1752
1753 /* Synchronisation is provided by struct_mutex and checking of
1754 * dev_priv->fbc_work, so we can perform the cancellation
1755 * entirely asynchronously.
1756 */
1757 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1758 /* tasklet was killed before being run, clean up */
1759 kfree(dev_priv->fbc_work);
1760
1761 /* Mark the work as no longer wanted so that if it does
1762 * wake-up (because the work was already running and waiting
1763 * for our mutex), it will discover that is no longer
1764 * necessary to run.
1765 */
1766 dev_priv->fbc_work = NULL;
1767}
1768
43a9539f 1769static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1770{
1630fe75
CW		 1771 struct intel_fbc_work *work;
1772 struct drm_device *dev = crtc->dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1774
1775 if (!dev_priv->display.enable_fbc)
1776 return;
1777
1630fe75
CW		 1778 intel_cancel_fbc_work(dev_priv);
1779
1780 work = kzalloc(sizeof *work, GFP_KERNEL);
1781 if (work == NULL) {
1782 dev_priv->display.enable_fbc(crtc, interval);
1783 return;
1784 }
1785
1786 work->crtc = crtc;
1787 work->fb = crtc->fb;
1788 work->interval = interval;
1789 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1790
1791 dev_priv->fbc_work = work;
1792
1793 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1794
1795 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1796 * display to settle before starting the compression. Note that
1797 * this delay also serves a second purpose: it allows for a
1798 * vblank to pass after disabling the FBC before we attempt
1799 * to modify the control registers.
1630fe75
CW		 1800 *
1801 * A more complicated solution would involve tracking vblanks
1802 * following the termination of the page-flipping sequence
1803 * and indeed performing the enable as a co-routine and not
1804 * waiting synchronously upon the vblank.
1805 */
1806 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1807}
1808
1809void intel_disable_fbc(struct drm_device *dev)
1810{
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812
1630fe75
CW		 1813 intel_cancel_fbc_work(dev_priv);
1814
ee5382ae
AJ		 1815 if (!dev_priv->display.disable_fbc)
1816 return;
1817
1818 dev_priv->display.disable_fbc(dev);
016b9b61 1819 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1820}
1821
80824003
JB		 1822/**
1823 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1824 * @dev: the drm_device
80824003
JB		 1825 *
1826 * Set up the framebuffer compression hardware at mode set time. We
1827 * enable it if possible:
1828 * - plane A only (on pre-965)
1829 * - no pixel mulitply/line duplication
1830 * - no alpha buffer discard
1831 * - no dual wide
1832 * - framebuffer <= 2048 in width, 1536 in height
1833 *
1834 * We can't assume that any compression will take place (worst case),
1835 * so the compressed buffer has to be the same size as the uncompressed
1836 * one. It also must reside (along with the line length buffer) in
1837 * stolen memory.
1838 *
1839 * We need to enable/disable FBC on a global basis.
1840 */
bed4a673 1841static void intel_update_fbc(struct drm_device *dev)
80824003 1842{
80824003 1843 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1844 struct drm_crtc *crtc = NULL, *tmp_crtc;
1845 struct intel_crtc *intel_crtc;
1846 struct drm_framebuffer *fb;
80824003 1847 struct intel_framebuffer *intel_fb;
05394f39 1848 struct drm_i915_gem_object *obj;
cd0de039 1849 int enable_fbc;
9c928d16
JB		 1850
1851 DRM_DEBUG_KMS("\n");
80824003
JB		 1852
1853 if (!i915_powersave)
1854 return;
1855
ee5382ae 1856 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1857 return;
1858
80824003
JB		 1859 /*
1860 * If FBC is already on, we just have to verify that we can
1861 * keep it that way...
1862 * Need to disable if:
9c928d16 1863 * - more than one pipe is active
80824003
JB		 1864 * - changing FBC params (stride, fence, mode)
1865 * - new fb is too large to fit in compressed buffer
1866 * - going to an unsupported config (interlace, pixel multiply, etc.)
1867 */
9c928d16 1868 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1869 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1870 if (crtc) {
1871 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1872 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1873 goto out_disable;
1874 }
1875 crtc = tmp_crtc;
1876 }
9c928d16 1877 }
bed4a673
CW		 1878
1879 if (!crtc || crtc->fb == NULL) {
1880 DRM_DEBUG_KMS("no output, disabling\n");
1881 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1882 goto out_disable;
1883 }
bed4a673
CW		 1884
1885 intel_crtc = to_intel_crtc(crtc);
1886 fb = crtc->fb;
1887 intel_fb = to_intel_framebuffer(fb);
05394f39 1888 obj = intel_fb->obj;
bed4a673 1889
cd0de039
KP		 1890 enable_fbc = i915_enable_fbc;
1891 if (enable_fbc < 0) {
1892 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1893 enable_fbc = 1;
1894 if (INTEL_INFO(dev)->gen <= 5)
1895 enable_fbc = 0;
1896 }
1897 if (!enable_fbc) {
1898 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1899 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1900 goto out_disable;
1901 }
05394f39 1902 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1903 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1904 "compression\n");
b5e50c3f 1905 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1906 goto out_disable;
1907 }
bed4a673
CW		 1908 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1909 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1910 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1911 "disabling\n");
b5e50c3f 1912 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1913 goto out_disable;
1914 }
bed4a673
CW		 1915 if ((crtc->mode.hdisplay > 2048) ||
1916 (crtc->mode.vdisplay > 1536)) {
28c97730 1917 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1918 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1919 goto out_disable;
1920 }
bed4a673 1921 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1922 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1923 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1924 goto out_disable;
1925 }
de568510
CW		 1926
1927 /* The use of a CPU fence is mandatory in order to detect writes
1928 * by the CPU to the scanout and trigger updates to the FBC.
1929 */
1930 if (obj->tiling_mode != I915_TILING_X ||
1931 obj->fence_reg == I915_FENCE_REG_NONE) {
1932 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1933 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1934 goto out_disable;
1935 }
1936
c924b934
JW		 1937 /* If the kernel debugger is active, always disable compression */
1938 if (in_dbg_master())
1939 goto out_disable;
1940
016b9b61
CW		 1941 /* If the scanout has not changed, don't modify the FBC settings.
1942 * Note that we make the fundamental assumption that the fb->obj
1943 * cannot be unpinned (and have its GTT offset and fence revoked)
1944 * without first being decoupled from the scanout and FBC disabled.
1945 */
1946 if (dev_priv->cfb_plane == intel_crtc->plane &&
1947 dev_priv->cfb_fb == fb->base.id &&
1948 dev_priv->cfb_y == crtc->y)
1949 return;
1950
1951 if (intel_fbc_enabled(dev)) {
1952 /* We update FBC along two paths, after changing fb/crtc
1953 * configuration (modeswitching) and after page-flipping
1954 * finishes. For the latter, we know that not only did
1955 * we disable the FBC at the start of the page-flip
1956 * sequence, but also more than one vblank has passed.
1957 *
1958 * For the former case of modeswitching, it is possible
1959 * to switch between two FBC valid configurations
1960 * instantaneously so we do need to disable the FBC
1961 * before we can modify its control registers. We also
1962 * have to wait for the next vblank for that to take
1963 * effect. However, since we delay enabling FBC we can
1964 * assume that a vblank has passed since disabling and
1965 * that we can safely alter the registers in the deferred
1966 * callback.
1967 *
1968 * In the scenario that we go from a valid to invalid
1969 * and then back to valid FBC configuration we have
1970 * no strict enforcement that a vblank occurred since
1971 * disabling the FBC. However, along all current pipe
1972 * disabling paths we do need to wait for a vblank at
1973 * some point. And we wait before enabling FBC anyway.
1974 */
1975 DRM_DEBUG_KMS("disabling active FBC for update\n");
1976 intel_disable_fbc(dev);
1977 }
1978
bed4a673 1979 intel_enable_fbc(crtc, 500);
80824003
JB		 1980 return;
1981
1982out_disable:
80824003 1983 /* Multiple disables should be harmless */
a939406f
CW		 1984 if (intel_fbc_enabled(dev)) {
1985 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1986 intel_disable_fbc(dev);
a939406f 1987 }
80824003
JB		 1988}
1989
127bd2ac 1990int
48b956c5 1991intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1992 struct drm_i915_gem_object *obj,
919926ae 1993 struct intel_ring_buffer *pipelined)
6b95a207 1994{
ce453d81 1995 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1996 u32 alignment;
1997 int ret;
1998
05394f39 1999 switch (obj->tiling_mode) {
6b95a207 2000 case I915_TILING_NONE:
534843da
CW		 2001 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2002 alignment = 128 * 1024;
a6c45cf0 2003 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2004 alignment = 4 * 1024;
2005 else
2006 alignment = 64 * 1024;
6b95a207
KH		 2007 break;
2008 case I915_TILING_X:
2009 /* pin() will align the object as required by fence */
2010 alignment = 0;
2011 break;
2012 case I915_TILING_Y:
2013 /* FIXME: Is this true? */
2014 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2015 return -EINVAL;
2016 default:
2017 BUG();
2018 }
2019
ce453d81 2020 dev_priv->mm.interruptible = false;
2da3b9b9 2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2022 if (ret)
ce453d81 2023 goto err_interruptible;
6b95a207
KH		 2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
05394f39 2030 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2031 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2032 if (ret)
2033 goto err_unpin;
6b95a207
KH		 2034 }
2035
ce453d81 2036 dev_priv->mm.interruptible = true;
6b95a207 2037 return 0;
48b956c5
CW		 2038
2039err_unpin:
2040 i915_gem_object_unpin(obj);
ce453d81
CW		 2041err_interruptible:
2042 dev_priv->mm.interruptible = true;
48b956c5 2043 return ret;
6b95a207
KH		 2044}
2045
17638cd6
JB		 2046static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2047 int x, int y)
81255565
JB		 2048{
2049 struct drm_device *dev = crtc->dev;
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2052 struct intel_framebuffer *intel_fb;
05394f39 2053 struct drm_i915_gem_object *obj;
81255565
JB		 2054 int plane = intel_crtc->plane;
2055 unsigned long Start, Offset;
81255565 2056 u32 dspcntr;
5eddb70b 2057 u32 reg;
81255565
JB		 2058
2059 switch (plane) {
2060 case 0:
2061 case 1:
2062 break;
2063 default:
2064 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2065 return -EINVAL;
2066 }
2067
2068 intel_fb = to_intel_framebuffer(fb);
2069 obj = intel_fb->obj;
81255565 2070
5eddb70b
CW		 2071 reg = DSPCNTR(plane);
2072 dspcntr = I915_READ(reg);
81255565
JB		 2073 /* Mask out pixel format bits in case we change it */
2074 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2075 switch (fb->bits_per_pixel) {
2076 case 8:
2077 dspcntr |= DISPPLANE_8BPP;
2078 break;
2079 case 16:
2080 if (fb->depth == 15)
2081 dspcntr |= DISPPLANE_15_16BPP;
2082 else
2083 dspcntr |= DISPPLANE_16BPP;
2084 break;
2085 case 24:
2086 case 32:
2087 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2088 break;
2089 default:
17638cd6 2090 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2091 return -EINVAL;
2092 }
a6c45cf0 2093 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2094 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2095 dspcntr |= DISPPLANE_TILED;
2096 else
2097 dspcntr &= ~DISPPLANE_TILED;
2098 }
2099
5eddb70b 2100 I915_WRITE(reg, dspcntr);
81255565 2101
05394f39 2102 Start = obj->gtt_offset;
01f2c773 2103 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2104
4e6cfefc 2105 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2106 Start, Offset, x, y, fb->pitches[0]);
2107 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2108 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2109 I915_WRITE(DSPSURF(plane), Start);
2110 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2111 I915_WRITE(DSPADDR(plane), Offset);
2112 } else
2113 I915_WRITE(DSPADDR(plane), Start + Offset);
2114 POSTING_READ(reg);
81255565 2115
17638cd6
JB		 2116 return 0;
2117}
2118
2119static int ironlake_update_plane(struct drm_crtc *crtc,
2120 struct drm_framebuffer *fb, int x, int y)
2121{
2122 struct drm_device *dev = crtc->dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2125 struct intel_framebuffer *intel_fb;
2126 struct drm_i915_gem_object *obj;
2127 int plane = intel_crtc->plane;
2128 unsigned long Start, Offset;
2129 u32 dspcntr;
2130 u32 reg;
2131
2132 switch (plane) {
2133 case 0:
2134 case 1:
27f8227b 2135 case 2:
17638cd6
JB		 2136 break;
2137 default:
2138 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2139 return -EINVAL;
2140 }
2141
2142 intel_fb = to_intel_framebuffer(fb);
2143 obj = intel_fb->obj;
2144
2145 reg = DSPCNTR(plane);
2146 dspcntr = I915_READ(reg);
2147 /* Mask out pixel format bits in case we change it */
2148 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2149 switch (fb->bits_per_pixel) {
2150 case 8:
2151 dspcntr |= DISPPLANE_8BPP;
2152 break;
2153 case 16:
2154 if (fb->depth != 16)
2155 return -EINVAL;
2156
2157 dspcntr |= DISPPLANE_16BPP;
2158 break;
2159 case 24:
2160 case 32:
2161 if (fb->depth == 24)
2162 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2163 else if (fb->depth == 30)
2164 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2165 else
2166 return -EINVAL;
2167 break;
2168 default:
2169 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
2183 Start = obj->gtt_offset;
01f2c773 2184 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2185
2186 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2187 Start, Offset, x, y, fb->pitches[0]);
2188 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2189 I915_WRITE(DSPSURF(plane), Start);
2190 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2191 I915_WRITE(DSPADDR(plane), Offset);
2192 POSTING_READ(reg);
2193
2194 return 0;
2195}
2196
2197/* Assume fb object is pinned & idle & fenced and just update base pointers */
2198static int
2199intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2200 int x, int y, enum mode_set_atomic state)
2201{
2202 struct drm_device *dev = crtc->dev;
2203 struct drm_i915_private *dev_priv = dev->dev_private;
2204 int ret;
2205
2206 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2207 if (ret)
2208 return ret;
2209
bed4a673 2210 intel_update_fbc(dev);
3dec0095 2211 intel_increase_pllclock(crtc);
81255565
JB		 2212
2213 return 0;
2214}
2215
5c3b82e2 2216static int
3c4fdcfb
KH		 2217intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2218 struct drm_framebuffer *old_fb)
79e53945
JB		 2219{
2220 struct drm_device *dev = crtc->dev;
79e53945
JB		 2221 struct drm_i915_master_private *master_priv;
2222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2223 int ret;
79e53945
JB		 2224
2225 /* no fb bound */
2226 if (!crtc->fb) {
a5071c2f 2227 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2228 return 0;
2229 }
2230
265db958 2231 switch (intel_crtc->plane) {
5c3b82e2
CW		 2232 case 0:
2233 case 1:
2234 break;
27f8227b
JB		 2235 case 2:
2236 if (IS_IVYBRIDGE(dev))
2237 break;
2238 /* fall through otherwise */
5c3b82e2 2239 default:
a5071c2f 2240 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2241 return -EINVAL;
79e53945
JB		 2242 }
2243
5c3b82e2 2244 mutex_lock(&dev->struct_mutex);
265db958
CW		 2245 ret = intel_pin_and_fence_fb_obj(dev,
2246 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2247 NULL);
5c3b82e2
CW		 2248 if (ret != 0) {
2249 mutex_unlock(&dev->struct_mutex);
a5071c2f 2250 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2251 return ret;
2252 }
79e53945 2253
265db958 2254 if (old_fb) {
e6c3a2a6 2255 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2256 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2257
e6c3a2a6 2258 wait_event(dev_priv->pending_flip_queue,
01eec727 2259 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2260 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2261
2262 /* Big Hammer, we also need to ensure that any pending
2263 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2264 * current scanout is retired before unpinning the old
2265 * framebuffer.
01eec727
CW		 2266 *
2267 * This should only fail upon a hung GPU, in which case we
2268 * can safely continue.
85345517 2269 */
a8198eea 2270 ret = i915_gem_object_finish_gpu(obj);
01eec727 2271 (void) ret;
265db958
CW		 2272 }
2273
21c74a8e
JW		 2274 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2275 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2276 if (ret) {
265db958 2277 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2278 mutex_unlock(&dev->struct_mutex);
a5071c2f 2279 DRM_ERROR("failed to update base address\n");
4e6cfefc 2280 return ret;
79e53945 2281 }
3c4fdcfb 2282
b7f1de28
CW		 2283 if (old_fb) {
2284 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2285 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2286 }
652c393a 2287
5c3b82e2 2288 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2289
2290 if (!dev->primary->master)
5c3b82e2 2291 return 0;
79e53945
JB		 2292
2293 master_priv = dev->primary->master->driver_priv;
2294 if (!master_priv->sarea_priv)
5c3b82e2 2295 return 0;
79e53945 2296
265db958 2297 if (intel_crtc->pipe) {
79e53945
JB		 2298 master_priv->sarea_priv->pipeB_x = x;
2299 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2300 } else {
2301 master_priv->sarea_priv->pipeA_x = x;
2302 master_priv->sarea_priv->pipeA_y = y;
79e53945 2303 }
5c3b82e2
CW		 2304
2305 return 0;
79e53945
JB		 2306}
2307
5eddb70b 2308static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2309{
2310 struct drm_device *dev = crtc->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 u32 dpa_ctl;
2313
28c97730 2314 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2315 dpa_ctl = I915_READ(DP_A);
2316 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2317
2318 if (clock < 200000) {
2319 u32 temp;
2320 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2321 /* workaround for 160Mhz:
2322 1) program 0x4600c bits 15:0 = 0x8124
2323 2) program 0x46010 bit 0 = 1
2324 3) program 0x46034 bit 24 = 1
2325 4) program 0x64000 bit 14 = 1
2326 */
2327 temp = I915_READ(0x4600c);
2328 temp &= 0xffff0000;
2329 I915_WRITE(0x4600c, temp | 0x8124);
2330
2331 temp = I915_READ(0x46010);
2332 I915_WRITE(0x46010, temp | 1);
2333
2334 temp = I915_READ(0x46034);
2335 I915_WRITE(0x46034, temp | (1 << 24));
2336 } else {
2337 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2338 }
2339 I915_WRITE(DP_A, dpa_ctl);
2340
5eddb70b 2341 POSTING_READ(DP_A);
32f9d658
ZW		 2342 udelay(500);
2343}
2344
5e84e1a4
ZW		 2345static void intel_fdi_normal_train(struct drm_crtc *crtc)
2346{
2347 struct drm_device *dev = crtc->dev;
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 int pipe = intel_crtc->pipe;
2351 u32 reg, temp;
2352
2353 /* enable normal train */
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
61e499bf 2356 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2357 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2358 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2362 }
5e84e1a4
ZW		 2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 if (HAS_PCH_CPT(dev)) {
2368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2369 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2370 } else {
2371 temp &= ~FDI_LINK_TRAIN_NONE;
2372 temp |= FDI_LINK_TRAIN_NONE;
2373 }
2374 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2375
2376 /* wait one idle pattern time */
2377 POSTING_READ(reg);
2378 udelay(1000);
357555c0
JB		 2379
2380 /* IVB wants error correction enabled */
2381 if (IS_IVYBRIDGE(dev))
2382 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2383 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2384}
2385
291427f5
JB		 2386static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2387{
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 u32 flags = I915_READ(SOUTH_CHICKEN1);
2390
2391 flags |= FDI_PHASE_SYNC_OVR(pipe);
2392 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2393 flags |= FDI_PHASE_SYNC_EN(pipe);
2394 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2395 POSTING_READ(SOUTH_CHICKEN1);
2396}
2397
8db9d77b
ZW		 2398/* The FDI link training functions for ILK/Ibexpeak. */
2399static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2400{
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404 int pipe = intel_crtc->pipe;
0fc932b8 2405 int plane = intel_crtc->plane;
5eddb70b 2406 u32 reg, temp, tries;
8db9d77b 2407
0fc932b8
JB		 2408 /* FDI needs bits from pipe & plane first */
2409 assert_pipe_enabled(dev_priv, pipe);
2410 assert_plane_enabled(dev_priv, plane);
2411
e1a44743
AJ		 2412 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2413 for train result */
5eddb70b
CW		 2414 reg = FDI_RX_IMR(pipe);
2415 temp = I915_READ(reg);
e1a44743
AJ		 2416 temp &= ~FDI_RX_SYMBOL_LOCK;
2417 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2418 I915_WRITE(reg, temp);
2419 I915_READ(reg);
e1a44743
AJ		 2420 udelay(150);
2421
8db9d77b 2422 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
77ffb597
AJ		 2425 temp &= ~(7 << 19);
2426 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2429 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2430
5eddb70b
CW		 2431 reg = FDI_RX_CTL(pipe);
2432 temp = I915_READ(reg);
8db9d77b
ZW		 2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2435 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437 POSTING_READ(reg);
8db9d77b
ZW		 2438 udelay(150);
2439
5b2adf89 2440 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2441 if (HAS_PCH_IBX(dev)) {
2442 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2443 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2444 FDI_RX_PHASE_SYNC_POINTER_EN);
2445 }
5b2adf89 2446
5eddb70b 2447 reg = FDI_RX_IIR(pipe);
e1a44743 2448 for (tries = 0; tries < 5; tries++) {
5eddb70b 2449 temp = I915_READ(reg);
8db9d77b
ZW		 2450 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2451
2452 if ((temp & FDI_RX_BIT_LOCK)) {
2453 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2454 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2455 break;
2456 }
8db9d77b 2457 }
e1a44743 2458 if (tries == 5)
5eddb70b 2459 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2460
2461 /* Train 2 */
5eddb70b
CW		 2462 reg = FDI_TX_CTL(pipe);
2463 temp = I915_READ(reg);
8db9d77b
ZW		 2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2466 I915_WRITE(reg, temp);
8db9d77b 2467
5eddb70b
CW		 2468 reg = FDI_RX_CTL(pipe);
2469 temp = I915_READ(reg);
8db9d77b
ZW		 2470 temp &= ~FDI_LINK_TRAIN_NONE;
2471 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2472 I915_WRITE(reg, temp);
8db9d77b 2473
5eddb70b
CW		 2474 POSTING_READ(reg);
2475 udelay(150);
8db9d77b 2476
5eddb70b 2477 reg = FDI_RX_IIR(pipe);
e1a44743 2478 for (tries = 0; tries < 5; tries++) {
5eddb70b 2479 temp = I915_READ(reg);
8db9d77b
ZW		 2480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2481
2482 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2483 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2484 DRM_DEBUG_KMS("FDI train 2 done.\n");
2485 break;
2486 }
8db9d77b 2487 }
e1a44743 2488 if (tries == 5)
5eddb70b 2489 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2490
2491 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2492
8db9d77b
ZW		 2493}
2494
0206e353 2495static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2496 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2497 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2498 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2499 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2500};
2501
2502/* The FDI link training functions for SNB/Cougarpoint. */
2503static void gen6_fdi_link_train(struct drm_crtc *crtc)
2504{
2505 struct drm_device *dev = crtc->dev;
2506 struct drm_i915_private *dev_priv = dev->dev_private;
2507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2508 int pipe = intel_crtc->pipe;
5eddb70b 2509 u32 reg, temp, i;
8db9d77b 2510
e1a44743
AJ		 2511 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2512 for train result */
5eddb70b
CW		 2513 reg = FDI_RX_IMR(pipe);
2514 temp = I915_READ(reg);
e1a44743
AJ		 2515 temp &= ~FDI_RX_SYMBOL_LOCK;
2516 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
e1a44743
AJ		 2520 udelay(150);
2521
8db9d77b 2522 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
77ffb597
AJ		 2525 temp &= ~(7 << 19);
2526 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_1;
2529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2530 /* SNB-B */
2531 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2532 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
291427f5
JB		 2548 if (HAS_PCH_CPT(dev))
2549 cpt_phase_pointer_enable(dev, pipe);
2550
0206e353 2551 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2552 reg = FDI_TX_CTL(pipe);
2553 temp = I915_READ(reg);
8db9d77b
ZW		 2554 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2555 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2556 I915_WRITE(reg, temp);
2557
2558 POSTING_READ(reg);
8db9d77b
ZW		 2559 udelay(500);
2560
5eddb70b
CW		 2561 reg = FDI_RX_IIR(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2564
2565 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2566 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2567 DRM_DEBUG_KMS("FDI train 1 done.\n");
2568 break;
2569 }
2570 }
2571 if (i == 4)
5eddb70b 2572 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2573
2574 /* Train 2 */
5eddb70b
CW		 2575 reg = FDI_TX_CTL(pipe);
2576 temp = I915_READ(reg);
8db9d77b
ZW		 2577 temp &= ~FDI_LINK_TRAIN_NONE;
2578 temp |= FDI_LINK_TRAIN_PATTERN_2;
2579 if (IS_GEN6(dev)) {
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 /* SNB-B */
2582 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2583 }
5eddb70b 2584 I915_WRITE(reg, temp);
8db9d77b 2585
5eddb70b
CW		 2586 reg = FDI_RX_CTL(pipe);
2587 temp = I915_READ(reg);
8db9d77b
ZW		 2588 if (HAS_PCH_CPT(dev)) {
2589 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2590 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2591 } else {
2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 }
5eddb70b
CW		 2595 I915_WRITE(reg, temp);
2596
2597 POSTING_READ(reg);
8db9d77b
ZW		 2598 udelay(150);
2599
0206e353 2600 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2601 reg = FDI_TX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2604 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
8db9d77b
ZW		 2608 udelay(500);
2609
5eddb70b
CW		 2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
8db9d77b
ZW		 2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613
2614 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2615 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2616 DRM_DEBUG_KMS("FDI train 2 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
5eddb70b 2621 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2622
2623 DRM_DEBUG_KMS("FDI train done.\n");
2624}
2625
357555c0
JB		 2626/* Manual link training for Ivy Bridge A0 parts */
2627static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2628{
2629 struct drm_device *dev = crtc->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2632 int pipe = intel_crtc->pipe;
2633 u32 reg, temp, i;
2634
2635 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2636 for train result */
2637 reg = FDI_RX_IMR(pipe);
2638 temp = I915_READ(reg);
2639 temp &= ~FDI_RX_SYMBOL_LOCK;
2640 temp &= ~FDI_RX_BIT_LOCK;
2641 I915_WRITE(reg, temp);
2642
2643 POSTING_READ(reg);
2644 udelay(150);
2645
2646 /* enable CPU FDI TX and PCH FDI RX */
2647 reg = FDI_TX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~(7 << 19);
2650 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2652 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2653 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2654 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2655 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2656 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2657
2658 reg = FDI_RX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_AUTO;
2661 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2662 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2663 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2664 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2665
2666 POSTING_READ(reg);
2667 udelay(150);
2668
291427f5
JB		 2669 if (HAS_PCH_CPT(dev))
2670 cpt_phase_pointer_enable(dev, pipe);
2671
0206e353 2672 for (i = 0; i < 4; i++) {
357555c0
JB		 2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= snb_b_fdi_train_param[i];
2677 I915_WRITE(reg, temp);
2678
2679 POSTING_READ(reg);
2680 udelay(500);
2681
2682 reg = FDI_RX_IIR(pipe);
2683 temp = I915_READ(reg);
2684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685
2686 if (temp & FDI_RX_BIT_LOCK ||
2687 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2688 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2689 DRM_DEBUG_KMS("FDI train 1 done.\n");
2690 break;
2691 }
2692 }
2693 if (i == 4)
2694 DRM_ERROR("FDI train 1 fail!\n");
2695
2696 /* Train 2 */
2697 reg = FDI_TX_CTL(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2700 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2703 I915_WRITE(reg, temp);
2704
2705 reg = FDI_RX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2709 I915_WRITE(reg, temp);
2710
2711 POSTING_READ(reg);
2712 udelay(150);
2713
0206e353 2714 for (i = 0; i < 4; i++) {
357555c0
JB		 2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2718 temp |= snb_b_fdi_train_param[i];
2719 I915_WRITE(reg, temp);
2720
2721 POSTING_READ(reg);
2722 udelay(500);
2723
2724 reg = FDI_RX_IIR(pipe);
2725 temp = I915_READ(reg);
2726 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2727
2728 if (temp & FDI_RX_SYMBOL_LOCK) {
2729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2730 DRM_DEBUG_KMS("FDI train 2 done.\n");
2731 break;
2732 }
2733 }
2734 if (i == 4)
2735 DRM_ERROR("FDI train 2 fail!\n");
2736
2737 DRM_DEBUG_KMS("FDI train done.\n");
2738}
2739
2740static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2741{
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745 int pipe = intel_crtc->pipe;
5eddb70b 2746 u32 reg, temp;
79e53945 2747
c64e311e 2748 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2749 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2750 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2751
c98e9dcf 2752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2753 reg = FDI_RX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2756 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2757 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2759
2760 POSTING_READ(reg);
c98e9dcf
JB		 2761 udelay(200);
2762
2763 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2764 temp = I915_READ(reg);
2765 I915_WRITE(reg, temp | FDI_PCDCLK);
2766
2767 POSTING_READ(reg);
c98e9dcf
JB		 2768 udelay(200);
2769
2770 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
c98e9dcf 2773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2775
2776 POSTING_READ(reg);
c98e9dcf 2777 udelay(100);
6be4a607 2778 }
0e23b99d
JB		 2779}
2780
291427f5
JB		 2781static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2782{
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 u32 flags = I915_READ(SOUTH_CHICKEN1);
2785
2786 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2787 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2788 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2789 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2790 POSTING_READ(SOUTH_CHICKEN1);
2791}
0fc932b8
JB		 2792static void ironlake_fdi_disable(struct drm_crtc *crtc)
2793{
2794 struct drm_device *dev = crtc->dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* disable CPU FDI tx and PCH FDI rx */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2804 POSTING_READ(reg);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 temp &= ~(0x7 << 16);
2809 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2810 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2811
2812 POSTING_READ(reg);
2813 udelay(100);
2814
2815 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2816 if (HAS_PCH_IBX(dev)) {
2817 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2818 I915_WRITE(FDI_RX_CHICKEN(pipe),
2819 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2820 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2821 } else if (HAS_PCH_CPT(dev)) {
2822 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2823 }
0fc932b8
JB		 2824
2825 /* still set train pattern 1 */
2826 reg = FDI_TX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~FDI_LINK_TRAIN_NONE;
2829 temp |= FDI_LINK_TRAIN_PATTERN_1;
2830 I915_WRITE(reg, temp);
2831
2832 reg = FDI_RX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 if (HAS_PCH_CPT(dev)) {
2835 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2836 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2837 } else {
2838 temp &= ~FDI_LINK_TRAIN_NONE;
2839 temp |= FDI_LINK_TRAIN_PATTERN_1;
2840 }
2841 /* BPC in FDI rx is consistent with that in PIPECONF */
2842 temp &= ~(0x07 << 16);
2843 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2844 I915_WRITE(reg, temp);
2845
2846 POSTING_READ(reg);
2847 udelay(100);
2848}
2849
6b383a7f
CW		 2850/*
2851 * When we disable a pipe, we need to clear any pending scanline wait events
2852 * to avoid hanging the ring, which we assume we are waiting on.
2853 */
2854static void intel_clear_scanline_wait(struct drm_device *dev)
2855{
2856 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2857 struct intel_ring_buffer *ring;
6b383a7f
CW		 2858 u32 tmp;
2859
2860 if (IS_GEN2(dev))
2861 /* Can't break the hang on i8xx */
2862 return;
2863
1ec14ad3 2864 ring = LP_RING(dev_priv);
8168bd48
CW		 2865 tmp = I915_READ_CTL(ring);
2866 if (tmp & RING_WAIT)
2867 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2868}
2869
e6c3a2a6
CW		 2870static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2871{
05394f39 2872 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2873 struct drm_i915_private *dev_priv;
2874
2875 if (crtc->fb == NULL)
2876 return;
2877
05394f39 2878 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2879 dev_priv = crtc->dev->dev_private;
2880 wait_event(dev_priv->pending_flip_queue,
05394f39 2881 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2882}
2883
040484af
JB		 2884static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2885{
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_mode_config *mode_config = &dev->mode_config;
2888 struct intel_encoder *encoder;
2889
2890 /*
2891 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2892 * must be driven by its own crtc; no sharing is possible.
2893 */
2894 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2895 if (encoder->base.crtc != crtc)
2896 continue;
2897
2898 switch (encoder->type) {
2899 case INTEL_OUTPUT_EDP:
2900 if (!intel_encoder_is_pch_edp(&encoder->base))
2901 return false;
2902 continue;
2903 }
2904 }
2905
2906 return true;
2907}
2908
f67a559d
JB		 2909/*
2910 * Enable PCH resources required for PCH ports:
2911 * - PCH PLLs
2912 * - FDI training & RX/TX
2913 * - update transcoder timings
2914 * - DP transcoding bits
2915 * - transcoder
2916 */
2917static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2918{
2919 struct drm_device *dev = crtc->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922 int pipe = intel_crtc->pipe;
4b645f14 2923 u32 reg, temp, transc_sel;
2c07245f 2924
c98e9dcf 2925 /* For PCH output, training FDI link */
674cf967 2926 dev_priv->display.fdi_link_train(crtc);
2c07245f 2927
92f2584a 2928 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2929
c98e9dcf 2930 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2931 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2932 TRANSC_DPLLB_SEL;
2933
c98e9dcf
JB		 2934 /* Be sure PCH DPLL SEL is set */
2935 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2936 if (pipe == 0) {
2937 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2938 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2939 } else if (pipe == 1) {
2940 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2941 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2942 } else if (pipe == 2) {
2943 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2944 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2945 }
c98e9dcf 2946 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2947 }
5eddb70b 2948
d9b6cb56
JB		 2949 /* set transcoder timing, panel must allow it */
2950 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2951 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2952 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2953 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2954
5eddb70b
CW		 2955 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2956 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2957 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2958
5e84e1a4
ZW		 2959 intel_fdi_normal_train(crtc);
2960
c98e9dcf
JB		 2961 /* For PCH DP, enable TRANS_DP_CTL */
2962 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2963 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2964 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2965 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2966 reg = TRANS_DP_CTL(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2969 TRANS_DP_SYNC_MASK |
2970 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2971 temp |= (TRANS_DP_OUTPUT_ENABLE |
2972 TRANS_DP_ENH_FRAMING);
9325c9f0 2973 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2974
2975 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2976 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2977 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2978 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2979
2980 switch (intel_trans_dp_port_sel(crtc)) {
2981 case PCH_DP_B:
5eddb70b 2982 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2983 break;
2984 case PCH_DP_C:
5eddb70b 2985 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2986 break;
2987 case PCH_DP_D:
5eddb70b 2988 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2989 break;
2990 default:
2991 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2992 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2993 break;
32f9d658 2994 }
2c07245f 2995
5eddb70b 2996 I915_WRITE(reg, temp);
6be4a607 2997 }
b52eb4dc 2998
040484af 2999 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3000}
3001
d4270e57
JB		 3002void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3003{
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3006 u32 temp;
3007
3008 temp = I915_READ(dslreg);
3009 udelay(500);
3010 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3011 /* Without this, mode sets may fail silently on FDI */
3012 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3013 udelay(250);
3014 I915_WRITE(tc2reg, 0);
3015 if (wait_for(I915_READ(dslreg) != temp, 5))
3016 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3017 }
3018}
3019
f67a559d
JB		 3020static void ironlake_crtc_enable(struct drm_crtc *crtc)
3021{
3022 struct drm_device *dev = crtc->dev;
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025 int pipe = intel_crtc->pipe;
3026 int plane = intel_crtc->plane;
3027 u32 temp;
3028 bool is_pch_port;
3029
3030 if (intel_crtc->active)
3031 return;
3032
3033 intel_crtc->active = true;
3034 intel_update_watermarks(dev);
3035
3036 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3037 temp = I915_READ(PCH_LVDS);
3038 if ((temp & LVDS_PORT_EN) == 0)
3039 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3040 }
3041
3042 is_pch_port = intel_crtc_driving_pch(crtc);
3043
3044 if (is_pch_port)
357555c0 3045 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3046 else
3047 ironlake_fdi_disable(crtc);
3048
3049 /* Enable panel fitting for LVDS */
3050 if (dev_priv->pch_pf_size &&
3051 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3052 /* Force use of hard-coded filter coefficients
3053 * as some pre-programmed values are broken,
3054 * e.g. x201.
3055 */
9db4a9c7
JB		 3056 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3057 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3058 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3059 }
3060
9c54c0dd
JB		 3061 /*
3062 * On ILK+ LUT must be loaded before the pipe is running but with
3063 * clocks enabled
3064 */
3065 intel_crtc_load_lut(crtc);
3066
f67a559d
JB		 3067 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3068 intel_enable_plane(dev_priv, plane, pipe);
3069
3070 if (is_pch_port)
3071 ironlake_pch_enable(crtc);
c98e9dcf 3072
d1ebd816 3073 mutex_lock(&dev->struct_mutex);
bed4a673 3074 intel_update_fbc(dev);
d1ebd816
BW		 3075 mutex_unlock(&dev->struct_mutex);
3076
6b383a7f 3077 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3078}
3079
3080static void ironlake_crtc_disable(struct drm_crtc *crtc)
3081{
3082 struct drm_device *dev = crtc->dev;
3083 struct drm_i915_private *dev_priv = dev->dev_private;
3084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3085 int pipe = intel_crtc->pipe;
3086 int plane = intel_crtc->plane;
5eddb70b 3087 u32 reg, temp;
b52eb4dc 3088
f7abfe8b
CW		 3089 if (!intel_crtc->active)
3090 return;
3091
e6c3a2a6 3092 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3093 drm_vblank_off(dev, pipe);
6b383a7f 3094 intel_crtc_update_cursor(crtc, false);
5eddb70b 3095
b24e7179 3096 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3097
973d04f9
CW		 3098 if (dev_priv->cfb_plane == plane)
3099 intel_disable_fbc(dev);
2c07245f 3100
b24e7179 3101 intel_disable_pipe(dev_priv, pipe);
32f9d658 3102
6be4a607 3103 /* Disable PF */
9db4a9c7
JB		 3104 I915_WRITE(PF_CTL(pipe), 0);
3105 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3106
0fc932b8 3107 ironlake_fdi_disable(crtc);
2c07245f 3108
47a05eca
JB		 3109 /* This is a horrible layering violation; we should be doing this in
3110 * the connector/encoder ->prepare instead, but we don't always have
3111 * enough information there about the config to know whether it will
3112 * actually be necessary or just cause undesired flicker.
3113 */
3114 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3115
040484af 3116 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3117
6be4a607
JB		 3118 if (HAS_PCH_CPT(dev)) {
3119 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3120 reg = TRANS_DP_CTL(pipe);
3121 temp = I915_READ(reg);
3122 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3123 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3124 I915_WRITE(reg, temp);
6be4a607
JB		 3125
3126 /* disable DPLL_SEL */
3127 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3128 switch (pipe) {
3129 case 0:
d64311ab 3130 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3131 break;
3132 case 1:
6be4a607 3133 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3134 break;
3135 case 2:
4b645f14 3136 /* C shares PLL A or B */
d64311ab 3137 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3138 break;
3139 default:
3140 BUG(); /* wtf */
3141 }
6be4a607 3142 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3143 }
e3421a18 3144
6be4a607 3145 /* disable PCH DPLL */
4b645f14
JB		 3146 if (!intel_crtc->no_pll)
3147 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3148
6be4a607 3149 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3150 reg = FDI_RX_CTL(pipe);
3151 temp = I915_READ(reg);
3152 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3153
6be4a607 3154 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3158
3159 POSTING_READ(reg);
6be4a607 3160 udelay(100);
8db9d77b 3161
5eddb70b
CW		 3162 reg = FDI_RX_CTL(pipe);
3163 temp = I915_READ(reg);
3164 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3165
6be4a607 3166 /* Wait for the clocks to turn off. */
5eddb70b 3167 POSTING_READ(reg);
6be4a607 3168 udelay(100);
6b383a7f 3169
f7abfe8b 3170 intel_crtc->active = false;
6b383a7f 3171 intel_update_watermarks(dev);
d1ebd816
BW		 3172
3173 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3174 intel_update_fbc(dev);
3175 intel_clear_scanline_wait(dev);
d1ebd816 3176 mutex_unlock(&dev->struct_mutex);
6be4a607 3177}
1b3c7a47 3178
6be4a607
JB		 3179static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3180{
3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 int pipe = intel_crtc->pipe;
3183 int plane = intel_crtc->plane;
8db9d77b 3184
6be4a607
JB		 3185 /* XXX: When our outputs are all unaware of DPMS modes other than off
3186 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3187 */
3188 switch (mode) {
3189 case DRM_MODE_DPMS_ON:
3190 case DRM_MODE_DPMS_STANDBY:
3191 case DRM_MODE_DPMS_SUSPEND:
3192 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3193 ironlake_crtc_enable(crtc);
3194 break;
1b3c7a47 3195
6be4a607
JB		 3196 case DRM_MODE_DPMS_OFF:
3197 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3198 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3199 break;
3200 }
3201}
3202
02e792fb
DV		 3203static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3204{
02e792fb 3205 if (!enable && intel_crtc->overlay) {
23f09ce3 3206 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3207 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3208
23f09ce3 3209 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3210 dev_priv->mm.interruptible = false;
3211 (void) intel_overlay_switch_off(intel_crtc->overlay);
3212 dev_priv->mm.interruptible = true;
23f09ce3 3213 mutex_unlock(&dev->struct_mutex);
02e792fb 3214 }
02e792fb 3215
5dcdbcb0
CW		 3216 /* Let userspace switch the overlay on again. In most cases userspace
3217 * has to recompute where to put it anyway.
3218 */
02e792fb
DV		 3219}
3220
0b8765c6 3221static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3222{
3223 struct drm_device *dev = crtc->dev;
79e53945
JB		 3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3226 int pipe = intel_crtc->pipe;
80824003 3227 int plane = intel_crtc->plane;
79e53945 3228
f7abfe8b
CW		 3229 if (intel_crtc->active)
3230 return;
3231
3232 intel_crtc->active = true;
6b383a7f
CW		 3233 intel_update_watermarks(dev);
3234
63d7bbe9 3235 intel_enable_pll(dev_priv, pipe);
040484af 3236 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3237 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3238
0b8765c6 3239 intel_crtc_load_lut(crtc);
bed4a673 3240 intel_update_fbc(dev);
79e53945 3241
0b8765c6
JB		 3242 /* Give the overlay scaler a chance to enable if it's on this pipe */
3243 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3244 intel_crtc_update_cursor(crtc, true);
0b8765c6 3245}
79e53945 3246
0b8765c6
JB		 3247static void i9xx_crtc_disable(struct drm_crtc *crtc)
3248{
3249 struct drm_device *dev = crtc->dev;
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252 int pipe = intel_crtc->pipe;
3253 int plane = intel_crtc->plane;
b690e96c 3254
f7abfe8b
CW		 3255 if (!intel_crtc->active)
3256 return;
3257
0b8765c6 3258 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3259 intel_crtc_wait_for_pending_flips(crtc);
3260 drm_vblank_off(dev, pipe);
0b8765c6 3261 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3262 intel_crtc_update_cursor(crtc, false);
0b8765c6 3263
973d04f9
CW		 3264 if (dev_priv->cfb_plane == plane)
3265 intel_disable_fbc(dev);
79e53945 3266
b24e7179 3267 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3268 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3269 intel_disable_pll(dev_priv, pipe);
0b8765c6 3270
f7abfe8b 3271 intel_crtc->active = false;
6b383a7f
CW		 3272 intel_update_fbc(dev);
3273 intel_update_watermarks(dev);
3274 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3275}
3276
3277static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3278{
3279 /* XXX: When our outputs are all unaware of DPMS modes other than off
3280 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3281 */
3282 switch (mode) {
3283 case DRM_MODE_DPMS_ON:
3284 case DRM_MODE_DPMS_STANDBY:
3285 case DRM_MODE_DPMS_SUSPEND:
3286 i9xx_crtc_enable(crtc);
3287 break;
3288 case DRM_MODE_DPMS_OFF:
3289 i9xx_crtc_disable(crtc);
79e53945
JB		 3290 break;
3291 }
2c07245f
ZW		 3292}
3293
3294/**
3295 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3296 */
3297static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3298{
3299 struct drm_device *dev = crtc->dev;
e70236a8 3300 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3301 struct drm_i915_master_private *master_priv;
3302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303 int pipe = intel_crtc->pipe;
3304 bool enabled;
3305
032d2a0d
CW		 3306 if (intel_crtc->dpms_mode == mode)
3307 return;
3308
65655d4a 3309 intel_crtc->dpms_mode = mode;
debcaddc 3310
e70236a8 3311 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3312
3313 if (!dev->primary->master)
3314 return;
3315
3316 master_priv = dev->primary->master->driver_priv;
3317 if (!master_priv->sarea_priv)
3318 return;
3319
3320 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3321
3322 switch (pipe) {
3323 case 0:
3324 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3325 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3326 break;
3327 case 1:
3328 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3329 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3330 break;
3331 default:
9db4a9c7 3332 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3333 break;
3334 }
79e53945
JB		 3335}
3336
cdd59983
CW		 3337static void intel_crtc_disable(struct drm_crtc *crtc)
3338{
3339 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3340 struct drm_device *dev = crtc->dev;
3341
3342 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3343 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3344 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3345
3346 if (crtc->fb) {
3347 mutex_lock(&dev->struct_mutex);
3348 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3349 mutex_unlock(&dev->struct_mutex);
3350 }
3351}
3352
7e7d76c3
JB		 3353/* Prepare for a mode set.
3354 *
3355 * Note we could be a lot smarter here. We need to figure out which outputs
3356 * will be enabled, which disabled (in short, how the config will changes)
3357 * and perform the minimum necessary steps to accomplish that, e.g. updating
3358 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3359 * panel fitting is in the proper state, etc.
3360 */
3361static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3362{
7e7d76c3 3363 i9xx_crtc_disable(crtc);
79e53945
JB		 3364}
3365
7e7d76c3 3366static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3367{
7e7d76c3 3368 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3369}
3370
3371static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3372{
7e7d76c3 3373 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3374}
3375
3376static void ironlake_crtc_commit(struct drm_crtc *crtc)
3377{
7e7d76c3 3378 ironlake_crtc_enable(crtc);
79e53945
JB		 3379}
3380
0206e353 3381void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3382{
3383 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3384 /* lvds has its own version of prepare see intel_lvds_prepare */
3385 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3386}
3387
0206e353 3388void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3389{
3390 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3391 struct drm_device *dev = encoder->dev;
3392 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3393 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3394
79e53945
JB		 3395 /* lvds has its own version of commit see intel_lvds_commit */
3396 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3397
3398 if (HAS_PCH_CPT(dev))
3399 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3400}
3401
ea5b213a
CW		 3402void intel_encoder_destroy(struct drm_encoder *encoder)
3403{
4ef69c7a 3404 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3405
ea5b213a
CW		 3406 drm_encoder_cleanup(encoder);
3407 kfree(intel_encoder);
3408}
3409
79e53945
JB		 3410static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3411 struct drm_display_mode *mode,
3412 struct drm_display_mode *adjusted_mode)
3413{
2c07245f 3414 struct drm_device *dev = crtc->dev;
89749350 3415
bad720ff 3416 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3417 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3418 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3419 return false;
2c07245f 3420 }
89749350
CW		 3421
3422 /* XXX some encoders set the crtcinfo, others don't.
3423 * Obviously we need some form of conflict resolution here...
3424 */
3425 if (adjusted_mode->crtc_htotal == 0)
3426 drm_mode_set_crtcinfo(adjusted_mode, 0);
3427
79e53945
JB		 3428 return true;
3429}
3430
e70236a8
JB		 3431static int i945_get_display_clock_speed(struct drm_device *dev)
3432{
3433 return 400000;
3434}
79e53945 3435
e70236a8 3436static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3437{
e70236a8
JB		 3438 return 333000;
3439}
79e53945 3440
e70236a8
JB		 3441static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3442{
3443 return 200000;
3444}
79e53945 3445
e70236a8
JB		 3446static int i915gm_get_display_clock_speed(struct drm_device *dev)
3447{
3448 u16 gcfgc = 0;
79e53945 3449
e70236a8
JB		 3450 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3451
3452 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3453 return 133000;
3454 else {
3455 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3456 case GC_DISPLAY_CLOCK_333_MHZ:
3457 return 333000;
3458 default:
3459 case GC_DISPLAY_CLOCK_190_200_MHZ:
3460 return 190000;
79e53945 3461 }
e70236a8
JB		 3462 }
3463}
3464
3465static int i865_get_display_clock_speed(struct drm_device *dev)
3466{
3467 return 266000;
3468}
3469
3470static int i855_get_display_clock_speed(struct drm_device *dev)
3471{
3472 u16 hpllcc = 0;
3473 /* Assume that the hardware is in the high speed state. This
3474 * should be the default.
3475 */
3476 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3477 case GC_CLOCK_133_200:
3478 case GC_CLOCK_100_200:
3479 return 200000;
3480 case GC_CLOCK_166_250:
3481 return 250000;
3482 case GC_CLOCK_100_133:
79e53945 3483 return 133000;
e70236a8 3484 }
79e53945 3485
e70236a8
JB		 3486 /* Shouldn't happen */
3487 return 0;
3488}
79e53945 3489
e70236a8
JB		 3490static int i830_get_display_clock_speed(struct drm_device *dev)
3491{
3492 return 133000;
79e53945
JB		 3493}
3494
2c07245f
ZW		 3495struct fdi_m_n {
3496 u32 tu;
3497 u32 gmch_m;
3498 u32 gmch_n;
3499 u32 link_m;
3500 u32 link_n;
3501};
3502
3503static void
3504fdi_reduce_ratio(u32 *num, u32 *den)
3505{
3506 while (*num > 0xffffff || *den > 0xffffff) {
3507 *num >>= 1;
3508 *den >>= 1;
3509 }
3510}
3511
2c07245f 3512static void
f2b115e6
AJ		 3513ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3514 int link_clock, struct fdi_m_n *m_n)
2c07245f 3515{
2c07245f
ZW		 3516 m_n->tu = 64; /* default size */
3517
22ed1113
CW		 3518 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3519 m_n->gmch_m = bits_per_pixel * pixel_clock;
3520 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3521 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3522
22ed1113
CW		 3523 m_n->link_m = pixel_clock;
3524 m_n->link_n = link_clock;
2c07245f
ZW		 3525 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3526}
3527
3528
7662c8bd
SL		 3529struct intel_watermark_params {
3530 unsigned long fifo_size;
3531 unsigned long max_wm;
3532 unsigned long default_wm;
3533 unsigned long guard_size;
3534 unsigned long cacheline_size;
3535};
3536
f2b115e6 3537/* Pineview has different values for various configs */
d210246a 3538static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3539 PINEVIEW_DISPLAY_FIFO,
3540 PINEVIEW_MAX_WM,
3541 PINEVIEW_DFT_WM,
3542 PINEVIEW_GUARD_WM,
3543 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3544};
d210246a 3545static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3546 PINEVIEW_DISPLAY_FIFO,
3547 PINEVIEW_MAX_WM,
3548 PINEVIEW_DFT_HPLLOFF_WM,
3549 PINEVIEW_GUARD_WM,
3550 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3551};
d210246a 3552static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3553 PINEVIEW_CURSOR_FIFO,
3554 PINEVIEW_CURSOR_MAX_WM,
3555 PINEVIEW_CURSOR_DFT_WM,
3556 PINEVIEW_CURSOR_GUARD_WM,
3557 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3558};
d210246a 3559static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3560 PINEVIEW_CURSOR_FIFO,
3561 PINEVIEW_CURSOR_MAX_WM,
3562 PINEVIEW_CURSOR_DFT_WM,
3563 PINEVIEW_CURSOR_GUARD_WM,
3564 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3565};
d210246a 3566static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3567 G4X_FIFO_SIZE,
3568 G4X_MAX_WM,
3569 G4X_MAX_WM,
3570 2,
3571 G4X_FIFO_LINE_SIZE,
3572};
d210246a 3573static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3574 I965_CURSOR_FIFO,
3575 I965_CURSOR_MAX_WM,
3576 I965_CURSOR_DFT_WM,
3577 2,
3578 G4X_FIFO_LINE_SIZE,
3579};
d210246a 3580static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3581 I965_CURSOR_FIFO,
3582 I965_CURSOR_MAX_WM,
3583 I965_CURSOR_DFT_WM,
3584 2,
3585 I915_FIFO_LINE_SIZE,
3586};
d210246a 3587static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3588 I945_FIFO_SIZE,
7662c8bd
SL		 3589 I915_MAX_WM,
3590 1,
dff33cfc
JB		 3591 2,
3592 I915_FIFO_LINE_SIZE
7662c8bd 3593};
d210246a 3594static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3595 I915_FIFO_SIZE,
7662c8bd
SL		 3596 I915_MAX_WM,
3597 1,
dff33cfc 3598 2,
7662c8bd
SL		 3599 I915_FIFO_LINE_SIZE
3600};
d210246a 3601static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3602 I855GM_FIFO_SIZE,
3603 I915_MAX_WM,
3604 1,
dff33cfc 3605 2,
7662c8bd
SL		 3606 I830_FIFO_LINE_SIZE
3607};
d210246a 3608static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3609 I830_FIFO_SIZE,
3610 I915_MAX_WM,
3611 1,
dff33cfc 3612 2,
7662c8bd
SL		 3613 I830_FIFO_LINE_SIZE
3614};
3615
d210246a 3616static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3617 ILK_DISPLAY_FIFO,
3618 ILK_DISPLAY_MAXWM,
3619 ILK_DISPLAY_DFTWM,
3620 2,
3621 ILK_FIFO_LINE_SIZE
3622};
d210246a 3623static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3624 ILK_CURSOR_FIFO,
3625 ILK_CURSOR_MAXWM,
3626 ILK_CURSOR_DFTWM,
3627 2,
3628 ILK_FIFO_LINE_SIZE
3629};
d210246a 3630static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3631 ILK_DISPLAY_SR_FIFO,
3632 ILK_DISPLAY_MAX_SRWM,
3633 ILK_DISPLAY_DFT_SRWM,
3634 2,
3635 ILK_FIFO_LINE_SIZE
3636};
d210246a 3637static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3638 ILK_CURSOR_SR_FIFO,
3639 ILK_CURSOR_MAX_SRWM,
3640 ILK_CURSOR_DFT_SRWM,
3641 2,
3642 ILK_FIFO_LINE_SIZE
3643};
3644
d210246a 3645static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3646 SNB_DISPLAY_FIFO,
3647 SNB_DISPLAY_MAXWM,
3648 SNB_DISPLAY_DFTWM,
3649 2,
3650 SNB_FIFO_LINE_SIZE
3651};
d210246a 3652static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3653 SNB_CURSOR_FIFO,
3654 SNB_CURSOR_MAXWM,
3655 SNB_CURSOR_DFTWM,
3656 2,
3657 SNB_FIFO_LINE_SIZE
3658};
d210246a 3659static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3660 SNB_DISPLAY_SR_FIFO,
3661 SNB_DISPLAY_MAX_SRWM,
3662 SNB_DISPLAY_DFT_SRWM,
3663 2,
3664 SNB_FIFO_LINE_SIZE
3665};
d210246a 3666static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3667 SNB_CURSOR_SR_FIFO,
3668 SNB_CURSOR_MAX_SRWM,
3669 SNB_CURSOR_DFT_SRWM,
3670 2,
3671 SNB_FIFO_LINE_SIZE
3672};
3673
3674
dff33cfc
JB		 3675/**
3676 * intel_calculate_wm - calculate watermark level
3677 * @clock_in_khz: pixel clock
3678 * @wm: chip FIFO params
3679 * @pixel_size: display pixel size
3680 * @latency_ns: memory latency for the platform
3681 *
3682 * Calculate the watermark level (the level at which the display plane will
3683 * start fetching from memory again). Each chip has a different display
3684 * FIFO size and allocation, so the caller needs to figure that out and pass
3685 * in the correct intel_watermark_params structure.
3686 *
3687 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3688 * on the pixel size. When it reaches the watermark level, it'll start
3689 * fetching FIFO line sized based chunks from memory until the FIFO fills
3690 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3691 * will occur, and a display engine hang could result.
3692 */
7662c8bd 3693static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3694 const struct intel_watermark_params *wm,
3695 int fifo_size,
7662c8bd
SL		 3696 int pixel_size,
3697 unsigned long latency_ns)
3698{
390c4dd4 3699 long entries_required, wm_size;
dff33cfc 3700
d660467c
JB		 3701 /*
3702 * Note: we need to make sure we don't overflow for various clock &
3703 * latency values.
3704 * clocks go from a few thousand to several hundred thousand.
3705 * latency is usually a few thousand
3706 */
3707 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3708 1000;
8de9b311 3709 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3710
bbb0aef5 3711 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3712
d210246a 3713 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3714
bbb0aef5 3715 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3716
390c4dd4
JB		 3717 /* Don't promote wm_size to unsigned... */
3718 if (wm_size > (long)wm->max_wm)
7662c8bd 3719 wm_size = wm->max_wm;
c3add4b6 3720 if (wm_size <= 0)
7662c8bd
SL		 3721 wm_size = wm->default_wm;
3722 return wm_size;
3723}
3724
3725struct cxsr_latency {
3726 int is_desktop;
95534263 3727 int is_ddr3;
7662c8bd
SL		 3728 unsigned long fsb_freq;
3729 unsigned long mem_freq;
3730 unsigned long display_sr;
3731 unsigned long display_hpll_disable;
3732 unsigned long cursor_sr;
3733 unsigned long cursor_hpll_disable;
3734};
3735
403c89ff 3736static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3737 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3738 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3739 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3740 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3741 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3742
3743 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3744 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3745 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3746 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3747 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3748
3749 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3750 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3751 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3752 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3753 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3754
3755 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3756 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3757 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3758 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3759 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3760
3761 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3762 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3763 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3764 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3765 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3766
3767 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3768 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3769 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3770 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3771 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3772};
3773
403c89ff
CW		 3774static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3775 int is_ddr3,
3776 int fsb,
3777 int mem)
7662c8bd 3778{
403c89ff 3779 const struct cxsr_latency *latency;
7662c8bd 3780 int i;
7662c8bd
SL		 3781
3782 if (fsb == 0 || mem == 0)
3783 return NULL;
3784
3785 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3786 latency = &cxsr_latency_table[i];
3787 if (is_desktop == latency->is_desktop &&
95534263 3788 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3789 fsb == latency->fsb_freq && mem == latency->mem_freq)
3790 return latency;
7662c8bd 3791 }
decbbcda 3792
28c97730 3793 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3794
3795 return NULL;
7662c8bd
SL		 3796}
3797
f2b115e6 3798static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3799{
3800 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3801
3802 /* deactivate cxsr */
3e33d94d 3803 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3804}
3805
bcc24fb4
JB		 3806/*
3807 * Latency for FIFO fetches is dependent on several factors:
3808 * - memory configuration (speed, channels)
3809 * - chipset
3810 * - current MCH state
3811 * It can be fairly high in some situations, so here we assume a fairly
3812 * pessimal value. It's a tradeoff between extra memory fetches (if we
3813 * set this value too high, the FIFO will fetch frequently to stay full)
3814 * and power consumption (set it too low to save power and we might see
3815 * FIFO underruns and display "flicker").
3816 *
3817 * A value of 5us seems to be a good balance; safe for very low end
3818 * platforms but not overly aggressive on lower latency configs.
3819 */
69e302a9 3820static const int latency_ns = 5000;
7662c8bd 3821
e70236a8 3822static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3823{
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 uint32_t dsparb = I915_READ(DSPARB);
3826 int size;
3827
8de9b311
CW		 3828 size = dsparb & 0x7f;
3829 if (plane)
3830 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3831
28c97730 3832 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3833 plane ? "B" : "A", size);
dff33cfc
JB		 3834
3835 return size;
3836}
7662c8bd 3837
e70236a8
JB		 3838static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t dsparb = I915_READ(DSPARB);
3842 int size;
3843
8de9b311
CW		 3844 size = dsparb & 0x1ff;
3845 if (plane)
3846 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3847 size >>= 1; /* Convert to cachelines */
dff33cfc 3848
28c97730 3849 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3850 plane ? "B" : "A", size);
dff33cfc
JB		 3851
3852 return size;
3853}
7662c8bd 3854
e70236a8
JB		 3855static int i845_get_fifo_size(struct drm_device *dev, int plane)
3856{
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 uint32_t dsparb = I915_READ(DSPARB);
3859 int size;
3860
3861 size = dsparb & 0x7f;
3862 size >>= 2; /* Convert to cachelines */
3863
28c97730 3864 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3865 plane ? "B" : "A",
3866 size);
e70236a8
JB		 3867
3868 return size;
3869}
3870
3871static int i830_get_fifo_size(struct drm_device *dev, int plane)
3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 uint32_t dsparb = I915_READ(DSPARB);
3875 int size;
3876
3877 size = dsparb & 0x7f;
3878 size >>= 1; /* Convert to cachelines */
3879
28c97730 3880 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3881 plane ? "B" : "A", size);
e70236a8
JB		 3882
3883 return size;
3884}
3885
d210246a
CW		 3886static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3887{
3888 struct drm_crtc *crtc, *enabled = NULL;
3889
3890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3891 if (crtc->enabled && crtc->fb) {
3892 if (enabled)
3893 return NULL;
3894 enabled = crtc;
3895 }
3896 }
3897
3898 return enabled;
3899}
3900
3901static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3902{
3903 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3904 struct drm_crtc *crtc;
403c89ff 3905 const struct cxsr_latency *latency;
d4294342
ZY		 3906 u32 reg;
3907 unsigned long wm;
d4294342 3908
403c89ff 3909 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3910 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3911 if (!latency) {
3912 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3913 pineview_disable_cxsr(dev);
3914 return;
3915 }
3916
d210246a
CW		 3917 crtc = single_enabled_crtc(dev);
3918 if (crtc) {
3919 int clock = crtc->mode.clock;
3920 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3921
3922 /* Display SR */
d210246a
CW		 3923 wm = intel_calculate_wm(clock, &pineview_display_wm,
3924 pineview_display_wm.fifo_size,
d4294342
ZY		 3925 pixel_size, latency->display_sr);
3926 reg = I915_READ(DSPFW1);
3927 reg &= ~DSPFW_SR_MASK;
3928 reg |= wm << DSPFW_SR_SHIFT;
3929 I915_WRITE(DSPFW1, reg);
3930 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3931
3932 /* cursor SR */
d210246a
CW		 3933 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3934 pineview_display_wm.fifo_size,
d4294342
ZY		 3935 pixel_size, latency->cursor_sr);
3936 reg = I915_READ(DSPFW3);
3937 reg &= ~DSPFW_CURSOR_SR_MASK;
3938 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3939 I915_WRITE(DSPFW3, reg);
3940
3941 /* Display HPLL off SR */
d210246a
CW		 3942 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3943 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3944 pixel_size, latency->display_hpll_disable);
3945 reg = I915_READ(DSPFW3);
3946 reg &= ~DSPFW_HPLL_SR_MASK;
3947 reg |= wm & DSPFW_HPLL_SR_MASK;
3948 I915_WRITE(DSPFW3, reg);
3949
3950 /* cursor HPLL off SR */
d210246a
CW		 3951 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3952 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3953 pixel_size, latency->cursor_hpll_disable);
3954 reg = I915_READ(DSPFW3);
3955 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3956 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3957 I915_WRITE(DSPFW3, reg);
3958 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3959
3960 /* activate cxsr */
3e33d94d
CW		 3961 I915_WRITE(DSPFW3,
3962 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3963 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3964 } else {
3965 pineview_disable_cxsr(dev);
3966 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3967 }
3968}
3969
417ae147
CW		 3970static bool g4x_compute_wm0(struct drm_device *dev,
3971 int plane,
3972 const struct intel_watermark_params *display,
3973 int display_latency_ns,
3974 const struct intel_watermark_params *cursor,
3975 int cursor_latency_ns,
3976 int *plane_wm,
3977 int *cursor_wm)
3978{
3979 struct drm_crtc *crtc;
3980 int htotal, hdisplay, clock, pixel_size;
3981 int line_time_us, line_count;
3982 int entries, tlb_miss;
3983
3984 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3985 if (crtc->fb == NULL || !crtc->enabled) {
3986 *cursor_wm = cursor->guard_size;
3987 *plane_wm = display->guard_size;
417ae147 3988 return false;
5c72d064 3989 }
417ae147
CW		 3990
3991 htotal = crtc->mode.htotal;
3992 hdisplay = crtc->mode.hdisplay;
3993 clock = crtc->mode.clock;
3994 pixel_size = crtc->fb->bits_per_pixel / 8;
3995
3996 /* Use the small buffer method to calculate plane watermark */
3997 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3998 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3999 if (tlb_miss > 0)
4000 entries += tlb_miss;
4001 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4002 *plane_wm = entries + display->guard_size;
4003 if (*plane_wm > (int)display->max_wm)
4004 *plane_wm = display->max_wm;
4005
4006 /* Use the large buffer method to calculate cursor watermark */
4007 line_time_us = ((htotal * 1000) / clock);
4008 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4009 entries = line_count * 64 * pixel_size;
4010 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4011 if (tlb_miss > 0)
4012 entries += tlb_miss;
4013 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4014 *cursor_wm = entries + cursor->guard_size;
4015 if (*cursor_wm > (int)cursor->max_wm)
4016 *cursor_wm = (int)cursor->max_wm;
4017
4018 return true;
4019}
4020
4021/*
4022 * Check the wm result.
4023 *
4024 * If any calculated watermark values is larger than the maximum value that
4025 * can be programmed into the associated watermark register, that watermark
4026 * must be disabled.
4027 */
4028static bool g4x_check_srwm(struct drm_device *dev,
4029 int display_wm, int cursor_wm,
4030 const struct intel_watermark_params *display,
4031 const struct intel_watermark_params *cursor)
652c393a 4032{
417ae147
CW		 4033 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4034 display_wm, cursor_wm);
652c393a 4035
417ae147 4036 if (display_wm > display->max_wm) {
bbb0aef5 4037 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4038 display_wm, display->max_wm);
4039 return false;
4040 }
0e442c60 4041
417ae147 4042 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4043 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4044 cursor_wm, cursor->max_wm);
4045 return false;
4046 }
0e442c60 4047
417ae147
CW		 4048 if (!(display_wm || cursor_wm)) {
4049 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4050 return false;
4051 }
0e442c60 4052
417ae147
CW		 4053 return true;
4054}
0e442c60 4055
417ae147 4056static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4057 int plane,
4058 int latency_ns,
417ae147
CW		 4059 const struct intel_watermark_params *display,
4060 const struct intel_watermark_params *cursor,
4061 int *display_wm, int *cursor_wm)
4062{
d210246a
CW		 4063 struct drm_crtc *crtc;
4064 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4065 unsigned long line_time_us;
4066 int line_count, line_size;
4067 int small, large;
4068 int entries;
0e442c60 4069
417ae147
CW		 4070 if (!latency_ns) {
4071 *display_wm = *cursor_wm = 0;
4072 return false;
4073 }
0e442c60 4074
d210246a
CW		 4075 crtc = intel_get_crtc_for_plane(dev, plane);
4076 hdisplay = crtc->mode.hdisplay;
4077 htotal = crtc->mode.htotal;
4078 clock = crtc->mode.clock;
4079 pixel_size = crtc->fb->bits_per_pixel / 8;
4080
417ae147
CW		 4081 line_time_us = (htotal * 1000) / clock;
4082 line_count = (latency_ns / line_time_us + 1000) / 1000;
4083 line_size = hdisplay * pixel_size;
0e442c60 4084
417ae147
CW		 4085 /* Use the minimum of the small and large buffer method for primary */
4086 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4087 large = line_count * line_size;
0e442c60 4088
417ae147
CW		 4089 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4090 *display_wm = entries + display->guard_size;
4fe5e611 4091
417ae147
CW		 4092 /* calculate the self-refresh watermark for display cursor */
4093 entries = line_count * pixel_size * 64;
4094 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4095 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4096
417ae147
CW		 4097 return g4x_check_srwm(dev,
4098 *display_wm, *cursor_wm,
4099 display, cursor);
4100}
4fe5e611 4101
7ccb4a53 4102#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4103
4104static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4105{
4106 static const int sr_latency_ns = 12000;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4109 int plane_sr, cursor_sr;
4110 unsigned int enabled = 0;
417ae147
CW		 4111
4112 if (g4x_compute_wm0(dev, 0,
4113 &g4x_wm_info, latency_ns,
4114 &g4x_cursor_wm_info, latency_ns,
4115 &planea_wm, &cursora_wm))
d210246a 4116 enabled |= 1;
417ae147
CW		 4117
4118 if (g4x_compute_wm0(dev, 1,
4119 &g4x_wm_info, latency_ns,
4120 &g4x_cursor_wm_info, latency_ns,
4121 &planeb_wm, &cursorb_wm))
d210246a 4122 enabled |= 2;
417ae147
CW		 4123
4124 plane_sr = cursor_sr = 0;
d210246a
CW		 4125 if (single_plane_enabled(enabled) &&
4126 g4x_compute_srwm(dev, ffs(enabled) - 1,
4127 sr_latency_ns,
417ae147
CW		 4128 &g4x_wm_info,
4129 &g4x_cursor_wm_info,
4130 &plane_sr, &cursor_sr))
0e442c60 4131 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4132 else
4133 I915_WRITE(FW_BLC_SELF,
4134 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4135
308977ac
CW		 4136 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4137 planea_wm, cursora_wm,
4138 planeb_wm, cursorb_wm,
4139 plane_sr, cursor_sr);
0e442c60 4140
417ae147
CW		 4141 I915_WRITE(DSPFW1,
4142 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4143 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4144 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4145 planea_wm);
4146 I915_WRITE(DSPFW2,
4147 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4148 (cursora_wm << DSPFW_CURSORA_SHIFT));
4149 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4150 I915_WRITE(DSPFW3,
4151 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4152 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4153}
4154
d210246a 4155static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4156{
4157 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4158 struct drm_crtc *crtc;
4159 int srwm = 1;
4fe5e611 4160 int cursor_sr = 16;
1dc7546d
JB		 4161
4162 /* Calc sr entries for one plane configs */
d210246a
CW		 4163 crtc = single_enabled_crtc(dev);
4164 if (crtc) {
1dc7546d 4165 /* self-refresh has much higher latency */
69e302a9 4166 static const int sr_latency_ns = 12000;
d210246a
CW		 4167 int clock = crtc->mode.clock;
4168 int htotal = crtc->mode.htotal;
4169 int hdisplay = crtc->mode.hdisplay;
4170 int pixel_size = crtc->fb->bits_per_pixel / 8;
4171 unsigned long line_time_us;
4172 int entries;
1dc7546d 4173
d210246a 4174 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4175
4176 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4177 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4178 pixel_size * hdisplay;
4179 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4180 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4181 if (srwm < 0)
4182 srwm = 1;
1b07e04e 4183 srwm &= 0x1ff;
308977ac
CW		 4184 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4185 entries, srwm);
4fe5e611 4186
d210246a 4187 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4188 pixel_size * 64;
d210246a 4189 entries = DIV_ROUND_UP(entries,
8de9b311 4190 i965_cursor_wm_info.cacheline_size);
4fe5e611 4191 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4192 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4193
4194 if (cursor_sr > i965_cursor_wm_info.max_wm)
4195 cursor_sr = i965_cursor_wm_info.max_wm;
4196
4197 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4198 "cursor %d\n", srwm, cursor_sr);
4199
a6c45cf0 4200 if (IS_CRESTLINE(dev))
adcdbc66 4201 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4202 } else {
4203 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4204 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4205 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4206 & ~FW_BLC_SELF_EN);
1dc7546d 4207 }
7662c8bd 4208
1dc7546d
JB		 4209 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4210 srwm);
7662c8bd
SL		 4211
4212 /* 965 has limitations... */
417ae147
CW		 4213 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4214 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4215 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4216 /* update cursor SR watermark */
4217 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4218}
4219
d210246a 4220static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4221{
4222 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4223 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4224 uint32_t fwater_lo;
4225 uint32_t fwater_hi;
d210246a
CW		 4226 int cwm, srwm = 1;
4227 int fifo_size;
dff33cfc 4228 int planea_wm, planeb_wm;
d210246a 4229 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4230
72557b4f 4231 if (IS_I945GM(dev))
d210246a 4232 wm_info = &i945_wm_info;
a6c45cf0 4233 else if (!IS_GEN2(dev))
d210246a 4234 wm_info = &i915_wm_info;
7662c8bd 4235 else
d210246a
CW		 4236 wm_info = &i855_wm_info;
4237
4238 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4239 crtc = intel_get_crtc_for_plane(dev, 0);
4240 if (crtc->enabled && crtc->fb) {
4241 planea_wm = intel_calculate_wm(crtc->mode.clock,
4242 wm_info, fifo_size,
4243 crtc->fb->bits_per_pixel / 8,
4244 latency_ns);
4245 enabled = crtc;
4246 } else
4247 planea_wm = fifo_size - wm_info->guard_size;
4248
4249 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4250 crtc = intel_get_crtc_for_plane(dev, 1);
4251 if (crtc->enabled && crtc->fb) {
4252 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4253 wm_info, fifo_size,
4254 crtc->fb->bits_per_pixel / 8,
4255 latency_ns);
4256 if (enabled == NULL)
4257 enabled = crtc;
4258 else
4259 enabled = NULL;
4260 } else
4261 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4262
28c97730 4263 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4264
4265 /*
4266 * Overlay gets an aggressive default since video jitter is bad.
4267 */
4268 cwm = 2;
4269
18b2190c
AL		 4270 /* Play safe and disable self-refresh before adjusting watermarks. */
4271 if (IS_I945G(dev) || IS_I945GM(dev))
4272 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4273 else if (IS_I915GM(dev))
4274 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4275
dff33cfc 4276 /* Calc sr entries for one plane configs */
d210246a 4277 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4278 /* self-refresh has much higher latency */
69e302a9 4279 static const int sr_latency_ns = 6000;
d210246a
CW		 4280 int clock = enabled->mode.clock;
4281 int htotal = enabled->mode.htotal;
4282 int hdisplay = enabled->mode.hdisplay;
4283 int pixel_size = enabled->fb->bits_per_pixel / 8;
4284 unsigned long line_time_us;
4285 int entries;
dff33cfc 4286
d210246a 4287 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4288
4289 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4290 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4291 pixel_size * hdisplay;
4292 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4293 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4294 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4295 if (srwm < 0)
4296 srwm = 1;
ee980b80
LP		 4297
4298 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4299 I915_WRITE(FW_BLC_SELF,
4300 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4301 else if (IS_I915GM(dev))
ee980b80 4302 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4303 }
4304
28c97730 4305 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4306 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4307
dff33cfc
JB		 4308 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4309 fwater_hi = (cwm & 0x1f);
4310
4311 /* Set request length to 8 cachelines per fetch */
4312 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4313 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4314
4315 I915_WRITE(FW_BLC, fwater_lo);
4316 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4317
d210246a
CW		 4318 if (HAS_FW_BLC(dev)) {
4319 if (enabled) {
4320 if (IS_I945G(dev) || IS_I945GM(dev))
4321 I915_WRITE(FW_BLC_SELF,
4322 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4323 else if (IS_I915GM(dev))
4324 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4325 DRM_DEBUG_KMS("memory self refresh enabled\n");
4326 } else
4327 DRM_DEBUG_KMS("memory self refresh disabled\n");
4328 }
7662c8bd
SL		 4329}
4330
d210246a 4331static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4332{
4333 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4334 struct drm_crtc *crtc;
4335 uint32_t fwater_lo;
dff33cfc 4336 int planea_wm;
7662c8bd 4337
d210246a
CW		 4338 crtc = single_enabled_crtc(dev);
4339 if (crtc == NULL)
4340 return;
7662c8bd 4341
d210246a
CW		 4342 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4343 dev_priv->display.get_fifo_size(dev, 0),
4344 crtc->fb->bits_per_pixel / 8,
4345 latency_ns);
4346 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4347 fwater_lo |= (3<<8) | planea_wm;
4348
28c97730 4349 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4350
4351 I915_WRITE(FW_BLC, fwater_lo);
4352}
4353
7f8a8569 4354#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4355#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4356
1398261a
YL		 4357/*
4358 * Check the wm result.
4359 *
4360 * If any calculated watermark values is larger than the maximum value that
4361 * can be programmed into the associated watermark register, that watermark
4362 * must be disabled.
1398261a 4363 */
b79d4990
JB		 4364static bool ironlake_check_srwm(struct drm_device *dev, int level,
4365 int fbc_wm, int display_wm, int cursor_wm,
4366 const struct intel_watermark_params *display,
4367 const struct intel_watermark_params *cursor)
1398261a
YL		 4368{
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4370
4371 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4372 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4373
4374 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4375 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4376 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4377
4378 /* fbc has it's own way to disable FBC WM */
4379 I915_WRITE(DISP_ARB_CTL,
4380 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4381 return false;
4382 }
4383
b79d4990 4384 if (display_wm > display->max_wm) {
1398261a 4385 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4386 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4387 return false;
4388 }
4389
b79d4990 4390 if (cursor_wm > cursor->max_wm) {
1398261a 4391 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4392 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4393 return false;
4394 }
4395
4396 if (!(fbc_wm || display_wm || cursor_wm)) {
4397 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4398 return false;
4399 }
4400
4401 return true;
4402}
4403
4404/*
4405 * Compute watermark values of WM[1-3],
4406 */
d210246a
CW		 4407static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4408 int latency_ns,
b79d4990
JB		 4409 const struct intel_watermark_params *display,
4410 const struct intel_watermark_params *cursor,
4411 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4412{
d210246a 4413 struct drm_crtc *crtc;
1398261a 4414 unsigned long line_time_us;
d210246a 4415 int hdisplay, htotal, pixel_size, clock;
b79d4990 4416 int line_count, line_size;
1398261a
YL		 4417 int small, large;
4418 int entries;
1398261a
YL		 4419
4420 if (!latency_ns) {
4421 *fbc_wm = *display_wm = *cursor_wm = 0;
4422 return false;
4423 }
4424
d210246a
CW		 4425 crtc = intel_get_crtc_for_plane(dev, plane);
4426 hdisplay = crtc->mode.hdisplay;
4427 htotal = crtc->mode.htotal;
4428 clock = crtc->mode.clock;
4429 pixel_size = crtc->fb->bits_per_pixel / 8;
4430
1398261a
YL		 4431 line_time_us = (htotal * 1000) / clock;
4432 line_count = (latency_ns / line_time_us + 1000) / 1000;
4433 line_size = hdisplay * pixel_size;
4434
4435 /* Use the minimum of the small and large buffer method for primary */
4436 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4437 large = line_count * line_size;
4438
b79d4990
JB		 4439 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4440 *display_wm = entries + display->guard_size;
1398261a
YL		 4441
4442 /*
b79d4990 4443 * Spec says:
1398261a
YL		 4444 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4445 */
4446 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4447
4448 /* calculate the self-refresh watermark for display cursor */
4449 entries = line_count * pixel_size * 64;
b79d4990
JB		 4450 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4451 *cursor_wm = entries + cursor->guard_size;
1398261a 4452
b79d4990
JB		 4453 return ironlake_check_srwm(dev, level,
4454 *fbc_wm, *display_wm, *cursor_wm,
4455 display, cursor);
4456}
4457
d210246a 4458static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4459{
4460 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4461 int fbc_wm, plane_wm, cursor_wm;
4462 unsigned int enabled;
b79d4990
JB		 4463
4464 enabled = 0;
9f405100
CW		 4465 if (g4x_compute_wm0(dev, 0,
4466 &ironlake_display_wm_info,
4467 ILK_LP0_PLANE_LATENCY,
4468 &ironlake_cursor_wm_info,
4469 ILK_LP0_CURSOR_LATENCY,
4470 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4471 I915_WRITE(WM0_PIPEA_ILK,
4472 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4473 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4474 " plane %d, " "cursor: %d\n",
4475 plane_wm, cursor_wm);
d210246a 4476 enabled |= 1;
b79d4990
JB		 4477 }
4478
9f405100
CW		 4479 if (g4x_compute_wm0(dev, 1,
4480 &ironlake_display_wm_info,
4481 ILK_LP0_PLANE_LATENCY,
4482 &ironlake_cursor_wm_info,
4483 ILK_LP0_CURSOR_LATENCY,
4484 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4485 I915_WRITE(WM0_PIPEB_ILK,
4486 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4487 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4488 " plane %d, cursor: %d\n",
4489 plane_wm, cursor_wm);
d210246a 4490 enabled |= 2;
b79d4990
JB		 4491 }
4492
4493 /*
4494 * Calculate and update the self-refresh watermark only when one
4495 * display plane is used.
4496 */
4497 I915_WRITE(WM3_LP_ILK, 0);
4498 I915_WRITE(WM2_LP_ILK, 0);
4499 I915_WRITE(WM1_LP_ILK, 0);
4500
d210246a 4501 if (!single_plane_enabled(enabled))
b79d4990 4502 return;
d210246a 4503 enabled = ffs(enabled) - 1;
b79d4990
JB		 4504
4505 /* WM1 */
d210246a
CW		 4506 if (!ironlake_compute_srwm(dev, 1, enabled,
4507 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4508 &ironlake_display_srwm_info,
4509 &ironlake_cursor_srwm_info,
4510 &fbc_wm, &plane_wm, &cursor_wm))
4511 return;
4512
4513 I915_WRITE(WM1_LP_ILK,
4514 WM1_LP_SR_EN |
4515 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4516 (fbc_wm << WM1_LP_FBC_SHIFT) |
4517 (plane_wm << WM1_LP_SR_SHIFT) |
4518 cursor_wm);
4519
4520 /* WM2 */
d210246a
CW		 4521 if (!ironlake_compute_srwm(dev, 2, enabled,
4522 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4523 &ironlake_display_srwm_info,
4524 &ironlake_cursor_srwm_info,
4525 &fbc_wm, &plane_wm, &cursor_wm))
4526 return;
4527
4528 I915_WRITE(WM2_LP_ILK,
4529 WM2_LP_EN |
4530 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4531 (fbc_wm << WM1_LP_FBC_SHIFT) |
4532 (plane_wm << WM1_LP_SR_SHIFT) |
4533 cursor_wm);
4534
4535 /*
4536 * WM3 is unsupported on ILK, probably because we don't have latency
4537 * data for that power state
4538 */
1398261a
YL		 4539}
4540
b840d907 4541void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4542{
4543 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4544 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4545 int fbc_wm, plane_wm, cursor_wm;
4546 unsigned int enabled;
1398261a
YL		 4547
4548 enabled = 0;
9f405100
CW		 4549 if (g4x_compute_wm0(dev, 0,
4550 &sandybridge_display_wm_info, latency,
4551 &sandybridge_cursor_wm_info, latency,
4552 &plane_wm, &cursor_wm)) {
1398261a
YL		 4553 I915_WRITE(WM0_PIPEA_ILK,
4554 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4555 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4556 " plane %d, " "cursor: %d\n",
4557 plane_wm, cursor_wm);
d210246a 4558 enabled |= 1;
1398261a
YL		 4559 }
4560
9f405100
CW		 4561 if (g4x_compute_wm0(dev, 1,
4562 &sandybridge_display_wm_info, latency,
4563 &sandybridge_cursor_wm_info, latency,
4564 &plane_wm, &cursor_wm)) {
1398261a
YL		 4565 I915_WRITE(WM0_PIPEB_ILK,
4566 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4567 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4568 " plane %d, cursor: %d\n",
4569 plane_wm, cursor_wm);
d210246a 4570 enabled |= 2;
1398261a
YL		 4571 }
4572
d6c892df
JB		 4573 /* IVB has 3 pipes */
4574 if (IS_IVYBRIDGE(dev) &&
4575 g4x_compute_wm0(dev, 2,
4576 &sandybridge_display_wm_info, latency,
4577 &sandybridge_cursor_wm_info, latency,
4578 &plane_wm, &cursor_wm)) {
4579 I915_WRITE(WM0_PIPEC_IVB,
4580 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4581 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4582 " plane %d, cursor: %d\n",
4583 plane_wm, cursor_wm);
4584 enabled |= 3;
4585 }
4586
1398261a
YL		 4587 /*
4588 * Calculate and update the self-refresh watermark only when one
4589 * display plane is used.
4590 *
4591 * SNB support 3 levels of watermark.
4592 *
4593 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4594 * and disabled in the descending order
4595 *
4596 */
4597 I915_WRITE(WM3_LP_ILK, 0);
4598 I915_WRITE(WM2_LP_ILK, 0);
4599 I915_WRITE(WM1_LP_ILK, 0);
4600
b840d907
JB		 4601 if (!single_plane_enabled(enabled) ||
4602 dev_priv->sprite_scaling_enabled)
1398261a 4603 return;
d210246a 4604 enabled = ffs(enabled) - 1;
1398261a
YL		 4605
4606 /* WM1 */
d210246a
CW		 4607 if (!ironlake_compute_srwm(dev, 1, enabled,
4608 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4609 &sandybridge_display_srwm_info,
4610 &sandybridge_cursor_srwm_info,
4611 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4612 return;
4613
4614 I915_WRITE(WM1_LP_ILK,
4615 WM1_LP_SR_EN |
4616 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4617 (fbc_wm << WM1_LP_FBC_SHIFT) |
4618 (plane_wm << WM1_LP_SR_SHIFT) |
4619 cursor_wm);
4620
4621 /* WM2 */
d210246a
CW		 4622 if (!ironlake_compute_srwm(dev, 2, enabled,
4623 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4624 &sandybridge_display_srwm_info,
4625 &sandybridge_cursor_srwm_info,
4626 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4627 return;
4628
4629 I915_WRITE(WM2_LP_ILK,
4630 WM2_LP_EN |
4631 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4632 (fbc_wm << WM1_LP_FBC_SHIFT) |
4633 (plane_wm << WM1_LP_SR_SHIFT) |
4634 cursor_wm);
4635
4636 /* WM3 */
d210246a
CW		 4637 if (!ironlake_compute_srwm(dev, 3, enabled,
4638 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4639 &sandybridge_display_srwm_info,
4640 &sandybridge_cursor_srwm_info,
4641 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4642 return;
4643
4644 I915_WRITE(WM3_LP_ILK,
4645 WM3_LP_EN |
4646 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4647 (fbc_wm << WM1_LP_FBC_SHIFT) |
4648 (plane_wm << WM1_LP_SR_SHIFT) |
4649 cursor_wm);
4650}
4651
b840d907
JB		 4652static bool
4653sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4654 uint32_t sprite_width, int pixel_size,
4655 const struct intel_watermark_params *display,
4656 int display_latency_ns, int *sprite_wm)
4657{
4658 struct drm_crtc *crtc;
4659 int clock;
4660 int entries, tlb_miss;
4661
4662 crtc = intel_get_crtc_for_plane(dev, plane);
4663 if (crtc->fb == NULL || !crtc->enabled) {
4664 *sprite_wm = display->guard_size;
4665 return false;
4666 }
4667
4668 clock = crtc->mode.clock;
4669
4670 /* Use the small buffer method to calculate the sprite watermark */
4671 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4672 tlb_miss = display->fifo_size*display->cacheline_size -
4673 sprite_width * 8;
4674 if (tlb_miss > 0)
4675 entries += tlb_miss;
4676 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4677 *sprite_wm = entries + display->guard_size;
4678 if (*sprite_wm > (int)display->max_wm)
4679 *sprite_wm = display->max_wm;
4680
4681 return true;
4682}
4683
4684static bool
4685sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4686 uint32_t sprite_width, int pixel_size,
4687 const struct intel_watermark_params *display,
4688 int latency_ns, int *sprite_wm)
4689{
4690 struct drm_crtc *crtc;
4691 unsigned long line_time_us;
4692 int clock;
4693 int line_count, line_size;
4694 int small, large;
4695 int entries;
4696
4697 if (!latency_ns) {
4698 *sprite_wm = 0;
4699 return false;
4700 }
4701
4702 crtc = intel_get_crtc_for_plane(dev, plane);
4703 clock = crtc->mode.clock;
4704
4705 line_time_us = (sprite_width * 1000) / clock;
4706 line_count = (latency_ns / line_time_us + 1000) / 1000;
4707 line_size = sprite_width * pixel_size;
4708
4709 /* Use the minimum of the small and large buffer method for primary */
4710 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4711 large = line_count * line_size;
4712
4713 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4714 *sprite_wm = entries + display->guard_size;
4715
4716 return *sprite_wm > 0x3ff ? false : true;
4717}
4718
4719static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4720 uint32_t sprite_width, int pixel_size)
4721{
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4724 int sprite_wm, reg;
4725 int ret;
4726
4727 switch (pipe) {
4728 case 0:
4729 reg = WM0_PIPEA_ILK;
4730 break;
4731 case 1:
4732 reg = WM0_PIPEB_ILK;
4733 break;
4734 case 2:
4735 reg = WM0_PIPEC_IVB;
4736 break;
4737 default:
4738 return; /* bad pipe */
4739 }
4740
4741 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4742 &sandybridge_display_wm_info,
4743 latency, &sprite_wm);
4744 if (!ret) {
4745 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4746 pipe);
4747 return;
4748 }
4749
4750 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4751 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4752
4753
4754 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4755 pixel_size,
4756 &sandybridge_display_srwm_info,
4757 SNB_READ_WM1_LATENCY() * 500,
4758 &sprite_wm);
4759 if (!ret) {
4760 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4761 pipe);
4762 return;
4763 }
4764 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4765
4766 /* Only IVB has two more LP watermarks for sprite */
4767 if (!IS_IVYBRIDGE(dev))
4768 return;
4769
4770 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4771 pixel_size,
4772 &sandybridge_display_srwm_info,
4773 SNB_READ_WM2_LATENCY() * 500,
4774 &sprite_wm);
4775 if (!ret) {
4776 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4777 pipe);
4778 return;
4779 }
4780 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4781
4782 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4783 pixel_size,
4784 &sandybridge_display_srwm_info,
4785 SNB_READ_WM3_LATENCY() * 500,
4786 &sprite_wm);
4787 if (!ret) {
4788 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4789 pipe);
4790 return;
4791 }
4792 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4793}
4794
7662c8bd
SL		 4795/**
4796 * intel_update_watermarks - update FIFO watermark values based on current modes
4797 *
4798 * Calculate watermark values for the various WM regs based on current mode
4799 * and plane configuration.
4800 *
4801 * There are several cases to deal with here:
4802 * - normal (i.e. non-self-refresh)
4803 * - self-refresh (SR) mode
4804 * - lines are large relative to FIFO size (buffer can hold up to 2)
4805 * - lines are small relative to FIFO size (buffer can hold more than 2
4806 * lines), so need to account for TLB latency
4807 *
4808 * The normal calculation is:
4809 * watermark = dotclock * bytes per pixel * latency
4810 * where latency is platform & configuration dependent (we assume pessimal
4811 * values here).
4812 *
4813 * The SR calculation is:
4814 * watermark = (trunc(latency/line time)+1) * surface width *
4815 * bytes per pixel
4816 * where
4817 * line time = htotal / dotclock
fa143215 4818 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4819 * and latency is assumed to be high, as above.
4820 *
4821 * The final value programmed to the register should always be rounded up,
4822 * and include an extra 2 entries to account for clock crossings.
4823 *
4824 * We don't use the sprite, so we can ignore that. And on Crestline we have
4825 * to set the non-SR watermarks to 8.
5eddb70b 4826 */
7662c8bd
SL		 4827static void intel_update_watermarks(struct drm_device *dev)
4828{
e70236a8 4829 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4830
d210246a
CW		 4831 if (dev_priv->display.update_wm)
4832 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4833}
4834
b840d907
JB		 4835void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4836 uint32_t sprite_width, int pixel_size)
4837{
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839
4840 if (dev_priv->display.update_sprite_wm)
4841 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4842 pixel_size);
4843}
4844
a7615030
CW		 4845static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4846{
72bbe58c
KP		 4847 if (i915_panel_use_ssc >= 0)
4848 return i915_panel_use_ssc != 0;
4849 return dev_priv->lvds_use_ssc
435793df 4850 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4851}
4852
5a354204
JB		 4853/**
4854 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4855 * @crtc: CRTC structure
3b5c78a3 4856 * @mode: requested mode
5a354204
JB		 4857 *
4858 * A pipe may be connected to one or more outputs. Based on the depth of the
4859 * attached framebuffer, choose a good color depth to use on the pipe.
4860 *
4861 * If possible, match the pipe depth to the fb depth. In some cases, this
4862 * isn't ideal, because the connected output supports a lesser or restricted
4863 * set of depths. Resolve that here:
4864 * LVDS typically supports only 6bpc, so clamp down in that case
4865 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4866 * Displays may support a restricted set as well, check EDID and clamp as
4867 * appropriate.
3b5c78a3 4868 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4869 *
4870 * RETURNS:
4871 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4872 * true if they don't match).
4873 */
4874static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4875 unsigned int *pipe_bpp,
4876 struct drm_display_mode *mode)
5a354204
JB		 4877{
4878 struct drm_device *dev = crtc->dev;
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 struct drm_encoder *encoder;
4881 struct drm_connector *connector;
4882 unsigned int display_bpc = UINT_MAX, bpc;
4883
4884 /* Walk the encoders & connectors on this crtc, get min bpc */
4885 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4886 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4887
4888 if (encoder->crtc != crtc)
4889 continue;
4890
4891 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4892 unsigned int lvds_bpc;
4893
4894 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4895 LVDS_A3_POWER_UP)
4896 lvds_bpc = 8;
4897 else
4898 lvds_bpc = 6;
4899
4900 if (lvds_bpc < display_bpc) {
82820490 4901 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4902 display_bpc = lvds_bpc;
4903 }
4904 continue;
4905 }
4906
4907 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4908 /* Use VBT settings if we have an eDP panel */
4909 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4910
4911 if (edp_bpc < display_bpc) {
82820490 4912 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4913 display_bpc = edp_bpc;
4914 }
4915 continue;
4916 }
4917
4918 /* Not one of the known troublemakers, check the EDID */
4919 list_for_each_entry(connector, &dev->mode_config.connector_list,
4920 head) {
4921 if (connector->encoder != encoder)
4922 continue;
4923
62ac41a6
JB		 4924 /* Don't use an invalid EDID bpc value */
4925 if (connector->display_info.bpc &&
4926 connector->display_info.bpc < display_bpc) {
82820490 4927 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4928 display_bpc = connector->display_info.bpc;
4929 }
4930 }
4931
4932 /*
4933 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4934 * through, clamp it down. (Note: >12bpc will be caught below.)
4935 */
4936 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4937 if (display_bpc > 8 && display_bpc < 12) {
82820490 4938 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4939 display_bpc = 12;
4940 } else {
82820490 4941 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4942 display_bpc = 8;
4943 }
4944 }
4945 }
4946
3b5c78a3
AJ		 4947 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4948 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4949 display_bpc = 6;
4950 }
4951
5a354204
JB		 4952 /*
4953 * We could just drive the pipe at the highest bpc all the time and
4954 * enable dithering as needed, but that costs bandwidth. So choose
4955 * the minimum value that expresses the full color range of the fb but
4956 * also stays within the max display bpc discovered above.
4957 */
4958
4959 switch (crtc->fb->depth) {
4960 case 8:
4961 bpc = 8; /* since we go through a colormap */
4962 break;
4963 case 15:
4964 case 16:
4965 bpc = 6; /* min is 18bpp */
4966 break;
4967 case 24:
578393cd 4968 bpc = 8;
5a354204
JB		 4969 break;
4970 case 30:
578393cd 4971 bpc = 10;
5a354204
JB		 4972 break;
4973 case 48:
578393cd 4974 bpc = 12;
5a354204
JB		 4975 break;
4976 default:
4977 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4978 bpc = min((unsigned int)8, display_bpc);
4979 break;
4980 }
4981
578393cd
KP		 4982 display_bpc = min(display_bpc, bpc);
4983
82820490
AJ		 4984 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4985 bpc, display_bpc);
5a354204 4986
578393cd 4987 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4988
4989 return display_bpc != bpc;
4990}
4991
c65d77d8
JB		 4992static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4993{
4994 struct drm_device *dev = crtc->dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 int refclk;
4997
4998 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4999 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5000 refclk = dev_priv->lvds_ssc_freq * 1000;
5001 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5002 refclk / 1000);
5003 } else if (!IS_GEN2(dev)) {
5004 refclk = 96000;
5005 } else {
5006 refclk = 48000;
5007 }
5008
5009 return refclk;
5010}
5011
5012static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5013 intel_clock_t *clock)
5014{
5015 /* SDVO TV has fixed PLL values depend on its clock range,
5016 this mirrors vbios setting. */
5017 if (adjusted_mode->clock >= 100000
5018 && adjusted_mode->clock < 140500) {
5019 clock->p1 = 2;
5020 clock->p2 = 10;
5021 clock->n = 3;
5022 clock->m1 = 16;
5023 clock->m2 = 8;
5024 } else if (adjusted_mode->clock >= 140500
5025 && adjusted_mode->clock <= 200000) {
5026 clock->p1 = 1;
5027 clock->p2 = 10;
5028 clock->n = 6;
5029 clock->m1 = 12;
5030 clock->m2 = 8;
5031 }
5032}
5033
a7516a05
JB		 5034static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5035 intel_clock_t *clock,
5036 intel_clock_t *reduced_clock)
5037{
5038 struct drm_device *dev = crtc->dev;
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5041 int pipe = intel_crtc->pipe;
5042 u32 fp, fp2 = 0;
5043
5044 if (IS_PINEVIEW(dev)) {
5045 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5046 if (reduced_clock)
5047 fp2 = (1 << reduced_clock->n) << 16 |
5048 reduced_clock->m1 << 8 | reduced_clock->m2;
5049 } else {
5050 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5051 if (reduced_clock)
5052 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5053 reduced_clock->m2;
5054 }
5055
5056 I915_WRITE(FP0(pipe), fp);
5057
5058 intel_crtc->lowfreq_avail = false;
5059 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5060 reduced_clock && i915_powersave) {
5061 I915_WRITE(FP1(pipe), fp2);
5062 intel_crtc->lowfreq_avail = true;
5063 } else {
5064 I915_WRITE(FP1(pipe), fp);
5065 }
5066}
5067
f564048e
EA		 5068static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5069 struct drm_display_mode *mode,
5070 struct drm_display_mode *adjusted_mode,
5071 int x, int y,
5072 struct drm_framebuffer *old_fb)
79e53945
JB		 5073{
5074 struct drm_device *dev = crtc->dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5077 int pipe = intel_crtc->pipe;
80824003 5078 int plane = intel_crtc->plane;
c751ce4f 5079 int refclk, num_connectors = 0;
652c393a 5080 intel_clock_t clock, reduced_clock;
a7516a05 5081 u32 dpll, dspcntr, pipeconf;
652c393a 5082 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5083 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5084 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5085 struct intel_encoder *encoder;
d4906093 5086 const intel_limit_t *limit;
5c3b82e2 5087 int ret;
fae14981 5088 u32 temp;
aa9b500d 5089 u32 lvds_sync = 0;
79e53945 5090
5eddb70b
CW		 5091 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5092 if (encoder->base.crtc != crtc)
79e53945
JB		 5093 continue;
5094
5eddb70b 5095 switch (encoder->type) {
79e53945
JB		 5096 case INTEL_OUTPUT_LVDS:
5097 is_lvds = true;
5098 break;
5099 case INTEL_OUTPUT_SDVO:
7d57382e 5100 case INTEL_OUTPUT_HDMI:
79e53945 5101 is_sdvo = true;
5eddb70b 5102 if (encoder->needs_tv_clock)
e2f0ba97 5103 is_tv = true;
79e53945
JB		 5104 break;
5105 case INTEL_OUTPUT_DVO:
5106 is_dvo = true;
5107 break;
5108 case INTEL_OUTPUT_TVOUT:
5109 is_tv = true;
5110 break;
5111 case INTEL_OUTPUT_ANALOG:
5112 is_crt = true;
5113 break;
a4fc5ed6
KP		 5114 case INTEL_OUTPUT_DISPLAYPORT:
5115 is_dp = true;
5116 break;
79e53945 5117 }
43565a06 5118
c751ce4f 5119 num_connectors++;
79e53945
JB		 5120 }
5121
c65d77d8 5122 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5123
d4906093
ML		 5124 /*
5125 * Returns a set of divisors for the desired target clock with the given
5126 * refclk, or FALSE. The returned values represent the clock equation:
5127 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5128 */
1b894b59 5129 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5130 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5131 &clock);
79e53945
JB		 5132 if (!ok) {
5133 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5134 return -EINVAL;
79e53945
JB		 5135 }
5136
cda4b7d3 5137 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5138 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5139
ddc9003c 5140 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5141 /*
5142 * Ensure we match the reduced clock's P to the target clock.
5143 * If the clocks don't match, we can't switch the display clock
5144 * by using the FP0/FP1. In such case we will disable the LVDS
5145 * downclock feature.
5146 */
ddc9003c 5147 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5148 dev_priv->lvds_downclock,
5149 refclk,
cec2f356 5150 &clock,
5eddb70b 5151 &reduced_clock);
652c393a 5152 }
c65d77d8
JB		 5153
5154 if (is_sdvo && is_tv)
5155 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5156
a7516a05
JB		 5157 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5158 &reduced_clock : NULL);
79e53945 5159
929c77fb 5160 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5161
a6c45cf0 5162 if (!IS_GEN2(dev)) {
79e53945
JB		 5163 if (is_lvds)
5164 dpll |= DPLLB_MODE_LVDS;
5165 else
5166 dpll |= DPLLB_MODE_DAC_SERIAL;
5167 if (is_sdvo) {
6c9547ff
CW		 5168 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5169 if (pixel_multiplier > 1) {
5170 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5171 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5172 }
79e53945 5173 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5174 }
929c77fb 5175 if (is_dp)
a4fc5ed6 5176 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5177
5178 /* compute bitmask from p1 value */
f2b115e6
AJ		 5179 if (IS_PINEVIEW(dev))
5180 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5181 else {
2177832f 5182 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5183 if (IS_G4X(dev) && has_reduced_clock)
5184 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5185 }
79e53945
JB		 5186 switch (clock.p2) {
5187 case 5:
5188 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5189 break;
5190 case 7:
5191 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5192 break;
5193 case 10:
5194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5195 break;
5196 case 14:
5197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5198 break;
5199 }
929c77fb 5200 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5201 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5202 } else {
5203 if (is_lvds) {
5204 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5205 } else {
5206 if (clock.p1 == 2)
5207 dpll |= PLL_P1_DIVIDE_BY_TWO;
5208 else
5209 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5210 if (clock.p2 == 4)
5211 dpll |= PLL_P2_DIVIDE_BY_4;
5212 }
5213 }
5214
43565a06
KH		 5215 if (is_sdvo && is_tv)
5216 dpll |= PLL_REF_INPUT_TVCLKINBC;
5217 else if (is_tv)
79e53945 5218 /* XXX: just matching BIOS for now */
43565a06 5219 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5220 dpll |= 3;
a7615030 5221 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5222 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5223 else
5224 dpll |= PLL_REF_INPUT_DREFCLK;
5225
5226 /* setup pipeconf */
5eddb70b 5227 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5228
5229 /* Set up the display plane register */
5230 dspcntr = DISPPLANE_GAMMA_ENABLE;
5231
f2b115e6 5232 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 5233 enable color space conversion */
929c77fb
EA		 5234 if (pipe == 0)
5235 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5236 else
5237 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5238
a6c45cf0 5239 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5240 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5241 * core speed.
5242 *
5243 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5244 * pipe == 0 check?
5245 */
e70236a8
JB		 5246 if (mode->clock >
5247 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5248 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5249 else
5eddb70b 5250 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5251 }
5252
3b5c78a3
AJ		 5253 /* default to 8bpc */
5254 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5255 if (is_dp) {
5256 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5257 pipeconf |= PIPECONF_BPP_6 |
5258 PIPECONF_DITHER_EN |
5259 PIPECONF_DITHER_TYPE_SP;
5260 }
5261 }
5262
929c77fb 5263 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5264
28c97730 5265 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5266 drm_mode_debug_printmodeline(mode);
5267
fae14981 5268 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5269
fae14981 5270 POSTING_READ(DPLL(pipe));
c713bb08 5271 udelay(150);
8db9d77b 5272
79e53945
JB		 5273 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5274 * This is an exception to the general rule that mode_set doesn't turn
5275 * things on.
5276 */
5277 if (is_lvds) {
fae14981 5278 temp = I915_READ(LVDS);
5eddb70b 5279 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5280 if (pipe == 1) {
929c77fb 5281 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5282 } else {
929c77fb 5283 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5284 }
a3e17eb8 5285 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5286 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5287 /* Set the B0-B3 data pairs corresponding to whether we're going to
5288 * set the DPLLs for dual-channel mode or not.
5289 */
5290 if (clock.p2 == 7)
5eddb70b 5291 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5292 else
5eddb70b 5293 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5294
5295 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5296 * appropriately here, but we need to look more thoroughly into how
5297 * panels behave in the two modes.
5298 */
929c77fb
EA		 5299 /* set the dithering flag on LVDS as needed */
5300 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5301 if (dev_priv->lvds_dither)
5eddb70b 5302 temp |= LVDS_ENABLE_DITHER;
434ed097 5303 else
5eddb70b 5304 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5305 }
aa9b500d
BF		 5306 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5307 lvds_sync |= LVDS_HSYNC_POLARITY;
5308 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5309 lvds_sync |= LVDS_VSYNC_POLARITY;
5310 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5311 != lvds_sync) {
5312 char flags[2] = "-+";
5313 DRM_INFO("Changing LVDS panel from "
5314 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5315 flags[!(temp & LVDS_HSYNC_POLARITY)],
5316 flags[!(temp & LVDS_VSYNC_POLARITY)],
5317 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5318 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5319 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5320 temp |= lvds_sync;
5321 }
fae14981 5322 I915_WRITE(LVDS, temp);
79e53945 5323 }
434ed097 5324
929c77fb 5325 if (is_dp) {
a4fc5ed6 5326 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5327 }
5328
fae14981 5329 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5330
c713bb08 5331 /* Wait for the clocks to stabilize. */
fae14981 5332 POSTING_READ(DPLL(pipe));
c713bb08 5333 udelay(150);
32f9d658 5334
c713bb08
EA		 5335 if (INTEL_INFO(dev)->gen >= 4) {
5336 temp = 0;
5337 if (is_sdvo) {
5338 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5339 if (temp > 1)
5340 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5341 else
5342 temp = 0;
32f9d658 5343 }
c713bb08
EA		 5344 I915_WRITE(DPLL_MD(pipe), temp);
5345 } else {
5346 /* The pixel multiplier can only be updated once the
5347 * DPLL is enabled and the clocks are stable.
5348 *
5349 * So write it again.
5350 */
fae14981 5351 I915_WRITE(DPLL(pipe), dpll);
79e53945 5352 }
79e53945 5353
a7516a05
JB		 5354 if (HAS_PIPE_CXSR(dev)) {
5355 if (intel_crtc->lowfreq_avail) {
28c97730 5356 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5357 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5358 } else {
28c97730 5359 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5360 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5361 }
5362 }
5363
734b4157
KH		 5364 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5365 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5366 /* the chip adds 2 halflines automatically */
5367 adjusted_mode->crtc_vdisplay -= 1;
5368 adjusted_mode->crtc_vtotal -= 1;
5369 adjusted_mode->crtc_vblank_start -= 1;
5370 adjusted_mode->crtc_vblank_end -= 1;
5371 adjusted_mode->crtc_vsync_end -= 1;
5372 adjusted_mode->crtc_vsync_start -= 1;
5373 } else
59df7b17 5374 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
734b4157 5375
5eddb70b
CW		 5376 I915_WRITE(HTOTAL(pipe),
5377 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5378 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5379 I915_WRITE(HBLANK(pipe),
5380 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5381 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5382 I915_WRITE(HSYNC(pipe),
5383 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5384 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5385
5386 I915_WRITE(VTOTAL(pipe),
5387 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5388 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5389 I915_WRITE(VBLANK(pipe),
5390 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5391 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5392 I915_WRITE(VSYNC(pipe),
5393 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5394 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5395
5396 /* pipesrc and dspsize control the size that is scaled from,
5397 * which should always be the user's requested size.
79e53945 5398 */
929c77fb
EA		 5399 I915_WRITE(DSPSIZE(plane),
5400 ((mode->vdisplay - 1) << 16) |
5401 (mode->hdisplay - 1));
5402 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5403 I915_WRITE(PIPESRC(pipe),
5404 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5405
f564048e
EA		 5406 I915_WRITE(PIPECONF(pipe), pipeconf);
5407 POSTING_READ(PIPECONF(pipe));
929c77fb 5408 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5409
5410 intel_wait_for_vblank(dev, pipe);
5411
f564048e
EA		 5412 I915_WRITE(DSPCNTR(plane), dspcntr);
5413 POSTING_READ(DSPCNTR(plane));
284d9529 5414 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5415
5416 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5417
5418 intel_update_watermarks(dev);
5419
f564048e
EA		 5420 return ret;
5421}
5422
9fb526db
KP		 5423/*
5424 * Initialize reference clocks when the driver loads
5425 */
5426void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5427{
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5430 struct intel_encoder *encoder;
13d83a67
JB		 5431 u32 temp;
5432 bool has_lvds = false;
199e5d79
KP		 5433 bool has_cpu_edp = false;
5434 bool has_pch_edp = false;
5435 bool has_panel = false;
99eb6a01
KP		 5436 bool has_ck505 = false;
5437 bool can_ssc = false;
13d83a67
JB		 5438
5439 /* We need to take the global config into account */
199e5d79
KP		 5440 list_for_each_entry(encoder, &mode_config->encoder_list,
5441 base.head) {
5442 switch (encoder->type) {
5443 case INTEL_OUTPUT_LVDS:
5444 has_panel = true;
5445 has_lvds = true;
5446 break;
5447 case INTEL_OUTPUT_EDP:
5448 has_panel = true;
5449 if (intel_encoder_is_pch_edp(&encoder->base))
5450 has_pch_edp = true;
5451 else
5452 has_cpu_edp = true;
5453 break;
13d83a67
JB		 5454 }
5455 }
5456
99eb6a01
KP		 5457 if (HAS_PCH_IBX(dev)) {
5458 has_ck505 = dev_priv->display_clock_mode;
5459 can_ssc = has_ck505;
5460 } else {
5461 has_ck505 = false;
5462 can_ssc = true;
5463 }
5464
5465 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5466 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5467 has_ck505);
13d83a67
JB		 5468
5469 /* Ironlake: try to setup display ref clock before DPLL
5470 * enabling. This is only under driver's control after
5471 * PCH B stepping, previous chipset stepping should be
5472 * ignoring this setting.
5473 */
5474 temp = I915_READ(PCH_DREF_CONTROL);
5475 /* Always enable nonspread source */
5476 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5477
99eb6a01
KP		 5478 if (has_ck505)
5479 temp |= DREF_NONSPREAD_CK505_ENABLE;
5480 else
5481 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5482
199e5d79
KP		 5483 if (has_panel) {
5484 temp &= ~DREF_SSC_SOURCE_MASK;
5485 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5486
199e5d79 5487 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5488 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5489 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5490 temp |= DREF_SSC1_ENABLE;
13d83a67 5491 }
199e5d79
KP		 5492
5493 /* Get SSC going before enabling the outputs */
5494 I915_WRITE(PCH_DREF_CONTROL, temp);
5495 POSTING_READ(PCH_DREF_CONTROL);
5496 udelay(200);
5497
13d83a67
JB		 5498 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5499
5500 /* Enable CPU source on CPU attached eDP */
199e5d79 5501 if (has_cpu_edp) {
99eb6a01 5502 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5503 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5504 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5505 }
13d83a67
JB		 5506 else
5507 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5508 } else
5509 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5510
5511 I915_WRITE(PCH_DREF_CONTROL, temp);
5512 POSTING_READ(PCH_DREF_CONTROL);
5513 udelay(200);
5514 } else {
5515 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5516
5517 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5518
5519 /* Turn off CPU output */
5520 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5521
5522 I915_WRITE(PCH_DREF_CONTROL, temp);
5523 POSTING_READ(PCH_DREF_CONTROL);
5524 udelay(200);
5525
5526 /* Turn off the SSC source */
5527 temp &= ~DREF_SSC_SOURCE_MASK;
5528 temp |= DREF_SSC_SOURCE_DISABLE;
5529
5530 /* Turn off SSC1 */
5531 temp &= ~ DREF_SSC1_ENABLE;
5532
13d83a67
JB		 5533 I915_WRITE(PCH_DREF_CONTROL, temp);
5534 POSTING_READ(PCH_DREF_CONTROL);
5535 udelay(200);
5536 }
5537}
5538
d9d444cb
JB		 5539static int ironlake_get_refclk(struct drm_crtc *crtc)
5540{
5541 struct drm_device *dev = crtc->dev;
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543 struct intel_encoder *encoder;
5544 struct drm_mode_config *mode_config = &dev->mode_config;
5545 struct intel_encoder *edp_encoder = NULL;
5546 int num_connectors = 0;
5547 bool is_lvds = false;
5548
5549 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5550 if (encoder->base.crtc != crtc)
5551 continue;
5552
5553 switch (encoder->type) {
5554 case INTEL_OUTPUT_LVDS:
5555 is_lvds = true;
5556 break;
5557 case INTEL_OUTPUT_EDP:
5558 edp_encoder = encoder;
5559 break;
5560 }
5561 num_connectors++;
5562 }
5563
5564 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5565 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5566 dev_priv->lvds_ssc_freq);
5567 return dev_priv->lvds_ssc_freq * 1000;
5568 }
5569
5570 return 120000;
5571}
5572
f564048e
EA		 5573static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5574 struct drm_display_mode *mode,
5575 struct drm_display_mode *adjusted_mode,
5576 int x, int y,
5577 struct drm_framebuffer *old_fb)
79e53945
JB		 5578{
5579 struct drm_device *dev = crtc->dev;
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5582 int pipe = intel_crtc->pipe;
80824003 5583 int plane = intel_crtc->plane;
c751ce4f 5584 int refclk, num_connectors = 0;
652c393a 5585 intel_clock_t clock, reduced_clock;
5eddb70b 5586 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5587 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5588 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5589 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5590 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5591 struct intel_encoder *encoder;
d4906093 5592 const intel_limit_t *limit;
5c3b82e2 5593 int ret;
2c07245f 5594 struct fdi_m_n m_n = {0};
fae14981 5595 u32 temp;
aa9b500d 5596 u32 lvds_sync = 0;
5a354204
JB		 5597 int target_clock, pixel_multiplier, lane, link_bw, factor;
5598 unsigned int pipe_bpp;
5599 bool dither;
79e53945 5600
5eddb70b
CW		 5601 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5602 if (encoder->base.crtc != crtc)
79e53945
JB		 5603 continue;
5604
5eddb70b 5605 switch (encoder->type) {
79e53945
JB		 5606 case INTEL_OUTPUT_LVDS:
5607 is_lvds = true;
5608 break;
5609 case INTEL_OUTPUT_SDVO:
7d57382e 5610 case INTEL_OUTPUT_HDMI:
79e53945 5611 is_sdvo = true;
5eddb70b 5612 if (encoder->needs_tv_clock)
e2f0ba97 5613 is_tv = true;
79e53945 5614 break;
79e53945
JB		 5615 case INTEL_OUTPUT_TVOUT:
5616 is_tv = true;
5617 break;
5618 case INTEL_OUTPUT_ANALOG:
5619 is_crt = true;
5620 break;
a4fc5ed6
KP		 5621 case INTEL_OUTPUT_DISPLAYPORT:
5622 is_dp = true;
5623 break;
32f9d658 5624 case INTEL_OUTPUT_EDP:
5eddb70b 5625 has_edp_encoder = encoder;
32f9d658 5626 break;
79e53945 5627 }
43565a06 5628
c751ce4f 5629 num_connectors++;
79e53945
JB		 5630 }
5631
d9d444cb 5632 refclk = ironlake_get_refclk(crtc);
79e53945 5633
d4906093
ML		 5634 /*
5635 * Returns a set of divisors for the desired target clock with the given
5636 * refclk, or FALSE. The returned values represent the clock equation:
5637 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5638 */
1b894b59 5639 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5640 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5641 &clock);
79e53945
JB		 5642 if (!ok) {
5643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5644 return -EINVAL;
79e53945
JB		 5645 }
5646
cda4b7d3 5647 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5648 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5649
ddc9003c 5650 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5651 /*
5652 * Ensure we match the reduced clock's P to the target clock.
5653 * If the clocks don't match, we can't switch the display clock
5654 * by using the FP0/FP1. In such case we will disable the LVDS
5655 * downclock feature.
5656 */
ddc9003c 5657 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5658 dev_priv->lvds_downclock,
5659 refclk,
cec2f356 5660 &clock,
5eddb70b 5661 &reduced_clock);
652c393a 5662 }
7026d4ac
ZW		 5663 /* SDVO TV has fixed PLL values depend on its clock range,
5664 this mirrors vbios setting. */
5665 if (is_sdvo && is_tv) {
5666 if (adjusted_mode->clock >= 100000
5eddb70b 5667 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5668 clock.p1 = 2;
5669 clock.p2 = 10;
5670 clock.n = 3;
5671 clock.m1 = 16;
5672 clock.m2 = 8;
5673 } else if (adjusted_mode->clock >= 140500
5eddb70b 5674 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5675 clock.p1 = 1;
5676 clock.p2 = 10;
5677 clock.n = 6;
5678 clock.m1 = 12;
5679 clock.m2 = 8;
5680 }
5681 }
5682
2c07245f 5683 /* FDI link */
8febb297
EA		 5684 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5685 lane = 0;
5686 /* CPU eDP doesn't require FDI link, so just set DP M/N
5687 according to current link config */
5688 if (has_edp_encoder &&
5689 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5690 target_clock = mode->clock;
5691 intel_edp_link_config(has_edp_encoder,
5692 &lane, &link_bw);
5693 } else {
5694 /* [e]DP over FDI requires target mode clock
5695 instead of link clock */
5696 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5697 target_clock = mode->clock;
8febb297
EA		 5698 else
5699 target_clock = adjusted_mode->clock;
5700
5701 /* FDI is a binary signal running at ~2.7GHz, encoding
5702 * each output octet as 10 bits. The actual frequency
5703 * is stored as a divider into a 100MHz clock, and the
5704 * mode pixel clock is stored in units of 1KHz.
5705 * Hence the bw of each lane in terms of the mode signal
5706 * is:
5707 */
5708 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5709 }
58a27471 5710
8febb297
EA		 5711 /* determine panel color depth */
5712 temp = I915_READ(PIPECONF(pipe));
5713 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5714 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5715 switch (pipe_bpp) {
5716 case 18:
5717 temp |= PIPE_6BPC;
8febb297 5718 break;
5a354204
JB		 5719 case 24:
5720 temp |= PIPE_8BPC;
8febb297 5721 break;
5a354204
JB		 5722 case 30:
5723 temp |= PIPE_10BPC;
8febb297 5724 break;
5a354204
JB		 5725 case 36:
5726 temp |= PIPE_12BPC;
8febb297
EA		 5727 break;
5728 default:
62ac41a6
JB		 5729 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5730 pipe_bpp);
5a354204
JB		 5731 temp |= PIPE_8BPC;
5732 pipe_bpp = 24;
5733 break;
8febb297 5734 }
77ffb597 5735
5a354204
JB		 5736 intel_crtc->bpp = pipe_bpp;
5737 I915_WRITE(PIPECONF(pipe), temp);
5738
8febb297
EA		 5739 if (!lane) {
5740 /*
5741 * Account for spread spectrum to avoid
5742 * oversubscribing the link. Max center spread
5743 * is 2.5%; use 5% for safety's sake.
5744 */
5a354204 5745 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5746 lane = bps / (link_bw * 8) + 1;
5eb08b69 5747 }
2c07245f 5748
8febb297
EA		 5749 intel_crtc->fdi_lanes = lane;
5750
5751 if (pixel_multiplier > 1)
5752 link_bw *= pixel_multiplier;
5a354204
JB		 5753 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5754 &m_n);
8febb297 5755
a07d6787
EA		 5756 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5757 if (has_reduced_clock)
5758 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5759 reduced_clock.m2;
79e53945 5760
c1858123 5761 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5762 factor = 21;
5763 if (is_lvds) {
5764 if ((intel_panel_use_ssc(dev_priv) &&
5765 dev_priv->lvds_ssc_freq == 100) ||
5766 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5767 factor = 25;
5768 } else if (is_sdvo && is_tv)
5769 factor = 20;
c1858123 5770
cb0e0931 5771 if (clock.m < factor * clock.n)
8febb297 5772 fp |= FP_CB_TUNE;
2c07245f 5773
5eddb70b 5774 dpll = 0;
2c07245f 5775
a07d6787
EA		 5776 if (is_lvds)
5777 dpll |= DPLLB_MODE_LVDS;
5778 else
5779 dpll |= DPLLB_MODE_DAC_SERIAL;
5780 if (is_sdvo) {
5781 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5782 if (pixel_multiplier > 1) {
5783 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5784 }
a07d6787
EA		 5785 dpll |= DPLL_DVO_HIGH_SPEED;
5786 }
5787 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5788 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5789
a07d6787
EA		 5790 /* compute bitmask from p1 value */
5791 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5792 /* also FPA1 */
5793 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5794
5795 switch (clock.p2) {
5796 case 5:
5797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5798 break;
5799 case 7:
5800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5801 break;
5802 case 10:
5803 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5804 break;
5805 case 14:
5806 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5807 break;
79e53945
JB		 5808 }
5809
43565a06
KH		 5810 if (is_sdvo && is_tv)
5811 dpll |= PLL_REF_INPUT_TVCLKINBC;
5812 else if (is_tv)
79e53945 5813 /* XXX: just matching BIOS for now */
43565a06 5814 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5815 dpll |= 3;
a7615030 5816 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5817 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5818 else
5819 dpll |= PLL_REF_INPUT_DREFCLK;
5820
5821 /* setup pipeconf */
5eddb70b 5822 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5823
5824 /* Set up the display plane register */
5825 dspcntr = DISPPLANE_GAMMA_ENABLE;
5826
f7cb34d4 5827 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5828 drm_mode_debug_printmodeline(mode);
5829
5c5313c8 5830 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5831 if (!intel_crtc->no_pll) {
5832 if (!has_edp_encoder ||
5833 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5834 I915_WRITE(PCH_FP0(pipe), fp);
5835 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5836
5837 POSTING_READ(PCH_DPLL(pipe));
5838 udelay(150);
5839 }
5840 } else {
5841 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5842 fp == I915_READ(PCH_FP0(0))) {
5843 intel_crtc->use_pll_a = true;
5844 DRM_DEBUG_KMS("using pipe a dpll\n");
5845 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5846 fp == I915_READ(PCH_FP0(1))) {
5847 intel_crtc->use_pll_a = false;
5848 DRM_DEBUG_KMS("using pipe b dpll\n");
5849 } else {
5850 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5851 return -EINVAL;
5852 }
79e53945
JB		 5853 }
5854
5855 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5856 * This is an exception to the general rule that mode_set doesn't turn
5857 * things on.
5858 */
5859 if (is_lvds) {
fae14981 5860 temp = I915_READ(PCH_LVDS);
5eddb70b 5861 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4b645f14
JB		 5862 if (HAS_PCH_CPT(dev))
5863 temp |= PORT_TRANS_SEL_CPT(pipe);
5864 else if (pipe == 1)
5865 temp |= LVDS_PIPEB_SELECT;
5866 else
5867 temp &= ~LVDS_PIPEB_SELECT;
5868
a3e17eb8 5869 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5870 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5871 /* Set the B0-B3 data pairs corresponding to whether we're going to
5872 * set the DPLLs for dual-channel mode or not.
5873 */
5874 if (clock.p2 == 7)
5eddb70b 5875 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5876 else
5eddb70b 5877 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5878
5879 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5880 * appropriately here, but we need to look more thoroughly into how
5881 * panels behave in the two modes.
5882 */
aa9b500d
BF		 5883 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5884 lvds_sync |= LVDS_HSYNC_POLARITY;
5885 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5886 lvds_sync |= LVDS_VSYNC_POLARITY;
5887 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5888 != lvds_sync) {
5889 char flags[2] = "-+";
5890 DRM_INFO("Changing LVDS panel from "
5891 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5892 flags[!(temp & LVDS_HSYNC_POLARITY)],
5893 flags[!(temp & LVDS_VSYNC_POLARITY)],
5894 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5895 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5896 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5897 temp |= lvds_sync;
5898 }
fae14981 5899 I915_WRITE(PCH_LVDS, temp);
79e53945 5900 }
434ed097 5901
8febb297
EA		 5902 pipeconf &= ~PIPECONF_DITHER_EN;
5903 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5904 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5905 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5906 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5907 }
5c5313c8 5908 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5909 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5910 } else {
8db9d77b 5911 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5912 I915_WRITE(TRANSDATA_M1(pipe), 0);
5913 I915_WRITE(TRANSDATA_N1(pipe), 0);
5914 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5915 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5916 }
79e53945 5917
4b645f14
JB		 5918 if (!intel_crtc->no_pll &&
5919 (!has_edp_encoder ||
5920 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5921 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5922
32f9d658 5923 /* Wait for the clocks to stabilize. */
fae14981 5924 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5925 udelay(150);
5926
8febb297
EA		 5927 /* The pixel multiplier can only be updated once the
5928 * DPLL is enabled and the clocks are stable.
5929 *
5930 * So write it again.
5931 */
fae14981 5932 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5933 }
79e53945 5934
5eddb70b 5935 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5936 if (!intel_crtc->no_pll) {
5937 if (is_lvds && has_reduced_clock && i915_powersave) {
5938 I915_WRITE(PCH_FP1(pipe), fp2);
5939 intel_crtc->lowfreq_avail = true;
5940 if (HAS_PIPE_CXSR(dev)) {
5941 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5942 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5943 }
5944 } else {
5945 I915_WRITE(PCH_FP1(pipe), fp);
5946 if (HAS_PIPE_CXSR(dev)) {
5947 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5948 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5949 }
652c393a
JB		 5950 }
5951 }
5952
734b4157
KH		 5953 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5954 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5955 /* the chip adds 2 halflines automatically */
5956 adjusted_mode->crtc_vdisplay -= 1;
5957 adjusted_mode->crtc_vtotal -= 1;
5958 adjusted_mode->crtc_vblank_start -= 1;
5959 adjusted_mode->crtc_vblank_end -= 1;
5960 adjusted_mode->crtc_vsync_end -= 1;
5961 adjusted_mode->crtc_vsync_start -= 1;
5962 } else
5963 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5964
5eddb70b
CW		 5965 I915_WRITE(HTOTAL(pipe),
5966 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5967 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5968 I915_WRITE(HBLANK(pipe),
5969 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5970 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5971 I915_WRITE(HSYNC(pipe),
5972 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5973 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5974
5975 I915_WRITE(VTOTAL(pipe),
5976 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5977 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5978 I915_WRITE(VBLANK(pipe),
5979 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5980 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5981 I915_WRITE(VSYNC(pipe),
5982 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5983 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5984
8febb297
EA		 5985 /* pipesrc controls the size that is scaled from, which should
5986 * always be the user's requested size.
79e53945 5987 */
5eddb70b
CW		 5988 I915_WRITE(PIPESRC(pipe),
5989 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5990
8febb297
EA		 5991 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5992 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5993 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5994 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5995
8febb297
EA		 5996 if (has_edp_encoder &&
5997 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5998 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5999 }
6000
5eddb70b
CW		 6001 I915_WRITE(PIPECONF(pipe), pipeconf);
6002 POSTING_READ(PIPECONF(pipe));
79e53945 6003
9d0498a2 6004 intel_wait_for_vblank(dev, pipe);
79e53945 6005
f00a3ddf 6006 if (IS_GEN5(dev)) {
553bd149
ZW		 6007 /* enable address swizzle for tiling buffer */
6008 temp = I915_READ(DISP_ARB_CTL);
6009 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6010 }
6011
5eddb70b 6012 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6013 POSTING_READ(DSPCNTR(plane));
79e53945 6014
5c3b82e2 6015 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6016
6017 intel_update_watermarks(dev);
6018
1f803ee5 6019 return ret;
79e53945
JB		 6020}
6021
f564048e
EA		 6022static int intel_crtc_mode_set(struct drm_crtc *crtc,
6023 struct drm_display_mode *mode,
6024 struct drm_display_mode *adjusted_mode,
6025 int x, int y,
6026 struct drm_framebuffer *old_fb)
6027{
6028 struct drm_device *dev = crtc->dev;
6029 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 int pipe = intel_crtc->pipe;
f564048e
EA		 6032 int ret;
6033
0b701d27 6034 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6035
f564048e
EA		 6036 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6037 x, y, old_fb);
79e53945 6038 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6039
d8e70a25
JB		 6040 if (ret)
6041 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6042 else
6043 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6044
1f803ee5 6045 return ret;
79e53945
JB		 6046}
6047
3a9627f4
WF		 6048static bool intel_eld_uptodate(struct drm_connector *connector,
6049 int reg_eldv, uint32_t bits_eldv,
6050 int reg_elda, uint32_t bits_elda,
6051 int reg_edid)
6052{
6053 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6054 uint8_t *eld = connector->eld;
6055 uint32_t i;
6056
6057 i = I915_READ(reg_eldv);
6058 i &= bits_eldv;
6059
6060 if (!eld[0])
6061 return !i;
6062
6063 if (!i)
6064 return false;
6065
6066 i = I915_READ(reg_elda);
6067 i &= ~bits_elda;
6068 I915_WRITE(reg_elda, i);
6069
6070 for (i = 0; i < eld[2]; i++)
6071 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6072 return false;
6073
6074 return true;
6075}
6076
e0dac65e
WF		 6077static void g4x_write_eld(struct drm_connector *connector,
6078 struct drm_crtc *crtc)
6079{
6080 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6081 uint8_t *eld = connector->eld;
6082 uint32_t eldv;
6083 uint32_t len;
6084 uint32_t i;
6085
6086 i = I915_READ(G4X_AUD_VID_DID);
6087
6088 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6089 eldv = G4X_ELDV_DEVCL_DEVBLC;
6090 else
6091 eldv = G4X_ELDV_DEVCTG;
6092
3a9627f4
WF		 6093 if (intel_eld_uptodate(connector,
6094 G4X_AUD_CNTL_ST, eldv,
6095 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6096 G4X_HDMIW_HDMIEDID))
6097 return;
6098
e0dac65e
WF		 6099 i = I915_READ(G4X_AUD_CNTL_ST);
6100 i &= ~(eldv | G4X_ELD_ADDR);
6101 len = (i >> 9) & 0x1f; /* ELD buffer size */
6102 I915_WRITE(G4X_AUD_CNTL_ST, i);
6103
6104 if (!eld[0])
6105 return;
6106
6107 len = min_t(uint8_t, eld[2], len);
6108 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6109 for (i = 0; i < len; i++)
6110 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6111
6112 i = I915_READ(G4X_AUD_CNTL_ST);
6113 i |= eldv;
6114 I915_WRITE(G4X_AUD_CNTL_ST, i);
6115}
6116
6117static void ironlake_write_eld(struct drm_connector *connector,
6118 struct drm_crtc *crtc)
6119{
6120 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6121 uint8_t *eld = connector->eld;
6122 uint32_t eldv;
6123 uint32_t i;
6124 int len;
6125 int hdmiw_hdmiedid;
6126 int aud_cntl_st;
6127 int aud_cntrl_st2;
6128
b3f33cbf 6129 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6
WF		 6130 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6131 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6132 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6133 } else {
1202b4c6
WF		 6134 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6135 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6136 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6137 }
6138
6139 i = to_intel_crtc(crtc)->pipe;
6140 hdmiw_hdmiedid += i * 0x100;
6141 aud_cntl_st += i * 0x100;
6142
6143 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6144
6145 i = I915_READ(aud_cntl_st);
6146 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6147 if (!i) {
6148 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6149 /* operate blindly on all ports */
1202b4c6
WF		 6150 eldv = IBX_ELD_VALIDB;
6151 eldv |= IBX_ELD_VALIDB << 4;
6152 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6153 } else {
6154 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6155 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6156 }
6157
3a9627f4
WF		 6158 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6159 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6160 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
e0dac65e
WF		 6161 }
6162
3a9627f4
WF		 6163 if (intel_eld_uptodate(connector,
6164 aud_cntrl_st2, eldv,
6165 aud_cntl_st, IBX_ELD_ADDRESS,
6166 hdmiw_hdmiedid))
6167 return;
6168
e0dac65e
WF		 6169 i = I915_READ(aud_cntrl_st2);
6170 i &= ~eldv;
6171 I915_WRITE(aud_cntrl_st2, i);
6172
6173 if (!eld[0])
6174 return;
6175
e0dac65e 6176 i = I915_READ(aud_cntl_st);
1202b4c6 6177 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6178 I915_WRITE(aud_cntl_st, i);
6179
6180 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6181 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6182 for (i = 0; i < len; i++)
6183 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6184
6185 i = I915_READ(aud_cntrl_st2);
6186 i |= eldv;
6187 I915_WRITE(aud_cntrl_st2, i);
6188}
6189
6190void intel_write_eld(struct drm_encoder *encoder,
6191 struct drm_display_mode *mode)
6192{
6193 struct drm_crtc *crtc = encoder->crtc;
6194 struct drm_connector *connector;
6195 struct drm_device *dev = encoder->dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197
6198 connector = drm_select_eld(encoder, mode);
6199 if (!connector)
6200 return;
6201
6202 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6203 connector->base.id,
6204 drm_get_connector_name(connector),
6205 connector->encoder->base.id,
6206 drm_get_encoder_name(connector->encoder));
6207
6208 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6209
6210 if (dev_priv->display.write_eld)
6211 dev_priv->display.write_eld(connector, crtc);
6212}
6213
79e53945
JB		 6214/** Loads the palette/gamma unit for the CRTC with the prepared values */
6215void intel_crtc_load_lut(struct drm_crtc *crtc)
6216{
6217 struct drm_device *dev = crtc->dev;
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6220 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6221 int i;
6222
6223 /* The clocks have to be on to load the palette. */
6224 if (!crtc->enabled)
6225 return;
6226
f2b115e6 6227 /* use legacy palette for Ironlake */
bad720ff 6228 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6229 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6230
79e53945
JB		 6231 for (i = 0; i < 256; i++) {
6232 I915_WRITE(palreg + 4 * i,
6233 (intel_crtc->lut_r[i] << 16) |
6234 (intel_crtc->lut_g[i] << 8) |
6235 intel_crtc->lut_b[i]);
6236 }
6237}
6238
560b85bb
CW		 6239static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6240{
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244 bool visible = base != 0;
6245 u32 cntl;
6246
6247 if (intel_crtc->cursor_visible == visible)
6248 return;
6249
9db4a9c7 6250 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6251 if (visible) {
6252 /* On these chipsets we can only modify the base whilst
6253 * the cursor is disabled.
6254 */
9db4a9c7 6255 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6256
6257 cntl &= ~(CURSOR_FORMAT_MASK);
6258 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6259 cntl |= CURSOR_ENABLE |
6260 CURSOR_GAMMA_ENABLE |
6261 CURSOR_FORMAT_ARGB;
6262 } else
6263 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6264 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6265
6266 intel_crtc->cursor_visible = visible;
6267}
6268
6269static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6270{
6271 struct drm_device *dev = crtc->dev;
6272 struct drm_i915_private *dev_priv = dev->dev_private;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 int pipe = intel_crtc->pipe;
6275 bool visible = base != 0;
6276
6277 if (intel_crtc->cursor_visible != visible) {
548f245b 6278 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6279 if (base) {
6280 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6281 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6282 cntl |= pipe << 28; /* Connect to correct pipe */
6283 } else {
6284 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6285 cntl |= CURSOR_MODE_DISABLE;
6286 }
9db4a9c7 6287 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6288
6289 intel_crtc->cursor_visible = visible;
6290 }
6291 /* and commit changes on next vblank */
9db4a9c7 6292 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6293}
6294
65a21cd6
JB		 6295static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6296{
6297 struct drm_device *dev = crtc->dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300 int pipe = intel_crtc->pipe;
6301 bool visible = base != 0;
6302
6303 if (intel_crtc->cursor_visible != visible) {
6304 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6305 if (base) {
6306 cntl &= ~CURSOR_MODE;
6307 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6308 } else {
6309 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6310 cntl |= CURSOR_MODE_DISABLE;
6311 }
6312 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6313
6314 intel_crtc->cursor_visible = visible;
6315 }
6316 /* and commit changes on next vblank */
6317 I915_WRITE(CURBASE_IVB(pipe), base);
6318}
6319
cda4b7d3 6320/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6321static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6322 bool on)
cda4b7d3
CW		 6323{
6324 struct drm_device *dev = crtc->dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6327 int pipe = intel_crtc->pipe;
6328 int x = intel_crtc->cursor_x;
6329 int y = intel_crtc->cursor_y;
560b85bb 6330 u32 base, pos;
cda4b7d3
CW		 6331 bool visible;
6332
6333 pos = 0;
6334
6b383a7f 6335 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6336 base = intel_crtc->cursor_addr;
6337 if (x > (int) crtc->fb->width)
6338 base = 0;
6339
6340 if (y > (int) crtc->fb->height)
6341 base = 0;
6342 } else
6343 base = 0;
6344
6345 if (x < 0) {
6346 if (x + intel_crtc->cursor_width < 0)
6347 base = 0;
6348
6349 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6350 x = -x;
6351 }
6352 pos |= x << CURSOR_X_SHIFT;
6353
6354 if (y < 0) {
6355 if (y + intel_crtc->cursor_height < 0)
6356 base = 0;
6357
6358 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6359 y = -y;
6360 }
6361 pos |= y << CURSOR_Y_SHIFT;
6362
6363 visible = base != 0;
560b85bb 6364 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6365 return;
6366
65a21cd6
JB		 6367 if (IS_IVYBRIDGE(dev)) {
6368 I915_WRITE(CURPOS_IVB(pipe), pos);
6369 ivb_update_cursor(crtc, base);
6370 } else {
6371 I915_WRITE(CURPOS(pipe), pos);
6372 if (IS_845G(dev) || IS_I865G(dev))
6373 i845_update_cursor(crtc, base);
6374 else
6375 i9xx_update_cursor(crtc, base);
6376 }
cda4b7d3
CW		 6377
6378 if (visible)
6379 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6380}
6381
79e53945 6382static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6383 struct drm_file *file,
79e53945
JB		 6384 uint32_t handle,
6385 uint32_t width, uint32_t height)
6386{
6387 struct drm_device *dev = crtc->dev;
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6390 struct drm_i915_gem_object *obj;
cda4b7d3 6391 uint32_t addr;
3f8bc370 6392 int ret;
79e53945 6393
28c97730 6394 DRM_DEBUG_KMS("\n");
79e53945
JB		 6395
6396 /* if we want to turn off the cursor ignore width and height */
6397 if (!handle) {
28c97730 6398 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6399 addr = 0;
05394f39 6400 obj = NULL;
5004417d 6401 mutex_lock(&dev->struct_mutex);
3f8bc370 6402 goto finish;
79e53945
JB		 6403 }
6404
6405 /* Currently we only support 64x64 cursors */
6406 if (width != 64 || height != 64) {
6407 DRM_ERROR("we currently only support 64x64 cursors\n");
6408 return -EINVAL;
6409 }
6410
05394f39 6411 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6412 if (&obj->base == NULL)
79e53945
JB		 6413 return -ENOENT;
6414
05394f39 6415 if (obj->base.size < width * height * 4) {
79e53945 6416 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6417 ret = -ENOMEM;
6418 goto fail;
79e53945
JB		 6419 }
6420
71acb5eb 6421 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6422 mutex_lock(&dev->struct_mutex);
b295d1b6 6423 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6424 if (obj->tiling_mode) {
6425 DRM_ERROR("cursor cannot be tiled\n");
6426 ret = -EINVAL;
6427 goto fail_locked;
6428 }
6429
2da3b9b9 6430 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6431 if (ret) {
6432 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6433 goto fail_locked;
e7b526bb
CW		 6434 }
6435
d9e86c0e
CW		 6436 ret = i915_gem_object_put_fence(obj);
6437 if (ret) {
2da3b9b9 6438 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6439 goto fail_unpin;
6440 }
6441
05394f39 6442 addr = obj->gtt_offset;
71acb5eb 6443 } else {
6eeefaf3 6444 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6445 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6446 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6447 align);
71acb5eb
DA		 6448 if (ret) {
6449 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6450 goto fail_locked;
71acb5eb 6451 }
05394f39 6452 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6453 }
6454
a6c45cf0 6455 if (IS_GEN2(dev))
14b60391
JB		 6456 I915_WRITE(CURSIZE, (height << 12) | width);
6457
3f8bc370 6458 finish:
3f8bc370 6459 if (intel_crtc->cursor_bo) {
b295d1b6 6460 if (dev_priv->info->cursor_needs_physical) {
05394f39 6461 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6462 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6463 } else
6464 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6465 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6466 }
80824003 6467
7f9872e0 6468 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6469
6470 intel_crtc->cursor_addr = addr;
05394f39 6471 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6472 intel_crtc->cursor_width = width;
6473 intel_crtc->cursor_height = height;
6474
6b383a7f 6475 intel_crtc_update_cursor(crtc, true);
3f8bc370 6476
79e53945 6477 return 0;
e7b526bb 6478fail_unpin:
05394f39 6479 i915_gem_object_unpin(obj);
7f9872e0 6480fail_locked:
34b8686e 6481 mutex_unlock(&dev->struct_mutex);
bc9025bd 6482fail:
05394f39 6483 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6484 return ret;
79e53945
JB		 6485}
6486
6487static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6488{
79e53945 6489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6490
cda4b7d3
CW		 6491 intel_crtc->cursor_x = x;
6492 intel_crtc->cursor_y = y;
652c393a 6493
6b383a7f 6494 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6495
6496 return 0;
6497}
6498
6499/** Sets the color ramps on behalf of RandR */
6500void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6501 u16 blue, int regno)
6502{
6503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6504
6505 intel_crtc->lut_r[regno] = red >> 8;
6506 intel_crtc->lut_g[regno] = green >> 8;
6507 intel_crtc->lut_b[regno] = blue >> 8;
6508}
6509
b8c00ac5
DA		 6510void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6511 u16 *blue, int regno)
6512{
6513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6514
6515 *red = intel_crtc->lut_r[regno] << 8;
6516 *green = intel_crtc->lut_g[regno] << 8;
6517 *blue = intel_crtc->lut_b[regno] << 8;
6518}
6519
79e53945 6520static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6521 u16 *blue, uint32_t start, uint32_t size)
79e53945 6522{
7203425a 6523 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6525
7203425a 6526 for (i = start; i < end; i++) {
79e53945
JB		 6527 intel_crtc->lut_r[i] = red[i] >> 8;
6528 intel_crtc->lut_g[i] = green[i] >> 8;
6529 intel_crtc->lut_b[i] = blue[i] >> 8;
6530 }
6531
6532 intel_crtc_load_lut(crtc);
6533}
6534
6535/**
6536 * Get a pipe with a simple mode set on it for doing load-based monitor
6537 * detection.
6538 *
6539 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6540 * its requirements. The pipe will be connected to no other encoders.
79e53945 6541 *
c751ce4f 6542 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6543 * configured for it. In the future, it could choose to temporarily disable
6544 * some outputs to free up a pipe for its use.
6545 *
6546 * \return crtc, or NULL if no pipes are available.
6547 */
6548
6549/* VESA 640x480x72Hz mode to set on the pipe */
6550static struct drm_display_mode load_detect_mode = {
6551 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6552 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6553};
6554
d2dff872
CW		 6555static struct drm_framebuffer *
6556intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6557 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6558 struct drm_i915_gem_object *obj)
6559{
6560 struct intel_framebuffer *intel_fb;
6561 int ret;
6562
6563 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6564 if (!intel_fb) {
6565 drm_gem_object_unreference_unlocked(&obj->base);
6566 return ERR_PTR(-ENOMEM);
6567 }
6568
6569 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6570 if (ret) {
6571 drm_gem_object_unreference_unlocked(&obj->base);
6572 kfree(intel_fb);
6573 return ERR_PTR(ret);
6574 }
6575
6576 return &intel_fb->base;
6577}
6578
6579static u32
6580intel_framebuffer_pitch_for_width(int width, int bpp)
6581{
6582 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6583 return ALIGN(pitch, 64);
6584}
6585
6586static u32
6587intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6588{
6589 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6590 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6591}
6592
6593static struct drm_framebuffer *
6594intel_framebuffer_create_for_mode(struct drm_device *dev,
6595 struct drm_display_mode *mode,
6596 int depth, int bpp)
6597{
6598 struct drm_i915_gem_object *obj;
308e5bcb 6599 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6600
6601 obj = i915_gem_alloc_object(dev,
6602 intel_framebuffer_size_for_mode(mode, bpp));
6603 if (obj == NULL)
6604 return ERR_PTR(-ENOMEM);
6605
6606 mode_cmd.width = mode->hdisplay;
6607 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6608 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6609 bpp);
6610 mode_cmd.pixel_format = 0;
d2dff872
CW		 6611
6612 return intel_framebuffer_create(dev, &mode_cmd, obj);
6613}
6614
6615static struct drm_framebuffer *
6616mode_fits_in_fbdev(struct drm_device *dev,
6617 struct drm_display_mode *mode)
6618{
6619 struct drm_i915_private *dev_priv = dev->dev_private;
6620 struct drm_i915_gem_object *obj;
6621 struct drm_framebuffer *fb;
6622
6623 if (dev_priv->fbdev == NULL)
6624 return NULL;
6625
6626 obj = dev_priv->fbdev->ifb.obj;
6627 if (obj == NULL)
6628 return NULL;
6629
6630 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6631 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6632 fb->bits_per_pixel))
d2dff872
CW		 6633 return NULL;
6634
01f2c773 6635 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6636 return NULL;
6637
6638 return fb;
6639}
6640
7173188d
CW		 6641bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6642 struct drm_connector *connector,
6643 struct drm_display_mode *mode,
8261b191 6644 struct intel_load_detect_pipe *old)
79e53945
JB		 6645{
6646 struct intel_crtc *intel_crtc;
6647 struct drm_crtc *possible_crtc;
4ef69c7a 6648 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6649 struct drm_crtc *crtc = NULL;
6650 struct drm_device *dev = encoder->dev;
d2dff872 6651 struct drm_framebuffer *old_fb;
79e53945
JB		 6652 int i = -1;
6653
d2dff872
CW		 6654 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6655 connector->base.id, drm_get_connector_name(connector),
6656 encoder->base.id, drm_get_encoder_name(encoder));
6657
79e53945
JB		 6658 /*
6659 * Algorithm gets a little messy:
7a5e4805 6660 *
79e53945
JB		 6661 * - if the connector already has an assigned crtc, use it (but make
6662 * sure it's on first)
7a5e4805 6663 *
79e53945
JB		 6664 * - try to find the first unused crtc that can drive this connector,
6665 * and use that if we find one
79e53945
JB		 6666 */
6667
6668 /* See if we already have a CRTC for this connector */
6669 if (encoder->crtc) {
6670 crtc = encoder->crtc;
8261b191 6671
79e53945 6672 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6673 old->dpms_mode = intel_crtc->dpms_mode;
6674 old->load_detect_temp = false;
6675
6676 /* Make sure the crtc and connector are running */
79e53945 6677 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6678 struct drm_encoder_helper_funcs *encoder_funcs;
6679 struct drm_crtc_helper_funcs *crtc_funcs;
6680
79e53945
JB		 6681 crtc_funcs = crtc->helper_private;
6682 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6683
6684 encoder_funcs = encoder->helper_private;
79e53945
JB		 6685 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6686 }
8261b191 6687
7173188d 6688 return true;
79e53945
JB		 6689 }
6690
6691 /* Find an unused one (if possible) */
6692 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6693 i++;
6694 if (!(encoder->possible_crtcs & (1 << i)))
6695 continue;
6696 if (!possible_crtc->enabled) {
6697 crtc = possible_crtc;
6698 break;
6699 }
79e53945
JB		 6700 }
6701
6702 /*
6703 * If we didn't find an unused CRTC, don't use any.
6704 */
6705 if (!crtc) {
7173188d
CW		 6706 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6707 return false;
79e53945
JB		 6708 }
6709
6710 encoder->crtc = crtc;
c1c43977 6711 connector->encoder = encoder;
79e53945
JB		 6712
6713 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6714 old->dpms_mode = intel_crtc->dpms_mode;
6715 old->load_detect_temp = true;
d2dff872 6716 old->release_fb = NULL;
79e53945 6717
6492711d
CW		 6718 if (!mode)
6719 mode = &load_detect_mode;
79e53945 6720
d2dff872
CW		 6721 old_fb = crtc->fb;
6722
6723 /* We need a framebuffer large enough to accommodate all accesses
6724 * that the plane may generate whilst we perform load detection.
6725 * We can not rely on the fbcon either being present (we get called
6726 * during its initialisation to detect all boot displays, or it may
6727 * not even exist) or that it is large enough to satisfy the
6728 * requested mode.
6729 */
6730 crtc->fb = mode_fits_in_fbdev(dev, mode);
6731 if (crtc->fb == NULL) {
6732 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6733 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6734 old->release_fb = crtc->fb;
6735 } else
6736 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6737 if (IS_ERR(crtc->fb)) {
6738 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6739 crtc->fb = old_fb;
6740 return false;
79e53945 6741 }
79e53945 6742
d2dff872 6743 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6744 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6745 if (old->release_fb)
6746 old->release_fb->funcs->destroy(old->release_fb);
6747 crtc->fb = old_fb;
6492711d 6748 return false;
79e53945 6749 }
7173188d 6750
79e53945 6751 /* let the connector get through one full cycle before testing */
9d0498a2 6752 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6753
7173188d 6754 return true;
79e53945
JB		 6755}
6756
c1c43977 6757void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6758 struct drm_connector *connector,
6759 struct intel_load_detect_pipe *old)
79e53945 6760{
4ef69c7a 6761 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6762 struct drm_device *dev = encoder->dev;
6763 struct drm_crtc *crtc = encoder->crtc;
6764 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6765 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6766
d2dff872
CW		 6767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6768 connector->base.id, drm_get_connector_name(connector),
6769 encoder->base.id, drm_get_encoder_name(encoder));
6770
8261b191 6771 if (old->load_detect_temp) {
c1c43977 6772 connector->encoder = NULL;
79e53945 6773 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6774
6775 if (old->release_fb)
6776 old->release_fb->funcs->destroy(old->release_fb);
6777
0622a53c 6778 return;
79e53945
JB		 6779 }
6780
c751ce4f 6781 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6782 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6783 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6784 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6785 }
6786}
6787
6788/* Returns the clock of the currently programmed mode of the given pipe. */
6789static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6790{
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793 int pipe = intel_crtc->pipe;
548f245b 6794 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6795 u32 fp;
6796 intel_clock_t clock;
6797
6798 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6799 fp = I915_READ(FP0(pipe));
79e53945 6800 else
39adb7a5 6801 fp = I915_READ(FP1(pipe));
79e53945
JB		 6802
6803 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6804 if (IS_PINEVIEW(dev)) {
6805 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6806 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6807 } else {
6808 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6809 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6810 }
6811
a6c45cf0 6812 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6813 if (IS_PINEVIEW(dev))
6814 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6815 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6816 else
6817 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6818 DPLL_FPA01_P1_POST_DIV_SHIFT);
6819
6820 switch (dpll & DPLL_MODE_MASK) {
6821 case DPLLB_MODE_DAC_SERIAL:
6822 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6823 5 : 10;
6824 break;
6825 case DPLLB_MODE_LVDS:
6826 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6827 7 : 14;
6828 break;
6829 default:
28c97730 6830 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6831 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6832 return 0;
6833 }
6834
6835 /* XXX: Handle the 100Mhz refclk */
2177832f 6836 intel_clock(dev, 96000, &clock);
79e53945
JB		 6837 } else {
6838 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6839
6840 if (is_lvds) {
6841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6842 DPLL_FPA01_P1_POST_DIV_SHIFT);
6843 clock.p2 = 14;
6844
6845 if ((dpll & PLL_REF_INPUT_MASK) ==
6846 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6847 /* XXX: might not be 66MHz */
2177832f 6848 intel_clock(dev, 66000, &clock);
79e53945 6849 } else
2177832f 6850 intel_clock(dev, 48000, &clock);
79e53945
JB		 6851 } else {
6852 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6853 clock.p1 = 2;
6854 else {
6855 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6856 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6857 }
6858 if (dpll & PLL_P2_DIVIDE_BY_4)
6859 clock.p2 = 4;
6860 else
6861 clock.p2 = 2;
6862
2177832f 6863 intel_clock(dev, 48000, &clock);
79e53945
JB		 6864 }
6865 }
6866
6867 /* XXX: It would be nice to validate the clocks, but we can't reuse
6868 * i830PllIsValid() because it relies on the xf86_config connector
6869 * configuration being accurate, which it isn't necessarily.
6870 */
6871
6872 return clock.dot;
6873}
6874
6875/** Returns the currently programmed mode of the given pipe. */
6876struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6877 struct drm_crtc *crtc)
6878{
548f245b 6879 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6881 int pipe = intel_crtc->pipe;
6882 struct drm_display_mode *mode;
548f245b
JB		 6883 int htot = I915_READ(HTOTAL(pipe));
6884 int hsync = I915_READ(HSYNC(pipe));
6885 int vtot = I915_READ(VTOTAL(pipe));
6886 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6887
6888 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6889 if (!mode)
6890 return NULL;
6891
6892 mode->clock = intel_crtc_clock_get(dev, crtc);
6893 mode->hdisplay = (htot & 0xffff) + 1;
6894 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6895 mode->hsync_start = (hsync & 0xffff) + 1;
6896 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6897 mode->vdisplay = (vtot & 0xffff) + 1;
6898 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6899 mode->vsync_start = (vsync & 0xffff) + 1;
6900 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6901
6902 drm_mode_set_name(mode);
6903 drm_mode_set_crtcinfo(mode, 0);
6904
6905 return mode;
6906}
6907
652c393a
JB		 6908#define GPU_IDLE_TIMEOUT 500 /* ms */
6909
6910/* When this timer fires, we've been idle for awhile */
6911static void intel_gpu_idle_timer(unsigned long arg)
6912{
6913 struct drm_device *dev = (struct drm_device *)arg;
6914 drm_i915_private_t *dev_priv = dev->dev_private;
6915
ff7ea4c0
CW		 6916 if (!list_empty(&dev_priv->mm.active_list)) {
6917 /* Still processing requests, so just re-arm the timer. */
6918 mod_timer(&dev_priv->idle_timer, jiffies +
6919 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6920 return;
6921 }
652c393a 6922
ff7ea4c0 6923 dev_priv->busy = false;
01dfba93 6924 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6925}
6926
652c393a
JB		 6927#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6928
6929static void intel_crtc_idle_timer(unsigned long arg)
6930{
6931 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6932 struct drm_crtc *crtc = &intel_crtc->base;
6933 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6934 struct intel_framebuffer *intel_fb;
652c393a 6935
ff7ea4c0
CW		 6936 intel_fb = to_intel_framebuffer(crtc->fb);
6937 if (intel_fb && intel_fb->obj->active) {
6938 /* The framebuffer is still being accessed by the GPU. */
6939 mod_timer(&intel_crtc->idle_timer, jiffies +
6940 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6941 return;
6942 }
652c393a 6943
ff7ea4c0 6944 intel_crtc->busy = false;
01dfba93 6945 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6946}
6947
3dec0095 6948static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6949{
6950 struct drm_device *dev = crtc->dev;
6951 drm_i915_private_t *dev_priv = dev->dev_private;
6952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6953 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6954 int dpll_reg = DPLL(pipe);
6955 int dpll;
652c393a 6956
bad720ff 6957 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6958 return;
6959
6960 if (!dev_priv->lvds_downclock_avail)
6961 return;
6962
dbdc6479 6963 dpll = I915_READ(dpll_reg);
652c393a 6964 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6965 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6966
6967 /* Unlock panel regs */
dbdc6479
JB		 6968 I915_WRITE(PP_CONTROL,
6969 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6970
6971 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6972 I915_WRITE(dpll_reg, dpll);
9d0498a2 6973 intel_wait_for_vblank(dev, pipe);
dbdc6479 6974
652c393a
JB		 6975 dpll = I915_READ(dpll_reg);
6976 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6977 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6978
6979 /* ...and lock them again */
6980 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6981 }
6982
6983 /* Schedule downclock */
3dec0095
DV		 6984 mod_timer(&intel_crtc->idle_timer, jiffies +
6985 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6986}
6987
6988static void intel_decrease_pllclock(struct drm_crtc *crtc)
6989{
6990 struct drm_device *dev = crtc->dev;
6991 drm_i915_private_t *dev_priv = dev->dev_private;
6992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993 int pipe = intel_crtc->pipe;
9db4a9c7 6994 int dpll_reg = DPLL(pipe);
652c393a
JB		 6995 int dpll = I915_READ(dpll_reg);
6996
bad720ff 6997 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6998 return;
6999
7000 if (!dev_priv->lvds_downclock_avail)
7001 return;
7002
7003 /*
7004 * Since this is called by a timer, we should never get here in
7005 * the manual case.
7006 */
7007 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7008 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 7009
7010 /* Unlock panel regs */
4a655f04
JB		 7011 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7012 PANEL_UNLOCK_REGS);
652c393a
JB		 7013
7014 dpll |= DISPLAY_RATE_SELECT_FPA1;
7015 I915_WRITE(dpll_reg, dpll);
9d0498a2 7016 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7017 dpll = I915_READ(dpll_reg);
7018 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7019 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7020
7021 /* ...and lock them again */
7022 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7023 }
7024
7025}
7026
7027/**
7028 * intel_idle_update - adjust clocks for idleness
7029 * @work: work struct
7030 *
7031 * Either the GPU or display (or both) went idle. Check the busy status
7032 * here and adjust the CRTC and GPU clocks as necessary.
7033 */
7034static void intel_idle_update(struct work_struct *work)
7035{
7036 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7037 idle_work);
7038 struct drm_device *dev = dev_priv->dev;
7039 struct drm_crtc *crtc;
7040 struct intel_crtc *intel_crtc;
7041
7042 if (!i915_powersave)
7043 return;
7044
7045 mutex_lock(&dev->struct_mutex);
7046
7648fa99
JB		 7047 i915_update_gfx_val(dev_priv);
7048
652c393a
JB		 7049 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7050 /* Skip inactive CRTCs */
7051 if (!crtc->fb)
7052 continue;
7053
7054 intel_crtc = to_intel_crtc(crtc);
7055 if (!intel_crtc->busy)
7056 intel_decrease_pllclock(crtc);
7057 }
7058
45ac22c8 7059
652c393a
JB		 7060 mutex_unlock(&dev->struct_mutex);
7061}
7062
7063/**
7064 * intel_mark_busy - mark the GPU and possibly the display busy
7065 * @dev: drm device
7066 * @obj: object we're operating on
7067 *
7068 * Callers can use this function to indicate that the GPU is busy processing
7069 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7070 * buffer), we'll also mark the display as busy, so we know to increase its
7071 * clock frequency.
7072 */
05394f39 7073void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7074{
7075 drm_i915_private_t *dev_priv = dev->dev_private;
7076 struct drm_crtc *crtc = NULL;
7077 struct intel_framebuffer *intel_fb;
7078 struct intel_crtc *intel_crtc;
7079
5e17ee74
ZW		 7080 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7081 return;
7082
18b2190c 7083 if (!dev_priv->busy)
28cf798f 7084 dev_priv->busy = true;
18b2190c 7085 else
28cf798f
CW		 7086 mod_timer(&dev_priv->idle_timer, jiffies +
7087 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7088
7089 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7090 if (!crtc->fb)
7091 continue;
7092
7093 intel_crtc = to_intel_crtc(crtc);
7094 intel_fb = to_intel_framebuffer(crtc->fb);
7095 if (intel_fb->obj == obj) {
7096 if (!intel_crtc->busy) {
7097 /* Non-busy -> busy, upclock */
3dec0095 7098 intel_increase_pllclock(crtc);
652c393a
JB		 7099 intel_crtc->busy = true;
7100 } else {
7101 /* Busy -> busy, put off timer */
7102 mod_timer(&intel_crtc->idle_timer, jiffies +
7103 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7104 }
7105 }
7106 }
7107}
7108
79e53945
JB		 7109static void intel_crtc_destroy(struct drm_crtc *crtc)
7110{
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7112 struct drm_device *dev = crtc->dev;
7113 struct intel_unpin_work *work;
7114 unsigned long flags;
7115
7116 spin_lock_irqsave(&dev->event_lock, flags);
7117 work = intel_crtc->unpin_work;
7118 intel_crtc->unpin_work = NULL;
7119 spin_unlock_irqrestore(&dev->event_lock, flags);
7120
7121 if (work) {
7122 cancel_work_sync(&work->work);
7123 kfree(work);
7124 }
79e53945
JB		 7125
7126 drm_crtc_cleanup(crtc);
67e77c5a 7127
79e53945
JB		 7128 kfree(intel_crtc);
7129}
7130
6b95a207
KH		 7131static void intel_unpin_work_fn(struct work_struct *__work)
7132{
7133 struct intel_unpin_work *work =
7134 container_of(__work, struct intel_unpin_work, work);
7135
7136 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 7137 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 7138 drm_gem_object_unreference(&work->pending_flip_obj->base);
7139 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7140
7782de3b 7141 intel_update_fbc(work->dev);
6b95a207
KH		 7142 mutex_unlock(&work->dev->struct_mutex);
7143 kfree(work);
7144}
7145
1afe3e9d 7146static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7147 struct drm_crtc *crtc)
6b95a207
KH		 7148{
7149 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7151 struct intel_unpin_work *work;
05394f39 7152 struct drm_i915_gem_object *obj;
6b95a207 7153 struct drm_pending_vblank_event *e;
49b14a5c 7154 struct timeval tnow, tvbl;
6b95a207
KH		 7155 unsigned long flags;
7156
7157 /* Ignore early vblank irqs */
7158 if (intel_crtc == NULL)
7159 return;
7160
49b14a5c
MK		 7161 do_gettimeofday(&tnow);
7162
6b95a207
KH		 7163 spin_lock_irqsave(&dev->event_lock, flags);
7164 work = intel_crtc->unpin_work;
7165 if (work == NULL || !work->pending) {
7166 spin_unlock_irqrestore(&dev->event_lock, flags);
7167 return;
7168 }
7169
7170 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7171
7172 if (work->event) {
7173 e = work->event;
49b14a5c 7174 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7175
7176 /* Called before vblank count and timestamps have
7177 * been updated for the vblank interval of flip
7178 * completion? Need to increment vblank count and
7179 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7180 * to account for this. We assume this happened if we
7181 * get called over 0.9 frame durations after the last
7182 * timestamped vblank.
7183 *
7184 * This calculation can not be used with vrefresh rates
7185 * below 5Hz (10Hz to be on the safe side) without
7186 * promoting to 64 integers.
0af7e4df 7187 */
49b14a5c
MK		 7188 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7189 9 * crtc->framedur_ns) {
0af7e4df 7190 e->event.sequence++;
49b14a5c
MK		 7191 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7192 crtc->framedur_ns);
0af7e4df
MK		 7193 }
7194
49b14a5c
MK		 7195 e->event.tv_sec = tvbl.tv_sec;
7196 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7197
6b95a207
KH		 7198 list_add_tail(&e->base.link,
7199 &e->base.file_priv->event_list);
7200 wake_up_interruptible(&e->base.file_priv->event_wait);
7201 }
7202
0af7e4df
MK		 7203 drm_vblank_put(dev, intel_crtc->pipe);
7204
6b95a207
KH		 7205 spin_unlock_irqrestore(&dev->event_lock, flags);
7206
05394f39 7207 obj = work->old_fb_obj;
d9e86c0e 7208
e59f2bac 7209 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7210 &obj->pending_flip.counter);
7211 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7212 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7213
6b95a207 7214 schedule_work(&work->work);
e5510fac
JB		 7215
7216 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7217}
7218
1afe3e9d
JB		 7219void intel_finish_page_flip(struct drm_device *dev, int pipe)
7220{
7221 drm_i915_private_t *dev_priv = dev->dev_private;
7222 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7223
49b14a5c 7224 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7225}
7226
7227void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7228{
7229 drm_i915_private_t *dev_priv = dev->dev_private;
7230 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7231
49b14a5c 7232 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7233}
7234
6b95a207
KH		 7235void intel_prepare_page_flip(struct drm_device *dev, int plane)
7236{
7237 drm_i915_private_t *dev_priv = dev->dev_private;
7238 struct intel_crtc *intel_crtc =
7239 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7240 unsigned long flags;
7241
7242 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7243 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7244 if ((++intel_crtc->unpin_work->pending) > 1)
7245 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7246 } else {
7247 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7248 }
6b95a207
KH		 7249 spin_unlock_irqrestore(&dev->event_lock, flags);
7250}
7251
8c9f3aaf
JB		 7252static int intel_gen2_queue_flip(struct drm_device *dev,
7253 struct drm_crtc *crtc,
7254 struct drm_framebuffer *fb,
7255 struct drm_i915_gem_object *obj)
7256{
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7259 unsigned long offset;
7260 u32 flip_mask;
7261 int ret;
7262
7263 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7264 if (ret)
7265 goto out;
7266
7267 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7268 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7269
7270 ret = BEGIN_LP_RING(6);
7271 if (ret)
7272 goto out;
7273
7274 /* Can't queue multiple flips, so wait for the previous
7275 * one to finish before executing the next.
7276 */
7277 if (intel_crtc->plane)
7278 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7279 else
7280 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7281 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7282 OUT_RING(MI_NOOP);
7283 OUT_RING(MI_DISPLAY_FLIP |
7284 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7285 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7286 OUT_RING(obj->gtt_offset + offset);
7287 OUT_RING(MI_NOOP);
7288 ADVANCE_LP_RING();
7289out:
7290 return ret;
7291}
7292
7293static int intel_gen3_queue_flip(struct drm_device *dev,
7294 struct drm_crtc *crtc,
7295 struct drm_framebuffer *fb,
7296 struct drm_i915_gem_object *obj)
7297{
7298 struct drm_i915_private *dev_priv = dev->dev_private;
7299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7300 unsigned long offset;
7301 u32 flip_mask;
7302 int ret;
7303
7304 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7305 if (ret)
7306 goto out;
7307
7308 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7309 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7310
7311 ret = BEGIN_LP_RING(6);
7312 if (ret)
7313 goto out;
7314
7315 if (intel_crtc->plane)
7316 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7317 else
7318 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7319 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7320 OUT_RING(MI_NOOP);
7321 OUT_RING(MI_DISPLAY_FLIP_I915 |
7322 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7323 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7324 OUT_RING(obj->gtt_offset + offset);
7325 OUT_RING(MI_NOOP);
7326
7327 ADVANCE_LP_RING();
7328out:
7329 return ret;
7330}
7331
7332static int intel_gen4_queue_flip(struct drm_device *dev,
7333 struct drm_crtc *crtc,
7334 struct drm_framebuffer *fb,
7335 struct drm_i915_gem_object *obj)
7336{
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7339 uint32_t pf, pipesrc;
7340 int ret;
7341
7342 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7343 if (ret)
7344 goto out;
7345
7346 ret = BEGIN_LP_RING(4);
7347 if (ret)
7348 goto out;
7349
7350 /* i965+ uses the linear or tiled offsets from the
7351 * Display Registers (which do not change across a page-flip)
7352 * so we need only reprogram the base address.
7353 */
7354 OUT_RING(MI_DISPLAY_FLIP |
7355 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7356 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7357 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7358
7359 /* XXX Enabling the panel-fitter across page-flip is so far
7360 * untested on non-native modes, so ignore it for now.
7361 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7362 */
7363 pf = 0;
7364 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7365 OUT_RING(pf | pipesrc);
7366 ADVANCE_LP_RING();
7367out:
7368 return ret;
7369}
7370
7371static int intel_gen6_queue_flip(struct drm_device *dev,
7372 struct drm_crtc *crtc,
7373 struct drm_framebuffer *fb,
7374 struct drm_i915_gem_object *obj)
7375{
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7378 uint32_t pf, pipesrc;
7379 int ret;
7380
7381 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7382 if (ret)
7383 goto out;
7384
7385 ret = BEGIN_LP_RING(4);
7386 if (ret)
7387 goto out;
7388
7389 OUT_RING(MI_DISPLAY_FLIP |
7390 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7391 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7392 OUT_RING(obj->gtt_offset);
7393
7394 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7396 OUT_RING(pf | pipesrc);
7397 ADVANCE_LP_RING();
7398out:
7399 return ret;
7400}
7401
7c9017e5
JB		 7402/*
7403 * On gen7 we currently use the blit ring because (in early silicon at least)
7404 * the render ring doesn't give us interrpts for page flip completion, which
7405 * means clients will hang after the first flip is queued. Fortunately the
7406 * blit ring generates interrupts properly, so use it instead.
7407 */
7408static int intel_gen7_queue_flip(struct drm_device *dev,
7409 struct drm_crtc *crtc,
7410 struct drm_framebuffer *fb,
7411 struct drm_i915_gem_object *obj)
7412{
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7416 int ret;
7417
7418 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7419 if (ret)
7420 goto out;
7421
7422 ret = intel_ring_begin(ring, 4);
7423 if (ret)
7424 goto out;
7425
7426 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7427 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7428 intel_ring_emit(ring, (obj->gtt_offset));
7429 intel_ring_emit(ring, (MI_NOOP));
7430 intel_ring_advance(ring);
7431out:
7432 return ret;
7433}
7434
8c9f3aaf
JB		 7435static int intel_default_queue_flip(struct drm_device *dev,
7436 struct drm_crtc *crtc,
7437 struct drm_framebuffer *fb,
7438 struct drm_i915_gem_object *obj)
7439{
7440 return -ENODEV;
7441}
7442
6b95a207
KH		 7443static int intel_crtc_page_flip(struct drm_crtc *crtc,
7444 struct drm_framebuffer *fb,
7445 struct drm_pending_vblank_event *event)
7446{
7447 struct drm_device *dev = crtc->dev;
7448 struct drm_i915_private *dev_priv = dev->dev_private;
7449 struct intel_framebuffer *intel_fb;
05394f39 7450 struct drm_i915_gem_object *obj;
6b95a207
KH		 7451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7452 struct intel_unpin_work *work;
8c9f3aaf 7453 unsigned long flags;
52e68630 7454 int ret;
6b95a207
KH		 7455
7456 work = kzalloc(sizeof *work, GFP_KERNEL);
7457 if (work == NULL)
7458 return -ENOMEM;
7459
6b95a207
KH		 7460 work->event = event;
7461 work->dev = crtc->dev;
7462 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7463 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7464 INIT_WORK(&work->work, intel_unpin_work_fn);
7465
7317c75e
JB		 7466 ret = drm_vblank_get(dev, intel_crtc->pipe);
7467 if (ret)
7468 goto free_work;
7469
6b95a207
KH		 7470 /* We borrow the event spin lock for protecting unpin_work */
7471 spin_lock_irqsave(&dev->event_lock, flags);
7472 if (intel_crtc->unpin_work) {
7473 spin_unlock_irqrestore(&dev->event_lock, flags);
7474 kfree(work);
7317c75e 7475 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7476
7477 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7478 return -EBUSY;
7479 }
7480 intel_crtc->unpin_work = work;
7481 spin_unlock_irqrestore(&dev->event_lock, flags);
7482
7483 intel_fb = to_intel_framebuffer(fb);
7484 obj = intel_fb->obj;
7485
468f0b44 7486 mutex_lock(&dev->struct_mutex);
6b95a207 7487
75dfca80 7488 /* Reference the objects for the scheduled work. */
05394f39
CW		 7489 drm_gem_object_reference(&work->old_fb_obj->base);
7490 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7491
7492 crtc->fb = fb;
96b099fd 7493
e1f99ce6 7494 work->pending_flip_obj = obj;
e1f99ce6 7495
4e5359cd
SF		 7496 work->enable_stall_check = true;
7497
e1f99ce6
CW		 7498 /* Block clients from rendering to the new back buffer until
7499 * the flip occurs and the object is no longer visible.
7500 */
05394f39 7501 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7502
8c9f3aaf
JB		 7503 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7504 if (ret)
7505 goto cleanup_pending;
6b95a207 7506
7782de3b 7507 intel_disable_fbc(dev);
6b95a207
KH		 7508 mutex_unlock(&dev->struct_mutex);
7509
e5510fac
JB		 7510 trace_i915_flip_request(intel_crtc->plane, obj);
7511
6b95a207 7512 return 0;
96b099fd 7513
8c9f3aaf
JB		 7514cleanup_pending:
7515 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7516 drm_gem_object_unreference(&work->old_fb_obj->base);
7517 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7518 mutex_unlock(&dev->struct_mutex);
7519
7520 spin_lock_irqsave(&dev->event_lock, flags);
7521 intel_crtc->unpin_work = NULL;
7522 spin_unlock_irqrestore(&dev->event_lock, flags);
7523
7317c75e
JB		 7524 drm_vblank_put(dev, intel_crtc->pipe);
7525free_work:
96b099fd
CW		 7526 kfree(work);
7527
7528 return ret;
6b95a207
KH		 7529}
7530
47f1c6c9
CW		 7531static void intel_sanitize_modesetting(struct drm_device *dev,
7532 int pipe, int plane)
7533{
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 u32 reg, val;
7536
7537 if (HAS_PCH_SPLIT(dev))
7538 return;
7539
7540 /* Who knows what state these registers were left in by the BIOS or
7541 * grub?
7542 *
7543 * If we leave the registers in a conflicting state (e.g. with the
7544 * display plane reading from the other pipe than the one we intend
7545 * to use) then when we attempt to teardown the active mode, we will
7546 * not disable the pipes and planes in the correct order -- leaving
7547 * a plane reading from a disabled pipe and possibly leading to
7548 * undefined behaviour.
7549 */
7550
7551 reg = DSPCNTR(plane);
7552 val = I915_READ(reg);
7553
7554 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7555 return;
7556 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7557 return;
7558
7559 /* This display plane is active and attached to the other CPU pipe. */
7560 pipe = !pipe;
7561
7562 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7563 intel_disable_plane(dev_priv, plane, pipe);
7564 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7565}
79e53945 7566
f6e5b160
CW		 7567static void intel_crtc_reset(struct drm_crtc *crtc)
7568{
7569 struct drm_device *dev = crtc->dev;
7570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7571
7572 /* Reset flags back to the 'unknown' status so that they
7573 * will be correctly set on the initial modeset.
7574 */
7575 intel_crtc->dpms_mode = -1;
7576
7577 /* We need to fix up any BIOS configuration that conflicts with
7578 * our expectations.
7579 */
7580 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7581}
7582
7583static struct drm_crtc_helper_funcs intel_helper_funcs = {
7584 .dpms = intel_crtc_dpms,
7585 .mode_fixup = intel_crtc_mode_fixup,
7586 .mode_set = intel_crtc_mode_set,
7587 .mode_set_base = intel_pipe_set_base,
7588 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7589 .load_lut = intel_crtc_load_lut,
7590 .disable = intel_crtc_disable,
7591};
7592
7593static const struct drm_crtc_funcs intel_crtc_funcs = {
7594 .reset = intel_crtc_reset,
7595 .cursor_set = intel_crtc_cursor_set,
7596 .cursor_move = intel_crtc_cursor_move,
7597 .gamma_set = intel_crtc_gamma_set,
7598 .set_config = drm_crtc_helper_set_config,
7599 .destroy = intel_crtc_destroy,
7600 .page_flip = intel_crtc_page_flip,
7601};
7602
b358d0a6 7603static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7604{
22fd0fab 7605 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7606 struct intel_crtc *intel_crtc;
7607 int i;
7608
7609 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7610 if (intel_crtc == NULL)
7611 return;
7612
7613 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7614
7615 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7616 for (i = 0; i < 256; i++) {
7617 intel_crtc->lut_r[i] = i;
7618 intel_crtc->lut_g[i] = i;
7619 intel_crtc->lut_b[i] = i;
7620 }
7621
80824003
JB		 7622 /* Swap pipes & planes for FBC on pre-965 */
7623 intel_crtc->pipe = pipe;
7624 intel_crtc->plane = pipe;
e2e767ab 7625 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7626 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7627 intel_crtc->plane = !pipe;
80824003
JB		 7628 }
7629
22fd0fab
JB		 7630 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7631 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7632 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7633 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7634
5d1d0cc8 7635 intel_crtc_reset(&intel_crtc->base);
04dbff52 7636 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7637 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7638
7639 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7640 if (pipe == 2 && IS_IVYBRIDGE(dev))
7641 intel_crtc->no_pll = true;
7e7d76c3
JB		 7642 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7643 intel_helper_funcs.commit = ironlake_crtc_commit;
7644 } else {
7645 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7646 intel_helper_funcs.commit = i9xx_crtc_commit;
7647 }
7648
79e53945
JB		 7649 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7650
652c393a
JB		 7651 intel_crtc->busy = false;
7652
7653 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7654 (unsigned long)intel_crtc);
79e53945
JB		 7655}
7656
08d7b3d1 7657int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7658 struct drm_file *file)
08d7b3d1
CW		 7659{
7660 drm_i915_private_t *dev_priv = dev->dev_private;
7661 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7662 struct drm_mode_object *drmmode_obj;
7663 struct intel_crtc *crtc;
08d7b3d1
CW		 7664
7665 if (!dev_priv) {
7666 DRM_ERROR("called with no initialization\n");
7667 return -EINVAL;
7668 }
7669
c05422d5
DV		 7670 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7671 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7672
c05422d5 7673 if (!drmmode_obj) {
08d7b3d1
CW		 7674 DRM_ERROR("no such CRTC id\n");
7675 return -EINVAL;
7676 }
7677
c05422d5
DV		 7678 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7679 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7680
c05422d5 7681 return 0;
08d7b3d1
CW		 7682}
7683
c5e4df33 7684static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7685{
4ef69c7a 7686 struct intel_encoder *encoder;
79e53945 7687 int index_mask = 0;
79e53945
JB		 7688 int entry = 0;
7689
4ef69c7a
CW		 7690 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7691 if (type_mask & encoder->clone_mask)
79e53945
JB		 7692 index_mask |= (1 << entry);
7693 entry++;
7694 }
4ef69c7a 7695
79e53945
JB		 7696 return index_mask;
7697}
7698
4d302442
CW		 7699static bool has_edp_a(struct drm_device *dev)
7700{
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702
7703 if (!IS_MOBILE(dev))
7704 return false;
7705
7706 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7707 return false;
7708
7709 if (IS_GEN5(dev) &&
7710 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7711 return false;
7712
7713 return true;
7714}
7715
79e53945
JB		 7716static void intel_setup_outputs(struct drm_device *dev)
7717{
725e30ad 7718 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7719 struct intel_encoder *encoder;
cb0953d7 7720 bool dpd_is_edp = false;
c5d1b51d 7721 bool has_lvds = false;
79e53945 7722
541998a1 7723 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7724 has_lvds = intel_lvds_init(dev);
7725 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7726 /* disable the panel fitter on everything but LVDS */
7727 I915_WRITE(PFIT_CONTROL, 0);
7728 }
79e53945 7729
bad720ff 7730 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7731 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7732
4d302442 7733 if (has_edp_a(dev))
32f9d658
ZW		 7734 intel_dp_init(dev, DP_A);
7735
cb0953d7
AJ		 7736 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7737 intel_dp_init(dev, PCH_DP_D);
7738 }
7739
7740 intel_crt_init(dev);
7741
7742 if (HAS_PCH_SPLIT(dev)) {
7743 int found;
7744
30ad48b7 7745 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7746 /* PCH SDVOB multiplex with HDMIB */
7747 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7748 if (!found)
7749 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7750 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7751 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7752 }
7753
7754 if (I915_READ(HDMIC) & PORT_DETECTED)
7755 intel_hdmi_init(dev, HDMIC);
7756
7757 if (I915_READ(HDMID) & PORT_DETECTED)
7758 intel_hdmi_init(dev, HDMID);
7759
5eb08b69
ZW		 7760 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7761 intel_dp_init(dev, PCH_DP_C);
7762
cb0953d7 7763 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7764 intel_dp_init(dev, PCH_DP_D);
7765
103a196f 7766 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7767 bool found = false;
7d57382e 7768
725e30ad 7769 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7770 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7771 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7772 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7773 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7774 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7775 }
27185ae1 7776
b01f2c3a
JB		 7777 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7778 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7779 intel_dp_init(dev, DP_B);
b01f2c3a 7780 }
725e30ad 7781 }
13520b05
KH		 7782
7783 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7784
b01f2c3a
JB		 7785 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7786 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7787 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7788 }
27185ae1
ML		 7789
7790 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7791
b01f2c3a
JB		 7792 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7793 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7794 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7795 }
7796 if (SUPPORTS_INTEGRATED_DP(dev)) {
7797 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7798 intel_dp_init(dev, DP_C);
b01f2c3a 7799 }
725e30ad 7800 }
27185ae1 7801
b01f2c3a
JB		 7802 if (SUPPORTS_INTEGRATED_DP(dev) &&
7803 (I915_READ(DP_D) & DP_DETECTED)) {
7804 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7805 intel_dp_init(dev, DP_D);
b01f2c3a 7806 }
bad720ff 7807 } else if (IS_GEN2(dev))
79e53945
JB		 7808 intel_dvo_init(dev);
7809
103a196f 7810 if (SUPPORTS_TV(dev))
79e53945
JB		 7811 intel_tv_init(dev);
7812
4ef69c7a
CW		 7813 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7814 encoder->base.possible_crtcs = encoder->crtc_mask;
7815 encoder->base.possible_clones =
7816 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7817 }
47356eb6 7818
2c7111db
CW		 7819 /* disable all the possible outputs/crtcs before entering KMS mode */
7820 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7821
7822 if (HAS_PCH_SPLIT(dev))
7823 ironlake_init_pch_refclk(dev);
79e53945
JB		 7824}
7825
7826static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7827{
7828 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7829
7830 drm_framebuffer_cleanup(fb);
05394f39 7831 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7832
7833 kfree(intel_fb);
7834}
7835
7836static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7837 struct drm_file *file,
79e53945
JB		 7838 unsigned int *handle)
7839{
7840 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7841 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7842
05394f39 7843 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7844}
7845
7846static const struct drm_framebuffer_funcs intel_fb_funcs = {
7847 .destroy = intel_user_framebuffer_destroy,
7848 .create_handle = intel_user_framebuffer_create_handle,
7849};
7850
38651674
DA		 7851int intel_framebuffer_init(struct drm_device *dev,
7852 struct intel_framebuffer *intel_fb,
308e5bcb 7853 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7854 struct drm_i915_gem_object *obj)
79e53945 7855{
79e53945
JB		 7856 int ret;
7857
05394f39 7858 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7859 return -EINVAL;
7860
308e5bcb 7861 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7862 return -EINVAL;
7863
308e5bcb 7864 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7865 case DRM_FORMAT_RGB332:
7866 case DRM_FORMAT_RGB565:
7867 case DRM_FORMAT_XRGB8888:
7868 case DRM_FORMAT_ARGB8888:
7869 case DRM_FORMAT_XRGB2101010:
7870 case DRM_FORMAT_ARGB2101010:
308e5bcb 7871 /* RGB formats are common across chipsets */
b5626747 7872 break;
04b3924d
VS		 7873 case DRM_FORMAT_YUYV:
7874 case DRM_FORMAT_UYVY:
7875 case DRM_FORMAT_YVYU:
7876 case DRM_FORMAT_VYUY:
57cd6508
CW		 7877 break;
7878 default:
308e5bcb 7879 DRM_ERROR("unsupported pixel format\n");
57cd6508
CW		 7880 return -EINVAL;
7881 }
7882
79e53945
JB		 7883 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7884 if (ret) {
7885 DRM_ERROR("framebuffer init failed %d\n", ret);
7886 return ret;
7887 }
7888
7889 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7890 intel_fb->obj = obj;
79e53945
JB		 7891 return 0;
7892}
7893
79e53945
JB		 7894static struct drm_framebuffer *
7895intel_user_framebuffer_create(struct drm_device *dev,
7896 struct drm_file *filp,
308e5bcb 7897 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7898{
05394f39 7899 struct drm_i915_gem_object *obj;
79e53945 7900
308e5bcb
JB		 7901 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7902 mode_cmd->handles[0]));
c8725226 7903 if (&obj->base == NULL)
cce13ff7 7904 return ERR_PTR(-ENOENT);
79e53945 7905
d2dff872 7906 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7907}
7908
79e53945 7909static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7910 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7911 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7912};
7913
05394f39 7914static struct drm_i915_gem_object *
aa40d6bb 7915intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7916{
05394f39 7917 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7918 int ret;
7919
2c34b850
BW		 7920 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7921
aa40d6bb
ZN		 7922 ctx = i915_gem_alloc_object(dev, 4096);
7923 if (!ctx) {
9ea8d059
CW		 7924 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7925 return NULL;
7926 }
7927
75e9e915 7928 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7929 if (ret) {
7930 DRM_ERROR("failed to pin power context: %d\n", ret);
7931 goto err_unref;
7932 }
7933
aa40d6bb 7934 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7935 if (ret) {
7936 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7937 goto err_unpin;
7938 }
9ea8d059 7939
aa40d6bb 7940 return ctx;
9ea8d059
CW		 7941
7942err_unpin:
aa40d6bb 7943 i915_gem_object_unpin(ctx);
9ea8d059 7944err_unref:
05394f39 7945 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7946 mutex_unlock(&dev->struct_mutex);
7947 return NULL;
7948}
7949
7648fa99
JB		 7950bool ironlake_set_drps(struct drm_device *dev, u8 val)
7951{
7952 struct drm_i915_private *dev_priv = dev->dev_private;
7953 u16 rgvswctl;
7954
7955 rgvswctl = I915_READ16(MEMSWCTL);
7956 if (rgvswctl & MEMCTL_CMD_STS) {
7957 DRM_DEBUG("gpu busy, RCS change rejected\n");
7958 return false; /* still busy with another command */
7959 }
7960
7961 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7962 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7963 I915_WRITE16(MEMSWCTL, rgvswctl);
7964 POSTING_READ16(MEMSWCTL);
7965
7966 rgvswctl |= MEMCTL_CMD_STS;
7967 I915_WRITE16(MEMSWCTL, rgvswctl);
7968
7969 return true;
7970}
7971
f97108d1
JB		 7972void ironlake_enable_drps(struct drm_device *dev)
7973{
7974 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7975 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7976 u8 fmax, fmin, fstart, vstart;
f97108d1 7977
ea056c14
JB		 7978 /* Enable temp reporting */
7979 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7980 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7981
f97108d1
JB		 7982 /* 100ms RC evaluation intervals */
7983 I915_WRITE(RCUPEI, 100000);
7984 I915_WRITE(RCDNEI, 100000);
7985
7986 /* Set max/min thresholds to 90ms and 80ms respectively */
7987 I915_WRITE(RCBMAXAVG, 90000);
7988 I915_WRITE(RCBMINAVG, 80000);
7989
7990 I915_WRITE(MEMIHYST, 1);
7991
7992 /* Set up min, max, and cur for interrupt handling */
7993 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7994 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7995 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7996 MEMMODE_FSTART_SHIFT;
7648fa99 7997
f97108d1
JB		 7998 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7999 PXVFREQ_PX_SHIFT;
8000
80dbf4b7 8001 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8002 dev_priv->fstart = fstart;
8003
80dbf4b7 8004 dev_priv->max_delay = fstart;
f97108d1
JB		 8005 dev_priv->min_delay = fmin;
8006 dev_priv->cur_delay = fstart;
8007
80dbf4b7
JB		 8008 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8009 fmax, fmin, fstart);
7648fa99 8010
f97108d1
JB		 8011 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8012
8013 /*
8014 * Interrupts will be enabled in ironlake_irq_postinstall
8015 */
8016
8017 I915_WRITE(VIDSTART, vstart);
8018 POSTING_READ(VIDSTART);
8019
8020 rgvmodectl |= MEMMODE_SWMODE_EN;
8021 I915_WRITE(MEMMODECTL, rgvmodectl);
8022
481b6af3 8023 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8024 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8025 msleep(1);
8026
7648fa99 8027 ironlake_set_drps(dev, fstart);
f97108d1 8028
7648fa99
JB		 8029 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8030 I915_READ(0x112e0);
8031 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8032 dev_priv->last_count2 = I915_READ(0x112f4);
8033 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8034}
8035
8036void ironlake_disable_drps(struct drm_device *dev)
8037{
8038 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8039 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8040
8041 /* Ack interrupts, disable EFC interrupt */
8042 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8043 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8044 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8045 I915_WRITE(DEIIR, DE_PCU_EVENT);
8046 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8047
8048 /* Go back to the starting frequency */
7648fa99 8049 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8050 msleep(1);
8051 rgvswctl |= MEMCTL_CMD_STS;
8052 I915_WRITE(MEMSWCTL, rgvswctl);
8053 msleep(1);
8054
8055}
8056
3b8d8d91
JB		 8057void gen6_set_rps(struct drm_device *dev, u8 val)
8058{
8059 struct drm_i915_private *dev_priv = dev->dev_private;
8060 u32 swreq;
8061
8062 swreq = (val & 0x3ff) << 25;
8063 I915_WRITE(GEN6_RPNSWREQ, swreq);
8064}
8065
8066void gen6_disable_rps(struct drm_device *dev)
8067{
8068 struct drm_i915_private *dev_priv = dev->dev_private;
8069
8070 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8071 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8072 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8073 /* Complete PM interrupt masking here doesn't race with the rps work
8074 * item again unmasking PM interrupts because that is using a different
8075 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8076 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8077
8078 spin_lock_irq(&dev_priv->rps_lock);
8079 dev_priv->pm_iir = 0;
8080 spin_unlock_irq(&dev_priv->rps_lock);
8081
3b8d8d91
JB		 8082 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8083}
8084
7648fa99
JB		 8085static unsigned long intel_pxfreq(u32 vidfreq)
8086{
8087 unsigned long freq;
8088 int div = (vidfreq & 0x3f0000) >> 16;
8089 int post = (vidfreq & 0x3000) >> 12;
8090 int pre = (vidfreq & 0x7);
8091
8092 if (!pre)
8093 return 0;
8094
8095 freq = ((div * 133333) / ((1<<post) * pre));
8096
8097 return freq;
8098}
8099
8100void intel_init_emon(struct drm_device *dev)
8101{
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 u32 lcfuse;
8104 u8 pxw[16];
8105 int i;
8106
8107 /* Disable to program */
8108 I915_WRITE(ECR, 0);
8109 POSTING_READ(ECR);
8110
8111 /* Program energy weights for various events */
8112 I915_WRITE(SDEW, 0x15040d00);
8113 I915_WRITE(CSIEW0, 0x007f0000);
8114 I915_WRITE(CSIEW1, 0x1e220004);
8115 I915_WRITE(CSIEW2, 0x04000004);
8116
8117 for (i = 0; i < 5; i++)
8118 I915_WRITE(PEW + (i * 4), 0);
8119 for (i = 0; i < 3; i++)
8120 I915_WRITE(DEW + (i * 4), 0);
8121
8122 /* Program P-state weights to account for frequency power adjustment */
8123 for (i = 0; i < 16; i++) {
8124 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8125 unsigned long freq = intel_pxfreq(pxvidfreq);
8126 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8127 PXVFREQ_PX_SHIFT;
8128 unsigned long val;
8129
8130 val = vid * vid;
8131 val *= (freq / 1000);
8132 val *= 255;
8133 val /= (127*127*900);
8134 if (val > 0xff)
8135 DRM_ERROR("bad pxval: %ld\n", val);
8136 pxw[i] = val;
8137 }
8138 /* Render standby states get 0 weight */
8139 pxw[14] = 0;
8140 pxw[15] = 0;
8141
8142 for (i = 0; i < 4; i++) {
8143 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8144 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8145 I915_WRITE(PXW + (i * 4), val);
8146 }
8147
8148 /* Adjust magic regs to magic values (more experimental results) */
8149 I915_WRITE(OGW0, 0);
8150 I915_WRITE(OGW1, 0);
8151 I915_WRITE(EG0, 0x00007f00);
8152 I915_WRITE(EG1, 0x0000000e);
8153 I915_WRITE(EG2, 0x000e0000);
8154 I915_WRITE(EG3, 0x68000300);
8155 I915_WRITE(EG4, 0x42000000);
8156 I915_WRITE(EG5, 0x00140031);
8157 I915_WRITE(EG6, 0);
8158 I915_WRITE(EG7, 0);
8159
8160 for (i = 0; i < 8; i++)
8161 I915_WRITE(PXWL + (i * 4), 0);
8162
8163 /* Enable PMON + select events */
8164 I915_WRITE(ECR, 0x80000019);
8165
8166 lcfuse = I915_READ(LCFUSE02);
8167
8168 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8169}
8170
c0f372b3
KP		 8171static bool intel_enable_rc6(struct drm_device *dev)
8172{
8173 /*
8174 * Respect the kernel parameter if it is set
8175 */
8176 if (i915_enable_rc6 >= 0)
8177 return i915_enable_rc6;
8178
8179 /*
8180 * Disable RC6 on Ironlake
8181 */
8182 if (INTEL_INFO(dev)->gen == 5)
8183 return 0;
8184
8185 /*
8186 * Enable rc6 on Sandybridge if DMA remapping is disabled
8187 */
8188 if (INTEL_INFO(dev)->gen == 6) {
8189 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8190 intel_iommu_enabled ? "true" : "false",
8191 !intel_iommu_enabled ? "en" : "dis");
8192 return !intel_iommu_enabled;
8193 }
8194 DRM_DEBUG_DRIVER("RC6 enabled\n");
8195 return 1;
8196}
8197
3b8d8d91 8198void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8199{
a6044e23
JB		 8200 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8201 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8202 u32 pcu_mbox, rc6_mask = 0;
a6044e23 8203 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8204 int i;
8205
8206 /* Here begins a magic sequence of register writes to enable
8207 * auto-downclocking.
8208 *
8209 * Perhaps there might be some value in exposing these to
8210 * userspace...
8211 */
8212 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8213 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 8214 gen6_gt_force_wake_get(dev_priv);
8fd26859 8215
3b8d8d91 8216 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8217 I915_WRITE(GEN6_RC_CONTROL, 0);
8218
8219 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8220 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8221 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8222 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8223 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8224
8225 for (i = 0; i < I915_NUM_RINGS; i++)
8226 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8227
8228 I915_WRITE(GEN6_RC_SLEEP, 0);
8229 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8230 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8231 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8232 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8233
c0f372b3 8234 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8235 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8236 GEN6_RC_CTL_RC6_ENABLE;
8237
8fd26859 8238 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8239 rc6_mask |
9c3d2f7f 8240 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8241 GEN6_RC_CTL_HW_ENABLE);
8242
3b8d8d91 8243 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8244 GEN6_FREQUENCY(10) |
8245 GEN6_OFFSET(0) |
8246 GEN6_AGGRESSIVE_TURBO);
8247 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8248 GEN6_FREQUENCY(12));
8249
8250 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8251 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8252 18 << 24 |
8253 6 << 16);
ccab5c82
JB		 8254 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8255 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8256 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8257 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8258 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8259 I915_WRITE(GEN6_RP_CONTROL,
8260 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8261 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8262 GEN6_RP_MEDIA_IS_GFX |
8263 GEN6_RP_ENABLE |
ccab5c82
JB		 8264 GEN6_RP_UP_BUSY_AVG |
8265 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8266
8267 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8268 500))
8269 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8270
8271 I915_WRITE(GEN6_PCODE_DATA, 0);
8272 I915_WRITE(GEN6_PCODE_MAILBOX,
8273 GEN6_PCODE_READY |
8274 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8275 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8276 500))
8277 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8278
a6044e23
JB		 8279 min_freq = (rp_state_cap & 0xff0000) >> 16;
8280 max_freq = rp_state_cap & 0xff;
8281 cur_freq = (gt_perf_status & 0xff00) >> 8;
8282
8283 /* Check for overclock support */
8284 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8285 500))
8286 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8287 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8288 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8289 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8290 500))
8291 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8292 if (pcu_mbox & (1<<31)) { /* OC supported */
8293 max_freq = pcu_mbox & 0xff;
e281fcaa 8294 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8295 }
8296
8297 /* In units of 100MHz */
8298 dev_priv->max_delay = max_freq;
8299 dev_priv->min_delay = min_freq;
8300 dev_priv->cur_delay = cur_freq;
8301
8fd26859
CW		 8302 /* requires MSI enabled */
8303 I915_WRITE(GEN6_PMIER,
8304 GEN6_PM_MBOX_EVENT |
8305 GEN6_PM_THERMAL_EVENT |
8306 GEN6_PM_RP_DOWN_TIMEOUT |
8307 GEN6_PM_RP_UP_THRESHOLD |
8308 GEN6_PM_RP_DOWN_THRESHOLD |
8309 GEN6_PM_RP_UP_EI_EXPIRED |
8310 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8311 spin_lock_irq(&dev_priv->rps_lock);
8312 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8313 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8314 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8315 /* enable all PM interrupts */
8316 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8317
fcca7926 8318 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8319 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8320}
8321
23b2f8bb
JB		 8322void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8323{
8324 int min_freq = 15;
8325 int gpu_freq, ia_freq, max_ia_freq;
8326 int scaling_factor = 180;
8327
8328 max_ia_freq = cpufreq_quick_get_max(0);
8329 /*
8330 * Default to measured freq if none found, PCU will ensure we don't go
8331 * over
8332 */
8333 if (!max_ia_freq)
8334 max_ia_freq = tsc_khz;
8335
8336 /* Convert from kHz to MHz */
8337 max_ia_freq /= 1000;
8338
8339 mutex_lock(&dev_priv->dev->struct_mutex);
8340
8341 /*
8342 * For each potential GPU frequency, load a ring frequency we'd like
8343 * to use for memory access. We do this by specifying the IA frequency
8344 * the PCU should use as a reference to determine the ring frequency.
8345 */
8346 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8347 gpu_freq--) {
8348 int diff = dev_priv->max_delay - gpu_freq;
8349
8350 /*
8351 * For GPU frequencies less than 750MHz, just use the lowest
8352 * ring freq.
8353 */
8354 if (gpu_freq < min_freq)
8355 ia_freq = 800;
8356 else
8357 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8358 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8359
8360 I915_WRITE(GEN6_PCODE_DATA,
8361 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8362 gpu_freq);
8363 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8364 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8365 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8366 GEN6_PCODE_READY) == 0, 10)) {
8367 DRM_ERROR("pcode write of freq table timed out\n");
8368 continue;
8369 }
8370 }
8371
8372 mutex_unlock(&dev_priv->dev->struct_mutex);
8373}
8374
6067aaea
JB		 8375static void ironlake_init_clock_gating(struct drm_device *dev)
8376{
8377 struct drm_i915_private *dev_priv = dev->dev_private;
8378 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8379
8380 /* Required for FBC */
8381 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8382 DPFCRUNIT_CLOCK_GATE_DISABLE |
8383 DPFDUNIT_CLOCK_GATE_DISABLE;
8384 /* Required for CxSR */
8385 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8386
8387 I915_WRITE(PCH_3DCGDIS0,
8388 MARIUNIT_CLOCK_GATE_DISABLE |
8389 SVSMUNIT_CLOCK_GATE_DISABLE);
8390 I915_WRITE(PCH_3DCGDIS1,
8391 VFMUNIT_CLOCK_GATE_DISABLE);
8392
8393 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8394
6067aaea
JB		 8395 /*
8396 * According to the spec the following bits should be set in
8397 * order to enable memory self-refresh
8398 * The bit 22/21 of 0x42004
8399 * The bit 5 of 0x42020
8400 * The bit 15 of 0x45000
8401 */
8402 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8403 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8404 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8405 I915_WRITE(ILK_DSPCLK_GATE,
8406 (I915_READ(ILK_DSPCLK_GATE) |
8407 ILK_DPARB_CLK_GATE));
8408 I915_WRITE(DISP_ARB_CTL,
8409 (I915_READ(DISP_ARB_CTL) |
8410 DISP_FBC_WM_DIS));
8411 I915_WRITE(WM3_LP_ILK, 0);
8412 I915_WRITE(WM2_LP_ILK, 0);
8413 I915_WRITE(WM1_LP_ILK, 0);
8414
8415 /*
8416 * Based on the document from hardware guys the following bits
8417 * should be set unconditionally in order to enable FBC.
8418 * The bit 22 of 0x42000
8419 * The bit 22 of 0x42004
8420 * The bit 7,8,9 of 0x42020.
8421 */
8422 if (IS_IRONLAKE_M(dev)) {
8423 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8424 I915_READ(ILK_DISPLAY_CHICKEN1) |
8425 ILK_FBCQ_DIS);
8426 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8427 I915_READ(ILK_DISPLAY_CHICKEN2) |
8428 ILK_DPARB_GATE);
8429 I915_WRITE(ILK_DSPCLK_GATE,
8430 I915_READ(ILK_DSPCLK_GATE) |
8431 ILK_DPFC_DIS1 |
8432 ILK_DPFC_DIS2 |
8433 ILK_CLK_FBC);
8434 }
8435
8436 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8437 I915_READ(ILK_DISPLAY_CHICKEN2) |
8438 ILK_ELPIN_409_SELECT);
8439 I915_WRITE(_3D_CHICKEN2,
8440 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8441 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8442}
8443
6067aaea 8444static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8445{
8446 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8447 int pipe;
6067aaea
JB		 8448 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8449
8450 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8451
6067aaea
JB		 8452 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8453 I915_READ(ILK_DISPLAY_CHICKEN2) |
8454 ILK_ELPIN_409_SELECT);
8956c8bb 8455
6067aaea
JB		 8456 I915_WRITE(WM3_LP_ILK, 0);
8457 I915_WRITE(WM2_LP_ILK, 0);
8458 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8459
406478dc
EA		 8460 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8461 * gating disable must be set. Failure to set it results in
8462 * flickering pixels due to Z write ordering failures after
8463 * some amount of runtime in the Mesa "fire" demo, and Unigine
8464 * Sanctuary and Tropics, and apparently anything else with
8465 * alpha test or pixel discard.
9ca1d10d
EA		 8466 *
8467 * According to the spec, bit 11 (RCCUNIT) must also be set,
8468 * but we didn't debug actual testcases to find it out.
406478dc 8469 */
9ca1d10d
EA		 8470 I915_WRITE(GEN6_UCGCTL2,
8471 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8472 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8473
652c393a 8474 /*
6067aaea
JB		 8475 * According to the spec the following bits should be
8476 * set in order to enable memory self-refresh and fbc:
8477 * The bit21 and bit22 of 0x42000
8478 * The bit21 and bit22 of 0x42004
8479 * The bit5 and bit7 of 0x42020
8480 * The bit14 of 0x70180
8481 * The bit14 of 0x71180
652c393a 8482 */
6067aaea
JB		 8483 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8484 I915_READ(ILK_DISPLAY_CHICKEN1) |
8485 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8486 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8487 I915_READ(ILK_DISPLAY_CHICKEN2) |
8488 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8489 I915_WRITE(ILK_DSPCLK_GATE,
8490 I915_READ(ILK_DSPCLK_GATE) |
8491 ILK_DPARB_CLK_GATE |
8492 ILK_DPFD_CLK_GATE);
8956c8bb 8493
d74362c9 8494 for_each_pipe(pipe) {
6067aaea
JB		 8495 I915_WRITE(DSPCNTR(pipe),
8496 I915_READ(DSPCNTR(pipe)) |
8497 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8498 intel_flush_display_plane(dev_priv, pipe);
8499 }
6067aaea 8500}
8956c8bb 8501
28963a3e
JB		 8502static void ivybridge_init_clock_gating(struct drm_device *dev)
8503{
8504 struct drm_i915_private *dev_priv = dev->dev_private;
8505 int pipe;
8506 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8507
28963a3e 8508 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8509
28963a3e
JB		 8510 I915_WRITE(WM3_LP_ILK, 0);
8511 I915_WRITE(WM2_LP_ILK, 0);
8512 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8513
28963a3e 8514 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8515
116ac8d2
EA		 8516 I915_WRITE(IVB_CHICKEN3,
8517 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8518 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8519
d74362c9 8520 for_each_pipe(pipe) {
28963a3e
JB		 8521 I915_WRITE(DSPCNTR(pipe),
8522 I915_READ(DSPCNTR(pipe)) |
8523 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8524 intel_flush_display_plane(dev_priv, pipe);
8525 }
28963a3e
JB		 8526}
8527
6067aaea
JB		 8528static void g4x_init_clock_gating(struct drm_device *dev)
8529{
8530 struct drm_i915_private *dev_priv = dev->dev_private;
8531 uint32_t dspclk_gate;
8fd26859 8532
6067aaea
JB		 8533 I915_WRITE(RENCLK_GATE_D1, 0);
8534 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8535 GS_UNIT_CLOCK_GATE_DISABLE |
8536 CL_UNIT_CLOCK_GATE_DISABLE);
8537 I915_WRITE(RAMCLK_GATE_D, 0);
8538 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8539 OVRUNIT_CLOCK_GATE_DISABLE |
8540 OVCUNIT_CLOCK_GATE_DISABLE;
8541 if (IS_GM45(dev))
8542 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8543 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8544}
1398261a 8545
6067aaea
JB		 8546static void crestline_init_clock_gating(struct drm_device *dev)
8547{
8548 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8549
6067aaea
JB		 8550 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8551 I915_WRITE(RENCLK_GATE_D2, 0);
8552 I915_WRITE(DSPCLK_GATE_D, 0);
8553 I915_WRITE(RAMCLK_GATE_D, 0);
8554 I915_WRITE16(DEUC, 0);
8555}
652c393a 8556
6067aaea
JB		 8557static void broadwater_init_clock_gating(struct drm_device *dev)
8558{
8559 struct drm_i915_private *dev_priv = dev->dev_private;
8560
8561 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8562 I965_RCC_CLOCK_GATE_DISABLE |
8563 I965_RCPB_CLOCK_GATE_DISABLE |
8564 I965_ISC_CLOCK_GATE_DISABLE |
8565 I965_FBC_CLOCK_GATE_DISABLE);
8566 I915_WRITE(RENCLK_GATE_D2, 0);
8567}
8568
8569static void gen3_init_clock_gating(struct drm_device *dev)
8570{
8571 struct drm_i915_private *dev_priv = dev->dev_private;
8572 u32 dstate = I915_READ(D_STATE);
8573
8574 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8575 DSTATE_DOT_CLOCK_GATING;
8576 I915_WRITE(D_STATE, dstate);
8577}
8578
8579static void i85x_init_clock_gating(struct drm_device *dev)
8580{
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582
8583 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8584}
8585
8586static void i830_init_clock_gating(struct drm_device *dev)
8587{
8588 struct drm_i915_private *dev_priv = dev->dev_private;
8589
8590 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8591}
8592
645c62a5
JB		 8593static void ibx_init_clock_gating(struct drm_device *dev)
8594{
8595 struct drm_i915_private *dev_priv = dev->dev_private;
8596
8597 /*
8598 * On Ibex Peak and Cougar Point, we need to disable clock
8599 * gating for the panel power sequencer or it will fail to
8600 * start up when no ports are active.
8601 */
8602 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8603}
8604
8605static void cpt_init_clock_gating(struct drm_device *dev)
8606{
8607 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8608 int pipe;
645c62a5
JB		 8609
8610 /*
8611 * On Ibex Peak and Cougar Point, we need to disable clock
8612 * gating for the panel power sequencer or it will fail to
8613 * start up when no ports are active.
8614 */
8615 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8616 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8617 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8618 /* Without this, mode sets may fail silently on FDI */
8619 for_each_pipe(pipe)
8620 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8621}
8622
ac668088 8623static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8624{
8625 struct drm_i915_private *dev_priv = dev->dev_private;
8626
8627 if (dev_priv->renderctx) {
ac668088
CW		 8628 i915_gem_object_unpin(dev_priv->renderctx);
8629 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8630 dev_priv->renderctx = NULL;
8631 }
8632
8633 if (dev_priv->pwrctx) {
ac668088
CW		 8634 i915_gem_object_unpin(dev_priv->pwrctx);
8635 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8636 dev_priv->pwrctx = NULL;
8637 }
8638}
8639
8640static void ironlake_disable_rc6(struct drm_device *dev)
8641{
8642 struct drm_i915_private *dev_priv = dev->dev_private;
8643
8644 if (I915_READ(PWRCTXA)) {
8645 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8646 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8647 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8648 50);
0cdab21f
CW		 8649
8650 I915_WRITE(PWRCTXA, 0);
8651 POSTING_READ(PWRCTXA);
8652
ac668088
CW		 8653 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8654 POSTING_READ(RSTDBYCTL);
0cdab21f 8655 }
ac668088 8656
99507307 8657 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8658}
8659
ac668088 8660static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8661{
8662 struct drm_i915_private *dev_priv = dev->dev_private;
8663
ac668088
CW		 8664 if (dev_priv->renderctx == NULL)
8665 dev_priv->renderctx = intel_alloc_context_page(dev);
8666 if (!dev_priv->renderctx)
8667 return -ENOMEM;
8668
8669 if (dev_priv->pwrctx == NULL)
8670 dev_priv->pwrctx = intel_alloc_context_page(dev);
8671 if (!dev_priv->pwrctx) {
8672 ironlake_teardown_rc6(dev);
8673 return -ENOMEM;
8674 }
8675
8676 return 0;
d5bb081b
JB		 8677}
8678
8679void ironlake_enable_rc6(struct drm_device *dev)
8680{
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682 int ret;
8683
ac668088
CW		 8684 /* rc6 disabled by default due to repeated reports of hanging during
8685 * boot and resume.
8686 */
c0f372b3 8687 if (!intel_enable_rc6(dev))
ac668088
CW		 8688 return;
8689
2c34b850 8690 mutex_lock(&dev->struct_mutex);
ac668088 8691 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8692 if (ret) {
8693 mutex_unlock(&dev->struct_mutex);
ac668088 8694 return;
2c34b850 8695 }
ac668088 8696
d5bb081b
JB		 8697 /*
8698 * GPU can automatically power down the render unit if given a page
8699 * to save state.
8700 */
8701 ret = BEGIN_LP_RING(6);
8702 if (ret) {
ac668088 8703 ironlake_teardown_rc6(dev);
2c34b850 8704 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8705 return;
8706 }
ac668088 8707
d5bb081b
JB		 8708 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8709 OUT_RING(MI_SET_CONTEXT);
8710 OUT_RING(dev_priv->renderctx->gtt_offset |
8711 MI_MM_SPACE_GTT |
8712 MI_SAVE_EXT_STATE_EN |
8713 MI_RESTORE_EXT_STATE_EN |
8714 MI_RESTORE_INHIBIT);
8715 OUT_RING(MI_SUSPEND_FLUSH);
8716 OUT_RING(MI_NOOP);
8717 OUT_RING(MI_FLUSH);
8718 ADVANCE_LP_RING();
8719
4a246cfc
BW		 8720 /*
8721 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8722 * does an implicit flush, combined with MI_FLUSH above, it should be
8723 * safe to assume that renderctx is valid
8724 */
8725 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8726 if (ret) {
8727 DRM_ERROR("failed to enable ironlake power power savings\n");
8728 ironlake_teardown_rc6(dev);
8729 mutex_unlock(&dev->struct_mutex);
8730 return;
8731 }
8732
d5bb081b
JB		 8733 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8734 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8735 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8736}
8737
645c62a5
JB		 8738void intel_init_clock_gating(struct drm_device *dev)
8739{
8740 struct drm_i915_private *dev_priv = dev->dev_private;
8741
8742 dev_priv->display.init_clock_gating(dev);
8743
8744 if (dev_priv->display.init_pch_clock_gating)
8745 dev_priv->display.init_pch_clock_gating(dev);
8746}
ac668088 8747
e70236a8
JB		 8748/* Set up chip specific display functions */
8749static void intel_init_display(struct drm_device *dev)
8750{
8751 struct drm_i915_private *dev_priv = dev->dev_private;
8752
8753 /* We always want a DPMS function */
f564048e 8754 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8755 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8756 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8757 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8758 } else {
e70236a8 8759 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8760 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8761 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8762 }
e70236a8 8763
ee5382ae 8764 if (I915_HAS_FBC(dev)) {
9c04f015 8765 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8766 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8767 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8768 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8769 } else if (IS_GM45(dev)) {
74dff282
JB		 8770 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8771 dev_priv->display.enable_fbc = g4x_enable_fbc;
8772 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8773 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8774 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8775 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8776 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8777 }
74dff282 8778 /* 855GM needs testing */
e70236a8
JB		 8779 }
8780
8781 /* Returns the core display clock speed */
0206e353 8782 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8783 dev_priv->display.get_display_clock_speed =
8784 i945_get_display_clock_speed;
8785 else if (IS_I915G(dev))
8786 dev_priv->display.get_display_clock_speed =
8787 i915_get_display_clock_speed;
f2b115e6 8788 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8789 dev_priv->display.get_display_clock_speed =
8790 i9xx_misc_get_display_clock_speed;
8791 else if (IS_I915GM(dev))
8792 dev_priv->display.get_display_clock_speed =
8793 i915gm_get_display_clock_speed;
8794 else if (IS_I865G(dev))
8795 dev_priv->display.get_display_clock_speed =
8796 i865_get_display_clock_speed;
f0f8a9ce 8797 else if (IS_I85X(dev))
e70236a8
JB		 8798 dev_priv->display.get_display_clock_speed =
8799 i855_get_display_clock_speed;
8800 else /* 852, 830 */
8801 dev_priv->display.get_display_clock_speed =
8802 i830_get_display_clock_speed;
8803
8804 /* For FIFO watermark updates */
7f8a8569 8805 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8806 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8807 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8808
8809 /* IVB configs may use multi-threaded forcewake */
8810 if (IS_IVYBRIDGE(dev)) {
8811 u32 ecobus;
8812
c7dffff7
KP		 8813 /* A small trick here - if the bios hasn't configured MT forcewake,
8814 * and if the device is in RC6, then force_wake_mt_get will not wake
8815 * the device and the ECOBUS read will return zero. Which will be
8816 * (correctly) interpreted by the test below as MT forcewake being
8817 * disabled.
8818 */
8d715f00
KP		 8819 mutex_lock(&dev->struct_mutex);
8820 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8821 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8822 __gen6_gt_force_wake_mt_put(dev_priv);
8823 mutex_unlock(&dev->struct_mutex);
8824
8825 if (ecobus & FORCEWAKE_MT_ENABLE) {
8826 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8827 dev_priv->display.force_wake_get =
8828 __gen6_gt_force_wake_mt_get;
8829 dev_priv->display.force_wake_put =
8830 __gen6_gt_force_wake_mt_put;
8831 }
8832 }
8833
645c62a5
JB		 8834 if (HAS_PCH_IBX(dev))
8835 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8836 else if (HAS_PCH_CPT(dev))
8837 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8838
f00a3ddf 8839 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8840 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8841 dev_priv->display.update_wm = ironlake_update_wm;
8842 else {
8843 DRM_DEBUG_KMS("Failed to get proper latency. "
8844 "Disable CxSR\n");
8845 dev_priv->display.update_wm = NULL;
1398261a 8846 }
674cf967 8847 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8848 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8849 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8850 } else if (IS_GEN6(dev)) {
8851 if (SNB_READ_WM0_LATENCY()) {
8852 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8853 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8854 } else {
8855 DRM_DEBUG_KMS("Failed to read display plane latency. "
8856 "Disable CxSR\n");
8857 dev_priv->display.update_wm = NULL;
7f8a8569 8858 }
674cf967 8859 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8860 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8861 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8862 } else if (IS_IVYBRIDGE(dev)) {
8863 /* FIXME: detect B0+ stepping and use auto training */
8864 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8865 if (SNB_READ_WM0_LATENCY()) {
8866 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8867 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8868 } else {
8869 DRM_DEBUG_KMS("Failed to read display plane latency. "
8870 "Disable CxSR\n");
8871 dev_priv->display.update_wm = NULL;
8872 }
28963a3e 8873 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8874 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8875 } else
8876 dev_priv->display.update_wm = NULL;
8877 } else if (IS_PINEVIEW(dev)) {
d4294342 8878 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8879 dev_priv->is_ddr3,
d4294342
ZY		 8880 dev_priv->fsb_freq,
8881 dev_priv->mem_freq)) {
8882 DRM_INFO("failed to find known CxSR latency "
95534263 8883 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8884 "disabling CxSR\n",
0206e353 8885 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8886 dev_priv->fsb_freq, dev_priv->mem_freq);
8887 /* Disable CxSR and never update its watermark again */
8888 pineview_disable_cxsr(dev);
8889 dev_priv->display.update_wm = NULL;
8890 } else
8891 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8892 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8893 } else if (IS_G4X(dev)) {
e0dac65e 8894 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8895 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8896 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8897 } else if (IS_GEN4(dev)) {
e70236a8 8898 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8899 if (IS_CRESTLINE(dev))
8900 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8901 else if (IS_BROADWATER(dev))
8902 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8903 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8904 dev_priv->display.update_wm = i9xx_update_wm;
8905 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8906 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8907 } else if (IS_I865G(dev)) {
8908 dev_priv->display.update_wm = i830_update_wm;
8909 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8910 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8911 } else if (IS_I85X(dev)) {
8912 dev_priv->display.update_wm = i9xx_update_wm;
8913 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8914 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8915 } else {
8f4695ed 8916 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8917 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8918 if (IS_845G(dev))
e70236a8
JB		 8919 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8920 else
8921 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8922 }
8c9f3aaf
JB		 8923
8924 /* Default just returns -ENODEV to indicate unsupported */
8925 dev_priv->display.queue_flip = intel_default_queue_flip;
8926
8927 switch (INTEL_INFO(dev)->gen) {
8928 case 2:
8929 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8930 break;
8931
8932 case 3:
8933 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8934 break;
8935
8936 case 4:
8937 case 5:
8938 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8939 break;
8940
8941 case 6:
8942 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8943 break;
7c9017e5
JB		 8944 case 7:
8945 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8946 break;
8c9f3aaf 8947 }
e70236a8
JB		 8948}
8949
b690e96c
JB		 8950/*
8951 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8952 * resume, or other times. This quirk makes sure that's the case for
8953 * affected systems.
8954 */
0206e353 8955static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8956{
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958
8959 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8960 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8961}
8962
435793df
KP		 8963/*
8964 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8965 */
8966static void quirk_ssc_force_disable(struct drm_device *dev)
8967{
8968 struct drm_i915_private *dev_priv = dev->dev_private;
8969 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8970}
8971
b690e96c
JB		 8972struct intel_quirk {
8973 int device;
8974 int subsystem_vendor;
8975 int subsystem_device;
8976 void (*hook)(struct drm_device *dev);
8977};
8978
8979struct intel_quirk intel_quirks[] = {
8980 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8981 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8982 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8983 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8984
8985 /* Thinkpad R31 needs pipe A force quirk */
8986 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8987 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8988 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8989
8990 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8991 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8992 /* ThinkPad X40 needs pipe A force quirk */
8993
8994 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8995 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8996
8997 /* 855 & before need to leave pipe A & dpll A up */
8998 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8999 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9000
9001 /* Lenovo U160 cannot use SSC on LVDS */
9002 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9003
9004 /* Sony Vaio Y cannot use SSC on LVDS */
9005 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9006};
9007
9008static void intel_init_quirks(struct drm_device *dev)
9009{
9010 struct pci_dev *d = dev->pdev;
9011 int i;
9012
9013 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9014 struct intel_quirk *q = &intel_quirks[i];
9015
9016 if (d->device == q->device &&
9017 (d->subsystem_vendor == q->subsystem_vendor ||
9018 q->subsystem_vendor == PCI_ANY_ID) &&
9019 (d->subsystem_device == q->subsystem_device ||
9020 q->subsystem_device == PCI_ANY_ID))
9021 q->hook(dev);
9022 }
9023}
9024
9cce37f4
JB		 9025/* Disable the VGA plane that we never use */
9026static void i915_disable_vga(struct drm_device *dev)
9027{
9028 struct drm_i915_private *dev_priv = dev->dev_private;
9029 u8 sr1;
9030 u32 vga_reg;
9031
9032 if (HAS_PCH_SPLIT(dev))
9033 vga_reg = CPU_VGACNTRL;
9034 else
9035 vga_reg = VGACNTRL;
9036
9037 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9038 outb(1, VGA_SR_INDEX);
9039 sr1 = inb(VGA_SR_DATA);
9040 outb(sr1 | 1<<5, VGA_SR_DATA);
9041 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9042 udelay(300);
9043
9044 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9045 POSTING_READ(vga_reg);
9046}
9047
79e53945
JB		 9048void intel_modeset_init(struct drm_device *dev)
9049{
652c393a 9050 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9051 int i, ret;
79e53945
JB		 9052
9053 drm_mode_config_init(dev);
9054
9055 dev->mode_config.min_width = 0;
9056 dev->mode_config.min_height = 0;
9057
9058 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9059
b690e96c
JB		 9060 intel_init_quirks(dev);
9061
e70236a8
JB		 9062 intel_init_display(dev);
9063
a6c45cf0
CW		 9064 if (IS_GEN2(dev)) {
9065 dev->mode_config.max_width = 2048;
9066 dev->mode_config.max_height = 2048;
9067 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9068 dev->mode_config.max_width = 4096;
9069 dev->mode_config.max_height = 4096;
79e53945 9070 } else {
a6c45cf0
CW		 9071 dev->mode_config.max_width = 8192;
9072 dev->mode_config.max_height = 8192;
79e53945 9073 }
35c3047a 9074 dev->mode_config.fb_base = dev->agp->base;
79e53945 9075
28c97730 9076 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9077 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9078
a3524f1b 9079 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9080 intel_crtc_init(dev, i);
b840d907
JB		 9081 if (HAS_PCH_SPLIT(dev)) {
9082 ret = intel_plane_init(dev, i);
9083 if (ret)
9084 DRM_ERROR("plane %d init failed: %d\n",
9085 i, ret);
9086 }
79e53945
JB		 9087 }
9088
9cce37f4
JB		 9089 /* Just disable it once at startup */
9090 i915_disable_vga(dev);
79e53945 9091 intel_setup_outputs(dev);
652c393a 9092
645c62a5 9093 intel_init_clock_gating(dev);
9cce37f4 9094
7648fa99 9095 if (IS_IRONLAKE_M(dev)) {
f97108d1 9096 ironlake_enable_drps(dev);
7648fa99
JB		 9097 intel_init_emon(dev);
9098 }
f97108d1 9099
1c70c0ce 9100 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9101 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9102 gen6_update_ring_freq(dev_priv);
9103 }
3b8d8d91 9104
652c393a
JB		 9105 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9106 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9107 (unsigned long)dev);
2c7111db
CW		 9108}
9109
9110void intel_modeset_gem_init(struct drm_device *dev)
9111{
9112 if (IS_IRONLAKE_M(dev))
9113 ironlake_enable_rc6(dev);
02e792fb
DV		 9114
9115 intel_setup_overlay(dev);
79e53945
JB		 9116}
9117
9118void intel_modeset_cleanup(struct drm_device *dev)
9119{
652c393a
JB		 9120 struct drm_i915_private *dev_priv = dev->dev_private;
9121 struct drm_crtc *crtc;
9122 struct intel_crtc *intel_crtc;
9123
f87ea761 9124 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9125 mutex_lock(&dev->struct_mutex);
9126
723bfd70
JB		 9127 intel_unregister_dsm_handler();
9128
9129
652c393a
JB		 9130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9131 /* Skip inactive CRTCs */
9132 if (!crtc->fb)
9133 continue;
9134
9135 intel_crtc = to_intel_crtc(crtc);
3dec0095 9136 intel_increase_pllclock(crtc);
652c393a
JB		 9137 }
9138
973d04f9 9139 intel_disable_fbc(dev);
e70236a8 9140
f97108d1
JB		 9141 if (IS_IRONLAKE_M(dev))
9142 ironlake_disable_drps(dev);
1c70c0ce 9143 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9144 gen6_disable_rps(dev);
f97108d1 9145
d5bb081b
JB		 9146 if (IS_IRONLAKE_M(dev))
9147 ironlake_disable_rc6(dev);
0cdab21f 9148
69341a5e
KH		 9149 mutex_unlock(&dev->struct_mutex);
9150
6c0d9350
DV		 9151 /* Disable the irq before mode object teardown, for the irq might
9152 * enqueue unpin/hotplug work. */
9153 drm_irq_uninstall(dev);
9154 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9155 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9156
1630fe75
CW		 9157 /* flush any delayed tasks or pending work */
9158 flush_scheduled_work();
9159
3dec0095
DV		 9160 /* Shut off idle work before the crtcs get freed. */
9161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9162 intel_crtc = to_intel_crtc(crtc);
9163 del_timer_sync(&intel_crtc->idle_timer);
9164 }
9165 del_timer_sync(&dev_priv->idle_timer);
9166 cancel_work_sync(&dev_priv->idle_work);
9167
79e53945
JB		 9168 drm_mode_config_cleanup(dev);
9169}
9170
f1c79df3
ZW		 9171/*
9172 * Return which encoder is currently attached for connector.
9173 */
df0e9248 9174struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9175{
df0e9248
CW		 9176 return &intel_attached_encoder(connector)->base;
9177}
f1c79df3 9178
df0e9248
CW		 9179void intel_connector_attach_encoder(struct intel_connector *connector,
9180 struct intel_encoder *encoder)
9181{
9182 connector->encoder = encoder;
9183 drm_mode_connector_attach_encoder(&connector->base,
9184 &encoder->base);
79e53945 9185}
28d52043
DA		 9186
9187/*
9188 * set vga decode state - true == enable VGA decode
9189 */
9190int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9191{
9192 struct drm_i915_private *dev_priv = dev->dev_private;
9193 u16 gmch_ctrl;
9194
9195 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9196 if (state)
9197 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9198 else
9199 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9200 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9201 return 0;
9202}
c4a1d9e4
CW		 9203
9204#ifdef CONFIG_DEBUG_FS
9205#include <linux/seq_file.h>
9206
9207struct intel_display_error_state {
9208 struct intel_cursor_error_state {
9209 u32 control;
9210 u32 position;
9211 u32 base;
9212 u32 size;
9213 } cursor[2];
9214
9215 struct intel_pipe_error_state {
9216 u32 conf;
9217 u32 source;
9218
9219 u32 htotal;
9220 u32 hblank;
9221 u32 hsync;
9222 u32 vtotal;
9223 u32 vblank;
9224 u32 vsync;
9225 } pipe[2];
9226
9227 struct intel_plane_error_state {
9228 u32 control;
9229 u32 stride;
9230 u32 size;
9231 u32 pos;
9232 u32 addr;
9233 u32 surface;
9234 u32 tile_offset;
9235 } plane[2];
9236};
9237
9238struct intel_display_error_state *
9239intel_display_capture_error_state(struct drm_device *dev)
9240{
0206e353 9241 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9242 struct intel_display_error_state *error;
9243 int i;
9244
9245 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9246 if (error == NULL)
9247 return NULL;
9248
9249 for (i = 0; i < 2; i++) {
9250 error->cursor[i].control = I915_READ(CURCNTR(i));
9251 error->cursor[i].position = I915_READ(CURPOS(i));
9252 error->cursor[i].base = I915_READ(CURBASE(i));
9253
9254 error->plane[i].control = I915_READ(DSPCNTR(i));
9255 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9256 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9257 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9258 error->plane[i].addr = I915_READ(DSPADDR(i));
9259 if (INTEL_INFO(dev)->gen >= 4) {
9260 error->plane[i].surface = I915_READ(DSPSURF(i));
9261 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9262 }
9263
9264 error->pipe[i].conf = I915_READ(PIPECONF(i));
9265 error->pipe[i].source = I915_READ(PIPESRC(i));
9266 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9267 error->pipe[i].hblank = I915_READ(HBLANK(i));
9268 error->pipe[i].hsync = I915_READ(HSYNC(i));
9269 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9270 error->pipe[i].vblank = I915_READ(VBLANK(i));
9271 error->pipe[i].vsync = I915_READ(VSYNC(i));
9272 }
9273
9274 return error;
9275}
9276
9277void
9278intel_display_print_error_state(struct seq_file *m,
9279 struct drm_device *dev,
9280 struct intel_display_error_state *error)
9281{
9282 int i;
9283
9284 for (i = 0; i < 2; i++) {
9285 seq_printf(m, "Pipe [%d]:\n", i);
9286 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9287 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9288 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9289 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9290 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9291 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9292 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9293 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9294
9295 seq_printf(m, "Plane [%d]:\n", i);
9296 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9297 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9298 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9299 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9300 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9301 if (INTEL_INFO(dev)->gen >= 4) {
9302 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9303 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9304 }
9305
9306 seq_printf(m, "Cursor [%d]:\n", i);
9307 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9308 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9309 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9310 }
9311}
9312#endif
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