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drm/i915: add swizzle/tiling support for Ivy Bridge
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
291906f1
JB		 982static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe, int reg)
984{
47a05eca
JB		 985 u32 val = I915_READ(reg);
986 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 987 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 988 reg, pipe_name(pipe));
291906f1
JB		 989}
990
991static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe, int reg)
993{
47a05eca
JB		 994 u32 val = I915_READ(reg);
995 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 996 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 997 reg, pipe_name(pipe));
291906f1
JB		 998}
999
1000static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001 enum pipe pipe)
1002{
1003 int reg;
1004 u32 val;
291906f1
JB		 1005
1006 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010 reg = PCH_ADPA;
1011 val = I915_READ(reg);
47a05eca 1012 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1013 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1014 pipe_name(pipe));
291906f1
JB		 1015
1016 reg = PCH_LVDS;
1017 val = I915_READ(reg);
47a05eca 1018 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1019 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1020 pipe_name(pipe));
291906f1
JB		 1021
1022 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025}
1026
63d7bbe9
JB		 1027/**
1028 * intel_enable_pll - enable a PLL
1029 * @dev_priv: i915 private structure
1030 * @pipe: pipe PLL to enable
1031 *
1032 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1033 * make sure the PLL reg is writable first though, since the panel write
1034 * protect mechanism may be enabled.
1035 *
1036 * Note! This is for pre-ILK only.
1037 */
1038static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039{
1040 int reg;
1041 u32 val;
1042
1043 /* No really, not for ILK+ */
1044 BUG_ON(dev_priv->info->gen >= 5);
1045
1046 /* PLL is protected by panel, make sure we can write it */
1047 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048 assert_panel_unlocked(dev_priv, pipe);
1049
1050 reg = DPLL(pipe);
1051 val = I915_READ(reg);
1052 val |= DPLL_VCO_ENABLE;
1053
1054 /* We do this three times for luck */
1055 I915_WRITE(reg, val);
1056 POSTING_READ(reg);
1057 udelay(150); /* wait for warmup */
1058 I915_WRITE(reg, val);
1059 POSTING_READ(reg);
1060 udelay(150); /* wait for warmup */
1061 I915_WRITE(reg, val);
1062 POSTING_READ(reg);
1063 udelay(150); /* wait for warmup */
1064}
1065
1066/**
1067 * intel_disable_pll - disable a PLL
1068 * @dev_priv: i915 private structure
1069 * @pipe: pipe PLL to disable
1070 *
1071 * Disable the PLL for @pipe, making sure the pipe is off first.
1072 *
1073 * Note! This is for pre-ILK only.
1074 */
1075static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076{
1077 int reg;
1078 u32 val;
1079
1080 /* Don't disable pipe A or pipe A PLLs if needed */
1081 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082 return;
1083
1084 /* Make sure the pipe isn't still relying on us */
1085 assert_pipe_disabled(dev_priv, pipe);
1086
1087 reg = DPLL(pipe);
1088 val = I915_READ(reg);
1089 val &= ~DPLL_VCO_ENABLE;
1090 I915_WRITE(reg, val);
1091 POSTING_READ(reg);
1092}
1093
92f2584a
JB		 1094/**
1095 * intel_enable_pch_pll - enable PCH PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100 * drives the transcoder clock.
1101 */
1102static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104{
1105 int reg;
1106 u32 val;
1107
1108 /* PCH only available on ILK+ */
1109 BUG_ON(dev_priv->info->gen < 5);
1110
1111 /* PCH refclock must be enabled first */
1112 assert_pch_refclk_enabled(dev_priv);
1113
1114 reg = PCH_DPLL(pipe);
1115 val = I915_READ(reg);
1116 val |= DPLL_VCO_ENABLE;
1117 I915_WRITE(reg, val);
1118 POSTING_READ(reg);
1119 udelay(200);
1120}
1121
1122static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* PCH only available on ILK+ */
1129 BUG_ON(dev_priv->info->gen < 5);
1130
1131 /* Make sure transcoder isn't still depending on us */
1132 assert_transcoder_disabled(dev_priv, pipe);
1133
1134 reg = PCH_DPLL(pipe);
1135 val = I915_READ(reg);
1136 val &= ~DPLL_VCO_ENABLE;
1137 I915_WRITE(reg, val);
1138 POSTING_READ(reg);
1139 udelay(200);
1140}
1141
040484af
JB		 1142static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144{
1145 int reg;
1146 u32 val;
1147
1148 /* PCH only available on ILK+ */
1149 BUG_ON(dev_priv->info->gen < 5);
1150
1151 /* Make sure PCH DPLL is enabled */
1152 assert_pch_pll_enabled(dev_priv, pipe);
1153
1154 /* FDI must be feeding us bits for PCH ports */
1155 assert_fdi_tx_enabled(dev_priv, pipe);
1156 assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158 reg = TRANSCONF(pipe);
1159 val = I915_READ(reg);
1160 /*
1161 * make the BPC in transcoder be consistent with
1162 * that in pipeconf reg.
1163 */
1164 val &= ~PIPE_BPC_MASK;
1165 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166 I915_WRITE(reg, val | TRANS_ENABLE);
1167 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169}
1170
1171static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173{
1174 int reg;
1175 u32 val;
1176
1177 /* FDI relies on the transcoder */
1178 assert_fdi_tx_disabled(dev_priv, pipe);
1179 assert_fdi_rx_disabled(dev_priv, pipe);
1180
291906f1
JB		 1181 /* Ports must be off as well */
1182 assert_pch_ports_disabled(dev_priv, pipe);
1183
040484af
JB		 1184 reg = TRANSCONF(pipe);
1185 val = I915_READ(reg);
1186 val &= ~TRANS_ENABLE;
1187 I915_WRITE(reg, val);
1188 /* wait for PCH transcoder off, transcoder state */
1189 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190 DRM_ERROR("failed to disable transcoder\n");
1191}
1192
b24e7179 1193/**
309cfea8 1194 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1195 * @dev_priv: i915 private structure
1196 * @pipe: pipe to enable
040484af 1197 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1198 *
1199 * Enable @pipe, making sure that various hardware specific requirements
1200 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201 *
1202 * @pipe should be %PIPE_A or %PIPE_B.
1203 *
1204 * Will wait until the pipe is actually running (i.e. first vblank) before
1205 * returning.
1206 */
040484af
JB		 1207static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208 bool pch_port)
b24e7179
JB		 1209{
1210 int reg;
1211 u32 val;
1212
1213 /*
1214 * A pipe without a PLL won't actually be able to drive bits from
1215 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1216 * need the check.
1217 */
1218 if (!HAS_PCH_SPLIT(dev_priv->dev))
1219 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1220 else {
1221 if (pch_port) {
1222 /* if driving the PCH, we need FDI enabled */
1223 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225 }
1226 /* FIXME: assert CPU port conditions for SNB+ */
1227 }
b24e7179
JB		 1228
1229 reg = PIPECONF(pipe);
1230 val = I915_READ(reg);
00d70b15
CW		 1231 if (val & PIPECONF_ENABLE)
1232 return;
1233
1234 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1235 intel_wait_for_vblank(dev_priv->dev, pipe);
1236}
1237
1238/**
309cfea8 1239 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1240 * @dev_priv: i915 private structure
1241 * @pipe: pipe to disable
1242 *
1243 * Disable @pipe, making sure that various hardware specific requirements
1244 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245 *
1246 * @pipe should be %PIPE_A or %PIPE_B.
1247 *
1248 * Will wait until the pipe has shut down before returning.
1249 */
1250static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252{
1253 int reg;
1254 u32 val;
1255
1256 /*
1257 * Make sure planes won't keep trying to pump pixels to us,
1258 * or we might hang the display.
1259 */
1260 assert_planes_disabled(dev_priv, pipe);
1261
1262 /* Don't disable pipe A or pipe A PLLs if needed */
1263 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264 return;
1265
1266 reg = PIPECONF(pipe);
1267 val = I915_READ(reg);
00d70b15
CW		 1268 if ((val & PIPECONF_ENABLE) == 0)
1269 return;
1270
1271 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1272 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273}
1274
1275/**
1276 * intel_enable_plane - enable a display plane on a given pipe
1277 * @dev_priv: i915 private structure
1278 * @plane: plane to enable
1279 * @pipe: pipe being fed
1280 *
1281 * Enable @plane on @pipe, making sure that @pipe is running first.
1282 */
1283static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, enum pipe pipe)
1285{
1286 int reg;
1287 u32 val;
1288
1289 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290 assert_pipe_enabled(dev_priv, pipe);
1291
1292 reg = DSPCNTR(plane);
1293 val = I915_READ(reg);
00d70b15
CW		 1294 if (val & DISPLAY_PLANE_ENABLE)
1295 return;
1296
1297 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1298 intel_wait_for_vblank(dev_priv->dev, pipe);
1299}
1300
1301/*
1302 * Plane regs are double buffered, going from enabled->disabled needs a
1303 * trigger in order to latch. The display address reg provides this.
1304 */
1305static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306 enum plane plane)
1307{
1308 u32 reg = DSPADDR(plane);
1309 I915_WRITE(reg, I915_READ(reg));
1310}
1311
1312/**
1313 * intel_disable_plane - disable a display plane
1314 * @dev_priv: i915 private structure
1315 * @plane: plane to disable
1316 * @pipe: pipe consuming the data
1317 *
1318 * Disable @plane; should be an independent operation.
1319 */
1320static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, enum pipe pipe)
1322{
1323 int reg;
1324 u32 val;
1325
1326 reg = DSPCNTR(plane);
1327 val = I915_READ(reg);
00d70b15
CW		 1328 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329 return;
1330
1331 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1332 intel_flush_display_plane(dev_priv, plane);
1333 intel_wait_for_vblank(dev_priv->dev, pipe);
1334}
1335
47a05eca
JB		 1336static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, int reg)
1338{
1339 u32 val = I915_READ(reg);
1340 if (DP_PIPE_ENABLED(val, pipe))
1341 I915_WRITE(reg, val & ~DP_PORT_EN);
1342}
1343
1344static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, int reg)
1346{
1347 u32 val = I915_READ(reg);
1348 if (HDMI_PIPE_ENABLED(val, pipe))
1349 I915_WRITE(reg, val & ~PORT_ENABLE);
1350}
1351
1352/* Disable any ports connected to this transcoder */
1353static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355{
1356 u32 reg, val;
1357
1358 val = I915_READ(PCH_PP_CONTROL);
1359 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365 reg = PCH_ADPA;
1366 val = I915_READ(reg);
1367 if (ADPA_PIPE_ENABLED(val, pipe))
1368 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370 reg = PCH_LVDS;
1371 val = I915_READ(reg);
1372 if (LVDS_PIPE_ENABLED(val, pipe)) {
1373 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374 POSTING_READ(reg);
1375 udelay(100);
1376 }
1377
1378 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380 disable_pch_hdmi(dev_priv, pipe, HDMID);
1381}
1382
80824003
JB		 1383static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384{
1385 struct drm_device *dev = crtc->dev;
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 struct drm_framebuffer *fb = crtc->fb;
1388 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1389 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391 int plane, i;
1392 u32 fbc_ctl, fbc_ctl2;
1393
bed4a673 1394 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1395 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1396 intel_crtc->plane == dev_priv->cfb_plane &&
1397 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398 return;
1399
1400 i8xx_disable_fbc(dev);
1401
80824003
JB		 1402 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404 if (fb->pitch < dev_priv->cfb_pitch)
1405 dev_priv->cfb_pitch = fb->pitch;
1406
1407 /* FBC_CTL wants 64B units */
1408 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1409 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1410 dev_priv->cfb_plane = intel_crtc->plane;
1411 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413 /* Clear old tags */
1414 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417 /* Set it up... */
1418 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1419 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1420 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424 /* enable it... */
1425 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1426 if (IS_I945GM(dev))
49677901 1427 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1428 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1430 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1431 fbc_ctl |= dev_priv->cfb_fence;
1432 I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
28c97730 1434 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1435 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1436}
1437
1438void i8xx_disable_fbc(struct drm_device *dev)
1439{
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 u32 fbc_ctl;
1442
1443 /* Disable compression */
1444 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1445 if ((fbc_ctl & FBC_CTL_EN) == 0)
1446 return;
1447
80824003
JB		 1448 fbc_ctl &= ~FBC_CTL_EN;
1449 I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451 /* Wait for compressing bit to clear */
481b6af3 1452 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1453 DRM_DEBUG_KMS("FBC idle timed out\n");
1454 return;
9517a92f 1455 }
80824003 1456
28c97730 1457 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1458}
1459
ee5382ae 1460static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1461{
80824003
JB		 1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465}
1466
74dff282
JB		 1467static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468{
1469 struct drm_device *dev = crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct drm_framebuffer *fb = crtc->fb;
1472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1473 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1475 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1476 unsigned long stall_watermark = 200;
1477 u32 dpfc_ctl;
1478
bed4a673
CW		 1479 dpfc_ctl = I915_READ(DPFC_CONTROL);
1480 if (dpfc_ctl & DPFC_CTL_EN) {
1481 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1482 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1483 dev_priv->cfb_plane == intel_crtc->plane &&
1484 dev_priv->cfb_y == crtc->y)
1485 return;
1486
1487 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1488 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489 }
1490
74dff282 1491 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1492 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1493 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1494 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1495
1496 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1497 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1498 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500 } else {
1501 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502 }
1503
74dff282
JB		 1504 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509 /* enable it... */
1510 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
28c97730 1512 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1513}
1514
1515void g4x_disable_fbc(struct drm_device *dev)
1516{
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 u32 dpfc_ctl;
1519
1520 /* Disable compression */
1521 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1522 if (dpfc_ctl & DPFC_CTL_EN) {
1523 dpfc_ctl &= ~DPFC_CTL_EN;
1524 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1525
bed4a673
CW		 1526 DRM_DEBUG_KMS("disabled FBC\n");
1527 }
74dff282
JB		 1528}
1529
ee5382ae 1530static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1531{
74dff282
JB		 1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535}
1536
4efe0708
JB		 1537static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538{
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 u32 blt_ecoskpd;
1541
1542 /* Make sure blitter notifies FBC of writes */
fcca7926 1543 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1544 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546 GEN6_BLITTER_LOCK_SHIFT;
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551 GEN6_BLITTER_LOCK_SHIFT);
1552 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1554 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1555}
1556
b52eb4dc
ZY		 1557static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558{
1559 struct drm_device *dev = crtc->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 struct drm_framebuffer *fb = crtc->fb;
1562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1563 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1565 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1566 unsigned long stall_watermark = 200;
1567 u32 dpfc_ctl;
1568
bed4a673
CW		 1569 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570 if (dpfc_ctl & DPFC_CTL_EN) {
1571 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1572 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1573 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1574 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1575 dev_priv->cfb_y == crtc->y)
1576 return;
1577
1578 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1579 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580 }
1581
b52eb4dc 1582 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1583 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1584 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1585 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1586 dev_priv->cfb_y = crtc->y;
b52eb4dc 1587
b52eb4dc
ZY		 1588 dpfc_ctl &= DPFC_RESERVED;
1589 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1590 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1591 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593 } else {
1594 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595 }
1596
b52eb4dc
ZY		 1597 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1601 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1602 /* enable it... */
bed4a673 1603 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1604
9c04f015
YL		 1605 if (IS_GEN6(dev)) {
1606 I915_WRITE(SNB_DPFC_CTL_SA,
1607 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1609 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1610 }
1611
b52eb4dc
ZY		 1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613}
1614
1615void ironlake_disable_fbc(struct drm_device *dev)
1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1625
bed4a673
CW		 1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
b52eb4dc
ZY		 1628}
1629
1630static bool ironlake_fbc_enabled(struct drm_device *dev)
1631{
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
ee5382ae
AJ		 1637bool intel_fbc_enabled(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641 if (!dev_priv->display.fbc_enabled)
1642 return false;
1643
1644 return dev_priv->display.fbc_enabled(dev);
1645}
1646
1647void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648{
1649 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651 if (!dev_priv->display.enable_fbc)
1652 return;
1653
1654 dev_priv->display.enable_fbc(crtc, interval);
1655}
1656
1657void intel_disable_fbc(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (!dev_priv->display.disable_fbc)
1662 return;
1663
1664 dev_priv->display.disable_fbc(dev);
1665}
1666
80824003
JB		 1667/**
1668 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1669 * @dev: the drm_device
80824003
JB		 1670 *
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1676 * - no dual wide
1677 * - framebuffer <= 2048 in width, 1536 in height
1678 *
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1682 * stolen memory.
1683 *
1684 * We need to enable/disable FBC on a global basis.
1685 */
bed4a673 1686static void intel_update_fbc(struct drm_device *dev)
80824003 1687{
80824003 1688 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1689 struct drm_crtc *crtc = NULL, *tmp_crtc;
1690 struct intel_crtc *intel_crtc;
1691 struct drm_framebuffer *fb;
80824003 1692 struct intel_framebuffer *intel_fb;
05394f39 1693 struct drm_i915_gem_object *obj;
9c928d16
JB		 1694
1695 DRM_DEBUG_KMS("\n");
80824003
JB		 1696
1697 if (!i915_powersave)
1698 return;
1699
ee5382ae 1700 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1701 return;
1702
80824003
JB		 1703 /*
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
9c928d16 1707 * - more than one pipe is active
80824003
JB		 1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1711 */
9c928d16 1712 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1713 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1714 if (crtc) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717 goto out_disable;
1718 }
1719 crtc = tmp_crtc;
1720 }
9c928d16 1721 }
bed4a673
CW		 1722
1723 if (!crtc || crtc->fb == NULL) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1726 goto out_disable;
1727 }
bed4a673
CW		 1728
1729 intel_crtc = to_intel_crtc(crtc);
1730 fb = crtc->fb;
1731 intel_fb = to_intel_framebuffer(fb);
05394f39 1732 obj = intel_fb->obj;
bed4a673 1733
05394f39 1734 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1735 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1736 "compression\n");
b5e50c3f 1737 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1738 goto out_disable;
1739 }
bed4a673
CW		 1740 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1741 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1742 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1743 "disabling\n");
b5e50c3f 1744 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1745 goto out_disable;
1746 }
bed4a673
CW		 1747 if ((crtc->mode.hdisplay > 2048) ||
1748 (crtc->mode.vdisplay > 1536)) {
28c97730 1749 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1750 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1751 goto out_disable;
1752 }
bed4a673 1753 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1754 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1755 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1756 goto out_disable;
1757 }
05394f39 1758 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1759 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1760 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1761 goto out_disable;
1762 }
1763
c924b934
JW		 1764 /* If the kernel debugger is active, always disable compression */
1765 if (in_dbg_master())
1766 goto out_disable;
1767
bed4a673 1768 intel_enable_fbc(crtc, 500);
80824003
JB		 1769 return;
1770
1771out_disable:
80824003 1772 /* Multiple disables should be harmless */
a939406f
CW		 1773 if (intel_fbc_enabled(dev)) {
1774 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1775 intel_disable_fbc(dev);
a939406f 1776 }
80824003
JB		 1777}
1778
127bd2ac 1779int
48b956c5 1780intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1781 struct drm_i915_gem_object *obj,
919926ae 1782 struct intel_ring_buffer *pipelined)
6b95a207 1783{
ce453d81 1784 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1785 u32 alignment;
1786 int ret;
1787
05394f39 1788 switch (obj->tiling_mode) {
6b95a207 1789 case I915_TILING_NONE:
534843da
CW		 1790 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791 alignment = 128 * 1024;
a6c45cf0 1792 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1793 alignment = 4 * 1024;
1794 else
1795 alignment = 64 * 1024;
6b95a207
KH		 1796 break;
1797 case I915_TILING_X:
1798 /* pin() will align the object as required by fence */
1799 alignment = 0;
1800 break;
1801 case I915_TILING_Y:
1802 /* FIXME: Is this true? */
1803 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1804 return -EINVAL;
1805 default:
1806 BUG();
1807 }
1808
ce453d81 1809 dev_priv->mm.interruptible = false;
75e9e915 1810 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1811 if (ret)
ce453d81 1812 goto err_interruptible;
6b95a207 1813
48b956c5
CW		 1814 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1815 if (ret)
1816 goto err_unpin;
7213342d 1817
6b95a207
KH		 1818 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1819 * fence, whereas 965+ only requires a fence if using
1820 * framebuffer compression. For simplicity, we always install
1821 * a fence as the cost is not that onerous.
1822 */
05394f39 1823 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1824 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1825 if (ret)
1826 goto err_unpin;
6b95a207
KH		 1827 }
1828
ce453d81 1829 dev_priv->mm.interruptible = true;
6b95a207 1830 return 0;
48b956c5
CW		 1831
1832err_unpin:
1833 i915_gem_object_unpin(obj);
ce453d81
CW		 1834err_interruptible:
1835 dev_priv->mm.interruptible = true;
48b956c5 1836 return ret;
6b95a207
KH		 1837}
1838
81255565
JB		 1839/* Assume fb object is pinned & idle & fenced and just update base pointers */
1840static int
1841intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1842 int x, int y, enum mode_set_atomic state)
81255565
JB		 1843{
1844 struct drm_device *dev = crtc->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 struct intel_framebuffer *intel_fb;
05394f39 1848 struct drm_i915_gem_object *obj;
81255565
JB		 1849 int plane = intel_crtc->plane;
1850 unsigned long Start, Offset;
81255565 1851 u32 dspcntr;
5eddb70b 1852 u32 reg;
81255565
JB		 1853
1854 switch (plane) {
1855 case 0:
1856 case 1:
1857 break;
1858 default:
1859 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1860 return -EINVAL;
1861 }
1862
1863 intel_fb = to_intel_framebuffer(fb);
1864 obj = intel_fb->obj;
81255565 1865
5eddb70b
CW		 1866 reg = DSPCNTR(plane);
1867 dspcntr = I915_READ(reg);
81255565
JB		 1868 /* Mask out pixel format bits in case we change it */
1869 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1870 switch (fb->bits_per_pixel) {
1871 case 8:
1872 dspcntr |= DISPPLANE_8BPP;
1873 break;
1874 case 16:
1875 if (fb->depth == 15)
1876 dspcntr |= DISPPLANE_15_16BPP;
1877 else
1878 dspcntr |= DISPPLANE_16BPP;
1879 break;
1880 case 24:
1881 case 32:
1882 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1883 break;
1884 default:
1885 DRM_ERROR("Unknown color depth\n");
1886 return -EINVAL;
1887 }
a6c45cf0 1888 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1889 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1890 dspcntr |= DISPPLANE_TILED;
1891 else
1892 dspcntr &= ~DISPPLANE_TILED;
1893 }
1894
4e6cfefc 1895 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1896 /* must disable */
1897 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1898
5eddb70b 1899 I915_WRITE(reg, dspcntr);
81255565 1900
05394f39 1901 Start = obj->gtt_offset;
81255565
JB		 1902 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1903
4e6cfefc
CW		 1904 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1905 Start, Offset, x, y, fb->pitch);
5eddb70b 1906 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1907 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1908 I915_WRITE(DSPSURF(plane), Start);
1909 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1910 I915_WRITE(DSPADDR(plane), Offset);
1911 } else
1912 I915_WRITE(DSPADDR(plane), Start + Offset);
1913 POSTING_READ(reg);
81255565 1914
bed4a673 1915 intel_update_fbc(dev);
3dec0095 1916 intel_increase_pllclock(crtc);
81255565
JB		 1917
1918 return 0;
1919}
1920
5c3b82e2 1921static int
3c4fdcfb
KH		 1922intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1923 struct drm_framebuffer *old_fb)
79e53945
JB		 1924{
1925 struct drm_device *dev = crtc->dev;
79e53945
JB		 1926 struct drm_i915_master_private *master_priv;
1927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1928 int ret;
79e53945
JB		 1929
1930 /* no fb bound */
1931 if (!crtc->fb) {
28c97730 1932 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1933 return 0;
1934 }
1935
265db958 1936 switch (intel_crtc->plane) {
5c3b82e2
CW		 1937 case 0:
1938 case 1:
1939 break;
1940 default:
5c3b82e2 1941 return -EINVAL;
79e53945
JB		 1942 }
1943
5c3b82e2 1944 mutex_lock(&dev->struct_mutex);
265db958
CW		 1945 ret = intel_pin_and_fence_fb_obj(dev,
1946 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1947 NULL);
5c3b82e2
CW		 1948 if (ret != 0) {
1949 mutex_unlock(&dev->struct_mutex);
1950 return ret;
1951 }
79e53945 1952
265db958 1953 if (old_fb) {
e6c3a2a6 1954 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1955 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1956
e6c3a2a6 1957 wait_event(dev_priv->pending_flip_queue,
01eec727 1958 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1959 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1960
1961 /* Big Hammer, we also need to ensure that any pending
1962 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1963 * current scanout is retired before unpinning the old
1964 * framebuffer.
01eec727
CW		 1965 *
1966 * This should only fail upon a hung GPU, in which case we
1967 * can safely continue.
85345517 1968 */
ce453d81 1969 ret = i915_gem_object_flush_gpu(obj);
01eec727 1970 (void) ret;
265db958
CW		 1971 }
1972
21c74a8e
JW		 1973 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1974 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1975 if (ret) {
265db958 1976 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1977 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1978 return ret;
79e53945 1979 }
3c4fdcfb 1980
b7f1de28
CW		 1981 if (old_fb) {
1982 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 1983 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1984 }
652c393a 1985
5c3b82e2 1986 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1987
1988 if (!dev->primary->master)
5c3b82e2 1989 return 0;
79e53945
JB		 1990
1991 master_priv = dev->primary->master->driver_priv;
1992 if (!master_priv->sarea_priv)
5c3b82e2 1993 return 0;
79e53945 1994
265db958 1995 if (intel_crtc->pipe) {
79e53945
JB		 1996 master_priv->sarea_priv->pipeB_x = x;
1997 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 1998 } else {
1999 master_priv->sarea_priv->pipeA_x = x;
2000 master_priv->sarea_priv->pipeA_y = y;
79e53945 2001 }
5c3b82e2
CW		 2002
2003 return 0;
79e53945
JB		 2004}
2005
5eddb70b 2006static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2007{
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 dpa_ctl;
2011
28c97730 2012 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2013 dpa_ctl = I915_READ(DP_A);
2014 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2015
2016 if (clock < 200000) {
2017 u32 temp;
2018 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2019 /* workaround for 160Mhz:
2020 1) program 0x4600c bits 15:0 = 0x8124
2021 2) program 0x46010 bit 0 = 1
2022 3) program 0x46034 bit 24 = 1
2023 4) program 0x64000 bit 14 = 1
2024 */
2025 temp = I915_READ(0x4600c);
2026 temp &= 0xffff0000;
2027 I915_WRITE(0x4600c, temp | 0x8124);
2028
2029 temp = I915_READ(0x46010);
2030 I915_WRITE(0x46010, temp | 1);
2031
2032 temp = I915_READ(0x46034);
2033 I915_WRITE(0x46034, temp | (1 << 24));
2034 } else {
2035 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2036 }
2037 I915_WRITE(DP_A, dpa_ctl);
2038
5eddb70b 2039 POSTING_READ(DP_A);
32f9d658
ZW		 2040 udelay(500);
2041}
2042
5e84e1a4
ZW		 2043static void intel_fdi_normal_train(struct drm_crtc *crtc)
2044{
2045 struct drm_device *dev = crtc->dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048 int pipe = intel_crtc->pipe;
2049 u32 reg, temp;
2050
2051 /* enable normal train */
2052 reg = FDI_TX_CTL(pipe);
2053 temp = I915_READ(reg);
2054 temp &= ~FDI_LINK_TRAIN_NONE;
2055 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2056 I915_WRITE(reg, temp);
2057
2058 reg = FDI_RX_CTL(pipe);
2059 temp = I915_READ(reg);
2060 if (HAS_PCH_CPT(dev)) {
2061 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2062 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2063 } else {
2064 temp &= ~FDI_LINK_TRAIN_NONE;
2065 temp |= FDI_LINK_TRAIN_NONE;
2066 }
2067 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2068
2069 /* wait one idle pattern time */
2070 POSTING_READ(reg);
2071 udelay(1000);
2072}
2073
8db9d77b
ZW		 2074/* The FDI link training functions for ILK/Ibexpeak. */
2075static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 int pipe = intel_crtc->pipe;
0fc932b8 2081 int plane = intel_crtc->plane;
5eddb70b 2082 u32 reg, temp, tries;
8db9d77b 2083
0fc932b8
JB		 2084 /* FDI needs bits from pipe & plane first */
2085 assert_pipe_enabled(dev_priv, pipe);
2086 assert_plane_enabled(dev_priv, plane);
2087
e1a44743
AJ		 2088 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2089 for train result */
5eddb70b
CW		 2090 reg = FDI_RX_IMR(pipe);
2091 temp = I915_READ(reg);
e1a44743
AJ		 2092 temp &= ~FDI_RX_SYMBOL_LOCK;
2093 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2094 I915_WRITE(reg, temp);
2095 I915_READ(reg);
e1a44743
AJ		 2096 udelay(150);
2097
8db9d77b 2098 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2099 reg = FDI_TX_CTL(pipe);
2100 temp = I915_READ(reg);
77ffb597
AJ		 2101 temp &= ~(7 << 19);
2102 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2103 temp &= ~FDI_LINK_TRAIN_NONE;
2104 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2105 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2106
5eddb70b
CW		 2107 reg = FDI_RX_CTL(pipe);
2108 temp = I915_READ(reg);
8db9d77b
ZW		 2109 temp &= ~FDI_LINK_TRAIN_NONE;
2110 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2111 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2112
2113 POSTING_READ(reg);
8db9d77b
ZW		 2114 udelay(150);
2115
5b2adf89 2116 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2117 if (HAS_PCH_IBX(dev)) {
2118 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2119 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2120 FDI_RX_PHASE_SYNC_POINTER_EN);
2121 }
5b2adf89 2122
5eddb70b 2123 reg = FDI_RX_IIR(pipe);
e1a44743 2124 for (tries = 0; tries < 5; tries++) {
5eddb70b 2125 temp = I915_READ(reg);
8db9d77b
ZW		 2126 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2127
2128 if ((temp & FDI_RX_BIT_LOCK)) {
2129 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2130 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2131 break;
2132 }
8db9d77b 2133 }
e1a44743 2134 if (tries == 5)
5eddb70b 2135 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2136
2137 /* Train 2 */
5eddb70b
CW		 2138 reg = FDI_TX_CTL(pipe);
2139 temp = I915_READ(reg);
8db9d77b
ZW		 2140 temp &= ~FDI_LINK_TRAIN_NONE;
2141 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2142 I915_WRITE(reg, temp);
8db9d77b 2143
5eddb70b
CW		 2144 reg = FDI_RX_CTL(pipe);
2145 temp = I915_READ(reg);
8db9d77b
ZW		 2146 temp &= ~FDI_LINK_TRAIN_NONE;
2147 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2148 I915_WRITE(reg, temp);
8db9d77b 2149
5eddb70b
CW		 2150 POSTING_READ(reg);
2151 udelay(150);
8db9d77b 2152
5eddb70b 2153 reg = FDI_RX_IIR(pipe);
e1a44743 2154 for (tries = 0; tries < 5; tries++) {
5eddb70b 2155 temp = I915_READ(reg);
8db9d77b
ZW		 2156 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2157
2158 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2159 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2160 DRM_DEBUG_KMS("FDI train 2 done.\n");
2161 break;
2162 }
8db9d77b 2163 }
e1a44743 2164 if (tries == 5)
5eddb70b 2165 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2166
2167 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2168
8db9d77b
ZW		 2169}
2170
311bd68e 2171static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2172 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2173 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2174 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2175 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2176};
2177
2178/* The FDI link training functions for SNB/Cougarpoint. */
2179static void gen6_fdi_link_train(struct drm_crtc *crtc)
2180{
2181 struct drm_device *dev = crtc->dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2184 int pipe = intel_crtc->pipe;
5eddb70b 2185 u32 reg, temp, i;
8db9d77b 2186
e1a44743
AJ		 2187 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2188 for train result */
5eddb70b
CW		 2189 reg = FDI_RX_IMR(pipe);
2190 temp = I915_READ(reg);
e1a44743
AJ		 2191 temp &= ~FDI_RX_SYMBOL_LOCK;
2192 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2193 I915_WRITE(reg, temp);
2194
2195 POSTING_READ(reg);
e1a44743
AJ		 2196 udelay(150);
2197
8db9d77b 2198 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2199 reg = FDI_TX_CTL(pipe);
2200 temp = I915_READ(reg);
77ffb597
AJ		 2201 temp &= ~(7 << 19);
2202 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2203 temp &= ~FDI_LINK_TRAIN_NONE;
2204 temp |= FDI_LINK_TRAIN_PATTERN_1;
2205 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2206 /* SNB-B */
2207 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2208 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2209
5eddb70b
CW		 2210 reg = FDI_RX_CTL(pipe);
2211 temp = I915_READ(reg);
8db9d77b
ZW		 2212 if (HAS_PCH_CPT(dev)) {
2213 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2215 } else {
2216 temp &= ~FDI_LINK_TRAIN_NONE;
2217 temp |= FDI_LINK_TRAIN_PATTERN_1;
2218 }
5eddb70b
CW		 2219 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2220
2221 POSTING_READ(reg);
8db9d77b
ZW		 2222 udelay(150);
2223
8db9d77b 2224 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2229 I915_WRITE(reg, temp);
2230
2231 POSTING_READ(reg);
8db9d77b
ZW		 2232 udelay(500);
2233
5eddb70b
CW		 2234 reg = FDI_RX_IIR(pipe);
2235 temp = I915_READ(reg);
8db9d77b
ZW		 2236 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2237
2238 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2240 DRM_DEBUG_KMS("FDI train 1 done.\n");
2241 break;
2242 }
2243 }
2244 if (i == 4)
5eddb70b 2245 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2246
2247 /* Train 2 */
5eddb70b
CW		 2248 reg = FDI_TX_CTL(pipe);
2249 temp = I915_READ(reg);
8db9d77b
ZW		 2250 temp &= ~FDI_LINK_TRAIN_NONE;
2251 temp |= FDI_LINK_TRAIN_PATTERN_2;
2252 if (IS_GEN6(dev)) {
2253 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2254 /* SNB-B */
2255 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2256 }
5eddb70b 2257 I915_WRITE(reg, temp);
8db9d77b 2258
5eddb70b
CW		 2259 reg = FDI_RX_CTL(pipe);
2260 temp = I915_READ(reg);
8db9d77b
ZW		 2261 if (HAS_PCH_CPT(dev)) {
2262 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2263 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2264 } else {
2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 }
5eddb70b
CW		 2268 I915_WRITE(reg, temp);
2269
2270 POSTING_READ(reg);
8db9d77b
ZW		 2271 udelay(150);
2272
2273 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
8db9d77b
ZW		 2276 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2277 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2278 I915_WRITE(reg, temp);
2279
2280 POSTING_READ(reg);
8db9d77b
ZW		 2281 udelay(500);
2282
5eddb70b
CW		 2283 reg = FDI_RX_IIR(pipe);
2284 temp = I915_READ(reg);
8db9d77b
ZW		 2285 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2286
2287 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2288 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2289 DRM_DEBUG_KMS("FDI train 2 done.\n");
2290 break;
2291 }
2292 }
2293 if (i == 4)
5eddb70b 2294 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2295
2296 DRM_DEBUG_KMS("FDI train done.\n");
2297}
2298
0e23b99d 2299static void ironlake_fdi_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2300{
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 int pipe = intel_crtc->pipe;
5eddb70b 2305 u32 reg, temp;
79e53945 2306
c64e311e 2307 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2308 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2309 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2310
c98e9dcf 2311 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2315 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2316 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2317 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2318
2319 POSTING_READ(reg);
c98e9dcf
JB		 2320 udelay(200);
2321
2322 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2323 temp = I915_READ(reg);
2324 I915_WRITE(reg, temp | FDI_PCDCLK);
2325
2326 POSTING_READ(reg);
c98e9dcf
JB		 2327 udelay(200);
2328
2329 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2330 reg = FDI_TX_CTL(pipe);
2331 temp = I915_READ(reg);
c98e9dcf 2332 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2333 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2334
2335 POSTING_READ(reg);
c98e9dcf 2336 udelay(100);
6be4a607 2337 }
0e23b99d
JB		 2338}
2339
0fc932b8
JB		 2340static void ironlake_fdi_disable(struct drm_crtc *crtc)
2341{
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 u32 reg, temp;
2347
2348 /* disable CPU FDI tx and PCH FDI rx */
2349 reg = FDI_TX_CTL(pipe);
2350 temp = I915_READ(reg);
2351 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2352 POSTING_READ(reg);
2353
2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~(0x7 << 16);
2357 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2358 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2359
2360 POSTING_READ(reg);
2361 udelay(100);
2362
2363 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2364 if (HAS_PCH_IBX(dev)) {
2365 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2366 I915_WRITE(FDI_RX_CHICKEN(pipe),
2367 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2368 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2369 }
0fc932b8
JB		 2370
2371 /* still set train pattern 1 */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 I915_WRITE(reg, temp);
2377
2378 reg = FDI_RX_CTL(pipe);
2379 temp = I915_READ(reg);
2380 if (HAS_PCH_CPT(dev)) {
2381 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2383 } else {
2384 temp &= ~FDI_LINK_TRAIN_NONE;
2385 temp |= FDI_LINK_TRAIN_PATTERN_1;
2386 }
2387 /* BPC in FDI rx is consistent with that in PIPECONF */
2388 temp &= ~(0x07 << 16);
2389 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2390 I915_WRITE(reg, temp);
2391
2392 POSTING_READ(reg);
2393 udelay(100);
2394}
2395
6b383a7f
CW		 2396/*
2397 * When we disable a pipe, we need to clear any pending scanline wait events
2398 * to avoid hanging the ring, which we assume we are waiting on.
2399 */
2400static void intel_clear_scanline_wait(struct drm_device *dev)
2401{
2402 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2403 struct intel_ring_buffer *ring;
6b383a7f
CW		 2404 u32 tmp;
2405
2406 if (IS_GEN2(dev))
2407 /* Can't break the hang on i8xx */
2408 return;
2409
1ec14ad3 2410 ring = LP_RING(dev_priv);
8168bd48
CW		 2411 tmp = I915_READ_CTL(ring);
2412 if (tmp & RING_WAIT)
2413 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2414}
2415
e6c3a2a6
CW		 2416static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2417{
05394f39 2418 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2419 struct drm_i915_private *dev_priv;
2420
2421 if (crtc->fb == NULL)
2422 return;
2423
05394f39 2424 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2425 dev_priv = crtc->dev->dev_private;
2426 wait_event(dev_priv->pending_flip_queue,
05394f39 2427 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2428}
2429
040484af
JB		 2430static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2431{
2432 struct drm_device *dev = crtc->dev;
2433 struct drm_mode_config *mode_config = &dev->mode_config;
2434 struct intel_encoder *encoder;
2435
2436 /*
2437 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2438 * must be driven by its own crtc; no sharing is possible.
2439 */
2440 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2441 if (encoder->base.crtc != crtc)
2442 continue;
2443
2444 switch (encoder->type) {
2445 case INTEL_OUTPUT_EDP:
2446 if (!intel_encoder_is_pch_edp(&encoder->base))
2447 return false;
2448 continue;
2449 }
2450 }
2451
2452 return true;
2453}
2454
f67a559d
JB		 2455/*
2456 * Enable PCH resources required for PCH ports:
2457 * - PCH PLLs
2458 * - FDI training & RX/TX
2459 * - update transcoder timings
2460 * - DP transcoding bits
2461 * - transcoder
2462 */
2463static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
5eddb70b 2469 u32 reg, temp;
2c07245f 2470
c98e9dcf 2471 /* For PCH output, training FDI link */
674cf967 2472 dev_priv->display.fdi_link_train(crtc);
2c07245f 2473
92f2584a 2474 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2475
c98e9dcf
JB		 2476 if (HAS_PCH_CPT(dev)) {
2477 /* Be sure PCH DPLL SEL is set */
2478 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2479 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2480 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2481 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2482 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2483 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2484 }
5eddb70b 2485
d9b6cb56
JB		 2486 /* set transcoder timing, panel must allow it */
2487 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2488 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2489 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2490 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2491
5eddb70b
CW		 2492 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2493 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2494 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2495
5e84e1a4
ZW		 2496 intel_fdi_normal_train(crtc);
2497
c98e9dcf
JB		 2498 /* For PCH DP, enable TRANS_DP_CTL */
2499 if (HAS_PCH_CPT(dev) &&
2500 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2501 reg = TRANS_DP_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2504 TRANS_DP_SYNC_MASK |
2505 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2506 temp |= (TRANS_DP_OUTPUT_ENABLE |
2507 TRANS_DP_ENH_FRAMING);
220cad3c 2508 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2509
2510 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2511 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2512 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2513 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2514
2515 switch (intel_trans_dp_port_sel(crtc)) {
2516 case PCH_DP_B:
5eddb70b 2517 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2518 break;
2519 case PCH_DP_C:
5eddb70b 2520 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2521 break;
2522 case PCH_DP_D:
5eddb70b 2523 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2524 break;
2525 default:
2526 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2527 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2528 break;
32f9d658 2529 }
2c07245f 2530
5eddb70b 2531 I915_WRITE(reg, temp);
6be4a607 2532 }
b52eb4dc 2533
040484af 2534 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2535}
2536
2537static void ironlake_crtc_enable(struct drm_crtc *crtc)
2538{
2539 struct drm_device *dev = crtc->dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2542 int pipe = intel_crtc->pipe;
2543 int plane = intel_crtc->plane;
2544 u32 temp;
2545 bool is_pch_port;
2546
2547 if (intel_crtc->active)
2548 return;
2549
2550 intel_crtc->active = true;
2551 intel_update_watermarks(dev);
2552
2553 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2554 temp = I915_READ(PCH_LVDS);
2555 if ((temp & LVDS_PORT_EN) == 0)
2556 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2557 }
2558
2559 is_pch_port = intel_crtc_driving_pch(crtc);
2560
2561 if (is_pch_port)
2562 ironlake_fdi_enable(crtc);
2563 else
2564 ironlake_fdi_disable(crtc);
2565
2566 /* Enable panel fitting for LVDS */
2567 if (dev_priv->pch_pf_size &&
2568 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2569 /* Force use of hard-coded filter coefficients
2570 * as some pre-programmed values are broken,
2571 * e.g. x201.
2572 */
9db4a9c7
JB		 2573 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2574 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2575 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2576 }
2577
2578 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2579 intel_enable_plane(dev_priv, plane, pipe);
2580
2581 if (is_pch_port)
2582 ironlake_pch_enable(crtc);
c98e9dcf 2583
6be4a607 2584 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2585
2586 mutex_lock(&dev->struct_mutex);
bed4a673 2587 intel_update_fbc(dev);
d1ebd816
BW		 2588 mutex_unlock(&dev->struct_mutex);
2589
6b383a7f 2590 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2591}
2592
2593static void ironlake_crtc_disable(struct drm_crtc *crtc)
2594{
2595 struct drm_device *dev = crtc->dev;
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2598 int pipe = intel_crtc->pipe;
2599 int plane = intel_crtc->plane;
5eddb70b 2600 u32 reg, temp;
b52eb4dc 2601
f7abfe8b
CW		 2602 if (!intel_crtc->active)
2603 return;
2604
e6c3a2a6 2605 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2606 drm_vblank_off(dev, pipe);
6b383a7f 2607 intel_crtc_update_cursor(crtc, false);
5eddb70b 2608
b24e7179 2609 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2610
6be4a607
JB		 2611 if (dev_priv->cfb_plane == plane &&
2612 dev_priv->display.disable_fbc)
2613 dev_priv->display.disable_fbc(dev);
2c07245f 2614
b24e7179 2615 intel_disable_pipe(dev_priv, pipe);
32f9d658 2616
6be4a607 2617 /* Disable PF */
9db4a9c7
JB		 2618 I915_WRITE(PF_CTL(pipe), 0);
2619 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2620
0fc932b8 2621 ironlake_fdi_disable(crtc);
2c07245f 2622
47a05eca
JB		 2623 /* This is a horrible layering violation; we should be doing this in
2624 * the connector/encoder ->prepare instead, but we don't always have
2625 * enough information there about the config to know whether it will
2626 * actually be necessary or just cause undesired flicker.
2627 */
2628 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2629
040484af 2630 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2631
6be4a607
JB		 2632 if (HAS_PCH_CPT(dev)) {
2633 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2634 reg = TRANS_DP_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2637 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2638 I915_WRITE(reg, temp);
6be4a607
JB		 2639
2640 /* disable DPLL_SEL */
2641 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2642 switch (pipe) {
2643 case 0:
2644 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2645 break;
2646 case 1:
6be4a607 2647 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2648 break;
2649 case 2:
2650 /* FIXME: manage transcoder PLLs? */
2651 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2652 break;
2653 default:
2654 BUG(); /* wtf */
2655 }
6be4a607 2656 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2657 }
e3421a18 2658
6be4a607 2659 /* disable PCH DPLL */
92f2584a 2660 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2661
6be4a607 2662 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2666
6be4a607 2667 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2668 reg = FDI_TX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2671
2672 POSTING_READ(reg);
6be4a607 2673 udelay(100);
8db9d77b 2674
5eddb70b
CW		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2678
6be4a607 2679 /* Wait for the clocks to turn off. */
5eddb70b 2680 POSTING_READ(reg);
6be4a607 2681 udelay(100);
6b383a7f 2682
f7abfe8b 2683 intel_crtc->active = false;
6b383a7f 2684 intel_update_watermarks(dev);
d1ebd816
BW		 2685
2686 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2687 intel_update_fbc(dev);
2688 intel_clear_scanline_wait(dev);
d1ebd816 2689 mutex_unlock(&dev->struct_mutex);
6be4a607 2690}
1b3c7a47 2691
6be4a607
JB		 2692static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2693{
2694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695 int pipe = intel_crtc->pipe;
2696 int plane = intel_crtc->plane;
8db9d77b 2697
6be4a607
JB		 2698 /* XXX: When our outputs are all unaware of DPMS modes other than off
2699 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2700 */
2701 switch (mode) {
2702 case DRM_MODE_DPMS_ON:
2703 case DRM_MODE_DPMS_STANDBY:
2704 case DRM_MODE_DPMS_SUSPEND:
2705 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2706 ironlake_crtc_enable(crtc);
2707 break;
1b3c7a47 2708
6be4a607
JB		 2709 case DRM_MODE_DPMS_OFF:
2710 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2711 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2712 break;
2713 }
2714}
2715
02e792fb
DV		 2716static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2717{
02e792fb 2718 if (!enable && intel_crtc->overlay) {
23f09ce3 2719 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2720 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2721
23f09ce3 2722 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2723 dev_priv->mm.interruptible = false;
2724 (void) intel_overlay_switch_off(intel_crtc->overlay);
2725 dev_priv->mm.interruptible = true;
23f09ce3 2726 mutex_unlock(&dev->struct_mutex);
02e792fb 2727 }
02e792fb 2728
5dcdbcb0
CW		 2729 /* Let userspace switch the overlay on again. In most cases userspace
2730 * has to recompute where to put it anyway.
2731 */
02e792fb
DV		 2732}
2733
0b8765c6 2734static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2735{
2736 struct drm_device *dev = crtc->dev;
79e53945
JB		 2737 struct drm_i915_private *dev_priv = dev->dev_private;
2738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2739 int pipe = intel_crtc->pipe;
80824003 2740 int plane = intel_crtc->plane;
79e53945 2741
f7abfe8b
CW		 2742 if (intel_crtc->active)
2743 return;
2744
2745 intel_crtc->active = true;
6b383a7f
CW		 2746 intel_update_watermarks(dev);
2747
63d7bbe9 2748 intel_enable_pll(dev_priv, pipe);
040484af 2749 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2750 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2751
0b8765c6 2752 intel_crtc_load_lut(crtc);
bed4a673 2753 intel_update_fbc(dev);
79e53945 2754
0b8765c6
JB		 2755 /* Give the overlay scaler a chance to enable if it's on this pipe */
2756 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2757 intel_crtc_update_cursor(crtc, true);
0b8765c6 2758}
79e53945 2759
0b8765c6
JB		 2760static void i9xx_crtc_disable(struct drm_crtc *crtc)
2761{
2762 struct drm_device *dev = crtc->dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765 int pipe = intel_crtc->pipe;
2766 int plane = intel_crtc->plane;
b690e96c 2767
f7abfe8b
CW		 2768 if (!intel_crtc->active)
2769 return;
2770
0b8765c6 2771 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2772 intel_crtc_wait_for_pending_flips(crtc);
2773 drm_vblank_off(dev, pipe);
0b8765c6 2774 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2775 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2776
2777 if (dev_priv->cfb_plane == plane &&
2778 dev_priv->display.disable_fbc)
2779 dev_priv->display.disable_fbc(dev);
79e53945 2780
b24e7179 2781 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2782 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2783 intel_disable_pll(dev_priv, pipe);
0b8765c6 2784
f7abfe8b 2785 intel_crtc->active = false;
6b383a7f
CW		 2786 intel_update_fbc(dev);
2787 intel_update_watermarks(dev);
2788 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2789}
2790
2791static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2792{
2793 /* XXX: When our outputs are all unaware of DPMS modes other than off
2794 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2795 */
2796 switch (mode) {
2797 case DRM_MODE_DPMS_ON:
2798 case DRM_MODE_DPMS_STANDBY:
2799 case DRM_MODE_DPMS_SUSPEND:
2800 i9xx_crtc_enable(crtc);
2801 break;
2802 case DRM_MODE_DPMS_OFF:
2803 i9xx_crtc_disable(crtc);
79e53945
JB		 2804 break;
2805 }
2c07245f
ZW		 2806}
2807
2808/**
2809 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2810 */
2811static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2812{
2813 struct drm_device *dev = crtc->dev;
e70236a8 2814 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2815 struct drm_i915_master_private *master_priv;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2818 bool enabled;
2819
032d2a0d
CW		 2820 if (intel_crtc->dpms_mode == mode)
2821 return;
2822
65655d4a 2823 intel_crtc->dpms_mode = mode;
debcaddc 2824
e70236a8 2825 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2826
2827 if (!dev->primary->master)
2828 return;
2829
2830 master_priv = dev->primary->master->driver_priv;
2831 if (!master_priv->sarea_priv)
2832 return;
2833
2834 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2835
2836 switch (pipe) {
2837 case 0:
2838 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2839 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2840 break;
2841 case 1:
2842 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2843 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2844 break;
2845 default:
9db4a9c7 2846 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2847 break;
2848 }
79e53945
JB		 2849}
2850
cdd59983
CW		 2851static void intel_crtc_disable(struct drm_crtc *crtc)
2852{
2853 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2854 struct drm_device *dev = crtc->dev;
2855
2856 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2857
2858 if (crtc->fb) {
2859 mutex_lock(&dev->struct_mutex);
2860 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2861 mutex_unlock(&dev->struct_mutex);
2862 }
2863}
2864
7e7d76c3
JB		 2865/* Prepare for a mode set.
2866 *
2867 * Note we could be a lot smarter here. We need to figure out which outputs
2868 * will be enabled, which disabled (in short, how the config will changes)
2869 * and perform the minimum necessary steps to accomplish that, e.g. updating
2870 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2871 * panel fitting is in the proper state, etc.
2872 */
2873static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2874{
7e7d76c3 2875 i9xx_crtc_disable(crtc);
79e53945
JB		 2876}
2877
7e7d76c3 2878static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 2879{
7e7d76c3 2880 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 2881}
2882
2883static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2884{
7e7d76c3 2885 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 2886}
2887
2888static void ironlake_crtc_commit(struct drm_crtc *crtc)
2889{
7e7d76c3 2890 ironlake_crtc_enable(crtc);
79e53945
JB		 2891}
2892
2893void intel_encoder_prepare (struct drm_encoder *encoder)
2894{
2895 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2896 /* lvds has its own version of prepare see intel_lvds_prepare */
2897 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2898}
2899
2900void intel_encoder_commit (struct drm_encoder *encoder)
2901{
2902 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2903 /* lvds has its own version of commit see intel_lvds_commit */
2904 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2905}
2906
ea5b213a
CW		 2907void intel_encoder_destroy(struct drm_encoder *encoder)
2908{
4ef69c7a 2909 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 2910
ea5b213a
CW		 2911 drm_encoder_cleanup(encoder);
2912 kfree(intel_encoder);
2913}
2914
79e53945
JB		 2915static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2916 struct drm_display_mode *mode,
2917 struct drm_display_mode *adjusted_mode)
2918{
2c07245f 2919 struct drm_device *dev = crtc->dev;
89749350 2920
bad720ff 2921 if (HAS_PCH_SPLIT(dev)) {
2c07245f 2922 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 2923 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2924 return false;
2c07245f 2925 }
89749350
CW		 2926
2927 /* XXX some encoders set the crtcinfo, others don't.
2928 * Obviously we need some form of conflict resolution here...
2929 */
2930 if (adjusted_mode->crtc_htotal == 0)
2931 drm_mode_set_crtcinfo(adjusted_mode, 0);
2932
79e53945
JB		 2933 return true;
2934}
2935
e70236a8
JB		 2936static int i945_get_display_clock_speed(struct drm_device *dev)
2937{
2938 return 400000;
2939}
79e53945 2940
e70236a8 2941static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 2942{
e70236a8
JB		 2943 return 333000;
2944}
79e53945 2945
e70236a8
JB		 2946static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2947{
2948 return 200000;
2949}
79e53945 2950
e70236a8
JB		 2951static int i915gm_get_display_clock_speed(struct drm_device *dev)
2952{
2953 u16 gcfgc = 0;
79e53945 2954
e70236a8
JB		 2955 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2956
2957 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2958 return 133000;
2959 else {
2960 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2961 case GC_DISPLAY_CLOCK_333_MHZ:
2962 return 333000;
2963 default:
2964 case GC_DISPLAY_CLOCK_190_200_MHZ:
2965 return 190000;
79e53945 2966 }
e70236a8
JB		 2967 }
2968}
2969
2970static int i865_get_display_clock_speed(struct drm_device *dev)
2971{
2972 return 266000;
2973}
2974
2975static int i855_get_display_clock_speed(struct drm_device *dev)
2976{
2977 u16 hpllcc = 0;
2978 /* Assume that the hardware is in the high speed state. This
2979 * should be the default.
2980 */
2981 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2982 case GC_CLOCK_133_200:
2983 case GC_CLOCK_100_200:
2984 return 200000;
2985 case GC_CLOCK_166_250:
2986 return 250000;
2987 case GC_CLOCK_100_133:
79e53945 2988 return 133000;
e70236a8 2989 }
79e53945 2990
e70236a8
JB		 2991 /* Shouldn't happen */
2992 return 0;
2993}
79e53945 2994
e70236a8
JB		 2995static int i830_get_display_clock_speed(struct drm_device *dev)
2996{
2997 return 133000;
79e53945
JB		 2998}
2999
2c07245f
ZW		 3000struct fdi_m_n {
3001 u32 tu;
3002 u32 gmch_m;
3003 u32 gmch_n;
3004 u32 link_m;
3005 u32 link_n;
3006};
3007
3008static void
3009fdi_reduce_ratio(u32 *num, u32 *den)
3010{
3011 while (*num > 0xffffff || *den > 0xffffff) {
3012 *num >>= 1;
3013 *den >>= 1;
3014 }
3015}
3016
2c07245f 3017static void
f2b115e6
AJ		 3018ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3019 int link_clock, struct fdi_m_n *m_n)
2c07245f 3020{
2c07245f
ZW		 3021 m_n->tu = 64; /* default size */
3022
22ed1113
CW		 3023 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3024 m_n->gmch_m = bits_per_pixel * pixel_clock;
3025 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3026 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3027
22ed1113
CW		 3028 m_n->link_m = pixel_clock;
3029 m_n->link_n = link_clock;
2c07245f
ZW		 3030 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3031}
3032
3033
7662c8bd
SL		 3034struct intel_watermark_params {
3035 unsigned long fifo_size;
3036 unsigned long max_wm;
3037 unsigned long default_wm;
3038 unsigned long guard_size;
3039 unsigned long cacheline_size;
3040};
3041
f2b115e6 3042/* Pineview has different values for various configs */
d210246a 3043static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3044 PINEVIEW_DISPLAY_FIFO,
3045 PINEVIEW_MAX_WM,
3046 PINEVIEW_DFT_WM,
3047 PINEVIEW_GUARD_WM,
3048 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3049};
d210246a 3050static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3051 PINEVIEW_DISPLAY_FIFO,
3052 PINEVIEW_MAX_WM,
3053 PINEVIEW_DFT_HPLLOFF_WM,
3054 PINEVIEW_GUARD_WM,
3055 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3056};
d210246a 3057static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3058 PINEVIEW_CURSOR_FIFO,
3059 PINEVIEW_CURSOR_MAX_WM,
3060 PINEVIEW_CURSOR_DFT_WM,
3061 PINEVIEW_CURSOR_GUARD_WM,
3062 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3063};
d210246a 3064static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3065 PINEVIEW_CURSOR_FIFO,
3066 PINEVIEW_CURSOR_MAX_WM,
3067 PINEVIEW_CURSOR_DFT_WM,
3068 PINEVIEW_CURSOR_GUARD_WM,
3069 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3070};
d210246a 3071static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3072 G4X_FIFO_SIZE,
3073 G4X_MAX_WM,
3074 G4X_MAX_WM,
3075 2,
3076 G4X_FIFO_LINE_SIZE,
3077};
d210246a 3078static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3079 I965_CURSOR_FIFO,
3080 I965_CURSOR_MAX_WM,
3081 I965_CURSOR_DFT_WM,
3082 2,
3083 G4X_FIFO_LINE_SIZE,
3084};
d210246a 3085static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3086 I965_CURSOR_FIFO,
3087 I965_CURSOR_MAX_WM,
3088 I965_CURSOR_DFT_WM,
3089 2,
3090 I915_FIFO_LINE_SIZE,
3091};
d210246a 3092static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3093 I945_FIFO_SIZE,
7662c8bd
SL		 3094 I915_MAX_WM,
3095 1,
dff33cfc
JB		 3096 2,
3097 I915_FIFO_LINE_SIZE
7662c8bd 3098};
d210246a 3099static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3100 I915_FIFO_SIZE,
7662c8bd
SL		 3101 I915_MAX_WM,
3102 1,
dff33cfc 3103 2,
7662c8bd
SL		 3104 I915_FIFO_LINE_SIZE
3105};
d210246a 3106static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3107 I855GM_FIFO_SIZE,
3108 I915_MAX_WM,
3109 1,
dff33cfc 3110 2,
7662c8bd
SL		 3111 I830_FIFO_LINE_SIZE
3112};
d210246a 3113static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3114 I830_FIFO_SIZE,
3115 I915_MAX_WM,
3116 1,
dff33cfc 3117 2,
7662c8bd
SL		 3118 I830_FIFO_LINE_SIZE
3119};
3120
d210246a 3121static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3122 ILK_DISPLAY_FIFO,
3123 ILK_DISPLAY_MAXWM,
3124 ILK_DISPLAY_DFTWM,
3125 2,
3126 ILK_FIFO_LINE_SIZE
3127};
d210246a 3128static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3129 ILK_CURSOR_FIFO,
3130 ILK_CURSOR_MAXWM,
3131 ILK_CURSOR_DFTWM,
3132 2,
3133 ILK_FIFO_LINE_SIZE
3134};
d210246a 3135static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3136 ILK_DISPLAY_SR_FIFO,
3137 ILK_DISPLAY_MAX_SRWM,
3138 ILK_DISPLAY_DFT_SRWM,
3139 2,
3140 ILK_FIFO_LINE_SIZE
3141};
d210246a 3142static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3143 ILK_CURSOR_SR_FIFO,
3144 ILK_CURSOR_MAX_SRWM,
3145 ILK_CURSOR_DFT_SRWM,
3146 2,
3147 ILK_FIFO_LINE_SIZE
3148};
3149
d210246a 3150static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3151 SNB_DISPLAY_FIFO,
3152 SNB_DISPLAY_MAXWM,
3153 SNB_DISPLAY_DFTWM,
3154 2,
3155 SNB_FIFO_LINE_SIZE
3156};
d210246a 3157static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3158 SNB_CURSOR_FIFO,
3159 SNB_CURSOR_MAXWM,
3160 SNB_CURSOR_DFTWM,
3161 2,
3162 SNB_FIFO_LINE_SIZE
3163};
d210246a 3164static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3165 SNB_DISPLAY_SR_FIFO,
3166 SNB_DISPLAY_MAX_SRWM,
3167 SNB_DISPLAY_DFT_SRWM,
3168 2,
3169 SNB_FIFO_LINE_SIZE
3170};
d210246a 3171static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3172 SNB_CURSOR_SR_FIFO,
3173 SNB_CURSOR_MAX_SRWM,
3174 SNB_CURSOR_DFT_SRWM,
3175 2,
3176 SNB_FIFO_LINE_SIZE
3177};
3178
3179
dff33cfc
JB		 3180/**
3181 * intel_calculate_wm - calculate watermark level
3182 * @clock_in_khz: pixel clock
3183 * @wm: chip FIFO params
3184 * @pixel_size: display pixel size
3185 * @latency_ns: memory latency for the platform
3186 *
3187 * Calculate the watermark level (the level at which the display plane will
3188 * start fetching from memory again). Each chip has a different display
3189 * FIFO size and allocation, so the caller needs to figure that out and pass
3190 * in the correct intel_watermark_params structure.
3191 *
3192 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3193 * on the pixel size. When it reaches the watermark level, it'll start
3194 * fetching FIFO line sized based chunks from memory until the FIFO fills
3195 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3196 * will occur, and a display engine hang could result.
3197 */
7662c8bd 3198static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3199 const struct intel_watermark_params *wm,
3200 int fifo_size,
7662c8bd
SL		 3201 int pixel_size,
3202 unsigned long latency_ns)
3203{
390c4dd4 3204 long entries_required, wm_size;
dff33cfc 3205
d660467c
JB		 3206 /*
3207 * Note: we need to make sure we don't overflow for various clock &
3208 * latency values.
3209 * clocks go from a few thousand to several hundred thousand.
3210 * latency is usually a few thousand
3211 */
3212 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3213 1000;
8de9b311 3214 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3215
28c97730 3216 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
dff33cfc 3217
d210246a 3218 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3219
28c97730 3220 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
7662c8bd 3221
390c4dd4
JB		 3222 /* Don't promote wm_size to unsigned... */
3223 if (wm_size > (long)wm->max_wm)
7662c8bd 3224 wm_size = wm->max_wm;
c3add4b6 3225 if (wm_size <= 0)
7662c8bd
SL		 3226 wm_size = wm->default_wm;
3227 return wm_size;
3228}
3229
3230struct cxsr_latency {
3231 int is_desktop;
95534263 3232 int is_ddr3;
7662c8bd
SL		 3233 unsigned long fsb_freq;
3234 unsigned long mem_freq;
3235 unsigned long display_sr;
3236 unsigned long display_hpll_disable;
3237 unsigned long cursor_sr;
3238 unsigned long cursor_hpll_disable;
3239};
3240
403c89ff 3241static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3242 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3243 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3244 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3245 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3246 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3247
3248 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3249 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3250 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3251 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3252 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3253
3254 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3255 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3256 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3257 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3258 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3259
3260 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3261 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3262 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3263 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3264 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3265
3266 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3267 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3268 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3269 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3270 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3271
3272 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3273 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3274 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3275 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3276 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3277};
3278
403c89ff
CW		 3279static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3280 int is_ddr3,
3281 int fsb,
3282 int mem)
7662c8bd 3283{
403c89ff 3284 const struct cxsr_latency *latency;
7662c8bd 3285 int i;
7662c8bd
SL		 3286
3287 if (fsb == 0 || mem == 0)
3288 return NULL;
3289
3290 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3291 latency = &cxsr_latency_table[i];
3292 if (is_desktop == latency->is_desktop &&
95534263 3293 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3294 fsb == latency->fsb_freq && mem == latency->mem_freq)
3295 return latency;
7662c8bd 3296 }
decbbcda 3297
28c97730 3298 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3299
3300 return NULL;
7662c8bd
SL		 3301}
3302
f2b115e6 3303static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3304{
3305 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3306
3307 /* deactivate cxsr */
3e33d94d 3308 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3309}
3310
bcc24fb4
JB		 3311/*
3312 * Latency for FIFO fetches is dependent on several factors:
3313 * - memory configuration (speed, channels)
3314 * - chipset
3315 * - current MCH state
3316 * It can be fairly high in some situations, so here we assume a fairly
3317 * pessimal value. It's a tradeoff between extra memory fetches (if we
3318 * set this value too high, the FIFO will fetch frequently to stay full)
3319 * and power consumption (set it too low to save power and we might see
3320 * FIFO underruns and display "flicker").
3321 *
3322 * A value of 5us seems to be a good balance; safe for very low end
3323 * platforms but not overly aggressive on lower latency configs.
3324 */
69e302a9 3325static const int latency_ns = 5000;
7662c8bd 3326
e70236a8 3327static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 uint32_t dsparb = I915_READ(DSPARB);
3331 int size;
3332
8de9b311
CW		 3333 size = dsparb & 0x7f;
3334 if (plane)
3335 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3336
28c97730 3337 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3338 plane ? "B" : "A", size);
dff33cfc
JB		 3339
3340 return size;
3341}
7662c8bd 3342
e70236a8
JB		 3343static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3344{
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346 uint32_t dsparb = I915_READ(DSPARB);
3347 int size;
3348
8de9b311
CW		 3349 size = dsparb & 0x1ff;
3350 if (plane)
3351 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3352 size >>= 1; /* Convert to cachelines */
dff33cfc 3353
28c97730 3354 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3355 plane ? "B" : "A", size);
dff33cfc
JB		 3356
3357 return size;
3358}
7662c8bd 3359
e70236a8
JB		 3360static int i845_get_fifo_size(struct drm_device *dev, int plane)
3361{
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 uint32_t dsparb = I915_READ(DSPARB);
3364 int size;
3365
3366 size = dsparb & 0x7f;
3367 size >>= 2; /* Convert to cachelines */
3368
28c97730 3369 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3370 plane ? "B" : "A",
3371 size);
e70236a8
JB		 3372
3373 return size;
3374}
3375
3376static int i830_get_fifo_size(struct drm_device *dev, int plane)
3377{
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 uint32_t dsparb = I915_READ(DSPARB);
3380 int size;
3381
3382 size = dsparb & 0x7f;
3383 size >>= 1; /* Convert to cachelines */
3384
28c97730 3385 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3386 plane ? "B" : "A", size);
e70236a8
JB		 3387
3388 return size;
3389}
3390
d210246a
CW		 3391static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3392{
3393 struct drm_crtc *crtc, *enabled = NULL;
3394
3395 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3396 if (crtc->enabled && crtc->fb) {
3397 if (enabled)
3398 return NULL;
3399 enabled = crtc;
3400 }
3401 }
3402
3403 return enabled;
3404}
3405
3406static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3407{
3408 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3409 struct drm_crtc *crtc;
403c89ff 3410 const struct cxsr_latency *latency;
d4294342
ZY		 3411 u32 reg;
3412 unsigned long wm;
d4294342 3413
403c89ff 3414 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3415 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3416 if (!latency) {
3417 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3418 pineview_disable_cxsr(dev);
3419 return;
3420 }
3421
d210246a
CW		 3422 crtc = single_enabled_crtc(dev);
3423 if (crtc) {
3424 int clock = crtc->mode.clock;
3425 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3426
3427 /* Display SR */
d210246a
CW		 3428 wm = intel_calculate_wm(clock, &pineview_display_wm,
3429 pineview_display_wm.fifo_size,
d4294342
ZY		 3430 pixel_size, latency->display_sr);
3431 reg = I915_READ(DSPFW1);
3432 reg &= ~DSPFW_SR_MASK;
3433 reg |= wm << DSPFW_SR_SHIFT;
3434 I915_WRITE(DSPFW1, reg);
3435 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3436
3437 /* cursor SR */
d210246a
CW		 3438 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3439 pineview_display_wm.fifo_size,
d4294342
ZY		 3440 pixel_size, latency->cursor_sr);
3441 reg = I915_READ(DSPFW3);
3442 reg &= ~DSPFW_CURSOR_SR_MASK;
3443 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3444 I915_WRITE(DSPFW3, reg);
3445
3446 /* Display HPLL off SR */
d210246a
CW		 3447 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3448 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3449 pixel_size, latency->display_hpll_disable);
3450 reg = I915_READ(DSPFW3);
3451 reg &= ~DSPFW_HPLL_SR_MASK;
3452 reg |= wm & DSPFW_HPLL_SR_MASK;
3453 I915_WRITE(DSPFW3, reg);
3454
3455 /* cursor HPLL off SR */
d210246a
CW		 3456 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3457 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3458 pixel_size, latency->cursor_hpll_disable);
3459 reg = I915_READ(DSPFW3);
3460 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3461 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3462 I915_WRITE(DSPFW3, reg);
3463 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3464
3465 /* activate cxsr */
3e33d94d
CW		 3466 I915_WRITE(DSPFW3,
3467 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3468 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3469 } else {
3470 pineview_disable_cxsr(dev);
3471 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3472 }
3473}
3474
417ae147
CW		 3475static bool g4x_compute_wm0(struct drm_device *dev,
3476 int plane,
3477 const struct intel_watermark_params *display,
3478 int display_latency_ns,
3479 const struct intel_watermark_params *cursor,
3480 int cursor_latency_ns,
3481 int *plane_wm,
3482 int *cursor_wm)
3483{
3484 struct drm_crtc *crtc;
3485 int htotal, hdisplay, clock, pixel_size;
3486 int line_time_us, line_count;
3487 int entries, tlb_miss;
3488
3489 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3490 if (crtc->fb == NULL || !crtc->enabled) {
3491 *cursor_wm = cursor->guard_size;
3492 *plane_wm = display->guard_size;
417ae147 3493 return false;
5c72d064 3494 }
417ae147
CW		 3495
3496 htotal = crtc->mode.htotal;
3497 hdisplay = crtc->mode.hdisplay;
3498 clock = crtc->mode.clock;
3499 pixel_size = crtc->fb->bits_per_pixel / 8;
3500
3501 /* Use the small buffer method to calculate plane watermark */
3502 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3503 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3504 if (tlb_miss > 0)
3505 entries += tlb_miss;
3506 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3507 *plane_wm = entries + display->guard_size;
3508 if (*plane_wm > (int)display->max_wm)
3509 *plane_wm = display->max_wm;
3510
3511 /* Use the large buffer method to calculate cursor watermark */
3512 line_time_us = ((htotal * 1000) / clock);
3513 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3514 entries = line_count * 64 * pixel_size;
3515 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3516 if (tlb_miss > 0)
3517 entries += tlb_miss;
3518 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3519 *cursor_wm = entries + cursor->guard_size;
3520 if (*cursor_wm > (int)cursor->max_wm)
3521 *cursor_wm = (int)cursor->max_wm;
3522
3523 return true;
3524}
3525
3526/*
3527 * Check the wm result.
3528 *
3529 * If any calculated watermark values is larger than the maximum value that
3530 * can be programmed into the associated watermark register, that watermark
3531 * must be disabled.
3532 */
3533static bool g4x_check_srwm(struct drm_device *dev,
3534 int display_wm, int cursor_wm,
3535 const struct intel_watermark_params *display,
3536 const struct intel_watermark_params *cursor)
652c393a 3537{
417ae147
CW		 3538 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3539 display_wm, cursor_wm);
652c393a 3540
417ae147
CW		 3541 if (display_wm > display->max_wm) {
3542 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3543 display_wm, display->max_wm);
3544 return false;
3545 }
0e442c60 3546
417ae147
CW		 3547 if (cursor_wm > cursor->max_wm) {
3548 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3549 cursor_wm, cursor->max_wm);
3550 return false;
3551 }
0e442c60 3552
417ae147
CW		 3553 if (!(display_wm || cursor_wm)) {
3554 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3555 return false;
3556 }
0e442c60 3557
417ae147
CW		 3558 return true;
3559}
0e442c60 3560
417ae147 3561static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3562 int plane,
3563 int latency_ns,
417ae147
CW		 3564 const struct intel_watermark_params *display,
3565 const struct intel_watermark_params *cursor,
3566 int *display_wm, int *cursor_wm)
3567{
d210246a
CW		 3568 struct drm_crtc *crtc;
3569 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3570 unsigned long line_time_us;
3571 int line_count, line_size;
3572 int small, large;
3573 int entries;
0e442c60 3574
417ae147
CW		 3575 if (!latency_ns) {
3576 *display_wm = *cursor_wm = 0;
3577 return false;
3578 }
0e442c60 3579
d210246a
CW		 3580 crtc = intel_get_crtc_for_plane(dev, plane);
3581 hdisplay = crtc->mode.hdisplay;
3582 htotal = crtc->mode.htotal;
3583 clock = crtc->mode.clock;
3584 pixel_size = crtc->fb->bits_per_pixel / 8;
3585
417ae147
CW		 3586 line_time_us = (htotal * 1000) / clock;
3587 line_count = (latency_ns / line_time_us + 1000) / 1000;
3588 line_size = hdisplay * pixel_size;
0e442c60 3589
417ae147
CW		 3590 /* Use the minimum of the small and large buffer method for primary */
3591 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3592 large = line_count * line_size;
0e442c60 3593
417ae147
CW		 3594 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3595 *display_wm = entries + display->guard_size;
4fe5e611 3596
417ae147
CW		 3597 /* calculate the self-refresh watermark for display cursor */
3598 entries = line_count * pixel_size * 64;
3599 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3600 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3601
417ae147
CW		 3602 return g4x_check_srwm(dev,
3603 *display_wm, *cursor_wm,
3604 display, cursor);
3605}
4fe5e611 3606
7ccb4a53 3607#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3608
3609static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3610{
3611 static const int sr_latency_ns = 12000;
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3614 int plane_sr, cursor_sr;
3615 unsigned int enabled = 0;
417ae147
CW		 3616
3617 if (g4x_compute_wm0(dev, 0,
3618 &g4x_wm_info, latency_ns,
3619 &g4x_cursor_wm_info, latency_ns,
3620 &planea_wm, &cursora_wm))
d210246a 3621 enabled |= 1;
417ae147
CW		 3622
3623 if (g4x_compute_wm0(dev, 1,
3624 &g4x_wm_info, latency_ns,
3625 &g4x_cursor_wm_info, latency_ns,
3626 &planeb_wm, &cursorb_wm))
d210246a 3627 enabled |= 2;
417ae147
CW		 3628
3629 plane_sr = cursor_sr = 0;
d210246a
CW		 3630 if (single_plane_enabled(enabled) &&
3631 g4x_compute_srwm(dev, ffs(enabled) - 1,
3632 sr_latency_ns,
417ae147
CW		 3633 &g4x_wm_info,
3634 &g4x_cursor_wm_info,
3635 &plane_sr, &cursor_sr))
0e442c60 3636 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3637 else
3638 I915_WRITE(FW_BLC_SELF,
3639 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3640
308977ac
CW		 3641 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3642 planea_wm, cursora_wm,
3643 planeb_wm, cursorb_wm,
3644 plane_sr, cursor_sr);
0e442c60 3645
417ae147
CW		 3646 I915_WRITE(DSPFW1,
3647 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3648 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3649 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3650 planea_wm);
3651 I915_WRITE(DSPFW2,
3652 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3653 (cursora_wm << DSPFW_CURSORA_SHIFT));
3654 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3655 I915_WRITE(DSPFW3,
3656 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3657 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3658}
3659
d210246a 3660static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3661{
3662 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3663 struct drm_crtc *crtc;
3664 int srwm = 1;
4fe5e611 3665 int cursor_sr = 16;
1dc7546d
JB		 3666
3667 /* Calc sr entries for one plane configs */
d210246a
CW		 3668 crtc = single_enabled_crtc(dev);
3669 if (crtc) {
1dc7546d 3670 /* self-refresh has much higher latency */
69e302a9 3671 static const int sr_latency_ns = 12000;
d210246a
CW		 3672 int clock = crtc->mode.clock;
3673 int htotal = crtc->mode.htotal;
3674 int hdisplay = crtc->mode.hdisplay;
3675 int pixel_size = crtc->fb->bits_per_pixel / 8;
3676 unsigned long line_time_us;
3677 int entries;
1dc7546d 3678
d210246a 3679 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3680
3681 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3682 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3683 pixel_size * hdisplay;
3684 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3685 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3686 if (srwm < 0)
3687 srwm = 1;
1b07e04e 3688 srwm &= 0x1ff;
308977ac
CW		 3689 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3690 entries, srwm);
4fe5e611 3691
d210246a 3692 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3693 pixel_size * 64;
d210246a 3694 entries = DIV_ROUND_UP(entries,
8de9b311 3695 i965_cursor_wm_info.cacheline_size);
4fe5e611 3696 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3697 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3698
3699 if (cursor_sr > i965_cursor_wm_info.max_wm)
3700 cursor_sr = i965_cursor_wm_info.max_wm;
3701
3702 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3703 "cursor %d\n", srwm, cursor_sr);
3704
a6c45cf0 3705 if (IS_CRESTLINE(dev))
adcdbc66 3706 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3707 } else {
3708 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3709 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3710 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3711 & ~FW_BLC_SELF_EN);
1dc7546d 3712 }
7662c8bd 3713
1dc7546d
JB		 3714 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3715 srwm);
7662c8bd
SL		 3716
3717 /* 965 has limitations... */
417ae147
CW		 3718 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3719 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3720 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3721 /* update cursor SR watermark */
3722 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3723}
3724
d210246a 3725static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3726{
3727 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3728 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3729 uint32_t fwater_lo;
3730 uint32_t fwater_hi;
d210246a
CW		 3731 int cwm, srwm = 1;
3732 int fifo_size;
dff33cfc 3733 int planea_wm, planeb_wm;
d210246a 3734 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3735
72557b4f 3736 if (IS_I945GM(dev))
d210246a 3737 wm_info = &i945_wm_info;
a6c45cf0 3738 else if (!IS_GEN2(dev))
d210246a 3739 wm_info = &i915_wm_info;
7662c8bd 3740 else
d210246a
CW		 3741 wm_info = &i855_wm_info;
3742
3743 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3744 crtc = intel_get_crtc_for_plane(dev, 0);
3745 if (crtc->enabled && crtc->fb) {
3746 planea_wm = intel_calculate_wm(crtc->mode.clock,
3747 wm_info, fifo_size,
3748 crtc->fb->bits_per_pixel / 8,
3749 latency_ns);
3750 enabled = crtc;
3751 } else
3752 planea_wm = fifo_size - wm_info->guard_size;
3753
3754 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3755 crtc = intel_get_crtc_for_plane(dev, 1);
3756 if (crtc->enabled && crtc->fb) {
3757 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3758 wm_info, fifo_size,
3759 crtc->fb->bits_per_pixel / 8,
3760 latency_ns);
3761 if (enabled == NULL)
3762 enabled = crtc;
3763 else
3764 enabled = NULL;
3765 } else
3766 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3767
28c97730 3768 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3769
3770 /*
3771 * Overlay gets an aggressive default since video jitter is bad.
3772 */
3773 cwm = 2;
3774
18b2190c
AL		 3775 /* Play safe and disable self-refresh before adjusting watermarks. */
3776 if (IS_I945G(dev) || IS_I945GM(dev))
3777 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3778 else if (IS_I915GM(dev))
3779 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3780
dff33cfc 3781 /* Calc sr entries for one plane configs */
d210246a 3782 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3783 /* self-refresh has much higher latency */
69e302a9 3784 static const int sr_latency_ns = 6000;
d210246a
CW		 3785 int clock = enabled->mode.clock;
3786 int htotal = enabled->mode.htotal;
3787 int hdisplay = enabled->mode.hdisplay;
3788 int pixel_size = enabled->fb->bits_per_pixel / 8;
3789 unsigned long line_time_us;
3790 int entries;
dff33cfc 3791
d210246a 3792 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3793
3794 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3795 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3796 pixel_size * hdisplay;
3797 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3798 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3799 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3800 if (srwm < 0)
3801 srwm = 1;
ee980b80
LP		 3802
3803 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3804 I915_WRITE(FW_BLC_SELF,
3805 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3806 else if (IS_I915GM(dev))
ee980b80 3807 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3808 }
3809
28c97730 3810 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3811 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3812
dff33cfc
JB		 3813 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3814 fwater_hi = (cwm & 0x1f);
3815
3816 /* Set request length to 8 cachelines per fetch */
3817 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3818 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3819
3820 I915_WRITE(FW_BLC, fwater_lo);
3821 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3822
d210246a
CW		 3823 if (HAS_FW_BLC(dev)) {
3824 if (enabled) {
3825 if (IS_I945G(dev) || IS_I945GM(dev))
3826 I915_WRITE(FW_BLC_SELF,
3827 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3828 else if (IS_I915GM(dev))
3829 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3830 DRM_DEBUG_KMS("memory self refresh enabled\n");
3831 } else
3832 DRM_DEBUG_KMS("memory self refresh disabled\n");
3833 }
7662c8bd
SL		 3834}
3835
d210246a 3836static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3837{
3838 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3839 struct drm_crtc *crtc;
3840 uint32_t fwater_lo;
dff33cfc 3841 int planea_wm;
7662c8bd 3842
d210246a
CW		 3843 crtc = single_enabled_crtc(dev);
3844 if (crtc == NULL)
3845 return;
7662c8bd 3846
d210246a
CW		 3847 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3848 dev_priv->display.get_fifo_size(dev, 0),
3849 crtc->fb->bits_per_pixel / 8,
3850 latency_ns);
3851 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 3852 fwater_lo |= (3<<8) | planea_wm;
3853
28c97730 3854 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 3855
3856 I915_WRITE(FW_BLC, fwater_lo);
3857}
3858
7f8a8569 3859#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3860#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3861
4ed765f9
CW		 3862static bool ironlake_compute_wm0(struct drm_device *dev,
3863 int pipe,
1398261a 3864 const struct intel_watermark_params *display,
a0fa62d3 3865 int display_latency_ns,
1398261a 3866 const struct intel_watermark_params *cursor,
a0fa62d3 3867 int cursor_latency_ns,
4ed765f9
CW		 3868 int *plane_wm,
3869 int *cursor_wm)
7f8a8569 3870{
c936f44d 3871 struct drm_crtc *crtc;
db66e37d
CW		 3872 int htotal, hdisplay, clock, pixel_size;
3873 int line_time_us, line_count;
3874 int entries, tlb_miss;
c936f44d 3875
4ed765f9
CW		 3876 crtc = intel_get_crtc_for_pipe(dev, pipe);
3877 if (crtc->fb == NULL || !crtc->enabled)
3878 return false;
7f8a8569 3879
4ed765f9
CW		 3880 htotal = crtc->mode.htotal;
3881 hdisplay = crtc->mode.hdisplay;
3882 clock = crtc->mode.clock;
3883 pixel_size = crtc->fb->bits_per_pixel / 8;
3884
3885 /* Use the small buffer method to calculate plane watermark */
a0fa62d3 3886 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
db66e37d
CW		 3887 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3888 if (tlb_miss > 0)
3889 entries += tlb_miss;
1398261a
YL		 3890 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3891 *plane_wm = entries + display->guard_size;
3892 if (*plane_wm > (int)display->max_wm)
3893 *plane_wm = display->max_wm;
4ed765f9
CW		 3894
3895 /* Use the large buffer method to calculate cursor watermark */
3896 line_time_us = ((htotal * 1000) / clock);
a0fa62d3 3897 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4ed765f9 3898 entries = line_count * 64 * pixel_size;
db66e37d
CW		 3899 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3900 if (tlb_miss > 0)
3901 entries += tlb_miss;
1398261a
YL		 3902 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3903 *cursor_wm = entries + cursor->guard_size;
3904 if (*cursor_wm > (int)cursor->max_wm)
3905 *cursor_wm = (int)cursor->max_wm;
7f8a8569 3906
4ed765f9
CW		 3907 return true;
3908}
c936f44d 3909
1398261a
YL		 3910/*
3911 * Check the wm result.
3912 *
3913 * If any calculated watermark values is larger than the maximum value that
3914 * can be programmed into the associated watermark register, that watermark
3915 * must be disabled.
1398261a 3916 */
b79d4990
JB		 3917static bool ironlake_check_srwm(struct drm_device *dev, int level,
3918 int fbc_wm, int display_wm, int cursor_wm,
3919 const struct intel_watermark_params *display,
3920 const struct intel_watermark_params *cursor)
1398261a
YL		 3921{
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923
3924 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3925 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3926
3927 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3928 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3929 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 3930
3931 /* fbc has it's own way to disable FBC WM */
3932 I915_WRITE(DISP_ARB_CTL,
3933 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3934 return false;
3935 }
3936
b79d4990 3937 if (display_wm > display->max_wm) {
1398261a 3938 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3939 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 3940 return false;
3941 }
3942
b79d4990 3943 if (cursor_wm > cursor->max_wm) {
1398261a 3944 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3945 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 3946 return false;
3947 }
3948
3949 if (!(fbc_wm || display_wm || cursor_wm)) {
3950 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3951 return false;
3952 }
3953
3954 return true;
3955}
3956
3957/*
3958 * Compute watermark values of WM[1-3],
3959 */
d210246a
CW		 3960static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
3961 int latency_ns,
b79d4990
JB		 3962 const struct intel_watermark_params *display,
3963 const struct intel_watermark_params *cursor,
3964 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 3965{
d210246a 3966 struct drm_crtc *crtc;
1398261a 3967 unsigned long line_time_us;
d210246a 3968 int hdisplay, htotal, pixel_size, clock;
b79d4990 3969 int line_count, line_size;
1398261a
YL		 3970 int small, large;
3971 int entries;
1398261a
YL		 3972
3973 if (!latency_ns) {
3974 *fbc_wm = *display_wm = *cursor_wm = 0;
3975 return false;
3976 }
3977
d210246a
CW		 3978 crtc = intel_get_crtc_for_plane(dev, plane);
3979 hdisplay = crtc->mode.hdisplay;
3980 htotal = crtc->mode.htotal;
3981 clock = crtc->mode.clock;
3982 pixel_size = crtc->fb->bits_per_pixel / 8;
3983
1398261a
YL		 3984 line_time_us = (htotal * 1000) / clock;
3985 line_count = (latency_ns / line_time_us + 1000) / 1000;
3986 line_size = hdisplay * pixel_size;
3987
3988 /* Use the minimum of the small and large buffer method for primary */
3989 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3990 large = line_count * line_size;
3991
b79d4990
JB		 3992 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3993 *display_wm = entries + display->guard_size;
1398261a
YL		 3994
3995 /*
b79d4990 3996 * Spec says:
1398261a
YL		 3997 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3998 */
3999 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4000
4001 /* calculate the self-refresh watermark for display cursor */
4002 entries = line_count * pixel_size * 64;
b79d4990
JB		 4003 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4004 *cursor_wm = entries + cursor->guard_size;
1398261a 4005
b79d4990
JB		 4006 return ironlake_check_srwm(dev, level,
4007 *fbc_wm, *display_wm, *cursor_wm,
4008 display, cursor);
4009}
4010
d210246a 4011static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4012{
4013 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4014 int fbc_wm, plane_wm, cursor_wm;
4015 unsigned int enabled;
b79d4990
JB		 4016
4017 enabled = 0;
4018 if (ironlake_compute_wm0(dev, 0,
4019 &ironlake_display_wm_info,
4020 ILK_LP0_PLANE_LATENCY,
4021 &ironlake_cursor_wm_info,
4022 ILK_LP0_CURSOR_LATENCY,
4023 &plane_wm, &cursor_wm)) {
4024 I915_WRITE(WM0_PIPEA_ILK,
4025 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4026 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4027 " plane %d, " "cursor: %d\n",
4028 plane_wm, cursor_wm);
d210246a 4029 enabled |= 1;
b79d4990
JB		 4030 }
4031
4032 if (ironlake_compute_wm0(dev, 1,
4033 &ironlake_display_wm_info,
4034 ILK_LP0_PLANE_LATENCY,
4035 &ironlake_cursor_wm_info,
4036 ILK_LP0_CURSOR_LATENCY,
4037 &plane_wm, &cursor_wm)) {
4038 I915_WRITE(WM0_PIPEB_ILK,
4039 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4040 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4041 " plane %d, cursor: %d\n",
4042 plane_wm, cursor_wm);
d210246a 4043 enabled |= 2;
b79d4990
JB		 4044 }
4045
4046 /*
4047 * Calculate and update the self-refresh watermark only when one
4048 * display plane is used.
4049 */
4050 I915_WRITE(WM3_LP_ILK, 0);
4051 I915_WRITE(WM2_LP_ILK, 0);
4052 I915_WRITE(WM1_LP_ILK, 0);
4053
d210246a 4054 if (!single_plane_enabled(enabled))
b79d4990 4055 return;
d210246a 4056 enabled = ffs(enabled) - 1;
b79d4990
JB		 4057
4058 /* WM1 */
d210246a
CW		 4059 if (!ironlake_compute_srwm(dev, 1, enabled,
4060 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4061 &ironlake_display_srwm_info,
4062 &ironlake_cursor_srwm_info,
4063 &fbc_wm, &plane_wm, &cursor_wm))
4064 return;
4065
4066 I915_WRITE(WM1_LP_ILK,
4067 WM1_LP_SR_EN |
4068 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4069 (fbc_wm << WM1_LP_FBC_SHIFT) |
4070 (plane_wm << WM1_LP_SR_SHIFT) |
4071 cursor_wm);
4072
4073 /* WM2 */
d210246a
CW		 4074 if (!ironlake_compute_srwm(dev, 2, enabled,
4075 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4076 &ironlake_display_srwm_info,
4077 &ironlake_cursor_srwm_info,
4078 &fbc_wm, &plane_wm, &cursor_wm))
4079 return;
4080
4081 I915_WRITE(WM2_LP_ILK,
4082 WM2_LP_EN |
4083 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4084 (fbc_wm << WM1_LP_FBC_SHIFT) |
4085 (plane_wm << WM1_LP_SR_SHIFT) |
4086 cursor_wm);
4087
4088 /*
4089 * WM3 is unsupported on ILK, probably because we don't have latency
4090 * data for that power state
4091 */
1398261a
YL		 4092}
4093
d210246a 4094static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4095{
4096 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4097 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4098 int fbc_wm, plane_wm, cursor_wm;
4099 unsigned int enabled;
1398261a
YL		 4100
4101 enabled = 0;
4102 if (ironlake_compute_wm0(dev, 0,
4103 &sandybridge_display_wm_info, latency,
4104 &sandybridge_cursor_wm_info, latency,
4105 &plane_wm, &cursor_wm)) {
4106 I915_WRITE(WM0_PIPEA_ILK,
4107 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4108 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4109 " plane %d, " "cursor: %d\n",
4110 plane_wm, cursor_wm);
d210246a 4111 enabled |= 1;
1398261a
YL		 4112 }
4113
4114 if (ironlake_compute_wm0(dev, 1,
4115 &sandybridge_display_wm_info, latency,
4116 &sandybridge_cursor_wm_info, latency,
4117 &plane_wm, &cursor_wm)) {
4118 I915_WRITE(WM0_PIPEB_ILK,
4119 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4120 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4121 " plane %d, cursor: %d\n",
4122 plane_wm, cursor_wm);
d210246a 4123 enabled |= 2;
1398261a
YL		 4124 }
4125
4126 /*
4127 * Calculate and update the self-refresh watermark only when one
4128 * display plane is used.
4129 *
4130 * SNB support 3 levels of watermark.
4131 *
4132 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4133 * and disabled in the descending order
4134 *
4135 */
4136 I915_WRITE(WM3_LP_ILK, 0);
4137 I915_WRITE(WM2_LP_ILK, 0);
4138 I915_WRITE(WM1_LP_ILK, 0);
4139
d210246a 4140 if (!single_plane_enabled(enabled))
1398261a 4141 return;
d210246a 4142 enabled = ffs(enabled) - 1;
1398261a
YL		 4143
4144 /* WM1 */
d210246a
CW		 4145 if (!ironlake_compute_srwm(dev, 1, enabled,
4146 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4147 &sandybridge_display_srwm_info,
4148 &sandybridge_cursor_srwm_info,
4149 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4150 return;
4151
4152 I915_WRITE(WM1_LP_ILK,
4153 WM1_LP_SR_EN |
4154 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4155 (fbc_wm << WM1_LP_FBC_SHIFT) |
4156 (plane_wm << WM1_LP_SR_SHIFT) |
4157 cursor_wm);
4158
4159 /* WM2 */
d210246a
CW		 4160 if (!ironlake_compute_srwm(dev, 2, enabled,
4161 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4162 &sandybridge_display_srwm_info,
4163 &sandybridge_cursor_srwm_info,
4164 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4165 return;
4166
4167 I915_WRITE(WM2_LP_ILK,
4168 WM2_LP_EN |
4169 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4170 (fbc_wm << WM1_LP_FBC_SHIFT) |
4171 (plane_wm << WM1_LP_SR_SHIFT) |
4172 cursor_wm);
4173
4174 /* WM3 */
d210246a
CW		 4175 if (!ironlake_compute_srwm(dev, 3, enabled,
4176 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4177 &sandybridge_display_srwm_info,
4178 &sandybridge_cursor_srwm_info,
4179 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4180 return;
4181
4182 I915_WRITE(WM3_LP_ILK,
4183 WM3_LP_EN |
4184 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4185 (fbc_wm << WM1_LP_FBC_SHIFT) |
4186 (plane_wm << WM1_LP_SR_SHIFT) |
4187 cursor_wm);
4188}
4189
7662c8bd
SL		 4190/**
4191 * intel_update_watermarks - update FIFO watermark values based on current modes
4192 *
4193 * Calculate watermark values for the various WM regs based on current mode
4194 * and plane configuration.
4195 *
4196 * There are several cases to deal with here:
4197 * - normal (i.e. non-self-refresh)
4198 * - self-refresh (SR) mode
4199 * - lines are large relative to FIFO size (buffer can hold up to 2)
4200 * - lines are small relative to FIFO size (buffer can hold more than 2
4201 * lines), so need to account for TLB latency
4202 *
4203 * The normal calculation is:
4204 * watermark = dotclock * bytes per pixel * latency
4205 * where latency is platform & configuration dependent (we assume pessimal
4206 * values here).
4207 *
4208 * The SR calculation is:
4209 * watermark = (trunc(latency/line time)+1) * surface width *
4210 * bytes per pixel
4211 * where
4212 * line time = htotal / dotclock
fa143215 4213 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4214 * and latency is assumed to be high, as above.
4215 *
4216 * The final value programmed to the register should always be rounded up,
4217 * and include an extra 2 entries to account for clock crossings.
4218 *
4219 * We don't use the sprite, so we can ignore that. And on Crestline we have
4220 * to set the non-SR watermarks to 8.
5eddb70b 4221 */
7662c8bd
SL		 4222static void intel_update_watermarks(struct drm_device *dev)
4223{
e70236a8 4224 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4225
d210246a
CW		 4226 if (dev_priv->display.update_wm)
4227 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4228}
4229
a7615030
CW		 4230static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4231{
4232 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4233}
4234
f564048e
EA		 4235static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4236 struct drm_display_mode *mode,
4237 struct drm_display_mode *adjusted_mode,
4238 int x, int y,
4239 struct drm_framebuffer *old_fb)
4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 int pipe = intel_crtc->pipe;
4245 int plane = intel_crtc->plane;
f564048e
EA		 4246 int refclk, num_connectors = 0;
4247 intel_clock_t clock, reduced_clock;
4248 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4249 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4250 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
f564048e
EA		 4251 struct drm_mode_config *mode_config = &dev->mode_config;
4252 struct intel_encoder *encoder;
4253 const intel_limit_t *limit;
4254 int ret;
fae14981 4255 u32 temp;
f564048e 4256 u32 lvds_sync = 0;
f564048e 4257
f564048e
EA		 4258 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4259 if (encoder->base.crtc != crtc)
4260 continue;
4261
4262 switch (encoder->type) {
4263 case INTEL_OUTPUT_LVDS:
4264 is_lvds = true;
4265 break;
4266 case INTEL_OUTPUT_SDVO:
4267 case INTEL_OUTPUT_HDMI:
4268 is_sdvo = true;
4269 if (encoder->needs_tv_clock)
4270 is_tv = true;
4271 break;
4272 case INTEL_OUTPUT_DVO:
4273 is_dvo = true;
4274 break;
4275 case INTEL_OUTPUT_TVOUT:
4276 is_tv = true;
4277 break;
4278 case INTEL_OUTPUT_ANALOG:
4279 is_crt = true;
4280 break;
4281 case INTEL_OUTPUT_DISPLAYPORT:
4282 is_dp = true;
4283 break;
f564048e
EA		 4284 }
4285
4286 num_connectors++;
4287 }
4288
4289 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4290 refclk = dev_priv->lvds_ssc_freq * 1000;
4291 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4292 refclk / 1000);
4293 } else if (!IS_GEN2(dev)) {
4294 refclk = 96000;
f564048e
EA		 4295 } else {
4296 refclk = 48000;
4297 }
4298
4299 /*
4300 * Returns a set of divisors for the desired target clock with the given
4301 * refclk, or FALSE. The returned values represent the clock equation:
4302 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4303 */
4304 limit = intel_limit(crtc, refclk);
4305 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4306 if (!ok) {
4307 DRM_ERROR("Couldn't find PLL settings for mode!\n");
f564048e
EA		 4308 return -EINVAL;
4309 }
4310
4311 /* Ensure that the cursor is valid for the new mode before changing... */
4312 intel_crtc_update_cursor(crtc, true);
4313
4314 if (is_lvds && dev_priv->lvds_downclock_avail) {
4315 has_reduced_clock = limit->find_pll(limit, crtc,
4316 dev_priv->lvds_downclock,
4317 refclk,
4318 &reduced_clock);
4319 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4320 /*
4321 * If the different P is found, it means that we can't
4322 * switch the display clock by using the FP0/FP1.
4323 * In such case we will disable the LVDS downclock
4324 * feature.
4325 */
4326 DRM_DEBUG_KMS("Different P is found for "
4327 "LVDS clock/downclock\n");
4328 has_reduced_clock = 0;
4329 }
4330 }
4331 /* SDVO TV has fixed PLL values depend on its clock range,
4332 this mirrors vbios setting. */
4333 if (is_sdvo && is_tv) {
4334 if (adjusted_mode->clock >= 100000
4335 && adjusted_mode->clock < 140500) {
4336 clock.p1 = 2;
4337 clock.p2 = 10;
4338 clock.n = 3;
4339 clock.m1 = 16;
4340 clock.m2 = 8;
4341 } else if (adjusted_mode->clock >= 140500
4342 && adjusted_mode->clock <= 200000) {
4343 clock.p1 = 1;
4344 clock.p2 = 10;
4345 clock.n = 6;
4346 clock.m1 = 12;
4347 clock.m2 = 8;
4348 }
4349 }
4350
f564048e
EA		 4351 if (IS_PINEVIEW(dev)) {
4352 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4353 if (has_reduced_clock)
4354 fp2 = (1 << reduced_clock.n) << 16 |
4355 reduced_clock.m1 << 8 | reduced_clock.m2;
4356 } else {
4357 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4358 if (has_reduced_clock)
4359 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4360 reduced_clock.m2;
4361 }
4362
929c77fb 4363 dpll = DPLL_VGA_MODE_DIS;
f564048e
EA		 4364
4365 if (!IS_GEN2(dev)) {
4366 if (is_lvds)
4367 dpll |= DPLLB_MODE_LVDS;
4368 else
4369 dpll |= DPLLB_MODE_DAC_SERIAL;
4370 if (is_sdvo) {
4371 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4372 if (pixel_multiplier > 1) {
4373 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4374 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
f564048e
EA		 4375 }
4376 dpll |= DPLL_DVO_HIGH_SPEED;
4377 }
929c77fb 4378 if (is_dp)
f564048e
EA		 4379 dpll |= DPLL_DVO_HIGH_SPEED;
4380
4381 /* compute bitmask from p1 value */
4382 if (IS_PINEVIEW(dev))
4383 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4384 else {
4385 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
f564048e
EA		 4386 if (IS_G4X(dev) && has_reduced_clock)
4387 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4388 }
4389 switch (clock.p2) {
4390 case 5:
4391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4392 break;
4393 case 7:
4394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4395 break;
4396 case 10:
4397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4398 break;
4399 case 14:
4400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4401 break;
4402 }
929c77fb 4403 if (INTEL_INFO(dev)->gen >= 4)
f564048e
EA		 4404 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4405 } else {
4406 if (is_lvds) {
4407 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4408 } else {
4409 if (clock.p1 == 2)
4410 dpll |= PLL_P1_DIVIDE_BY_TWO;
4411 else
4412 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4413 if (clock.p2 == 4)
4414 dpll |= PLL_P2_DIVIDE_BY_4;
4415 }
4416 }
4417
4418 if (is_sdvo && is_tv)
4419 dpll |= PLL_REF_INPUT_TVCLKINBC;
4420 else if (is_tv)
4421 /* XXX: just matching BIOS for now */
4422 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4423 dpll |= 3;
4424 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4425 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4426 else
4427 dpll |= PLL_REF_INPUT_DREFCLK;
4428
4429 /* setup pipeconf */
4430 pipeconf = I915_READ(PIPECONF(pipe));
4431
4432 /* Set up the display plane register */
4433 dspcntr = DISPPLANE_GAMMA_ENABLE;
4434
4435 /* Ironlake's plane is forced to pipe, bit 24 is to
4436 enable color space conversion */
929c77fb
EA		 4437 if (pipe == 0)
4438 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4439 else
4440 dspcntr |= DISPPLANE_SEL_PIPE_B;
f564048e
EA		 4441
4442 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4443 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4444 * core speed.
4445 *
4446 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4447 * pipe == 0 check?
4448 */
4449 if (mode->clock >
4450 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4451 pipeconf |= PIPECONF_DOUBLE_WIDE;
4452 else
4453 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4454 }
4455
929c77fb 4456 dpll |= DPLL_VCO_ENABLE;
f564048e
EA		 4457
4458 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4459 drm_mode_debug_printmodeline(mode);
4460
fae14981
EA		 4461 I915_WRITE(FP0(pipe), fp);
4462 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
f564048e 4463
fae14981 4464 POSTING_READ(DPLL(pipe));
c713bb08 4465 udelay(150);
f564048e 4466
f564048e
EA		 4467 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4468 * This is an exception to the general rule that mode_set doesn't turn
4469 * things on.
4470 */
4471 if (is_lvds) {
fae14981 4472 temp = I915_READ(LVDS);
f564048e
EA		 4473 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4474 if (pipe == 1) {
929c77fb 4475 temp |= LVDS_PIPEB_SELECT;
f564048e 4476 } else {
929c77fb 4477 temp &= ~LVDS_PIPEB_SELECT;
f564048e
EA		 4478 }
4479 /* set the corresponsding LVDS_BORDER bit */
4480 temp |= dev_priv->lvds_border_bits;
4481 /* Set the B0-B3 data pairs corresponding to whether we're going to
4482 * set the DPLLs for dual-channel mode or not.
4483 */
4484 if (clock.p2 == 7)
4485 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4486 else
4487 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4488
4489 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4490 * appropriately here, but we need to look more thoroughly into how
4491 * panels behave in the two modes.
4492 */
929c77fb
EA		 4493 /* set the dithering flag on LVDS as needed */
4494 if (INTEL_INFO(dev)->gen >= 4) {
f564048e
EA		 4495 if (dev_priv->lvds_dither)
4496 temp |= LVDS_ENABLE_DITHER;
4497 else
4498 temp &= ~LVDS_ENABLE_DITHER;
4499 }
4500 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4501 lvds_sync |= LVDS_HSYNC_POLARITY;
4502 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4503 lvds_sync |= LVDS_VSYNC_POLARITY;
4504 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4505 != lvds_sync) {
4506 char flags[2] = "-+";
4507 DRM_INFO("Changing LVDS panel from "
4508 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4509 flags[!(temp & LVDS_HSYNC_POLARITY)],
4510 flags[!(temp & LVDS_VSYNC_POLARITY)],
4511 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4512 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4513 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4514 temp |= lvds_sync;
4515 }
fae14981 4516 I915_WRITE(LVDS, temp);
f564048e
EA		 4517 }
4518
929c77fb 4519 if (is_dp) {
f564048e 4520 intel_dp_set_m_n(crtc, mode, adjusted_mode);
f564048e
EA		 4521 }
4522
fae14981 4523 I915_WRITE(DPLL(pipe), dpll);
f564048e 4524
c713bb08 4525 /* Wait for the clocks to stabilize. */
fae14981 4526 POSTING_READ(DPLL(pipe));
c713bb08 4527 udelay(150);
f564048e 4528
c713bb08
EA		 4529 if (INTEL_INFO(dev)->gen >= 4) {
4530 temp = 0;
4531 if (is_sdvo) {
4532 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4533 if (temp > 1)
4534 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4535 else
4536 temp = 0;
f564048e 4537 }
c713bb08
EA		 4538 I915_WRITE(DPLL_MD(pipe), temp);
4539 } else {
4540 /* The pixel multiplier can only be updated once the
4541 * DPLL is enabled and the clocks are stable.
4542 *
4543 * So write it again.
4544 */
fae14981 4545 I915_WRITE(DPLL(pipe), dpll);
f564048e
EA		 4546 }
4547
4548 intel_crtc->lowfreq_avail = false;
4549 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4550 I915_WRITE(FP1(pipe), fp2);
f564048e
EA		 4551 intel_crtc->lowfreq_avail = true;
4552 if (HAS_PIPE_CXSR(dev)) {
4553 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4554 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4555 }
4556 } else {
fae14981 4557 I915_WRITE(FP1(pipe), fp);
f564048e
EA		 4558 if (HAS_PIPE_CXSR(dev)) {
4559 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4560 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4561 }
4562 }
4563
4564 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4565 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4566 /* the chip adds 2 halflines automatically */
4567 adjusted_mode->crtc_vdisplay -= 1;
4568 adjusted_mode->crtc_vtotal -= 1;
4569 adjusted_mode->crtc_vblank_start -= 1;
4570 adjusted_mode->crtc_vblank_end -= 1;
4571 adjusted_mode->crtc_vsync_end -= 1;
4572 adjusted_mode->crtc_vsync_start -= 1;
4573 } else
4574 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4575
4576 I915_WRITE(HTOTAL(pipe),
4577 (adjusted_mode->crtc_hdisplay - 1) |
4578 ((adjusted_mode->crtc_htotal - 1) << 16));
4579 I915_WRITE(HBLANK(pipe),
4580 (adjusted_mode->crtc_hblank_start - 1) |
4581 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4582 I915_WRITE(HSYNC(pipe),
4583 (adjusted_mode->crtc_hsync_start - 1) |
4584 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4585
4586 I915_WRITE(VTOTAL(pipe),
4587 (adjusted_mode->crtc_vdisplay - 1) |
4588 ((adjusted_mode->crtc_vtotal - 1) << 16));
4589 I915_WRITE(VBLANK(pipe),
4590 (adjusted_mode->crtc_vblank_start - 1) |
4591 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4592 I915_WRITE(VSYNC(pipe),
4593 (adjusted_mode->crtc_vsync_start - 1) |
4594 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4595
4596 /* pipesrc and dspsize control the size that is scaled from,
4597 * which should always be the user's requested size.
4598 */
929c77fb
EA		 4599 I915_WRITE(DSPSIZE(plane),
4600 ((mode->vdisplay - 1) << 16) |
4601 (mode->hdisplay - 1));
4602 I915_WRITE(DSPPOS(plane), 0);
f564048e
EA		 4603 I915_WRITE(PIPESRC(pipe),
4604 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4605
f564048e
EA		 4606 I915_WRITE(PIPECONF(pipe), pipeconf);
4607 POSTING_READ(PIPECONF(pipe));
929c77fb 4608 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4609
4610 intel_wait_for_vblank(dev, pipe);
4611
f564048e
EA		 4612 I915_WRITE(DSPCNTR(plane), dspcntr);
4613 POSTING_READ(DSPCNTR(plane));
4614
4615 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4616
4617 intel_update_watermarks(dev);
4618
f564048e
EA		 4619 return ret;
4620}
4621
4622static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4623 struct drm_display_mode *mode,
4624 struct drm_display_mode *adjusted_mode,
4625 int x, int y,
4626 struct drm_framebuffer *old_fb)
79e53945
JB		 4627{
4628 struct drm_device *dev = crtc->dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4631 int pipe = intel_crtc->pipe;
80824003 4632 int plane = intel_crtc->plane;
c751ce4f 4633 int refclk, num_connectors = 0;
652c393a 4634 intel_clock_t clock, reduced_clock;
5eddb70b 4635 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4636 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4637 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4638 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4639 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4640 struct intel_encoder *encoder;
d4906093 4641 const intel_limit_t *limit;
5c3b82e2 4642 int ret;
2c07245f 4643 struct fdi_m_n m_n = {0};
fae14981 4644 u32 temp;
aa9b500d 4645 u32 lvds_sync = 0;
8febb297 4646 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4647
5eddb70b
CW		 4648 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4649 if (encoder->base.crtc != crtc)
79e53945
JB		 4650 continue;
4651
5eddb70b 4652 switch (encoder->type) {
79e53945
JB		 4653 case INTEL_OUTPUT_LVDS:
4654 is_lvds = true;
4655 break;
4656 case INTEL_OUTPUT_SDVO:
7d57382e 4657 case INTEL_OUTPUT_HDMI:
79e53945 4658 is_sdvo = true;
5eddb70b 4659 if (encoder->needs_tv_clock)
e2f0ba97 4660 is_tv = true;
79e53945 4661 break;
79e53945
JB		 4662 case INTEL_OUTPUT_TVOUT:
4663 is_tv = true;
4664 break;
4665 case INTEL_OUTPUT_ANALOG:
4666 is_crt = true;
4667 break;
a4fc5ed6
KP		 4668 case INTEL_OUTPUT_DISPLAYPORT:
4669 is_dp = true;
4670 break;
32f9d658 4671 case INTEL_OUTPUT_EDP:
5eddb70b 4672 has_edp_encoder = encoder;
32f9d658 4673 break;
79e53945 4674 }
43565a06 4675
c751ce4f 4676 num_connectors++;
79e53945
JB		 4677 }
4678
a7615030 4679 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4680 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4681 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4682 refclk / 1000);
a07d6787 4683 } else {
79e53945 4684 refclk = 96000;
8febb297
EA		 4685 if (!has_edp_encoder ||
4686 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4687 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4688 }
4689
d4906093
ML		 4690 /*
4691 * Returns a set of divisors for the desired target clock with the given
4692 * refclk, or FALSE. The returned values represent the clock equation:
4693 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4694 */
1b894b59 4695 limit = intel_limit(crtc, refclk);
d4906093 4696 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4697 if (!ok) {
4698 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4699 return -EINVAL;
79e53945
JB		 4700 }
4701
cda4b7d3 4702 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4703 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4704
ddc9003c
ZY		 4705 if (is_lvds && dev_priv->lvds_downclock_avail) {
4706 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4707 dev_priv->lvds_downclock,
4708 refclk,
4709 &reduced_clock);
18f9ed12
ZY		 4710 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4711 /*
4712 * If the different P is found, it means that we can't
4713 * switch the display clock by using the FP0/FP1.
4714 * In such case we will disable the LVDS downclock
4715 * feature.
4716 */
4717 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4718 "LVDS clock/downclock\n");
18f9ed12
ZY		 4719 has_reduced_clock = 0;
4720 }
652c393a 4721 }
7026d4ac
ZW		 4722 /* SDVO TV has fixed PLL values depend on its clock range,
4723 this mirrors vbios setting. */
4724 if (is_sdvo && is_tv) {
4725 if (adjusted_mode->clock >= 100000
5eddb70b 4726 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4727 clock.p1 = 2;
4728 clock.p2 = 10;
4729 clock.n = 3;
4730 clock.m1 = 16;
4731 clock.m2 = 8;
4732 } else if (adjusted_mode->clock >= 140500
5eddb70b 4733 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4734 clock.p1 = 1;
4735 clock.p2 = 10;
4736 clock.n = 6;
4737 clock.m1 = 12;
4738 clock.m2 = 8;
4739 }
4740 }
4741
2c07245f 4742 /* FDI link */
8febb297
EA		 4743 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4744 lane = 0;
4745 /* CPU eDP doesn't require FDI link, so just set DP M/N
4746 according to current link config */
4747 if (has_edp_encoder &&
4748 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4749 target_clock = mode->clock;
4750 intel_edp_link_config(has_edp_encoder,
4751 &lane, &link_bw);
4752 } else {
4753 /* [e]DP over FDI requires target mode clock
4754 instead of link clock */
4755 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4756 target_clock = mode->clock;
8febb297
EA		 4757 else
4758 target_clock = adjusted_mode->clock;
4759
4760 /* FDI is a binary signal running at ~2.7GHz, encoding
4761 * each output octet as 10 bits. The actual frequency
4762 * is stored as a divider into a 100MHz clock, and the
4763 * mode pixel clock is stored in units of 1KHz.
4764 * Hence the bw of each lane in terms of the mode signal
4765 * is:
4766 */
4767 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4768 }
58a27471 4769
8febb297
EA		 4770 /* determine panel color depth */
4771 temp = I915_READ(PIPECONF(pipe));
4772 temp &= ~PIPE_BPC_MASK;
4773 if (is_lvds) {
4774 /* the BPC will be 6 if it is 18-bit LVDS panel */
4775 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4776 temp |= PIPE_8BPC;
4777 else
4778 temp |= PIPE_6BPC;
4779 } else if (has_edp_encoder) {
4780 switch (dev_priv->edp.bpp/3) {
4781 case 8:
e5a95eb7 4782 temp |= PIPE_8BPC;
58a27471 4783 break;
8febb297
EA		 4784 case 10:
4785 temp |= PIPE_10BPC;
58a27471 4786 break;
8febb297
EA		 4787 case 6:
4788 temp |= PIPE_6BPC;
58a27471 4789 break;
8febb297
EA		 4790 case 12:
4791 temp |= PIPE_12BPC;
58a27471 4792 break;
77ffb597 4793 }
8febb297
EA		 4794 } else
4795 temp |= PIPE_8BPC;
4796 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4797
8febb297
EA		 4798 switch (temp & PIPE_BPC_MASK) {
4799 case PIPE_8BPC:
4800 bpp = 24;
4801 break;
4802 case PIPE_10BPC:
4803 bpp = 30;
4804 break;
4805 case PIPE_6BPC:
4806 bpp = 18;
4807 break;
4808 case PIPE_12BPC:
4809 bpp = 36;
4810 break;
4811 default:
4812 DRM_ERROR("unknown pipe bpc value\n");
4813 bpp = 24;
4814 }
77ffb597 4815
8febb297
EA		 4816 if (!lane) {
4817 /*
4818 * Account for spread spectrum to avoid
4819 * oversubscribing the link. Max center spread
4820 * is 2.5%; use 5% for safety's sake.
4821 */
4822 u32 bps = target_clock * bpp * 21 / 20;
4823 lane = bps / (link_bw * 8) + 1;
5eb08b69 4824 }
2c07245f 4825
8febb297
EA		 4826 intel_crtc->fdi_lanes = lane;
4827
4828 if (pixel_multiplier > 1)
4829 link_bw *= pixel_multiplier;
4830 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4831
c038e51e
ZW		 4832 /* Ironlake: try to setup display ref clock before DPLL
4833 * enabling. This is only under driver's control after
4834 * PCH B stepping, previous chipset stepping should be
4835 * ignoring this setting.
4836 */
8febb297
EA		 4837 temp = I915_READ(PCH_DREF_CONTROL);
4838 /* Always enable nonspread source */
4839 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4840 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4841 temp &= ~DREF_SSC_SOURCE_MASK;
4842 temp |= DREF_SSC_SOURCE_ENABLE;
4843 I915_WRITE(PCH_DREF_CONTROL, temp);
4844
4845 POSTING_READ(PCH_DREF_CONTROL);
4846 udelay(200);
fc9a2228 4847
8febb297
EA		 4848 if (has_edp_encoder) {
4849 if (intel_panel_use_ssc(dev_priv)) {
4850 temp |= DREF_SSC1_ENABLE;
fc9a2228 4851 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4852
fc9a2228
CW		 4853 POSTING_READ(PCH_DREF_CONTROL);
4854 udelay(200);
4855 }
8febb297
EA		 4856 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4857
4858 /* Enable CPU source on CPU attached eDP */
4859 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4860 if (intel_panel_use_ssc(dev_priv))
4861 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4862 else
4863 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4864 } else {
4865 /* Enable SSC on PCH eDP if needed */
4866 if (intel_panel_use_ssc(dev_priv)) {
4867 DRM_ERROR("enabling SSC on PCH\n");
4868 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4869 }
4870 }
4871 I915_WRITE(PCH_DREF_CONTROL, temp);
4872 POSTING_READ(PCH_DREF_CONTROL);
4873 udelay(200);
fc9a2228 4874 }
c038e51e 4875
a07d6787
EA		 4876 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4877 if (has_reduced_clock)
4878 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4879 reduced_clock.m2;
79e53945 4880
c1858123 4881 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4882 factor = 21;
4883 if (is_lvds) {
4884 if ((intel_panel_use_ssc(dev_priv) &&
4885 dev_priv->lvds_ssc_freq == 100) ||
4886 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4887 factor = 25;
4888 } else if (is_sdvo && is_tv)
4889 factor = 20;
c1858123 4890
8febb297
EA		 4891 if (clock.m1 < factor * clock.n)
4892 fp |= FP_CB_TUNE;
c1858123 4893
5eddb70b 4894 dpll = 0;
2c07245f 4895
a07d6787
EA		 4896 if (is_lvds)
4897 dpll |= DPLLB_MODE_LVDS;
4898 else
4899 dpll |= DPLLB_MODE_DAC_SERIAL;
4900 if (is_sdvo) {
4901 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4902 if (pixel_multiplier > 1) {
4903 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4904 }
a07d6787
EA		 4905 dpll |= DPLL_DVO_HIGH_SPEED;
4906 }
4907 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4908 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4909
a07d6787
EA		 4910 /* compute bitmask from p1 value */
4911 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4912 /* also FPA1 */
4913 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4914
4915 switch (clock.p2) {
4916 case 5:
4917 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4918 break;
4919 case 7:
4920 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4921 break;
4922 case 10:
4923 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4924 break;
4925 case 14:
4926 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4927 break;
79e53945
JB		 4928 }
4929
43565a06
KH		 4930 if (is_sdvo && is_tv)
4931 dpll |= PLL_REF_INPUT_TVCLKINBC;
4932 else if (is_tv)
79e53945 4933 /* XXX: just matching BIOS for now */
43565a06 4934 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4935 dpll |= 3;
a7615030 4936 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4937 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4938 else
4939 dpll |= PLL_REF_INPUT_DREFCLK;
4940
4941 /* setup pipeconf */
5eddb70b 4942 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4943
4944 /* Set up the display plane register */
4945 dspcntr = DISPPLANE_GAMMA_ENABLE;
4946
28c97730 4947 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4948 drm_mode_debug_printmodeline(mode);
4949
5c5313c8
JB		 4950 /* PCH eDP needs FDI, but CPU eDP does not */
4951 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 4952 I915_WRITE(PCH_FP0(pipe), fp);
4953 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4954
fae14981 4955 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 4956 udelay(150);
4957 }
4958
8db9d77b
ZW		 4959 /* enable transcoder DPLL */
4960 if (HAS_PCH_CPT(dev)) {
4961 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 4962 switch (pipe) {
4963 case 0:
5eddb70b 4964 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 4965 break;
4966 case 1:
5eddb70b 4967 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 4968 break;
4969 case 2:
4970 /* FIXME: manage transcoder PLLs? */
4971 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4972 break;
4973 default:
4974 BUG();
4975 }
8db9d77b 4976 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 4977
4978 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 4979 udelay(150);
4980 }
4981
79e53945
JB		 4982 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4983 * This is an exception to the general rule that mode_set doesn't turn
4984 * things on.
4985 */
4986 if (is_lvds) {
fae14981 4987 temp = I915_READ(PCH_LVDS);
5eddb70b 4988 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 4989 if (pipe == 1) {
4990 if (HAS_PCH_CPT(dev))
5eddb70b 4991 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 4992 else
5eddb70b 4993 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 4994 } else {
4995 if (HAS_PCH_CPT(dev))
5eddb70b 4996 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 4997 else
5eddb70b 4998 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4999 }
a3e17eb8 5000 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5001 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5002 /* Set the B0-B3 data pairs corresponding to whether we're going to
5003 * set the DPLLs for dual-channel mode or not.
5004 */
5005 if (clock.p2 == 7)
5eddb70b 5006 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5007 else
5eddb70b 5008 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5009
5010 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5011 * appropriately here, but we need to look more thoroughly into how
5012 * panels behave in the two modes.
5013 */
aa9b500d
BF		 5014 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5015 lvds_sync |= LVDS_HSYNC_POLARITY;
5016 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5017 lvds_sync |= LVDS_VSYNC_POLARITY;
5018 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5019 != lvds_sync) {
5020 char flags[2] = "-+";
5021 DRM_INFO("Changing LVDS panel from "
5022 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5023 flags[!(temp & LVDS_HSYNC_POLARITY)],
5024 flags[!(temp & LVDS_VSYNC_POLARITY)],
5025 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5026 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5027 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5028 temp |= lvds_sync;
5029 }
fae14981 5030 I915_WRITE(PCH_LVDS, temp);
79e53945 5031 }
434ed097
JB		 5032
5033 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5034 pipeconf &= ~PIPECONF_DITHER_EN;
5035 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5036 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5037 pipeconf |= PIPECONF_DITHER_EN;
5038 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5039 }
5040
5c5313c8 5041 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5042 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5043 } else {
8db9d77b 5044 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5045 I915_WRITE(TRANSDATA_M1(pipe), 0);
5046 I915_WRITE(TRANSDATA_N1(pipe), 0);
5047 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5048 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5049 }
79e53945 5050
8febb297
EA		 5051 if (!has_edp_encoder ||
5052 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5053 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5054
32f9d658 5055 /* Wait for the clocks to stabilize. */
fae14981 5056 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5057 udelay(150);
5058
8febb297
EA		 5059 /* The pixel multiplier can only be updated once the
5060 * DPLL is enabled and the clocks are stable.
5061 *
5062 * So write it again.
5063 */
fae14981 5064 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5065 }
79e53945 5066
5eddb70b 5067 intel_crtc->lowfreq_avail = false;
652c393a 5068 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5069 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5070 intel_crtc->lowfreq_avail = true;
5071 if (HAS_PIPE_CXSR(dev)) {
28c97730 5072 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5073 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5074 }
5075 } else {
fae14981 5076 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5077 if (HAS_PIPE_CXSR(dev)) {
28c97730 5078 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5079 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5080 }
5081 }
5082
734b4157
KH		 5083 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5084 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5085 /* the chip adds 2 halflines automatically */
5086 adjusted_mode->crtc_vdisplay -= 1;
5087 adjusted_mode->crtc_vtotal -= 1;
5088 adjusted_mode->crtc_vblank_start -= 1;
5089 adjusted_mode->crtc_vblank_end -= 1;
5090 adjusted_mode->crtc_vsync_end -= 1;
5091 adjusted_mode->crtc_vsync_start -= 1;
5092 } else
5093 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5094
5eddb70b
CW		 5095 I915_WRITE(HTOTAL(pipe),
5096 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5097 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5098 I915_WRITE(HBLANK(pipe),
5099 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5100 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5101 I915_WRITE(HSYNC(pipe),
5102 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5103 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5104
5105 I915_WRITE(VTOTAL(pipe),
5106 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5107 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5108 I915_WRITE(VBLANK(pipe),
5109 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5110 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5111 I915_WRITE(VSYNC(pipe),
5112 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5113 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5114
8febb297
EA		 5115 /* pipesrc controls the size that is scaled from, which should
5116 * always be the user's requested size.
79e53945 5117 */
5eddb70b
CW		 5118 I915_WRITE(PIPESRC(pipe),
5119 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5120
8febb297
EA		 5121 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5122 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5123 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5124 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5125
8febb297
EA		 5126 if (has_edp_encoder &&
5127 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5128 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5129 }
5130
5eddb70b
CW		 5131 I915_WRITE(PIPECONF(pipe), pipeconf);
5132 POSTING_READ(PIPECONF(pipe));
79e53945 5133
9d0498a2 5134 intel_wait_for_vblank(dev, pipe);
79e53945 5135
f00a3ddf 5136 if (IS_GEN5(dev)) {
553bd149
ZW		 5137 /* enable address swizzle for tiling buffer */
5138 temp = I915_READ(DISP_ARB_CTL);
5139 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5140 }
5141
5eddb70b 5142 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5143 POSTING_READ(DSPCNTR(plane));
79e53945 5144
5c3b82e2 5145 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5146
5147 intel_update_watermarks(dev);
5148
1f803ee5 5149 return ret;
79e53945
JB		 5150}
5151
f564048e
EA		 5152static int intel_crtc_mode_set(struct drm_crtc *crtc,
5153 struct drm_display_mode *mode,
5154 struct drm_display_mode *adjusted_mode,
5155 int x, int y,
5156 struct drm_framebuffer *old_fb)
5157{
5158 struct drm_device *dev = crtc->dev;
5159 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161 int pipe = intel_crtc->pipe;
f564048e
EA		 5162 int ret;
5163
0b701d27
EA		 5164 drm_vblank_pre_modeset(dev, pipe);
5165
f564048e
EA		 5166 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5167 x, y, old_fb);
5168
0b701d27
EA		 5169 drm_vblank_post_modeset(dev, pipe);
5170
f564048e
EA		 5171 return ret;
5172}
5173
79e53945
JB		 5174/** Loads the palette/gamma unit for the CRTC with the prepared values */
5175void intel_crtc_load_lut(struct drm_crtc *crtc)
5176{
5177 struct drm_device *dev = crtc->dev;
5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5180 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5181 int i;
5182
5183 /* The clocks have to be on to load the palette. */
5184 if (!crtc->enabled)
5185 return;
5186
f2b115e6 5187 /* use legacy palette for Ironlake */
bad720ff 5188 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5189 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5190
79e53945
JB		 5191 for (i = 0; i < 256; i++) {
5192 I915_WRITE(palreg + 4 * i,
5193 (intel_crtc->lut_r[i] << 16) |
5194 (intel_crtc->lut_g[i] << 8) |
5195 intel_crtc->lut_b[i]);
5196 }
5197}
5198
560b85bb
CW		 5199static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5200{
5201 struct drm_device *dev = crtc->dev;
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204 bool visible = base != 0;
5205 u32 cntl;
5206
5207 if (intel_crtc->cursor_visible == visible)
5208 return;
5209
9db4a9c7 5210 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5211 if (visible) {
5212 /* On these chipsets we can only modify the base whilst
5213 * the cursor is disabled.
5214 */
9db4a9c7 5215 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5216
5217 cntl &= ~(CURSOR_FORMAT_MASK);
5218 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5219 cntl |= CURSOR_ENABLE |
5220 CURSOR_GAMMA_ENABLE |
5221 CURSOR_FORMAT_ARGB;
5222 } else
5223 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5224 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5225
5226 intel_crtc->cursor_visible = visible;
5227}
5228
5229static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5230{
5231 struct drm_device *dev = crtc->dev;
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234 int pipe = intel_crtc->pipe;
5235 bool visible = base != 0;
5236
5237 if (intel_crtc->cursor_visible != visible) {
548f245b 5238 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5239 if (base) {
5240 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5241 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5242 cntl |= pipe << 28; /* Connect to correct pipe */
5243 } else {
5244 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5245 cntl |= CURSOR_MODE_DISABLE;
5246 }
9db4a9c7 5247 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5248
5249 intel_crtc->cursor_visible = visible;
5250 }
5251 /* and commit changes on next vblank */
9db4a9c7 5252 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5253}
5254
cda4b7d3 5255/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5256static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5257 bool on)
cda4b7d3
CW		 5258{
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262 int pipe = intel_crtc->pipe;
5263 int x = intel_crtc->cursor_x;
5264 int y = intel_crtc->cursor_y;
560b85bb 5265 u32 base, pos;
cda4b7d3
CW		 5266 bool visible;
5267
5268 pos = 0;
5269
6b383a7f 5270 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5271 base = intel_crtc->cursor_addr;
5272 if (x > (int) crtc->fb->width)
5273 base = 0;
5274
5275 if (y > (int) crtc->fb->height)
5276 base = 0;
5277 } else
5278 base = 0;
5279
5280 if (x < 0) {
5281 if (x + intel_crtc->cursor_width < 0)
5282 base = 0;
5283
5284 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5285 x = -x;
5286 }
5287 pos |= x << CURSOR_X_SHIFT;
5288
5289 if (y < 0) {
5290 if (y + intel_crtc->cursor_height < 0)
5291 base = 0;
5292
5293 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5294 y = -y;
5295 }
5296 pos |= y << CURSOR_Y_SHIFT;
5297
5298 visible = base != 0;
560b85bb 5299 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5300 return;
5301
9db4a9c7 5302 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5303 if (IS_845G(dev) || IS_I865G(dev))
5304 i845_update_cursor(crtc, base);
5305 else
5306 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5307
5308 if (visible)
5309 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5310}
5311
79e53945 5312static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5313 struct drm_file *file,
79e53945
JB		 5314 uint32_t handle,
5315 uint32_t width, uint32_t height)
5316{
5317 struct drm_device *dev = crtc->dev;
5318 struct drm_i915_private *dev_priv = dev->dev_private;
5319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5320 struct drm_i915_gem_object *obj;
cda4b7d3 5321 uint32_t addr;
3f8bc370 5322 int ret;
79e53945 5323
28c97730 5324 DRM_DEBUG_KMS("\n");
79e53945
JB		 5325
5326 /* if we want to turn off the cursor ignore width and height */
5327 if (!handle) {
28c97730 5328 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5329 addr = 0;
05394f39 5330 obj = NULL;
5004417d 5331 mutex_lock(&dev->struct_mutex);
3f8bc370 5332 goto finish;
79e53945
JB		 5333 }
5334
5335 /* Currently we only support 64x64 cursors */
5336 if (width != 64 || height != 64) {
5337 DRM_ERROR("we currently only support 64x64 cursors\n");
5338 return -EINVAL;
5339 }
5340
05394f39 5341 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5342 if (&obj->base == NULL)
79e53945
JB		 5343 return -ENOENT;
5344
05394f39 5345 if (obj->base.size < width * height * 4) {
79e53945 5346 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5347 ret = -ENOMEM;
5348 goto fail;
79e53945
JB		 5349 }
5350
71acb5eb 5351 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5352 mutex_lock(&dev->struct_mutex);
b295d1b6 5353 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5354 if (obj->tiling_mode) {
5355 DRM_ERROR("cursor cannot be tiled\n");
5356 ret = -EINVAL;
5357 goto fail_locked;
5358 }
5359
05394f39 5360 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5361 if (ret) {
5362 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5363 goto fail_locked;
71acb5eb 5364 }
e7b526bb 5365
05394f39 5366 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5367 if (ret) {
5368 DRM_ERROR("failed to move cursor bo into the GTT\n");
5369 goto fail_unpin;
5370 }
5371
d9e86c0e
CW		 5372 ret = i915_gem_object_put_fence(obj);
5373 if (ret) {
5374 DRM_ERROR("failed to move cursor bo into the GTT\n");
5375 goto fail_unpin;
5376 }
5377
05394f39 5378 addr = obj->gtt_offset;
71acb5eb 5379 } else {
6eeefaf3 5380 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5381 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5382 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5383 align);
71acb5eb
DA		 5384 if (ret) {
5385 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5386 goto fail_locked;
71acb5eb 5387 }
05394f39 5388 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5389 }
5390
a6c45cf0 5391 if (IS_GEN2(dev))
14b60391
JB		 5392 I915_WRITE(CURSIZE, (height << 12) | width);
5393
3f8bc370 5394 finish:
3f8bc370 5395 if (intel_crtc->cursor_bo) {
b295d1b6 5396 if (dev_priv->info->cursor_needs_physical) {
05394f39 5397 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5398 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5399 } else
5400 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5401 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5402 }
80824003 5403
7f9872e0 5404 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5405
5406 intel_crtc->cursor_addr = addr;
05394f39 5407 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5408 intel_crtc->cursor_width = width;
5409 intel_crtc->cursor_height = height;
5410
6b383a7f 5411 intel_crtc_update_cursor(crtc, true);
3f8bc370 5412
79e53945 5413 return 0;
e7b526bb 5414fail_unpin:
05394f39 5415 i915_gem_object_unpin(obj);
7f9872e0 5416fail_locked:
34b8686e 5417 mutex_unlock(&dev->struct_mutex);
bc9025bd 5418fail:
05394f39 5419 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5420 return ret;
79e53945
JB		 5421}
5422
5423static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5424{
79e53945 5425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5426
cda4b7d3
CW		 5427 intel_crtc->cursor_x = x;
5428 intel_crtc->cursor_y = y;
652c393a 5429
6b383a7f 5430 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5431
5432 return 0;
5433}
5434
5435/** Sets the color ramps on behalf of RandR */
5436void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5437 u16 blue, int regno)
5438{
5439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5440
5441 intel_crtc->lut_r[regno] = red >> 8;
5442 intel_crtc->lut_g[regno] = green >> 8;
5443 intel_crtc->lut_b[regno] = blue >> 8;
5444}
5445
b8c00ac5
DA		 5446void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5447 u16 *blue, int regno)
5448{
5449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450
5451 *red = intel_crtc->lut_r[regno] << 8;
5452 *green = intel_crtc->lut_g[regno] << 8;
5453 *blue = intel_crtc->lut_b[regno] << 8;
5454}
5455
79e53945 5456static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5457 u16 *blue, uint32_t start, uint32_t size)
79e53945 5458{
7203425a 5459 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5461
7203425a 5462 for (i = start; i < end; i++) {
79e53945
JB		 5463 intel_crtc->lut_r[i] = red[i] >> 8;
5464 intel_crtc->lut_g[i] = green[i] >> 8;
5465 intel_crtc->lut_b[i] = blue[i] >> 8;
5466 }
5467
5468 intel_crtc_load_lut(crtc);
5469}
5470
5471/**
5472 * Get a pipe with a simple mode set on it for doing load-based monitor
5473 * detection.
5474 *
5475 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5476 * its requirements. The pipe will be connected to no other encoders.
79e53945 5477 *
c751ce4f 5478 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5479 * configured for it. In the future, it could choose to temporarily disable
5480 * some outputs to free up a pipe for its use.
5481 *
5482 * \return crtc, or NULL if no pipes are available.
5483 */
5484
5485/* VESA 640x480x72Hz mode to set on the pipe */
5486static struct drm_display_mode load_detect_mode = {
5487 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5488 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5489};
5490
d2dff872
CW		 5491static struct drm_framebuffer *
5492intel_framebuffer_create(struct drm_device *dev,
5493 struct drm_mode_fb_cmd *mode_cmd,
5494 struct drm_i915_gem_object *obj)
5495{
5496 struct intel_framebuffer *intel_fb;
5497 int ret;
5498
5499 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5500 if (!intel_fb) {
5501 drm_gem_object_unreference_unlocked(&obj->base);
5502 return ERR_PTR(-ENOMEM);
5503 }
5504
5505 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5506 if (ret) {
5507 drm_gem_object_unreference_unlocked(&obj->base);
5508 kfree(intel_fb);
5509 return ERR_PTR(ret);
5510 }
5511
5512 return &intel_fb->base;
5513}
5514
5515static u32
5516intel_framebuffer_pitch_for_width(int width, int bpp)
5517{
5518 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5519 return ALIGN(pitch, 64);
5520}
5521
5522static u32
5523intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5524{
5525 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5526 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5527}
5528
5529static struct drm_framebuffer *
5530intel_framebuffer_create_for_mode(struct drm_device *dev,
5531 struct drm_display_mode *mode,
5532 int depth, int bpp)
5533{
5534 struct drm_i915_gem_object *obj;
5535 struct drm_mode_fb_cmd mode_cmd;
5536
5537 obj = i915_gem_alloc_object(dev,
5538 intel_framebuffer_size_for_mode(mode, bpp));
5539 if (obj == NULL)
5540 return ERR_PTR(-ENOMEM);
5541
5542 mode_cmd.width = mode->hdisplay;
5543 mode_cmd.height = mode->vdisplay;
5544 mode_cmd.depth = depth;
5545 mode_cmd.bpp = bpp;
5546 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5547
5548 return intel_framebuffer_create(dev, &mode_cmd, obj);
5549}
5550
5551static struct drm_framebuffer *
5552mode_fits_in_fbdev(struct drm_device *dev,
5553 struct drm_display_mode *mode)
5554{
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 struct drm_i915_gem_object *obj;
5557 struct drm_framebuffer *fb;
5558
5559 if (dev_priv->fbdev == NULL)
5560 return NULL;
5561
5562 obj = dev_priv->fbdev->ifb.obj;
5563 if (obj == NULL)
5564 return NULL;
5565
5566 fb = &dev_priv->fbdev->ifb.base;
5567 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5568 fb->bits_per_pixel))
5569 return NULL;
5570
5571 if (obj->base.size < mode->vdisplay * fb->pitch)
5572 return NULL;
5573
5574 return fb;
5575}
5576
7173188d
CW		 5577bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5578 struct drm_connector *connector,
5579 struct drm_display_mode *mode,
8261b191 5580 struct intel_load_detect_pipe *old)
79e53945
JB		 5581{
5582 struct intel_crtc *intel_crtc;
5583 struct drm_crtc *possible_crtc;
4ef69c7a 5584 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5585 struct drm_crtc *crtc = NULL;
5586 struct drm_device *dev = encoder->dev;
d2dff872 5587 struct drm_framebuffer *old_fb;
79e53945
JB		 5588 int i = -1;
5589
d2dff872
CW		 5590 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5591 connector->base.id, drm_get_connector_name(connector),
5592 encoder->base.id, drm_get_encoder_name(encoder));
5593
79e53945
JB		 5594 /*
5595 * Algorithm gets a little messy:
7a5e4805 5596 *
79e53945
JB		 5597 * - if the connector already has an assigned crtc, use it (but make
5598 * sure it's on first)
7a5e4805 5599 *
79e53945
JB		 5600 * - try to find the first unused crtc that can drive this connector,
5601 * and use that if we find one
79e53945
JB		 5602 */
5603
5604 /* See if we already have a CRTC for this connector */
5605 if (encoder->crtc) {
5606 crtc = encoder->crtc;
8261b191 5607
79e53945 5608 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5609 old->dpms_mode = intel_crtc->dpms_mode;
5610 old->load_detect_temp = false;
5611
5612 /* Make sure the crtc and connector are running */
79e53945 5613 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5614 struct drm_encoder_helper_funcs *encoder_funcs;
5615 struct drm_crtc_helper_funcs *crtc_funcs;
5616
79e53945
JB		 5617 crtc_funcs = crtc->helper_private;
5618 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5619
5620 encoder_funcs = encoder->helper_private;
79e53945
JB		 5621 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5622 }
8261b191 5623
7173188d 5624 return true;
79e53945
JB		 5625 }
5626
5627 /* Find an unused one (if possible) */
5628 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5629 i++;
5630 if (!(encoder->possible_crtcs & (1 << i)))
5631 continue;
5632 if (!possible_crtc->enabled) {
5633 crtc = possible_crtc;
5634 break;
5635 }
79e53945
JB		 5636 }
5637
5638 /*
5639 * If we didn't find an unused CRTC, don't use any.
5640 */
5641 if (!crtc) {
7173188d
CW		 5642 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5643 return false;
79e53945
JB		 5644 }
5645
5646 encoder->crtc = crtc;
c1c43977 5647 connector->encoder = encoder;
79e53945
JB		 5648
5649 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5650 old->dpms_mode = intel_crtc->dpms_mode;
5651 old->load_detect_temp = true;
d2dff872 5652 old->release_fb = NULL;
79e53945 5653
6492711d
CW		 5654 if (!mode)
5655 mode = &load_detect_mode;
79e53945 5656
d2dff872
CW		 5657 old_fb = crtc->fb;
5658
5659 /* We need a framebuffer large enough to accommodate all accesses
5660 * that the plane may generate whilst we perform load detection.
5661 * We can not rely on the fbcon either being present (we get called
5662 * during its initialisation to detect all boot displays, or it may
5663 * not even exist) or that it is large enough to satisfy the
5664 * requested mode.
5665 */
5666 crtc->fb = mode_fits_in_fbdev(dev, mode);
5667 if (crtc->fb == NULL) {
5668 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5669 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5670 old->release_fb = crtc->fb;
5671 } else
5672 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5673 if (IS_ERR(crtc->fb)) {
5674 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5675 crtc->fb = old_fb;
5676 return false;
5677 }
5678
5679 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5680 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5681 if (old->release_fb)
5682 old->release_fb->funcs->destroy(old->release_fb);
5683 crtc->fb = old_fb;
6492711d 5684 return false;
79e53945 5685 }
7173188d 5686
79e53945 5687 /* let the connector get through one full cycle before testing */
9d0498a2 5688 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5689
7173188d 5690 return true;
79e53945
JB		 5691}
5692
c1c43977 5693void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5694 struct drm_connector *connector,
5695 struct intel_load_detect_pipe *old)
79e53945 5696{
4ef69c7a 5697 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5698 struct drm_device *dev = encoder->dev;
5699 struct drm_crtc *crtc = encoder->crtc;
5700 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5701 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5702
d2dff872
CW		 5703 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5704 connector->base.id, drm_get_connector_name(connector),
5705 encoder->base.id, drm_get_encoder_name(encoder));
5706
8261b191 5707 if (old->load_detect_temp) {
c1c43977 5708 connector->encoder = NULL;
79e53945 5709 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5710
5711 if (old->release_fb)
5712 old->release_fb->funcs->destroy(old->release_fb);
5713
0622a53c 5714 return;
79e53945
JB		 5715 }
5716
c751ce4f 5717 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5718 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5719 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5720 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5721 }
5722}
5723
5724/* Returns the clock of the currently programmed mode of the given pipe. */
5725static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5726{
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 int pipe = intel_crtc->pipe;
548f245b 5730 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5731 u32 fp;
5732 intel_clock_t clock;
5733
5734 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5735 fp = I915_READ(FP0(pipe));
79e53945 5736 else
39adb7a5 5737 fp = I915_READ(FP1(pipe));
79e53945
JB		 5738
5739 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5740 if (IS_PINEVIEW(dev)) {
5741 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5742 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5743 } else {
5744 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5745 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5746 }
5747
a6c45cf0 5748 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5749 if (IS_PINEVIEW(dev))
5750 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5751 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5752 else
5753 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5754 DPLL_FPA01_P1_POST_DIV_SHIFT);
5755
5756 switch (dpll & DPLL_MODE_MASK) {
5757 case DPLLB_MODE_DAC_SERIAL:
5758 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5759 5 : 10;
5760 break;
5761 case DPLLB_MODE_LVDS:
5762 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5763 7 : 14;
5764 break;
5765 default:
28c97730 5766 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5767 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5768 return 0;
5769 }
5770
5771 /* XXX: Handle the 100Mhz refclk */
2177832f 5772 intel_clock(dev, 96000, &clock);
79e53945
JB		 5773 } else {
5774 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5775
5776 if (is_lvds) {
5777 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5778 DPLL_FPA01_P1_POST_DIV_SHIFT);
5779 clock.p2 = 14;
5780
5781 if ((dpll & PLL_REF_INPUT_MASK) ==
5782 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5783 /* XXX: might not be 66MHz */
2177832f 5784 intel_clock(dev, 66000, &clock);
79e53945 5785 } else
2177832f 5786 intel_clock(dev, 48000, &clock);
79e53945
JB		 5787 } else {
5788 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5789 clock.p1 = 2;
5790 else {
5791 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5792 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5793 }
5794 if (dpll & PLL_P2_DIVIDE_BY_4)
5795 clock.p2 = 4;
5796 else
5797 clock.p2 = 2;
5798
2177832f 5799 intel_clock(dev, 48000, &clock);
79e53945
JB		 5800 }
5801 }
5802
5803 /* XXX: It would be nice to validate the clocks, but we can't reuse
5804 * i830PllIsValid() because it relies on the xf86_config connector
5805 * configuration being accurate, which it isn't necessarily.
5806 */
5807
5808 return clock.dot;
5809}
5810
5811/** Returns the currently programmed mode of the given pipe. */
5812struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5813 struct drm_crtc *crtc)
5814{
548f245b 5815 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817 int pipe = intel_crtc->pipe;
5818 struct drm_display_mode *mode;
548f245b
JB		 5819 int htot = I915_READ(HTOTAL(pipe));
5820 int hsync = I915_READ(HSYNC(pipe));
5821 int vtot = I915_READ(VTOTAL(pipe));
5822 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5823
5824 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5825 if (!mode)
5826 return NULL;
5827
5828 mode->clock = intel_crtc_clock_get(dev, crtc);
5829 mode->hdisplay = (htot & 0xffff) + 1;
5830 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5831 mode->hsync_start = (hsync & 0xffff) + 1;
5832 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5833 mode->vdisplay = (vtot & 0xffff) + 1;
5834 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5835 mode->vsync_start = (vsync & 0xffff) + 1;
5836 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5837
5838 drm_mode_set_name(mode);
5839 drm_mode_set_crtcinfo(mode, 0);
5840
5841 return mode;
5842}
5843
652c393a
JB		 5844#define GPU_IDLE_TIMEOUT 500 /* ms */
5845
5846/* When this timer fires, we've been idle for awhile */
5847static void intel_gpu_idle_timer(unsigned long arg)
5848{
5849 struct drm_device *dev = (struct drm_device *)arg;
5850 drm_i915_private_t *dev_priv = dev->dev_private;
5851
ff7ea4c0
CW		 5852 if (!list_empty(&dev_priv->mm.active_list)) {
5853 /* Still processing requests, so just re-arm the timer. */
5854 mod_timer(&dev_priv->idle_timer, jiffies +
5855 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5856 return;
5857 }
652c393a 5858
ff7ea4c0 5859 dev_priv->busy = false;
01dfba93 5860 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5861}
5862
652c393a
JB		 5863#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5864
5865static void intel_crtc_idle_timer(unsigned long arg)
5866{
5867 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5868 struct drm_crtc *crtc = &intel_crtc->base;
5869 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5870 struct intel_framebuffer *intel_fb;
652c393a 5871
ff7ea4c0
CW		 5872 intel_fb = to_intel_framebuffer(crtc->fb);
5873 if (intel_fb && intel_fb->obj->active) {
5874 /* The framebuffer is still being accessed by the GPU. */
5875 mod_timer(&intel_crtc->idle_timer, jiffies +
5876 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5877 return;
5878 }
652c393a 5879
ff7ea4c0 5880 intel_crtc->busy = false;
01dfba93 5881 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5882}
5883
3dec0095 5884static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5885{
5886 struct drm_device *dev = crtc->dev;
5887 drm_i915_private_t *dev_priv = dev->dev_private;
5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5890 int dpll_reg = DPLL(pipe);
5891 int dpll;
652c393a 5892
bad720ff 5893 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5894 return;
5895
5896 if (!dev_priv->lvds_downclock_avail)
5897 return;
5898
dbdc6479 5899 dpll = I915_READ(dpll_reg);
652c393a 5900 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5901 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 5902
5903 /* Unlock panel regs */
dbdc6479
JB		 5904 I915_WRITE(PP_CONTROL,
5905 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 5906
5907 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5908 I915_WRITE(dpll_reg, dpll);
9d0498a2 5909 intel_wait_for_vblank(dev, pipe);
dbdc6479 5910
652c393a
JB		 5911 dpll = I915_READ(dpll_reg);
5912 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5913 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5914
5915 /* ...and lock them again */
5916 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5917 }
5918
5919 /* Schedule downclock */
3dec0095
DV		 5920 mod_timer(&intel_crtc->idle_timer, jiffies +
5921 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5922}
5923
5924static void intel_decrease_pllclock(struct drm_crtc *crtc)
5925{
5926 struct drm_device *dev = crtc->dev;
5927 drm_i915_private_t *dev_priv = dev->dev_private;
5928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5929 int pipe = intel_crtc->pipe;
9db4a9c7 5930 int dpll_reg = DPLL(pipe);
652c393a
JB		 5931 int dpll = I915_READ(dpll_reg);
5932
bad720ff 5933 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5934 return;
5935
5936 if (!dev_priv->lvds_downclock_avail)
5937 return;
5938
5939 /*
5940 * Since this is called by a timer, we should never get here in
5941 * the manual case.
5942 */
5943 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 5944 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 5945
5946 /* Unlock panel regs */
4a655f04
JB		 5947 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5948 PANEL_UNLOCK_REGS);
652c393a
JB		 5949
5950 dpll |= DISPLAY_RATE_SELECT_FPA1;
5951 I915_WRITE(dpll_reg, dpll);
9d0498a2 5952 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5953 dpll = I915_READ(dpll_reg);
5954 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5955 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5956
5957 /* ...and lock them again */
5958 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5959 }
5960
5961}
5962
5963/**
5964 * intel_idle_update - adjust clocks for idleness
5965 * @work: work struct
5966 *
5967 * Either the GPU or display (or both) went idle. Check the busy status
5968 * here and adjust the CRTC and GPU clocks as necessary.
5969 */
5970static void intel_idle_update(struct work_struct *work)
5971{
5972 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5973 idle_work);
5974 struct drm_device *dev = dev_priv->dev;
5975 struct drm_crtc *crtc;
5976 struct intel_crtc *intel_crtc;
5977
5978 if (!i915_powersave)
5979 return;
5980
5981 mutex_lock(&dev->struct_mutex);
5982
7648fa99
JB		 5983 i915_update_gfx_val(dev_priv);
5984
652c393a
JB		 5985 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5986 /* Skip inactive CRTCs */
5987 if (!crtc->fb)
5988 continue;
5989
5990 intel_crtc = to_intel_crtc(crtc);
5991 if (!intel_crtc->busy)
5992 intel_decrease_pllclock(crtc);
5993 }
5994
45ac22c8 5995
652c393a
JB		 5996 mutex_unlock(&dev->struct_mutex);
5997}
5998
5999/**
6000 * intel_mark_busy - mark the GPU and possibly the display busy
6001 * @dev: drm device
6002 * @obj: object we're operating on
6003 *
6004 * Callers can use this function to indicate that the GPU is busy processing
6005 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6006 * buffer), we'll also mark the display as busy, so we know to increase its
6007 * clock frequency.
6008 */
05394f39 6009void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6010{
6011 drm_i915_private_t *dev_priv = dev->dev_private;
6012 struct drm_crtc *crtc = NULL;
6013 struct intel_framebuffer *intel_fb;
6014 struct intel_crtc *intel_crtc;
6015
5e17ee74
ZW		 6016 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6017 return;
6018
18b2190c 6019 if (!dev_priv->busy)
28cf798f 6020 dev_priv->busy = true;
18b2190c 6021 else
28cf798f
CW		 6022 mod_timer(&dev_priv->idle_timer, jiffies +
6023 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6024
6025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6026 if (!crtc->fb)
6027 continue;
6028
6029 intel_crtc = to_intel_crtc(crtc);
6030 intel_fb = to_intel_framebuffer(crtc->fb);
6031 if (intel_fb->obj == obj) {
6032 if (!intel_crtc->busy) {
6033 /* Non-busy -> busy, upclock */
3dec0095 6034 intel_increase_pllclock(crtc);
652c393a
JB		 6035 intel_crtc->busy = true;
6036 } else {
6037 /* Busy -> busy, put off timer */
6038 mod_timer(&intel_crtc->idle_timer, jiffies +
6039 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6040 }
6041 }
6042 }
6043}
6044
79e53945
JB		 6045static void intel_crtc_destroy(struct drm_crtc *crtc)
6046{
6047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6048 struct drm_device *dev = crtc->dev;
6049 struct intel_unpin_work *work;
6050 unsigned long flags;
6051
6052 spin_lock_irqsave(&dev->event_lock, flags);
6053 work = intel_crtc->unpin_work;
6054 intel_crtc->unpin_work = NULL;
6055 spin_unlock_irqrestore(&dev->event_lock, flags);
6056
6057 if (work) {
6058 cancel_work_sync(&work->work);
6059 kfree(work);
6060 }
79e53945
JB		 6061
6062 drm_crtc_cleanup(crtc);
67e77c5a 6063
79e53945
JB		 6064 kfree(intel_crtc);
6065}
6066
6b95a207
KH		 6067static void intel_unpin_work_fn(struct work_struct *__work)
6068{
6069 struct intel_unpin_work *work =
6070 container_of(__work, struct intel_unpin_work, work);
6071
6072 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6073 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6074 drm_gem_object_unreference(&work->pending_flip_obj->base);
6075 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6076
6b95a207
KH		 6077 mutex_unlock(&work->dev->struct_mutex);
6078 kfree(work);
6079}
6080
1afe3e9d 6081static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6082 struct drm_crtc *crtc)
6b95a207
KH		 6083{
6084 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086 struct intel_unpin_work *work;
05394f39 6087 struct drm_i915_gem_object *obj;
6b95a207 6088 struct drm_pending_vblank_event *e;
49b14a5c 6089 struct timeval tnow, tvbl;
6b95a207
KH		 6090 unsigned long flags;
6091
6092 /* Ignore early vblank irqs */
6093 if (intel_crtc == NULL)
6094 return;
6095
49b14a5c
MK		 6096 do_gettimeofday(&tnow);
6097
6b95a207
KH		 6098 spin_lock_irqsave(&dev->event_lock, flags);
6099 work = intel_crtc->unpin_work;
6100 if (work == NULL || !work->pending) {
6101 spin_unlock_irqrestore(&dev->event_lock, flags);
6102 return;
6103 }
6104
6105 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6106
6107 if (work->event) {
6108 e = work->event;
49b14a5c 6109 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6110
6111 /* Called before vblank count and timestamps have
6112 * been updated for the vblank interval of flip
6113 * completion? Need to increment vblank count and
6114 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6115 * to account for this. We assume this happened if we
6116 * get called over 0.9 frame durations after the last
6117 * timestamped vblank.
6118 *
6119 * This calculation can not be used with vrefresh rates
6120 * below 5Hz (10Hz to be on the safe side) without
6121 * promoting to 64 integers.
0af7e4df 6122 */
49b14a5c
MK		 6123 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6124 9 * crtc->framedur_ns) {
0af7e4df 6125 e->event.sequence++;
49b14a5c
MK		 6126 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6127 crtc->framedur_ns);
0af7e4df
MK		 6128 }
6129
49b14a5c
MK		 6130 e->event.tv_sec = tvbl.tv_sec;
6131 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6132
6b95a207
KH		 6133 list_add_tail(&e->base.link,
6134 &e->base.file_priv->event_list);
6135 wake_up_interruptible(&e->base.file_priv->event_wait);
6136 }
6137
0af7e4df
MK		 6138 drm_vblank_put(dev, intel_crtc->pipe);
6139
6b95a207
KH		 6140 spin_unlock_irqrestore(&dev->event_lock, flags);
6141
05394f39 6142 obj = work->old_fb_obj;
d9e86c0e 6143
e59f2bac 6144 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6145 &obj->pending_flip.counter);
6146 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6147 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6148
6b95a207 6149 schedule_work(&work->work);
e5510fac
JB		 6150
6151 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6152}
6153
1afe3e9d
JB		 6154void intel_finish_page_flip(struct drm_device *dev, int pipe)
6155{
6156 drm_i915_private_t *dev_priv = dev->dev_private;
6157 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6158
49b14a5c 6159 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6160}
6161
6162void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6163{
6164 drm_i915_private_t *dev_priv = dev->dev_private;
6165 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6166
49b14a5c 6167 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6168}
6169
6b95a207
KH		 6170void intel_prepare_page_flip(struct drm_device *dev, int plane)
6171{
6172 drm_i915_private_t *dev_priv = dev->dev_private;
6173 struct intel_crtc *intel_crtc =
6174 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6175 unsigned long flags;
6176
6177 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6178 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6179 if ((++intel_crtc->unpin_work->pending) > 1)
6180 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6181 } else {
6182 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6183 }
6b95a207
KH		 6184 spin_unlock_irqrestore(&dev->event_lock, flags);
6185}
6186
6187static int intel_crtc_page_flip(struct drm_crtc *crtc,
6188 struct drm_framebuffer *fb,
6189 struct drm_pending_vblank_event *event)
6190{
6191 struct drm_device *dev = crtc->dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
6193 struct intel_framebuffer *intel_fb;
05394f39 6194 struct drm_i915_gem_object *obj;
6b95a207
KH		 6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 struct intel_unpin_work *work;
be9a3dbf 6197 unsigned long flags, offset;
52e68630 6198 int pipe = intel_crtc->pipe;
20f0cd55 6199 u32 pf, pipesrc;
52e68630 6200 int ret;
6b95a207
KH		 6201
6202 work = kzalloc(sizeof *work, GFP_KERNEL);
6203 if (work == NULL)
6204 return -ENOMEM;
6205
6b95a207
KH		 6206 work->event = event;
6207 work->dev = crtc->dev;
6208 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6209 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6210 INIT_WORK(&work->work, intel_unpin_work_fn);
6211
6212 /* We borrow the event spin lock for protecting unpin_work */
6213 spin_lock_irqsave(&dev->event_lock, flags);
6214 if (intel_crtc->unpin_work) {
6215 spin_unlock_irqrestore(&dev->event_lock, flags);
6216 kfree(work);
468f0b44
CW		 6217
6218 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6219 return -EBUSY;
6220 }
6221 intel_crtc->unpin_work = work;
6222 spin_unlock_irqrestore(&dev->event_lock, flags);
6223
6224 intel_fb = to_intel_framebuffer(fb);
6225 obj = intel_fb->obj;
6226
468f0b44 6227 mutex_lock(&dev->struct_mutex);
1ec14ad3 6228 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
96b099fd
CW		 6229 if (ret)
6230 goto cleanup_work;
6b95a207 6231
75dfca80 6232 /* Reference the objects for the scheduled work. */
05394f39
CW		 6233 drm_gem_object_reference(&work->old_fb_obj->base);
6234 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6235
6236 crtc->fb = fb;
96b099fd
CW		 6237
6238 ret = drm_vblank_get(dev, intel_crtc->pipe);
6239 if (ret)
6240 goto cleanup_objs;
6241
c7f9f9a8
CW		 6242 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6243 u32 flip_mask;
48b956c5 6244
c7f9f9a8
CW		 6245 /* Can't queue multiple flips, so wait for the previous
6246 * one to finish before executing the next.
6247 */
e1f99ce6
CW		 6248 ret = BEGIN_LP_RING(2);
6249 if (ret)
6250 goto cleanup_objs;
6251
c7f9f9a8
CW		 6252 if (intel_crtc->plane)
6253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6254 else
6255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6256 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6257 OUT_RING(MI_NOOP);
6146b3d6
DV		 6258 ADVANCE_LP_RING();
6259 }
83f7fd05 6260
e1f99ce6 6261 work->pending_flip_obj = obj;
e1f99ce6 6262
4e5359cd
SF		 6263 work->enable_stall_check = true;
6264
be9a3dbf 6265 /* Offset into the new buffer for cases of shared fbs between CRTCs */
52e68630 6266 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
be9a3dbf 6267
e1f99ce6
CW		 6268 ret = BEGIN_LP_RING(4);
6269 if (ret)
6270 goto cleanup_objs;
6271
6272 /* Block clients from rendering to the new back buffer until
6273 * the flip occurs and the object is no longer visible.
6274 */
05394f39 6275 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6
CW		 6276
6277 switch (INTEL_INFO(dev)->gen) {
52e68630 6278 case 2:
1afe3e9d
JB		 6279 OUT_RING(MI_DISPLAY_FLIP |
6280 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6281 OUT_RING(fb->pitch);
05394f39 6282 OUT_RING(obj->gtt_offset + offset);
52e68630
CW		 6283 OUT_RING(MI_NOOP);
6284 break;
6285
6286 case 3:
1afe3e9d
JB		 6287 OUT_RING(MI_DISPLAY_FLIP_I915 |
6288 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6289 OUT_RING(fb->pitch);
05394f39 6290 OUT_RING(obj->gtt_offset + offset);
22fd0fab 6291 OUT_RING(MI_NOOP);
52e68630
CW		 6292 break;
6293
6294 case 4:
6295 case 5:
6296 /* i965+ uses the linear or tiled offsets from the
6297 * Display Registers (which do not change across a page-flip)
6298 * so we need only reprogram the base address.
6299 */
69d0b96c
DV		 6300 OUT_RING(MI_DISPLAY_FLIP |
6301 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6302 OUT_RING(fb->pitch);
05394f39 6303 OUT_RING(obj->gtt_offset | obj->tiling_mode);
52e68630
CW		 6304
6305 /* XXX Enabling the panel-fitter across page-flip is so far
6306 * untested on non-native modes, so ignore it for now.
6307 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6308 */
6309 pf = 0;
9db4a9c7 6310 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6311 OUT_RING(pf | pipesrc);
6312 break;
6313
6314 case 6:
6315 OUT_RING(MI_DISPLAY_FLIP |
6316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
05394f39
CW		 6317 OUT_RING(fb->pitch | obj->tiling_mode);
6318 OUT_RING(obj->gtt_offset);
52e68630 6319
9db4a9c7
JB		 6320 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6321 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6322 OUT_RING(pf | pipesrc);
6323 break;
22fd0fab 6324 }
6b95a207
KH		 6325 ADVANCE_LP_RING();
6326
6327 mutex_unlock(&dev->struct_mutex);
6328
e5510fac
JB		 6329 trace_i915_flip_request(intel_crtc->plane, obj);
6330
6b95a207 6331 return 0;
96b099fd
CW		 6332
6333cleanup_objs:
05394f39
CW		 6334 drm_gem_object_unreference(&work->old_fb_obj->base);
6335 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6336cleanup_work:
6337 mutex_unlock(&dev->struct_mutex);
6338
6339 spin_lock_irqsave(&dev->event_lock, flags);
6340 intel_crtc->unpin_work = NULL;
6341 spin_unlock_irqrestore(&dev->event_lock, flags);
6342
6343 kfree(work);
6344
6345 return ret;
6b95a207
KH		 6346}
6347
47f1c6c9
CW		 6348static void intel_sanitize_modesetting(struct drm_device *dev,
6349 int pipe, int plane)
6350{
6351 struct drm_i915_private *dev_priv = dev->dev_private;
6352 u32 reg, val;
6353
6354 if (HAS_PCH_SPLIT(dev))
6355 return;
6356
6357 /* Who knows what state these registers were left in by the BIOS or
6358 * grub?
6359 *
6360 * If we leave the registers in a conflicting state (e.g. with the
6361 * display plane reading from the other pipe than the one we intend
6362 * to use) then when we attempt to teardown the active mode, we will
6363 * not disable the pipes and planes in the correct order -- leaving
6364 * a plane reading from a disabled pipe and possibly leading to
6365 * undefined behaviour.
6366 */
6367
6368 reg = DSPCNTR(plane);
6369 val = I915_READ(reg);
6370
6371 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6372 return;
6373 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6374 return;
6375
6376 /* This display plane is active and attached to the other CPU pipe. */
6377 pipe = !pipe;
6378
6379 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6380 intel_disable_plane(dev_priv, plane, pipe);
6381 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6382}
79e53945 6383
f6e5b160
CW		 6384static void intel_crtc_reset(struct drm_crtc *crtc)
6385{
6386 struct drm_device *dev = crtc->dev;
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388
6389 /* Reset flags back to the 'unknown' status so that they
6390 * will be correctly set on the initial modeset.
6391 */
6392 intel_crtc->dpms_mode = -1;
6393
6394 /* We need to fix up any BIOS configuration that conflicts with
6395 * our expectations.
6396 */
6397 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6398}
6399
6400static struct drm_crtc_helper_funcs intel_helper_funcs = {
6401 .dpms = intel_crtc_dpms,
6402 .mode_fixup = intel_crtc_mode_fixup,
6403 .mode_set = intel_crtc_mode_set,
6404 .mode_set_base = intel_pipe_set_base,
6405 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6406 .load_lut = intel_crtc_load_lut,
6407 .disable = intel_crtc_disable,
6408};
6409
6410static const struct drm_crtc_funcs intel_crtc_funcs = {
6411 .reset = intel_crtc_reset,
6412 .cursor_set = intel_crtc_cursor_set,
6413 .cursor_move = intel_crtc_cursor_move,
6414 .gamma_set = intel_crtc_gamma_set,
6415 .set_config = drm_crtc_helper_set_config,
6416 .destroy = intel_crtc_destroy,
6417 .page_flip = intel_crtc_page_flip,
6418};
6419
b358d0a6 6420static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6421{
22fd0fab 6422 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6423 struct intel_crtc *intel_crtc;
6424 int i;
6425
6426 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6427 if (intel_crtc == NULL)
6428 return;
6429
6430 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6431
6432 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6433 for (i = 0; i < 256; i++) {
6434 intel_crtc->lut_r[i] = i;
6435 intel_crtc->lut_g[i] = i;
6436 intel_crtc->lut_b[i] = i;
6437 }
6438
80824003
JB		 6439 /* Swap pipes & planes for FBC on pre-965 */
6440 intel_crtc->pipe = pipe;
6441 intel_crtc->plane = pipe;
e2e767ab 6442 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6443 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6444 intel_crtc->plane = !pipe;
80824003
JB		 6445 }
6446
22fd0fab
JB		 6447 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6448 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6449 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6450 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6451
5d1d0cc8 6452 intel_crtc_reset(&intel_crtc->base);
04dbff52 6453 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6454
6455 if (HAS_PCH_SPLIT(dev)) {
6456 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6457 intel_helper_funcs.commit = ironlake_crtc_commit;
6458 } else {
6459 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6460 intel_helper_funcs.commit = i9xx_crtc_commit;
6461 }
6462
79e53945
JB		 6463 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6464
652c393a
JB		 6465 intel_crtc->busy = false;
6466
6467 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6468 (unsigned long)intel_crtc);
79e53945
JB		 6469}
6470
08d7b3d1 6471int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6472 struct drm_file *file)
08d7b3d1
CW		 6473{
6474 drm_i915_private_t *dev_priv = dev->dev_private;
6475 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6476 struct drm_mode_object *drmmode_obj;
6477 struct intel_crtc *crtc;
08d7b3d1
CW		 6478
6479 if (!dev_priv) {
6480 DRM_ERROR("called with no initialization\n");
6481 return -EINVAL;
6482 }
6483
c05422d5
DV		 6484 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6485 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6486
c05422d5 6487 if (!drmmode_obj) {
08d7b3d1
CW		 6488 DRM_ERROR("no such CRTC id\n");
6489 return -EINVAL;
6490 }
6491
c05422d5
DV		 6492 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6493 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6494
c05422d5 6495 return 0;
08d7b3d1
CW		 6496}
6497
c5e4df33 6498static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6499{
4ef69c7a 6500 struct intel_encoder *encoder;
79e53945 6501 int index_mask = 0;
79e53945
JB		 6502 int entry = 0;
6503
4ef69c7a
CW		 6504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6505 if (type_mask & encoder->clone_mask)
79e53945
JB		 6506 index_mask |= (1 << entry);
6507 entry++;
6508 }
4ef69c7a 6509
79e53945
JB		 6510 return index_mask;
6511}
6512
4d302442
CW		 6513static bool has_edp_a(struct drm_device *dev)
6514{
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516
6517 if (!IS_MOBILE(dev))
6518 return false;
6519
6520 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6521 return false;
6522
6523 if (IS_GEN5(dev) &&
6524 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6525 return false;
6526
6527 return true;
6528}
6529
79e53945
JB		 6530static void intel_setup_outputs(struct drm_device *dev)
6531{
725e30ad 6532 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6533 struct intel_encoder *encoder;
cb0953d7 6534 bool dpd_is_edp = false;
c5d1b51d 6535 bool has_lvds = false;
79e53945 6536
541998a1 6537 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6538 has_lvds = intel_lvds_init(dev);
6539 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6540 /* disable the panel fitter on everything but LVDS */
6541 I915_WRITE(PFIT_CONTROL, 0);
6542 }
79e53945 6543
bad720ff 6544 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6545 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6546
4d302442 6547 if (has_edp_a(dev))
32f9d658
ZW		 6548 intel_dp_init(dev, DP_A);
6549
cb0953d7
AJ		 6550 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6551 intel_dp_init(dev, PCH_DP_D);
6552 }
6553
6554 intel_crt_init(dev);
6555
6556 if (HAS_PCH_SPLIT(dev)) {
6557 int found;
6558
30ad48b7 6559 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6560 /* PCH SDVOB multiplex with HDMIB */
6561 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6562 if (!found)
6563 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6564 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6565 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6566 }
6567
6568 if (I915_READ(HDMIC) & PORT_DETECTED)
6569 intel_hdmi_init(dev, HDMIC);
6570
6571 if (I915_READ(HDMID) & PORT_DETECTED)
6572 intel_hdmi_init(dev, HDMID);
6573
5eb08b69
ZW		 6574 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6575 intel_dp_init(dev, PCH_DP_C);
6576
cb0953d7 6577 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6578 intel_dp_init(dev, PCH_DP_D);
6579
103a196f 6580 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6581 bool found = false;
7d57382e 6582
725e30ad 6583 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6584 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6585 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6586 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6587 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6588 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6589 }
27185ae1 6590
b01f2c3a
JB		 6591 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6592 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6593 intel_dp_init(dev, DP_B);
b01f2c3a 6594 }
725e30ad 6595 }
13520b05
KH		 6596
6597 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6598
b01f2c3a
JB		 6599 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6600 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6601 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6602 }
27185ae1
ML		 6603
6604 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6605
b01f2c3a
JB		 6606 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6607 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6608 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6609 }
6610 if (SUPPORTS_INTEGRATED_DP(dev)) {
6611 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6612 intel_dp_init(dev, DP_C);
b01f2c3a 6613 }
725e30ad 6614 }
27185ae1 6615
b01f2c3a
JB		 6616 if (SUPPORTS_INTEGRATED_DP(dev) &&
6617 (I915_READ(DP_D) & DP_DETECTED)) {
6618 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6619 intel_dp_init(dev, DP_D);
b01f2c3a 6620 }
bad720ff 6621 } else if (IS_GEN2(dev))
79e53945
JB		 6622 intel_dvo_init(dev);
6623
103a196f 6624 if (SUPPORTS_TV(dev))
79e53945
JB		 6625 intel_tv_init(dev);
6626
4ef69c7a
CW		 6627 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6628 encoder->base.possible_crtcs = encoder->crtc_mask;
6629 encoder->base.possible_clones =
6630 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6631 }
47356eb6
CW		 6632
6633 intel_panel_setup_backlight(dev);
2c7111db
CW		 6634
6635 /* disable all the possible outputs/crtcs before entering KMS mode */
6636 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6637}
6638
6639static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6640{
6641 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6642
6643 drm_framebuffer_cleanup(fb);
05394f39 6644 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6645
6646 kfree(intel_fb);
6647}
6648
6649static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6650 struct drm_file *file,
79e53945
JB		 6651 unsigned int *handle)
6652{
6653 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6654 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6655
05394f39 6656 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6657}
6658
6659static const struct drm_framebuffer_funcs intel_fb_funcs = {
6660 .destroy = intel_user_framebuffer_destroy,
6661 .create_handle = intel_user_framebuffer_create_handle,
6662};
6663
38651674
DA		 6664int intel_framebuffer_init(struct drm_device *dev,
6665 struct intel_framebuffer *intel_fb,
6666 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6667 struct drm_i915_gem_object *obj)
79e53945 6668{
79e53945
JB		 6669 int ret;
6670
05394f39 6671 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6672 return -EINVAL;
6673
6674 if (mode_cmd->pitch & 63)
6675 return -EINVAL;
6676
6677 switch (mode_cmd->bpp) {
6678 case 8:
6679 case 16:
6680 case 24:
6681 case 32:
6682 break;
6683 default:
6684 return -EINVAL;
6685 }
6686
79e53945
JB		 6687 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6688 if (ret) {
6689 DRM_ERROR("framebuffer init failed %d\n", ret);
6690 return ret;
6691 }
6692
6693 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6694 intel_fb->obj = obj;
79e53945
JB		 6695 return 0;
6696}
6697
79e53945
JB		 6698static struct drm_framebuffer *
6699intel_user_framebuffer_create(struct drm_device *dev,
6700 struct drm_file *filp,
6701 struct drm_mode_fb_cmd *mode_cmd)
6702{
05394f39 6703 struct drm_i915_gem_object *obj;
79e53945 6704
05394f39 6705 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6706 if (&obj->base == NULL)
cce13ff7 6707 return ERR_PTR(-ENOENT);
79e53945 6708
d2dff872 6709 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6710}
6711
79e53945 6712static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6713 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6714 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6715};
6716
05394f39 6717static struct drm_i915_gem_object *
aa40d6bb 6718intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6719{
05394f39 6720 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6721 int ret;
6722
2c34b850
BW		 6723 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6724
aa40d6bb
ZN		 6725 ctx = i915_gem_alloc_object(dev, 4096);
6726 if (!ctx) {
9ea8d059
CW		 6727 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6728 return NULL;
6729 }
6730
75e9e915 6731 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6732 if (ret) {
6733 DRM_ERROR("failed to pin power context: %d\n", ret);
6734 goto err_unref;
6735 }
6736
aa40d6bb 6737 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6738 if (ret) {
6739 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6740 goto err_unpin;
6741 }
9ea8d059 6742
aa40d6bb 6743 return ctx;
9ea8d059
CW		 6744
6745err_unpin:
aa40d6bb 6746 i915_gem_object_unpin(ctx);
9ea8d059 6747err_unref:
05394f39 6748 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6749 mutex_unlock(&dev->struct_mutex);
6750 return NULL;
6751}
6752
7648fa99
JB		 6753bool ironlake_set_drps(struct drm_device *dev, u8 val)
6754{
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 u16 rgvswctl;
6757
6758 rgvswctl = I915_READ16(MEMSWCTL);
6759 if (rgvswctl & MEMCTL_CMD_STS) {
6760 DRM_DEBUG("gpu busy, RCS change rejected\n");
6761 return false; /* still busy with another command */
6762 }
6763
6764 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6765 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6766 I915_WRITE16(MEMSWCTL, rgvswctl);
6767 POSTING_READ16(MEMSWCTL);
6768
6769 rgvswctl |= MEMCTL_CMD_STS;
6770 I915_WRITE16(MEMSWCTL, rgvswctl);
6771
6772 return true;
6773}
6774
f97108d1
JB		 6775void ironlake_enable_drps(struct drm_device *dev)
6776{
6777 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6778 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6779 u8 fmax, fmin, fstart, vstart;
f97108d1 6780
ea056c14
JB		 6781 /* Enable temp reporting */
6782 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6783 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6784
f97108d1
JB		 6785 /* 100ms RC evaluation intervals */
6786 I915_WRITE(RCUPEI, 100000);
6787 I915_WRITE(RCDNEI, 100000);
6788
6789 /* Set max/min thresholds to 90ms and 80ms respectively */
6790 I915_WRITE(RCBMAXAVG, 90000);
6791 I915_WRITE(RCBMINAVG, 80000);
6792
6793 I915_WRITE(MEMIHYST, 1);
6794
6795 /* Set up min, max, and cur for interrupt handling */
6796 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6797 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6798 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6799 MEMMODE_FSTART_SHIFT;
7648fa99 6800
f97108d1
JB		 6801 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6802 PXVFREQ_PX_SHIFT;
6803
80dbf4b7 6804 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 6805 dev_priv->fstart = fstart;
6806
80dbf4b7 6807 dev_priv->max_delay = fstart;
f97108d1
JB		 6808 dev_priv->min_delay = fmin;
6809 dev_priv->cur_delay = fstart;
6810
80dbf4b7
JB		 6811 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6812 fmax, fmin, fstart);
7648fa99 6813
f97108d1
JB		 6814 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6815
6816 /*
6817 * Interrupts will be enabled in ironlake_irq_postinstall
6818 */
6819
6820 I915_WRITE(VIDSTART, vstart);
6821 POSTING_READ(VIDSTART);
6822
6823 rgvmodectl |= MEMMODE_SWMODE_EN;
6824 I915_WRITE(MEMMODECTL, rgvmodectl);
6825
481b6af3 6826 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 6827 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 6828 msleep(1);
6829
7648fa99 6830 ironlake_set_drps(dev, fstart);
f97108d1 6831
7648fa99
JB		 6832 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6833 I915_READ(0x112e0);
6834 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6835 dev_priv->last_count2 = I915_READ(0x112f4);
6836 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 6837}
6838
6839void ironlake_disable_drps(struct drm_device *dev)
6840{
6841 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6842 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 6843
6844 /* Ack interrupts, disable EFC interrupt */
6845 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6846 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6847 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6848 I915_WRITE(DEIIR, DE_PCU_EVENT);
6849 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6850
6851 /* Go back to the starting frequency */
7648fa99 6852 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 6853 msleep(1);
6854 rgvswctl |= MEMCTL_CMD_STS;
6855 I915_WRITE(MEMSWCTL, rgvswctl);
6856 msleep(1);
6857
6858}
6859
3b8d8d91
JB		 6860void gen6_set_rps(struct drm_device *dev, u8 val)
6861{
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 u32 swreq;
6864
6865 swreq = (val & 0x3ff) << 25;
6866 I915_WRITE(GEN6_RPNSWREQ, swreq);
6867}
6868
6869void gen6_disable_rps(struct drm_device *dev)
6870{
6871 struct drm_i915_private *dev_priv = dev->dev_private;
6872
6873 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6874 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6875 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 6876
6877 spin_lock_irq(&dev_priv->rps_lock);
6878 dev_priv->pm_iir = 0;
6879 spin_unlock_irq(&dev_priv->rps_lock);
6880
3b8d8d91
JB		 6881 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6882}
6883
7648fa99
JB		 6884static unsigned long intel_pxfreq(u32 vidfreq)
6885{
6886 unsigned long freq;
6887 int div = (vidfreq & 0x3f0000) >> 16;
6888 int post = (vidfreq & 0x3000) >> 12;
6889 int pre = (vidfreq & 0x7);
6890
6891 if (!pre)
6892 return 0;
6893
6894 freq = ((div * 133333) / ((1<<post) * pre));
6895
6896 return freq;
6897}
6898
6899void intel_init_emon(struct drm_device *dev)
6900{
6901 struct drm_i915_private *dev_priv = dev->dev_private;
6902 u32 lcfuse;
6903 u8 pxw[16];
6904 int i;
6905
6906 /* Disable to program */
6907 I915_WRITE(ECR, 0);
6908 POSTING_READ(ECR);
6909
6910 /* Program energy weights for various events */
6911 I915_WRITE(SDEW, 0x15040d00);
6912 I915_WRITE(CSIEW0, 0x007f0000);
6913 I915_WRITE(CSIEW1, 0x1e220004);
6914 I915_WRITE(CSIEW2, 0x04000004);
6915
6916 for (i = 0; i < 5; i++)
6917 I915_WRITE(PEW + (i * 4), 0);
6918 for (i = 0; i < 3; i++)
6919 I915_WRITE(DEW + (i * 4), 0);
6920
6921 /* Program P-state weights to account for frequency power adjustment */
6922 for (i = 0; i < 16; i++) {
6923 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6924 unsigned long freq = intel_pxfreq(pxvidfreq);
6925 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6926 PXVFREQ_PX_SHIFT;
6927 unsigned long val;
6928
6929 val = vid * vid;
6930 val *= (freq / 1000);
6931 val *= 255;
6932 val /= (127*127*900);
6933 if (val > 0xff)
6934 DRM_ERROR("bad pxval: %ld\n", val);
6935 pxw[i] = val;
6936 }
6937 /* Render standby states get 0 weight */
6938 pxw[14] = 0;
6939 pxw[15] = 0;
6940
6941 for (i = 0; i < 4; i++) {
6942 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6943 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6944 I915_WRITE(PXW + (i * 4), val);
6945 }
6946
6947 /* Adjust magic regs to magic values (more experimental results) */
6948 I915_WRITE(OGW0, 0);
6949 I915_WRITE(OGW1, 0);
6950 I915_WRITE(EG0, 0x00007f00);
6951 I915_WRITE(EG1, 0x0000000e);
6952 I915_WRITE(EG2, 0x000e0000);
6953 I915_WRITE(EG3, 0x68000300);
6954 I915_WRITE(EG4, 0x42000000);
6955 I915_WRITE(EG5, 0x00140031);
6956 I915_WRITE(EG6, 0);
6957 I915_WRITE(EG7, 0);
6958
6959 for (i = 0; i < 8; i++)
6960 I915_WRITE(PXWL + (i * 4), 0);
6961
6962 /* Enable PMON + select events */
6963 I915_WRITE(ECR, 0x80000019);
6964
6965 lcfuse = I915_READ(LCFUSE02);
6966
6967 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6968}
6969
3b8d8d91 6970void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 6971{
a6044e23
JB		 6972 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6973 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 6974 u32 pcu_mbox, rc6_mask = 0;
a6044e23 6975 int cur_freq, min_freq, max_freq;
8fd26859
CW		 6976 int i;
6977
6978 /* Here begins a magic sequence of register writes to enable
6979 * auto-downclocking.
6980 *
6981 * Perhaps there might be some value in exposing these to
6982 * userspace...
6983 */
6984 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 6985 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 6986 gen6_gt_force_wake_get(dev_priv);
8fd26859 6987
3b8d8d91 6988 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 6989 I915_WRITE(GEN6_RC_CONTROL, 0);
6990
6991 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6992 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6993 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6994 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6995 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6996
6997 for (i = 0; i < I915_NUM_RINGS; i++)
6998 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6999
7000 I915_WRITE(GEN6_RC_SLEEP, 0);
7001 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7002 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7003 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7004 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7005
7df8721b
JB		 7006 if (i915_enable_rc6)
7007 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7008 GEN6_RC_CTL_RC6_ENABLE;
7009
8fd26859 7010 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7011 rc6_mask |
9c3d2f7f 7012 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7013 GEN6_RC_CTL_HW_ENABLE);
7014
3b8d8d91 7015 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7016 GEN6_FREQUENCY(10) |
7017 GEN6_OFFSET(0) |
7018 GEN6_AGGRESSIVE_TURBO);
7019 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7020 GEN6_FREQUENCY(12));
7021
7022 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7023 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7024 18 << 24 |
7025 6 << 16);
ccab5c82
JB		 7026 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7027 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7028 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7029 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7030 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7031 I915_WRITE(GEN6_RP_CONTROL,
7032 GEN6_RP_MEDIA_TURBO |
7033 GEN6_RP_USE_NORMAL_FREQ |
7034 GEN6_RP_MEDIA_IS_GFX |
7035 GEN6_RP_ENABLE |
ccab5c82
JB		 7036 GEN6_RP_UP_BUSY_AVG |
7037 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7038
7039 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7040 500))
7041 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7042
7043 I915_WRITE(GEN6_PCODE_DATA, 0);
7044 I915_WRITE(GEN6_PCODE_MAILBOX,
7045 GEN6_PCODE_READY |
7046 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7047 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7048 500))
7049 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7050
a6044e23
JB		 7051 min_freq = (rp_state_cap & 0xff0000) >> 16;
7052 max_freq = rp_state_cap & 0xff;
7053 cur_freq = (gt_perf_status & 0xff00) >> 8;
7054
7055 /* Check for overclock support */
7056 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7057 500))
7058 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7059 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7060 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7061 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7062 500))
7063 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7064 if (pcu_mbox & (1<<31)) { /* OC supported */
7065 max_freq = pcu_mbox & 0xff;
e281fcaa 7066 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7067 }
7068
7069 /* In units of 100MHz */
7070 dev_priv->max_delay = max_freq;
7071 dev_priv->min_delay = min_freq;
7072 dev_priv->cur_delay = cur_freq;
7073
8fd26859
CW		 7074 /* requires MSI enabled */
7075 I915_WRITE(GEN6_PMIER,
7076 GEN6_PM_MBOX_EVENT |
7077 GEN6_PM_THERMAL_EVENT |
7078 GEN6_PM_RP_DOWN_TIMEOUT |
7079 GEN6_PM_RP_UP_THRESHOLD |
7080 GEN6_PM_RP_DOWN_THRESHOLD |
7081 GEN6_PM_RP_UP_EI_EXPIRED |
7082 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7083 spin_lock_irq(&dev_priv->rps_lock);
7084 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7085 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7086 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7087 /* enable all PM interrupts */
7088 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7089
fcca7926 7090 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7091 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7092}
7093
0cdab21f 7094void intel_enable_clock_gating(struct drm_device *dev)
652c393a
JB		 7095{
7096 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7097 int pipe;
652c393a
JB		 7098
7099 /*
7100 * Disable clock gating reported to work incorrectly according to the
7101 * specs, but enable as much else as we can.
7102 */
bad720ff 7103 if (HAS_PCH_SPLIT(dev)) {
8956c8bb
EA		 7104 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7105
f00a3ddf 7106 if (IS_GEN5(dev)) {
8956c8bb 7107 /* Required for FBC */
1ffa325b
JB		 7108 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7109 DPFCRUNIT_CLOCK_GATE_DISABLE |
7110 DPFDUNIT_CLOCK_GATE_DISABLE;
8956c8bb
EA		 7111 /* Required for CxSR */
7112 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7113
7114 I915_WRITE(PCH_3DCGDIS0,
7115 MARIUNIT_CLOCK_GATE_DISABLE |
7116 SVSMUNIT_CLOCK_GATE_DISABLE);
06f37751
EA		 7117 I915_WRITE(PCH_3DCGDIS1,
7118 VFMUNIT_CLOCK_GATE_DISABLE);
8956c8bb
EA		 7119 }
7120
7121 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7f8a8569 7122
382b0936
JB		 7123 /*
7124 * On Ibex Peak and Cougar Point, we need to disable clock
7125 * gating for the panel power sequencer or it will fail to
7126 * start up when no ports are active.
7127 */
7128 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7129
7f8a8569
ZW		 7130 /*
7131 * According to the spec the following bits should be set in
7132 * order to enable memory self-refresh
7133 * The bit 22/21 of 0x42004
7134 * The bit 5 of 0x42020
7135 * The bit 15 of 0x45000
7136 */
f00a3ddf 7137 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7138 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7139 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7140 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7141 I915_WRITE(ILK_DSPCLK_GATE,
7142 (I915_READ(ILK_DSPCLK_GATE) |
7143 ILK_DPARB_CLK_GATE));
7144 I915_WRITE(DISP_ARB_CTL,
7145 (I915_READ(DISP_ARB_CTL) |
7146 DISP_FBC_WM_DIS));
1398261a
YL		 7147 I915_WRITE(WM3_LP_ILK, 0);
7148 I915_WRITE(WM2_LP_ILK, 0);
7149 I915_WRITE(WM1_LP_ILK, 0);
7f8a8569 7150 }
b52eb4dc
ZY		 7151 /*
7152 * Based on the document from hardware guys the following bits
7153 * should be set unconditionally in order to enable FBC.
7154 * The bit 22 of 0x42000
7155 * The bit 22 of 0x42004
7156 * The bit 7,8,9 of 0x42020.
7157 */
7158 if (IS_IRONLAKE_M(dev)) {
7159 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7160 I915_READ(ILK_DISPLAY_CHICKEN1) |
7161 ILK_FBCQ_DIS);
7162 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7163 I915_READ(ILK_DISPLAY_CHICKEN2) |
7164 ILK_DPARB_GATE);
7165 I915_WRITE(ILK_DSPCLK_GATE,
7166 I915_READ(ILK_DSPCLK_GATE) |
7167 ILK_DPFC_DIS1 |
7168 ILK_DPFC_DIS2 |
7169 ILK_CLK_FBC);
7170 }
de6e2eaf 7171
67e92af0
EA		 7172 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7173 I915_READ(ILK_DISPLAY_CHICKEN2) |
7174 ILK_ELPIN_409_SELECT);
7175
de6e2eaf
EA		 7176 if (IS_GEN5(dev)) {
7177 I915_WRITE(_3D_CHICKEN2,
7178 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7179 _3D_CHICKEN2_WM_READ_PIPELINED);
7180 }
8fd26859 7181
1398261a
YL		 7182 if (IS_GEN6(dev)) {
7183 I915_WRITE(WM3_LP_ILK, 0);
7184 I915_WRITE(WM2_LP_ILK, 0);
7185 I915_WRITE(WM1_LP_ILK, 0);
7186
7187 /*
7188 * According to the spec the following bits should be
7189 * set in order to enable memory self-refresh and fbc:
7190 * The bit21 and bit22 of 0x42000
7191 * The bit21 and bit22 of 0x42004
7192 * The bit5 and bit7 of 0x42020
7193 * The bit14 of 0x70180
7194 * The bit14 of 0x71180
7195 */
7196 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7197 I915_READ(ILK_DISPLAY_CHICKEN1) |
7198 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7199 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7200 I915_READ(ILK_DISPLAY_CHICKEN2) |
7201 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7202 I915_WRITE(ILK_DSPCLK_GATE,
7203 I915_READ(ILK_DSPCLK_GATE) |
7204 ILK_DPARB_CLK_GATE |
7205 ILK_DPFD_CLK_GATE);
7206
9db4a9c7
JB		 7207 for_each_pipe(pipe)
7208 I915_WRITE(DSPCNTR(pipe),
7209 I915_READ(DSPCNTR(pipe)) |
7210 DISPPLANE_TRICKLE_FEED_DISABLE);
1398261a 7211 }
c03342fa 7212 } else if (IS_G4X(dev)) {
652c393a
JB		 7213 uint32_t dspclk_gate;
7214 I915_WRITE(RENCLK_GATE_D1, 0);
7215 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7216 GS_UNIT_CLOCK_GATE_DISABLE |
7217 CL_UNIT_CLOCK_GATE_DISABLE);
7218 I915_WRITE(RAMCLK_GATE_D, 0);
7219 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7220 OVRUNIT_CLOCK_GATE_DISABLE |
7221 OVCUNIT_CLOCK_GATE_DISABLE;
7222 if (IS_GM45(dev))
7223 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7224 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
a6c45cf0 7225 } else if (IS_CRESTLINE(dev)) {
652c393a
JB		 7226 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7227 I915_WRITE(RENCLK_GATE_D2, 0);
7228 I915_WRITE(DSPCLK_GATE_D, 0);
7229 I915_WRITE(RAMCLK_GATE_D, 0);
7230 I915_WRITE16(DEUC, 0);
a6c45cf0 7231 } else if (IS_BROADWATER(dev)) {
652c393a
JB		 7232 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7233 I965_RCC_CLOCK_GATE_DISABLE |
7234 I965_RCPB_CLOCK_GATE_DISABLE |
7235 I965_ISC_CLOCK_GATE_DISABLE |
7236 I965_FBC_CLOCK_GATE_DISABLE);
7237 I915_WRITE(RENCLK_GATE_D2, 0);
a6c45cf0 7238 } else if (IS_GEN3(dev)) {
652c393a
JB		 7239 u32 dstate = I915_READ(D_STATE);
7240
7241 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7242 DSTATE_DOT_CLOCK_GATING;
7243 I915_WRITE(D_STATE, dstate);
f0f8a9ce 7244 } else if (IS_I85X(dev) || IS_I865G(dev)) {
652c393a
JB		 7245 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7246 } else if (IS_I830(dev)) {
7247 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7248 }
7249}
7250
ac668088 7251static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7252{
7253 struct drm_i915_private *dev_priv = dev->dev_private;
7254
7255 if (dev_priv->renderctx) {
ac668088
CW		 7256 i915_gem_object_unpin(dev_priv->renderctx);
7257 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7258 dev_priv->renderctx = NULL;
7259 }
7260
7261 if (dev_priv->pwrctx) {
ac668088
CW		 7262 i915_gem_object_unpin(dev_priv->pwrctx);
7263 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7264 dev_priv->pwrctx = NULL;
7265 }
7266}
7267
7268static void ironlake_disable_rc6(struct drm_device *dev)
7269{
7270 struct drm_i915_private *dev_priv = dev->dev_private;
7271
7272 if (I915_READ(PWRCTXA)) {
7273 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7274 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7275 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7276 50);
0cdab21f
CW		 7277
7278 I915_WRITE(PWRCTXA, 0);
7279 POSTING_READ(PWRCTXA);
7280
ac668088
CW		 7281 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7282 POSTING_READ(RSTDBYCTL);
0cdab21f 7283 }
ac668088 7284
99507307 7285 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7286}
7287
ac668088 7288static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7289{
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291
ac668088
CW		 7292 if (dev_priv->renderctx == NULL)
7293 dev_priv->renderctx = intel_alloc_context_page(dev);
7294 if (!dev_priv->renderctx)
7295 return -ENOMEM;
7296
7297 if (dev_priv->pwrctx == NULL)
7298 dev_priv->pwrctx = intel_alloc_context_page(dev);
7299 if (!dev_priv->pwrctx) {
7300 ironlake_teardown_rc6(dev);
7301 return -ENOMEM;
7302 }
7303
7304 return 0;
d5bb081b
JB		 7305}
7306
7307void ironlake_enable_rc6(struct drm_device *dev)
7308{
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 int ret;
7311
ac668088
CW		 7312 /* rc6 disabled by default due to repeated reports of hanging during
7313 * boot and resume.
7314 */
7315 if (!i915_enable_rc6)
7316 return;
7317
2c34b850 7318 mutex_lock(&dev->struct_mutex);
ac668088 7319 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7320 if (ret) {
7321 mutex_unlock(&dev->struct_mutex);
ac668088 7322 return;
2c34b850 7323 }
ac668088 7324
d5bb081b
JB		 7325 /*
7326 * GPU can automatically power down the render unit if given a page
7327 * to save state.
7328 */
7329 ret = BEGIN_LP_RING(6);
7330 if (ret) {
ac668088 7331 ironlake_teardown_rc6(dev);
2c34b850 7332 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7333 return;
7334 }
ac668088 7335
d5bb081b
JB		 7336 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7337 OUT_RING(MI_SET_CONTEXT);
7338 OUT_RING(dev_priv->renderctx->gtt_offset |
7339 MI_MM_SPACE_GTT |
7340 MI_SAVE_EXT_STATE_EN |
7341 MI_RESTORE_EXT_STATE_EN |
7342 MI_RESTORE_INHIBIT);
7343 OUT_RING(MI_SUSPEND_FLUSH);
7344 OUT_RING(MI_NOOP);
7345 OUT_RING(MI_FLUSH);
7346 ADVANCE_LP_RING();
7347
4a246cfc
BW		 7348 /*
7349 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7350 * does an implicit flush, combined with MI_FLUSH above, it should be
7351 * safe to assume that renderctx is valid
7352 */
7353 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7354 if (ret) {
7355 DRM_ERROR("failed to enable ironlake power power savings\n");
7356 ironlake_teardown_rc6(dev);
7357 mutex_unlock(&dev->struct_mutex);
7358 return;
7359 }
7360
d5bb081b
JB		 7361 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7362 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7363 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7364}
7365
ac668088 7366
e70236a8
JB		 7367/* Set up chip specific display functions */
7368static void intel_init_display(struct drm_device *dev)
7369{
7370 struct drm_i915_private *dev_priv = dev->dev_private;
7371
7372 /* We always want a DPMS function */
f564048e 7373 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7374 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7375 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7376 } else {
e70236a8 7377 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7378 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7379 }
e70236a8 7380
ee5382ae 7381 if (I915_HAS_FBC(dev)) {
9c04f015 7382 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7383 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7384 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7385 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7386 } else if (IS_GM45(dev)) {
74dff282
JB		 7387 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7388 dev_priv->display.enable_fbc = g4x_enable_fbc;
7389 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7390 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7391 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7392 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7393 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7394 }
74dff282 7395 /* 855GM needs testing */
e70236a8
JB		 7396 }
7397
7398 /* Returns the core display clock speed */
f2b115e6 7399 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7400 dev_priv->display.get_display_clock_speed =
7401 i945_get_display_clock_speed;
7402 else if (IS_I915G(dev))
7403 dev_priv->display.get_display_clock_speed =
7404 i915_get_display_clock_speed;
f2b115e6 7405 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7406 dev_priv->display.get_display_clock_speed =
7407 i9xx_misc_get_display_clock_speed;
7408 else if (IS_I915GM(dev))
7409 dev_priv->display.get_display_clock_speed =
7410 i915gm_get_display_clock_speed;
7411 else if (IS_I865G(dev))
7412 dev_priv->display.get_display_clock_speed =
7413 i865_get_display_clock_speed;
f0f8a9ce 7414 else if (IS_I85X(dev))
e70236a8
JB		 7415 dev_priv->display.get_display_clock_speed =
7416 i855_get_display_clock_speed;
7417 else /* 852, 830 */
7418 dev_priv->display.get_display_clock_speed =
7419 i830_get_display_clock_speed;
7420
7421 /* For FIFO watermark updates */
7f8a8569 7422 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7423 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7424 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7425 dev_priv->display.update_wm = ironlake_update_wm;
7426 else {
7427 DRM_DEBUG_KMS("Failed to get proper latency. "
7428 "Disable CxSR\n");
7429 dev_priv->display.update_wm = NULL;
1398261a 7430 }
674cf967 7431 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
1398261a
YL		 7432 } else if (IS_GEN6(dev)) {
7433 if (SNB_READ_WM0_LATENCY()) {
7434 dev_priv->display.update_wm = sandybridge_update_wm;
7435 } else {
7436 DRM_DEBUG_KMS("Failed to read display plane latency. "
7437 "Disable CxSR\n");
7438 dev_priv->display.update_wm = NULL;
7f8a8569 7439 }
674cf967 7440 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7f8a8569
ZW		 7441 } else
7442 dev_priv->display.update_wm = NULL;
7443 } else if (IS_PINEVIEW(dev)) {
d4294342 7444 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7445 dev_priv->is_ddr3,
d4294342
ZY		 7446 dev_priv->fsb_freq,
7447 dev_priv->mem_freq)) {
7448 DRM_INFO("failed to find known CxSR latency "
95534263 7449 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7450 "disabling CxSR\n",
95534263 7451 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7452 dev_priv->fsb_freq, dev_priv->mem_freq);
7453 /* Disable CxSR and never update its watermark again */
7454 pineview_disable_cxsr(dev);
7455 dev_priv->display.update_wm = NULL;
7456 } else
7457 dev_priv->display.update_wm = pineview_update_wm;
7458 } else if (IS_G4X(dev))
e70236a8 7459 dev_priv->display.update_wm = g4x_update_wm;
a6c45cf0 7460 else if (IS_GEN4(dev))
e70236a8 7461 dev_priv->display.update_wm = i965_update_wm;
a6c45cf0 7462 else if (IS_GEN3(dev)) {
e70236a8
JB		 7463 dev_priv->display.update_wm = i9xx_update_wm;
7464 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8f4695ed
AJ		 7465 } else if (IS_I85X(dev)) {
7466 dev_priv->display.update_wm = i9xx_update_wm;
7467 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
e70236a8 7468 } else {
8f4695ed
AJ		 7469 dev_priv->display.update_wm = i830_update_wm;
7470 if (IS_845G(dev))
e70236a8
JB		 7471 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7472 else
7473 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8
JB		 7474 }
7475}
7476
b690e96c
JB		 7477/*
7478 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7479 * resume, or other times. This quirk makes sure that's the case for
7480 * affected systems.
7481 */
7482static void quirk_pipea_force (struct drm_device *dev)
7483{
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485
7486 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7487 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7488}
7489
7490struct intel_quirk {
7491 int device;
7492 int subsystem_vendor;
7493 int subsystem_device;
7494 void (*hook)(struct drm_device *dev);
7495};
7496
7497struct intel_quirk intel_quirks[] = {
7498 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7499 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7500 /* HP Mini needs pipe A force quirk (LP: #322104) */
7501 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7502
7503 /* Thinkpad R31 needs pipe A force quirk */
7504 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7505 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7506 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7507
7508 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7509 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7510 /* ThinkPad X40 needs pipe A force quirk */
7511
7512 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7513 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7514
7515 /* 855 & before need to leave pipe A & dpll A up */
7516 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7517 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7518};
7519
7520static void intel_init_quirks(struct drm_device *dev)
7521{
7522 struct pci_dev *d = dev->pdev;
7523 int i;
7524
7525 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7526 struct intel_quirk *q = &intel_quirks[i];
7527
7528 if (d->device == q->device &&
7529 (d->subsystem_vendor == q->subsystem_vendor ||
7530 q->subsystem_vendor == PCI_ANY_ID) &&
7531 (d->subsystem_device == q->subsystem_device ||
7532 q->subsystem_device == PCI_ANY_ID))
7533 q->hook(dev);
7534 }
7535}
7536
9cce37f4
JB		 7537/* Disable the VGA plane that we never use */
7538static void i915_disable_vga(struct drm_device *dev)
7539{
7540 struct drm_i915_private *dev_priv = dev->dev_private;
7541 u8 sr1;
7542 u32 vga_reg;
7543
7544 if (HAS_PCH_SPLIT(dev))
7545 vga_reg = CPU_VGACNTRL;
7546 else
7547 vga_reg = VGACNTRL;
7548
7549 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7550 outb(1, VGA_SR_INDEX);
7551 sr1 = inb(VGA_SR_DATA);
7552 outb(sr1 | 1<<5, VGA_SR_DATA);
7553 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7554 udelay(300);
7555
7556 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7557 POSTING_READ(vga_reg);
7558}
7559
79e53945
JB		 7560void intel_modeset_init(struct drm_device *dev)
7561{
652c393a 7562 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7563 int i;
7564
7565 drm_mode_config_init(dev);
7566
7567 dev->mode_config.min_width = 0;
7568 dev->mode_config.min_height = 0;
7569
7570 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7571
b690e96c
JB		 7572 intel_init_quirks(dev);
7573
e70236a8
JB		 7574 intel_init_display(dev);
7575
a6c45cf0
CW		 7576 if (IS_GEN2(dev)) {
7577 dev->mode_config.max_width = 2048;
7578 dev->mode_config.max_height = 2048;
7579 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7580 dev->mode_config.max_width = 4096;
7581 dev->mode_config.max_height = 4096;
79e53945 7582 } else {
a6c45cf0
CW		 7583 dev->mode_config.max_width = 8192;
7584 dev->mode_config.max_height = 8192;
79e53945 7585 }
35c3047a 7586 dev->mode_config.fb_base = dev->agp->base;
79e53945 7587
28c97730 7588 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7589 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7590
a3524f1b 7591 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7592 intel_crtc_init(dev, i);
7593 }
7594
2c7111db
CW		 7595 /* Just disable it once at startup */
7596 i915_disable_vga(dev);
79e53945 7597 intel_setup_outputs(dev);
652c393a 7598
0cdab21f 7599 intel_enable_clock_gating(dev);
652c393a 7600
7648fa99 7601 if (IS_IRONLAKE_M(dev)) {
f97108d1 7602 ironlake_enable_drps(dev);
7648fa99
JB		 7603 intel_init_emon(dev);
7604 }
f97108d1 7605
3b8d8d91
JB		 7606 if (IS_GEN6(dev))
7607 gen6_enable_rps(dev_priv);
7608
652c393a
JB		 7609 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7610 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7611 (unsigned long)dev);
2c7111db
CW		 7612}
7613
7614void intel_modeset_gem_init(struct drm_device *dev)
7615{
7616 if (IS_IRONLAKE_M(dev))
7617 ironlake_enable_rc6(dev);
02e792fb
DV		 7618
7619 intel_setup_overlay(dev);
79e53945
JB		 7620}
7621
7622void intel_modeset_cleanup(struct drm_device *dev)
7623{
652c393a
JB		 7624 struct drm_i915_private *dev_priv = dev->dev_private;
7625 struct drm_crtc *crtc;
7626 struct intel_crtc *intel_crtc;
7627
f87ea761 7628 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7629 mutex_lock(&dev->struct_mutex);
7630
723bfd70
JB		 7631 intel_unregister_dsm_handler();
7632
7633
652c393a
JB		 7634 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7635 /* Skip inactive CRTCs */
7636 if (!crtc->fb)
7637 continue;
7638
7639 intel_crtc = to_intel_crtc(crtc);
3dec0095 7640 intel_increase_pllclock(crtc);
652c393a
JB		 7641 }
7642
e70236a8
JB		 7643 if (dev_priv->display.disable_fbc)
7644 dev_priv->display.disable_fbc(dev);
7645
f97108d1
JB		 7646 if (IS_IRONLAKE_M(dev))
7647 ironlake_disable_drps(dev);
3b8d8d91
JB		 7648 if (IS_GEN6(dev))
7649 gen6_disable_rps(dev);
f97108d1 7650
d5bb081b
JB		 7651 if (IS_IRONLAKE_M(dev))
7652 ironlake_disable_rc6(dev);
0cdab21f 7653
69341a5e
KH		 7654 mutex_unlock(&dev->struct_mutex);
7655
6c0d9350
DV		 7656 /* Disable the irq before mode object teardown, for the irq might
7657 * enqueue unpin/hotplug work. */
7658 drm_irq_uninstall(dev);
7659 cancel_work_sync(&dev_priv->hotplug_work);
7660
3dec0095
DV		 7661 /* Shut off idle work before the crtcs get freed. */
7662 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7663 intel_crtc = to_intel_crtc(crtc);
7664 del_timer_sync(&intel_crtc->idle_timer);
7665 }
7666 del_timer_sync(&dev_priv->idle_timer);
7667 cancel_work_sync(&dev_priv->idle_work);
7668
79e53945
JB		 7669 drm_mode_config_cleanup(dev);
7670}
7671
f1c79df3
ZW		 7672/*
7673 * Return which encoder is currently attached for connector.
7674 */
df0e9248 7675struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7676{
df0e9248
CW		 7677 return &intel_attached_encoder(connector)->base;
7678}
f1c79df3 7679
df0e9248
CW		 7680void intel_connector_attach_encoder(struct intel_connector *connector,
7681 struct intel_encoder *encoder)
7682{
7683 connector->encoder = encoder;
7684 drm_mode_connector_attach_encoder(&connector->base,
7685 &encoder->base);
79e53945 7686}
28d52043
DA		 7687
7688/*
7689 * set vga decode state - true == enable VGA decode
7690 */
7691int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7692{
7693 struct drm_i915_private *dev_priv = dev->dev_private;
7694 u16 gmch_ctrl;
7695
7696 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7697 if (state)
7698 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7699 else
7700 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7701 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7702 return 0;
7703}
c4a1d9e4
CW		 7704
7705#ifdef CONFIG_DEBUG_FS
7706#include <linux/seq_file.h>
7707
7708struct intel_display_error_state {
7709 struct intel_cursor_error_state {
7710 u32 control;
7711 u32 position;
7712 u32 base;
7713 u32 size;
7714 } cursor[2];
7715
7716 struct intel_pipe_error_state {
7717 u32 conf;
7718 u32 source;
7719
7720 u32 htotal;
7721 u32 hblank;
7722 u32 hsync;
7723 u32 vtotal;
7724 u32 vblank;
7725 u32 vsync;
7726 } pipe[2];
7727
7728 struct intel_plane_error_state {
7729 u32 control;
7730 u32 stride;
7731 u32 size;
7732 u32 pos;
7733 u32 addr;
7734 u32 surface;
7735 u32 tile_offset;
7736 } plane[2];
7737};
7738
7739struct intel_display_error_state *
7740intel_display_capture_error_state(struct drm_device *dev)
7741{
7742 drm_i915_private_t *dev_priv = dev->dev_private;
7743 struct intel_display_error_state *error;
7744 int i;
7745
7746 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7747 if (error == NULL)
7748 return NULL;
7749
7750 for (i = 0; i < 2; i++) {
7751 error->cursor[i].control = I915_READ(CURCNTR(i));
7752 error->cursor[i].position = I915_READ(CURPOS(i));
7753 error->cursor[i].base = I915_READ(CURBASE(i));
7754
7755 error->plane[i].control = I915_READ(DSPCNTR(i));
7756 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7757 error->plane[i].size = I915_READ(DSPSIZE(i));
7758 error->plane[i].pos= I915_READ(DSPPOS(i));
7759 error->plane[i].addr = I915_READ(DSPADDR(i));
7760 if (INTEL_INFO(dev)->gen >= 4) {
7761 error->plane[i].surface = I915_READ(DSPSURF(i));
7762 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7763 }
7764
7765 error->pipe[i].conf = I915_READ(PIPECONF(i));
7766 error->pipe[i].source = I915_READ(PIPESRC(i));
7767 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7768 error->pipe[i].hblank = I915_READ(HBLANK(i));
7769 error->pipe[i].hsync = I915_READ(HSYNC(i));
7770 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7771 error->pipe[i].vblank = I915_READ(VBLANK(i));
7772 error->pipe[i].vsync = I915_READ(VSYNC(i));
7773 }
7774
7775 return error;
7776}
7777
7778void
7779intel_display_print_error_state(struct seq_file *m,
7780 struct drm_device *dev,
7781 struct intel_display_error_state *error)
7782{
7783 int i;
7784
7785 for (i = 0; i < 2; i++) {
7786 seq_printf(m, "Pipe [%d]:\n", i);
7787 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7788 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7789 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7790 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7791 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7792 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7793 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7794 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7795
7796 seq_printf(m, "Plane [%d]:\n", i);
7797 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7798 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7799 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7800 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7801 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7802 if (INTEL_INFO(dev)->gen >= 4) {
7803 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7804 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7805 }
7806
7807 seq_printf(m, "Cursor [%d]:\n", i);
7808 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7809 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7810 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7811 }
7812}
7813#endif
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