]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
47 | |
48 | typedef struct { | |
0206e353 AJ |
49 | /* given values */ |
50 | int n; | |
51 | int m1, m2; | |
52 | int p1, p2; | |
53 | /* derived values */ | |
54 | int dot; | |
55 | int vco; | |
56 | int m; | |
57 | int p; | |
79e53945 JB |
58 | } intel_clock_t; |
59 | ||
60 | typedef struct { | |
0206e353 | 61 | int min, max; |
79e53945 JB |
62 | } intel_range_t; |
63 | ||
64 | typedef struct { | |
0206e353 AJ |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; | |
79e53945 JB |
67 | } intel_p2_t; |
68 | ||
69 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
70 | typedef struct intel_limit intel_limit_t; |
71 | struct intel_limit { | |
0206e353 AJ |
72 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
73 | intel_p2_t p2; | |
74 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 75 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 76 | }; |
79e53945 | 77 | |
2377b741 JB |
78 | /* FDI */ |
79 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
80 | ||
d2acd215 DV |
81 | int |
82 | intel_pch_rawclk(struct drm_device *dev) | |
83 | { | |
84 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85 | ||
86 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
87 | ||
88 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
89 | } | |
90 | ||
d4906093 ML |
91 | static bool |
92 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
93 | int target, int refclk, intel_clock_t *match_clock, |
94 | intel_clock_t *best_clock); | |
d4906093 ML |
95 | static bool |
96 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
97 | int target, int refclk, intel_clock_t *match_clock, |
98 | intel_clock_t *best_clock); | |
79e53945 | 99 | |
a4fc5ed6 KP |
100 | static bool |
101 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
102 | int target, int refclk, intel_clock_t *match_clock, |
103 | intel_clock_t *best_clock); | |
5eb08b69 | 104 | static bool |
f2b115e6 | 105 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
106 | int target, int refclk, intel_clock_t *match_clock, |
107 | intel_clock_t *best_clock); | |
a4fc5ed6 | 108 | |
a0c4da24 JB |
109 | static bool |
110 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
111 | int target, int refclk, intel_clock_t *match_clock, | |
112 | intel_clock_t *best_clock); | |
113 | ||
021357ac CW |
114 | static inline u32 /* units of 100MHz */ |
115 | intel_fdi_link_freq(struct drm_device *dev) | |
116 | { | |
8b99e68c CW |
117 | if (IS_GEN5(dev)) { |
118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
119 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
120 | } else | |
121 | return 27; | |
021357ac CW |
122 | } |
123 | ||
e4b36699 | 124 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
125 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, | |
127 | .n = { .min = 3, .max = 16 }, | |
128 | .m = { .min = 96, .max = 140 }, | |
129 | .m1 = { .min = 18, .max = 26 }, | |
130 | .m2 = { .min = 6, .max = 16 }, | |
131 | .p = { .min = 4, .max = 128 }, | |
132 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
133 | .p2 = { .dot_limit = 165000, |
134 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 135 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
136 | }; |
137 | ||
138 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
139 | .dot = { .min = 25000, .max = 350000 }, |
140 | .vco = { .min = 930000, .max = 1400000 }, | |
141 | .n = { .min = 3, .max = 16 }, | |
142 | .m = { .min = 96, .max = 140 }, | |
143 | .m1 = { .min = 18, .max = 26 }, | |
144 | .m2 = { .min = 6, .max = 16 }, | |
145 | .p = { .min = 4, .max = 128 }, | |
146 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
147 | .p2 = { .dot_limit = 165000, |
148 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 149 | .find_pll = intel_find_best_PLL, |
e4b36699 | 150 | }; |
273e27ca | 151 | |
e4b36699 | 152 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
153 | .dot = { .min = 20000, .max = 400000 }, |
154 | .vco = { .min = 1400000, .max = 2800000 }, | |
155 | .n = { .min = 1, .max = 6 }, | |
156 | .m = { .min = 70, .max = 120 }, | |
157 | .m1 = { .min = 10, .max = 22 }, | |
158 | .m2 = { .min = 5, .max = 9 }, | |
159 | .p = { .min = 5, .max = 80 }, | |
160 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 200000, |
162 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 163 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
164 | }; |
165 | ||
166 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
167 | .dot = { .min = 20000, .max = 400000 }, |
168 | .vco = { .min = 1400000, .max = 2800000 }, | |
169 | .n = { .min = 1, .max = 6 }, | |
170 | .m = { .min = 70, .max = 120 }, | |
171 | .m1 = { .min = 10, .max = 22 }, | |
172 | .m2 = { .min = 5, .max = 9 }, | |
173 | .p = { .min = 7, .max = 98 }, | |
174 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
175 | .p2 = { .dot_limit = 112000, |
176 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 177 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
178 | }; |
179 | ||
273e27ca | 180 | |
e4b36699 | 181 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
182 | .dot = { .min = 25000, .max = 270000 }, |
183 | .vco = { .min = 1750000, .max = 3500000}, | |
184 | .n = { .min = 1, .max = 4 }, | |
185 | .m = { .min = 104, .max = 138 }, | |
186 | .m1 = { .min = 17, .max = 23 }, | |
187 | .m2 = { .min = 5, .max = 11 }, | |
188 | .p = { .min = 10, .max = 30 }, | |
189 | .p1 = { .min = 1, .max = 3}, | |
190 | .p2 = { .dot_limit = 270000, | |
191 | .p2_slow = 10, | |
192 | .p2_fast = 10 | |
044c7c41 | 193 | }, |
d4906093 | 194 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
195 | }; |
196 | ||
197 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
198 | .dot = { .min = 22000, .max = 400000 }, |
199 | .vco = { .min = 1750000, .max = 3500000}, | |
200 | .n = { .min = 1, .max = 4 }, | |
201 | .m = { .min = 104, .max = 138 }, | |
202 | .m1 = { .min = 16, .max = 23 }, | |
203 | .m2 = { .min = 5, .max = 11 }, | |
204 | .p = { .min = 5, .max = 80 }, | |
205 | .p1 = { .min = 1, .max = 8}, | |
206 | .p2 = { .dot_limit = 165000, | |
207 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 208 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
209 | }; |
210 | ||
211 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
212 | .dot = { .min = 20000, .max = 115000 }, |
213 | .vco = { .min = 1750000, .max = 3500000 }, | |
214 | .n = { .min = 1, .max = 3 }, | |
215 | .m = { .min = 104, .max = 138 }, | |
216 | .m1 = { .min = 17, .max = 23 }, | |
217 | .m2 = { .min = 5, .max = 11 }, | |
218 | .p = { .min = 28, .max = 112 }, | |
219 | .p1 = { .min = 2, .max = 8 }, | |
220 | .p2 = { .dot_limit = 0, | |
221 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 222 | }, |
d4906093 | 223 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
224 | }; |
225 | ||
226 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
227 | .dot = { .min = 80000, .max = 224000 }, |
228 | .vco = { .min = 1750000, .max = 3500000 }, | |
229 | .n = { .min = 1, .max = 3 }, | |
230 | .m = { .min = 104, .max = 138 }, | |
231 | .m1 = { .min = 17, .max = 23 }, | |
232 | .m2 = { .min = 5, .max = 11 }, | |
233 | .p = { .min = 14, .max = 42 }, | |
234 | .p1 = { .min = 2, .max = 6 }, | |
235 | .p2 = { .dot_limit = 0, | |
236 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 237 | }, |
d4906093 | 238 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
242 | .dot = { .min = 161670, .max = 227000 }, |
243 | .vco = { .min = 1750000, .max = 3500000}, | |
244 | .n = { .min = 1, .max = 2 }, | |
245 | .m = { .min = 97, .max = 108 }, | |
246 | .m1 = { .min = 0x10, .max = 0x12 }, | |
247 | .m2 = { .min = 0x05, .max = 0x06 }, | |
248 | .p = { .min = 10, .max = 20 }, | |
249 | .p1 = { .min = 1, .max = 2}, | |
250 | .p2 = { .dot_limit = 0, | |
273e27ca | 251 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 252 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000}, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 258 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
259 | .n = { .min = 3, .max = 6 }, |
260 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 261 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
262 | .m1 = { .min = 0, .max = 0 }, |
263 | .m2 = { .min = 0, .max = 254 }, | |
264 | .p = { .min = 5, .max = 80 }, | |
265 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
266 | .p2 = { .dot_limit = 200000, |
267 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 268 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
269 | }; |
270 | ||
f2b115e6 | 271 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
272 | .dot = { .min = 20000, .max = 400000 }, |
273 | .vco = { .min = 1700000, .max = 3500000 }, | |
274 | .n = { .min = 3, .max = 6 }, | |
275 | .m = { .min = 2, .max = 256 }, | |
276 | .m1 = { .min = 0, .max = 0 }, | |
277 | .m2 = { .min = 0, .max = 254 }, | |
278 | .p = { .min = 7, .max = 112 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
280 | .p2 = { .dot_limit = 112000, |
281 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 282 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
283 | }; |
284 | ||
273e27ca EA |
285 | /* Ironlake / Sandybridge |
286 | * | |
287 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
288 | * the range value for them is (actual_value - 2). | |
289 | */ | |
b91ad0ec | 290 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
291 | .dot = { .min = 25000, .max = 350000 }, |
292 | .vco = { .min = 1760000, .max = 3510000 }, | |
293 | .n = { .min = 1, .max = 5 }, | |
294 | .m = { .min = 79, .max = 127 }, | |
295 | .m1 = { .min = 12, .max = 22 }, | |
296 | .m2 = { .min = 5, .max = 9 }, | |
297 | .p = { .min = 5, .max = 80 }, | |
298 | .p1 = { .min = 1, .max = 8 }, | |
299 | .p2 = { .dot_limit = 225000, | |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 301 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
302 | }; |
303 | ||
b91ad0ec | 304 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 350000 }, |
306 | .vco = { .min = 1760000, .max = 3510000 }, | |
307 | .n = { .min = 1, .max = 3 }, | |
308 | .m = { .min = 79, .max = 118 }, | |
309 | .m1 = { .min = 12, .max = 22 }, | |
310 | .m2 = { .min = 5, .max = 9 }, | |
311 | .p = { .min = 28, .max = 112 }, | |
312 | .p1 = { .min = 2, .max = 8 }, | |
313 | .p2 = { .dot_limit = 225000, | |
314 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
315 | .find_pll = intel_g4x_find_best_PLL, |
316 | }; | |
317 | ||
318 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 127 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 14, .max = 56 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
329 | .find_pll = intel_g4x_find_best_PLL, |
330 | }; | |
331 | ||
273e27ca | 332 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 333 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 2 }, | |
337 | .m = { .min = 79, .max = 126 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 341 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
342 | .p2 = { .dot_limit = 225000, |
343 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
344 | .find_pll = intel_g4x_find_best_PLL, |
345 | }; | |
346 | ||
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 3 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
358 | .find_pll = intel_g4x_find_best_PLL, |
359 | }; | |
360 | ||
361 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
362 | .dot = { .min = 25000, .max = 350000 }, |
363 | .vco = { .min = 1760000, .max = 3510000}, | |
364 | .n = { .min = 1, .max = 2 }, | |
365 | .m = { .min = 81, .max = 90 }, | |
366 | .m1 = { .min = 12, .max = 22 }, | |
367 | .m2 = { .min = 5, .max = 9 }, | |
368 | .p = { .min = 10, .max = 20 }, | |
369 | .p1 = { .min = 1, .max = 2}, | |
370 | .p2 = { .dot_limit = 0, | |
273e27ca | 371 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 372 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
373 | }; |
374 | ||
a0c4da24 JB |
375 | static const intel_limit_t intel_limits_vlv_dac = { |
376 | .dot = { .min = 25000, .max = 270000 }, | |
377 | .vco = { .min = 4000000, .max = 6000000 }, | |
378 | .n = { .min = 1, .max = 7 }, | |
379 | .m = { .min = 22, .max = 450 }, /* guess */ | |
380 | .m1 = { .min = 2, .max = 3 }, | |
381 | .m2 = { .min = 11, .max = 156 }, | |
382 | .p = { .min = 10, .max = 30 }, | |
383 | .p1 = { .min = 2, .max = 3 }, | |
384 | .p2 = { .dot_limit = 270000, | |
385 | .p2_slow = 2, .p2_fast = 20 }, | |
386 | .find_pll = intel_vlv_find_best_pll, | |
387 | }; | |
388 | ||
389 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
390 | .dot = { .min = 20000, .max = 165000 }, | |
17dc9257 | 391 | .vco = { .min = 4000000, .max = 5994000}, |
a0c4da24 JB |
392 | .n = { .min = 1, .max = 7 }, |
393 | .m = { .min = 60, .max = 300 }, /* guess */ | |
394 | .m1 = { .min = 2, .max = 3 }, | |
395 | .m2 = { .min = 11, .max = 156 }, | |
396 | .p = { .min = 10, .max = 30 }, | |
397 | .p1 = { .min = 2, .max = 3 }, | |
398 | .p2 = { .dot_limit = 270000, | |
399 | .p2_slow = 2, .p2_fast = 20 }, | |
400 | .find_pll = intel_vlv_find_best_pll, | |
401 | }; | |
402 | ||
403 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
404 | .dot = { .min = 25000, .max = 270000 }, |
405 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 406 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 407 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
408 | .m1 = { .min = 2, .max = 3 }, |
409 | .m2 = { .min = 11, .max = 156 }, | |
410 | .p = { .min = 10, .max = 30 }, | |
411 | .p1 = { .min = 2, .max = 3 }, | |
412 | .p2 = { .dot_limit = 270000, | |
413 | .p2_slow = 2, .p2_fast = 20 }, | |
414 | .find_pll = intel_vlv_find_best_pll, | |
415 | }; | |
416 | ||
57f350b6 JB |
417 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
418 | { | |
419 | unsigned long flags; | |
420 | u32 val = 0; | |
421 | ||
422 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
423 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
424 | DRM_ERROR("DPIO idle wait timed out\n"); | |
425 | goto out_unlock; | |
426 | } | |
427 | ||
428 | I915_WRITE(DPIO_REG, reg); | |
429 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
430 | DPIO_BYTE); | |
431 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
432 | DRM_ERROR("DPIO read wait timed out\n"); | |
433 | goto out_unlock; | |
434 | } | |
435 | val = I915_READ(DPIO_DATA); | |
436 | ||
437 | out_unlock: | |
438 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
439 | return val; | |
440 | } | |
441 | ||
a0c4da24 JB |
442 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
443 | u32 val) | |
444 | { | |
445 | unsigned long flags; | |
446 | ||
447 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
448 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
449 | DRM_ERROR("DPIO idle wait timed out\n"); | |
450 | goto out_unlock; | |
451 | } | |
452 | ||
453 | I915_WRITE(DPIO_DATA, val); | |
454 | I915_WRITE(DPIO_REG, reg); | |
455 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
456 | DPIO_BYTE); | |
457 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
458 | DRM_ERROR("DPIO write wait timed out\n"); | |
459 | ||
460 | out_unlock: | |
461 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
462 | } | |
463 | ||
57f350b6 JB |
464 | static void vlv_init_dpio(struct drm_device *dev) |
465 | { | |
466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
467 | ||
468 | /* Reset the DPIO config */ | |
469 | I915_WRITE(DPIO_CTL, 0); | |
470 | POSTING_READ(DPIO_CTL); | |
471 | I915_WRITE(DPIO_CTL, 1); | |
472 | POSTING_READ(DPIO_CTL); | |
473 | } | |
474 | ||
1b894b59 CW |
475 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
476 | int refclk) | |
2c07245f | 477 | { |
b91ad0ec | 478 | struct drm_device *dev = crtc->dev; |
2c07245f | 479 | const intel_limit_t *limit; |
b91ad0ec ZW |
480 | |
481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 482 | if (intel_is_dual_link_lvds(dev)) { |
b91ad0ec | 483 | /* LVDS dual channel */ |
1b894b59 | 484 | if (refclk == 100000) |
b91ad0ec ZW |
485 | limit = &intel_limits_ironlake_dual_lvds_100m; |
486 | else | |
487 | limit = &intel_limits_ironlake_dual_lvds; | |
488 | } else { | |
1b894b59 | 489 | if (refclk == 100000) |
b91ad0ec ZW |
490 | limit = &intel_limits_ironlake_single_lvds_100m; |
491 | else | |
492 | limit = &intel_limits_ironlake_single_lvds; | |
493 | } | |
494 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
547dc041 | 495 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
4547668a | 496 | limit = &intel_limits_ironlake_display_port; |
2c07245f | 497 | else |
b91ad0ec | 498 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
499 | |
500 | return limit; | |
501 | } | |
502 | ||
044c7c41 ML |
503 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
504 | { | |
505 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
506 | const intel_limit_t *limit; |
507 | ||
508 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 509 | if (intel_is_dual_link_lvds(dev)) |
044c7c41 | 510 | /* LVDS with dual channel */ |
e4b36699 | 511 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
512 | else |
513 | /* LVDS with dual channel */ | |
e4b36699 | 514 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
515 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
516 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 517 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 518 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 519 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 520 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 521 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 522 | } else /* The option is for other outputs */ |
e4b36699 | 523 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
524 | |
525 | return limit; | |
526 | } | |
527 | ||
1b894b59 | 528 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
529 | { |
530 | struct drm_device *dev = crtc->dev; | |
531 | const intel_limit_t *limit; | |
532 | ||
bad720ff | 533 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 534 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 535 | else if (IS_G4X(dev)) { |
044c7c41 | 536 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 537 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 538 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 539 | limit = &intel_limits_pineview_lvds; |
2177832f | 540 | else |
f2b115e6 | 541 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
542 | } else if (IS_VALLEYVIEW(dev)) { |
543 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
544 | limit = &intel_limits_vlv_dac; | |
545 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
546 | limit = &intel_limits_vlv_hdmi; | |
547 | else | |
548 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
549 | } else if (!IS_GEN2(dev)) { |
550 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
551 | limit = &intel_limits_i9xx_lvds; | |
552 | else | |
553 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
554 | } else { |
555 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 556 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 557 | else |
e4b36699 | 558 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
559 | } |
560 | return limit; | |
561 | } | |
562 | ||
f2b115e6 AJ |
563 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
564 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 565 | { |
2177832f SL |
566 | clock->m = clock->m2 + 2; |
567 | clock->p = clock->p1 * clock->p2; | |
568 | clock->vco = refclk * clock->m / clock->n; | |
569 | clock->dot = clock->vco / clock->p; | |
570 | } | |
571 | ||
572 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
573 | { | |
f2b115e6 AJ |
574 | if (IS_PINEVIEW(dev)) { |
575 | pineview_clock(refclk, clock); | |
2177832f SL |
576 | return; |
577 | } | |
79e53945 JB |
578 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
579 | clock->p = clock->p1 * clock->p2; | |
580 | clock->vco = refclk * clock->m / (clock->n + 2); | |
581 | clock->dot = clock->vco / clock->p; | |
582 | } | |
583 | ||
79e53945 JB |
584 | /** |
585 | * Returns whether any output on the specified pipe is of the specified type | |
586 | */ | |
4ef69c7a | 587 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 588 | { |
4ef69c7a | 589 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
590 | struct intel_encoder *encoder; |
591 | ||
6c2b7c12 DV |
592 | for_each_encoder_on_crtc(dev, crtc, encoder) |
593 | if (encoder->type == type) | |
4ef69c7a CW |
594 | return true; |
595 | ||
596 | return false; | |
79e53945 JB |
597 | } |
598 | ||
7c04d1d9 | 599 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
600 | /** |
601 | * Returns whether the given set of divisors are valid for a given refclk with | |
602 | * the given connectors. | |
603 | */ | |
604 | ||
1b894b59 CW |
605 | static bool intel_PLL_is_valid(struct drm_device *dev, |
606 | const intel_limit_t *limit, | |
607 | const intel_clock_t *clock) | |
79e53945 | 608 | { |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 612 | INTELPllInvalid("p out of range\n"); |
79e53945 | 613 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 614 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 615 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 616 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 617 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 618 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 619 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 620 | INTELPllInvalid("m out of range\n"); |
79e53945 | 621 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 622 | INTELPllInvalid("n out of range\n"); |
79e53945 | 623 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 624 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
625 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
626 | * connector, etc., rather than just a single range. | |
627 | */ | |
628 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 629 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
630 | |
631 | return true; | |
632 | } | |
633 | ||
d4906093 ML |
634 | static bool |
635 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
636 | int target, int refclk, intel_clock_t *match_clock, |
637 | intel_clock_t *best_clock) | |
d4906093 | 638 | |
79e53945 JB |
639 | { |
640 | struct drm_device *dev = crtc->dev; | |
79e53945 | 641 | intel_clock_t clock; |
79e53945 JB |
642 | int err = target; |
643 | ||
a210b028 | 644 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 645 | /* |
a210b028 DV |
646 | * For LVDS just rely on its current settings for dual-channel. |
647 | * We haven't figured out how to reliably set up different | |
648 | * single/dual channel state, if we even can. | |
79e53945 | 649 | */ |
1974cad0 | 650 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
651 | clock.p2 = limit->p2.p2_fast; |
652 | else | |
653 | clock.p2 = limit->p2.p2_slow; | |
654 | } else { | |
655 | if (target < limit->p2.dot_limit) | |
656 | clock.p2 = limit->p2.p2_slow; | |
657 | else | |
658 | clock.p2 = limit->p2.p2_fast; | |
659 | } | |
660 | ||
0206e353 | 661 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 662 | |
42158660 ZY |
663 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
664 | clock.m1++) { | |
665 | for (clock.m2 = limit->m2.min; | |
666 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
667 | /* m1 is always 0 in Pineview */ |
668 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
669 | break; |
670 | for (clock.n = limit->n.min; | |
671 | clock.n <= limit->n.max; clock.n++) { | |
672 | for (clock.p1 = limit->p1.min; | |
673 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
674 | int this_err; |
675 | ||
2177832f | 676 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
677 | if (!intel_PLL_is_valid(dev, limit, |
678 | &clock)) | |
79e53945 | 679 | continue; |
cec2f356 SP |
680 | if (match_clock && |
681 | clock.p != match_clock->p) | |
682 | continue; | |
79e53945 JB |
683 | |
684 | this_err = abs(clock.dot - target); | |
685 | if (this_err < err) { | |
686 | *best_clock = clock; | |
687 | err = this_err; | |
688 | } | |
689 | } | |
690 | } | |
691 | } | |
692 | } | |
693 | ||
694 | return (err != target); | |
695 | } | |
696 | ||
d4906093 ML |
697 | static bool |
698 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
699 | int target, int refclk, intel_clock_t *match_clock, |
700 | intel_clock_t *best_clock) | |
d4906093 ML |
701 | { |
702 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
703 | intel_clock_t clock; |
704 | int max_n; | |
705 | bool found; | |
6ba770dc AJ |
706 | /* approximately equals target * 0.00585 */ |
707 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
708 | found = false; |
709 | ||
710 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
711 | int lvds_reg; |
712 | ||
c619eed4 | 713 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
714 | lvds_reg = PCH_LVDS; |
715 | else | |
716 | lvds_reg = LVDS; | |
1974cad0 | 717 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
718 | clock.p2 = limit->p2.p2_fast; |
719 | else | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | } else { | |
722 | if (target < limit->p2.dot_limit) | |
723 | clock.p2 = limit->p2.p2_slow; | |
724 | else | |
725 | clock.p2 = limit->p2.p2_fast; | |
726 | } | |
727 | ||
728 | memset(best_clock, 0, sizeof(*best_clock)); | |
729 | max_n = limit->n.max; | |
f77f13e2 | 730 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 731 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 732 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
733 | for (clock.m1 = limit->m1.max; |
734 | clock.m1 >= limit->m1.min; clock.m1--) { | |
735 | for (clock.m2 = limit->m2.max; | |
736 | clock.m2 >= limit->m2.min; clock.m2--) { | |
737 | for (clock.p1 = limit->p1.max; | |
738 | clock.p1 >= limit->p1.min; clock.p1--) { | |
739 | int this_err; | |
740 | ||
2177832f | 741 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
d4906093 | 744 | continue; |
cec2f356 SP |
745 | if (match_clock && |
746 | clock.p != match_clock->p) | |
747 | continue; | |
1b894b59 CW |
748 | |
749 | this_err = abs(clock.dot - target); | |
d4906093 ML |
750 | if (this_err < err_most) { |
751 | *best_clock = clock; | |
752 | err_most = this_err; | |
753 | max_n = clock.n; | |
754 | found = true; | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
2c07245f ZW |
760 | return found; |
761 | } | |
762 | ||
5eb08b69 | 763 | static bool |
f2b115e6 | 764 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
765 | int target, int refclk, intel_clock_t *match_clock, |
766 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
767 | { |
768 | struct drm_device *dev = crtc->dev; | |
769 | intel_clock_t clock; | |
4547668a | 770 | |
5eb08b69 ZW |
771 | if (target < 200000) { |
772 | clock.n = 1; | |
773 | clock.p1 = 2; | |
774 | clock.p2 = 10; | |
775 | clock.m1 = 12; | |
776 | clock.m2 = 9; | |
777 | } else { | |
778 | clock.n = 2; | |
779 | clock.p1 = 1; | |
780 | clock.p2 = 10; | |
781 | clock.m1 = 14; | |
782 | clock.m2 = 8; | |
783 | } | |
784 | intel_clock(dev, refclk, &clock); | |
785 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
786 | return true; | |
787 | } | |
788 | ||
a4fc5ed6 KP |
789 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
790 | static bool | |
791 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
792 | int target, int refclk, intel_clock_t *match_clock, |
793 | intel_clock_t *best_clock) | |
a4fc5ed6 | 794 | { |
5eddb70b CW |
795 | intel_clock_t clock; |
796 | if (target < 200000) { | |
797 | clock.p1 = 2; | |
798 | clock.p2 = 10; | |
799 | clock.n = 2; | |
800 | clock.m1 = 23; | |
801 | clock.m2 = 8; | |
802 | } else { | |
803 | clock.p1 = 1; | |
804 | clock.p2 = 10; | |
805 | clock.n = 1; | |
806 | clock.m1 = 14; | |
807 | clock.m2 = 2; | |
808 | } | |
809 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
810 | clock.p = (clock.p1 * clock.p2); | |
811 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
812 | clock.vco = 0; | |
813 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
814 | return true; | |
a4fc5ed6 | 815 | } |
a0c4da24 JB |
816 | static bool |
817 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
818 | int target, int refclk, intel_clock_t *match_clock, | |
819 | intel_clock_t *best_clock) | |
820 | { | |
821 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
822 | u32 m, n, fastclk; | |
823 | u32 updrate, minupdate, fracbits, p; | |
824 | unsigned long bestppm, ppm, absppm; | |
825 | int dotclk, flag; | |
826 | ||
af447bd3 | 827 | flag = 0; |
a0c4da24 JB |
828 | dotclk = target * 1000; |
829 | bestppm = 1000000; | |
830 | ppm = absppm = 0; | |
831 | fastclk = dotclk / (2*100); | |
832 | updrate = 0; | |
833 | minupdate = 19200; | |
834 | fracbits = 1; | |
835 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
836 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
837 | ||
838 | /* based on hardware requirement, prefer smaller n to precision */ | |
839 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
840 | updrate = refclk / n; | |
841 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
842 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
843 | if (p2 > 10) | |
844 | p2 = p2 - 1; | |
845 | p = p1 * p2; | |
846 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
847 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
848 | m2 = (((2*(fastclk * p * n / m1 )) + | |
849 | refclk) / (2*refclk)); | |
850 | m = m1 * m2; | |
851 | vco = updrate * m; | |
852 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
853 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
854 | absppm = (ppm > 0) ? ppm : (-ppm); | |
855 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
856 | bestppm = 0; | |
857 | flag = 1; | |
858 | } | |
859 | if (absppm < bestppm - 10) { | |
860 | bestppm = absppm; | |
861 | flag = 1; | |
862 | } | |
863 | if (flag) { | |
864 | bestn = n; | |
865 | bestm1 = m1; | |
866 | bestm2 = m2; | |
867 | bestp1 = p1; | |
868 | bestp2 = p2; | |
869 | flag = 0; | |
870 | } | |
871 | } | |
872 | } | |
873 | } | |
874 | } | |
875 | } | |
876 | best_clock->n = bestn; | |
877 | best_clock->m1 = bestm1; | |
878 | best_clock->m2 = bestm2; | |
879 | best_clock->p1 = bestp1; | |
880 | best_clock->p2 = bestp2; | |
881 | ||
882 | return true; | |
883 | } | |
a4fc5ed6 | 884 | |
a5c961d1 PZ |
885 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
886 | enum pipe pipe) | |
887 | { | |
888 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890 | ||
891 | return intel_crtc->cpu_transcoder; | |
892 | } | |
893 | ||
a928d536 PZ |
894 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
895 | { | |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
897 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
898 | ||
899 | frame = I915_READ(frame_reg); | |
900 | ||
901 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
902 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
903 | } | |
904 | ||
9d0498a2 JB |
905 | /** |
906 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
907 | * @dev: drm device | |
908 | * @pipe: pipe to wait for | |
909 | * | |
910 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
911 | * mode setting code. | |
912 | */ | |
913 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 914 | { |
9d0498a2 | 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 916 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 917 | |
a928d536 PZ |
918 | if (INTEL_INFO(dev)->gen >= 5) { |
919 | ironlake_wait_for_vblank(dev, pipe); | |
920 | return; | |
921 | } | |
922 | ||
300387c0 CW |
923 | /* Clear existing vblank status. Note this will clear any other |
924 | * sticky status fields as well. | |
925 | * | |
926 | * This races with i915_driver_irq_handler() with the result | |
927 | * that either function could miss a vblank event. Here it is not | |
928 | * fatal, as we will either wait upon the next vblank interrupt or | |
929 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
930 | * called during modeset at which time the GPU should be idle and | |
931 | * should *not* be performing page flips and thus not waiting on | |
932 | * vblanks... | |
933 | * Currently, the result of us stealing a vblank from the irq | |
934 | * handler is that a single frame will be skipped during swapbuffers. | |
935 | */ | |
936 | I915_WRITE(pipestat_reg, | |
937 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
938 | ||
9d0498a2 | 939 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
940 | if (wait_for(I915_READ(pipestat_reg) & |
941 | PIPE_VBLANK_INTERRUPT_STATUS, | |
942 | 50)) | |
9d0498a2 JB |
943 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
944 | } | |
945 | ||
ab7ad7f6 KP |
946 | /* |
947 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
948 | * @dev: drm device |
949 | * @pipe: pipe to wait for | |
950 | * | |
951 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
952 | * spinning on the vblank interrupt status bit, since we won't actually | |
953 | * see an interrupt when the pipe is disabled. | |
954 | * | |
ab7ad7f6 KP |
955 | * On Gen4 and above: |
956 | * wait for the pipe register state bit to turn off | |
957 | * | |
958 | * Otherwise: | |
959 | * wait for the display line value to settle (it usually | |
960 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 961 | * |
9d0498a2 | 962 | */ |
58e10eb9 | 963 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
964 | { |
965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
966 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
967 | pipe); | |
ab7ad7f6 KP |
968 | |
969 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 970 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
971 | |
972 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
973 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
974 | 100)) | |
284637d9 | 975 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 976 | } else { |
837ba00f | 977 | u32 last_line, line_mask; |
58e10eb9 | 978 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
979 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
980 | ||
837ba00f PZ |
981 | if (IS_GEN2(dev)) |
982 | line_mask = DSL_LINEMASK_GEN2; | |
983 | else | |
984 | line_mask = DSL_LINEMASK_GEN3; | |
985 | ||
ab7ad7f6 KP |
986 | /* Wait for the display line to settle */ |
987 | do { | |
837ba00f | 988 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 989 | mdelay(5); |
837ba00f | 990 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
991 | time_after(timeout, jiffies)); |
992 | if (time_after(jiffies, timeout)) | |
284637d9 | 993 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 994 | } |
79e53945 JB |
995 | } |
996 | ||
b24e7179 JB |
997 | static const char *state_string(bool enabled) |
998 | { | |
999 | return enabled ? "on" : "off"; | |
1000 | } | |
1001 | ||
1002 | /* Only for pre-ILK configs */ | |
1003 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1004 | enum pipe pipe, bool state) | |
1005 | { | |
1006 | int reg; | |
1007 | u32 val; | |
1008 | bool cur_state; | |
1009 | ||
1010 | reg = DPLL(pipe); | |
1011 | val = I915_READ(reg); | |
1012 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1013 | WARN(cur_state != state, | |
1014 | "PLL state assertion failure (expected %s, current %s)\n", | |
1015 | state_string(state), state_string(cur_state)); | |
1016 | } | |
1017 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1018 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1019 | ||
040484af JB |
1020 | /* For ILK+ */ |
1021 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1022 | struct intel_pch_pll *pll, |
1023 | struct intel_crtc *crtc, | |
1024 | bool state) | |
040484af | 1025 | { |
040484af JB |
1026 | u32 val; |
1027 | bool cur_state; | |
1028 | ||
9d82aa17 ED |
1029 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1030 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1031 | return; | |
1032 | } | |
1033 | ||
92b27b08 CW |
1034 | if (WARN (!pll, |
1035 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1036 | return; |
ee7b9f93 | 1037 | |
92b27b08 CW |
1038 | val = I915_READ(pll->pll_reg); |
1039 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1040 | WARN(cur_state != state, | |
1041 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1042 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1043 | ||
1044 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1045 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1046 | u32 pch_dpll; |
1047 | ||
1048 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1049 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1050 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1051 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1052 | cur_state, crtc->pipe, pch_dpll)) { | |
1053 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1054 | WARN(cur_state != state, | |
1055 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1056 | pll->pll_reg == _PCH_DPLL_B, | |
1057 | state_string(state), | |
1058 | crtc->pipe, | |
1059 | val); | |
1060 | } | |
d3ccbe86 | 1061 | } |
040484af | 1062 | } |
92b27b08 CW |
1063 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1064 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1065 | |
1066 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1067 | enum pipe pipe, bool state) | |
1068 | { | |
1069 | int reg; | |
1070 | u32 val; | |
1071 | bool cur_state; | |
ad80a810 PZ |
1072 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1073 | pipe); | |
040484af | 1074 | |
affa9354 PZ |
1075 | if (HAS_DDI(dev_priv->dev)) { |
1076 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1077 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1078 | val = I915_READ(reg); |
ad80a810 | 1079 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1080 | } else { |
1081 | reg = FDI_TX_CTL(pipe); | |
1082 | val = I915_READ(reg); | |
1083 | cur_state = !!(val & FDI_TX_ENABLE); | |
1084 | } | |
040484af JB |
1085 | WARN(cur_state != state, |
1086 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1087 | state_string(state), state_string(cur_state)); | |
1088 | } | |
1089 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1090 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1091 | ||
1092 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1093 | enum pipe pipe, bool state) | |
1094 | { | |
1095 | int reg; | |
1096 | u32 val; | |
1097 | bool cur_state; | |
1098 | ||
d63fa0dc PZ |
1099 | reg = FDI_RX_CTL(pipe); |
1100 | val = I915_READ(reg); | |
1101 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1102 | WARN(cur_state != state, |
1103 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1104 | state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1107 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1108 | ||
1109 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1110 | enum pipe pipe) | |
1111 | { | |
1112 | int reg; | |
1113 | u32 val; | |
1114 | ||
1115 | /* ILK FDI PLL is always enabled */ | |
1116 | if (dev_priv->info->gen == 5) | |
1117 | return; | |
1118 | ||
bf507ef7 | 1119 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1120 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1121 | return; |
1122 | ||
040484af JB |
1123 | reg = FDI_TX_CTL(pipe); |
1124 | val = I915_READ(reg); | |
1125 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1126 | } | |
1127 | ||
1128 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1129 | enum pipe pipe) | |
1130 | { | |
1131 | int reg; | |
1132 | u32 val; | |
1133 | ||
1134 | reg = FDI_RX_CTL(pipe); | |
1135 | val = I915_READ(reg); | |
1136 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1137 | } | |
1138 | ||
ea0760cf JB |
1139 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1140 | enum pipe pipe) | |
1141 | { | |
1142 | int pp_reg, lvds_reg; | |
1143 | u32 val; | |
1144 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1145 | bool locked = true; |
ea0760cf JB |
1146 | |
1147 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1148 | pp_reg = PCH_PP_CONTROL; | |
1149 | lvds_reg = PCH_LVDS; | |
1150 | } else { | |
1151 | pp_reg = PP_CONTROL; | |
1152 | lvds_reg = LVDS; | |
1153 | } | |
1154 | ||
1155 | val = I915_READ(pp_reg); | |
1156 | if (!(val & PANEL_POWER_ON) || | |
1157 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1158 | locked = false; | |
1159 | ||
1160 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1161 | panel_pipe = PIPE_B; | |
1162 | ||
1163 | WARN(panel_pipe == pipe && locked, | |
1164 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1165 | pipe_name(pipe)); |
ea0760cf JB |
1166 | } |
1167 | ||
b840d907 JB |
1168 | void assert_pipe(struct drm_i915_private *dev_priv, |
1169 | enum pipe pipe, bool state) | |
b24e7179 JB |
1170 | { |
1171 | int reg; | |
1172 | u32 val; | |
63d7bbe9 | 1173 | bool cur_state; |
702e7a56 PZ |
1174 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1175 | pipe); | |
b24e7179 | 1176 | |
8e636784 DV |
1177 | /* if we need the pipe A quirk it must be always on */ |
1178 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1179 | state = true; | |
1180 | ||
702e7a56 | 1181 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1182 | val = I915_READ(reg); |
63d7bbe9 JB |
1183 | cur_state = !!(val & PIPECONF_ENABLE); |
1184 | WARN(cur_state != state, | |
1185 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1186 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1187 | } |
1188 | ||
931872fc CW |
1189 | static void assert_plane(struct drm_i915_private *dev_priv, |
1190 | enum plane plane, bool state) | |
b24e7179 JB |
1191 | { |
1192 | int reg; | |
1193 | u32 val; | |
931872fc | 1194 | bool cur_state; |
b24e7179 JB |
1195 | |
1196 | reg = DSPCNTR(plane); | |
1197 | val = I915_READ(reg); | |
931872fc CW |
1198 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1199 | WARN(cur_state != state, | |
1200 | "plane %c assertion failure (expected %s, current %s)\n", | |
1201 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1202 | } |
1203 | ||
931872fc CW |
1204 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1205 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1206 | ||
b24e7179 JB |
1207 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1208 | enum pipe pipe) | |
1209 | { | |
1210 | int reg, i; | |
1211 | u32 val; | |
1212 | int cur_pipe; | |
1213 | ||
19ec1358 | 1214 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1215 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1216 | reg = DSPCNTR(pipe); | |
1217 | val = I915_READ(reg); | |
1218 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1219 | "plane %c assertion failure, should be disabled but not\n", | |
1220 | plane_name(pipe)); | |
19ec1358 | 1221 | return; |
28c05794 | 1222 | } |
19ec1358 | 1223 | |
b24e7179 JB |
1224 | /* Need to check both planes against the pipe */ |
1225 | for (i = 0; i < 2; i++) { | |
1226 | reg = DSPCNTR(i); | |
1227 | val = I915_READ(reg); | |
1228 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1229 | DISPPLANE_SEL_PIPE_SHIFT; | |
1230 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1231 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1232 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1233 | } |
1234 | } | |
1235 | ||
92f2584a JB |
1236 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1237 | { | |
1238 | u32 val; | |
1239 | bool enabled; | |
1240 | ||
9d82aa17 ED |
1241 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1242 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1243 | return; | |
1244 | } | |
1245 | ||
92f2584a JB |
1246 | val = I915_READ(PCH_DREF_CONTROL); |
1247 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1248 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1249 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1250 | } | |
1251 | ||
1252 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1253 | enum pipe pipe) | |
1254 | { | |
1255 | int reg; | |
1256 | u32 val; | |
1257 | bool enabled; | |
1258 | ||
1259 | reg = TRANSCONF(pipe); | |
1260 | val = I915_READ(reg); | |
1261 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1262 | WARN(enabled, |
1263 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1264 | pipe_name(pipe)); | |
92f2584a JB |
1265 | } |
1266 | ||
4e634389 KP |
1267 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1269 | { |
1270 | if ((val & DP_PORT_EN) == 0) | |
1271 | return false; | |
1272 | ||
1273 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1274 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1275 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1276 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1277 | return false; | |
1278 | } else { | |
1279 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1280 | return false; | |
1281 | } | |
1282 | return true; | |
1283 | } | |
1284 | ||
1519b995 KP |
1285 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1286 | enum pipe pipe, u32 val) | |
1287 | { | |
1288 | if ((val & PORT_ENABLE) == 0) | |
1289 | return false; | |
1290 | ||
1291 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1292 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1293 | return false; | |
1294 | } else { | |
1295 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1296 | return false; | |
1297 | } | |
1298 | return true; | |
1299 | } | |
1300 | ||
1301 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1302 | enum pipe pipe, u32 val) | |
1303 | { | |
1304 | if ((val & LVDS_PORT_EN) == 0) | |
1305 | return false; | |
1306 | ||
1307 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1308 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1309 | return false; | |
1310 | } else { | |
1311 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1312 | return false; | |
1313 | } | |
1314 | return true; | |
1315 | } | |
1316 | ||
1317 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1318 | enum pipe pipe, u32 val) | |
1319 | { | |
1320 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1321 | return false; | |
1322 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1323 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1324 | return false; | |
1325 | } else { | |
1326 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1327 | return false; | |
1328 | } | |
1329 | return true; | |
1330 | } | |
1331 | ||
291906f1 | 1332 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1333 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1334 | { |
47a05eca | 1335 | u32 val = I915_READ(reg); |
4e634389 | 1336 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1337 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1338 | reg, pipe_name(pipe)); |
de9a35ab | 1339 | |
75c5da27 DV |
1340 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1341 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1342 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1343 | } |
1344 | ||
1345 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1346 | enum pipe pipe, int reg) | |
1347 | { | |
47a05eca | 1348 | u32 val = I915_READ(reg); |
b70ad586 | 1349 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1350 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1351 | reg, pipe_name(pipe)); |
de9a35ab | 1352 | |
75c5da27 DV |
1353 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
1354 | && (val & SDVO_PIPE_B_SELECT), | |
de9a35ab | 1355 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1356 | } |
1357 | ||
1358 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1359 | enum pipe pipe) | |
1360 | { | |
1361 | int reg; | |
1362 | u32 val; | |
291906f1 | 1363 | |
f0575e92 KP |
1364 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1365 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1366 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1367 | |
1368 | reg = PCH_ADPA; | |
1369 | val = I915_READ(reg); | |
b70ad586 | 1370 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1371 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1372 | pipe_name(pipe)); |
291906f1 JB |
1373 | |
1374 | reg = PCH_LVDS; | |
1375 | val = I915_READ(reg); | |
b70ad586 | 1376 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1377 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1378 | pipe_name(pipe)); |
291906f1 JB |
1379 | |
1380 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1381 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1382 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1383 | } | |
1384 | ||
63d7bbe9 JB |
1385 | /** |
1386 | * intel_enable_pll - enable a PLL | |
1387 | * @dev_priv: i915 private structure | |
1388 | * @pipe: pipe PLL to enable | |
1389 | * | |
1390 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1391 | * make sure the PLL reg is writable first though, since the panel write | |
1392 | * protect mechanism may be enabled. | |
1393 | * | |
1394 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1395 | * |
1396 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 JB |
1397 | */ |
1398 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1399 | { | |
1400 | int reg; | |
1401 | u32 val; | |
1402 | ||
1403 | /* No really, not for ILK+ */ | |
a0c4da24 | 1404 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1405 | |
1406 | /* PLL is protected by panel, make sure we can write it */ | |
1407 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1408 | assert_panel_unlocked(dev_priv, pipe); | |
1409 | ||
1410 | reg = DPLL(pipe); | |
1411 | val = I915_READ(reg); | |
1412 | val |= DPLL_VCO_ENABLE; | |
1413 | ||
1414 | /* We do this three times for luck */ | |
1415 | I915_WRITE(reg, val); | |
1416 | POSTING_READ(reg); | |
1417 | udelay(150); /* wait for warmup */ | |
1418 | I915_WRITE(reg, val); | |
1419 | POSTING_READ(reg); | |
1420 | udelay(150); /* wait for warmup */ | |
1421 | I915_WRITE(reg, val); | |
1422 | POSTING_READ(reg); | |
1423 | udelay(150); /* wait for warmup */ | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * intel_disable_pll - disable a PLL | |
1428 | * @dev_priv: i915 private structure | |
1429 | * @pipe: pipe PLL to disable | |
1430 | * | |
1431 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1432 | * | |
1433 | * Note! This is for pre-ILK only. | |
1434 | */ | |
1435 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1436 | { | |
1437 | int reg; | |
1438 | u32 val; | |
1439 | ||
1440 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1441 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1442 | return; | |
1443 | ||
1444 | /* Make sure the pipe isn't still relying on us */ | |
1445 | assert_pipe_disabled(dev_priv, pipe); | |
1446 | ||
1447 | reg = DPLL(pipe); | |
1448 | val = I915_READ(reg); | |
1449 | val &= ~DPLL_VCO_ENABLE; | |
1450 | I915_WRITE(reg, val); | |
1451 | POSTING_READ(reg); | |
1452 | } | |
1453 | ||
a416edef ED |
1454 | /* SBI access */ |
1455 | static void | |
1456 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) | |
1457 | { | |
1458 | unsigned long flags; | |
1459 | ||
1460 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1461 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1462 | 100)) { |
1463 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1464 | goto out_unlock; | |
1465 | } | |
1466 | ||
1467 | I915_WRITE(SBI_ADDR, | |
1468 | (reg << 16)); | |
1469 | I915_WRITE(SBI_DATA, | |
1470 | value); | |
1471 | I915_WRITE(SBI_CTL_STAT, | |
1472 | SBI_BUSY | | |
1473 | SBI_CTL_OP_CRWR); | |
1474 | ||
39fb50f6 | 1475 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1476 | 100)) { |
1477 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
1478 | goto out_unlock; | |
1479 | } | |
1480 | ||
1481 | out_unlock: | |
1482 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1483 | } | |
1484 | ||
1485 | static u32 | |
1486 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) | |
1487 | { | |
1488 | unsigned long flags; | |
39fb50f6 | 1489 | u32 value = 0; |
a416edef ED |
1490 | |
1491 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
39fb50f6 | 1492 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1493 | 100)) { |
1494 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
1495 | goto out_unlock; | |
1496 | } | |
1497 | ||
1498 | I915_WRITE(SBI_ADDR, | |
1499 | (reg << 16)); | |
1500 | I915_WRITE(SBI_CTL_STAT, | |
1501 | SBI_BUSY | | |
1502 | SBI_CTL_OP_CRRD); | |
1503 | ||
39fb50f6 | 1504 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1505 | 100)) { |
1506 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
1507 | goto out_unlock; | |
1508 | } | |
1509 | ||
1510 | value = I915_READ(SBI_DATA); | |
1511 | ||
1512 | out_unlock: | |
1513 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
1514 | return value; | |
1515 | } | |
1516 | ||
92f2584a | 1517 | /** |
b6b4e185 | 1518 | * ironlake_enable_pch_pll - enable PCH PLL |
92f2584a JB |
1519 | * @dev_priv: i915 private structure |
1520 | * @pipe: pipe PLL to enable | |
1521 | * | |
1522 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1523 | * drives the transcoder clock. | |
1524 | */ | |
b6b4e185 | 1525 | static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1526 | { |
ee7b9f93 | 1527 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1528 | struct intel_pch_pll *pll; |
92f2584a JB |
1529 | int reg; |
1530 | u32 val; | |
1531 | ||
48da64a8 | 1532 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1533 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1534 | pll = intel_crtc->pch_pll; |
1535 | if (pll == NULL) | |
1536 | return; | |
1537 | ||
1538 | if (WARN_ON(pll->refcount == 0)) | |
1539 | return; | |
ee7b9f93 JB |
1540 | |
1541 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1542 | pll->pll_reg, pll->active, pll->on, | |
1543 | intel_crtc->base.base.id); | |
92f2584a JB |
1544 | |
1545 | /* PCH refclock must be enabled first */ | |
1546 | assert_pch_refclk_enabled(dev_priv); | |
1547 | ||
ee7b9f93 | 1548 | if (pll->active++ && pll->on) { |
92b27b08 | 1549 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1550 | return; |
1551 | } | |
1552 | ||
1553 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1554 | ||
1555 | reg = pll->pll_reg; | |
92f2584a JB |
1556 | val = I915_READ(reg); |
1557 | val |= DPLL_VCO_ENABLE; | |
1558 | I915_WRITE(reg, val); | |
1559 | POSTING_READ(reg); | |
1560 | udelay(200); | |
ee7b9f93 JB |
1561 | |
1562 | pll->on = true; | |
92f2584a JB |
1563 | } |
1564 | ||
ee7b9f93 | 1565 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1566 | { |
ee7b9f93 JB |
1567 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1568 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1569 | int reg; |
ee7b9f93 | 1570 | u32 val; |
4c609cb8 | 1571 | |
92f2584a JB |
1572 | /* PCH only available on ILK+ */ |
1573 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1574 | if (pll == NULL) |
1575 | return; | |
92f2584a | 1576 | |
48da64a8 CW |
1577 | if (WARN_ON(pll->refcount == 0)) |
1578 | return; | |
7a419866 | 1579 | |
ee7b9f93 JB |
1580 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1581 | pll->pll_reg, pll->active, pll->on, | |
1582 | intel_crtc->base.base.id); | |
7a419866 | 1583 | |
48da64a8 | 1584 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1585 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1586 | return; |
1587 | } | |
1588 | ||
ee7b9f93 | 1589 | if (--pll->active) { |
92b27b08 | 1590 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1591 | return; |
ee7b9f93 JB |
1592 | } |
1593 | ||
1594 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1595 | ||
1596 | /* Make sure transcoder isn't still depending on us */ | |
1597 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1598 | |
ee7b9f93 | 1599 | reg = pll->pll_reg; |
92f2584a JB |
1600 | val = I915_READ(reg); |
1601 | val &= ~DPLL_VCO_ENABLE; | |
1602 | I915_WRITE(reg, val); | |
1603 | POSTING_READ(reg); | |
1604 | udelay(200); | |
ee7b9f93 JB |
1605 | |
1606 | pll->on = false; | |
92f2584a JB |
1607 | } |
1608 | ||
b8a4f404 PZ |
1609 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1610 | enum pipe pipe) | |
040484af | 1611 | { |
23670b32 | 1612 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1613 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
23670b32 | 1614 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1615 | |
1616 | /* PCH only available on ILK+ */ | |
1617 | BUG_ON(dev_priv->info->gen < 5); | |
1618 | ||
1619 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1620 | assert_pch_pll_enabled(dev_priv, |
1621 | to_intel_crtc(crtc)->pch_pll, | |
1622 | to_intel_crtc(crtc)); | |
040484af JB |
1623 | |
1624 | /* FDI must be feeding us bits for PCH ports */ | |
1625 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1626 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1627 | ||
23670b32 DV |
1628 | if (HAS_PCH_CPT(dev)) { |
1629 | /* Workaround: Set the timing override bit before enabling the | |
1630 | * pch transcoder. */ | |
1631 | reg = TRANS_CHICKEN2(pipe); | |
1632 | val = I915_READ(reg); | |
1633 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1634 | I915_WRITE(reg, val); | |
59c859d6 | 1635 | } |
23670b32 | 1636 | |
040484af JB |
1637 | reg = TRANSCONF(pipe); |
1638 | val = I915_READ(reg); | |
5f7f726d | 1639 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1640 | |
1641 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1642 | /* | |
1643 | * make the BPC in transcoder be consistent with | |
1644 | * that in pipeconf reg. | |
1645 | */ | |
1646 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1647 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1648 | } |
5f7f726d PZ |
1649 | |
1650 | val &= ~TRANS_INTERLACE_MASK; | |
1651 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1652 | if (HAS_PCH_IBX(dev_priv->dev) && |
1653 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1654 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1655 | else | |
1656 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1657 | else |
1658 | val |= TRANS_PROGRESSIVE; | |
1659 | ||
040484af JB |
1660 | I915_WRITE(reg, val | TRANS_ENABLE); |
1661 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1662 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1663 | } | |
1664 | ||
8fb033d7 | 1665 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1666 | enum transcoder cpu_transcoder) |
040484af | 1667 | { |
8fb033d7 | 1668 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1669 | |
1670 | /* PCH only available on ILK+ */ | |
1671 | BUG_ON(dev_priv->info->gen < 5); | |
1672 | ||
8fb033d7 | 1673 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1674 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1675 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1676 | |
223a6fdf PZ |
1677 | /* Workaround: set timing override bit. */ |
1678 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1679 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1680 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1681 | ||
25f3ef11 | 1682 | val = TRANS_ENABLE; |
937bb610 | 1683 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1684 | |
9a76b1c6 PZ |
1685 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1686 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1687 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1688 | else |
1689 | val |= TRANS_PROGRESSIVE; | |
1690 | ||
25f3ef11 | 1691 | I915_WRITE(TRANSCONF(TRANSCODER_A), val); |
937bb610 PZ |
1692 | if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) |
1693 | DRM_ERROR("Failed to enable PCH transcoder\n"); | |
8fb033d7 PZ |
1694 | } |
1695 | ||
b8a4f404 PZ |
1696 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1697 | enum pipe pipe) | |
040484af | 1698 | { |
23670b32 DV |
1699 | struct drm_device *dev = dev_priv->dev; |
1700 | uint32_t reg, val; | |
040484af JB |
1701 | |
1702 | /* FDI relies on the transcoder */ | |
1703 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1704 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1705 | ||
291906f1 JB |
1706 | /* Ports must be off as well */ |
1707 | assert_pch_ports_disabled(dev_priv, pipe); | |
1708 | ||
040484af JB |
1709 | reg = TRANSCONF(pipe); |
1710 | val = I915_READ(reg); | |
1711 | val &= ~TRANS_ENABLE; | |
1712 | I915_WRITE(reg, val); | |
1713 | /* wait for PCH transcoder off, transcoder state */ | |
1714 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1715 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
23670b32 DV |
1716 | |
1717 | if (!HAS_PCH_IBX(dev)) { | |
1718 | /* Workaround: Clear the timing override chicken bit again. */ | |
1719 | reg = TRANS_CHICKEN2(pipe); | |
1720 | val = I915_READ(reg); | |
1721 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1722 | I915_WRITE(reg, val); | |
1723 | } | |
040484af JB |
1724 | } |
1725 | ||
ab4d966c | 1726 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1727 | { |
8fb033d7 PZ |
1728 | u32 val; |
1729 | ||
8a52fd9f | 1730 | val = I915_READ(_TRANSACONF); |
8fb033d7 | 1731 | val &= ~TRANS_ENABLE; |
8a52fd9f | 1732 | I915_WRITE(_TRANSACONF, val); |
8fb033d7 | 1733 | /* wait for PCH transcoder off, transcoder state */ |
8a52fd9f PZ |
1734 | if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1735 | DRM_ERROR("Failed to disable PCH transcoder\n"); | |
223a6fdf PZ |
1736 | |
1737 | /* Workaround: clear timing override bit. */ | |
1738 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1739 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1740 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1741 | } |
1742 | ||
b24e7179 | 1743 | /** |
309cfea8 | 1744 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1745 | * @dev_priv: i915 private structure |
1746 | * @pipe: pipe to enable | |
040484af | 1747 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1748 | * |
1749 | * Enable @pipe, making sure that various hardware specific requirements | |
1750 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1751 | * | |
1752 | * @pipe should be %PIPE_A or %PIPE_B. | |
1753 | * | |
1754 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1755 | * returning. | |
1756 | */ | |
040484af JB |
1757 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1758 | bool pch_port) | |
b24e7179 | 1759 | { |
702e7a56 PZ |
1760 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1761 | pipe); | |
1a240d4d | 1762 | enum pipe pch_transcoder; |
b24e7179 JB |
1763 | int reg; |
1764 | u32 val; | |
1765 | ||
cc391bbb PZ |
1766 | if (IS_HASWELL(dev_priv->dev)) |
1767 | pch_transcoder = TRANSCODER_A; | |
1768 | else | |
1769 | pch_transcoder = pipe; | |
1770 | ||
b24e7179 JB |
1771 | /* |
1772 | * A pipe without a PLL won't actually be able to drive bits from | |
1773 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1774 | * need the check. | |
1775 | */ | |
1776 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1777 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1778 | else { |
1779 | if (pch_port) { | |
1780 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1781 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1782 | assert_fdi_tx_pll_enabled(dev_priv, |
1783 | (enum pipe) cpu_transcoder); | |
040484af JB |
1784 | } |
1785 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1786 | } | |
b24e7179 | 1787 | |
702e7a56 | 1788 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1789 | val = I915_READ(reg); |
00d70b15 CW |
1790 | if (val & PIPECONF_ENABLE) |
1791 | return; | |
1792 | ||
1793 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1794 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1795 | } | |
1796 | ||
1797 | /** | |
309cfea8 | 1798 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1799 | * @dev_priv: i915 private structure |
1800 | * @pipe: pipe to disable | |
1801 | * | |
1802 | * Disable @pipe, making sure that various hardware specific requirements | |
1803 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1804 | * | |
1805 | * @pipe should be %PIPE_A or %PIPE_B. | |
1806 | * | |
1807 | * Will wait until the pipe has shut down before returning. | |
1808 | */ | |
1809 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1810 | enum pipe pipe) | |
1811 | { | |
702e7a56 PZ |
1812 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1813 | pipe); | |
b24e7179 JB |
1814 | int reg; |
1815 | u32 val; | |
1816 | ||
1817 | /* | |
1818 | * Make sure planes won't keep trying to pump pixels to us, | |
1819 | * or we might hang the display. | |
1820 | */ | |
1821 | assert_planes_disabled(dev_priv, pipe); | |
1822 | ||
1823 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1824 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1825 | return; | |
1826 | ||
702e7a56 | 1827 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1828 | val = I915_READ(reg); |
00d70b15 CW |
1829 | if ((val & PIPECONF_ENABLE) == 0) |
1830 | return; | |
1831 | ||
1832 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1833 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1834 | } | |
1835 | ||
d74362c9 KP |
1836 | /* |
1837 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1838 | * trigger in order to latch. The display address reg provides this. | |
1839 | */ | |
6f1d69b0 | 1840 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1841 | enum plane plane) |
1842 | { | |
14f86147 DL |
1843 | if (dev_priv->info->gen >= 4) |
1844 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1845 | else | |
1846 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1847 | } |
1848 | ||
b24e7179 JB |
1849 | /** |
1850 | * intel_enable_plane - enable a display plane on a given pipe | |
1851 | * @dev_priv: i915 private structure | |
1852 | * @plane: plane to enable | |
1853 | * @pipe: pipe being fed | |
1854 | * | |
1855 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1856 | */ | |
1857 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1858 | enum plane plane, enum pipe pipe) | |
1859 | { | |
1860 | int reg; | |
1861 | u32 val; | |
1862 | ||
1863 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1864 | assert_pipe_enabled(dev_priv, pipe); | |
1865 | ||
1866 | reg = DSPCNTR(plane); | |
1867 | val = I915_READ(reg); | |
00d70b15 CW |
1868 | if (val & DISPLAY_PLANE_ENABLE) |
1869 | return; | |
1870 | ||
1871 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1872 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1873 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1874 | } | |
1875 | ||
b24e7179 JB |
1876 | /** |
1877 | * intel_disable_plane - disable a display plane | |
1878 | * @dev_priv: i915 private structure | |
1879 | * @plane: plane to disable | |
1880 | * @pipe: pipe consuming the data | |
1881 | * | |
1882 | * Disable @plane; should be an independent operation. | |
1883 | */ | |
1884 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1885 | enum plane plane, enum pipe pipe) | |
1886 | { | |
1887 | int reg; | |
1888 | u32 val; | |
1889 | ||
1890 | reg = DSPCNTR(plane); | |
1891 | val = I915_READ(reg); | |
00d70b15 CW |
1892 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1893 | return; | |
1894 | ||
1895 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1896 | intel_flush_display_plane(dev_priv, plane); |
1897 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1898 | } | |
1899 | ||
127bd2ac | 1900 | int |
48b956c5 | 1901 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1902 | struct drm_i915_gem_object *obj, |
919926ae | 1903 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1904 | { |
ce453d81 | 1905 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1906 | u32 alignment; |
1907 | int ret; | |
1908 | ||
05394f39 | 1909 | switch (obj->tiling_mode) { |
6b95a207 | 1910 | case I915_TILING_NONE: |
534843da CW |
1911 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1912 | alignment = 128 * 1024; | |
a6c45cf0 | 1913 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1914 | alignment = 4 * 1024; |
1915 | else | |
1916 | alignment = 64 * 1024; | |
6b95a207 KH |
1917 | break; |
1918 | case I915_TILING_X: | |
1919 | /* pin() will align the object as required by fence */ | |
1920 | alignment = 0; | |
1921 | break; | |
1922 | case I915_TILING_Y: | |
1923 | /* FIXME: Is this true? */ | |
1924 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1925 | return -EINVAL; | |
1926 | default: | |
1927 | BUG(); | |
1928 | } | |
1929 | ||
ce453d81 | 1930 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1931 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1932 | if (ret) |
ce453d81 | 1933 | goto err_interruptible; |
6b95a207 KH |
1934 | |
1935 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1936 | * fence, whereas 965+ only requires a fence if using | |
1937 | * framebuffer compression. For simplicity, we always install | |
1938 | * a fence as the cost is not that onerous. | |
1939 | */ | |
06d98131 | 1940 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1941 | if (ret) |
1942 | goto err_unpin; | |
1690e1eb | 1943 | |
9a5a53b3 | 1944 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1945 | |
ce453d81 | 1946 | dev_priv->mm.interruptible = true; |
6b95a207 | 1947 | return 0; |
48b956c5 CW |
1948 | |
1949 | err_unpin: | |
1950 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1951 | err_interruptible: |
1952 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1953 | return ret; |
6b95a207 KH |
1954 | } |
1955 | ||
1690e1eb CW |
1956 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1957 | { | |
1958 | i915_gem_object_unpin_fence(obj); | |
1959 | i915_gem_object_unpin(obj); | |
1960 | } | |
1961 | ||
c2c75131 DV |
1962 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1963 | * is assumed to be a power-of-two. */ | |
5a35e99e DL |
1964 | unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, |
1965 | unsigned int bpp, | |
1966 | unsigned int pitch) | |
c2c75131 DV |
1967 | { |
1968 | int tile_rows, tiles; | |
1969 | ||
1970 | tile_rows = *y / 8; | |
1971 | *y %= 8; | |
1972 | tiles = *x / (512/bpp); | |
1973 | *x %= 512/bpp; | |
1974 | ||
1975 | return tile_rows * pitch * 8 + tiles * 4096; | |
1976 | } | |
1977 | ||
17638cd6 JB |
1978 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1979 | int x, int y) | |
81255565 JB |
1980 | { |
1981 | struct drm_device *dev = crtc->dev; | |
1982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1984 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1985 | struct drm_i915_gem_object *obj; |
81255565 | 1986 | int plane = intel_crtc->plane; |
e506a0c6 | 1987 | unsigned long linear_offset; |
81255565 | 1988 | u32 dspcntr; |
5eddb70b | 1989 | u32 reg; |
81255565 JB |
1990 | |
1991 | switch (plane) { | |
1992 | case 0: | |
1993 | case 1: | |
1994 | break; | |
1995 | default: | |
1996 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1997 | return -EINVAL; | |
1998 | } | |
1999 | ||
2000 | intel_fb = to_intel_framebuffer(fb); | |
2001 | obj = intel_fb->obj; | |
81255565 | 2002 | |
5eddb70b CW |
2003 | reg = DSPCNTR(plane); |
2004 | dspcntr = I915_READ(reg); | |
81255565 JB |
2005 | /* Mask out pixel format bits in case we change it */ |
2006 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2007 | switch (fb->pixel_format) { |
2008 | case DRM_FORMAT_C8: | |
81255565 JB |
2009 | dspcntr |= DISPPLANE_8BPP; |
2010 | break; | |
57779d06 VS |
2011 | case DRM_FORMAT_XRGB1555: |
2012 | case DRM_FORMAT_ARGB1555: | |
2013 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2014 | break; |
57779d06 VS |
2015 | case DRM_FORMAT_RGB565: |
2016 | dspcntr |= DISPPLANE_BGRX565; | |
2017 | break; | |
2018 | case DRM_FORMAT_XRGB8888: | |
2019 | case DRM_FORMAT_ARGB8888: | |
2020 | dspcntr |= DISPPLANE_BGRX888; | |
2021 | break; | |
2022 | case DRM_FORMAT_XBGR8888: | |
2023 | case DRM_FORMAT_ABGR8888: | |
2024 | dspcntr |= DISPPLANE_RGBX888; | |
2025 | break; | |
2026 | case DRM_FORMAT_XRGB2101010: | |
2027 | case DRM_FORMAT_ARGB2101010: | |
2028 | dspcntr |= DISPPLANE_BGRX101010; | |
2029 | break; | |
2030 | case DRM_FORMAT_XBGR2101010: | |
2031 | case DRM_FORMAT_ABGR2101010: | |
2032 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2033 | break; |
2034 | default: | |
57779d06 | 2035 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
81255565 JB |
2036 | return -EINVAL; |
2037 | } | |
57779d06 | 2038 | |
a6c45cf0 | 2039 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2040 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2041 | dspcntr |= DISPPLANE_TILED; |
2042 | else | |
2043 | dspcntr &= ~DISPPLANE_TILED; | |
2044 | } | |
2045 | ||
5eddb70b | 2046 | I915_WRITE(reg, dspcntr); |
81255565 | 2047 | |
e506a0c6 | 2048 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2049 | |
c2c75131 DV |
2050 | if (INTEL_INFO(dev)->gen >= 4) { |
2051 | intel_crtc->dspaddr_offset = | |
5a35e99e DL |
2052 | intel_gen4_compute_offset_xtiled(&x, &y, |
2053 | fb->bits_per_pixel / 8, | |
2054 | fb->pitches[0]); | |
c2c75131 DV |
2055 | linear_offset -= intel_crtc->dspaddr_offset; |
2056 | } else { | |
e506a0c6 | 2057 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2058 | } |
e506a0c6 DV |
2059 | |
2060 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2061 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2062 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2063 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2064 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2065 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2066 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2067 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2068 | } else |
e506a0c6 | 2069 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2070 | POSTING_READ(reg); |
81255565 | 2071 | |
17638cd6 JB |
2072 | return 0; |
2073 | } | |
2074 | ||
2075 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2076 | struct drm_framebuffer *fb, int x, int y) | |
2077 | { | |
2078 | struct drm_device *dev = crtc->dev; | |
2079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2081 | struct intel_framebuffer *intel_fb; | |
2082 | struct drm_i915_gem_object *obj; | |
2083 | int plane = intel_crtc->plane; | |
e506a0c6 | 2084 | unsigned long linear_offset; |
17638cd6 JB |
2085 | u32 dspcntr; |
2086 | u32 reg; | |
2087 | ||
2088 | switch (plane) { | |
2089 | case 0: | |
2090 | case 1: | |
27f8227b | 2091 | case 2: |
17638cd6 JB |
2092 | break; |
2093 | default: | |
2094 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2095 | return -EINVAL; | |
2096 | } | |
2097 | ||
2098 | intel_fb = to_intel_framebuffer(fb); | |
2099 | obj = intel_fb->obj; | |
2100 | ||
2101 | reg = DSPCNTR(plane); | |
2102 | dspcntr = I915_READ(reg); | |
2103 | /* Mask out pixel format bits in case we change it */ | |
2104 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2105 | switch (fb->pixel_format) { |
2106 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2107 | dspcntr |= DISPPLANE_8BPP; |
2108 | break; | |
57779d06 VS |
2109 | case DRM_FORMAT_RGB565: |
2110 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2111 | break; |
57779d06 VS |
2112 | case DRM_FORMAT_XRGB8888: |
2113 | case DRM_FORMAT_ARGB8888: | |
2114 | dspcntr |= DISPPLANE_BGRX888; | |
2115 | break; | |
2116 | case DRM_FORMAT_XBGR8888: | |
2117 | case DRM_FORMAT_ABGR8888: | |
2118 | dspcntr |= DISPPLANE_RGBX888; | |
2119 | break; | |
2120 | case DRM_FORMAT_XRGB2101010: | |
2121 | case DRM_FORMAT_ARGB2101010: | |
2122 | dspcntr |= DISPPLANE_BGRX101010; | |
2123 | break; | |
2124 | case DRM_FORMAT_XBGR2101010: | |
2125 | case DRM_FORMAT_ABGR2101010: | |
2126 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2127 | break; |
2128 | default: | |
57779d06 | 2129 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
17638cd6 JB |
2130 | return -EINVAL; |
2131 | } | |
2132 | ||
2133 | if (obj->tiling_mode != I915_TILING_NONE) | |
2134 | dspcntr |= DISPPLANE_TILED; | |
2135 | else | |
2136 | dspcntr &= ~DISPPLANE_TILED; | |
2137 | ||
2138 | /* must disable */ | |
2139 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2140 | ||
2141 | I915_WRITE(reg, dspcntr); | |
2142 | ||
e506a0c6 | 2143 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2144 | intel_crtc->dspaddr_offset = |
5a35e99e DL |
2145 | intel_gen4_compute_offset_xtiled(&x, &y, |
2146 | fb->bits_per_pixel / 8, | |
2147 | fb->pitches[0]); | |
c2c75131 | 2148 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2149 | |
e506a0c6 DV |
2150 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2151 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2152 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2153 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2154 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
bc1c91eb DL |
2155 | if (IS_HASWELL(dev)) { |
2156 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2157 | } else { | |
2158 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2159 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2160 | } | |
17638cd6 JB |
2161 | POSTING_READ(reg); |
2162 | ||
2163 | return 0; | |
2164 | } | |
2165 | ||
2166 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2167 | static int | |
2168 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2169 | int x, int y, enum mode_set_atomic state) | |
2170 | { | |
2171 | struct drm_device *dev = crtc->dev; | |
2172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2173 | |
6b8e6ed0 CW |
2174 | if (dev_priv->display.disable_fbc) |
2175 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2176 | intel_increase_pllclock(crtc); |
81255565 | 2177 | |
6b8e6ed0 | 2178 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2179 | } |
2180 | ||
14667a4b CW |
2181 | static int |
2182 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2183 | { | |
2184 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2185 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2186 | bool was_interruptible = dev_priv->mm.interruptible; | |
2187 | int ret; | |
2188 | ||
2189 | wait_event(dev_priv->pending_flip_queue, | |
2190 | atomic_read(&dev_priv->mm.wedged) || | |
2191 | atomic_read(&obj->pending_flip) == 0); | |
2192 | ||
2193 | /* Big Hammer, we also need to ensure that any pending | |
2194 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2195 | * current scanout is retired before unpinning the old | |
2196 | * framebuffer. | |
2197 | * | |
2198 | * This should only fail upon a hung GPU, in which case we | |
2199 | * can safely continue. | |
2200 | */ | |
2201 | dev_priv->mm.interruptible = false; | |
2202 | ret = i915_gem_object_finish_gpu(obj); | |
2203 | dev_priv->mm.interruptible = was_interruptible; | |
2204 | ||
2205 | return ret; | |
2206 | } | |
2207 | ||
198598d0 VS |
2208 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2209 | { | |
2210 | struct drm_device *dev = crtc->dev; | |
2211 | struct drm_i915_master_private *master_priv; | |
2212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2213 | ||
2214 | if (!dev->primary->master) | |
2215 | return; | |
2216 | ||
2217 | master_priv = dev->primary->master->driver_priv; | |
2218 | if (!master_priv->sarea_priv) | |
2219 | return; | |
2220 | ||
2221 | switch (intel_crtc->pipe) { | |
2222 | case 0: | |
2223 | master_priv->sarea_priv->pipeA_x = x; | |
2224 | master_priv->sarea_priv->pipeA_y = y; | |
2225 | break; | |
2226 | case 1: | |
2227 | master_priv->sarea_priv->pipeB_x = x; | |
2228 | master_priv->sarea_priv->pipeB_y = y; | |
2229 | break; | |
2230 | default: | |
2231 | break; | |
2232 | } | |
2233 | } | |
2234 | ||
5c3b82e2 | 2235 | static int |
3c4fdcfb | 2236 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2237 | struct drm_framebuffer *fb) |
79e53945 JB |
2238 | { |
2239 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2242 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2243 | int ret; |
79e53945 JB |
2244 | |
2245 | /* no fb bound */ | |
94352cf9 | 2246 | if (!fb) { |
a5071c2f | 2247 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2248 | return 0; |
2249 | } | |
2250 | ||
5826eca5 ED |
2251 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2252 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", | |
2253 | intel_crtc->plane, | |
2254 | dev_priv->num_pipe); | |
5c3b82e2 | 2255 | return -EINVAL; |
79e53945 JB |
2256 | } |
2257 | ||
5c3b82e2 | 2258 | mutex_lock(&dev->struct_mutex); |
265db958 | 2259 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2260 | to_intel_framebuffer(fb)->obj, |
919926ae | 2261 | NULL); |
5c3b82e2 CW |
2262 | if (ret != 0) { |
2263 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2264 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2265 | return ret; |
2266 | } | |
79e53945 | 2267 | |
94352cf9 DV |
2268 | if (crtc->fb) |
2269 | intel_finish_fb(crtc->fb); | |
265db958 | 2270 | |
94352cf9 | 2271 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2272 | if (ret) { |
94352cf9 | 2273 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2274 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2275 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2276 | return ret; |
79e53945 | 2277 | } |
3c4fdcfb | 2278 | |
94352cf9 DV |
2279 | old_fb = crtc->fb; |
2280 | crtc->fb = fb; | |
6c4c86f5 DV |
2281 | crtc->x = x; |
2282 | crtc->y = y; | |
94352cf9 | 2283 | |
b7f1de28 CW |
2284 | if (old_fb) { |
2285 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2286 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2287 | } |
652c393a | 2288 | |
6b8e6ed0 | 2289 | intel_update_fbc(dev); |
5c3b82e2 | 2290 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2291 | |
198598d0 | 2292 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2293 | |
2294 | return 0; | |
79e53945 JB |
2295 | } |
2296 | ||
5e84e1a4 ZW |
2297 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2298 | { | |
2299 | struct drm_device *dev = crtc->dev; | |
2300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2301 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2302 | int pipe = intel_crtc->pipe; | |
2303 | u32 reg, temp; | |
2304 | ||
2305 | /* enable normal train */ | |
2306 | reg = FDI_TX_CTL(pipe); | |
2307 | temp = I915_READ(reg); | |
61e499bf | 2308 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2309 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2310 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2311 | } else { |
2312 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2313 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2314 | } |
5e84e1a4 ZW |
2315 | I915_WRITE(reg, temp); |
2316 | ||
2317 | reg = FDI_RX_CTL(pipe); | |
2318 | temp = I915_READ(reg); | |
2319 | if (HAS_PCH_CPT(dev)) { | |
2320 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2321 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2322 | } else { | |
2323 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2324 | temp |= FDI_LINK_TRAIN_NONE; | |
2325 | } | |
2326 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2327 | ||
2328 | /* wait one idle pattern time */ | |
2329 | POSTING_READ(reg); | |
2330 | udelay(1000); | |
357555c0 JB |
2331 | |
2332 | /* IVB wants error correction enabled */ | |
2333 | if (IS_IVYBRIDGE(dev)) | |
2334 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2335 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2336 | } |
2337 | ||
291427f5 JB |
2338 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2339 | { | |
2340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2341 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2342 | ||
2343 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2344 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2345 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2346 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2347 | POSTING_READ(SOUTH_CHICKEN1); | |
2348 | } | |
2349 | ||
01a415fd DV |
2350 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2351 | { | |
2352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2353 | struct intel_crtc *pipe_B_crtc = | |
2354 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2355 | struct intel_crtc *pipe_C_crtc = | |
2356 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2357 | uint32_t temp; | |
2358 | ||
2359 | /* When everything is off disable fdi C so that we could enable fdi B | |
2360 | * with all lanes. XXX: This misses the case where a pipe is not using | |
2361 | * any pch resources and so doesn't need any fdi lanes. */ | |
2362 | if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { | |
2363 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
2364 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2365 | ||
2366 | temp = I915_READ(SOUTH_CHICKEN1); | |
2367 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2368 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2369 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2370 | } | |
2371 | } | |
2372 | ||
8db9d77b ZW |
2373 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2374 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2375 | { | |
2376 | struct drm_device *dev = crtc->dev; | |
2377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2379 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2380 | int plane = intel_crtc->plane; |
5eddb70b | 2381 | u32 reg, temp, tries; |
8db9d77b | 2382 | |
0fc932b8 JB |
2383 | /* FDI needs bits from pipe & plane first */ |
2384 | assert_pipe_enabled(dev_priv, pipe); | |
2385 | assert_plane_enabled(dev_priv, plane); | |
2386 | ||
e1a44743 AJ |
2387 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2388 | for train result */ | |
5eddb70b CW |
2389 | reg = FDI_RX_IMR(pipe); |
2390 | temp = I915_READ(reg); | |
e1a44743 AJ |
2391 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2392 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2393 | I915_WRITE(reg, temp); |
2394 | I915_READ(reg); | |
e1a44743 AJ |
2395 | udelay(150); |
2396 | ||
8db9d77b | 2397 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2398 | reg = FDI_TX_CTL(pipe); |
2399 | temp = I915_READ(reg); | |
77ffb597 AJ |
2400 | temp &= ~(7 << 19); |
2401 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2402 | temp &= ~FDI_LINK_TRAIN_NONE; |
2403 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2404 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2405 | |
5eddb70b CW |
2406 | reg = FDI_RX_CTL(pipe); |
2407 | temp = I915_READ(reg); | |
8db9d77b ZW |
2408 | temp &= ~FDI_LINK_TRAIN_NONE; |
2409 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2410 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2411 | ||
2412 | POSTING_READ(reg); | |
8db9d77b ZW |
2413 | udelay(150); |
2414 | ||
5b2adf89 | 2415 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2416 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2417 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2418 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2419 | |
5eddb70b | 2420 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2421 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2422 | temp = I915_READ(reg); |
8db9d77b ZW |
2423 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2424 | ||
2425 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2426 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2427 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2428 | break; |
2429 | } | |
8db9d77b | 2430 | } |
e1a44743 | 2431 | if (tries == 5) |
5eddb70b | 2432 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2433 | |
2434 | /* Train 2 */ | |
5eddb70b CW |
2435 | reg = FDI_TX_CTL(pipe); |
2436 | temp = I915_READ(reg); | |
8db9d77b ZW |
2437 | temp &= ~FDI_LINK_TRAIN_NONE; |
2438 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2439 | I915_WRITE(reg, temp); |
8db9d77b | 2440 | |
5eddb70b CW |
2441 | reg = FDI_RX_CTL(pipe); |
2442 | temp = I915_READ(reg); | |
8db9d77b ZW |
2443 | temp &= ~FDI_LINK_TRAIN_NONE; |
2444 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2445 | I915_WRITE(reg, temp); |
8db9d77b | 2446 | |
5eddb70b CW |
2447 | POSTING_READ(reg); |
2448 | udelay(150); | |
8db9d77b | 2449 | |
5eddb70b | 2450 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2451 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2452 | temp = I915_READ(reg); |
8db9d77b ZW |
2453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2454 | ||
2455 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2456 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2457 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2458 | break; | |
2459 | } | |
8db9d77b | 2460 | } |
e1a44743 | 2461 | if (tries == 5) |
5eddb70b | 2462 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2463 | |
2464 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2465 | |
8db9d77b ZW |
2466 | } |
2467 | ||
0206e353 | 2468 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2469 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2470 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2471 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2472 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2473 | }; | |
2474 | ||
2475 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2476 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2477 | { | |
2478 | struct drm_device *dev = crtc->dev; | |
2479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2481 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2482 | u32 reg, temp, i, retry; |
8db9d77b | 2483 | |
e1a44743 AJ |
2484 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2485 | for train result */ | |
5eddb70b CW |
2486 | reg = FDI_RX_IMR(pipe); |
2487 | temp = I915_READ(reg); | |
e1a44743 AJ |
2488 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2489 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2490 | I915_WRITE(reg, temp); |
2491 | ||
2492 | POSTING_READ(reg); | |
e1a44743 AJ |
2493 | udelay(150); |
2494 | ||
8db9d77b | 2495 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2496 | reg = FDI_TX_CTL(pipe); |
2497 | temp = I915_READ(reg); | |
77ffb597 AJ |
2498 | temp &= ~(7 << 19); |
2499 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2500 | temp &= ~FDI_LINK_TRAIN_NONE; |
2501 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2502 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2503 | /* SNB-B */ | |
2504 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2505 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2506 | |
d74cf324 DV |
2507 | I915_WRITE(FDI_RX_MISC(pipe), |
2508 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2509 | ||
5eddb70b CW |
2510 | reg = FDI_RX_CTL(pipe); |
2511 | temp = I915_READ(reg); | |
8db9d77b ZW |
2512 | if (HAS_PCH_CPT(dev)) { |
2513 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2514 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2515 | } else { | |
2516 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2517 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2518 | } | |
5eddb70b CW |
2519 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2520 | ||
2521 | POSTING_READ(reg); | |
8db9d77b ZW |
2522 | udelay(150); |
2523 | ||
8f5718a6 | 2524 | cpt_phase_pointer_enable(dev, pipe); |
291427f5 | 2525 | |
0206e353 | 2526 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2527 | reg = FDI_TX_CTL(pipe); |
2528 | temp = I915_READ(reg); | |
8db9d77b ZW |
2529 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2530 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2531 | I915_WRITE(reg, temp); |
2532 | ||
2533 | POSTING_READ(reg); | |
8db9d77b ZW |
2534 | udelay(500); |
2535 | ||
fa37d39e SP |
2536 | for (retry = 0; retry < 5; retry++) { |
2537 | reg = FDI_RX_IIR(pipe); | |
2538 | temp = I915_READ(reg); | |
2539 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2540 | if (temp & FDI_RX_BIT_LOCK) { | |
2541 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2542 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2543 | break; | |
2544 | } | |
2545 | udelay(50); | |
8db9d77b | 2546 | } |
fa37d39e SP |
2547 | if (retry < 5) |
2548 | break; | |
8db9d77b ZW |
2549 | } |
2550 | if (i == 4) | |
5eddb70b | 2551 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2552 | |
2553 | /* Train 2 */ | |
5eddb70b CW |
2554 | reg = FDI_TX_CTL(pipe); |
2555 | temp = I915_READ(reg); | |
8db9d77b ZW |
2556 | temp &= ~FDI_LINK_TRAIN_NONE; |
2557 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2558 | if (IS_GEN6(dev)) { | |
2559 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2560 | /* SNB-B */ | |
2561 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2562 | } | |
5eddb70b | 2563 | I915_WRITE(reg, temp); |
8db9d77b | 2564 | |
5eddb70b CW |
2565 | reg = FDI_RX_CTL(pipe); |
2566 | temp = I915_READ(reg); | |
8db9d77b ZW |
2567 | if (HAS_PCH_CPT(dev)) { |
2568 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2569 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2570 | } else { | |
2571 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2572 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2573 | } | |
5eddb70b CW |
2574 | I915_WRITE(reg, temp); |
2575 | ||
2576 | POSTING_READ(reg); | |
8db9d77b ZW |
2577 | udelay(150); |
2578 | ||
0206e353 | 2579 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2580 | reg = FDI_TX_CTL(pipe); |
2581 | temp = I915_READ(reg); | |
8db9d77b ZW |
2582 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2583 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2584 | I915_WRITE(reg, temp); |
2585 | ||
2586 | POSTING_READ(reg); | |
8db9d77b ZW |
2587 | udelay(500); |
2588 | ||
fa37d39e SP |
2589 | for (retry = 0; retry < 5; retry++) { |
2590 | reg = FDI_RX_IIR(pipe); | |
2591 | temp = I915_READ(reg); | |
2592 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2593 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2594 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2595 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2596 | break; | |
2597 | } | |
2598 | udelay(50); | |
8db9d77b | 2599 | } |
fa37d39e SP |
2600 | if (retry < 5) |
2601 | break; | |
8db9d77b ZW |
2602 | } |
2603 | if (i == 4) | |
5eddb70b | 2604 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2605 | |
2606 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2607 | } | |
2608 | ||
357555c0 JB |
2609 | /* Manual link training for Ivy Bridge A0 parts */ |
2610 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2611 | { | |
2612 | struct drm_device *dev = crtc->dev; | |
2613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2615 | int pipe = intel_crtc->pipe; | |
2616 | u32 reg, temp, i; | |
2617 | ||
2618 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2619 | for train result */ | |
2620 | reg = FDI_RX_IMR(pipe); | |
2621 | temp = I915_READ(reg); | |
2622 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2623 | temp &= ~FDI_RX_BIT_LOCK; | |
2624 | I915_WRITE(reg, temp); | |
2625 | ||
2626 | POSTING_READ(reg); | |
2627 | udelay(150); | |
2628 | ||
01a415fd DV |
2629 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2630 | I915_READ(FDI_RX_IIR(pipe))); | |
2631 | ||
357555c0 JB |
2632 | /* enable CPU FDI TX and PCH FDI RX */ |
2633 | reg = FDI_TX_CTL(pipe); | |
2634 | temp = I915_READ(reg); | |
2635 | temp &= ~(7 << 19); | |
2636 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2637 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2638 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2639 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2640 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2641 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2642 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2643 | ||
d74cf324 DV |
2644 | I915_WRITE(FDI_RX_MISC(pipe), |
2645 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2646 | ||
357555c0 JB |
2647 | reg = FDI_RX_CTL(pipe); |
2648 | temp = I915_READ(reg); | |
2649 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2650 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2651 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2652 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2653 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2654 | ||
2655 | POSTING_READ(reg); | |
2656 | udelay(150); | |
2657 | ||
8f5718a6 | 2658 | cpt_phase_pointer_enable(dev, pipe); |
291427f5 | 2659 | |
0206e353 | 2660 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2661 | reg = FDI_TX_CTL(pipe); |
2662 | temp = I915_READ(reg); | |
2663 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2664 | temp |= snb_b_fdi_train_param[i]; | |
2665 | I915_WRITE(reg, temp); | |
2666 | ||
2667 | POSTING_READ(reg); | |
2668 | udelay(500); | |
2669 | ||
2670 | reg = FDI_RX_IIR(pipe); | |
2671 | temp = I915_READ(reg); | |
2672 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2673 | ||
2674 | if (temp & FDI_RX_BIT_LOCK || | |
2675 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2676 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
01a415fd | 2677 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); |
357555c0 JB |
2678 | break; |
2679 | } | |
2680 | } | |
2681 | if (i == 4) | |
2682 | DRM_ERROR("FDI train 1 fail!\n"); | |
2683 | ||
2684 | /* Train 2 */ | |
2685 | reg = FDI_TX_CTL(pipe); | |
2686 | temp = I915_READ(reg); | |
2687 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2688 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2689 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2690 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2691 | I915_WRITE(reg, temp); | |
2692 | ||
2693 | reg = FDI_RX_CTL(pipe); | |
2694 | temp = I915_READ(reg); | |
2695 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2696 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2697 | I915_WRITE(reg, temp); | |
2698 | ||
2699 | POSTING_READ(reg); | |
2700 | udelay(150); | |
2701 | ||
0206e353 | 2702 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2703 | reg = FDI_TX_CTL(pipe); |
2704 | temp = I915_READ(reg); | |
2705 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2706 | temp |= snb_b_fdi_train_param[i]; | |
2707 | I915_WRITE(reg, temp); | |
2708 | ||
2709 | POSTING_READ(reg); | |
2710 | udelay(500); | |
2711 | ||
2712 | reg = FDI_RX_IIR(pipe); | |
2713 | temp = I915_READ(reg); | |
2714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2715 | ||
2716 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2717 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
01a415fd | 2718 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); |
357555c0 JB |
2719 | break; |
2720 | } | |
2721 | } | |
2722 | if (i == 4) | |
2723 | DRM_ERROR("FDI train 2 fail!\n"); | |
2724 | ||
2725 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2726 | } | |
2727 | ||
88cefb6c | 2728 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2729 | { |
88cefb6c | 2730 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2731 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2732 | int pipe = intel_crtc->pipe; |
5eddb70b | 2733 | u32 reg, temp; |
79e53945 | 2734 | |
c64e311e | 2735 | |
c98e9dcf | 2736 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2737 | reg = FDI_RX_CTL(pipe); |
2738 | temp = I915_READ(reg); | |
2739 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2740 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2741 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2742 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2743 | ||
2744 | POSTING_READ(reg); | |
c98e9dcf JB |
2745 | udelay(200); |
2746 | ||
2747 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2748 | temp = I915_READ(reg); |
2749 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2750 | ||
2751 | POSTING_READ(reg); | |
c98e9dcf JB |
2752 | udelay(200); |
2753 | ||
20749730 PZ |
2754 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2755 | reg = FDI_TX_CTL(pipe); | |
2756 | temp = I915_READ(reg); | |
2757 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2758 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2759 | |
20749730 PZ |
2760 | POSTING_READ(reg); |
2761 | udelay(100); | |
6be4a607 | 2762 | } |
0e23b99d JB |
2763 | } |
2764 | ||
88cefb6c DV |
2765 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2766 | { | |
2767 | struct drm_device *dev = intel_crtc->base.dev; | |
2768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2769 | int pipe = intel_crtc->pipe; | |
2770 | u32 reg, temp; | |
2771 | ||
2772 | /* Switch from PCDclk to Rawclk */ | |
2773 | reg = FDI_RX_CTL(pipe); | |
2774 | temp = I915_READ(reg); | |
2775 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2776 | ||
2777 | /* Disable CPU FDI TX PLL */ | |
2778 | reg = FDI_TX_CTL(pipe); | |
2779 | temp = I915_READ(reg); | |
2780 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2781 | ||
2782 | POSTING_READ(reg); | |
2783 | udelay(100); | |
2784 | ||
2785 | reg = FDI_RX_CTL(pipe); | |
2786 | temp = I915_READ(reg); | |
2787 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2788 | ||
2789 | /* Wait for the clocks to turn off. */ | |
2790 | POSTING_READ(reg); | |
2791 | udelay(100); | |
2792 | } | |
2793 | ||
291427f5 JB |
2794 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2795 | { | |
2796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2797 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2798 | ||
2799 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2800 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2801 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2802 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2803 | POSTING_READ(SOUTH_CHICKEN1); | |
2804 | } | |
0fc932b8 JB |
2805 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2806 | { | |
2807 | struct drm_device *dev = crtc->dev; | |
2808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2810 | int pipe = intel_crtc->pipe; | |
2811 | u32 reg, temp; | |
2812 | ||
2813 | /* disable CPU FDI tx and PCH FDI rx */ | |
2814 | reg = FDI_TX_CTL(pipe); | |
2815 | temp = I915_READ(reg); | |
2816 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2817 | POSTING_READ(reg); | |
2818 | ||
2819 | reg = FDI_RX_CTL(pipe); | |
2820 | temp = I915_READ(reg); | |
2821 | temp &= ~(0x7 << 16); | |
2822 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2823 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2824 | ||
2825 | POSTING_READ(reg); | |
2826 | udelay(100); | |
2827 | ||
2828 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2829 | if (HAS_PCH_IBX(dev)) { |
2830 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
291427f5 JB |
2831 | } else if (HAS_PCH_CPT(dev)) { |
2832 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2833 | } |
0fc932b8 JB |
2834 | |
2835 | /* still set train pattern 1 */ | |
2836 | reg = FDI_TX_CTL(pipe); | |
2837 | temp = I915_READ(reg); | |
2838 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2839 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2840 | I915_WRITE(reg, temp); | |
2841 | ||
2842 | reg = FDI_RX_CTL(pipe); | |
2843 | temp = I915_READ(reg); | |
2844 | if (HAS_PCH_CPT(dev)) { | |
2845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2846 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2847 | } else { | |
2848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2849 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2850 | } | |
2851 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2852 | temp &= ~(0x07 << 16); | |
2853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2854 | I915_WRITE(reg, temp); | |
2855 | ||
2856 | POSTING_READ(reg); | |
2857 | udelay(100); | |
2858 | } | |
2859 | ||
5bb61643 CW |
2860 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2861 | { | |
2862 | struct drm_device *dev = crtc->dev; | |
2863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2864 | unsigned long flags; | |
2865 | bool pending; | |
2866 | ||
2867 | if (atomic_read(&dev_priv->mm.wedged)) | |
2868 | return false; | |
2869 | ||
2870 | spin_lock_irqsave(&dev->event_lock, flags); | |
2871 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2872 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2873 | ||
2874 | return pending; | |
2875 | } | |
2876 | ||
e6c3a2a6 CW |
2877 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2878 | { | |
0f91128d | 2879 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2880 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2881 | |
2882 | if (crtc->fb == NULL) | |
2883 | return; | |
2884 | ||
5bb61643 CW |
2885 | wait_event(dev_priv->pending_flip_queue, |
2886 | !intel_crtc_has_pending_flip(crtc)); | |
2887 | ||
0f91128d CW |
2888 | mutex_lock(&dev->struct_mutex); |
2889 | intel_finish_fb(crtc->fb); | |
2890 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2891 | } |
2892 | ||
fc316cbe | 2893 | static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc) |
040484af JB |
2894 | { |
2895 | struct drm_device *dev = crtc->dev; | |
228d3e36 | 2896 | struct intel_encoder *intel_encoder; |
040484af JB |
2897 | |
2898 | /* | |
2899 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2900 | * must be driven by its own crtc; no sharing is possible. | |
2901 | */ | |
228d3e36 | 2902 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
228d3e36 | 2903 | switch (intel_encoder->type) { |
040484af | 2904 | case INTEL_OUTPUT_EDP: |
228d3e36 | 2905 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
040484af JB |
2906 | return false; |
2907 | continue; | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | return true; | |
2912 | } | |
2913 | ||
fc316cbe PZ |
2914 | static bool haswell_crtc_driving_pch(struct drm_crtc *crtc) |
2915 | { | |
2916 | return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG); | |
2917 | } | |
2918 | ||
e615efe4 ED |
2919 | /* Program iCLKIP clock to the desired frequency */ |
2920 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2921 | { | |
2922 | struct drm_device *dev = crtc->dev; | |
2923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2924 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2925 | u32 temp; | |
2926 | ||
2927 | /* It is necessary to ungate the pixclk gate prior to programming | |
2928 | * the divisors, and gate it back when it is done. | |
2929 | */ | |
2930 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2931 | ||
2932 | /* Disable SSCCTL */ | |
2933 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
2934 | intel_sbi_read(dev_priv, SBI_SSCCTL6) | | |
2935 | SBI_SSCCTL_DISABLE); | |
2936 | ||
2937 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2938 | if (crtc->mode.clock == 20000) { | |
2939 | auxdiv = 1; | |
2940 | divsel = 0x41; | |
2941 | phaseinc = 0x20; | |
2942 | } else { | |
2943 | /* The iCLK virtual clock root frequency is in MHz, | |
2944 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2945 | * it is necessary to divide one by another, so we | |
2946 | * convert the virtual clock precision to KHz here for higher | |
2947 | * precision. | |
2948 | */ | |
2949 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2950 | u32 iclk_pi_range = 64; | |
2951 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2952 | ||
2953 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2954 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2955 | pi_value = desired_divisor % iclk_pi_range; | |
2956 | ||
2957 | auxdiv = 0; | |
2958 | divsel = msb_divisor_value - 2; | |
2959 | phaseinc = pi_value; | |
2960 | } | |
2961 | ||
2962 | /* This should not happen with any sane values */ | |
2963 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2964 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2965 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2966 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2967 | ||
2968 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2969 | crtc->mode.clock, | |
2970 | auxdiv, | |
2971 | divsel, | |
2972 | phasedir, | |
2973 | phaseinc); | |
2974 | ||
2975 | /* Program SSCDIVINTPHASE6 */ | |
2976 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6); | |
2977 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; | |
2978 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2979 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2980 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2981 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2982 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
2983 | ||
2984 | intel_sbi_write(dev_priv, | |
2985 | SBI_SSCDIVINTPHASE6, | |
2986 | temp); | |
2987 | ||
2988 | /* Program SSCAUXDIV */ | |
2989 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6); | |
2990 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); | |
2991 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
2992 | intel_sbi_write(dev_priv, | |
2993 | SBI_SSCAUXDIV6, | |
2994 | temp); | |
2995 | ||
2996 | ||
2997 | /* Enable modulator and associated divider */ | |
2998 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6); | |
2999 | temp &= ~SBI_SSCCTL_DISABLE; | |
3000 | intel_sbi_write(dev_priv, | |
3001 | SBI_SSCCTL6, | |
3002 | temp); | |
3003 | ||
3004 | /* Wait for initialization time */ | |
3005 | udelay(24); | |
3006 | ||
3007 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3008 | } | |
3009 | ||
f67a559d JB |
3010 | /* |
3011 | * Enable PCH resources required for PCH ports: | |
3012 | * - PCH PLLs | |
3013 | * - FDI training & RX/TX | |
3014 | * - update transcoder timings | |
3015 | * - DP transcoding bits | |
3016 | * - transcoder | |
3017 | */ | |
3018 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3019 | { |
3020 | struct drm_device *dev = crtc->dev; | |
3021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3023 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3024 | u32 reg, temp; |
2c07245f | 3025 | |
e7e164db CW |
3026 | assert_transcoder_disabled(dev_priv, pipe); |
3027 | ||
cd986abb DV |
3028 | /* Write the TU size bits before fdi link training, so that error |
3029 | * detection works. */ | |
3030 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3031 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3032 | ||
c98e9dcf | 3033 | /* For PCH output, training FDI link */ |
674cf967 | 3034 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3035 | |
572deb37 DV |
3036 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3037 | * transcoder, and we actually should do this to not upset any PCH | |
3038 | * transcoder that already use the clock when we share it. | |
3039 | * | |
3040 | * Note that enable_pch_pll tries to do the right thing, but get_pch_pll | |
3041 | * unconditionally resets the pll - we need that to have the right LVDS | |
3042 | * enable sequence. */ | |
b6b4e185 | 3043 | ironlake_enable_pch_pll(intel_crtc); |
6f13b7b5 | 3044 | |
303b81e0 | 3045 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3046 | u32 sel; |
4b645f14 | 3047 | |
c98e9dcf | 3048 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3049 | switch (pipe) { |
3050 | default: | |
3051 | case 0: | |
3052 | temp |= TRANSA_DPLL_ENABLE; | |
3053 | sel = TRANSA_DPLLB_SEL; | |
3054 | break; | |
3055 | case 1: | |
3056 | temp |= TRANSB_DPLL_ENABLE; | |
3057 | sel = TRANSB_DPLLB_SEL; | |
3058 | break; | |
3059 | case 2: | |
3060 | temp |= TRANSC_DPLL_ENABLE; | |
3061 | sel = TRANSC_DPLLB_SEL; | |
3062 | break; | |
d64311ab | 3063 | } |
ee7b9f93 JB |
3064 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3065 | temp |= sel; | |
3066 | else | |
3067 | temp &= ~sel; | |
c98e9dcf | 3068 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3069 | } |
5eddb70b | 3070 | |
d9b6cb56 JB |
3071 | /* set transcoder timing, panel must allow it */ |
3072 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3073 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3074 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3075 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3076 | |
5eddb70b CW |
3077 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3078 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3079 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3080 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3081 | |
303b81e0 | 3082 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3083 | |
c98e9dcf JB |
3084 | /* For PCH DP, enable TRANS_DP_CTL */ |
3085 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3086 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3087 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 3088 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
3089 | reg = TRANS_DP_CTL(pipe); |
3090 | temp = I915_READ(reg); | |
3091 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3092 | TRANS_DP_SYNC_MASK | |
3093 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3094 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3095 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3096 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3097 | |
3098 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3099 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3100 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3101 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3102 | |
3103 | switch (intel_trans_dp_port_sel(crtc)) { | |
3104 | case PCH_DP_B: | |
5eddb70b | 3105 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3106 | break; |
3107 | case PCH_DP_C: | |
5eddb70b | 3108 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3109 | break; |
3110 | case PCH_DP_D: | |
5eddb70b | 3111 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3112 | break; |
3113 | default: | |
e95d41e1 | 3114 | BUG(); |
32f9d658 | 3115 | } |
2c07245f | 3116 | |
5eddb70b | 3117 | I915_WRITE(reg, temp); |
6be4a607 | 3118 | } |
b52eb4dc | 3119 | |
b8a4f404 | 3120 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3121 | } |
3122 | ||
1507e5bd PZ |
3123 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3124 | { | |
3125 | struct drm_device *dev = crtc->dev; | |
3126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3127 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
daed2dbb | 3128 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1507e5bd | 3129 | |
daed2dbb | 3130 | assert_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3131 | |
8c52b5e8 | 3132 | lpt_program_iclkip(crtc); |
1507e5bd | 3133 | |
0540e488 | 3134 | /* Set transcoder timing. */ |
daed2dbb PZ |
3135 | I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); |
3136 | I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); | |
3137 | I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); | |
1507e5bd | 3138 | |
daed2dbb PZ |
3139 | I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); |
3140 | I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); | |
3141 | I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); | |
3142 | I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
1507e5bd | 3143 | |
937bb610 | 3144 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3145 | } |
3146 | ||
ee7b9f93 JB |
3147 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3148 | { | |
3149 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3150 | ||
3151 | if (pll == NULL) | |
3152 | return; | |
3153 | ||
3154 | if (pll->refcount == 0) { | |
3155 | WARN(1, "bad PCH PLL refcount\n"); | |
3156 | return; | |
3157 | } | |
3158 | ||
3159 | --pll->refcount; | |
3160 | intel_crtc->pch_pll = NULL; | |
3161 | } | |
3162 | ||
3163 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3164 | { | |
3165 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3166 | struct intel_pch_pll *pll; | |
3167 | int i; | |
3168 | ||
3169 | pll = intel_crtc->pch_pll; | |
3170 | if (pll) { | |
3171 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3172 | intel_crtc->base.base.id, pll->pll_reg); | |
3173 | goto prepare; | |
3174 | } | |
3175 | ||
98b6bd99 DV |
3176 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3177 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3178 | i = intel_crtc->pipe; | |
3179 | pll = &dev_priv->pch_plls[i]; | |
3180 | ||
3181 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3182 | intel_crtc->base.base.id, pll->pll_reg); | |
3183 | ||
3184 | goto found; | |
3185 | } | |
3186 | ||
ee7b9f93 JB |
3187 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3188 | pll = &dev_priv->pch_plls[i]; | |
3189 | ||
3190 | /* Only want to check enabled timings first */ | |
3191 | if (pll->refcount == 0) | |
3192 | continue; | |
3193 | ||
3194 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3195 | fp == I915_READ(pll->fp0_reg)) { | |
3196 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3197 | intel_crtc->base.base.id, | |
3198 | pll->pll_reg, pll->refcount, pll->active); | |
3199 | ||
3200 | goto found; | |
3201 | } | |
3202 | } | |
3203 | ||
3204 | /* Ok no matching timings, maybe there's a free one? */ | |
3205 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3206 | pll = &dev_priv->pch_plls[i]; | |
3207 | if (pll->refcount == 0) { | |
3208 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3209 | intel_crtc->base.base.id, pll->pll_reg); | |
3210 | goto found; | |
3211 | } | |
3212 | } | |
3213 | ||
3214 | return NULL; | |
3215 | ||
3216 | found: | |
3217 | intel_crtc->pch_pll = pll; | |
3218 | pll->refcount++; | |
3219 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3220 | prepare: /* separate function? */ | |
3221 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3222 | |
e04c7350 CW |
3223 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3224 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3225 | POSTING_READ(pll->pll_reg); |
3226 | udelay(150); | |
e04c7350 CW |
3227 | |
3228 | I915_WRITE(pll->fp0_reg, fp); | |
3229 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3230 | pll->on = false; |
3231 | return pll; | |
3232 | } | |
3233 | ||
d4270e57 JB |
3234 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3235 | { | |
3236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3237 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3238 | u32 temp; |
3239 | ||
3240 | temp = I915_READ(dslreg); | |
3241 | udelay(500); | |
3242 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 JB |
3243 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3244 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3245 | } | |
3246 | } | |
3247 | ||
f67a559d JB |
3248 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3249 | { | |
3250 | struct drm_device *dev = crtc->dev; | |
3251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3252 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3253 | struct intel_encoder *encoder; |
f67a559d JB |
3254 | int pipe = intel_crtc->pipe; |
3255 | int plane = intel_crtc->plane; | |
3256 | u32 temp; | |
3257 | bool is_pch_port; | |
3258 | ||
08a48469 DV |
3259 | WARN_ON(!crtc->enabled); |
3260 | ||
f67a559d JB |
3261 | if (intel_crtc->active) |
3262 | return; | |
3263 | ||
3264 | intel_crtc->active = true; | |
3265 | intel_update_watermarks(dev); | |
3266 | ||
3267 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3268 | temp = I915_READ(PCH_LVDS); | |
3269 | if ((temp & LVDS_PORT_EN) == 0) | |
3270 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3271 | } | |
3272 | ||
fc316cbe | 3273 | is_pch_port = ironlake_crtc_driving_pch(crtc); |
f67a559d | 3274 | |
46b6f814 | 3275 | if (is_pch_port) { |
fff367c7 DV |
3276 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3277 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3278 | * enabling. */ | |
88cefb6c | 3279 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3280 | } else { |
3281 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3282 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3283 | } | |
f67a559d | 3284 | |
bf49ec8c DV |
3285 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3286 | if (encoder->pre_enable) | |
3287 | encoder->pre_enable(encoder); | |
f67a559d JB |
3288 | |
3289 | /* Enable panel fitting for LVDS */ | |
3290 | if (dev_priv->pch_pf_size && | |
547dc041 JN |
3291 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3292 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
f67a559d JB |
3293 | /* Force use of hard-coded filter coefficients |
3294 | * as some pre-programmed values are broken, | |
3295 | * e.g. x201. | |
3296 | */ | |
13888d78 PZ |
3297 | if (IS_IVYBRIDGE(dev)) |
3298 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3299 | PF_PIPE_SEL_IVB(pipe)); | |
3300 | else | |
3301 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
9db4a9c7 JB |
3302 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3303 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3304 | } |
3305 | ||
9c54c0dd JB |
3306 | /* |
3307 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3308 | * clocks enabled | |
3309 | */ | |
3310 | intel_crtc_load_lut(crtc); | |
3311 | ||
f67a559d JB |
3312 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3313 | intel_enable_plane(dev_priv, plane, pipe); | |
3314 | ||
3315 | if (is_pch_port) | |
3316 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3317 | |
d1ebd816 | 3318 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3319 | intel_update_fbc(dev); |
d1ebd816 BW |
3320 | mutex_unlock(&dev->struct_mutex); |
3321 | ||
6b383a7f | 3322 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3323 | |
fa5c73b1 DV |
3324 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3325 | encoder->enable(encoder); | |
61b77ddd DV |
3326 | |
3327 | if (HAS_PCH_CPT(dev)) | |
3328 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
6ce94100 DV |
3329 | |
3330 | /* | |
3331 | * There seems to be a race in PCH platform hw (at least on some | |
3332 | * outputs) where an enabled pipe still completes any pageflip right | |
3333 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3334 | * as the first vblank happend, everything works as expected. Hence just | |
3335 | * wait for one vblank before returning to avoid strange things | |
3336 | * happening. | |
3337 | */ | |
3338 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3339 | } |
3340 | ||
4f771f10 PZ |
3341 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3342 | { | |
3343 | struct drm_device *dev = crtc->dev; | |
3344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3346 | struct intel_encoder *encoder; | |
3347 | int pipe = intel_crtc->pipe; | |
3348 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3349 | bool is_pch_port; |
3350 | ||
3351 | WARN_ON(!crtc->enabled); | |
3352 | ||
3353 | if (intel_crtc->active) | |
3354 | return; | |
3355 | ||
3356 | intel_crtc->active = true; | |
3357 | intel_update_watermarks(dev); | |
3358 | ||
fc316cbe | 3359 | is_pch_port = haswell_crtc_driving_pch(crtc); |
4f771f10 | 3360 | |
83616634 | 3361 | if (is_pch_port) |
04945641 | 3362 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3363 | |
3364 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3365 | if (encoder->pre_enable) | |
3366 | encoder->pre_enable(encoder); | |
3367 | ||
1f544388 | 3368 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3369 | |
1f544388 | 3370 | /* Enable panel fitting for eDP */ |
547dc041 JN |
3371 | if (dev_priv->pch_pf_size && |
3372 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4f771f10 PZ |
3373 | /* Force use of hard-coded filter coefficients |
3374 | * as some pre-programmed values are broken, | |
3375 | * e.g. x201. | |
3376 | */ | |
54075a7d PZ |
3377 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3378 | PF_PIPE_SEL_IVB(pipe)); | |
4f771f10 PZ |
3379 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3380 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
3381 | } | |
3382 | ||
3383 | /* | |
3384 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3385 | * clocks enabled | |
3386 | */ | |
3387 | intel_crtc_load_lut(crtc); | |
3388 | ||
1f544388 PZ |
3389 | intel_ddi_set_pipe_settings(crtc); |
3390 | intel_ddi_enable_pipe_func(crtc); | |
4f771f10 PZ |
3391 | |
3392 | intel_enable_pipe(dev_priv, pipe, is_pch_port); | |
3393 | intel_enable_plane(dev_priv, plane, pipe); | |
3394 | ||
3395 | if (is_pch_port) | |
1507e5bd | 3396 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3397 | |
3398 | mutex_lock(&dev->struct_mutex); | |
3399 | intel_update_fbc(dev); | |
3400 | mutex_unlock(&dev->struct_mutex); | |
3401 | ||
3402 | intel_crtc_update_cursor(crtc, true); | |
3403 | ||
3404 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3405 | encoder->enable(encoder); | |
3406 | ||
4f771f10 PZ |
3407 | /* |
3408 | * There seems to be a race in PCH platform hw (at least on some | |
3409 | * outputs) where an enabled pipe still completes any pageflip right | |
3410 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3411 | * as the first vblank happend, everything works as expected. Hence just | |
3412 | * wait for one vblank before returning to avoid strange things | |
3413 | * happening. | |
3414 | */ | |
3415 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3416 | } | |
3417 | ||
6be4a607 JB |
3418 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3419 | { | |
3420 | struct drm_device *dev = crtc->dev; | |
3421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3423 | struct intel_encoder *encoder; |
6be4a607 JB |
3424 | int pipe = intel_crtc->pipe; |
3425 | int plane = intel_crtc->plane; | |
5eddb70b | 3426 | u32 reg, temp; |
b52eb4dc | 3427 | |
ef9c3aee | 3428 | |
f7abfe8b CW |
3429 | if (!intel_crtc->active) |
3430 | return; | |
3431 | ||
ea9d758d DV |
3432 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3433 | encoder->disable(encoder); | |
3434 | ||
e6c3a2a6 | 3435 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3436 | drm_vblank_off(dev, pipe); |
6b383a7f | 3437 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3438 | |
b24e7179 | 3439 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3440 | |
973d04f9 CW |
3441 | if (dev_priv->cfb_plane == plane) |
3442 | intel_disable_fbc(dev); | |
2c07245f | 3443 | |
b24e7179 | 3444 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3445 | |
6be4a607 | 3446 | /* Disable PF */ |
9db4a9c7 JB |
3447 | I915_WRITE(PF_CTL(pipe), 0); |
3448 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3449 | |
bf49ec8c DV |
3450 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3451 | if (encoder->post_disable) | |
3452 | encoder->post_disable(encoder); | |
2c07245f | 3453 | |
0fc932b8 | 3454 | ironlake_fdi_disable(crtc); |
249c0e64 | 3455 | |
b8a4f404 | 3456 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
913d8d11 | 3457 | |
6be4a607 JB |
3458 | if (HAS_PCH_CPT(dev)) { |
3459 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3460 | reg = TRANS_DP_CTL(pipe); |
3461 | temp = I915_READ(reg); | |
3462 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3463 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3464 | I915_WRITE(reg, temp); |
6be4a607 JB |
3465 | |
3466 | /* disable DPLL_SEL */ | |
3467 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3468 | switch (pipe) { |
3469 | case 0: | |
d64311ab | 3470 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3471 | break; |
3472 | case 1: | |
6be4a607 | 3473 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3474 | break; |
3475 | case 2: | |
4b645f14 | 3476 | /* C shares PLL A or B */ |
d64311ab | 3477 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3478 | break; |
3479 | default: | |
3480 | BUG(); /* wtf */ | |
3481 | } | |
6be4a607 | 3482 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3483 | } |
e3421a18 | 3484 | |
6be4a607 | 3485 | /* disable PCH DPLL */ |
ee7b9f93 | 3486 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3487 | |
88cefb6c | 3488 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3489 | |
f7abfe8b | 3490 | intel_crtc->active = false; |
6b383a7f | 3491 | intel_update_watermarks(dev); |
d1ebd816 BW |
3492 | |
3493 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3494 | intel_update_fbc(dev); |
d1ebd816 | 3495 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3496 | } |
1b3c7a47 | 3497 | |
4f771f10 | 3498 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3499 | { |
4f771f10 PZ |
3500 | struct drm_device *dev = crtc->dev; |
3501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3503 | struct intel_encoder *encoder; |
3504 | int pipe = intel_crtc->pipe; | |
3505 | int plane = intel_crtc->plane; | |
ad80a810 | 3506 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
83616634 | 3507 | bool is_pch_port; |
ee7b9f93 | 3508 | |
4f771f10 PZ |
3509 | if (!intel_crtc->active) |
3510 | return; | |
3511 | ||
83616634 PZ |
3512 | is_pch_port = haswell_crtc_driving_pch(crtc); |
3513 | ||
4f771f10 PZ |
3514 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3515 | encoder->disable(encoder); | |
3516 | ||
3517 | intel_crtc_wait_for_pending_flips(crtc); | |
3518 | drm_vblank_off(dev, pipe); | |
3519 | intel_crtc_update_cursor(crtc, false); | |
3520 | ||
3521 | intel_disable_plane(dev_priv, plane, pipe); | |
3522 | ||
3523 | if (dev_priv->cfb_plane == plane) | |
3524 | intel_disable_fbc(dev); | |
3525 | ||
3526 | intel_disable_pipe(dev_priv, pipe); | |
3527 | ||
ad80a810 | 3528 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 PZ |
3529 | |
3530 | /* Disable PF */ | |
3531 | I915_WRITE(PF_CTL(pipe), 0); | |
3532 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3533 | ||
1f544388 | 3534 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3535 | |
3536 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3537 | if (encoder->post_disable) | |
3538 | encoder->post_disable(encoder); | |
3539 | ||
83616634 | 3540 | if (is_pch_port) { |
ab4d966c | 3541 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 3542 | intel_ddi_fdi_disable(crtc); |
83616634 | 3543 | } |
4f771f10 PZ |
3544 | |
3545 | intel_crtc->active = false; | |
3546 | intel_update_watermarks(dev); | |
3547 | ||
3548 | mutex_lock(&dev->struct_mutex); | |
3549 | intel_update_fbc(dev); | |
3550 | mutex_unlock(&dev->struct_mutex); | |
3551 | } | |
3552 | ||
ee7b9f93 JB |
3553 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3554 | { | |
3555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3556 | intel_put_pch_pll(intel_crtc); | |
3557 | } | |
3558 | ||
6441ab5f PZ |
3559 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3560 | { | |
a5c961d1 PZ |
3561 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3562 | ||
3563 | /* Stop saying we're using TRANSCODER_EDP because some other CRTC might | |
3564 | * start using it. */ | |
1a240d4d | 3565 | intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
a5c961d1 | 3566 | |
6441ab5f PZ |
3567 | intel_ddi_put_crtc_pll(crtc); |
3568 | } | |
3569 | ||
02e792fb DV |
3570 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3571 | { | |
02e792fb | 3572 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3573 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3574 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3575 | |
23f09ce3 | 3576 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3577 | dev_priv->mm.interruptible = false; |
3578 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3579 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3580 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3581 | } |
02e792fb | 3582 | |
5dcdbcb0 CW |
3583 | /* Let userspace switch the overlay on again. In most cases userspace |
3584 | * has to recompute where to put it anyway. | |
3585 | */ | |
02e792fb DV |
3586 | } |
3587 | ||
0b8765c6 | 3588 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3589 | { |
3590 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3591 | struct drm_i915_private *dev_priv = dev->dev_private; |
3592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3593 | struct intel_encoder *encoder; |
79e53945 | 3594 | int pipe = intel_crtc->pipe; |
80824003 | 3595 | int plane = intel_crtc->plane; |
79e53945 | 3596 | |
08a48469 DV |
3597 | WARN_ON(!crtc->enabled); |
3598 | ||
f7abfe8b CW |
3599 | if (intel_crtc->active) |
3600 | return; | |
3601 | ||
3602 | intel_crtc->active = true; | |
6b383a7f CW |
3603 | intel_update_watermarks(dev); |
3604 | ||
63d7bbe9 | 3605 | intel_enable_pll(dev_priv, pipe); |
040484af | 3606 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3607 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3608 | |
0b8765c6 | 3609 | intel_crtc_load_lut(crtc); |
bed4a673 | 3610 | intel_update_fbc(dev); |
79e53945 | 3611 | |
0b8765c6 JB |
3612 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3613 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3614 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3615 | |
fa5c73b1 DV |
3616 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3617 | encoder->enable(encoder); | |
0b8765c6 | 3618 | } |
79e53945 | 3619 | |
0b8765c6 JB |
3620 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3621 | { | |
3622 | struct drm_device *dev = crtc->dev; | |
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3625 | struct intel_encoder *encoder; |
0b8765c6 JB |
3626 | int pipe = intel_crtc->pipe; |
3627 | int plane = intel_crtc->plane; | |
b690e96c | 3628 | |
ef9c3aee | 3629 | |
f7abfe8b CW |
3630 | if (!intel_crtc->active) |
3631 | return; | |
3632 | ||
ea9d758d DV |
3633 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3634 | encoder->disable(encoder); | |
3635 | ||
0b8765c6 | 3636 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3637 | intel_crtc_wait_for_pending_flips(crtc); |
3638 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3639 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3640 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3641 | |
973d04f9 CW |
3642 | if (dev_priv->cfb_plane == plane) |
3643 | intel_disable_fbc(dev); | |
79e53945 | 3644 | |
b24e7179 | 3645 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3646 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3647 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3648 | |
f7abfe8b | 3649 | intel_crtc->active = false; |
6b383a7f CW |
3650 | intel_update_fbc(dev); |
3651 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3652 | } |
3653 | ||
ee7b9f93 JB |
3654 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3655 | { | |
3656 | } | |
3657 | ||
976f8a20 DV |
3658 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3659 | bool enabled) | |
2c07245f ZW |
3660 | { |
3661 | struct drm_device *dev = crtc->dev; | |
3662 | struct drm_i915_master_private *master_priv; | |
3663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3664 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3665 | |
3666 | if (!dev->primary->master) | |
3667 | return; | |
3668 | ||
3669 | master_priv = dev->primary->master->driver_priv; | |
3670 | if (!master_priv->sarea_priv) | |
3671 | return; | |
3672 | ||
79e53945 JB |
3673 | switch (pipe) { |
3674 | case 0: | |
3675 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3676 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3677 | break; | |
3678 | case 1: | |
3679 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3680 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3681 | break; | |
3682 | default: | |
9db4a9c7 | 3683 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3684 | break; |
3685 | } | |
79e53945 JB |
3686 | } |
3687 | ||
976f8a20 DV |
3688 | /** |
3689 | * Sets the power management mode of the pipe and plane. | |
3690 | */ | |
3691 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3692 | { | |
3693 | struct drm_device *dev = crtc->dev; | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3695 | struct intel_encoder *intel_encoder; | |
3696 | bool enable = false; | |
3697 | ||
3698 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3699 | enable |= intel_encoder->connectors_active; | |
3700 | ||
3701 | if (enable) | |
3702 | dev_priv->display.crtc_enable(crtc); | |
3703 | else | |
3704 | dev_priv->display.crtc_disable(crtc); | |
3705 | ||
3706 | intel_crtc_update_sarea(crtc, enable); | |
3707 | } | |
3708 | ||
3709 | static void intel_crtc_noop(struct drm_crtc *crtc) | |
3710 | { | |
3711 | } | |
3712 | ||
cdd59983 CW |
3713 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3714 | { | |
cdd59983 | 3715 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3716 | struct drm_connector *connector; |
ee7b9f93 | 3717 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 3718 | |
976f8a20 DV |
3719 | /* crtc should still be enabled when we disable it. */ |
3720 | WARN_ON(!crtc->enabled); | |
3721 | ||
3722 | dev_priv->display.crtc_disable(crtc); | |
3723 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
3724 | dev_priv->display.off(crtc); |
3725 | ||
931872fc CW |
3726 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3727 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3728 | |
3729 | if (crtc->fb) { | |
3730 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3731 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3732 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3733 | crtc->fb = NULL; |
3734 | } | |
3735 | ||
3736 | /* Update computed state. */ | |
3737 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3738 | if (!connector->encoder || !connector->encoder->crtc) | |
3739 | continue; | |
3740 | ||
3741 | if (connector->encoder->crtc != crtc) | |
3742 | continue; | |
3743 | ||
3744 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3745 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3746 | } |
3747 | } | |
3748 | ||
a261b246 | 3749 | void intel_modeset_disable(struct drm_device *dev) |
79e53945 | 3750 | { |
a261b246 DV |
3751 | struct drm_crtc *crtc; |
3752 | ||
3753 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3754 | if (crtc->enabled) | |
3755 | intel_crtc_disable(crtc); | |
3756 | } | |
79e53945 JB |
3757 | } |
3758 | ||
1f703855 | 3759 | void intel_encoder_noop(struct drm_encoder *encoder) |
79e53945 | 3760 | { |
7e7d76c3 JB |
3761 | } |
3762 | ||
ea5b213a | 3763 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3764 | { |
4ef69c7a | 3765 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3766 | |
ea5b213a CW |
3767 | drm_encoder_cleanup(encoder); |
3768 | kfree(intel_encoder); | |
7e7d76c3 JB |
3769 | } |
3770 | ||
5ab432ef DV |
3771 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3772 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3773 | * state of the entire output pipe. */ | |
3774 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
7e7d76c3 | 3775 | { |
5ab432ef DV |
3776 | if (mode == DRM_MODE_DPMS_ON) { |
3777 | encoder->connectors_active = true; | |
3778 | ||
b2cabb0e | 3779 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3780 | } else { |
3781 | encoder->connectors_active = false; | |
3782 | ||
b2cabb0e | 3783 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3784 | } |
79e53945 JB |
3785 | } |
3786 | ||
0a91ca29 DV |
3787 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3788 | * internal consistency). */ | |
b980514c | 3789 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3790 | { |
0a91ca29 DV |
3791 | if (connector->get_hw_state(connector)) { |
3792 | struct intel_encoder *encoder = connector->encoder; | |
3793 | struct drm_crtc *crtc; | |
3794 | bool encoder_enabled; | |
3795 | enum pipe pipe; | |
3796 | ||
3797 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3798 | connector->base.base.id, | |
3799 | drm_get_connector_name(&connector->base)); | |
3800 | ||
3801 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3802 | "wrong connector dpms state\n"); | |
3803 | WARN(connector->base.encoder != &encoder->base, | |
3804 | "active connector not linked to encoder\n"); | |
3805 | WARN(!encoder->connectors_active, | |
3806 | "encoder->connectors_active not set\n"); | |
3807 | ||
3808 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3809 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3810 | if (WARN_ON(!encoder->base.crtc)) | |
3811 | return; | |
3812 | ||
3813 | crtc = encoder->base.crtc; | |
3814 | ||
3815 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3816 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3817 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3818 | "encoder active on the wrong pipe\n"); | |
3819 | } | |
79e53945 JB |
3820 | } |
3821 | ||
5ab432ef DV |
3822 | /* Even simpler default implementation, if there's really no special case to |
3823 | * consider. */ | |
3824 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3825 | { |
5ab432ef | 3826 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3827 | |
5ab432ef DV |
3828 | /* All the simple cases only support two dpms states. */ |
3829 | if (mode != DRM_MODE_DPMS_ON) | |
3830 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3831 | |
5ab432ef DV |
3832 | if (mode == connector->dpms) |
3833 | return; | |
3834 | ||
3835 | connector->dpms = mode; | |
3836 | ||
3837 | /* Only need to change hw state when actually enabled */ | |
3838 | if (encoder->base.crtc) | |
3839 | intel_encoder_dpms(encoder, mode); | |
3840 | else | |
8af6cf88 | 3841 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3842 | |
b980514c | 3843 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3844 | } |
3845 | ||
f0947c37 DV |
3846 | /* Simple connector->get_hw_state implementation for encoders that support only |
3847 | * one connector and no cloning and hence the encoder state determines the state | |
3848 | * of the connector. */ | |
3849 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3850 | { |
24929352 | 3851 | enum pipe pipe = 0; |
f0947c37 | 3852 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3853 | |
f0947c37 | 3854 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3855 | } |
3856 | ||
79e53945 | 3857 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
35313cde | 3858 | const struct drm_display_mode *mode, |
79e53945 JB |
3859 | struct drm_display_mode *adjusted_mode) |
3860 | { | |
2c07245f | 3861 | struct drm_device *dev = crtc->dev; |
89749350 | 3862 | |
bad720ff | 3863 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3864 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3865 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3866 | return false; | |
2c07245f | 3867 | } |
89749350 | 3868 | |
f9bef081 DV |
3869 | /* All interlaced capable intel hw wants timings in frames. Note though |
3870 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3871 | * timings, so we need to be careful not to clobber these.*/ | |
3872 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) | |
3873 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3874 | |
44f46b42 CW |
3875 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3876 | * with a hsync front porch of 0. | |
3877 | */ | |
3878 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
3879 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
3880 | return false; | |
3881 | ||
79e53945 JB |
3882 | return true; |
3883 | } | |
3884 | ||
25eb05fc JB |
3885 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3886 | { | |
3887 | return 400000; /* FIXME */ | |
3888 | } | |
3889 | ||
e70236a8 JB |
3890 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3891 | { | |
3892 | return 400000; | |
3893 | } | |
79e53945 | 3894 | |
e70236a8 | 3895 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3896 | { |
e70236a8 JB |
3897 | return 333000; |
3898 | } | |
79e53945 | 3899 | |
e70236a8 JB |
3900 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3901 | { | |
3902 | return 200000; | |
3903 | } | |
79e53945 | 3904 | |
e70236a8 JB |
3905 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3906 | { | |
3907 | u16 gcfgc = 0; | |
79e53945 | 3908 | |
e70236a8 JB |
3909 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3910 | ||
3911 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3912 | return 133000; | |
3913 | else { | |
3914 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3915 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3916 | return 333000; | |
3917 | default: | |
3918 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3919 | return 190000; | |
79e53945 | 3920 | } |
e70236a8 JB |
3921 | } |
3922 | } | |
3923 | ||
3924 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3925 | { | |
3926 | return 266000; | |
3927 | } | |
3928 | ||
3929 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3930 | { | |
3931 | u16 hpllcc = 0; | |
3932 | /* Assume that the hardware is in the high speed state. This | |
3933 | * should be the default. | |
3934 | */ | |
3935 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3936 | case GC_CLOCK_133_200: | |
3937 | case GC_CLOCK_100_200: | |
3938 | return 200000; | |
3939 | case GC_CLOCK_166_250: | |
3940 | return 250000; | |
3941 | case GC_CLOCK_100_133: | |
79e53945 | 3942 | return 133000; |
e70236a8 | 3943 | } |
79e53945 | 3944 | |
e70236a8 JB |
3945 | /* Shouldn't happen */ |
3946 | return 0; | |
3947 | } | |
79e53945 | 3948 | |
e70236a8 JB |
3949 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3950 | { | |
3951 | return 133000; | |
79e53945 JB |
3952 | } |
3953 | ||
2c07245f | 3954 | static void |
e69d0bc1 | 3955 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
2c07245f ZW |
3956 | { |
3957 | while (*num > 0xffffff || *den > 0xffffff) { | |
3958 | *num >>= 1; | |
3959 | *den >>= 1; | |
3960 | } | |
3961 | } | |
3962 | ||
e69d0bc1 DV |
3963 | void |
3964 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
3965 | int pixel_clock, int link_clock, | |
3966 | struct intel_link_m_n *m_n) | |
2c07245f | 3967 | { |
e69d0bc1 | 3968 | m_n->tu = 64; |
22ed1113 CW |
3969 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
3970 | m_n->gmch_n = link_clock * nlanes * 8; | |
e69d0bc1 | 3971 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
22ed1113 CW |
3972 | m_n->link_m = pixel_clock; |
3973 | m_n->link_n = link_clock; | |
e69d0bc1 | 3974 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2c07245f ZW |
3975 | } |
3976 | ||
a7615030 CW |
3977 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3978 | { | |
72bbe58c KP |
3979 | if (i915_panel_use_ssc >= 0) |
3980 | return i915_panel_use_ssc != 0; | |
3981 | return dev_priv->lvds_use_ssc | |
435793df | 3982 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3983 | } |
3984 | ||
5a354204 JB |
3985 | /** |
3986 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3987 | * @crtc: CRTC structure | |
3b5c78a3 | 3988 | * @mode: requested mode |
5a354204 JB |
3989 | * |
3990 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3991 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3992 | * | |
3993 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
3994 | * isn't ideal, because the connected output supports a lesser or restricted | |
3995 | * set of depths. Resolve that here: | |
3996 | * LVDS typically supports only 6bpc, so clamp down in that case | |
3997 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
3998 | * Displays may support a restricted set as well, check EDID and clamp as | |
3999 | * appropriate. | |
3b5c78a3 | 4000 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4001 | * |
4002 | * RETURNS: | |
4003 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4004 | * true if they don't match). | |
4005 | */ | |
4006 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
94352cf9 | 4007 | struct drm_framebuffer *fb, |
3b5c78a3 AJ |
4008 | unsigned int *pipe_bpp, |
4009 | struct drm_display_mode *mode) | |
5a354204 JB |
4010 | { |
4011 | struct drm_device *dev = crtc->dev; | |
4012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5a354204 | 4013 | struct drm_connector *connector; |
6c2b7c12 | 4014 | struct intel_encoder *intel_encoder; |
5a354204 JB |
4015 | unsigned int display_bpc = UINT_MAX, bpc; |
4016 | ||
4017 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
6c2b7c12 | 4018 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5a354204 JB |
4019 | |
4020 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4021 | unsigned int lvds_bpc; | |
4022 | ||
4023 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4024 | LVDS_A3_POWER_UP) | |
4025 | lvds_bpc = 8; | |
4026 | else | |
4027 | lvds_bpc = 6; | |
4028 | ||
4029 | if (lvds_bpc < display_bpc) { | |
82820490 | 4030 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4031 | display_bpc = lvds_bpc; |
4032 | } | |
4033 | continue; | |
4034 | } | |
4035 | ||
5a354204 JB |
4036 | /* Not one of the known troublemakers, check the EDID */ |
4037 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4038 | head) { | |
6c2b7c12 | 4039 | if (connector->encoder != &intel_encoder->base) |
5a354204 JB |
4040 | continue; |
4041 | ||
62ac41a6 JB |
4042 | /* Don't use an invalid EDID bpc value */ |
4043 | if (connector->display_info.bpc && | |
4044 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4045 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4046 | display_bpc = connector->display_info.bpc; |
4047 | } | |
4048 | } | |
4049 | ||
4050 | /* | |
4051 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4052 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4053 | */ | |
4054 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4055 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 4056 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
4057 | display_bpc = 12; |
4058 | } else { | |
82820490 | 4059 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
4060 | display_bpc = 8; |
4061 | } | |
4062 | } | |
4063 | } | |
4064 | ||
3b5c78a3 AJ |
4065 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4066 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
4067 | display_bpc = 6; | |
4068 | } | |
4069 | ||
5a354204 JB |
4070 | /* |
4071 | * We could just drive the pipe at the highest bpc all the time and | |
4072 | * enable dithering as needed, but that costs bandwidth. So choose | |
4073 | * the minimum value that expresses the full color range of the fb but | |
4074 | * also stays within the max display bpc discovered above. | |
4075 | */ | |
4076 | ||
94352cf9 | 4077 | switch (fb->depth) { |
5a354204 JB |
4078 | case 8: |
4079 | bpc = 8; /* since we go through a colormap */ | |
4080 | break; | |
4081 | case 15: | |
4082 | case 16: | |
4083 | bpc = 6; /* min is 18bpp */ | |
4084 | break; | |
4085 | case 24: | |
578393cd | 4086 | bpc = 8; |
5a354204 JB |
4087 | break; |
4088 | case 30: | |
578393cd | 4089 | bpc = 10; |
5a354204 JB |
4090 | break; |
4091 | case 48: | |
578393cd | 4092 | bpc = 12; |
5a354204 JB |
4093 | break; |
4094 | default: | |
4095 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
4096 | bpc = min((unsigned int)8, display_bpc); | |
4097 | break; | |
4098 | } | |
4099 | ||
578393cd KP |
4100 | display_bpc = min(display_bpc, bpc); |
4101 | ||
82820490 AJ |
4102 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
4103 | bpc, display_bpc); | |
5a354204 | 4104 | |
578393cd | 4105 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
4106 | |
4107 | return display_bpc != bpc; | |
4108 | } | |
4109 | ||
a0c4da24 JB |
4110 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4111 | { | |
4112 | struct drm_device *dev = crtc->dev; | |
4113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4114 | int refclk = 27000; /* for DP & HDMI */ | |
4115 | ||
4116 | return 100000; /* only one validated so far */ | |
4117 | ||
4118 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4119 | refclk = 96000; | |
4120 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4121 | if (intel_panel_use_ssc(dev_priv)) | |
4122 | refclk = 100000; | |
4123 | else | |
4124 | refclk = 96000; | |
4125 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4126 | refclk = 100000; | |
4127 | } | |
4128 | ||
4129 | return refclk; | |
4130 | } | |
4131 | ||
c65d77d8 JB |
4132 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4133 | { | |
4134 | struct drm_device *dev = crtc->dev; | |
4135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4136 | int refclk; | |
4137 | ||
a0c4da24 JB |
4138 | if (IS_VALLEYVIEW(dev)) { |
4139 | refclk = vlv_get_refclk(crtc); | |
4140 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
4141 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4142 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4143 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4144 | refclk / 1000); | |
4145 | } else if (!IS_GEN2(dev)) { | |
4146 | refclk = 96000; | |
4147 | } else { | |
4148 | refclk = 48000; | |
4149 | } | |
4150 | ||
4151 | return refclk; | |
4152 | } | |
4153 | ||
4154 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
4155 | intel_clock_t *clock) | |
4156 | { | |
4157 | /* SDVO TV has fixed PLL values depend on its clock range, | |
4158 | this mirrors vbios setting. */ | |
4159 | if (adjusted_mode->clock >= 100000 | |
4160 | && adjusted_mode->clock < 140500) { | |
4161 | clock->p1 = 2; | |
4162 | clock->p2 = 10; | |
4163 | clock->n = 3; | |
4164 | clock->m1 = 16; | |
4165 | clock->m2 = 8; | |
4166 | } else if (adjusted_mode->clock >= 140500 | |
4167 | && adjusted_mode->clock <= 200000) { | |
4168 | clock->p1 = 1; | |
4169 | clock->p2 = 10; | |
4170 | clock->n = 6; | |
4171 | clock->m1 = 12; | |
4172 | clock->m2 = 8; | |
4173 | } | |
4174 | } | |
4175 | ||
a7516a05 JB |
4176 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
4177 | intel_clock_t *clock, | |
4178 | intel_clock_t *reduced_clock) | |
4179 | { | |
4180 | struct drm_device *dev = crtc->dev; | |
4181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4183 | int pipe = intel_crtc->pipe; | |
4184 | u32 fp, fp2 = 0; | |
4185 | ||
4186 | if (IS_PINEVIEW(dev)) { | |
4187 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
4188 | if (reduced_clock) | |
4189 | fp2 = (1 << reduced_clock->n) << 16 | | |
4190 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
4191 | } else { | |
4192 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
4193 | if (reduced_clock) | |
4194 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
4195 | reduced_clock->m2; | |
4196 | } | |
4197 | ||
4198 | I915_WRITE(FP0(pipe), fp); | |
4199 | ||
4200 | intel_crtc->lowfreq_avail = false; | |
4201 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4202 | reduced_clock && i915_powersave) { | |
4203 | I915_WRITE(FP1(pipe), fp2); | |
4204 | intel_crtc->lowfreq_avail = true; | |
4205 | } else { | |
4206 | I915_WRITE(FP1(pipe), fp); | |
4207 | } | |
4208 | } | |
4209 | ||
a0c4da24 JB |
4210 | static void vlv_update_pll(struct drm_crtc *crtc, |
4211 | struct drm_display_mode *mode, | |
4212 | struct drm_display_mode *adjusted_mode, | |
4213 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
2a8f64ca | 4214 | int num_connectors) |
a0c4da24 JB |
4215 | { |
4216 | struct drm_device *dev = crtc->dev; | |
4217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4219 | int pipe = intel_crtc->pipe; | |
4220 | u32 dpll, mdiv, pdiv; | |
4221 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
2a8f64ca VP |
4222 | bool is_sdvo; |
4223 | u32 temp; | |
a0c4da24 | 4224 | |
2a8f64ca VP |
4225 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4226 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
a0c4da24 | 4227 | |
2a8f64ca VP |
4228 | dpll = DPLL_VGA_MODE_DIS; |
4229 | dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; | |
4230 | dpll |= DPLL_REFA_CLK_ENABLE_VLV; | |
4231 | dpll |= DPLL_INTEGRATED_CLOCK_VLV; | |
4232 | ||
4233 | I915_WRITE(DPLL(pipe), dpll); | |
4234 | POSTING_READ(DPLL(pipe)); | |
a0c4da24 JB |
4235 | |
4236 | bestn = clock->n; | |
4237 | bestm1 = clock->m1; | |
4238 | bestm2 = clock->m2; | |
4239 | bestp1 = clock->p1; | |
4240 | bestp2 = clock->p2; | |
4241 | ||
2a8f64ca VP |
4242 | /* |
4243 | * In Valleyview PLL and program lane counter registers are exposed | |
4244 | * through DPIO interface | |
4245 | */ | |
a0c4da24 JB |
4246 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4247 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4248 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4249 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4250 | mdiv |= (1 << DPIO_K_SHIFT); | |
4251 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4252 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4253 | ||
4254 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4255 | ||
2a8f64ca | 4256 | pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | |
a0c4da24 | 4257 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
2a8f64ca VP |
4258 | (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | |
4259 | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
a0c4da24 JB |
4260 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4261 | ||
2a8f64ca | 4262 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); |
a0c4da24 JB |
4263 | |
4264 | dpll |= DPLL_VCO_ENABLE; | |
4265 | I915_WRITE(DPLL(pipe), dpll); | |
4266 | POSTING_READ(DPLL(pipe)); | |
4267 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4268 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4269 | ||
2a8f64ca VP |
4270 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); |
4271 | ||
4272 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4273 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4274 | ||
4275 | I915_WRITE(DPLL(pipe), dpll); | |
4276 | ||
4277 | /* Wait for the clocks to stabilize. */ | |
4278 | POSTING_READ(DPLL(pipe)); | |
4279 | udelay(150); | |
a0c4da24 | 4280 | |
2a8f64ca VP |
4281 | temp = 0; |
4282 | if (is_sdvo) { | |
4283 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
a0c4da24 JB |
4284 | if (temp > 1) |
4285 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4286 | else | |
4287 | temp = 0; | |
a0c4da24 | 4288 | } |
2a8f64ca VP |
4289 | I915_WRITE(DPLL_MD(pipe), temp); |
4290 | POSTING_READ(DPLL_MD(pipe)); | |
a0c4da24 | 4291 | |
2a8f64ca VP |
4292 | /* Now program lane control registers */ |
4293 | if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) | |
4294 | || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
4295 | { | |
4296 | temp = 0x1000C4; | |
4297 | if(pipe == 1) | |
4298 | temp |= (1 << 21); | |
4299 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); | |
4300 | } | |
4301 | if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP)) | |
4302 | { | |
4303 | temp = 0x1000C4; | |
4304 | if(pipe == 1) | |
4305 | temp |= (1 << 21); | |
4306 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); | |
4307 | } | |
a0c4da24 JB |
4308 | } |
4309 | ||
eb1cbe48 DV |
4310 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4311 | struct drm_display_mode *mode, | |
4312 | struct drm_display_mode *adjusted_mode, | |
4313 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4314 | int num_connectors) | |
4315 | { | |
4316 | struct drm_device *dev = crtc->dev; | |
4317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4319 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4320 | int pipe = intel_crtc->pipe; |
4321 | u32 dpll; | |
4322 | bool is_sdvo; | |
4323 | ||
2a8f64ca VP |
4324 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4325 | ||
eb1cbe48 DV |
4326 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4327 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4328 | ||
4329 | dpll = DPLL_VGA_MODE_DIS; | |
4330 | ||
4331 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4332 | dpll |= DPLLB_MODE_LVDS; | |
4333 | else | |
4334 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4335 | if (is_sdvo) { | |
4336 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4337 | if (pixel_multiplier > 1) { | |
4338 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4339 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4340 | } | |
4341 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4342 | } | |
4343 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4344 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4345 | ||
4346 | /* compute bitmask from p1 value */ | |
4347 | if (IS_PINEVIEW(dev)) | |
4348 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4349 | else { | |
4350 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4351 | if (IS_G4X(dev) && reduced_clock) | |
4352 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4353 | } | |
4354 | switch (clock->p2) { | |
4355 | case 5: | |
4356 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4357 | break; | |
4358 | case 7: | |
4359 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4360 | break; | |
4361 | case 10: | |
4362 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4363 | break; | |
4364 | case 14: | |
4365 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4366 | break; | |
4367 | } | |
4368 | if (INTEL_INFO(dev)->gen >= 4) | |
4369 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4370 | ||
4371 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4372 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4373 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4374 | /* XXX: just matching BIOS for now */ | |
4375 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4376 | dpll |= 3; | |
4377 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4378 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4379 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4380 | else | |
4381 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4382 | ||
4383 | dpll |= DPLL_VCO_ENABLE; | |
4384 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4385 | POSTING_READ(DPLL(pipe)); | |
4386 | udelay(150); | |
4387 | ||
dafd226c DV |
4388 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4389 | if (encoder->pre_pll_enable) | |
4390 | encoder->pre_pll_enable(encoder); | |
4391 | ||
eb1cbe48 DV |
4392 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
4393 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4394 | ||
4395 | I915_WRITE(DPLL(pipe), dpll); | |
4396 | ||
4397 | /* Wait for the clocks to stabilize. */ | |
4398 | POSTING_READ(DPLL(pipe)); | |
4399 | udelay(150); | |
4400 | ||
4401 | if (INTEL_INFO(dev)->gen >= 4) { | |
4402 | u32 temp = 0; | |
4403 | if (is_sdvo) { | |
4404 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4405 | if (temp > 1) | |
4406 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4407 | else | |
4408 | temp = 0; | |
4409 | } | |
4410 | I915_WRITE(DPLL_MD(pipe), temp); | |
4411 | } else { | |
4412 | /* The pixel multiplier can only be updated once the | |
4413 | * DPLL is enabled and the clocks are stable. | |
4414 | * | |
4415 | * So write it again. | |
4416 | */ | |
4417 | I915_WRITE(DPLL(pipe), dpll); | |
4418 | } | |
4419 | } | |
4420 | ||
4421 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
4422 | struct drm_display_mode *adjusted_mode, | |
2a8f64ca | 4423 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4424 | int num_connectors) |
4425 | { | |
4426 | struct drm_device *dev = crtc->dev; | |
4427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4429 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4430 | int pipe = intel_crtc->pipe; |
4431 | u32 dpll; | |
4432 | ||
2a8f64ca VP |
4433 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4434 | ||
eb1cbe48 DV |
4435 | dpll = DPLL_VGA_MODE_DIS; |
4436 | ||
4437 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4438 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4439 | } else { | |
4440 | if (clock->p1 == 2) | |
4441 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4442 | else | |
4443 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4444 | if (clock->p2 == 4) | |
4445 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4446 | } | |
4447 | ||
4448 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4449 | /* XXX: just matching BIOS for now */ | |
4450 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4451 | dpll |= 3; | |
4452 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4453 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4454 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4455 | else | |
4456 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4457 | ||
4458 | dpll |= DPLL_VCO_ENABLE; | |
4459 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4460 | POSTING_READ(DPLL(pipe)); | |
4461 | udelay(150); | |
4462 | ||
dafd226c DV |
4463 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4464 | if (encoder->pre_pll_enable) | |
4465 | encoder->pre_pll_enable(encoder); | |
4466 | ||
5b5896e4 DV |
4467 | I915_WRITE(DPLL(pipe), dpll); |
4468 | ||
4469 | /* Wait for the clocks to stabilize. */ | |
4470 | POSTING_READ(DPLL(pipe)); | |
4471 | udelay(150); | |
4472 | ||
eb1cbe48 DV |
4473 | /* The pixel multiplier can only be updated once the |
4474 | * DPLL is enabled and the clocks are stable. | |
4475 | * | |
4476 | * So write it again. | |
4477 | */ | |
4478 | I915_WRITE(DPLL(pipe), dpll); | |
4479 | } | |
4480 | ||
b0e77b9c PZ |
4481 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, |
4482 | struct drm_display_mode *mode, | |
4483 | struct drm_display_mode *adjusted_mode) | |
4484 | { | |
4485 | struct drm_device *dev = intel_crtc->base.dev; | |
4486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4487 | enum pipe pipe = intel_crtc->pipe; | |
fe2b8f9d | 4488 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
b0e77b9c PZ |
4489 | uint32_t vsyncshift; |
4490 | ||
4491 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4492 | /* the chip adds 2 halflines automatically */ | |
4493 | adjusted_mode->crtc_vtotal -= 1; | |
4494 | adjusted_mode->crtc_vblank_end -= 1; | |
4495 | vsyncshift = adjusted_mode->crtc_hsync_start | |
4496 | - adjusted_mode->crtc_htotal / 2; | |
4497 | } else { | |
4498 | vsyncshift = 0; | |
4499 | } | |
4500 | ||
4501 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4502 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4503 | |
fe2b8f9d | 4504 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4505 | (adjusted_mode->crtc_hdisplay - 1) | |
4506 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4507 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4508 | (adjusted_mode->crtc_hblank_start - 1) | |
4509 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4510 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4511 | (adjusted_mode->crtc_hsync_start - 1) | |
4512 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4513 | ||
fe2b8f9d | 4514 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4515 | (adjusted_mode->crtc_vdisplay - 1) | |
4516 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
fe2b8f9d | 4517 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c PZ |
4518 | (adjusted_mode->crtc_vblank_start - 1) | |
4519 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
fe2b8f9d | 4520 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4521 | (adjusted_mode->crtc_vsync_start - 1) | |
4522 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4523 | ||
b5e508d4 PZ |
4524 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4525 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4526 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4527 | * bits. */ | |
4528 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4529 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4530 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4531 | ||
b0e77b9c PZ |
4532 | /* pipesrc controls the size that is scaled from, which should |
4533 | * always be the user's requested size. | |
4534 | */ | |
4535 | I915_WRITE(PIPESRC(pipe), | |
4536 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4537 | } | |
4538 | ||
f564048e EA |
4539 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4540 | struct drm_display_mode *mode, | |
4541 | struct drm_display_mode *adjusted_mode, | |
4542 | int x, int y, | |
94352cf9 | 4543 | struct drm_framebuffer *fb) |
79e53945 JB |
4544 | { |
4545 | struct drm_device *dev = crtc->dev; | |
4546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4548 | int pipe = intel_crtc->pipe; | |
80824003 | 4549 | int plane = intel_crtc->plane; |
c751ce4f | 4550 | int refclk, num_connectors = 0; |
652c393a | 4551 | intel_clock_t clock, reduced_clock; |
b0e77b9c | 4552 | u32 dspcntr, pipeconf; |
eb1cbe48 DV |
4553 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4554 | bool is_lvds = false, is_tv = false, is_dp = false; | |
5eddb70b | 4555 | struct intel_encoder *encoder; |
d4906093 | 4556 | const intel_limit_t *limit; |
5c3b82e2 | 4557 | int ret; |
79e53945 | 4558 | |
6c2b7c12 | 4559 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4560 | switch (encoder->type) { |
79e53945 JB |
4561 | case INTEL_OUTPUT_LVDS: |
4562 | is_lvds = true; | |
4563 | break; | |
4564 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4565 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4566 | is_sdvo = true; |
5eddb70b | 4567 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4568 | is_tv = true; |
79e53945 | 4569 | break; |
79e53945 JB |
4570 | case INTEL_OUTPUT_TVOUT: |
4571 | is_tv = true; | |
4572 | break; | |
a4fc5ed6 KP |
4573 | case INTEL_OUTPUT_DISPLAYPORT: |
4574 | is_dp = true; | |
4575 | break; | |
79e53945 | 4576 | } |
43565a06 | 4577 | |
c751ce4f | 4578 | num_connectors++; |
79e53945 JB |
4579 | } |
4580 | ||
c65d77d8 | 4581 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4582 | |
d4906093 ML |
4583 | /* |
4584 | * Returns a set of divisors for the desired target clock with the given | |
4585 | * refclk, or FALSE. The returned values represent the clock equation: | |
4586 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4587 | */ | |
1b894b59 | 4588 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4589 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4590 | &clock); | |
79e53945 JB |
4591 | if (!ok) { |
4592 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4593 | return -EINVAL; |
79e53945 JB |
4594 | } |
4595 | ||
cda4b7d3 | 4596 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4597 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4598 | |
ddc9003c | 4599 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4600 | /* |
4601 | * Ensure we match the reduced clock's P to the target clock. | |
4602 | * If the clocks don't match, we can't switch the display clock | |
4603 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4604 | * downclock feature. | |
4605 | */ | |
ddc9003c | 4606 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4607 | dev_priv->lvds_downclock, |
4608 | refclk, | |
cec2f356 | 4609 | &clock, |
5eddb70b | 4610 | &reduced_clock); |
7026d4ac ZW |
4611 | } |
4612 | ||
c65d77d8 JB |
4613 | if (is_sdvo && is_tv) |
4614 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 4615 | |
eb1cbe48 | 4616 | if (IS_GEN2(dev)) |
2a8f64ca VP |
4617 | i8xx_update_pll(crtc, adjusted_mode, &clock, |
4618 | has_reduced_clock ? &reduced_clock : NULL, | |
4619 | num_connectors); | |
a0c4da24 | 4620 | else if (IS_VALLEYVIEW(dev)) |
2a8f64ca VP |
4621 | vlv_update_pll(crtc, mode, adjusted_mode, &clock, |
4622 | has_reduced_clock ? &reduced_clock : NULL, | |
4623 | num_connectors); | |
79e53945 | 4624 | else |
eb1cbe48 DV |
4625 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4626 | has_reduced_clock ? &reduced_clock : NULL, | |
4627 | num_connectors); | |
79e53945 JB |
4628 | |
4629 | /* setup pipeconf */ | |
5eddb70b | 4630 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4631 | |
4632 | /* Set up the display plane register */ | |
4633 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4634 | ||
929c77fb EA |
4635 | if (pipe == 0) |
4636 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4637 | else | |
4638 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4639 | |
a6c45cf0 | 4640 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4641 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4642 | * core speed. | |
4643 | * | |
4644 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4645 | * pipe == 0 check? | |
4646 | */ | |
e70236a8 JB |
4647 | if (mode->clock > |
4648 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4649 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4650 | else |
5eddb70b | 4651 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4652 | } |
4653 | ||
3b5c78a3 AJ |
4654 | /* default to 8bpc */ |
4655 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
4656 | if (is_dp) { | |
0c96c65b | 4657 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3b5c78a3 AJ |
4658 | pipeconf |= PIPECONF_BPP_6 | |
4659 | PIPECONF_DITHER_EN | | |
4660 | PIPECONF_DITHER_TYPE_SP; | |
4661 | } | |
4662 | } | |
4663 | ||
19c03924 GB |
4664 | if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4665 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
4666 | pipeconf |= PIPECONF_BPP_6 | | |
4667 | PIPECONF_ENABLE | | |
4668 | I965_PIPECONF_ACTIVE; | |
4669 | } | |
4670 | } | |
4671 | ||
28c97730 | 4672 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4673 | drm_mode_debug_printmodeline(mode); |
4674 | ||
a7516a05 JB |
4675 | if (HAS_PIPE_CXSR(dev)) { |
4676 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 4677 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 4678 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 4679 | } else { |
28c97730 | 4680 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4681 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4682 | } | |
4683 | } | |
4684 | ||
617cf884 | 4685 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 | 4686 | if (!IS_GEN2(dev) && |
b0e77b9c | 4687 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
734b4157 | 4688 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
b0e77b9c | 4689 | else |
617cf884 | 4690 | pipeconf |= PIPECONF_PROGRESSIVE; |
734b4157 | 4691 | |
b0e77b9c | 4692 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b CW |
4693 | |
4694 | /* pipesrc and dspsize control the size that is scaled from, | |
4695 | * which should always be the user's requested size. | |
79e53945 | 4696 | */ |
929c77fb EA |
4697 | I915_WRITE(DSPSIZE(plane), |
4698 | ((mode->vdisplay - 1) << 16) | | |
4699 | (mode->hdisplay - 1)); | |
4700 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4701 | |
f564048e EA |
4702 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4703 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 4704 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4705 | |
4706 | intel_wait_for_vblank(dev, pipe); | |
4707 | ||
f564048e EA |
4708 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4709 | POSTING_READ(DSPCNTR(plane)); | |
4710 | ||
94352cf9 | 4711 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4712 | |
4713 | intel_update_watermarks(dev); | |
4714 | ||
f564048e EA |
4715 | return ret; |
4716 | } | |
4717 | ||
9fb526db KP |
4718 | /* |
4719 | * Initialize reference clocks when the driver loads | |
4720 | */ | |
4721 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
4722 | { |
4723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4724 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4725 | struct intel_encoder *encoder; |
13d83a67 JB |
4726 | u32 temp; |
4727 | bool has_lvds = false; | |
199e5d79 KP |
4728 | bool has_cpu_edp = false; |
4729 | bool has_pch_edp = false; | |
4730 | bool has_panel = false; | |
99eb6a01 KP |
4731 | bool has_ck505 = false; |
4732 | bool can_ssc = false; | |
13d83a67 JB |
4733 | |
4734 | /* We need to take the global config into account */ | |
199e5d79 KP |
4735 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4736 | base.head) { | |
4737 | switch (encoder->type) { | |
4738 | case INTEL_OUTPUT_LVDS: | |
4739 | has_panel = true; | |
4740 | has_lvds = true; | |
4741 | break; | |
4742 | case INTEL_OUTPUT_EDP: | |
4743 | has_panel = true; | |
4744 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4745 | has_pch_edp = true; | |
4746 | else | |
4747 | has_cpu_edp = true; | |
4748 | break; | |
13d83a67 JB |
4749 | } |
4750 | } | |
4751 | ||
99eb6a01 KP |
4752 | if (HAS_PCH_IBX(dev)) { |
4753 | has_ck505 = dev_priv->display_clock_mode; | |
4754 | can_ssc = has_ck505; | |
4755 | } else { | |
4756 | has_ck505 = false; | |
4757 | can_ssc = true; | |
4758 | } | |
4759 | ||
4760 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4761 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4762 | has_ck505); | |
13d83a67 JB |
4763 | |
4764 | /* Ironlake: try to setup display ref clock before DPLL | |
4765 | * enabling. This is only under driver's control after | |
4766 | * PCH B stepping, previous chipset stepping should be | |
4767 | * ignoring this setting. | |
4768 | */ | |
4769 | temp = I915_READ(PCH_DREF_CONTROL); | |
4770 | /* Always enable nonspread source */ | |
4771 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 4772 | |
99eb6a01 KP |
4773 | if (has_ck505) |
4774 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
4775 | else | |
4776 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 4777 | |
199e5d79 KP |
4778 | if (has_panel) { |
4779 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4780 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4781 | |
199e5d79 | 4782 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4783 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4784 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 4785 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
4786 | } else |
4787 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
4788 | |
4789 | /* Get SSC going before enabling the outputs */ | |
4790 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4791 | POSTING_READ(PCH_DREF_CONTROL); | |
4792 | udelay(200); | |
4793 | ||
13d83a67 JB |
4794 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4795 | ||
4796 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4797 | if (has_cpu_edp) { |
99eb6a01 | 4798 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4799 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 4800 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4801 | } |
13d83a67 JB |
4802 | else |
4803 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
4804 | } else |
4805 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4806 | ||
4807 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4808 | POSTING_READ(PCH_DREF_CONTROL); | |
4809 | udelay(200); | |
4810 | } else { | |
4811 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4812 | ||
4813 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4814 | ||
4815 | /* Turn off CPU output */ | |
4816 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4817 | ||
4818 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4819 | POSTING_READ(PCH_DREF_CONTROL); | |
4820 | udelay(200); | |
4821 | ||
4822 | /* Turn off the SSC source */ | |
4823 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4824 | temp |= DREF_SSC_SOURCE_DISABLE; | |
4825 | ||
4826 | /* Turn off SSC1 */ | |
4827 | temp &= ~ DREF_SSC1_ENABLE; | |
4828 | ||
13d83a67 JB |
4829 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4830 | POSTING_READ(PCH_DREF_CONTROL); | |
4831 | udelay(200); | |
4832 | } | |
4833 | } | |
4834 | ||
d9d444cb JB |
4835 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
4836 | { | |
4837 | struct drm_device *dev = crtc->dev; | |
4838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4839 | struct intel_encoder *encoder; | |
d9d444cb JB |
4840 | struct intel_encoder *edp_encoder = NULL; |
4841 | int num_connectors = 0; | |
4842 | bool is_lvds = false; | |
4843 | ||
6c2b7c12 | 4844 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
4845 | switch (encoder->type) { |
4846 | case INTEL_OUTPUT_LVDS: | |
4847 | is_lvds = true; | |
4848 | break; | |
4849 | case INTEL_OUTPUT_EDP: | |
4850 | edp_encoder = encoder; | |
4851 | break; | |
4852 | } | |
4853 | num_connectors++; | |
4854 | } | |
4855 | ||
4856 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
4857 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4858 | dev_priv->lvds_ssc_freq); | |
4859 | return dev_priv->lvds_ssc_freq * 1000; | |
4860 | } | |
4861 | ||
4862 | return 120000; | |
4863 | } | |
4864 | ||
c8203565 | 4865 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
f564048e | 4866 | struct drm_display_mode *adjusted_mode, |
c8203565 | 4867 | bool dither) |
79e53945 | 4868 | { |
c8203565 | 4869 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
4870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4871 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
4872 | uint32_t val; |
4873 | ||
4874 | val = I915_READ(PIPECONF(pipe)); | |
4875 | ||
4876 | val &= ~PIPE_BPC_MASK; | |
4877 | switch (intel_crtc->bpp) { | |
4878 | case 18: | |
4879 | val |= PIPE_6BPC; | |
4880 | break; | |
4881 | case 24: | |
4882 | val |= PIPE_8BPC; | |
4883 | break; | |
4884 | case 30: | |
4885 | val |= PIPE_10BPC; | |
4886 | break; | |
4887 | case 36: | |
4888 | val |= PIPE_12BPC; | |
4889 | break; | |
4890 | default: | |
cc769b62 PZ |
4891 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
4892 | BUG(); | |
c8203565 PZ |
4893 | } |
4894 | ||
4895 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
4896 | if (dither) | |
4897 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
4898 | ||
4899 | val &= ~PIPECONF_INTERLACE_MASK; | |
4900 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
4901 | val |= PIPECONF_INTERLACED_ILK; | |
4902 | else | |
4903 | val |= PIPECONF_PROGRESSIVE; | |
4904 | ||
4905 | I915_WRITE(PIPECONF(pipe), val); | |
4906 | POSTING_READ(PIPECONF(pipe)); | |
4907 | } | |
4908 | ||
ee2b0b38 PZ |
4909 | static void haswell_set_pipeconf(struct drm_crtc *crtc, |
4910 | struct drm_display_mode *adjusted_mode, | |
4911 | bool dither) | |
4912 | { | |
4913 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
4914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
702e7a56 | 4915 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
ee2b0b38 PZ |
4916 | uint32_t val; |
4917 | ||
702e7a56 | 4918 | val = I915_READ(PIPECONF(cpu_transcoder)); |
ee2b0b38 PZ |
4919 | |
4920 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
4921 | if (dither) | |
4922 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
4923 | ||
4924 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | |
4925 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
4926 | val |= PIPECONF_INTERLACED_ILK; | |
4927 | else | |
4928 | val |= PIPECONF_PROGRESSIVE; | |
4929 | ||
702e7a56 PZ |
4930 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
4931 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
ee2b0b38 PZ |
4932 | } |
4933 | ||
6591c6e4 PZ |
4934 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
4935 | struct drm_display_mode *adjusted_mode, | |
4936 | intel_clock_t *clock, | |
4937 | bool *has_reduced_clock, | |
4938 | intel_clock_t *reduced_clock) | |
4939 | { | |
4940 | struct drm_device *dev = crtc->dev; | |
4941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4942 | struct intel_encoder *intel_encoder; | |
4943 | int refclk; | |
d4906093 | 4944 | const intel_limit_t *limit; |
6591c6e4 | 4945 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
79e53945 | 4946 | |
6591c6e4 PZ |
4947 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4948 | switch (intel_encoder->type) { | |
79e53945 JB |
4949 | case INTEL_OUTPUT_LVDS: |
4950 | is_lvds = true; | |
4951 | break; | |
4952 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4953 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4954 | is_sdvo = true; |
6591c6e4 | 4955 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 4956 | is_tv = true; |
79e53945 | 4957 | break; |
79e53945 JB |
4958 | case INTEL_OUTPUT_TVOUT: |
4959 | is_tv = true; | |
4960 | break; | |
79e53945 JB |
4961 | } |
4962 | } | |
4963 | ||
d9d444cb | 4964 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 4965 | |
d4906093 ML |
4966 | /* |
4967 | * Returns a set of divisors for the desired target clock with the given | |
4968 | * refclk, or FALSE. The returned values represent the clock equation: | |
4969 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4970 | */ | |
1b894b59 | 4971 | limit = intel_limit(crtc, refclk); |
6591c6e4 PZ |
4972 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4973 | clock); | |
4974 | if (!ret) | |
4975 | return false; | |
cda4b7d3 | 4976 | |
ddc9003c | 4977 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4978 | /* |
4979 | * Ensure we match the reduced clock's P to the target clock. | |
4980 | * If the clocks don't match, we can't switch the display clock | |
4981 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4982 | * downclock feature. | |
4983 | */ | |
6591c6e4 PZ |
4984 | *has_reduced_clock = limit->find_pll(limit, crtc, |
4985 | dev_priv->lvds_downclock, | |
4986 | refclk, | |
4987 | clock, | |
4988 | reduced_clock); | |
652c393a | 4989 | } |
61e9653f DV |
4990 | |
4991 | if (is_sdvo && is_tv) | |
6591c6e4 PZ |
4992 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
4993 | ||
4994 | return true; | |
4995 | } | |
4996 | ||
01a415fd DV |
4997 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
4998 | { | |
4999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5000 | uint32_t temp; | |
5001 | ||
5002 | temp = I915_READ(SOUTH_CHICKEN1); | |
5003 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5004 | return; | |
5005 | ||
5006 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5007 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5008 | ||
5009 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5010 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5011 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5012 | POSTING_READ(SOUTH_CHICKEN1); | |
5013 | } | |
5014 | ||
5015 | static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) | |
5016 | { | |
5017 | struct drm_device *dev = intel_crtc->base.dev; | |
5018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5019 | struct intel_crtc *pipe_B_crtc = | |
5020 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5021 | ||
5022 | DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", | |
5023 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5024 | if (intel_crtc->fdi_lanes > 4) { | |
5025 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", | |
5026 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5027 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5028 | intel_crtc->fdi_lanes = 4; | |
5029 | ||
5030 | return false; | |
5031 | } | |
5032 | ||
5033 | if (dev_priv->num_pipe == 2) | |
5034 | return true; | |
5035 | ||
5036 | switch (intel_crtc->pipe) { | |
5037 | case PIPE_A: | |
5038 | return true; | |
5039 | case PIPE_B: | |
5040 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5041 | intel_crtc->fdi_lanes > 2) { | |
5042 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5043 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5044 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5045 | intel_crtc->fdi_lanes = 2; | |
5046 | ||
5047 | return false; | |
5048 | } | |
5049 | ||
5050 | if (intel_crtc->fdi_lanes > 2) | |
5051 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
5052 | else | |
5053 | cpt_enable_fdi_bc_bifurcation(dev); | |
5054 | ||
5055 | return true; | |
5056 | case PIPE_C: | |
5057 | if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { | |
5058 | if (intel_crtc->fdi_lanes > 2) { | |
5059 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5060 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5061 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5062 | intel_crtc->fdi_lanes = 2; | |
5063 | ||
5064 | return false; | |
5065 | } | |
5066 | } else { | |
5067 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5068 | return false; | |
5069 | } | |
5070 | ||
5071 | cpt_enable_fdi_bc_bifurcation(dev); | |
5072 | ||
5073 | return true; | |
5074 | default: | |
5075 | BUG(); | |
5076 | } | |
5077 | } | |
5078 | ||
f48d8f23 PZ |
5079 | static void ironlake_set_m_n(struct drm_crtc *crtc, |
5080 | struct drm_display_mode *mode, | |
5081 | struct drm_display_mode *adjusted_mode) | |
79e53945 JB |
5082 | { |
5083 | struct drm_device *dev = crtc->dev; | |
5084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
afe2fcf5 | 5086 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
f48d8f23 | 5087 | struct intel_encoder *intel_encoder, *edp_encoder = NULL; |
e69d0bc1 | 5088 | struct intel_link_m_n m_n = {0}; |
f48d8f23 PZ |
5089 | int target_clock, pixel_multiplier, lane, link_bw; |
5090 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5091 | |
f48d8f23 PZ |
5092 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5093 | switch (intel_encoder->type) { | |
a4fc5ed6 KP |
5094 | case INTEL_OUTPUT_DISPLAYPORT: |
5095 | is_dp = true; | |
5096 | break; | |
32f9d658 | 5097 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5098 | is_dp = true; |
f48d8f23 | 5099 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5100 | is_cpu_edp = true; |
f48d8f23 | 5101 | edp_encoder = intel_encoder; |
32f9d658 | 5102 | break; |
79e53945 | 5103 | } |
79e53945 | 5104 | } |
61e9653f | 5105 | |
2c07245f | 5106 | /* FDI link */ |
8febb297 EA |
5107 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5108 | lane = 0; | |
5109 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5110 | according to current link config */ | |
e3aef172 | 5111 | if (is_cpu_edp) { |
e3aef172 | 5112 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 | 5113 | } else { |
8febb297 EA |
5114 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5115 | * each output octet as 10 bits. The actual frequency | |
5116 | * is stored as a divider into a 100MHz clock, and the | |
5117 | * mode pixel clock is stored in units of 1KHz. | |
5118 | * Hence the bw of each lane in terms of the mode signal | |
5119 | * is: | |
5120 | */ | |
5121 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5122 | } | |
58a27471 | 5123 | |
94bf2ced DV |
5124 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
5125 | if (edp_encoder) | |
5126 | target_clock = intel_edp_target_clock(edp_encoder, mode); | |
5127 | else if (is_dp) | |
5128 | target_clock = mode->clock; | |
5129 | else | |
5130 | target_clock = adjusted_mode->clock; | |
5131 | ||
8febb297 EA |
5132 | if (!lane) { |
5133 | /* | |
5134 | * Account for spread spectrum to avoid | |
5135 | * oversubscribing the link. Max center spread | |
5136 | * is 2.5%; use 5% for safety's sake. | |
5137 | */ | |
5a354204 | 5138 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5139 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5140 | } |
2c07245f | 5141 | |
8febb297 EA |
5142 | intel_crtc->fdi_lanes = lane; |
5143 | ||
5144 | if (pixel_multiplier > 1) | |
5145 | link_bw *= pixel_multiplier; | |
e69d0bc1 | 5146 | intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n); |
8febb297 | 5147 | |
afe2fcf5 PZ |
5148 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5149 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); | |
5150 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); | |
5151 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); | |
f48d8f23 PZ |
5152 | } |
5153 | ||
de13a2e3 PZ |
5154 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5155 | struct drm_display_mode *adjusted_mode, | |
5156 | intel_clock_t *clock, u32 fp) | |
79e53945 | 5157 | { |
de13a2e3 | 5158 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5159 | struct drm_device *dev = crtc->dev; |
5160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5161 | struct intel_encoder *intel_encoder; |
5162 | uint32_t dpll; | |
5163 | int factor, pixel_multiplier, num_connectors = 0; | |
5164 | bool is_lvds = false, is_sdvo = false, is_tv = false; | |
5165 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5166 | |
de13a2e3 PZ |
5167 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5168 | switch (intel_encoder->type) { | |
79e53945 JB |
5169 | case INTEL_OUTPUT_LVDS: |
5170 | is_lvds = true; | |
5171 | break; | |
5172 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5173 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5174 | is_sdvo = true; |
de13a2e3 | 5175 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5176 | is_tv = true; |
79e53945 | 5177 | break; |
79e53945 JB |
5178 | case INTEL_OUTPUT_TVOUT: |
5179 | is_tv = true; | |
5180 | break; | |
a4fc5ed6 KP |
5181 | case INTEL_OUTPUT_DISPLAYPORT: |
5182 | is_dp = true; | |
5183 | break; | |
32f9d658 | 5184 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5185 | is_dp = true; |
de13a2e3 | 5186 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5187 | is_cpu_edp = true; |
32f9d658 | 5188 | break; |
79e53945 | 5189 | } |
43565a06 | 5190 | |
c751ce4f | 5191 | num_connectors++; |
79e53945 | 5192 | } |
79e53945 | 5193 | |
c1858123 | 5194 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5195 | factor = 21; |
5196 | if (is_lvds) { | |
5197 | if ((intel_panel_use_ssc(dev_priv) && | |
5198 | dev_priv->lvds_ssc_freq == 100) || | |
1974cad0 | 5199 | intel_is_dual_link_lvds(dev)) |
8febb297 EA |
5200 | factor = 25; |
5201 | } else if (is_sdvo && is_tv) | |
5202 | factor = 20; | |
c1858123 | 5203 | |
de13a2e3 | 5204 | if (clock->m < factor * clock->n) |
8febb297 | 5205 | fp |= FP_CB_TUNE; |
2c07245f | 5206 | |
5eddb70b | 5207 | dpll = 0; |
2c07245f | 5208 | |
a07d6787 EA |
5209 | if (is_lvds) |
5210 | dpll |= DPLLB_MODE_LVDS; | |
5211 | else | |
5212 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5213 | if (is_sdvo) { | |
de13a2e3 | 5214 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
a07d6787 EA |
5215 | if (pixel_multiplier > 1) { |
5216 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5217 | } |
a07d6787 EA |
5218 | dpll |= DPLL_DVO_HIGH_SPEED; |
5219 | } | |
e3aef172 | 5220 | if (is_dp && !is_cpu_edp) |
a07d6787 | 5221 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5222 | |
a07d6787 | 5223 | /* compute bitmask from p1 value */ |
de13a2e3 | 5224 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5225 | /* also FPA1 */ |
de13a2e3 | 5226 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5227 | |
de13a2e3 | 5228 | switch (clock->p2) { |
a07d6787 EA |
5229 | case 5: |
5230 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5231 | break; | |
5232 | case 7: | |
5233 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5234 | break; | |
5235 | case 10: | |
5236 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5237 | break; | |
5238 | case 14: | |
5239 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5240 | break; | |
79e53945 JB |
5241 | } |
5242 | ||
43565a06 KH |
5243 | if (is_sdvo && is_tv) |
5244 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5245 | else if (is_tv) | |
79e53945 | 5246 | /* XXX: just matching BIOS for now */ |
43565a06 | 5247 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5248 | dpll |= 3; |
a7615030 | 5249 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5250 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5251 | else |
5252 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5253 | ||
de13a2e3 PZ |
5254 | return dpll; |
5255 | } | |
5256 | ||
5257 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
5258 | struct drm_display_mode *mode, | |
5259 | struct drm_display_mode *adjusted_mode, | |
5260 | int x, int y, | |
5261 | struct drm_framebuffer *fb) | |
5262 | { | |
5263 | struct drm_device *dev = crtc->dev; | |
5264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5266 | int pipe = intel_crtc->pipe; | |
5267 | int plane = intel_crtc->plane; | |
5268 | int num_connectors = 0; | |
5269 | intel_clock_t clock, reduced_clock; | |
5270 | u32 dpll, fp = 0, fp2 = 0; | |
e2f12b07 PZ |
5271 | bool ok, has_reduced_clock = false; |
5272 | bool is_lvds = false, is_dp = false, is_cpu_edp = false; | |
de13a2e3 | 5273 | struct intel_encoder *encoder; |
de13a2e3 | 5274 | int ret; |
01a415fd | 5275 | bool dither, fdi_config_ok; |
de13a2e3 PZ |
5276 | |
5277 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5278 | switch (encoder->type) { | |
5279 | case INTEL_OUTPUT_LVDS: | |
5280 | is_lvds = true; | |
5281 | break; | |
de13a2e3 PZ |
5282 | case INTEL_OUTPUT_DISPLAYPORT: |
5283 | is_dp = true; | |
5284 | break; | |
5285 | case INTEL_OUTPUT_EDP: | |
5286 | is_dp = true; | |
e2f12b07 | 5287 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
de13a2e3 PZ |
5288 | is_cpu_edp = true; |
5289 | break; | |
5290 | } | |
5291 | ||
5292 | num_connectors++; | |
a07d6787 | 5293 | } |
79e53945 | 5294 | |
5dc5298b PZ |
5295 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5296 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5297 | |
de13a2e3 PZ |
5298 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
5299 | &has_reduced_clock, &reduced_clock); | |
5300 | if (!ok) { | |
5301 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5302 | return -EINVAL; | |
79e53945 JB |
5303 | } |
5304 | ||
de13a2e3 PZ |
5305 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5306 | intel_crtc_update_cursor(crtc, true); | |
5307 | ||
5308 | /* determine panel color depth */ | |
c8241969 JN |
5309 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5310 | adjusted_mode); | |
de13a2e3 PZ |
5311 | if (is_lvds && dev_priv->lvds_dither) |
5312 | dither = true; | |
5313 | ||
5314 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
5315 | if (has_reduced_clock) | |
5316 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5317 | reduced_clock.m2; | |
5318 | ||
5319 | dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp); | |
79e53945 | 5320 | |
f7cb34d4 | 5321 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5322 | drm_mode_debug_printmodeline(mode); |
5323 | ||
5dc5298b PZ |
5324 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5325 | if (!is_cpu_edp) { | |
ee7b9f93 | 5326 | struct intel_pch_pll *pll; |
4b645f14 | 5327 | |
ee7b9f93 JB |
5328 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
5329 | if (pll == NULL) { | |
5330 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
5331 | pipe); | |
4b645f14 JB |
5332 | return -EINVAL; |
5333 | } | |
ee7b9f93 JB |
5334 | } else |
5335 | intel_put_pch_pll(intel_crtc); | |
79e53945 | 5336 | |
2f0c2ad1 | 5337 | if (is_dp && !is_cpu_edp) |
a4fc5ed6 | 5338 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
79e53945 | 5339 | |
dafd226c DV |
5340 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5341 | if (encoder->pre_pll_enable) | |
5342 | encoder->pre_pll_enable(encoder); | |
5343 | ||
ee7b9f93 JB |
5344 | if (intel_crtc->pch_pll) { |
5345 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 5346 | |
32f9d658 | 5347 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 5348 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
5349 | udelay(150); |
5350 | ||
8febb297 EA |
5351 | /* The pixel multiplier can only be updated once the |
5352 | * DPLL is enabled and the clocks are stable. | |
5353 | * | |
5354 | * So write it again. | |
5355 | */ | |
ee7b9f93 | 5356 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 5357 | } |
79e53945 | 5358 | |
5eddb70b | 5359 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 5360 | if (intel_crtc->pch_pll) { |
4b645f14 | 5361 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 5362 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 5363 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 5364 | } else { |
ee7b9f93 | 5365 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
5366 | } |
5367 | } | |
5368 | ||
b0e77b9c | 5369 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b | 5370 | |
01a415fd DV |
5371 | /* Note, this also computes intel_crtc->fdi_lanes which is used below in |
5372 | * ironlake_check_fdi_lanes. */ | |
f48d8f23 | 5373 | ironlake_set_m_n(crtc, mode, adjusted_mode); |
2c07245f | 5374 | |
01a415fd | 5375 | fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); |
2c07245f | 5376 | |
c8203565 | 5377 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
79e53945 | 5378 | |
9d0498a2 | 5379 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5380 | |
a1f9e77e PZ |
5381 | /* Set up the display plane register */ |
5382 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5383 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5384 | |
94352cf9 | 5385 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5386 | |
5387 | intel_update_watermarks(dev); | |
5388 | ||
1f8eeabf ED |
5389 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5390 | ||
01a415fd | 5391 | return fdi_config_ok ? ret : -EINVAL; |
79e53945 JB |
5392 | } |
5393 | ||
09b4ddf9 PZ |
5394 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
5395 | struct drm_display_mode *mode, | |
5396 | struct drm_display_mode *adjusted_mode, | |
5397 | int x, int y, | |
5398 | struct drm_framebuffer *fb) | |
5399 | { | |
5400 | struct drm_device *dev = crtc->dev; | |
5401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5403 | int pipe = intel_crtc->pipe; | |
5404 | int plane = intel_crtc->plane; | |
5405 | int num_connectors = 0; | |
ed7ef439 | 5406 | bool is_dp = false, is_cpu_edp = false; |
09b4ddf9 | 5407 | struct intel_encoder *encoder; |
09b4ddf9 PZ |
5408 | int ret; |
5409 | bool dither; | |
5410 | ||
5411 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5412 | switch (encoder->type) { | |
09b4ddf9 PZ |
5413 | case INTEL_OUTPUT_DISPLAYPORT: |
5414 | is_dp = true; | |
5415 | break; | |
5416 | case INTEL_OUTPUT_EDP: | |
5417 | is_dp = true; | |
5418 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
5419 | is_cpu_edp = true; | |
5420 | break; | |
5421 | } | |
5422 | ||
5423 | num_connectors++; | |
5424 | } | |
5425 | ||
a5c961d1 PZ |
5426 | if (is_cpu_edp) |
5427 | intel_crtc->cpu_transcoder = TRANSCODER_EDP; | |
5428 | else | |
5429 | intel_crtc->cpu_transcoder = pipe; | |
5430 | ||
5dc5298b PZ |
5431 | /* We are not sure yet this won't happen. */ |
5432 | WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", | |
5433 | INTEL_PCH_TYPE(dev)); | |
5434 | ||
5435 | WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", | |
5436 | num_connectors, pipe_name(pipe)); | |
5437 | ||
702e7a56 | 5438 | WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & |
1ce42920 PZ |
5439 | (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); |
5440 | ||
5441 | WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); | |
5442 | ||
6441ab5f PZ |
5443 | if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) |
5444 | return -EINVAL; | |
5445 | ||
09b4ddf9 PZ |
5446 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5447 | intel_crtc_update_cursor(crtc, true); | |
5448 | ||
5449 | /* determine panel color depth */ | |
c8241969 JN |
5450 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5451 | adjusted_mode); | |
09b4ddf9 | 5452 | |
09b4ddf9 PZ |
5453 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
5454 | drm_mode_debug_printmodeline(mode); | |
5455 | ||
ed7ef439 | 5456 | if (is_dp && !is_cpu_edp) |
09b4ddf9 | 5457 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
09b4ddf9 PZ |
5458 | |
5459 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 PZ |
5460 | |
5461 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); | |
5462 | ||
1eb8dfec PZ |
5463 | if (!is_dp || is_cpu_edp) |
5464 | ironlake_set_m_n(crtc, mode, adjusted_mode); | |
09b4ddf9 | 5465 | |
ee2b0b38 | 5466 | haswell_set_pipeconf(crtc, adjusted_mode, dither); |
09b4ddf9 | 5467 | |
09b4ddf9 PZ |
5468 | /* Set up the display plane register */ |
5469 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
5470 | POSTING_READ(DSPCNTR(plane)); | |
5471 | ||
5472 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
5473 | ||
5474 | intel_update_watermarks(dev); | |
5475 | ||
5476 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); | |
5477 | ||
1f803ee5 | 5478 | return ret; |
79e53945 JB |
5479 | } |
5480 | ||
f564048e EA |
5481 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5482 | struct drm_display_mode *mode, | |
5483 | struct drm_display_mode *adjusted_mode, | |
5484 | int x, int y, | |
94352cf9 | 5485 | struct drm_framebuffer *fb) |
f564048e EA |
5486 | { |
5487 | struct drm_device *dev = crtc->dev; | |
5488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 DV |
5489 | struct drm_encoder_helper_funcs *encoder_funcs; |
5490 | struct intel_encoder *encoder; | |
0b701d27 EA |
5491 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5492 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5493 | int ret; |
5494 | ||
0b701d27 | 5495 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5496 | |
f564048e | 5497 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
94352cf9 | 5498 | x, y, fb); |
79e53945 | 5499 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5500 | |
9256aa19 DV |
5501 | if (ret != 0) |
5502 | return ret; | |
5503 | ||
5504 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5505 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
5506 | encoder->base.base.id, | |
5507 | drm_get_encoder_name(&encoder->base), | |
5508 | mode->base.id, mode->name); | |
5509 | encoder_funcs = encoder->base.helper_private; | |
5510 | encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); | |
5511 | } | |
5512 | ||
5513 | return 0; | |
79e53945 JB |
5514 | } |
5515 | ||
3a9627f4 WF |
5516 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5517 | int reg_eldv, uint32_t bits_eldv, | |
5518 | int reg_elda, uint32_t bits_elda, | |
5519 | int reg_edid) | |
5520 | { | |
5521 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5522 | uint8_t *eld = connector->eld; | |
5523 | uint32_t i; | |
5524 | ||
5525 | i = I915_READ(reg_eldv); | |
5526 | i &= bits_eldv; | |
5527 | ||
5528 | if (!eld[0]) | |
5529 | return !i; | |
5530 | ||
5531 | if (!i) | |
5532 | return false; | |
5533 | ||
5534 | i = I915_READ(reg_elda); | |
5535 | i &= ~bits_elda; | |
5536 | I915_WRITE(reg_elda, i); | |
5537 | ||
5538 | for (i = 0; i < eld[2]; i++) | |
5539 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5540 | return false; | |
5541 | ||
5542 | return true; | |
5543 | } | |
5544 | ||
e0dac65e WF |
5545 | static void g4x_write_eld(struct drm_connector *connector, |
5546 | struct drm_crtc *crtc) | |
5547 | { | |
5548 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5549 | uint8_t *eld = connector->eld; | |
5550 | uint32_t eldv; | |
5551 | uint32_t len; | |
5552 | uint32_t i; | |
5553 | ||
5554 | i = I915_READ(G4X_AUD_VID_DID); | |
5555 | ||
5556 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5557 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5558 | else | |
5559 | eldv = G4X_ELDV_DEVCTG; | |
5560 | ||
3a9627f4 WF |
5561 | if (intel_eld_uptodate(connector, |
5562 | G4X_AUD_CNTL_ST, eldv, | |
5563 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5564 | G4X_HDMIW_HDMIEDID)) | |
5565 | return; | |
5566 | ||
e0dac65e WF |
5567 | i = I915_READ(G4X_AUD_CNTL_ST); |
5568 | i &= ~(eldv | G4X_ELD_ADDR); | |
5569 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5570 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5571 | ||
5572 | if (!eld[0]) | |
5573 | return; | |
5574 | ||
5575 | len = min_t(uint8_t, eld[2], len); | |
5576 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5577 | for (i = 0; i < len; i++) | |
5578 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5579 | ||
5580 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5581 | i |= eldv; | |
5582 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5583 | } | |
5584 | ||
83358c85 WX |
5585 | static void haswell_write_eld(struct drm_connector *connector, |
5586 | struct drm_crtc *crtc) | |
5587 | { | |
5588 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5589 | uint8_t *eld = connector->eld; | |
5590 | struct drm_device *dev = crtc->dev; | |
5591 | uint32_t eldv; | |
5592 | uint32_t i; | |
5593 | int len; | |
5594 | int pipe = to_intel_crtc(crtc)->pipe; | |
5595 | int tmp; | |
5596 | ||
5597 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
5598 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
5599 | int aud_config = HSW_AUD_CFG(pipe); | |
5600 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
5601 | ||
5602 | ||
5603 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
5604 | ||
5605 | /* Audio output enable */ | |
5606 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
5607 | tmp = I915_READ(aud_cntrl_st2); | |
5608 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
5609 | I915_WRITE(aud_cntrl_st2, tmp); | |
5610 | ||
5611 | /* Wait for 1 vertical blank */ | |
5612 | intel_wait_for_vblank(dev, pipe); | |
5613 | ||
5614 | /* Set ELD valid state */ | |
5615 | tmp = I915_READ(aud_cntrl_st2); | |
5616 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
5617 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
5618 | I915_WRITE(aud_cntrl_st2, tmp); | |
5619 | tmp = I915_READ(aud_cntrl_st2); | |
5620 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
5621 | ||
5622 | /* Enable HDMI mode */ | |
5623 | tmp = I915_READ(aud_config); | |
5624 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
5625 | /* clear N_programing_enable and N_value_index */ | |
5626 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
5627 | I915_WRITE(aud_config, tmp); | |
5628 | ||
5629 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
5630 | ||
5631 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
5632 | ||
5633 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5634 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5635 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5636 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
5637 | } else | |
5638 | I915_WRITE(aud_config, 0); | |
5639 | ||
5640 | if (intel_eld_uptodate(connector, | |
5641 | aud_cntrl_st2, eldv, | |
5642 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5643 | hdmiw_hdmiedid)) | |
5644 | return; | |
5645 | ||
5646 | i = I915_READ(aud_cntrl_st2); | |
5647 | i &= ~eldv; | |
5648 | I915_WRITE(aud_cntrl_st2, i); | |
5649 | ||
5650 | if (!eld[0]) | |
5651 | return; | |
5652 | ||
5653 | i = I915_READ(aud_cntl_st); | |
5654 | i &= ~IBX_ELD_ADDRESS; | |
5655 | I915_WRITE(aud_cntl_st, i); | |
5656 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
5657 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
5658 | ||
5659 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5660 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5661 | for (i = 0; i < len; i++) | |
5662 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5663 | ||
5664 | i = I915_READ(aud_cntrl_st2); | |
5665 | i |= eldv; | |
5666 | I915_WRITE(aud_cntrl_st2, i); | |
5667 | ||
5668 | } | |
5669 | ||
e0dac65e WF |
5670 | static void ironlake_write_eld(struct drm_connector *connector, |
5671 | struct drm_crtc *crtc) | |
5672 | { | |
5673 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5674 | uint8_t *eld = connector->eld; | |
5675 | uint32_t eldv; | |
5676 | uint32_t i; | |
5677 | int len; | |
5678 | int hdmiw_hdmiedid; | |
b6daa025 | 5679 | int aud_config; |
e0dac65e WF |
5680 | int aud_cntl_st; |
5681 | int aud_cntrl_st2; | |
9b138a83 | 5682 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 5683 | |
b3f33cbf | 5684 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
5685 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5686 | aud_config = IBX_AUD_CFG(pipe); | |
5687 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5688 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 5689 | } else { |
9b138a83 WX |
5690 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5691 | aud_config = CPT_AUD_CFG(pipe); | |
5692 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5693 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
5694 | } |
5695 | ||
9b138a83 | 5696 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
5697 | |
5698 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 5699 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
5700 | if (!i) { |
5701 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5702 | /* operate blindly on all ports */ | |
1202b4c6 WF |
5703 | eldv = IBX_ELD_VALIDB; |
5704 | eldv |= IBX_ELD_VALIDB << 4; | |
5705 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
5706 | } else { |
5707 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 5708 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
5709 | } |
5710 | ||
3a9627f4 WF |
5711 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5712 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5713 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
5714 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5715 | } else | |
5716 | I915_WRITE(aud_config, 0); | |
e0dac65e | 5717 | |
3a9627f4 WF |
5718 | if (intel_eld_uptodate(connector, |
5719 | aud_cntrl_st2, eldv, | |
5720 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5721 | hdmiw_hdmiedid)) | |
5722 | return; | |
5723 | ||
e0dac65e WF |
5724 | i = I915_READ(aud_cntrl_st2); |
5725 | i &= ~eldv; | |
5726 | I915_WRITE(aud_cntrl_st2, i); | |
5727 | ||
5728 | if (!eld[0]) | |
5729 | return; | |
5730 | ||
e0dac65e | 5731 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 5732 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
5733 | I915_WRITE(aud_cntl_st, i); |
5734 | ||
5735 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5736 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5737 | for (i = 0; i < len; i++) | |
5738 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5739 | ||
5740 | i = I915_READ(aud_cntrl_st2); | |
5741 | i |= eldv; | |
5742 | I915_WRITE(aud_cntrl_st2, i); | |
5743 | } | |
5744 | ||
5745 | void intel_write_eld(struct drm_encoder *encoder, | |
5746 | struct drm_display_mode *mode) | |
5747 | { | |
5748 | struct drm_crtc *crtc = encoder->crtc; | |
5749 | struct drm_connector *connector; | |
5750 | struct drm_device *dev = encoder->dev; | |
5751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5752 | ||
5753 | connector = drm_select_eld(encoder, mode); | |
5754 | if (!connector) | |
5755 | return; | |
5756 | ||
5757 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5758 | connector->base.id, | |
5759 | drm_get_connector_name(connector), | |
5760 | connector->encoder->base.id, | |
5761 | drm_get_encoder_name(connector->encoder)); | |
5762 | ||
5763 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5764 | ||
5765 | if (dev_priv->display.write_eld) | |
5766 | dev_priv->display.write_eld(connector, crtc); | |
5767 | } | |
5768 | ||
79e53945 JB |
5769 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5770 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5771 | { | |
5772 | struct drm_device *dev = crtc->dev; | |
5773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5775 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5776 | int i; |
5777 | ||
5778 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 5779 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
5780 | return; |
5781 | ||
f2b115e6 | 5782 | /* use legacy palette for Ironlake */ |
bad720ff | 5783 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5784 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5785 | |
79e53945 JB |
5786 | for (i = 0; i < 256; i++) { |
5787 | I915_WRITE(palreg + 4 * i, | |
5788 | (intel_crtc->lut_r[i] << 16) | | |
5789 | (intel_crtc->lut_g[i] << 8) | | |
5790 | intel_crtc->lut_b[i]); | |
5791 | } | |
5792 | } | |
5793 | ||
560b85bb CW |
5794 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5795 | { | |
5796 | struct drm_device *dev = crtc->dev; | |
5797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5799 | bool visible = base != 0; | |
5800 | u32 cntl; | |
5801 | ||
5802 | if (intel_crtc->cursor_visible == visible) | |
5803 | return; | |
5804 | ||
9db4a9c7 | 5805 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5806 | if (visible) { |
5807 | /* On these chipsets we can only modify the base whilst | |
5808 | * the cursor is disabled. | |
5809 | */ | |
9db4a9c7 | 5810 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5811 | |
5812 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5813 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5814 | cntl |= CURSOR_ENABLE | | |
5815 | CURSOR_GAMMA_ENABLE | | |
5816 | CURSOR_FORMAT_ARGB; | |
5817 | } else | |
5818 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5819 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5820 | |
5821 | intel_crtc->cursor_visible = visible; | |
5822 | } | |
5823 | ||
5824 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5825 | { | |
5826 | struct drm_device *dev = crtc->dev; | |
5827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5829 | int pipe = intel_crtc->pipe; | |
5830 | bool visible = base != 0; | |
5831 | ||
5832 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5833 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5834 | if (base) { |
5835 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5836 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5837 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5838 | } else { | |
5839 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5840 | cntl |= CURSOR_MODE_DISABLE; | |
5841 | } | |
9db4a9c7 | 5842 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5843 | |
5844 | intel_crtc->cursor_visible = visible; | |
5845 | } | |
5846 | /* and commit changes on next vblank */ | |
9db4a9c7 | 5847 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
5848 | } |
5849 | ||
65a21cd6 JB |
5850 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
5851 | { | |
5852 | struct drm_device *dev = crtc->dev; | |
5853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5855 | int pipe = intel_crtc->pipe; | |
5856 | bool visible = base != 0; | |
5857 | ||
5858 | if (intel_crtc->cursor_visible != visible) { | |
5859 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
5860 | if (base) { | |
5861 | cntl &= ~CURSOR_MODE; | |
5862 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5863 | } else { | |
5864 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5865 | cntl |= CURSOR_MODE_DISABLE; | |
5866 | } | |
5867 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
5868 | ||
5869 | intel_crtc->cursor_visible = visible; | |
5870 | } | |
5871 | /* and commit changes on next vblank */ | |
5872 | I915_WRITE(CURBASE_IVB(pipe), base); | |
5873 | } | |
5874 | ||
cda4b7d3 | 5875 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
5876 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5877 | bool on) | |
cda4b7d3 CW |
5878 | { |
5879 | struct drm_device *dev = crtc->dev; | |
5880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5882 | int pipe = intel_crtc->pipe; | |
5883 | int x = intel_crtc->cursor_x; | |
5884 | int y = intel_crtc->cursor_y; | |
560b85bb | 5885 | u32 base, pos; |
cda4b7d3 CW |
5886 | bool visible; |
5887 | ||
5888 | pos = 0; | |
5889 | ||
6b383a7f | 5890 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
5891 | base = intel_crtc->cursor_addr; |
5892 | if (x > (int) crtc->fb->width) | |
5893 | base = 0; | |
5894 | ||
5895 | if (y > (int) crtc->fb->height) | |
5896 | base = 0; | |
5897 | } else | |
5898 | base = 0; | |
5899 | ||
5900 | if (x < 0) { | |
5901 | if (x + intel_crtc->cursor_width < 0) | |
5902 | base = 0; | |
5903 | ||
5904 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
5905 | x = -x; | |
5906 | } | |
5907 | pos |= x << CURSOR_X_SHIFT; | |
5908 | ||
5909 | if (y < 0) { | |
5910 | if (y + intel_crtc->cursor_height < 0) | |
5911 | base = 0; | |
5912 | ||
5913 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
5914 | y = -y; | |
5915 | } | |
5916 | pos |= y << CURSOR_Y_SHIFT; | |
5917 | ||
5918 | visible = base != 0; | |
560b85bb | 5919 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
5920 | return; |
5921 | ||
0cd83aa9 | 5922 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
5923 | I915_WRITE(CURPOS_IVB(pipe), pos); |
5924 | ivb_update_cursor(crtc, base); | |
5925 | } else { | |
5926 | I915_WRITE(CURPOS(pipe), pos); | |
5927 | if (IS_845G(dev) || IS_I865G(dev)) | |
5928 | i845_update_cursor(crtc, base); | |
5929 | else | |
5930 | i9xx_update_cursor(crtc, base); | |
5931 | } | |
cda4b7d3 CW |
5932 | } |
5933 | ||
79e53945 | 5934 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 5935 | struct drm_file *file, |
79e53945 JB |
5936 | uint32_t handle, |
5937 | uint32_t width, uint32_t height) | |
5938 | { | |
5939 | struct drm_device *dev = crtc->dev; | |
5940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 5942 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 5943 | uint32_t addr; |
3f8bc370 | 5944 | int ret; |
79e53945 | 5945 | |
79e53945 JB |
5946 | /* if we want to turn off the cursor ignore width and height */ |
5947 | if (!handle) { | |
28c97730 | 5948 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 5949 | addr = 0; |
05394f39 | 5950 | obj = NULL; |
5004417d | 5951 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 5952 | goto finish; |
79e53945 JB |
5953 | } |
5954 | ||
5955 | /* Currently we only support 64x64 cursors */ | |
5956 | if (width != 64 || height != 64) { | |
5957 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
5958 | return -EINVAL; | |
5959 | } | |
5960 | ||
05394f39 | 5961 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 5962 | if (&obj->base == NULL) |
79e53945 JB |
5963 | return -ENOENT; |
5964 | ||
05394f39 | 5965 | if (obj->base.size < width * height * 4) { |
79e53945 | 5966 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
5967 | ret = -ENOMEM; |
5968 | goto fail; | |
79e53945 JB |
5969 | } |
5970 | ||
71acb5eb | 5971 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 5972 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 5973 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
5974 | if (obj->tiling_mode) { |
5975 | DRM_ERROR("cursor cannot be tiled\n"); | |
5976 | ret = -EINVAL; | |
5977 | goto fail_locked; | |
5978 | } | |
5979 | ||
2da3b9b9 | 5980 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
5981 | if (ret) { |
5982 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 5983 | goto fail_locked; |
e7b526bb CW |
5984 | } |
5985 | ||
d9e86c0e CW |
5986 | ret = i915_gem_object_put_fence(obj); |
5987 | if (ret) { | |
2da3b9b9 | 5988 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
5989 | goto fail_unpin; |
5990 | } | |
5991 | ||
05394f39 | 5992 | addr = obj->gtt_offset; |
71acb5eb | 5993 | } else { |
6eeefaf3 | 5994 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 5995 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
5996 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
5997 | align); | |
71acb5eb DA |
5998 | if (ret) { |
5999 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6000 | goto fail_locked; |
71acb5eb | 6001 | } |
05394f39 | 6002 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6003 | } |
6004 | ||
a6c45cf0 | 6005 | if (IS_GEN2(dev)) |
14b60391 JB |
6006 | I915_WRITE(CURSIZE, (height << 12) | width); |
6007 | ||
3f8bc370 | 6008 | finish: |
3f8bc370 | 6009 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6010 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6011 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6012 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6013 | } else | |
6014 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6015 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6016 | } |
80824003 | 6017 | |
7f9872e0 | 6018 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6019 | |
6020 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6021 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6022 | intel_crtc->cursor_width = width; |
6023 | intel_crtc->cursor_height = height; | |
6024 | ||
6b383a7f | 6025 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6026 | |
79e53945 | 6027 | return 0; |
e7b526bb | 6028 | fail_unpin: |
05394f39 | 6029 | i915_gem_object_unpin(obj); |
7f9872e0 | 6030 | fail_locked: |
34b8686e | 6031 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6032 | fail: |
05394f39 | 6033 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6034 | return ret; |
79e53945 JB |
6035 | } |
6036 | ||
6037 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6038 | { | |
79e53945 | 6039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6040 | |
cda4b7d3 CW |
6041 | intel_crtc->cursor_x = x; |
6042 | intel_crtc->cursor_y = y; | |
652c393a | 6043 | |
6b383a7f | 6044 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6045 | |
6046 | return 0; | |
6047 | } | |
6048 | ||
6049 | /** Sets the color ramps on behalf of RandR */ | |
6050 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6051 | u16 blue, int regno) | |
6052 | { | |
6053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6054 | ||
6055 | intel_crtc->lut_r[regno] = red >> 8; | |
6056 | intel_crtc->lut_g[regno] = green >> 8; | |
6057 | intel_crtc->lut_b[regno] = blue >> 8; | |
6058 | } | |
6059 | ||
b8c00ac5 DA |
6060 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6061 | u16 *blue, int regno) | |
6062 | { | |
6063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6064 | ||
6065 | *red = intel_crtc->lut_r[regno] << 8; | |
6066 | *green = intel_crtc->lut_g[regno] << 8; | |
6067 | *blue = intel_crtc->lut_b[regno] << 8; | |
6068 | } | |
6069 | ||
79e53945 | 6070 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6071 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6072 | { |
7203425a | 6073 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6075 | |
7203425a | 6076 | for (i = start; i < end; i++) { |
79e53945 JB |
6077 | intel_crtc->lut_r[i] = red[i] >> 8; |
6078 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6079 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6080 | } | |
6081 | ||
6082 | intel_crtc_load_lut(crtc); | |
6083 | } | |
6084 | ||
6085 | /** | |
6086 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6087 | * detection. | |
6088 | * | |
6089 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6090 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6091 | * |
c751ce4f | 6092 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6093 | * configured for it. In the future, it could choose to temporarily disable |
6094 | * some outputs to free up a pipe for its use. | |
6095 | * | |
6096 | * \return crtc, or NULL if no pipes are available. | |
6097 | */ | |
6098 | ||
6099 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6100 | static struct drm_display_mode load_detect_mode = { | |
6101 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6102 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6103 | }; | |
6104 | ||
d2dff872 CW |
6105 | static struct drm_framebuffer * |
6106 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6107 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6108 | struct drm_i915_gem_object *obj) |
6109 | { | |
6110 | struct intel_framebuffer *intel_fb; | |
6111 | int ret; | |
6112 | ||
6113 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6114 | if (!intel_fb) { | |
6115 | drm_gem_object_unreference_unlocked(&obj->base); | |
6116 | return ERR_PTR(-ENOMEM); | |
6117 | } | |
6118 | ||
6119 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6120 | if (ret) { | |
6121 | drm_gem_object_unreference_unlocked(&obj->base); | |
6122 | kfree(intel_fb); | |
6123 | return ERR_PTR(ret); | |
6124 | } | |
6125 | ||
6126 | return &intel_fb->base; | |
6127 | } | |
6128 | ||
6129 | static u32 | |
6130 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6131 | { | |
6132 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6133 | return ALIGN(pitch, 64); | |
6134 | } | |
6135 | ||
6136 | static u32 | |
6137 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6138 | { | |
6139 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6140 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6141 | } | |
6142 | ||
6143 | static struct drm_framebuffer * | |
6144 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6145 | struct drm_display_mode *mode, | |
6146 | int depth, int bpp) | |
6147 | { | |
6148 | struct drm_i915_gem_object *obj; | |
0fed39bd | 6149 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
6150 | |
6151 | obj = i915_gem_alloc_object(dev, | |
6152 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6153 | if (obj == NULL) | |
6154 | return ERR_PTR(-ENOMEM); | |
6155 | ||
6156 | mode_cmd.width = mode->hdisplay; | |
6157 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6158 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6159 | bpp); | |
5ca0c34a | 6160 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6161 | |
6162 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6163 | } | |
6164 | ||
6165 | static struct drm_framebuffer * | |
6166 | mode_fits_in_fbdev(struct drm_device *dev, | |
6167 | struct drm_display_mode *mode) | |
6168 | { | |
6169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6170 | struct drm_i915_gem_object *obj; | |
6171 | struct drm_framebuffer *fb; | |
6172 | ||
6173 | if (dev_priv->fbdev == NULL) | |
6174 | return NULL; | |
6175 | ||
6176 | obj = dev_priv->fbdev->ifb.obj; | |
6177 | if (obj == NULL) | |
6178 | return NULL; | |
6179 | ||
6180 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6181 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6182 | fb->bits_per_pixel)) | |
d2dff872 CW |
6183 | return NULL; |
6184 | ||
01f2c773 | 6185 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6186 | return NULL; |
6187 | ||
6188 | return fb; | |
6189 | } | |
6190 | ||
d2434ab7 | 6191 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 6192 | struct drm_display_mode *mode, |
8261b191 | 6193 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6194 | { |
6195 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
6196 | struct intel_encoder *intel_encoder = |
6197 | intel_attached_encoder(connector); | |
79e53945 | 6198 | struct drm_crtc *possible_crtc; |
4ef69c7a | 6199 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6200 | struct drm_crtc *crtc = NULL; |
6201 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 6202 | struct drm_framebuffer *fb; |
79e53945 JB |
6203 | int i = -1; |
6204 | ||
d2dff872 CW |
6205 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6206 | connector->base.id, drm_get_connector_name(connector), | |
6207 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6208 | ||
79e53945 JB |
6209 | /* |
6210 | * Algorithm gets a little messy: | |
7a5e4805 | 6211 | * |
79e53945 JB |
6212 | * - if the connector already has an assigned crtc, use it (but make |
6213 | * sure it's on first) | |
7a5e4805 | 6214 | * |
79e53945 JB |
6215 | * - try to find the first unused crtc that can drive this connector, |
6216 | * and use that if we find one | |
79e53945 JB |
6217 | */ |
6218 | ||
6219 | /* See if we already have a CRTC for this connector */ | |
6220 | if (encoder->crtc) { | |
6221 | crtc = encoder->crtc; | |
8261b191 | 6222 | |
24218aac | 6223 | old->dpms_mode = connector->dpms; |
8261b191 CW |
6224 | old->load_detect_temp = false; |
6225 | ||
6226 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
6227 | if (connector->dpms != DRM_MODE_DPMS_ON) |
6228 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 6229 | |
7173188d | 6230 | return true; |
79e53945 JB |
6231 | } |
6232 | ||
6233 | /* Find an unused one (if possible) */ | |
6234 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6235 | i++; | |
6236 | if (!(encoder->possible_crtcs & (1 << i))) | |
6237 | continue; | |
6238 | if (!possible_crtc->enabled) { | |
6239 | crtc = possible_crtc; | |
6240 | break; | |
6241 | } | |
79e53945 JB |
6242 | } |
6243 | ||
6244 | /* | |
6245 | * If we didn't find an unused CRTC, don't use any. | |
6246 | */ | |
6247 | if (!crtc) { | |
7173188d CW |
6248 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6249 | return false; | |
79e53945 JB |
6250 | } |
6251 | ||
fc303101 DV |
6252 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
6253 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
6254 | |
6255 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 6256 | old->dpms_mode = connector->dpms; |
8261b191 | 6257 | old->load_detect_temp = true; |
d2dff872 | 6258 | old->release_fb = NULL; |
79e53945 | 6259 | |
6492711d CW |
6260 | if (!mode) |
6261 | mode = &load_detect_mode; | |
79e53945 | 6262 | |
d2dff872 CW |
6263 | /* We need a framebuffer large enough to accommodate all accesses |
6264 | * that the plane may generate whilst we perform load detection. | |
6265 | * We can not rely on the fbcon either being present (we get called | |
6266 | * during its initialisation to detect all boot displays, or it may | |
6267 | * not even exist) or that it is large enough to satisfy the | |
6268 | * requested mode. | |
6269 | */ | |
94352cf9 DV |
6270 | fb = mode_fits_in_fbdev(dev, mode); |
6271 | if (fb == NULL) { | |
d2dff872 | 6272 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
6273 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
6274 | old->release_fb = fb; | |
d2dff872 CW |
6275 | } else |
6276 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 6277 | if (IS_ERR(fb)) { |
d2dff872 | 6278 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
0e8b3d3e | 6279 | return false; |
79e53945 | 6280 | } |
79e53945 | 6281 | |
94352cf9 | 6282 | if (!intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 6283 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6284 | if (old->release_fb) |
6285 | old->release_fb->funcs->destroy(old->release_fb); | |
0e8b3d3e | 6286 | return false; |
79e53945 | 6287 | } |
7173188d | 6288 | |
79e53945 | 6289 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6290 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 6291 | return true; |
79e53945 JB |
6292 | } |
6293 | ||
d2434ab7 | 6294 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 6295 | struct intel_load_detect_pipe *old) |
79e53945 | 6296 | { |
d2434ab7 DV |
6297 | struct intel_encoder *intel_encoder = |
6298 | intel_attached_encoder(connector); | |
4ef69c7a | 6299 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 | 6300 | |
d2dff872 CW |
6301 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6302 | connector->base.id, drm_get_connector_name(connector), | |
6303 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6304 | ||
8261b191 | 6305 | if (old->load_detect_temp) { |
fc303101 DV |
6306 | struct drm_crtc *crtc = encoder->crtc; |
6307 | ||
6308 | to_intel_connector(connector)->new_encoder = NULL; | |
6309 | intel_encoder->new_crtc = NULL; | |
6310 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 CW |
6311 | |
6312 | if (old->release_fb) | |
6313 | old->release_fb->funcs->destroy(old->release_fb); | |
6314 | ||
0622a53c | 6315 | return; |
79e53945 JB |
6316 | } |
6317 | ||
c751ce4f | 6318 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
6319 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
6320 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
6321 | } |
6322 | ||
6323 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6324 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6325 | { | |
6326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6328 | int pipe = intel_crtc->pipe; | |
548f245b | 6329 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6330 | u32 fp; |
6331 | intel_clock_t clock; | |
6332 | ||
6333 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6334 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6335 | else |
39adb7a5 | 6336 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6337 | |
6338 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6339 | if (IS_PINEVIEW(dev)) { |
6340 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6341 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6342 | } else { |
6343 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6344 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6345 | } | |
6346 | ||
a6c45cf0 | 6347 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6348 | if (IS_PINEVIEW(dev)) |
6349 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6350 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6351 | else |
6352 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6353 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6354 | ||
6355 | switch (dpll & DPLL_MODE_MASK) { | |
6356 | case DPLLB_MODE_DAC_SERIAL: | |
6357 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6358 | 5 : 10; | |
6359 | break; | |
6360 | case DPLLB_MODE_LVDS: | |
6361 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6362 | 7 : 14; | |
6363 | break; | |
6364 | default: | |
28c97730 | 6365 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6366 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6367 | return 0; | |
6368 | } | |
6369 | ||
6370 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6371 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6372 | } else { |
6373 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6374 | ||
6375 | if (is_lvds) { | |
6376 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6377 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6378 | clock.p2 = 14; | |
6379 | ||
6380 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6381 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6382 | /* XXX: might not be 66MHz */ | |
2177832f | 6383 | intel_clock(dev, 66000, &clock); |
79e53945 | 6384 | } else |
2177832f | 6385 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6386 | } else { |
6387 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6388 | clock.p1 = 2; | |
6389 | else { | |
6390 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6391 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6392 | } | |
6393 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6394 | clock.p2 = 4; | |
6395 | else | |
6396 | clock.p2 = 2; | |
6397 | ||
2177832f | 6398 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6399 | } |
6400 | } | |
6401 | ||
6402 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6403 | * i830PllIsValid() because it relies on the xf86_config connector | |
6404 | * configuration being accurate, which it isn't necessarily. | |
6405 | */ | |
6406 | ||
6407 | return clock.dot; | |
6408 | } | |
6409 | ||
6410 | /** Returns the currently programmed mode of the given pipe. */ | |
6411 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6412 | struct drm_crtc *crtc) | |
6413 | { | |
548f245b | 6414 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 6415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
fe2b8f9d | 6416 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
79e53945 | 6417 | struct drm_display_mode *mode; |
fe2b8f9d PZ |
6418 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
6419 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
6420 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
6421 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
6422 | |
6423 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6424 | if (!mode) | |
6425 | return NULL; | |
6426 | ||
6427 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6428 | mode->hdisplay = (htot & 0xffff) + 1; | |
6429 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6430 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6431 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6432 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6433 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6434 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6435 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6436 | ||
6437 | drm_mode_set_name(mode); | |
79e53945 JB |
6438 | |
6439 | return mode; | |
6440 | } | |
6441 | ||
3dec0095 | 6442 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6443 | { |
6444 | struct drm_device *dev = crtc->dev; | |
6445 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6447 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6448 | int dpll_reg = DPLL(pipe); |
6449 | int dpll; | |
652c393a | 6450 | |
bad720ff | 6451 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6452 | return; |
6453 | ||
6454 | if (!dev_priv->lvds_downclock_avail) | |
6455 | return; | |
6456 | ||
dbdc6479 | 6457 | dpll = I915_READ(dpll_reg); |
652c393a | 6458 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6459 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 6460 | |
8ac5a6d5 | 6461 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
6462 | |
6463 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6464 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6465 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6466 | |
652c393a JB |
6467 | dpll = I915_READ(dpll_reg); |
6468 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6469 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 6470 | } |
652c393a JB |
6471 | } |
6472 | ||
6473 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6474 | { | |
6475 | struct drm_device *dev = crtc->dev; | |
6476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 6478 | |
bad720ff | 6479 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6480 | return; |
6481 | ||
6482 | if (!dev_priv->lvds_downclock_avail) | |
6483 | return; | |
6484 | ||
6485 | /* | |
6486 | * Since this is called by a timer, we should never get here in | |
6487 | * the manual case. | |
6488 | */ | |
6489 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
6490 | int pipe = intel_crtc->pipe; |
6491 | int dpll_reg = DPLL(pipe); | |
6492 | int dpll; | |
f6e5b160 | 6493 | |
44d98a61 | 6494 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 6495 | |
8ac5a6d5 | 6496 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 6497 | |
dc257cf1 | 6498 | dpll = I915_READ(dpll_reg); |
652c393a JB |
6499 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6500 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6501 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6502 | dpll = I915_READ(dpll_reg); |
6503 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6504 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6505 | } |
6506 | ||
6507 | } | |
6508 | ||
f047e395 CW |
6509 | void intel_mark_busy(struct drm_device *dev) |
6510 | { | |
f047e395 CW |
6511 | i915_update_gfx_val(dev->dev_private); |
6512 | } | |
6513 | ||
6514 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 6515 | { |
f047e395 CW |
6516 | } |
6517 | ||
6518 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) | |
6519 | { | |
6520 | struct drm_device *dev = obj->base.dev; | |
652c393a | 6521 | struct drm_crtc *crtc; |
652c393a JB |
6522 | |
6523 | if (!i915_powersave) | |
6524 | return; | |
6525 | ||
652c393a | 6526 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
6527 | if (!crtc->fb) |
6528 | continue; | |
6529 | ||
f047e395 CW |
6530 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6531 | intel_increase_pllclock(crtc); | |
652c393a | 6532 | } |
652c393a JB |
6533 | } |
6534 | ||
f047e395 | 6535 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
652c393a | 6536 | { |
f047e395 CW |
6537 | struct drm_device *dev = obj->base.dev; |
6538 | struct drm_crtc *crtc; | |
652c393a | 6539 | |
f047e395 | 6540 | if (!i915_powersave) |
acb87dfb CW |
6541 | return; |
6542 | ||
652c393a JB |
6543 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6544 | if (!crtc->fb) | |
6545 | continue; | |
6546 | ||
f047e395 CW |
6547 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6548 | intel_decrease_pllclock(crtc); | |
652c393a JB |
6549 | } |
6550 | } | |
6551 | ||
79e53945 JB |
6552 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6553 | { | |
6554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6555 | struct drm_device *dev = crtc->dev; |
6556 | struct intel_unpin_work *work; | |
6557 | unsigned long flags; | |
6558 | ||
6559 | spin_lock_irqsave(&dev->event_lock, flags); | |
6560 | work = intel_crtc->unpin_work; | |
6561 | intel_crtc->unpin_work = NULL; | |
6562 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6563 | ||
6564 | if (work) { | |
6565 | cancel_work_sync(&work->work); | |
6566 | kfree(work); | |
6567 | } | |
79e53945 JB |
6568 | |
6569 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6570 | |
79e53945 JB |
6571 | kfree(intel_crtc); |
6572 | } | |
6573 | ||
6b95a207 KH |
6574 | static void intel_unpin_work_fn(struct work_struct *__work) |
6575 | { | |
6576 | struct intel_unpin_work *work = | |
6577 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 6578 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 6579 | |
b4a98e57 | 6580 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 6581 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6582 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6583 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6584 | |
b4a98e57 CW |
6585 | intel_update_fbc(dev); |
6586 | mutex_unlock(&dev->struct_mutex); | |
6587 | ||
6588 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
6589 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
6590 | ||
6b95a207 KH |
6591 | kfree(work); |
6592 | } | |
6593 | ||
1afe3e9d | 6594 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6595 | struct drm_crtc *crtc) |
6b95a207 KH |
6596 | { |
6597 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6599 | struct intel_unpin_work *work; | |
05394f39 | 6600 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6601 | unsigned long flags; |
6602 | ||
6603 | /* Ignore early vblank irqs */ | |
6604 | if (intel_crtc == NULL) | |
6605 | return; | |
6606 | ||
6607 | spin_lock_irqsave(&dev->event_lock, flags); | |
6608 | work = intel_crtc->unpin_work; | |
6609 | if (work == NULL || !work->pending) { | |
6610 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6611 | return; | |
6612 | } | |
6613 | ||
6614 | intel_crtc->unpin_work = NULL; | |
6b95a207 | 6615 | |
45a066eb RC |
6616 | if (work->event) |
6617 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 6618 | |
0af7e4df MK |
6619 | drm_vblank_put(dev, intel_crtc->pipe); |
6620 | ||
6b95a207 KH |
6621 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6622 | ||
05394f39 | 6623 | obj = work->old_fb_obj; |
d9e86c0e | 6624 | |
5bb61643 | 6625 | wake_up(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
6626 | |
6627 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
6628 | |
6629 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6630 | } |
6631 | ||
1afe3e9d JB |
6632 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6633 | { | |
6634 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6635 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6636 | ||
49b14a5c | 6637 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6638 | } |
6639 | ||
6640 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6641 | { | |
6642 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6643 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6644 | ||
49b14a5c | 6645 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6646 | } |
6647 | ||
6b95a207 KH |
6648 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6649 | { | |
6650 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6651 | struct intel_crtc *intel_crtc = | |
6652 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6653 | unsigned long flags; | |
6654 | ||
6655 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6656 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6657 | if ((++intel_crtc->unpin_work->pending) > 1) |
6658 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6659 | } else { |
6660 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6661 | } | |
6b95a207 KH |
6662 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6663 | } | |
6664 | ||
8c9f3aaf JB |
6665 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6666 | struct drm_crtc *crtc, | |
6667 | struct drm_framebuffer *fb, | |
6668 | struct drm_i915_gem_object *obj) | |
6669 | { | |
6670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6672 | u32 flip_mask; |
6d90c952 | 6673 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6674 | int ret; |
6675 | ||
6d90c952 | 6676 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6677 | if (ret) |
83d4092b | 6678 | goto err; |
8c9f3aaf | 6679 | |
6d90c952 | 6680 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6681 | if (ret) |
83d4092b | 6682 | goto err_unpin; |
8c9f3aaf JB |
6683 | |
6684 | /* Can't queue multiple flips, so wait for the previous | |
6685 | * one to finish before executing the next. | |
6686 | */ | |
6687 | if (intel_crtc->plane) | |
6688 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6689 | else | |
6690 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6691 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6692 | intel_ring_emit(ring, MI_NOOP); | |
6693 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
6694 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6695 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6696 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6697 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
6698 | intel_ring_advance(ring); | |
83d4092b CW |
6699 | return 0; |
6700 | ||
6701 | err_unpin: | |
6702 | intel_unpin_fb_obj(obj); | |
6703 | err: | |
8c9f3aaf JB |
6704 | return ret; |
6705 | } | |
6706 | ||
6707 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6708 | struct drm_crtc *crtc, | |
6709 | struct drm_framebuffer *fb, | |
6710 | struct drm_i915_gem_object *obj) | |
6711 | { | |
6712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6713 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6714 | u32 flip_mask; |
6d90c952 | 6715 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6716 | int ret; |
6717 | ||
6d90c952 | 6718 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6719 | if (ret) |
83d4092b | 6720 | goto err; |
8c9f3aaf | 6721 | |
6d90c952 | 6722 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6723 | if (ret) |
83d4092b | 6724 | goto err_unpin; |
8c9f3aaf JB |
6725 | |
6726 | if (intel_crtc->plane) | |
6727 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6728 | else | |
6729 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6730 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6731 | intel_ring_emit(ring, MI_NOOP); | |
6732 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
6733 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6734 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6735 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6736 | intel_ring_emit(ring, MI_NOOP); |
6737 | ||
6738 | intel_ring_advance(ring); | |
83d4092b CW |
6739 | return 0; |
6740 | ||
6741 | err_unpin: | |
6742 | intel_unpin_fb_obj(obj); | |
6743 | err: | |
8c9f3aaf JB |
6744 | return ret; |
6745 | } | |
6746 | ||
6747 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
6748 | struct drm_crtc *crtc, | |
6749 | struct drm_framebuffer *fb, | |
6750 | struct drm_i915_gem_object *obj) | |
6751 | { | |
6752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6754 | uint32_t pf, pipesrc; | |
6d90c952 | 6755 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6756 | int ret; |
6757 | ||
6d90c952 | 6758 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6759 | if (ret) |
83d4092b | 6760 | goto err; |
8c9f3aaf | 6761 | |
6d90c952 | 6762 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6763 | if (ret) |
83d4092b | 6764 | goto err_unpin; |
8c9f3aaf JB |
6765 | |
6766 | /* i965+ uses the linear or tiled offsets from the | |
6767 | * Display Registers (which do not change across a page-flip) | |
6768 | * so we need only reprogram the base address. | |
6769 | */ | |
6d90c952 DV |
6770 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6771 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6772 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
6773 | intel_ring_emit(ring, |
6774 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
6775 | obj->tiling_mode); | |
8c9f3aaf JB |
6776 | |
6777 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6778 | * untested on non-native modes, so ignore it for now. | |
6779 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6780 | */ | |
6781 | pf = 0; | |
6782 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 DV |
6783 | intel_ring_emit(ring, pf | pipesrc); |
6784 | intel_ring_advance(ring); | |
83d4092b CW |
6785 | return 0; |
6786 | ||
6787 | err_unpin: | |
6788 | intel_unpin_fb_obj(obj); | |
6789 | err: | |
8c9f3aaf JB |
6790 | return ret; |
6791 | } | |
6792 | ||
6793 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
6794 | struct drm_crtc *crtc, | |
6795 | struct drm_framebuffer *fb, | |
6796 | struct drm_i915_gem_object *obj) | |
6797 | { | |
6798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 6800 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6801 | uint32_t pf, pipesrc; |
6802 | int ret; | |
6803 | ||
6d90c952 | 6804 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6805 | if (ret) |
83d4092b | 6806 | goto err; |
8c9f3aaf | 6807 | |
6d90c952 | 6808 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6809 | if (ret) |
83d4092b | 6810 | goto err_unpin; |
8c9f3aaf | 6811 | |
6d90c952 DV |
6812 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6813 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6814 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 6815 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 6816 | |
dc257cf1 DV |
6817 | /* Contrary to the suggestions in the documentation, |
6818 | * "Enable Panel Fitter" does not seem to be required when page | |
6819 | * flipping with a non-native mode, and worse causes a normal | |
6820 | * modeset to fail. | |
6821 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
6822 | */ | |
6823 | pf = 0; | |
8c9f3aaf | 6824 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 DV |
6825 | intel_ring_emit(ring, pf | pipesrc); |
6826 | intel_ring_advance(ring); | |
83d4092b CW |
6827 | return 0; |
6828 | ||
6829 | err_unpin: | |
6830 | intel_unpin_fb_obj(obj); | |
6831 | err: | |
8c9f3aaf JB |
6832 | return ret; |
6833 | } | |
6834 | ||
7c9017e5 JB |
6835 | /* |
6836 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
6837 | * the render ring doesn't give us interrpts for page flip completion, which | |
6838 | * means clients will hang after the first flip is queued. Fortunately the | |
6839 | * blit ring generates interrupts properly, so use it instead. | |
6840 | */ | |
6841 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
6842 | struct drm_crtc *crtc, | |
6843 | struct drm_framebuffer *fb, | |
6844 | struct drm_i915_gem_object *obj) | |
6845 | { | |
6846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6848 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 6849 | uint32_t plane_bit = 0; |
7c9017e5 JB |
6850 | int ret; |
6851 | ||
6852 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
6853 | if (ret) | |
83d4092b | 6854 | goto err; |
7c9017e5 | 6855 | |
cb05d8de DV |
6856 | switch(intel_crtc->plane) { |
6857 | case PLANE_A: | |
6858 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
6859 | break; | |
6860 | case PLANE_B: | |
6861 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
6862 | break; | |
6863 | case PLANE_C: | |
6864 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
6865 | break; | |
6866 | default: | |
6867 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
6868 | ret = -ENODEV; | |
ab3951eb | 6869 | goto err_unpin; |
cb05d8de DV |
6870 | } |
6871 | ||
7c9017e5 JB |
6872 | ret = intel_ring_begin(ring, 4); |
6873 | if (ret) | |
83d4092b | 6874 | goto err_unpin; |
7c9017e5 | 6875 | |
cb05d8de | 6876 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 6877 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 6878 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 JB |
6879 | intel_ring_emit(ring, (MI_NOOP)); |
6880 | intel_ring_advance(ring); | |
83d4092b CW |
6881 | return 0; |
6882 | ||
6883 | err_unpin: | |
6884 | intel_unpin_fb_obj(obj); | |
6885 | err: | |
7c9017e5 JB |
6886 | return ret; |
6887 | } | |
6888 | ||
8c9f3aaf JB |
6889 | static int intel_default_queue_flip(struct drm_device *dev, |
6890 | struct drm_crtc *crtc, | |
6891 | struct drm_framebuffer *fb, | |
6892 | struct drm_i915_gem_object *obj) | |
6893 | { | |
6894 | return -ENODEV; | |
6895 | } | |
6896 | ||
6b95a207 KH |
6897 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
6898 | struct drm_framebuffer *fb, | |
6899 | struct drm_pending_vblank_event *event) | |
6900 | { | |
6901 | struct drm_device *dev = crtc->dev; | |
6902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6903 | struct intel_framebuffer *intel_fb; | |
05394f39 | 6904 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6906 | struct intel_unpin_work *work; | |
8c9f3aaf | 6907 | unsigned long flags; |
52e68630 | 6908 | int ret; |
6b95a207 | 6909 | |
e6a595d2 VS |
6910 | /* Can't change pixel format via MI display flips. */ |
6911 | if (fb->pixel_format != crtc->fb->pixel_format) | |
6912 | return -EINVAL; | |
6913 | ||
6914 | /* | |
6915 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
6916 | * Note that pitch changes could also affect these register. | |
6917 | */ | |
6918 | if (INTEL_INFO(dev)->gen > 3 && | |
6919 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
6920 | fb->pitches[0] != crtc->fb->pitches[0])) | |
6921 | return -EINVAL; | |
6922 | ||
6b95a207 KH |
6923 | work = kzalloc(sizeof *work, GFP_KERNEL); |
6924 | if (work == NULL) | |
6925 | return -ENOMEM; | |
6926 | ||
6b95a207 | 6927 | work->event = event; |
b4a98e57 | 6928 | work->crtc = crtc; |
6b95a207 | 6929 | intel_fb = to_intel_framebuffer(crtc->fb); |
b1b87f6b | 6930 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
6931 | INIT_WORK(&work->work, intel_unpin_work_fn); |
6932 | ||
7317c75e JB |
6933 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
6934 | if (ret) | |
6935 | goto free_work; | |
6936 | ||
6b95a207 KH |
6937 | /* We borrow the event spin lock for protecting unpin_work */ |
6938 | spin_lock_irqsave(&dev->event_lock, flags); | |
6939 | if (intel_crtc->unpin_work) { | |
6940 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6941 | kfree(work); | |
7317c75e | 6942 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
6943 | |
6944 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
6945 | return -EBUSY; |
6946 | } | |
6947 | intel_crtc->unpin_work = work; | |
6948 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6949 | ||
6950 | intel_fb = to_intel_framebuffer(fb); | |
6951 | obj = intel_fb->obj; | |
6952 | ||
b4a98e57 CW |
6953 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
6954 | flush_workqueue(dev_priv->wq); | |
6955 | ||
79158103 CW |
6956 | ret = i915_mutex_lock_interruptible(dev); |
6957 | if (ret) | |
6958 | goto cleanup; | |
6b95a207 | 6959 | |
75dfca80 | 6960 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
6961 | drm_gem_object_reference(&work->old_fb_obj->base); |
6962 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
6963 | |
6964 | crtc->fb = fb; | |
96b099fd | 6965 | |
e1f99ce6 | 6966 | work->pending_flip_obj = obj; |
e1f99ce6 | 6967 | |
4e5359cd SF |
6968 | work->enable_stall_check = true; |
6969 | ||
b4a98e57 | 6970 | atomic_inc(&intel_crtc->unpin_work_count); |
e1f99ce6 | 6971 | |
8c9f3aaf JB |
6972 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
6973 | if (ret) | |
6974 | goto cleanup_pending; | |
6b95a207 | 6975 | |
7782de3b | 6976 | intel_disable_fbc(dev); |
f047e395 | 6977 | intel_mark_fb_busy(obj); |
6b95a207 KH |
6978 | mutex_unlock(&dev->struct_mutex); |
6979 | ||
e5510fac JB |
6980 | trace_i915_flip_request(intel_crtc->plane, obj); |
6981 | ||
6b95a207 | 6982 | return 0; |
96b099fd | 6983 | |
8c9f3aaf | 6984 | cleanup_pending: |
b4a98e57 | 6985 | atomic_dec(&intel_crtc->unpin_work_count); |
05394f39 CW |
6986 | drm_gem_object_unreference(&work->old_fb_obj->base); |
6987 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
6988 | mutex_unlock(&dev->struct_mutex); |
6989 | ||
79158103 | 6990 | cleanup: |
96b099fd CW |
6991 | spin_lock_irqsave(&dev->event_lock, flags); |
6992 | intel_crtc->unpin_work = NULL; | |
6993 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6994 | ||
7317c75e JB |
6995 | drm_vblank_put(dev, intel_crtc->pipe); |
6996 | free_work: | |
96b099fd CW |
6997 | kfree(work); |
6998 | ||
6999 | return ret; | |
6b95a207 KH |
7000 | } |
7001 | ||
f6e5b160 | 7002 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
7003 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
7004 | .load_lut = intel_crtc_load_lut, | |
976f8a20 | 7005 | .disable = intel_crtc_noop, |
f6e5b160 CW |
7006 | }; |
7007 | ||
6ed0f796 | 7008 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
47f1c6c9 | 7009 | { |
6ed0f796 DV |
7010 | struct intel_encoder *other_encoder; |
7011 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
47f1c6c9 | 7012 | |
6ed0f796 DV |
7013 | if (WARN_ON(!crtc)) |
7014 | return false; | |
7015 | ||
7016 | list_for_each_entry(other_encoder, | |
7017 | &crtc->dev->mode_config.encoder_list, | |
7018 | base.head) { | |
7019 | ||
7020 | if (&other_encoder->new_crtc->base != crtc || | |
7021 | encoder == other_encoder) | |
7022 | continue; | |
7023 | else | |
7024 | return true; | |
f47166d2 CW |
7025 | } |
7026 | ||
6ed0f796 DV |
7027 | return false; |
7028 | } | |
47f1c6c9 | 7029 | |
50f56119 DV |
7030 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
7031 | struct drm_crtc *crtc) | |
7032 | { | |
7033 | struct drm_device *dev; | |
7034 | struct drm_crtc *tmp; | |
7035 | int crtc_mask = 1; | |
47f1c6c9 | 7036 | |
50f56119 | 7037 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 7038 | |
50f56119 | 7039 | dev = crtc->dev; |
47f1c6c9 | 7040 | |
50f56119 DV |
7041 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
7042 | if (tmp == crtc) | |
7043 | break; | |
7044 | crtc_mask <<= 1; | |
7045 | } | |
47f1c6c9 | 7046 | |
50f56119 DV |
7047 | if (encoder->possible_crtcs & crtc_mask) |
7048 | return true; | |
7049 | return false; | |
47f1c6c9 | 7050 | } |
79e53945 | 7051 | |
9a935856 DV |
7052 | /** |
7053 | * intel_modeset_update_staged_output_state | |
7054 | * | |
7055 | * Updates the staged output configuration state, e.g. after we've read out the | |
7056 | * current hw state. | |
7057 | */ | |
7058 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 7059 | { |
9a935856 DV |
7060 | struct intel_encoder *encoder; |
7061 | struct intel_connector *connector; | |
f6e5b160 | 7062 | |
9a935856 DV |
7063 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7064 | base.head) { | |
7065 | connector->new_encoder = | |
7066 | to_intel_encoder(connector->base.encoder); | |
7067 | } | |
f6e5b160 | 7068 | |
9a935856 DV |
7069 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7070 | base.head) { | |
7071 | encoder->new_crtc = | |
7072 | to_intel_crtc(encoder->base.crtc); | |
7073 | } | |
f6e5b160 CW |
7074 | } |
7075 | ||
9a935856 DV |
7076 | /** |
7077 | * intel_modeset_commit_output_state | |
7078 | * | |
7079 | * This function copies the stage display pipe configuration to the real one. | |
7080 | */ | |
7081 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
7082 | { | |
7083 | struct intel_encoder *encoder; | |
7084 | struct intel_connector *connector; | |
f6e5b160 | 7085 | |
9a935856 DV |
7086 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7087 | base.head) { | |
7088 | connector->base.encoder = &connector->new_encoder->base; | |
7089 | } | |
f6e5b160 | 7090 | |
9a935856 DV |
7091 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7092 | base.head) { | |
7093 | encoder->base.crtc = &encoder->new_crtc->base; | |
7094 | } | |
7095 | } | |
7096 | ||
7758a113 DV |
7097 | static struct drm_display_mode * |
7098 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, | |
7099 | struct drm_display_mode *mode) | |
ee7b9f93 | 7100 | { |
7758a113 DV |
7101 | struct drm_device *dev = crtc->dev; |
7102 | struct drm_display_mode *adjusted_mode; | |
7103 | struct drm_encoder_helper_funcs *encoder_funcs; | |
7104 | struct intel_encoder *encoder; | |
ee7b9f93 | 7105 | |
7758a113 DV |
7106 | adjusted_mode = drm_mode_duplicate(dev, mode); |
7107 | if (!adjusted_mode) | |
7108 | return ERR_PTR(-ENOMEM); | |
7109 | ||
7110 | /* Pass our mode to the connectors and the CRTC to give them a chance to | |
7111 | * adjust it according to limitations or connector properties, and also | |
7112 | * a chance to reject the mode entirely. | |
47f1c6c9 | 7113 | */ |
7758a113 DV |
7114 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7115 | base.head) { | |
47f1c6c9 | 7116 | |
7758a113 DV |
7117 | if (&encoder->new_crtc->base != crtc) |
7118 | continue; | |
7119 | encoder_funcs = encoder->base.helper_private; | |
7120 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, | |
7121 | adjusted_mode))) { | |
7122 | DRM_DEBUG_KMS("Encoder fixup failed\n"); | |
7123 | goto fail; | |
7124 | } | |
ee7b9f93 | 7125 | } |
47f1c6c9 | 7126 | |
7758a113 DV |
7127 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
7128 | DRM_DEBUG_KMS("CRTC fixup failed\n"); | |
7129 | goto fail; | |
ee7b9f93 | 7130 | } |
7758a113 | 7131 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
47f1c6c9 | 7132 | |
7758a113 DV |
7133 | return adjusted_mode; |
7134 | fail: | |
7135 | drm_mode_destroy(dev, adjusted_mode); | |
7136 | return ERR_PTR(-EINVAL); | |
ee7b9f93 | 7137 | } |
47f1c6c9 | 7138 | |
e2e1ed41 DV |
7139 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
7140 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
7141 | static void | |
7142 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
7143 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
7144 | { |
7145 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
7146 | struct drm_device *dev = crtc->dev; |
7147 | struct intel_encoder *encoder; | |
7148 | struct intel_connector *connector; | |
7149 | struct drm_crtc *tmp_crtc; | |
79e53945 | 7150 | |
e2e1ed41 | 7151 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 7152 | |
e2e1ed41 DV |
7153 | /* Check which crtcs have changed outputs connected to them, these need |
7154 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
7155 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
7156 | * bit set at most. */ | |
7157 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7158 | base.head) { | |
7159 | if (connector->base.encoder == &connector->new_encoder->base) | |
7160 | continue; | |
79e53945 | 7161 | |
e2e1ed41 DV |
7162 | if (connector->base.encoder) { |
7163 | tmp_crtc = connector->base.encoder->crtc; | |
7164 | ||
7165 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7166 | } | |
7167 | ||
7168 | if (connector->new_encoder) | |
7169 | *prepare_pipes |= | |
7170 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
7171 | } |
7172 | ||
e2e1ed41 DV |
7173 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7174 | base.head) { | |
7175 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
7176 | continue; | |
7177 | ||
7178 | if (encoder->base.crtc) { | |
7179 | tmp_crtc = encoder->base.crtc; | |
7180 | ||
7181 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7182 | } | |
7183 | ||
7184 | if (encoder->new_crtc) | |
7185 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
7186 | } |
7187 | ||
e2e1ed41 DV |
7188 | /* Check for any pipes that will be fully disabled ... */ |
7189 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7190 | base.head) { | |
7191 | bool used = false; | |
22fd0fab | 7192 | |
e2e1ed41 DV |
7193 | /* Don't try to disable disabled crtcs. */ |
7194 | if (!intel_crtc->base.enabled) | |
7195 | continue; | |
7e7d76c3 | 7196 | |
e2e1ed41 DV |
7197 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7198 | base.head) { | |
7199 | if (encoder->new_crtc == intel_crtc) | |
7200 | used = true; | |
7201 | } | |
7202 | ||
7203 | if (!used) | |
7204 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
7205 | } |
7206 | ||
e2e1ed41 DV |
7207 | |
7208 | /* set_mode is also used to update properties on life display pipes. */ | |
7209 | intel_crtc = to_intel_crtc(crtc); | |
7210 | if (crtc->enabled) | |
7211 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7212 | ||
7213 | /* We only support modeset on one single crtc, hence we need to do that | |
7214 | * only for the passed in crtc iff we change anything else than just | |
7215 | * disable crtcs. | |
7216 | * | |
7217 | * This is actually not true, to be fully compatible with the old crtc | |
7218 | * helper we automatically disable _any_ output (i.e. doesn't need to be | |
7219 | * connected to the crtc we're modesetting on) if it's disconnected. | |
7220 | * Which is a rather nutty api (since changed the output configuration | |
7221 | * without userspace's explicit request can lead to confusion), but | |
7222 | * alas. Hence we currently need to modeset on all pipes we prepare. */ | |
7223 | if (*prepare_pipes) | |
7224 | *modeset_pipes = *prepare_pipes; | |
7225 | ||
7226 | /* ... and mask these out. */ | |
7227 | *modeset_pipes &= ~(*disable_pipes); | |
7228 | *prepare_pipes &= ~(*disable_pipes); | |
47f1c6c9 | 7229 | } |
79e53945 | 7230 | |
ea9d758d | 7231 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 7232 | { |
ea9d758d | 7233 | struct drm_encoder *encoder; |
f6e5b160 | 7234 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 7235 | |
ea9d758d DV |
7236 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
7237 | if (encoder->crtc == crtc) | |
7238 | return true; | |
7239 | ||
7240 | return false; | |
7241 | } | |
7242 | ||
7243 | static void | |
7244 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
7245 | { | |
7246 | struct intel_encoder *intel_encoder; | |
7247 | struct intel_crtc *intel_crtc; | |
7248 | struct drm_connector *connector; | |
7249 | ||
7250 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
7251 | base.head) { | |
7252 | if (!intel_encoder->base.crtc) | |
7253 | continue; | |
7254 | ||
7255 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
7256 | ||
7257 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
7258 | intel_encoder->connectors_active = false; | |
7259 | } | |
7260 | ||
7261 | intel_modeset_commit_output_state(dev); | |
7262 | ||
7263 | /* Update computed state. */ | |
7264 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7265 | base.head) { | |
7266 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
7267 | } | |
7268 | ||
7269 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
7270 | if (!connector->encoder || !connector->encoder->crtc) | |
7271 | continue; | |
7272 | ||
7273 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
7274 | ||
7275 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
7276 | struct drm_property *dpms_property = |
7277 | dev->mode_config.dpms_property; | |
7278 | ||
ea9d758d | 7279 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 7280 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
7281 | dpms_property, |
7282 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
7283 | |
7284 | intel_encoder = to_intel_encoder(connector->encoder); | |
7285 | intel_encoder->connectors_active = true; | |
7286 | } | |
7287 | } | |
7288 | ||
7289 | } | |
7290 | ||
25c5b266 DV |
7291 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
7292 | list_for_each_entry((intel_crtc), \ | |
7293 | &(dev)->mode_config.crtc_list, \ | |
7294 | base.head) \ | |
7295 | if (mask & (1 <<(intel_crtc)->pipe)) \ | |
7296 | ||
b980514c | 7297 | void |
8af6cf88 DV |
7298 | intel_modeset_check_state(struct drm_device *dev) |
7299 | { | |
7300 | struct intel_crtc *crtc; | |
7301 | struct intel_encoder *encoder; | |
7302 | struct intel_connector *connector; | |
7303 | ||
7304 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7305 | base.head) { | |
7306 | /* This also checks the encoder/connector hw state with the | |
7307 | * ->get_hw_state callbacks. */ | |
7308 | intel_connector_check_state(connector); | |
7309 | ||
7310 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
7311 | "connector's staged encoder doesn't match current encoder\n"); | |
7312 | } | |
7313 | ||
7314 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7315 | base.head) { | |
7316 | bool enabled = false; | |
7317 | bool active = false; | |
7318 | enum pipe pipe, tracked_pipe; | |
7319 | ||
7320 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
7321 | encoder->base.base.id, | |
7322 | drm_get_encoder_name(&encoder->base)); | |
7323 | ||
7324 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
7325 | "encoder's stage crtc doesn't match current crtc\n"); | |
7326 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
7327 | "encoder's active_connectors set, but no crtc\n"); | |
7328 | ||
7329 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7330 | base.head) { | |
7331 | if (connector->base.encoder != &encoder->base) | |
7332 | continue; | |
7333 | enabled = true; | |
7334 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
7335 | active = true; | |
7336 | } | |
7337 | WARN(!!encoder->base.crtc != enabled, | |
7338 | "encoder's enabled state mismatch " | |
7339 | "(expected %i, found %i)\n", | |
7340 | !!encoder->base.crtc, enabled); | |
7341 | WARN(active && !encoder->base.crtc, | |
7342 | "active encoder with no crtc\n"); | |
7343 | ||
7344 | WARN(encoder->connectors_active != active, | |
7345 | "encoder's computed active state doesn't match tracked active state " | |
7346 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
7347 | ||
7348 | active = encoder->get_hw_state(encoder, &pipe); | |
7349 | WARN(active != encoder->connectors_active, | |
7350 | "encoder's hw state doesn't match sw tracking " | |
7351 | "(expected %i, found %i)\n", | |
7352 | encoder->connectors_active, active); | |
7353 | ||
7354 | if (!encoder->base.crtc) | |
7355 | continue; | |
7356 | ||
7357 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
7358 | WARN(active && pipe != tracked_pipe, | |
7359 | "active encoder's pipe doesn't match" | |
7360 | "(expected %i, found %i)\n", | |
7361 | tracked_pipe, pipe); | |
7362 | ||
7363 | } | |
7364 | ||
7365 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
7366 | base.head) { | |
7367 | bool enabled = false; | |
7368 | bool active = false; | |
7369 | ||
7370 | DRM_DEBUG_KMS("[CRTC:%d]\n", | |
7371 | crtc->base.base.id); | |
7372 | ||
7373 | WARN(crtc->active && !crtc->base.enabled, | |
7374 | "active crtc, but not enabled in sw tracking\n"); | |
7375 | ||
7376 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7377 | base.head) { | |
7378 | if (encoder->base.crtc != &crtc->base) | |
7379 | continue; | |
7380 | enabled = true; | |
7381 | if (encoder->connectors_active) | |
7382 | active = true; | |
7383 | } | |
7384 | WARN(active != crtc->active, | |
7385 | "crtc's computed active state doesn't match tracked active state " | |
7386 | "(expected %i, found %i)\n", active, crtc->active); | |
7387 | WARN(enabled != crtc->base.enabled, | |
7388 | "crtc's computed enabled state doesn't match tracked enabled state " | |
7389 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
7390 | ||
7391 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); | |
7392 | } | |
7393 | } | |
7394 | ||
a6778b3c DV |
7395 | bool intel_set_mode(struct drm_crtc *crtc, |
7396 | struct drm_display_mode *mode, | |
94352cf9 | 7397 | int x, int y, struct drm_framebuffer *fb) |
a6778b3c DV |
7398 | { |
7399 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 7400 | drm_i915_private_t *dev_priv = dev->dev_private; |
a6778b3c | 7401 | struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode; |
25c5b266 DV |
7402 | struct intel_crtc *intel_crtc; |
7403 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
a6778b3c DV |
7404 | bool ret = true; |
7405 | ||
e2e1ed41 | 7406 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
7407 | &prepare_pipes, &disable_pipes); |
7408 | ||
7409 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
7410 | modeset_pipes, prepare_pipes, disable_pipes); | |
e2e1ed41 | 7411 | |
976f8a20 DV |
7412 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
7413 | intel_crtc_disable(&intel_crtc->base); | |
87f1faa6 | 7414 | |
a6778b3c DV |
7415 | saved_hwmode = crtc->hwmode; |
7416 | saved_mode = crtc->mode; | |
a6778b3c | 7417 | |
25c5b266 DV |
7418 | /* Hack: Because we don't (yet) support global modeset on multiple |
7419 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
7420 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
7421 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
7422 | * changing their mode at the same time. */ | |
7423 | adjusted_mode = NULL; | |
7424 | if (modeset_pipes) { | |
7425 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); | |
7426 | if (IS_ERR(adjusted_mode)) { | |
7427 | return false; | |
7428 | } | |
25c5b266 | 7429 | } |
a6778b3c | 7430 | |
ea9d758d DV |
7431 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7432 | if (intel_crtc->base.enabled) | |
7433 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
7434 | } | |
a6778b3c | 7435 | |
6c4c86f5 DV |
7436 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7437 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 7438 | */ |
6c4c86f5 | 7439 | if (modeset_pipes) |
25c5b266 | 7440 | crtc->mode = *mode; |
7758a113 | 7441 | |
ea9d758d DV |
7442 | /* Only after disabling all output pipelines that will be changed can we |
7443 | * update the the output configuration. */ | |
7444 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 7445 | |
47fab737 DV |
7446 | if (dev_priv->display.modeset_global_resources) |
7447 | dev_priv->display.modeset_global_resources(dev); | |
7448 | ||
a6778b3c DV |
7449 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7450 | * on the DPLL. | |
f6e5b160 | 7451 | */ |
25c5b266 DV |
7452 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
7453 | ret = !intel_crtc_mode_set(&intel_crtc->base, | |
7454 | mode, adjusted_mode, | |
7455 | x, y, fb); | |
7456 | if (!ret) | |
7457 | goto done; | |
a6778b3c DV |
7458 | } |
7459 | ||
7460 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
7461 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7462 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 7463 | |
25c5b266 DV |
7464 | if (modeset_pipes) { |
7465 | /* Store real post-adjustment hardware mode. */ | |
7466 | crtc->hwmode = *adjusted_mode; | |
a6778b3c | 7467 | |
25c5b266 DV |
7468 | /* Calculate and store various constants which |
7469 | * are later needed by vblank and swap-completion | |
7470 | * timestamping. They are derived from true hwmode. | |
7471 | */ | |
7472 | drm_calc_timestamping_constants(crtc); | |
7473 | } | |
a6778b3c DV |
7474 | |
7475 | /* FIXME: add subpixel order */ | |
7476 | done: | |
7477 | drm_mode_destroy(dev, adjusted_mode); | |
25c5b266 | 7478 | if (!ret && crtc->enabled) { |
a6778b3c DV |
7479 | crtc->hwmode = saved_hwmode; |
7480 | crtc->mode = saved_mode; | |
8af6cf88 DV |
7481 | } else { |
7482 | intel_modeset_check_state(dev); | |
a6778b3c DV |
7483 | } |
7484 | ||
7485 | return ret; | |
f6e5b160 CW |
7486 | } |
7487 | ||
25c5b266 DV |
7488 | #undef for_each_intel_crtc_masked |
7489 | ||
d9e55608 DV |
7490 | static void intel_set_config_free(struct intel_set_config *config) |
7491 | { | |
7492 | if (!config) | |
7493 | return; | |
7494 | ||
1aa4b628 DV |
7495 | kfree(config->save_connector_encoders); |
7496 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
7497 | kfree(config); |
7498 | } | |
7499 | ||
85f9eb71 DV |
7500 | static int intel_set_config_save_state(struct drm_device *dev, |
7501 | struct intel_set_config *config) | |
7502 | { | |
85f9eb71 DV |
7503 | struct drm_encoder *encoder; |
7504 | struct drm_connector *connector; | |
7505 | int count; | |
7506 | ||
1aa4b628 DV |
7507 | config->save_encoder_crtcs = |
7508 | kcalloc(dev->mode_config.num_encoder, | |
7509 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
7510 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
7511 | return -ENOMEM; |
7512 | ||
1aa4b628 DV |
7513 | config->save_connector_encoders = |
7514 | kcalloc(dev->mode_config.num_connector, | |
7515 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
7516 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
7517 | return -ENOMEM; |
7518 | ||
7519 | /* Copy data. Note that driver private data is not affected. | |
7520 | * Should anything bad happen only the expected state is | |
7521 | * restored, not the drivers personal bookkeeping. | |
7522 | */ | |
85f9eb71 DV |
7523 | count = 0; |
7524 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 7525 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
7526 | } |
7527 | ||
7528 | count = 0; | |
7529 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 7530 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
7531 | } |
7532 | ||
7533 | return 0; | |
7534 | } | |
7535 | ||
7536 | static void intel_set_config_restore_state(struct drm_device *dev, | |
7537 | struct intel_set_config *config) | |
7538 | { | |
9a935856 DV |
7539 | struct intel_encoder *encoder; |
7540 | struct intel_connector *connector; | |
85f9eb71 DV |
7541 | int count; |
7542 | ||
85f9eb71 | 7543 | count = 0; |
9a935856 DV |
7544 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7545 | encoder->new_crtc = | |
7546 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
7547 | } |
7548 | ||
7549 | count = 0; | |
9a935856 DV |
7550 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7551 | connector->new_encoder = | |
7552 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
7553 | } |
7554 | } | |
7555 | ||
5e2b584e DV |
7556 | static void |
7557 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
7558 | struct intel_set_config *config) | |
7559 | { | |
7560 | ||
7561 | /* We should be able to check here if the fb has the same properties | |
7562 | * and then just flip_or_move it */ | |
7563 | if (set->crtc->fb != set->fb) { | |
7564 | /* If we have no fb then treat it as a full mode set */ | |
7565 | if (set->crtc->fb == NULL) { | |
7566 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
7567 | config->mode_changed = true; | |
7568 | } else if (set->fb == NULL) { | |
7569 | config->mode_changed = true; | |
7570 | } else if (set->fb->depth != set->crtc->fb->depth) { | |
7571 | config->mode_changed = true; | |
7572 | } else if (set->fb->bits_per_pixel != | |
7573 | set->crtc->fb->bits_per_pixel) { | |
7574 | config->mode_changed = true; | |
7575 | } else | |
7576 | config->fb_changed = true; | |
7577 | } | |
7578 | ||
835c5873 | 7579 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
7580 | config->fb_changed = true; |
7581 | ||
7582 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
7583 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
7584 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
7585 | drm_mode_debug_printmodeline(set->mode); | |
7586 | config->mode_changed = true; | |
7587 | } | |
7588 | } | |
7589 | ||
2e431051 | 7590 | static int |
9a935856 DV |
7591 | intel_modeset_stage_output_state(struct drm_device *dev, |
7592 | struct drm_mode_set *set, | |
7593 | struct intel_set_config *config) | |
50f56119 | 7594 | { |
85f9eb71 | 7595 | struct drm_crtc *new_crtc; |
9a935856 DV |
7596 | struct intel_connector *connector; |
7597 | struct intel_encoder *encoder; | |
2e431051 | 7598 | int count, ro; |
50f56119 | 7599 | |
9a935856 DV |
7600 | /* The upper layers ensure that we either disabl a crtc or have a list |
7601 | * of connectors. For paranoia, double-check this. */ | |
7602 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
7603 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
7604 | ||
50f56119 | 7605 | count = 0; |
9a935856 DV |
7606 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7607 | base.head) { | |
7608 | /* Otherwise traverse passed in connector list and get encoders | |
7609 | * for them. */ | |
50f56119 | 7610 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
7611 | if (set->connectors[ro] == &connector->base) { |
7612 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
7613 | break; |
7614 | } | |
7615 | } | |
7616 | ||
9a935856 DV |
7617 | /* If we disable the crtc, disable all its connectors. Also, if |
7618 | * the connector is on the changing crtc but not on the new | |
7619 | * connector list, disable it. */ | |
7620 | if ((!set->fb || ro == set->num_connectors) && | |
7621 | connector->base.encoder && | |
7622 | connector->base.encoder->crtc == set->crtc) { | |
7623 | connector->new_encoder = NULL; | |
7624 | ||
7625 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
7626 | connector->base.base.id, | |
7627 | drm_get_connector_name(&connector->base)); | |
7628 | } | |
7629 | ||
7630 | ||
7631 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 7632 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 7633 | config->mode_changed = true; |
50f56119 | 7634 | } |
9a935856 DV |
7635 | |
7636 | /* Disable all disconnected encoders. */ | |
7637 | if (connector->base.status == connector_status_disconnected) | |
7638 | connector->new_encoder = NULL; | |
50f56119 | 7639 | } |
9a935856 | 7640 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 7641 | |
9a935856 | 7642 | /* Update crtc of enabled connectors. */ |
50f56119 | 7643 | count = 0; |
9a935856 DV |
7644 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7645 | base.head) { | |
7646 | if (!connector->new_encoder) | |
50f56119 DV |
7647 | continue; |
7648 | ||
9a935856 | 7649 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
7650 | |
7651 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 7652 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
7653 | new_crtc = set->crtc; |
7654 | } | |
7655 | ||
7656 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
7657 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7658 | new_crtc)) { | |
5e2b584e | 7659 | return -EINVAL; |
50f56119 | 7660 | } |
9a935856 DV |
7661 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7662 | ||
7663 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
7664 | connector->base.base.id, | |
7665 | drm_get_connector_name(&connector->base), | |
7666 | new_crtc->base.id); | |
7667 | } | |
7668 | ||
7669 | /* Check for any encoders that needs to be disabled. */ | |
7670 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7671 | base.head) { | |
7672 | list_for_each_entry(connector, | |
7673 | &dev->mode_config.connector_list, | |
7674 | base.head) { | |
7675 | if (connector->new_encoder == encoder) { | |
7676 | WARN_ON(!connector->new_encoder->new_crtc); | |
7677 | ||
7678 | goto next_encoder; | |
7679 | } | |
7680 | } | |
7681 | encoder->new_crtc = NULL; | |
7682 | next_encoder: | |
7683 | /* Only now check for crtc changes so we don't miss encoders | |
7684 | * that will be disabled. */ | |
7685 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 7686 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 7687 | config->mode_changed = true; |
50f56119 DV |
7688 | } |
7689 | } | |
9a935856 | 7690 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 7691 | |
2e431051 DV |
7692 | return 0; |
7693 | } | |
7694 | ||
7695 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
7696 | { | |
7697 | struct drm_device *dev; | |
2e431051 DV |
7698 | struct drm_mode_set save_set; |
7699 | struct intel_set_config *config; | |
7700 | int ret; | |
2e431051 | 7701 | |
8d3e375e DV |
7702 | BUG_ON(!set); |
7703 | BUG_ON(!set->crtc); | |
7704 | BUG_ON(!set->crtc->helper_private); | |
2e431051 DV |
7705 | |
7706 | if (!set->mode) | |
7707 | set->fb = NULL; | |
7708 | ||
431e50f7 DV |
7709 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7710 | * Unfortunately the crtc helper doesn't do much at all for this case, | |
7711 | * so we have to cope with this madness until the fb helper is fixed up. */ | |
7712 | if (set->fb && set->num_connectors == 0) | |
7713 | return 0; | |
7714 | ||
2e431051 DV |
7715 | if (set->fb) { |
7716 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
7717 | set->crtc->base.id, set->fb->base.id, | |
7718 | (int)set->num_connectors, set->x, set->y); | |
7719 | } else { | |
7720 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
7721 | } |
7722 | ||
7723 | dev = set->crtc->dev; | |
7724 | ||
7725 | ret = -ENOMEM; | |
7726 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
7727 | if (!config) | |
7728 | goto out_config; | |
7729 | ||
7730 | ret = intel_set_config_save_state(dev, config); | |
7731 | if (ret) | |
7732 | goto out_config; | |
7733 | ||
7734 | save_set.crtc = set->crtc; | |
7735 | save_set.mode = &set->crtc->mode; | |
7736 | save_set.x = set->crtc->x; | |
7737 | save_set.y = set->crtc->y; | |
7738 | save_set.fb = set->crtc->fb; | |
7739 | ||
7740 | /* Compute whether we need a full modeset, only an fb base update or no | |
7741 | * change at all. In the future we might also check whether only the | |
7742 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
7743 | * such cases. */ | |
7744 | intel_set_config_compute_mode_changes(set, config); | |
7745 | ||
9a935856 | 7746 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
7747 | if (ret) |
7748 | goto fail; | |
7749 | ||
5e2b584e | 7750 | if (config->mode_changed) { |
87f1faa6 | 7751 | if (set->mode) { |
50f56119 DV |
7752 | DRM_DEBUG_KMS("attempting to set mode from" |
7753 | " userspace\n"); | |
7754 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
7755 | } |
7756 | ||
7757 | if (!intel_set_mode(set->crtc, set->mode, | |
7758 | set->x, set->y, set->fb)) { | |
7759 | DRM_ERROR("failed to set mode on [CRTC:%d]\n", | |
7760 | set->crtc->base.id); | |
7761 | ret = -EINVAL; | |
7762 | goto fail; | |
7763 | } | |
5e2b584e | 7764 | } else if (config->fb_changed) { |
4f660f49 | 7765 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 7766 | set->x, set->y, set->fb); |
50f56119 DV |
7767 | } |
7768 | ||
d9e55608 DV |
7769 | intel_set_config_free(config); |
7770 | ||
50f56119 DV |
7771 | return 0; |
7772 | ||
7773 | fail: | |
85f9eb71 | 7774 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
7775 | |
7776 | /* Try to restore the config */ | |
5e2b584e | 7777 | if (config->mode_changed && |
a6778b3c DV |
7778 | !intel_set_mode(save_set.crtc, save_set.mode, |
7779 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
7780 | DRM_ERROR("failed to restore config after modeset failure\n"); |
7781 | ||
d9e55608 DV |
7782 | out_config: |
7783 | intel_set_config_free(config); | |
50f56119 DV |
7784 | return ret; |
7785 | } | |
f6e5b160 CW |
7786 | |
7787 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
7788 | .cursor_set = intel_crtc_cursor_set, |
7789 | .cursor_move = intel_crtc_cursor_move, | |
7790 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 7791 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
7792 | .destroy = intel_crtc_destroy, |
7793 | .page_flip = intel_crtc_page_flip, | |
7794 | }; | |
7795 | ||
79f689aa PZ |
7796 | static void intel_cpu_pll_init(struct drm_device *dev) |
7797 | { | |
affa9354 | 7798 | if (HAS_DDI(dev)) |
79f689aa PZ |
7799 | intel_ddi_pll_init(dev); |
7800 | } | |
7801 | ||
ee7b9f93 JB |
7802 | static void intel_pch_pll_init(struct drm_device *dev) |
7803 | { | |
7804 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7805 | int i; | |
7806 | ||
7807 | if (dev_priv->num_pch_pll == 0) { | |
7808 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
7809 | return; | |
7810 | } | |
7811 | ||
7812 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
7813 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
7814 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
7815 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
7816 | } | |
7817 | } | |
7818 | ||
b358d0a6 | 7819 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7820 | { |
22fd0fab | 7821 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7822 | struct intel_crtc *intel_crtc; |
7823 | int i; | |
7824 | ||
7825 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7826 | if (intel_crtc == NULL) | |
7827 | return; | |
7828 | ||
7829 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7830 | ||
7831 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7832 | for (i = 0; i < 256; i++) { |
7833 | intel_crtc->lut_r[i] = i; | |
7834 | intel_crtc->lut_g[i] = i; | |
7835 | intel_crtc->lut_b[i] = i; | |
7836 | } | |
7837 | ||
80824003 JB |
7838 | /* Swap pipes & planes for FBC on pre-965 */ |
7839 | intel_crtc->pipe = pipe; | |
7840 | intel_crtc->plane = pipe; | |
a5c961d1 | 7841 | intel_crtc->cpu_transcoder = pipe; |
e2e767ab | 7842 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7843 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7844 | intel_crtc->plane = !pipe; |
80824003 JB |
7845 | } |
7846 | ||
22fd0fab JB |
7847 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7848 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7849 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7850 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7851 | ||
5a354204 | 7852 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 | 7853 | |
79e53945 | 7854 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
7855 | } |
7856 | ||
08d7b3d1 | 7857 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7858 | struct drm_file *file) |
08d7b3d1 | 7859 | { |
08d7b3d1 | 7860 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
7861 | struct drm_mode_object *drmmode_obj; |
7862 | struct intel_crtc *crtc; | |
08d7b3d1 | 7863 | |
1cff8f6b DV |
7864 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7865 | return -ENODEV; | |
08d7b3d1 | 7866 | |
c05422d5 DV |
7867 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7868 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7869 | |
c05422d5 | 7870 | if (!drmmode_obj) { |
08d7b3d1 CW |
7871 | DRM_ERROR("no such CRTC id\n"); |
7872 | return -EINVAL; | |
7873 | } | |
7874 | ||
c05422d5 DV |
7875 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7876 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7877 | |
c05422d5 | 7878 | return 0; |
08d7b3d1 CW |
7879 | } |
7880 | ||
66a9278e | 7881 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 7882 | { |
66a9278e DV |
7883 | struct drm_device *dev = encoder->base.dev; |
7884 | struct intel_encoder *source_encoder; | |
79e53945 | 7885 | int index_mask = 0; |
79e53945 JB |
7886 | int entry = 0; |
7887 | ||
66a9278e DV |
7888 | list_for_each_entry(source_encoder, |
7889 | &dev->mode_config.encoder_list, base.head) { | |
7890 | ||
7891 | if (encoder == source_encoder) | |
79e53945 | 7892 | index_mask |= (1 << entry); |
66a9278e DV |
7893 | |
7894 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
7895 | if (encoder->cloneable && source_encoder->cloneable) | |
7896 | index_mask |= (1 << entry); | |
7897 | ||
79e53945 JB |
7898 | entry++; |
7899 | } | |
4ef69c7a | 7900 | |
79e53945 JB |
7901 | return index_mask; |
7902 | } | |
7903 | ||
4d302442 CW |
7904 | static bool has_edp_a(struct drm_device *dev) |
7905 | { | |
7906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7907 | ||
7908 | if (!IS_MOBILE(dev)) | |
7909 | return false; | |
7910 | ||
7911 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7912 | return false; | |
7913 | ||
7914 | if (IS_GEN5(dev) && | |
7915 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7916 | return false; | |
7917 | ||
7918 | return true; | |
7919 | } | |
7920 | ||
79e53945 JB |
7921 | static void intel_setup_outputs(struct drm_device *dev) |
7922 | { | |
725e30ad | 7923 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7924 | struct intel_encoder *encoder; |
cb0953d7 | 7925 | bool dpd_is_edp = false; |
f3cfcba6 | 7926 | bool has_lvds; |
79e53945 | 7927 | |
f3cfcba6 | 7928 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
7929 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7930 | /* disable the panel fitter on everything but LVDS */ | |
7931 | I915_WRITE(PFIT_CONTROL, 0); | |
7932 | } | |
79e53945 | 7933 | |
affa9354 | 7934 | if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES))) |
79935fca | 7935 | intel_crt_init(dev); |
cb0953d7 | 7936 | |
affa9354 | 7937 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
7938 | int found; |
7939 | ||
7940 | /* Haswell uses DDI functions to detect digital outputs */ | |
7941 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
7942 | /* DDI A only supports eDP */ | |
7943 | if (found) | |
7944 | intel_ddi_init(dev, PORT_A); | |
7945 | ||
7946 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
7947 | * register */ | |
7948 | found = I915_READ(SFUSE_STRAP); | |
7949 | ||
7950 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
7951 | intel_ddi_init(dev, PORT_B); | |
7952 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
7953 | intel_ddi_init(dev, PORT_C); | |
7954 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
7955 | intel_ddi_init(dev, PORT_D); | |
7956 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 7957 | int found; |
270b3042 DV |
7958 | dpd_is_edp = intel_dpd_is_edp(dev); |
7959 | ||
7960 | if (has_edp_a(dev)) | |
7961 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 7962 | |
30ad48b7 | 7963 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 7964 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 7965 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 7966 | if (!found) |
08d644ad | 7967 | intel_hdmi_init(dev, HDMIB, PORT_B); |
5eb08b69 | 7968 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 7969 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
7970 | } |
7971 | ||
7972 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
08d644ad | 7973 | intel_hdmi_init(dev, HDMIC, PORT_C); |
30ad48b7 | 7974 | |
b708a1d5 | 7975 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
08d644ad | 7976 | intel_hdmi_init(dev, HDMID, PORT_D); |
30ad48b7 | 7977 | |
5eb08b69 | 7978 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 7979 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 7980 | |
270b3042 | 7981 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 7982 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d JB |
7983 | } else if (IS_VALLEYVIEW(dev)) { |
7984 | int found; | |
7985 | ||
19c03924 GB |
7986 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
7987 | if (I915_READ(DP_C) & DP_DETECTED) | |
7988 | intel_dp_init(dev, DP_C, PORT_C); | |
7989 | ||
4a87d65d JB |
7990 | if (I915_READ(SDVOB) & PORT_DETECTED) { |
7991 | /* SDVOB multiplex with HDMIB */ | |
7992 | found = intel_sdvo_init(dev, SDVOB, true); | |
7993 | if (!found) | |
08d644ad | 7994 | intel_hdmi_init(dev, SDVOB, PORT_B); |
4a87d65d | 7995 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
ab9d7c30 | 7996 | intel_dp_init(dev, DP_B, PORT_B); |
4a87d65d JB |
7997 | } |
7998 | ||
7999 | if (I915_READ(SDVOC) & PORT_DETECTED) | |
08d644ad | 8000 | intel_hdmi_init(dev, SDVOC, PORT_C); |
5eb08b69 | 8001 | |
103a196f | 8002 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8003 | bool found = false; |
7d57382e | 8004 | |
725e30ad | 8005 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8006 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 8007 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
8008 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8009 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
08d644ad | 8010 | intel_hdmi_init(dev, SDVOB, PORT_B); |
b01f2c3a | 8011 | } |
27185ae1 | 8012 | |
b01f2c3a JB |
8013 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8014 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 8015 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 8016 | } |
725e30ad | 8017 | } |
13520b05 KH |
8018 | |
8019 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8020 | |
b01f2c3a JB |
8021 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
8022 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 8023 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 8024 | } |
27185ae1 ML |
8025 | |
8026 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
8027 | ||
b01f2c3a JB |
8028 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8029 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
08d644ad | 8030 | intel_hdmi_init(dev, SDVOC, PORT_C); |
b01f2c3a JB |
8031 | } |
8032 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8033 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 8034 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 8035 | } |
725e30ad | 8036 | } |
27185ae1 | 8037 | |
b01f2c3a JB |
8038 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8039 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8040 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 8041 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 8042 | } |
bad720ff | 8043 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8044 | intel_dvo_init(dev); |
8045 | ||
103a196f | 8046 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8047 | intel_tv_init(dev); |
8048 | ||
4ef69c7a CW |
8049 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8050 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8051 | encoder->base.possible_clones = | |
66a9278e | 8052 | intel_encoder_clones(encoder); |
79e53945 | 8053 | } |
47356eb6 | 8054 | |
40579abe | 8055 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
9fb526db | 8056 | ironlake_init_pch_refclk(dev); |
270b3042 DV |
8057 | |
8058 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
8059 | } |
8060 | ||
8061 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8062 | { | |
8063 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8064 | |
8065 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8066 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8067 | |
8068 | kfree(intel_fb); | |
8069 | } | |
8070 | ||
8071 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8072 | struct drm_file *file, |
79e53945 JB |
8073 | unsigned int *handle) |
8074 | { | |
8075 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8076 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8077 | |
05394f39 | 8078 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8079 | } |
8080 | ||
8081 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8082 | .destroy = intel_user_framebuffer_destroy, | |
8083 | .create_handle = intel_user_framebuffer_create_handle, | |
8084 | }; | |
8085 | ||
38651674 DA |
8086 | int intel_framebuffer_init(struct drm_device *dev, |
8087 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8088 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8089 | struct drm_i915_gem_object *obj) |
79e53945 | 8090 | { |
79e53945 JB |
8091 | int ret; |
8092 | ||
05394f39 | 8093 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
8094 | return -EINVAL; |
8095 | ||
308e5bcb | 8096 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
8097 | return -EINVAL; |
8098 | ||
5d7bd705 VS |
8099 | /* FIXME <= Gen4 stride limits are bit unclear */ |
8100 | if (mode_cmd->pitches[0] > 32768) | |
8101 | return -EINVAL; | |
8102 | ||
8103 | if (obj->tiling_mode != I915_TILING_NONE && | |
8104 | mode_cmd->pitches[0] != obj->stride) | |
8105 | return -EINVAL; | |
8106 | ||
57779d06 | 8107 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 8108 | switch (mode_cmd->pixel_format) { |
57779d06 | 8109 | case DRM_FORMAT_C8: |
04b3924d VS |
8110 | case DRM_FORMAT_RGB565: |
8111 | case DRM_FORMAT_XRGB8888: | |
8112 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
8113 | break; |
8114 | case DRM_FORMAT_XRGB1555: | |
8115 | case DRM_FORMAT_ARGB1555: | |
8116 | if (INTEL_INFO(dev)->gen > 3) | |
8117 | return -EINVAL; | |
8118 | break; | |
8119 | case DRM_FORMAT_XBGR8888: | |
8120 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
8121 | case DRM_FORMAT_XRGB2101010: |
8122 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
8123 | case DRM_FORMAT_XBGR2101010: |
8124 | case DRM_FORMAT_ABGR2101010: | |
8125 | if (INTEL_INFO(dev)->gen < 4) | |
8126 | return -EINVAL; | |
b5626747 | 8127 | break; |
04b3924d VS |
8128 | case DRM_FORMAT_YUYV: |
8129 | case DRM_FORMAT_UYVY: | |
8130 | case DRM_FORMAT_YVYU: | |
8131 | case DRM_FORMAT_VYUY: | |
57779d06 VS |
8132 | if (INTEL_INFO(dev)->gen < 6) |
8133 | return -EINVAL; | |
57cd6508 CW |
8134 | break; |
8135 | default: | |
57779d06 | 8136 | DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); |
57cd6508 CW |
8137 | return -EINVAL; |
8138 | } | |
8139 | ||
90f9a336 VS |
8140 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
8141 | if (mode_cmd->offsets[0] != 0) | |
8142 | return -EINVAL; | |
8143 | ||
79e53945 JB |
8144 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8145 | if (ret) { | |
8146 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8147 | return ret; | |
8148 | } | |
8149 | ||
8150 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 8151 | intel_fb->obj = obj; |
79e53945 JB |
8152 | return 0; |
8153 | } | |
8154 | ||
79e53945 JB |
8155 | static struct drm_framebuffer * |
8156 | intel_user_framebuffer_create(struct drm_device *dev, | |
8157 | struct drm_file *filp, | |
308e5bcb | 8158 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8159 | { |
05394f39 | 8160 | struct drm_i915_gem_object *obj; |
79e53945 | 8161 | |
308e5bcb JB |
8162 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8163 | mode_cmd->handles[0])); | |
c8725226 | 8164 | if (&obj->base == NULL) |
cce13ff7 | 8165 | return ERR_PTR(-ENOENT); |
79e53945 | 8166 | |
d2dff872 | 8167 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
8168 | } |
8169 | ||
79e53945 | 8170 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 8171 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 8172 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
8173 | }; |
8174 | ||
e70236a8 JB |
8175 | /* Set up chip specific display functions */ |
8176 | static void intel_init_display(struct drm_device *dev) | |
8177 | { | |
8178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8179 | ||
8180 | /* We always want a DPMS function */ | |
affa9354 | 8181 | if (HAS_DDI(dev)) { |
09b4ddf9 | 8182 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
8183 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
8184 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 8185 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
8186 | dev_priv->display.update_plane = ironlake_update_plane; |
8187 | } else if (HAS_PCH_SPLIT(dev)) { | |
f564048e | 8188 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
8189 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
8190 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 8191 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 8192 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8193 | } else { |
f564048e | 8194 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
8195 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
8196 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 8197 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 8198 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8199 | } |
e70236a8 | 8200 | |
e70236a8 | 8201 | /* Returns the core display clock speed */ |
25eb05fc JB |
8202 | if (IS_VALLEYVIEW(dev)) |
8203 | dev_priv->display.get_display_clock_speed = | |
8204 | valleyview_get_display_clock_speed; | |
8205 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
8206 | dev_priv->display.get_display_clock_speed = |
8207 | i945_get_display_clock_speed; | |
8208 | else if (IS_I915G(dev)) | |
8209 | dev_priv->display.get_display_clock_speed = | |
8210 | i915_get_display_clock_speed; | |
f2b115e6 | 8211 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8212 | dev_priv->display.get_display_clock_speed = |
8213 | i9xx_misc_get_display_clock_speed; | |
8214 | else if (IS_I915GM(dev)) | |
8215 | dev_priv->display.get_display_clock_speed = | |
8216 | i915gm_get_display_clock_speed; | |
8217 | else if (IS_I865G(dev)) | |
8218 | dev_priv->display.get_display_clock_speed = | |
8219 | i865_get_display_clock_speed; | |
f0f8a9ce | 8220 | else if (IS_I85X(dev)) |
e70236a8 JB |
8221 | dev_priv->display.get_display_clock_speed = |
8222 | i855_get_display_clock_speed; | |
8223 | else /* 852, 830 */ | |
8224 | dev_priv->display.get_display_clock_speed = | |
8225 | i830_get_display_clock_speed; | |
8226 | ||
7f8a8569 | 8227 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 8228 | if (IS_GEN5(dev)) { |
674cf967 | 8229 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 8230 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 8231 | } else if (IS_GEN6(dev)) { |
674cf967 | 8232 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 8233 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8234 | } else if (IS_IVYBRIDGE(dev)) { |
8235 | /* FIXME: detect B0+ stepping and use auto training */ | |
8236 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 8237 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
8238 | dev_priv->display.modeset_global_resources = |
8239 | ivb_modeset_global_resources; | |
c82e4d26 ED |
8240 | } else if (IS_HASWELL(dev)) { |
8241 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 8242 | dev_priv->display.write_eld = haswell_write_eld; |
7f8a8569 ZW |
8243 | } else |
8244 | dev_priv->display.update_wm = NULL; | |
6067aaea | 8245 | } else if (IS_G4X(dev)) { |
e0dac65e | 8246 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8247 | } |
8c9f3aaf JB |
8248 | |
8249 | /* Default just returns -ENODEV to indicate unsupported */ | |
8250 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8251 | ||
8252 | switch (INTEL_INFO(dev)->gen) { | |
8253 | case 2: | |
8254 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8255 | break; | |
8256 | ||
8257 | case 3: | |
8258 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8259 | break; | |
8260 | ||
8261 | case 4: | |
8262 | case 5: | |
8263 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8264 | break; | |
8265 | ||
8266 | case 6: | |
8267 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8268 | break; | |
7c9017e5 JB |
8269 | case 7: |
8270 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8271 | break; | |
8c9f3aaf | 8272 | } |
e70236a8 JB |
8273 | } |
8274 | ||
b690e96c JB |
8275 | /* |
8276 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8277 | * resume, or other times. This quirk makes sure that's the case for | |
8278 | * affected systems. | |
8279 | */ | |
0206e353 | 8280 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8281 | { |
8282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8283 | ||
8284 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 8285 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
8286 | } |
8287 | ||
435793df KP |
8288 | /* |
8289 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8290 | */ | |
8291 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8292 | { | |
8293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8294 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 8295 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
8296 | } |
8297 | ||
4dca20ef | 8298 | /* |
5a15ab5b CE |
8299 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
8300 | * brightness value | |
4dca20ef CE |
8301 | */ |
8302 | static void quirk_invert_brightness(struct drm_device *dev) | |
8303 | { | |
8304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8305 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 8306 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
8307 | } |
8308 | ||
b690e96c JB |
8309 | struct intel_quirk { |
8310 | int device; | |
8311 | int subsystem_vendor; | |
8312 | int subsystem_device; | |
8313 | void (*hook)(struct drm_device *dev); | |
8314 | }; | |
8315 | ||
5f85f176 EE |
8316 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
8317 | struct intel_dmi_quirk { | |
8318 | void (*hook)(struct drm_device *dev); | |
8319 | const struct dmi_system_id (*dmi_id_list)[]; | |
8320 | }; | |
8321 | ||
8322 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
8323 | { | |
8324 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
8325 | return 1; | |
8326 | } | |
8327 | ||
8328 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
8329 | { | |
8330 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
8331 | { | |
8332 | .callback = intel_dmi_reverse_brightness, | |
8333 | .ident = "NCR Corporation", | |
8334 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
8335 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
8336 | }, | |
8337 | }, | |
8338 | { } /* terminating entry */ | |
8339 | }, | |
8340 | .hook = quirk_invert_brightness, | |
8341 | }, | |
8342 | }; | |
8343 | ||
c43b5634 | 8344 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 8345 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 8346 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 8347 | |
b690e96c JB |
8348 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
8349 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8350 | ||
b690e96c JB |
8351 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
8352 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8353 | ||
ccd0d36e | 8354 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 8355 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 8356 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
8357 | |
8358 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8359 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8360 | |
8361 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8362 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
8363 | |
8364 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
8365 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
8366 | }; |
8367 | ||
8368 | static void intel_init_quirks(struct drm_device *dev) | |
8369 | { | |
8370 | struct pci_dev *d = dev->pdev; | |
8371 | int i; | |
8372 | ||
8373 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8374 | struct intel_quirk *q = &intel_quirks[i]; | |
8375 | ||
8376 | if (d->device == q->device && | |
8377 | (d->subsystem_vendor == q->subsystem_vendor || | |
8378 | q->subsystem_vendor == PCI_ANY_ID) && | |
8379 | (d->subsystem_device == q->subsystem_device || | |
8380 | q->subsystem_device == PCI_ANY_ID)) | |
8381 | q->hook(dev); | |
8382 | } | |
5f85f176 EE |
8383 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
8384 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
8385 | intel_dmi_quirks[i].hook(dev); | |
8386 | } | |
b690e96c JB |
8387 | } |
8388 | ||
9cce37f4 JB |
8389 | /* Disable the VGA plane that we never use */ |
8390 | static void i915_disable_vga(struct drm_device *dev) | |
8391 | { | |
8392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8393 | u8 sr1; | |
8394 | u32 vga_reg; | |
8395 | ||
8396 | if (HAS_PCH_SPLIT(dev)) | |
8397 | vga_reg = CPU_VGACNTRL; | |
8398 | else | |
8399 | vga_reg = VGACNTRL; | |
8400 | ||
8401 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 8402 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
8403 | sr1 = inb(VGA_SR_DATA); |
8404 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8405 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8406 | udelay(300); | |
8407 | ||
8408 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8409 | POSTING_READ(vga_reg); | |
8410 | } | |
8411 | ||
f817586c DV |
8412 | void intel_modeset_init_hw(struct drm_device *dev) |
8413 | { | |
0232e927 ED |
8414 | /* We attempt to init the necessary power wells early in the initialization |
8415 | * time, so the subsystems that expect power to be enabled can work. | |
8416 | */ | |
8417 | intel_init_power_wells(dev); | |
8418 | ||
a8f78b58 ED |
8419 | intel_prepare_ddi(dev); |
8420 | ||
f817586c DV |
8421 | intel_init_clock_gating(dev); |
8422 | ||
79f5b2c7 | 8423 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 8424 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 8425 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
8426 | } |
8427 | ||
79e53945 JB |
8428 | void intel_modeset_init(struct drm_device *dev) |
8429 | { | |
652c393a | 8430 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 8431 | int i, ret; |
79e53945 JB |
8432 | |
8433 | drm_mode_config_init(dev); | |
8434 | ||
8435 | dev->mode_config.min_width = 0; | |
8436 | dev->mode_config.min_height = 0; | |
8437 | ||
019d96cb DA |
8438 | dev->mode_config.preferred_depth = 24; |
8439 | dev->mode_config.prefer_shadow = 1; | |
8440 | ||
e6ecefaa | 8441 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 8442 | |
b690e96c JB |
8443 | intel_init_quirks(dev); |
8444 | ||
1fa61106 ED |
8445 | intel_init_pm(dev); |
8446 | ||
e70236a8 JB |
8447 | intel_init_display(dev); |
8448 | ||
a6c45cf0 CW |
8449 | if (IS_GEN2(dev)) { |
8450 | dev->mode_config.max_width = 2048; | |
8451 | dev->mode_config.max_height = 2048; | |
8452 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8453 | dev->mode_config.max_width = 4096; |
8454 | dev->mode_config.max_height = 4096; | |
79e53945 | 8455 | } else { |
a6c45cf0 CW |
8456 | dev->mode_config.max_width = 8192; |
8457 | dev->mode_config.max_height = 8192; | |
79e53945 | 8458 | } |
dd2757f8 | 8459 | dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr; |
79e53945 | 8460 | |
28c97730 | 8461 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8462 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8463 | |
a3524f1b | 8464 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 8465 | intel_crtc_init(dev, i); |
00c2064b JB |
8466 | ret = intel_plane_init(dev, i); |
8467 | if (ret) | |
8468 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
8469 | } |
8470 | ||
79f689aa | 8471 | intel_cpu_pll_init(dev); |
ee7b9f93 JB |
8472 | intel_pch_pll_init(dev); |
8473 | ||
9cce37f4 JB |
8474 | /* Just disable it once at startup */ |
8475 | i915_disable_vga(dev); | |
79e53945 | 8476 | intel_setup_outputs(dev); |
11be49eb CW |
8477 | |
8478 | /* Just in case the BIOS is doing something questionable. */ | |
8479 | intel_disable_fbc(dev); | |
2c7111db CW |
8480 | } |
8481 | ||
24929352 DV |
8482 | static void |
8483 | intel_connector_break_all_links(struct intel_connector *connector) | |
8484 | { | |
8485 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8486 | connector->base.encoder = NULL; | |
8487 | connector->encoder->connectors_active = false; | |
8488 | connector->encoder->base.crtc = NULL; | |
8489 | } | |
8490 | ||
7fad798e DV |
8491 | static void intel_enable_pipe_a(struct drm_device *dev) |
8492 | { | |
8493 | struct intel_connector *connector; | |
8494 | struct drm_connector *crt = NULL; | |
8495 | struct intel_load_detect_pipe load_detect_temp; | |
8496 | ||
8497 | /* We can't just switch on the pipe A, we need to set things up with a | |
8498 | * proper mode and output configuration. As a gross hack, enable pipe A | |
8499 | * by enabling the load detect pipe once. */ | |
8500 | list_for_each_entry(connector, | |
8501 | &dev->mode_config.connector_list, | |
8502 | base.head) { | |
8503 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
8504 | crt = &connector->base; | |
8505 | break; | |
8506 | } | |
8507 | } | |
8508 | ||
8509 | if (!crt) | |
8510 | return; | |
8511 | ||
8512 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
8513 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
8514 | ||
652c393a | 8515 | |
7fad798e DV |
8516 | } |
8517 | ||
fa555837 DV |
8518 | static bool |
8519 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
8520 | { | |
8521 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
8522 | u32 reg, val; | |
8523 | ||
8524 | if (dev_priv->num_pipe == 1) | |
8525 | return true; | |
8526 | ||
8527 | reg = DSPCNTR(!crtc->plane); | |
8528 | val = I915_READ(reg); | |
8529 | ||
8530 | if ((val & DISPLAY_PLANE_ENABLE) && | |
8531 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
8532 | return false; | |
8533 | ||
8534 | return true; | |
8535 | } | |
8536 | ||
24929352 DV |
8537 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8538 | { | |
8539 | struct drm_device *dev = crtc->base.dev; | |
8540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 8541 | u32 reg; |
24929352 | 8542 | |
24929352 | 8543 | /* Clear any frame start delays used for debugging left by the BIOS */ |
702e7a56 | 8544 | reg = PIPECONF(crtc->cpu_transcoder); |
24929352 DV |
8545 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8546 | ||
8547 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
8548 | * disable the crtc (and hence change the state) if it is wrong. Note |
8549 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
8550 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
8551 | struct intel_connector *connector; |
8552 | bool plane; | |
8553 | ||
24929352 DV |
8554 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8555 | crtc->base.base.id); | |
8556 | ||
8557 | /* Pipe has the wrong plane attached and the plane is active. | |
8558 | * Temporarily change the plane mapping and disable everything | |
8559 | * ... */ | |
8560 | plane = crtc->plane; | |
8561 | crtc->plane = !plane; | |
8562 | dev_priv->display.crtc_disable(&crtc->base); | |
8563 | crtc->plane = plane; | |
8564 | ||
8565 | /* ... and break all links. */ | |
8566 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8567 | base.head) { | |
8568 | if (connector->encoder->base.crtc != &crtc->base) | |
8569 | continue; | |
8570 | ||
8571 | intel_connector_break_all_links(connector); | |
8572 | } | |
8573 | ||
8574 | WARN_ON(crtc->active); | |
8575 | crtc->base.enabled = false; | |
8576 | } | |
24929352 | 8577 | |
7fad798e DV |
8578 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8579 | crtc->pipe == PIPE_A && !crtc->active) { | |
8580 | /* BIOS forgot to enable pipe A, this mostly happens after | |
8581 | * resume. Force-enable the pipe to fix this, the update_dpms | |
8582 | * call below we restore the pipe to the right state, but leave | |
8583 | * the required bits on. */ | |
8584 | intel_enable_pipe_a(dev); | |
8585 | } | |
8586 | ||
24929352 DV |
8587 | /* Adjust the state of the output pipe according to whether we |
8588 | * have active connectors/encoders. */ | |
8589 | intel_crtc_update_dpms(&crtc->base); | |
8590 | ||
8591 | if (crtc->active != crtc->base.enabled) { | |
8592 | struct intel_encoder *encoder; | |
8593 | ||
8594 | /* This can happen either due to bugs in the get_hw_state | |
8595 | * functions or because the pipe is force-enabled due to the | |
8596 | * pipe A quirk. */ | |
8597 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
8598 | crtc->base.base.id, | |
8599 | crtc->base.enabled ? "enabled" : "disabled", | |
8600 | crtc->active ? "enabled" : "disabled"); | |
8601 | ||
8602 | crtc->base.enabled = crtc->active; | |
8603 | ||
8604 | /* Because we only establish the connector -> encoder -> | |
8605 | * crtc links if something is active, this means the | |
8606 | * crtc is now deactivated. Break the links. connector | |
8607 | * -> encoder links are only establish when things are | |
8608 | * actually up, hence no need to break them. */ | |
8609 | WARN_ON(crtc->active); | |
8610 | ||
8611 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
8612 | WARN_ON(encoder->connectors_active); | |
8613 | encoder->base.crtc = NULL; | |
8614 | } | |
8615 | } | |
8616 | } | |
8617 | ||
8618 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
8619 | { | |
8620 | struct intel_connector *connector; | |
8621 | struct drm_device *dev = encoder->base.dev; | |
8622 | ||
8623 | /* We need to check both for a crtc link (meaning that the | |
8624 | * encoder is active and trying to read from a pipe) and the | |
8625 | * pipe itself being active. */ | |
8626 | bool has_active_crtc = encoder->base.crtc && | |
8627 | to_intel_crtc(encoder->base.crtc)->active; | |
8628 | ||
8629 | if (encoder->connectors_active && !has_active_crtc) { | |
8630 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
8631 | encoder->base.base.id, | |
8632 | drm_get_encoder_name(&encoder->base)); | |
8633 | ||
8634 | /* Connector is active, but has no active pipe. This is | |
8635 | * fallout from our resume register restoring. Disable | |
8636 | * the encoder manually again. */ | |
8637 | if (encoder->base.crtc) { | |
8638 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
8639 | encoder->base.base.id, | |
8640 | drm_get_encoder_name(&encoder->base)); | |
8641 | encoder->disable(encoder); | |
8642 | } | |
8643 | ||
8644 | /* Inconsistent output/port/pipe state happens presumably due to | |
8645 | * a bug in one of the get_hw_state functions. Or someplace else | |
8646 | * in our code, like the register restore mess on resume. Clamp | |
8647 | * things to off as a safer default. */ | |
8648 | list_for_each_entry(connector, | |
8649 | &dev->mode_config.connector_list, | |
8650 | base.head) { | |
8651 | if (connector->encoder != encoder) | |
8652 | continue; | |
8653 | ||
8654 | intel_connector_break_all_links(connector); | |
8655 | } | |
8656 | } | |
8657 | /* Enabled encoders without active connectors will be fixed in | |
8658 | * the crtc fixup. */ | |
8659 | } | |
8660 | ||
8661 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
8662 | * and i915 state tracking structures. */ | |
45e2b5f6 DV |
8663 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
8664 | bool force_restore) | |
24929352 DV |
8665 | { |
8666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8667 | enum pipe pipe; | |
8668 | u32 tmp; | |
8669 | struct intel_crtc *crtc; | |
8670 | struct intel_encoder *encoder; | |
8671 | struct intel_connector *connector; | |
8672 | ||
affa9354 | 8673 | if (HAS_DDI(dev)) { |
e28d54cb PZ |
8674 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8675 | ||
8676 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8677 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8678 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8679 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8680 | pipe = PIPE_A; | |
8681 | break; | |
8682 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8683 | pipe = PIPE_B; | |
8684 | break; | |
8685 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8686 | pipe = PIPE_C; | |
8687 | break; | |
8688 | } | |
8689 | ||
8690 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8691 | crtc->cpu_transcoder = TRANSCODER_EDP; | |
8692 | ||
8693 | DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", | |
8694 | pipe_name(pipe)); | |
8695 | } | |
8696 | } | |
8697 | ||
24929352 DV |
8698 | for_each_pipe(pipe) { |
8699 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8700 | ||
702e7a56 | 8701 | tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); |
24929352 DV |
8702 | if (tmp & PIPECONF_ENABLE) |
8703 | crtc->active = true; | |
8704 | else | |
8705 | crtc->active = false; | |
8706 | ||
8707 | crtc->base.enabled = crtc->active; | |
8708 | ||
8709 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
8710 | crtc->base.base.id, | |
8711 | crtc->active ? "enabled" : "disabled"); | |
8712 | } | |
8713 | ||
affa9354 | 8714 | if (HAS_DDI(dev)) |
6441ab5f PZ |
8715 | intel_ddi_setup_hw_pll_state(dev); |
8716 | ||
24929352 DV |
8717 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8718 | base.head) { | |
8719 | pipe = 0; | |
8720 | ||
8721 | if (encoder->get_hw_state(encoder, &pipe)) { | |
8722 | encoder->base.crtc = | |
8723 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
8724 | } else { | |
8725 | encoder->base.crtc = NULL; | |
8726 | } | |
8727 | ||
8728 | encoder->connectors_active = false; | |
8729 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
8730 | encoder->base.base.id, | |
8731 | drm_get_encoder_name(&encoder->base), | |
8732 | encoder->base.crtc ? "enabled" : "disabled", | |
8733 | pipe); | |
8734 | } | |
8735 | ||
8736 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8737 | base.head) { | |
8738 | if (connector->get_hw_state(connector)) { | |
8739 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
8740 | connector->encoder->connectors_active = true; | |
8741 | connector->base.encoder = &connector->encoder->base; | |
8742 | } else { | |
8743 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8744 | connector->base.encoder = NULL; | |
8745 | } | |
8746 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
8747 | connector->base.base.id, | |
8748 | drm_get_connector_name(&connector->base), | |
8749 | connector->base.encoder ? "enabled" : "disabled"); | |
8750 | } | |
8751 | ||
8752 | /* HW state is read out, now we need to sanitize this mess. */ | |
8753 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8754 | base.head) { | |
8755 | intel_sanitize_encoder(encoder); | |
8756 | } | |
8757 | ||
8758 | for_each_pipe(pipe) { | |
8759 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8760 | intel_sanitize_crtc(crtc); | |
8761 | } | |
9a935856 | 8762 | |
45e2b5f6 DV |
8763 | if (force_restore) { |
8764 | for_each_pipe(pipe) { | |
8765 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8766 | intel_set_mode(&crtc->base, &crtc->base.mode, | |
8767 | crtc->base.x, crtc->base.y, crtc->base.fb); | |
8768 | } | |
8769 | } else { | |
8770 | intel_modeset_update_staged_output_state(dev); | |
8771 | } | |
8af6cf88 DV |
8772 | |
8773 | intel_modeset_check_state(dev); | |
2e938892 DV |
8774 | |
8775 | drm_mode_config_reset(dev); | |
2c7111db CW |
8776 | } |
8777 | ||
8778 | void intel_modeset_gem_init(struct drm_device *dev) | |
8779 | { | |
1833b134 | 8780 | intel_modeset_init_hw(dev); |
02e792fb DV |
8781 | |
8782 | intel_setup_overlay(dev); | |
24929352 | 8783 | |
45e2b5f6 | 8784 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
8785 | } |
8786 | ||
8787 | void intel_modeset_cleanup(struct drm_device *dev) | |
8788 | { | |
652c393a JB |
8789 | struct drm_i915_private *dev_priv = dev->dev_private; |
8790 | struct drm_crtc *crtc; | |
8791 | struct intel_crtc *intel_crtc; | |
8792 | ||
f87ea761 | 8793 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
8794 | mutex_lock(&dev->struct_mutex); |
8795 | ||
723bfd70 JB |
8796 | intel_unregister_dsm_handler(); |
8797 | ||
8798 | ||
652c393a JB |
8799 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8800 | /* Skip inactive CRTCs */ | |
8801 | if (!crtc->fb) | |
8802 | continue; | |
8803 | ||
8804 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 8805 | intel_increase_pllclock(crtc); |
652c393a JB |
8806 | } |
8807 | ||
973d04f9 | 8808 | intel_disable_fbc(dev); |
e70236a8 | 8809 | |
8090c6b9 | 8810 | intel_disable_gt_powersave(dev); |
0cdab21f | 8811 | |
930ebb46 DV |
8812 | ironlake_teardown_rc6(dev); |
8813 | ||
57f350b6 JB |
8814 | if (IS_VALLEYVIEW(dev)) |
8815 | vlv_init_dpio(dev); | |
8816 | ||
69341a5e KH |
8817 | mutex_unlock(&dev->struct_mutex); |
8818 | ||
6c0d9350 DV |
8819 | /* Disable the irq before mode object teardown, for the irq might |
8820 | * enqueue unpin/hotplug work. */ | |
8821 | drm_irq_uninstall(dev); | |
8822 | cancel_work_sync(&dev_priv->hotplug_work); | |
c6a828d3 | 8823 | cancel_work_sync(&dev_priv->rps.work); |
6c0d9350 | 8824 | |
1630fe75 CW |
8825 | /* flush any delayed tasks or pending work */ |
8826 | flush_scheduled_work(); | |
8827 | ||
79e53945 JB |
8828 | drm_mode_config_cleanup(dev); |
8829 | } | |
8830 | ||
f1c79df3 ZW |
8831 | /* |
8832 | * Return which encoder is currently attached for connector. | |
8833 | */ | |
df0e9248 | 8834 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 8835 | { |
df0e9248 CW |
8836 | return &intel_attached_encoder(connector)->base; |
8837 | } | |
f1c79df3 | 8838 | |
df0e9248 CW |
8839 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8840 | struct intel_encoder *encoder) | |
8841 | { | |
8842 | connector->encoder = encoder; | |
8843 | drm_mode_connector_attach_encoder(&connector->base, | |
8844 | &encoder->base); | |
79e53945 | 8845 | } |
28d52043 DA |
8846 | |
8847 | /* | |
8848 | * set vga decode state - true == enable VGA decode | |
8849 | */ | |
8850 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
8851 | { | |
8852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8853 | u16 gmch_ctrl; | |
8854 | ||
8855 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
8856 | if (state) | |
8857 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
8858 | else | |
8859 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
8860 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
8861 | return 0; | |
8862 | } | |
c4a1d9e4 CW |
8863 | |
8864 | #ifdef CONFIG_DEBUG_FS | |
8865 | #include <linux/seq_file.h> | |
8866 | ||
8867 | struct intel_display_error_state { | |
8868 | struct intel_cursor_error_state { | |
8869 | u32 control; | |
8870 | u32 position; | |
8871 | u32 base; | |
8872 | u32 size; | |
52331309 | 8873 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8874 | |
8875 | struct intel_pipe_error_state { | |
8876 | u32 conf; | |
8877 | u32 source; | |
8878 | ||
8879 | u32 htotal; | |
8880 | u32 hblank; | |
8881 | u32 hsync; | |
8882 | u32 vtotal; | |
8883 | u32 vblank; | |
8884 | u32 vsync; | |
52331309 | 8885 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8886 | |
8887 | struct intel_plane_error_state { | |
8888 | u32 control; | |
8889 | u32 stride; | |
8890 | u32 size; | |
8891 | u32 pos; | |
8892 | u32 addr; | |
8893 | u32 surface; | |
8894 | u32 tile_offset; | |
52331309 | 8895 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
8896 | }; |
8897 | ||
8898 | struct intel_display_error_state * | |
8899 | intel_display_capture_error_state(struct drm_device *dev) | |
8900 | { | |
0206e353 | 8901 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 8902 | struct intel_display_error_state *error; |
702e7a56 | 8903 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
8904 | int i; |
8905 | ||
8906 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
8907 | if (error == NULL) | |
8908 | return NULL; | |
8909 | ||
52331309 | 8910 | for_each_pipe(i) { |
702e7a56 PZ |
8911 | cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); |
8912 | ||
c4a1d9e4 CW |
8913 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
8914 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
8915 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
8916 | ||
8917 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
8918 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
8919 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 8920 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
8921 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8922 | if (INTEL_INFO(dev)->gen >= 4) { | |
8923 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
8924 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
8925 | } | |
8926 | ||
702e7a56 | 8927 | error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
c4a1d9e4 | 8928 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
fe2b8f9d PZ |
8929 | error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
8930 | error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
8931 | error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8932 | error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
8933 | error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
8934 | error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
8935 | } |
8936 | ||
8937 | return error; | |
8938 | } | |
8939 | ||
8940 | void | |
8941 | intel_display_print_error_state(struct seq_file *m, | |
8942 | struct drm_device *dev, | |
8943 | struct intel_display_error_state *error) | |
8944 | { | |
52331309 | 8945 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
8946 | int i; |
8947 | ||
52331309 DL |
8948 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
8949 | for_each_pipe(i) { | |
c4a1d9e4 CW |
8950 | seq_printf(m, "Pipe [%d]:\n", i); |
8951 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
8952 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
8953 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
8954 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
8955 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
8956 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
8957 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
8958 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
8959 | ||
8960 | seq_printf(m, "Plane [%d]:\n", i); | |
8961 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
8962 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
8963 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
8964 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
8965 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
8966 | if (INTEL_INFO(dev)->gen >= 4) { | |
8967 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
8968 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
8969 | } | |
8970 | ||
8971 | seq_printf(m, "Cursor [%d]:\n", i); | |
8972 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
8973 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
8974 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
8975 | } | |
8976 | } | |
8977 | #endif |