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Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linux
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945
JB		 41
42#include "drm_crtc_helper.h"
43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
79e53945 90
a4fc5ed6
KP		 91static bool
92intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 94static bool
f2b115e6
AJ		 95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 97
021357ac
CW		 98static inline u32 /* units of 100MHz */
99intel_fdi_link_freq(struct drm_device *dev)
100{
8b99e68c
CW		 101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
021357ac
CW		 106}
107
e4b36699 108static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
d4906093 119 .find_pll = intel_find_best_PLL,
e4b36699
KP		 120};
121
122static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
d4906093 133 .find_pll = intel_find_best_PLL,
e4b36699 134};
273e27ca 135
e4b36699 136static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
d4906093 147 .find_pll = intel_find_best_PLL,
e4b36699
KP		 148};
149
150static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
d4906093 161 .find_pll = intel_find_best_PLL,
e4b36699
KP		 162};
163
273e27ca 164
e4b36699 165static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
044c7c41 177 },
d4906093 178 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 179};
180
181static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
d4906093 192 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 193};
194
195static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
044c7c41 206 },
d4906093 207 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
044c7c41 221 },
d4906093 222 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 223};
224
225static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
273e27ca 235 .p2_slow = 10, .p2_fast = 10 },
0206e353 236 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 237};
238
f2b115e6 239static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 242 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
273e27ca 245 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
6115707b 252 .find_pll = intel_find_best_PLL,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
6115707b 266 .find_pll = intel_find_best_PLL,
e4b36699
KP		 267};
268
273e27ca
EA		 269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
4547668a 285 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 286};
287
b91ad0ec 288static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 313 .find_pll = intel_g4x_find_best_PLL,
314};
315
273e27ca 316/* LVDS 100mhz refclk limits. */
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
0206e353 325 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
0206e353 339 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 342 .find_pll = intel_g4x_find_best_PLL,
343};
344
345static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
273e27ca 355 .p2_slow = 10, .p2_fast = 10 },
0206e353 356 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 357};
358
1b894b59
CW		 359static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
2c07245f 361{
b91ad0ec
ZW		 362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 364 const intel_limit_t *limit;
b91ad0ec
ZW		 365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
1b894b59 370 if (refclk == 100000)
b91ad0ec
ZW		 371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
1b894b59 375 if (refclk == 100000)
b91ad0ec
ZW		 376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
2c07245f 383 else
b91ad0ec 384 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 385
386 return limit;
387}
388
044c7c41
ML		 389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
e4b36699 399 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 400 else
401 /* LVDS with dual channel */
e4b36699 402 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 405 limit = &intel_limits_g4x_hdmi;
044c7c41 406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 407 limit = &intel_limits_g4x_sdvo;
0206e353 408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 409 limit = &intel_limits_g4x_display_port;
044c7c41 410 } else /* The option is for other outputs */
e4b36699 411 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 412
413 return limit;
414}
415
1b894b59 416static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 417{
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
bad720ff 421 if (HAS_PCH_SPLIT(dev))
1b894b59 422 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 423 else if (IS_G4X(dev)) {
044c7c41 424 limit = intel_g4x_limit(crtc);
f2b115e6 425 } else if (IS_PINEVIEW(dev)) {
2177832f 426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 427 limit = &intel_limits_pineview_lvds;
2177832f 428 else
f2b115e6 429 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 437 limit = &intel_limits_i8xx_lvds;
79e53945 438 else
e4b36699 439 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 440 }
441 return limit;
442}
443
f2b115e6
AJ		 444/* m1 is reserved as 0 in Pineview, n is a ring counter */
445static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 446{
2177832f
SL		 447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451}
452
453static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454{
f2b115e6
AJ		 455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
2177832f
SL		 457 return;
458 }
79e53945
JB		 459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463}
464
79e53945
JB		 465/**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
4ef69c7a 468bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 469{
4ef69c7a
CW		 470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
79e53945
JB		 479}
480
7c04d1d9 481#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 482/**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
1b894b59
CW		 487static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
79e53945 490{
79e53945 491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 492 INTELPllInvalid("p1 out of range\n");
79e53945 493 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 494 INTELPllInvalid("p out of range\n");
79e53945 495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 496 INTELPllInvalid("m2 out of range\n");
79e53945 497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 498 INTELPllInvalid("m1 out of range\n");
f2b115e6 499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 500 INTELPllInvalid("m1 <= m2\n");
79e53945 501 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 502 INTELPllInvalid("m out of range\n");
79e53945 503 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 504 INTELPllInvalid("n out of range\n");
79e53945 505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 506 INTELPllInvalid("vco out of range\n");
79e53945
JB		 507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 511 INTELPllInvalid("dot out of range\n");
79e53945
JB		 512
513 return true;
514}
515
d4906093
ML		 516static bool
517intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
79e53945
JB		 524 int err = target;
525
bc5e5718 526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 527 (I915_READ(LVDS)) != 0) {
79e53945
JB		 528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
0206e353 546 memset(best_clock, 0, sizeof(*best_clock));
79e53945 547
42158660
ZY		 548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 559 int this_err;
560
2177832f 561 intel_clock(dev, refclk, &clock);
1b894b59
CW		 562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
79e53945
JB		 564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577}
578
d4906093
ML		 579static bool
580intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
6ba770dc
AJ		 588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 593 int lvds_reg;
594
c619eed4 595 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
f77f13e2 613 /* based on hardware requirement, prefer smaller n to precision */
d4906093 614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 615 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
2177832f 624 intel_clock(dev, refclk, &clock);
1b894b59
CW		 625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
d4906093 627 continue;
1b894b59
CW		 628
629 this_err = abs(clock.dot - target);
d4906093
ML		 630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
2c07245f
ZW		 640 return found;
641}
642
5eb08b69 643static bool
f2b115e6
AJ		 644intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 646{
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
4547668a 649
5eb08b69
ZW		 650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666}
667
a4fc5ed6
KP		 668/* DisplayPort has only two frequencies, 162MHz and 270MHz */
669static bool
670intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672{
5eddb70b
CW		 673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
a4fc5ed6
KP		 693}
694
9d0498a2
JB		 695/**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 704{
9d0498a2 705 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 706 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 707
300387c0
CW		 708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
9d0498a2 724 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
9d0498a2
JB		 728 DRM_DEBUG_KMS("vblank wait timed out\n");
729}
730
ab7ad7f6
KP		 731/*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
ab7ad7f6
KP		 740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
58e10eb9 746 *
9d0498a2 747 */
58e10eb9 748void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 751
752 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 753 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 754
755 /* Wait for the Pipe State to go off */
58e10eb9
CW		 756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
ab7ad7f6
KP		 758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
58e10eb9 761 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
58e10eb9 766 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 767 mdelay(5);
58e10eb9 768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
79e53945
JB		 773}
774
b24e7179
JB		 775static const char *state_string(bool enabled)
776{
777 return enabled ? "on" : "off";
778}
779
780/* Only for pre-ILK configs */
781static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783{
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794}
795#define assert_pll_enabled(d, p) assert_pll(d, p, true)
796#define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
040484af
JB		 798/* For ILK+ */
799static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801{
802 int reg;
803 u32 val;
804 bool cur_state;
805
d3ccbe86
JB		 806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
040484af
JB		 819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825}
826#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831{
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842}
843#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848{
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859}
860#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876}
877
878static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880{
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887}
888
ea0760cf
JB		 889static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
0de3b485 895 bool locked = true;
ea0760cf
JB		 896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 915 pipe_name(pipe));
ea0760cf
JB		 916}
917
63d7bbe9
JB		 918static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
b24e7179
JB		 920{
921 int reg;
922 u32 val;
63d7bbe9 923 bool cur_state;
b24e7179
JB		 924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
63d7bbe9
JB		 927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 930 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 931}
63d7bbe9
JB		 932#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 934
935static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936 enum plane plane)
937{
938 int reg;
939 u32 val;
940
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 945 plane_name(plane));
b24e7179
JB		 946}
947
948static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 int reg, i;
952 u32 val;
953 int cur_pipe;
954
19ec1358
JB		 955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
957 return;
958
b24e7179
JB		 959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
961 reg = DSPCNTR(i);
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
b24e7179
JB		 968 }
969}
970
92f2584a
JB		 971static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972{
973 u32 val;
974 bool enabled;
975
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980}
981
982static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe)
984{
985 int reg;
986 u32 val;
987 bool enabled;
988
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 992 WARN(enabled,
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
994 pipe_name(pipe));
92f2584a
JB		 995}
996
4e634389
KP		 997static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 999{
1000 if ((val & DP_PORT_EN) == 0)
1001 return false;
1002
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 return false;
1008 } else {
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010 return false;
1011 }
1012 return true;
1013}
1014
1519b995
KP		 1015static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1017{
1018 if ((val & PORT_ENABLE) == 0)
1019 return false;
1020
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 return false;
1024 } else {
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026 return false;
1027 }
1028 return true;
1029}
1030
1031static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1033{
1034 if ((val & LVDS_PORT_EN) == 0)
1035 return false;
1036
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 return false;
1040 } else {
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042 return false;
1043 }
1044 return true;
1045}
1046
1047static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1049{
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1051 return false;
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 return false;
1055 } else {
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057 return false;
1058 }
1059 return true;
1060}
1061
291906f1 1062static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1063 enum pipe pipe, int reg, u32 port_sel)
291906f1 1064{
47a05eca 1065 u32 val = I915_READ(reg);
4e634389 1066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1068 reg, pipe_name(pipe));
291906f1
JB		 1069}
1070
1071static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1073{
47a05eca 1074 u32 val = I915_READ(reg);
1519b995 1075 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1076 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1077 reg, pipe_name(pipe));
291906f1
JB		 1078}
1079
1080static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe)
1082{
1083 int reg;
1084 u32 val;
291906f1 1085
f0575e92
KP		 1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1089
1090 reg = PCH_ADPA;
1091 val = I915_READ(reg);
1519b995 1092 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1093 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1094 pipe_name(pipe));
291906f1
JB		 1095
1096 reg = PCH_LVDS;
1097 val = I915_READ(reg);
1519b995 1098 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1100 pipe_name(pipe));
291906f1
JB		 1101
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105}
1106
63d7bbe9
JB		 1107/**
1108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1111 *
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1115 *
1116 * Note! This is for pre-ILK only.
1117 */
1118static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119{
1120 int reg;
1121 u32 val;
1122
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1125
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1133
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1142 POSTING_READ(reg);
1143 udelay(150); /* wait for warmup */
1144}
1145
1146/**
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1150 *
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1152 *
1153 * Note! This is for pre-ILK only.
1154 */
1155static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156{
1157 int reg;
1158 u32 val;
1159
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 return;
1163
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1166
1167 reg = DPLL(pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1171 POSTING_READ(reg);
1172}
1173
92f2584a
JB		 1174/**
1175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1178 *
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1181 */
1182static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
4c609cb8
JB		 1188 if (pipe > 1)
1189 return;
1190
92f2584a
JB		 1191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1193
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1196
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1201 POSTING_READ(reg);
1202 udelay(200);
1203}
1204
1205static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
1208 int reg;
1209 u32 val;
1210
4c609cb8
JB		 1211 if (pipe > 1)
1212 return;
1213
92f2584a
JB		 1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226}
1227
040484af
JB		 1228static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1236
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1239
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
e9bcff5c
JB		 1246
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1248 /*
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1251 */
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254 }
040484af
JB		 1255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258}
1259
1260static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg;
1264 u32 val;
1265
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1269
291906f1
JB		 1270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1272
040484af
JB		 1273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1279 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1280}
1281
b24e7179 1282/**
309cfea8 1283 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
040484af 1286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1287 *
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290 *
1291 * @pipe should be %PIPE_A or %PIPE_B.
1292 *
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1294 * returning.
1295 */
040484af
JB		 1296static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297 bool pch_port)
b24e7179
JB		 1298{
1299 int reg;
1300 u32 val;
1301
1302 /*
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1305 * need the check.
1306 */
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1309 else {
1310 if (pch_port) {
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314 }
1315 /* FIXME: assert CPU port conditions for SNB+ */
1316 }
b24e7179
JB		 1317
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
00d70b15
CW		 1320 if (val & PIPECONF_ENABLE)
1321 return;
1322
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1324 intel_wait_for_vblank(dev_priv->dev, pipe);
1325}
1326
1327/**
309cfea8 1328 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1331 *
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334 *
1335 * @pipe should be %PIPE_A or %PIPE_B.
1336 *
1337 * Will wait until the pipe has shut down before returning.
1338 */
1339static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 /*
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1348 */
1349 assert_planes_disabled(dev_priv, pipe);
1350
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353 return;
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
00d70b15
CW		 1357 if ((val & PIPECONF_ENABLE) == 0)
1358 return;
1359
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362}
1363
d74362c9
KP		 1364/*
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1367 */
1368static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane)
1370{
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373}
1374
b24e7179
JB		 1375/**
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1380 *
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1382 */
1383static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1385{
1386 int reg;
1387 u32 val;
1388
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1391
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
00d70b15
CW		 1394 if (val & DISPLAY_PLANE_ENABLE)
1395 return;
1396
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1398 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1399 intel_wait_for_vblank(dev_priv->dev, pipe);
1400}
1401
b24e7179
JB		 1402/**
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1407 *
1408 * Disable @plane; should be an independent operation.
1409 */
1410static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
00d70b15
CW		 1418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419 return;
1420
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1424}
1425
47a05eca 1426static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1427 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1428{
1429 u32 val = I915_READ(reg);
4e634389 1430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1432 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1433 }
47a05eca
JB		 1434}
1435
1436static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1438{
1439 u32 val = I915_READ(reg);
1519b995 1440 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442 reg, pipe);
47a05eca 1443 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1444 }
47a05eca
JB		 1445}
1446
1447/* Disable any ports connected to this transcoder */
1448static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 u32 reg, val;
1452
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
f0575e92
KP		 1456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1459
1460 reg = PCH_ADPA;
1461 val = I915_READ(reg);
1519b995 1462 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465 reg = PCH_LVDS;
1466 val = I915_READ(reg);
1519b995
KP		 1467 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470 POSTING_READ(reg);
1471 udelay(100);
1472 }
1473
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1477}
1478
43a9539f
CW		 1479static void i8xx_disable_fbc(struct drm_device *dev)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 fbc_ctl;
1483
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1487 return;
1488
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1495 return;
1496 }
1497
1498 DRM_DEBUG_KMS("disabled FBC\n");
1499}
1500
80824003
JB		 1501static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502{
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1507 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1509 int cfb_pitch;
80824003
JB		 1510 int plane, i;
1511 u32 fbc_ctl, fbc_ctl2;
1512
016b9b61
CW		 1513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
80824003
JB		 1516
1517 /* FBC_CTL wants 64B units */
016b9b61
CW		 1518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1520
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525 /* Set it up... */
de568510
CW		 1526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527 fbc_ctl2 |= plane;
80824003
JB		 1528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531 /* enable it... */
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1533 if (IS_I945GM(dev))
49677901 1534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1537 fbc_ctl |= obj->fence_reg;
80824003
JB		 1538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
016b9b61
CW		 1540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1542}
1543
ee5382ae 1544static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1545{
80824003
JB		 1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549}
1550
74dff282
JB		 1551static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1560 unsigned long stall_watermark = 200;
1561 u32 dpfc_ctl;
1562
74dff282 1563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1566
74dff282
JB		 1567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572 /* enable it... */
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
28c97730 1575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1576}
1577
43a9539f 1578static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 u32 dpfc_ctl;
1582
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1588
bed4a673
CW		 1589 DRM_DEBUG_KMS("disabled FBC\n");
1590 }
74dff282
JB		 1591}
1592
ee5382ae 1593static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1594{
74dff282
JB		 1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598}
1599
4efe0708
JB		 1600static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601{
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 blt_ecoskpd;
1604
1605 /* Make sure blitter notifies FBC of writes */
fcca7926 1606 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1617 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1618}
1619
b52eb4dc
ZY		 1620static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621{
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1626 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1629 unsigned long stall_watermark = 200;
1630 u32 dpfc_ctl;
1631
bed4a673 1632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1639
b52eb4dc
ZY		 1640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1645 /* enable it... */
bed4a673 1646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1647
9c04f015
YL		 1648 if (IS_GEN6(dev)) {
1649 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1652 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1653 }
1654
b52eb4dc
ZY		 1655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656}
1657
43a9539f 1658static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1659{
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 u32 dpfc_ctl;
1662
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1668
bed4a673
CW		 1669 DRM_DEBUG_KMS("disabled FBC\n");
1670 }
b52eb4dc
ZY		 1671}
1672
1673static bool ironlake_fbc_enabled(struct drm_device *dev)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678}
1679
ee5382ae
AJ		 1680bool intel_fbc_enabled(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.fbc_enabled)
1685 return false;
1686
1687 return dev_priv->display.fbc_enabled(dev);
1688}
1689
1630fe75
CW		 1690static void intel_fbc_work_fn(struct work_struct *__work)
1691{
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1701 * the prior work.
1702 */
016b9b61 1703 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1704 dev_priv->display.enable_fbc(work->crtc,
1705 work->interval);
1706
016b9b61
CW		 1707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1710 }
1711
1630fe75
CW		 1712 dev_priv->fbc_work = NULL;
1713 }
1714 mutex_unlock(&dev->struct_mutex);
1715
1716 kfree(work);
1717}
1718
1719static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720{
1721 if (dev_priv->fbc_work == NULL)
1722 return;
1723
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1729 */
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1733
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1737 * necessary to run.
1738 */
1739 dev_priv->fbc_work = NULL;
1740}
1741
43a9539f 1742static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1743{
1630fe75
CW		 1744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1747
1748 if (!dev_priv->display.enable_fbc)
1749 return;
1750
1630fe75
CW		 1751 intel_cancel_fbc_work(dev_priv);
1752
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1754 if (work == NULL) {
1755 dev_priv->display.enable_fbc(crtc, interval);
1756 return;
1757 }
1758
1759 work->crtc = crtc;
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764 dev_priv->fbc_work = work;
1765
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
1630fe75
CW		 1773 *
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1778 */
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1780}
1781
1782void intel_disable_fbc(struct drm_device *dev)
1783{
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785
1630fe75
CW		 1786 intel_cancel_fbc_work(dev_priv);
1787
ee5382ae
AJ		 1788 if (!dev_priv->display.disable_fbc)
1789 return;
1790
1791 dev_priv->display.disable_fbc(dev);
016b9b61 1792 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1793}
1794
80824003
JB		 1795/**
1796 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1797 * @dev: the drm_device
80824003
JB		 1798 *
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1804 * - no dual wide
1805 * - framebuffer <= 2048 in width, 1536 in height
1806 *
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1810 * stolen memory.
1811 *
1812 * We need to enable/disable FBC on a global basis.
1813 */
bed4a673 1814static void intel_update_fbc(struct drm_device *dev)
80824003 1815{
80824003 1816 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
80824003 1820 struct intel_framebuffer *intel_fb;
05394f39 1821 struct drm_i915_gem_object *obj;
cd0de039 1822 int enable_fbc;
9c928d16
JB		 1823
1824 DRM_DEBUG_KMS("\n");
80824003
JB		 1825
1826 if (!i915_powersave)
1827 return;
1828
ee5382ae 1829 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1830 return;
1831
80824003
JB		 1832 /*
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
9c928d16 1836 * - more than one pipe is active
80824003
JB		 1837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1840 */
9c928d16 1841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1842 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1843 if (crtc) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846 goto out_disable;
1847 }
1848 crtc = tmp_crtc;
1849 }
9c928d16 1850 }
bed4a673
CW		 1851
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1855 goto out_disable;
1856 }
bed4a673
CW		 1857
1858 intel_crtc = to_intel_crtc(crtc);
1859 fb = crtc->fb;
1860 intel_fb = to_intel_framebuffer(fb);
05394f39 1861 obj = intel_fb->obj;
bed4a673 1862
cd0de039
KP		 1863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866 enable_fbc = 1;
1867 if (INTEL_INFO(dev)->gen <= 5)
1868 enable_fbc = 0;
1869 }
1870 if (!enable_fbc) {
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873 goto out_disable;
1874 }
05394f39 1875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1876 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1877 "compression\n");
b5e50c3f 1878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1879 goto out_disable;
1880 }
bed4a673
CW		 1881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1883 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1884 "disabling\n");
b5e50c3f 1885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1886 goto out_disable;
1887 }
bed4a673
CW		 1888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
28c97730 1890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1892 goto out_disable;
1893 }
bed4a673 1894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1897 goto out_disable;
1898 }
de568510
CW		 1899
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1902 */
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1907 goto out_disable;
1908 }
1909
c924b934
JW		 1910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1912 goto out_disable;
1913
016b9b61
CW		 1914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1918 */
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1922 return;
1923
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1930 *
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1939 * callback.
1940 *
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1947 */
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1950 }
1951
bed4a673 1952 intel_enable_fbc(crtc, 500);
80824003
JB		 1953 return;
1954
1955out_disable:
80824003 1956 /* Multiple disables should be harmless */
a939406f
CW		 1957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1959 intel_disable_fbc(dev);
a939406f 1960 }
80824003
JB		 1961}
1962
127bd2ac 1963int
48b956c5 1964intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1965 struct drm_i915_gem_object *obj,
919926ae 1966 struct intel_ring_buffer *pipelined)
6b95a207 1967{
ce453d81 1968 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1969 u32 alignment;
1970 int ret;
1971
05394f39 1972 switch (obj->tiling_mode) {
6b95a207 1973 case I915_TILING_NONE:
534843da
CW		 1974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
a6c45cf0 1976 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
6b95a207
KH		 1980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
ce453d81 1993 dev_priv->mm.interruptible = false;
2da3b9b9 1994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1995 if (ret)
ce453d81 1996 goto err_interruptible;
6b95a207
KH		 1997
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2002 */
05394f39 2003 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2004 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2005 if (ret)
2006 goto err_unpin;
6b95a207
KH		 2007 }
2008
ce453d81 2009 dev_priv->mm.interruptible = true;
6b95a207 2010 return 0;
48b956c5
CW		 2011
2012err_unpin:
2013 i915_gem_object_unpin(obj);
ce453d81
CW		 2014err_interruptible:
2015 dev_priv->mm.interruptible = true;
48b956c5 2016 return ret;
6b95a207
KH		 2017}
2018
17638cd6
JB		 2019static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020 int x, int y)
81255565
JB		 2021{
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
05394f39 2026 struct drm_i915_gem_object *obj;
81255565
JB		 2027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
81255565 2029 u32 dspcntr;
5eddb70b 2030 u32 reg;
81255565
JB		 2031
2032 switch (plane) {
2033 case 0:
2034 case 1:
2035 break;
2036 default:
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
81255565 2043
5eddb70b
CW		 2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
81255565
JB		 2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2049 case 8:
2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
2052 case 16:
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2055 else
2056 dspcntr |= DISPPLANE_16BPP;
2057 break;
2058 case 24:
2059 case 32:
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061 break;
2062 default:
17638cd6 2063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2064 return -EINVAL;
2065 }
a6c45cf0 2066 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2067 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2068 dspcntr |= DISPPLANE_TILED;
2069 else
2070 dspcntr &= ~DISPPLANE_TILED;
2071 }
2072
5eddb70b 2073 I915_WRITE(reg, dspcntr);
81255565 2074
05394f39 2075 Start = obj->gtt_offset;
81255565
JB		 2076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
4e6cfefc
CW		 2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
5eddb70b 2080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 2081 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2085 } else
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2087 POSTING_READ(reg);
81255565 2088
17638cd6
JB		 2089 return 0;
2090}
2091
2092static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2102 u32 dspcntr;
2103 u32 reg;
2104
2105 switch (plane) {
2106 case 0:
2107 case 1:
27f8227b 2108 case 2:
17638cd6
JB		 2109 break;
2110 default:
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112 return -EINVAL;
2113 }
2114
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2117
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2123 case 8:
2124 dspcntr |= DISPPLANE_8BPP;
2125 break;
2126 case 16:
2127 if (fb->depth != 16)
2128 return -EINVAL;
2129
2130 dspcntr |= DISPPLANE_16BPP;
2131 break;
2132 case 24:
2133 case 32:
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138 else
2139 return -EINVAL;
2140 break;
2141 default:
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143 return -EINVAL;
2144 }
2145
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2148 else
2149 dspcntr &= ~DISPPLANE_TILED;
2150
2151 /* must disable */
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154 I915_WRITE(reg, dspcntr);
2155
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2165 POSTING_READ(reg);
2166
2167 return 0;
2168}
2169
2170/* Assume fb object is pinned & idle & fenced and just update base pointers */
2171static int
2172intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180 if (ret)
2181 return ret;
2182
bed4a673 2183 intel_update_fbc(dev);
3dec0095 2184 intel_increase_pllclock(crtc);
81255565
JB		 2185
2186 return 0;
2187}
2188
5c3b82e2 2189static int
3c4fdcfb
KH		 2190intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
79e53945
JB		 2192{
2193 struct drm_device *dev = crtc->dev;
79e53945
JB		 2194 struct drm_i915_master_private *master_priv;
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2196 int ret;
79e53945
JB		 2197
2198 /* no fb bound */
2199 if (!crtc->fb) {
a5071c2f 2200 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2201 return 0;
2202 }
2203
265db958 2204 switch (intel_crtc->plane) {
5c3b82e2
CW		 2205 case 0:
2206 case 1:
2207 break;
27f8227b
JB		 2208 case 2:
2209 if (IS_IVYBRIDGE(dev))
2210 break;
2211 /* fall through otherwise */
5c3b82e2 2212 default:
a5071c2f 2213 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2214 return -EINVAL;
79e53945
JB		 2215 }
2216
5c3b82e2 2217 mutex_lock(&dev->struct_mutex);
265db958
CW		 2218 ret = intel_pin_and_fence_fb_obj(dev,
2219 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2220 NULL);
5c3b82e2
CW		 2221 if (ret != 0) {
2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2224 return ret;
2225 }
79e53945 2226
265db958 2227 if (old_fb) {
e6c3a2a6 2228 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2230
e6c3a2a6 2231 wait_event(dev_priv->pending_flip_queue,
01eec727 2232 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2233 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
01eec727
CW		 2239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
85345517 2242 */
a8198eea 2243 ret = i915_gem_object_finish_gpu(obj);
01eec727 2244 (void) ret;
265db958
CW		 2245 }
2246
21c74a8e
JW		 2247 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2249 if (ret) {
265db958 2250 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2251 mutex_unlock(&dev->struct_mutex);
a5071c2f 2252 DRM_ERROR("failed to update base address\n");
4e6cfefc 2253 return ret;
79e53945 2254 }
3c4fdcfb 2255
b7f1de28
CW		 2256 if (old_fb) {
2257 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2258 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2259 }
652c393a 2260
5c3b82e2 2261 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2262
2263 if (!dev->primary->master)
5c3b82e2 2264 return 0;
79e53945
JB		 2265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
5c3b82e2 2268 return 0;
79e53945 2269
265db958 2270 if (intel_crtc->pipe) {
79e53945
JB		 2271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2273 } else {
2274 master_priv->sarea_priv->pipeA_x = x;
2275 master_priv->sarea_priv->pipeA_y = y;
79e53945 2276 }
5c3b82e2
CW		 2277
2278 return 0;
79e53945
JB		 2279}
2280
5eddb70b 2281static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2282{
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 u32 dpa_ctl;
2286
28c97730 2287 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2288 dpa_ctl = I915_READ(DP_A);
2289 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291 if (clock < 200000) {
2292 u32 temp;
2293 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294 /* workaround for 160Mhz:
2295 1) program 0x4600c bits 15:0 = 0x8124
2296 2) program 0x46010 bit 0 = 1
2297 3) program 0x46034 bit 24 = 1
2298 4) program 0x64000 bit 14 = 1
2299 */
2300 temp = I915_READ(0x4600c);
2301 temp &= 0xffff0000;
2302 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304 temp = I915_READ(0x46010);
2305 I915_WRITE(0x46010, temp | 1);
2306
2307 temp = I915_READ(0x46034);
2308 I915_WRITE(0x46034, temp | (1 << 24));
2309 } else {
2310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311 }
2312 I915_WRITE(DP_A, dpa_ctl);
2313
5eddb70b 2314 POSTING_READ(DP_A);
32f9d658
ZW		 2315 udelay(500);
2316}
2317
5e84e1a4
ZW		 2318static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 u32 reg, temp;
2325
2326 /* enable normal train */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
61e499bf 2329 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2335 }
5e84e1a4
ZW		 2336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
357555c0
JB		 2352
2353 /* IVB wants error correction enabled */
2354 if (IS_IVYBRIDGE(dev))
2355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2357}
2358
291427f5
JB		 2359static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364 flags |= FDI_PHASE_SYNC_OVR(pipe);
2365 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366 flags |= FDI_PHASE_SYNC_EN(pipe);
2367 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368 POSTING_READ(SOUTH_CHICKEN1);
2369}
2370
8db9d77b
ZW		 2371/* The FDI link training functions for ILK/Ibexpeak. */
2372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373{
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
0fc932b8 2378 int plane = intel_crtc->plane;
5eddb70b 2379 u32 reg, temp, tries;
8db9d77b 2380
0fc932b8
JB		 2381 /* FDI needs bits from pipe & plane first */
2382 assert_pipe_enabled(dev_priv, pipe);
2383 assert_plane_enabled(dev_priv, plane);
2384
e1a44743
AJ		 2385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386 for train result */
5eddb70b
CW		 2387 reg = FDI_RX_IMR(pipe);
2388 temp = I915_READ(reg);
e1a44743
AJ		 2389 temp &= ~FDI_RX_SYMBOL_LOCK;
2390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2391 I915_WRITE(reg, temp);
2392 I915_READ(reg);
e1a44743
AJ		 2393 udelay(150);
2394
8db9d77b 2395 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
77ffb597
AJ		 2398 temp &= ~(7 << 19);
2399 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2403
5eddb70b
CW		 2404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
8db9d77b
ZW		 2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410 POSTING_READ(reg);
8db9d77b
ZW		 2411 udelay(150);
2412
5b2adf89 2413 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2414 if (HAS_PCH_IBX(dev)) {
2415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417 FDI_RX_PHASE_SYNC_POINTER_EN);
2418 }
5b2adf89 2419
5eddb70b 2420 reg = FDI_RX_IIR(pipe);
e1a44743 2421 for (tries = 0; tries < 5; tries++) {
5eddb70b 2422 temp = I915_READ(reg);
8db9d77b
ZW		 2423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2428 break;
2429 }
8db9d77b 2430 }
e1a44743 2431 if (tries == 5)
5eddb70b 2432 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2433
2434 /* Train 2 */
5eddb70b
CW		 2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2439 I915_WRITE(reg, temp);
8db9d77b 2440
5eddb70b
CW		 2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2445 I915_WRITE(reg, temp);
8db9d77b 2446
5eddb70b
CW		 2447 POSTING_READ(reg);
2448 udelay(150);
8db9d77b 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2463
2464 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2465
8db9d77b
ZW		 2466}
2467
0206e353 2468static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473};
2474
2475/* The FDI link training functions for SNB/Cougarpoint. */
2476static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
5eddb70b 2482 u32 reg, temp, i;
8db9d77b 2483
e1a44743
AJ		 2484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
5eddb70b
CW		 2486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
e1a44743
AJ		 2488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2506
5eddb70b
CW		 2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 }
5eddb70b
CW		 2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(150);
2520
291427f5
JB		 2521 if (HAS_PCH_CPT(dev))
2522 cpt_phase_pointer_enable(dev, pipe);
2523
0206e353 2524 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
8db9d77b
ZW		 2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2529 I915_WRITE(reg, temp);
2530
2531 POSTING_READ(reg);
8db9d77b
ZW		 2532 udelay(500);
2533
5eddb70b
CW		 2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 break;
2542 }
2543 }
2544 if (i == 4)
5eddb70b 2545 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2546
2547 /* Train 2 */
5eddb70b
CW		 2548 reg = FDI_TX_CTL(pipe);
2549 temp = I915_READ(reg);
8db9d77b
ZW		 2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 if (IS_GEN6(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 /* SNB-B */
2555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 }
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 if (HAS_PCH_CPT(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 } else {
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 }
5eddb70b
CW		 2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
8db9d77b
ZW		 2571 udelay(150);
2572
0206e353 2573 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2578 I915_WRITE(reg, temp);
2579
2580 POSTING_READ(reg);
8db9d77b
ZW		 2581 udelay(500);
2582
5eddb70b
CW		 2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2589 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 break;
2591 }
2592 }
2593 if (i == 4)
5eddb70b 2594 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2595
2596 DRM_DEBUG_KMS("FDI train done.\n");
2597}
2598
357555c0
JB		 2599/* Manual link training for Ivy Bridge A0 parts */
2600static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601{
2602 struct drm_device *dev = crtc->dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605 int pipe = intel_crtc->pipe;
2606 u32 reg, temp, i;
2607
2608 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 for train result */
2610 reg = FDI_RX_IMR(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_RX_SYMBOL_LOCK;
2613 temp &= ~FDI_RX_BIT_LOCK;
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~(7 << 19);
2623 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2628 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2629 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2636 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
291427f5
JB		 2642 if (HAS_PCH_CPT(dev))
2643 cpt_phase_pointer_enable(dev, pipe);
2644
0206e353 2645 for (i = 0; i < 4; i++) {
357555c0
JB		 2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659 if (temp & FDI_RX_BIT_LOCK ||
2660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 break;
2664 }
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
0206e353 2687 for (i = 0; i < 4; i++) {
357555c0
JB		 2688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691 temp |= snb_b_fdi_train_param[i];
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(500);
2696
2697 reg = FDI_RX_IIR(pipe);
2698 temp = I915_READ(reg);
2699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701 if (temp & FDI_RX_SYMBOL_LOCK) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711}
2712
2713static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2714{
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
5eddb70b 2719 u32 reg, temp;
79e53945 2720
c64e311e 2721 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2722 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2724
c98e9dcf 2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2729 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
c98e9dcf
JB		 2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
c98e9dcf
JB		 2741 udelay(200);
2742
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
c98e9dcf 2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749 POSTING_READ(reg);
c98e9dcf 2750 udelay(100);
6be4a607 2751 }
0e23b99d
JB		 2752}
2753
291427f5
JB		 2754static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755{
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1);
2764}
0fc932b8
JB		 2765static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766{
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777 POSTING_READ(reg);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(0x7 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2789 if (HAS_PCH_IBX(dev)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2791 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2793 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2794 } else if (HAS_PCH_CPT(dev)) {
2795 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2796 }
0fc932b8
JB		 2797
2798 /* still set train pattern 1 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 if (HAS_PCH_CPT(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810 } else {
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 }
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp &= ~(0x07 << 16);
2816 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817 I915_WRITE(reg, temp);
2818
2819 POSTING_READ(reg);
2820 udelay(100);
2821}
2822
6b383a7f
CW		 2823/*
2824 * When we disable a pipe, we need to clear any pending scanline wait events
2825 * to avoid hanging the ring, which we assume we are waiting on.
2826 */
2827static void intel_clear_scanline_wait(struct drm_device *dev)
2828{
2829 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2830 struct intel_ring_buffer *ring;
6b383a7f
CW		 2831 u32 tmp;
2832
2833 if (IS_GEN2(dev))
2834 /* Can't break the hang on i8xx */
2835 return;
2836
1ec14ad3 2837 ring = LP_RING(dev_priv);
8168bd48
CW		 2838 tmp = I915_READ_CTL(ring);
2839 if (tmp & RING_WAIT)
2840 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2841}
2842
e6c3a2a6
CW		 2843static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844{
05394f39 2845 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2846 struct drm_i915_private *dev_priv;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
05394f39 2851 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2852 dev_priv = crtc->dev->dev_private;
2853 wait_event(dev_priv->pending_flip_queue,
05394f39 2854 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2855}
2856
040484af
JB		 2857static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858{
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_mode_config *mode_config = &dev->mode_config;
2861 struct intel_encoder *encoder;
2862
2863 /*
2864 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865 * must be driven by its own crtc; no sharing is possible.
2866 */
2867 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868 if (encoder->base.crtc != crtc)
2869 continue;
2870
2871 switch (encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 if (!intel_encoder_is_pch_edp(&encoder->base))
2874 return false;
2875 continue;
2876 }
2877 }
2878
2879 return true;
2880}
2881
f67a559d
JB		 2882/*
2883 * Enable PCH resources required for PCH ports:
2884 * - PCH PLLs
2885 * - FDI training & RX/TX
2886 * - update transcoder timings
2887 * - DP transcoding bits
2888 * - transcoder
2889 */
2890static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
4b645f14 2896 u32 reg, temp, transc_sel;
2c07245f 2897
c98e9dcf 2898 /* For PCH output, training FDI link */
674cf967 2899 dev_priv->display.fdi_link_train(crtc);
2c07245f 2900
92f2584a 2901 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2902
c98e9dcf 2903 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2904 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2905 TRANSC_DPLLB_SEL;
2906
c98e9dcf
JB		 2907 /* Be sure PCH DPLL SEL is set */
2908 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2909 if (pipe == 0) {
2910 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2911 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2912 } else if (pipe == 1) {
2913 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2914 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2915 } else if (pipe == 2) {
2916 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2917 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2918 }
c98e9dcf 2919 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2920 }
5eddb70b 2921
d9b6cb56
JB		 2922 /* set transcoder timing, panel must allow it */
2923 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2924 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2925 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2926 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2927
5eddb70b
CW		 2928 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2929 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2930 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2931
5e84e1a4
ZW		 2932 intel_fdi_normal_train(crtc);
2933
c98e9dcf
JB		 2934 /* For PCH DP, enable TRANS_DP_CTL */
2935 if (HAS_PCH_CPT(dev) &&
2936 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2937 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2938 reg = TRANS_DP_CTL(pipe);
2939 temp = I915_READ(reg);
2940 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2941 TRANS_DP_SYNC_MASK |
2942 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2943 temp |= (TRANS_DP_OUTPUT_ENABLE |
2944 TRANS_DP_ENH_FRAMING);
9325c9f0 2945 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2946
2947 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2948 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2949 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2950 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2951
2952 switch (intel_trans_dp_port_sel(crtc)) {
2953 case PCH_DP_B:
5eddb70b 2954 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2955 break;
2956 case PCH_DP_C:
5eddb70b 2957 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2958 break;
2959 case PCH_DP_D:
5eddb70b 2960 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2961 break;
2962 default:
2963 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2964 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2965 break;
32f9d658 2966 }
2c07245f 2967
5eddb70b 2968 I915_WRITE(reg, temp);
6be4a607 2969 }
b52eb4dc 2970
040484af 2971 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2972}
2973
d4270e57
JB		 2974void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2975{
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2978 u32 temp;
2979
2980 temp = I915_READ(dslreg);
2981 udelay(500);
2982 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2983 /* Without this, mode sets may fail silently on FDI */
2984 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2985 udelay(250);
2986 I915_WRITE(tc2reg, 0);
2987 if (wait_for(I915_READ(dslreg) != temp, 5))
2988 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2989 }
2990}
2991
f67a559d
JB		 2992static void ironlake_crtc_enable(struct drm_crtc *crtc)
2993{
2994 struct drm_device *dev = crtc->dev;
2995 struct drm_i915_private *dev_priv = dev->dev_private;
2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997 int pipe = intel_crtc->pipe;
2998 int plane = intel_crtc->plane;
2999 u32 temp;
3000 bool is_pch_port;
3001
3002 if (intel_crtc->active)
3003 return;
3004
3005 intel_crtc->active = true;
3006 intel_update_watermarks(dev);
3007
3008 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3009 temp = I915_READ(PCH_LVDS);
3010 if ((temp & LVDS_PORT_EN) == 0)
3011 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3012 }
3013
3014 is_pch_port = intel_crtc_driving_pch(crtc);
3015
3016 if (is_pch_port)
357555c0 3017 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3018 else
3019 ironlake_fdi_disable(crtc);
3020
3021 /* Enable panel fitting for LVDS */
3022 if (dev_priv->pch_pf_size &&
3023 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3024 /* Force use of hard-coded filter coefficients
3025 * as some pre-programmed values are broken,
3026 * e.g. x201.
3027 */
9db4a9c7
JB		 3028 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3029 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3030 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3031 }
3032
9c54c0dd
JB		 3033 /*
3034 * On ILK+ LUT must be loaded before the pipe is running but with
3035 * clocks enabled
3036 */
3037 intel_crtc_load_lut(crtc);
3038
f67a559d
JB		 3039 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3040 intel_enable_plane(dev_priv, plane, pipe);
3041
3042 if (is_pch_port)
3043 ironlake_pch_enable(crtc);
c98e9dcf 3044
d1ebd816 3045 mutex_lock(&dev->struct_mutex);
bed4a673 3046 intel_update_fbc(dev);
d1ebd816
BW		 3047 mutex_unlock(&dev->struct_mutex);
3048
6b383a7f 3049 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3050}
3051
3052static void ironlake_crtc_disable(struct drm_crtc *crtc)
3053{
3054 struct drm_device *dev = crtc->dev;
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057 int pipe = intel_crtc->pipe;
3058 int plane = intel_crtc->plane;
5eddb70b 3059 u32 reg, temp;
b52eb4dc 3060
f7abfe8b
CW		 3061 if (!intel_crtc->active)
3062 return;
3063
e6c3a2a6 3064 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3065 drm_vblank_off(dev, pipe);
6b383a7f 3066 intel_crtc_update_cursor(crtc, false);
5eddb70b 3067
b24e7179 3068 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3069
973d04f9
CW		 3070 if (dev_priv->cfb_plane == plane)
3071 intel_disable_fbc(dev);
2c07245f 3072
b24e7179 3073 intel_disable_pipe(dev_priv, pipe);
32f9d658 3074
6be4a607 3075 /* Disable PF */
9db4a9c7
JB		 3076 I915_WRITE(PF_CTL(pipe), 0);
3077 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3078
0fc932b8 3079 ironlake_fdi_disable(crtc);
2c07245f 3080
47a05eca
JB		 3081 /* This is a horrible layering violation; we should be doing this in
3082 * the connector/encoder ->prepare instead, but we don't always have
3083 * enough information there about the config to know whether it will
3084 * actually be necessary or just cause undesired flicker.
3085 */
3086 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3087
040484af 3088 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3089
6be4a607
JB		 3090 if (HAS_PCH_CPT(dev)) {
3091 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3092 reg = TRANS_DP_CTL(pipe);
3093 temp = I915_READ(reg);
3094 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3095 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607
JB		 3097
3098 /* disable DPLL_SEL */
3099 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3100 switch (pipe) {
3101 case 0:
d64311ab 3102 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3103 break;
3104 case 1:
6be4a607 3105 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3106 break;
3107 case 2:
4b645f14 3108 /* C shares PLL A or B */
d64311ab 3109 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3110 break;
3111 default:
3112 BUG(); /* wtf */
3113 }
6be4a607 3114 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3115 }
e3421a18 3116
6be4a607 3117 /* disable PCH DPLL */
4b645f14
JB		 3118 if (!intel_crtc->no_pll)
3119 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3120
6be4a607 3121 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3122 reg = FDI_RX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3125
6be4a607 3126 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3127 reg = FDI_TX_CTL(pipe);
3128 temp = I915_READ(reg);
3129 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3130
3131 POSTING_READ(reg);
6be4a607 3132 udelay(100);
8db9d77b 3133
5eddb70b
CW		 3134 reg = FDI_RX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3137
6be4a607 3138 /* Wait for the clocks to turn off. */
5eddb70b 3139 POSTING_READ(reg);
6be4a607 3140 udelay(100);
6b383a7f 3141
f7abfe8b 3142 intel_crtc->active = false;
6b383a7f 3143 intel_update_watermarks(dev);
d1ebd816
BW		 3144
3145 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3146 intel_update_fbc(dev);
3147 intel_clear_scanline_wait(dev);
d1ebd816 3148 mutex_unlock(&dev->struct_mutex);
6be4a607 3149}
1b3c7a47 3150
6be4a607
JB		 3151static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3152{
3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154 int pipe = intel_crtc->pipe;
3155 int plane = intel_crtc->plane;
8db9d77b 3156
6be4a607
JB		 3157 /* XXX: When our outputs are all unaware of DPMS modes other than off
3158 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3159 */
3160 switch (mode) {
3161 case DRM_MODE_DPMS_ON:
3162 case DRM_MODE_DPMS_STANDBY:
3163 case DRM_MODE_DPMS_SUSPEND:
3164 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3165 ironlake_crtc_enable(crtc);
3166 break;
1b3c7a47 3167
6be4a607
JB		 3168 case DRM_MODE_DPMS_OFF:
3169 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3170 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3171 break;
3172 }
3173}
3174
02e792fb
DV		 3175static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3176{
02e792fb 3177 if (!enable && intel_crtc->overlay) {
23f09ce3 3178 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3179 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3180
23f09ce3 3181 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3182 dev_priv->mm.interruptible = false;
3183 (void) intel_overlay_switch_off(intel_crtc->overlay);
3184 dev_priv->mm.interruptible = true;
23f09ce3 3185 mutex_unlock(&dev->struct_mutex);
02e792fb 3186 }
02e792fb 3187
5dcdbcb0
CW		 3188 /* Let userspace switch the overlay on again. In most cases userspace
3189 * has to recompute where to put it anyway.
3190 */
02e792fb
DV		 3191}
3192
0b8765c6 3193static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3194{
3195 struct drm_device *dev = crtc->dev;
79e53945
JB		 3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198 int pipe = intel_crtc->pipe;
80824003 3199 int plane = intel_crtc->plane;
79e53945 3200
f7abfe8b
CW		 3201 if (intel_crtc->active)
3202 return;
3203
3204 intel_crtc->active = true;
6b383a7f
CW		 3205 intel_update_watermarks(dev);
3206
63d7bbe9 3207 intel_enable_pll(dev_priv, pipe);
040484af 3208 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3209 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3210
0b8765c6 3211 intel_crtc_load_lut(crtc);
bed4a673 3212 intel_update_fbc(dev);
79e53945 3213
0b8765c6
JB		 3214 /* Give the overlay scaler a chance to enable if it's on this pipe */
3215 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3216 intel_crtc_update_cursor(crtc, true);
0b8765c6 3217}
79e53945 3218
0b8765c6
JB		 3219static void i9xx_crtc_disable(struct drm_crtc *crtc)
3220{
3221 struct drm_device *dev = crtc->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224 int pipe = intel_crtc->pipe;
3225 int plane = intel_crtc->plane;
b690e96c 3226
f7abfe8b
CW		 3227 if (!intel_crtc->active)
3228 return;
3229
0b8765c6 3230 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3231 intel_crtc_wait_for_pending_flips(crtc);
3232 drm_vblank_off(dev, pipe);
0b8765c6 3233 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3234 intel_crtc_update_cursor(crtc, false);
0b8765c6 3235
973d04f9
CW		 3236 if (dev_priv->cfb_plane == plane)
3237 intel_disable_fbc(dev);
79e53945 3238
b24e7179 3239 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3240 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3241 intel_disable_pll(dev_priv, pipe);
0b8765c6 3242
f7abfe8b 3243 intel_crtc->active = false;
6b383a7f
CW		 3244 intel_update_fbc(dev);
3245 intel_update_watermarks(dev);
3246 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3247}
3248
3249static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3250{
3251 /* XXX: When our outputs are all unaware of DPMS modes other than off
3252 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3253 */
3254 switch (mode) {
3255 case DRM_MODE_DPMS_ON:
3256 case DRM_MODE_DPMS_STANDBY:
3257 case DRM_MODE_DPMS_SUSPEND:
3258 i9xx_crtc_enable(crtc);
3259 break;
3260 case DRM_MODE_DPMS_OFF:
3261 i9xx_crtc_disable(crtc);
79e53945
JB		 3262 break;
3263 }
2c07245f
ZW		 3264}
3265
3266/**
3267 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3268 */
3269static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3270{
3271 struct drm_device *dev = crtc->dev;
e70236a8 3272 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3273 struct drm_i915_master_private *master_priv;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275 int pipe = intel_crtc->pipe;
3276 bool enabled;
3277
032d2a0d
CW		 3278 if (intel_crtc->dpms_mode == mode)
3279 return;
3280
65655d4a 3281 intel_crtc->dpms_mode = mode;
debcaddc 3282
e70236a8 3283 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3284
3285 if (!dev->primary->master)
3286 return;
3287
3288 master_priv = dev->primary->master->driver_priv;
3289 if (!master_priv->sarea_priv)
3290 return;
3291
3292 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3293
3294 switch (pipe) {
3295 case 0:
3296 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3297 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3298 break;
3299 case 1:
3300 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3301 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3302 break;
3303 default:
9db4a9c7 3304 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3305 break;
3306 }
79e53945
JB		 3307}
3308
cdd59983
CW		 3309static void intel_crtc_disable(struct drm_crtc *crtc)
3310{
3311 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3312 struct drm_device *dev = crtc->dev;
3313
3314 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3315
3316 if (crtc->fb) {
3317 mutex_lock(&dev->struct_mutex);
3318 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3319 mutex_unlock(&dev->struct_mutex);
3320 }
3321}
3322
7e7d76c3
JB		 3323/* Prepare for a mode set.
3324 *
3325 * Note we could be a lot smarter here. We need to figure out which outputs
3326 * will be enabled, which disabled (in short, how the config will changes)
3327 * and perform the minimum necessary steps to accomplish that, e.g. updating
3328 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3329 * panel fitting is in the proper state, etc.
3330 */
3331static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3332{
7e7d76c3 3333 i9xx_crtc_disable(crtc);
79e53945
JB		 3334}
3335
7e7d76c3 3336static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3337{
7e7d76c3 3338 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3339}
3340
3341static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3342{
7e7d76c3 3343 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3344}
3345
3346static void ironlake_crtc_commit(struct drm_crtc *crtc)
3347{
7e7d76c3 3348 ironlake_crtc_enable(crtc);
79e53945
JB		 3349}
3350
0206e353 3351void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3352{
3353 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3354 /* lvds has its own version of prepare see intel_lvds_prepare */
3355 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3356}
3357
0206e353 3358void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3359{
3360 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3361 struct drm_device *dev = encoder->dev;
3362 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3363 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3364
79e53945
JB		 3365 /* lvds has its own version of commit see intel_lvds_commit */
3366 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3367
3368 if (HAS_PCH_CPT(dev))
3369 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3370}
3371
ea5b213a
CW		 3372void intel_encoder_destroy(struct drm_encoder *encoder)
3373{
4ef69c7a 3374 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3375
ea5b213a
CW		 3376 drm_encoder_cleanup(encoder);
3377 kfree(intel_encoder);
3378}
3379
79e53945
JB		 3380static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3381 struct drm_display_mode *mode,
3382 struct drm_display_mode *adjusted_mode)
3383{
2c07245f 3384 struct drm_device *dev = crtc->dev;
89749350 3385
bad720ff 3386 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3387 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3388 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3389 return false;
2c07245f 3390 }
89749350
CW		 3391
3392 /* XXX some encoders set the crtcinfo, others don't.
3393 * Obviously we need some form of conflict resolution here...
3394 */
3395 if (adjusted_mode->crtc_htotal == 0)
3396 drm_mode_set_crtcinfo(adjusted_mode, 0);
3397
79e53945
JB		 3398 return true;
3399}
3400
e70236a8
JB		 3401static int i945_get_display_clock_speed(struct drm_device *dev)
3402{
3403 return 400000;
3404}
79e53945 3405
e70236a8 3406static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3407{
e70236a8
JB		 3408 return 333000;
3409}
79e53945 3410
e70236a8
JB		 3411static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3412{
3413 return 200000;
3414}
79e53945 3415
e70236a8
JB		 3416static int i915gm_get_display_clock_speed(struct drm_device *dev)
3417{
3418 u16 gcfgc = 0;
79e53945 3419
e70236a8
JB		 3420 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3421
3422 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3423 return 133000;
3424 else {
3425 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3426 case GC_DISPLAY_CLOCK_333_MHZ:
3427 return 333000;
3428 default:
3429 case GC_DISPLAY_CLOCK_190_200_MHZ:
3430 return 190000;
79e53945 3431 }
e70236a8
JB		 3432 }
3433}
3434
3435static int i865_get_display_clock_speed(struct drm_device *dev)
3436{
3437 return 266000;
3438}
3439
3440static int i855_get_display_clock_speed(struct drm_device *dev)
3441{
3442 u16 hpllcc = 0;
3443 /* Assume that the hardware is in the high speed state. This
3444 * should be the default.
3445 */
3446 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3447 case GC_CLOCK_133_200:
3448 case GC_CLOCK_100_200:
3449 return 200000;
3450 case GC_CLOCK_166_250:
3451 return 250000;
3452 case GC_CLOCK_100_133:
79e53945 3453 return 133000;
e70236a8 3454 }
79e53945 3455
e70236a8
JB		 3456 /* Shouldn't happen */
3457 return 0;
3458}
79e53945 3459
e70236a8
JB		 3460static int i830_get_display_clock_speed(struct drm_device *dev)
3461{
3462 return 133000;
79e53945
JB		 3463}
3464
2c07245f
ZW		 3465struct fdi_m_n {
3466 u32 tu;
3467 u32 gmch_m;
3468 u32 gmch_n;
3469 u32 link_m;
3470 u32 link_n;
3471};
3472
3473static void
3474fdi_reduce_ratio(u32 *num, u32 *den)
3475{
3476 while (*num > 0xffffff || *den > 0xffffff) {
3477 *num >>= 1;
3478 *den >>= 1;
3479 }
3480}
3481
2c07245f 3482static void
f2b115e6
AJ		 3483ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3484 int link_clock, struct fdi_m_n *m_n)
2c07245f 3485{
2c07245f
ZW		 3486 m_n->tu = 64; /* default size */
3487
22ed1113
CW		 3488 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3489 m_n->gmch_m = bits_per_pixel * pixel_clock;
3490 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3491 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3492
22ed1113
CW		 3493 m_n->link_m = pixel_clock;
3494 m_n->link_n = link_clock;
2c07245f
ZW		 3495 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3496}
3497
3498
7662c8bd
SL		 3499struct intel_watermark_params {
3500 unsigned long fifo_size;
3501 unsigned long max_wm;
3502 unsigned long default_wm;
3503 unsigned long guard_size;
3504 unsigned long cacheline_size;
3505};
3506
f2b115e6 3507/* Pineview has different values for various configs */
d210246a 3508static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3509 PINEVIEW_DISPLAY_FIFO,
3510 PINEVIEW_MAX_WM,
3511 PINEVIEW_DFT_WM,
3512 PINEVIEW_GUARD_WM,
3513 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3514};
d210246a 3515static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3516 PINEVIEW_DISPLAY_FIFO,
3517 PINEVIEW_MAX_WM,
3518 PINEVIEW_DFT_HPLLOFF_WM,
3519 PINEVIEW_GUARD_WM,
3520 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3521};
d210246a 3522static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3523 PINEVIEW_CURSOR_FIFO,
3524 PINEVIEW_CURSOR_MAX_WM,
3525 PINEVIEW_CURSOR_DFT_WM,
3526 PINEVIEW_CURSOR_GUARD_WM,
3527 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3528};
d210246a 3529static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3530 PINEVIEW_CURSOR_FIFO,
3531 PINEVIEW_CURSOR_MAX_WM,
3532 PINEVIEW_CURSOR_DFT_WM,
3533 PINEVIEW_CURSOR_GUARD_WM,
3534 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3535};
d210246a 3536static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3537 G4X_FIFO_SIZE,
3538 G4X_MAX_WM,
3539 G4X_MAX_WM,
3540 2,
3541 G4X_FIFO_LINE_SIZE,
3542};
d210246a 3543static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3544 I965_CURSOR_FIFO,
3545 I965_CURSOR_MAX_WM,
3546 I965_CURSOR_DFT_WM,
3547 2,
3548 G4X_FIFO_LINE_SIZE,
3549};
d210246a 3550static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3551 I965_CURSOR_FIFO,
3552 I965_CURSOR_MAX_WM,
3553 I965_CURSOR_DFT_WM,
3554 2,
3555 I915_FIFO_LINE_SIZE,
3556};
d210246a 3557static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3558 I945_FIFO_SIZE,
7662c8bd
SL		 3559 I915_MAX_WM,
3560 1,
dff33cfc
JB		 3561 2,
3562 I915_FIFO_LINE_SIZE
7662c8bd 3563};
d210246a 3564static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3565 I915_FIFO_SIZE,
7662c8bd
SL		 3566 I915_MAX_WM,
3567 1,
dff33cfc 3568 2,
7662c8bd
SL		 3569 I915_FIFO_LINE_SIZE
3570};
d210246a 3571static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3572 I855GM_FIFO_SIZE,
3573 I915_MAX_WM,
3574 1,
dff33cfc 3575 2,
7662c8bd
SL		 3576 I830_FIFO_LINE_SIZE
3577};
d210246a 3578static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3579 I830_FIFO_SIZE,
3580 I915_MAX_WM,
3581 1,
dff33cfc 3582 2,
7662c8bd
SL		 3583 I830_FIFO_LINE_SIZE
3584};
3585
d210246a 3586static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3587 ILK_DISPLAY_FIFO,
3588 ILK_DISPLAY_MAXWM,
3589 ILK_DISPLAY_DFTWM,
3590 2,
3591 ILK_FIFO_LINE_SIZE
3592};
d210246a 3593static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3594 ILK_CURSOR_FIFO,
3595 ILK_CURSOR_MAXWM,
3596 ILK_CURSOR_DFTWM,
3597 2,
3598 ILK_FIFO_LINE_SIZE
3599};
d210246a 3600static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3601 ILK_DISPLAY_SR_FIFO,
3602 ILK_DISPLAY_MAX_SRWM,
3603 ILK_DISPLAY_DFT_SRWM,
3604 2,
3605 ILK_FIFO_LINE_SIZE
3606};
d210246a 3607static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3608 ILK_CURSOR_SR_FIFO,
3609 ILK_CURSOR_MAX_SRWM,
3610 ILK_CURSOR_DFT_SRWM,
3611 2,
3612 ILK_FIFO_LINE_SIZE
3613};
3614
d210246a 3615static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3616 SNB_DISPLAY_FIFO,
3617 SNB_DISPLAY_MAXWM,
3618 SNB_DISPLAY_DFTWM,
3619 2,
3620 SNB_FIFO_LINE_SIZE
3621};
d210246a 3622static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3623 SNB_CURSOR_FIFO,
3624 SNB_CURSOR_MAXWM,
3625 SNB_CURSOR_DFTWM,
3626 2,
3627 SNB_FIFO_LINE_SIZE
3628};
d210246a 3629static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3630 SNB_DISPLAY_SR_FIFO,
3631 SNB_DISPLAY_MAX_SRWM,
3632 SNB_DISPLAY_DFT_SRWM,
3633 2,
3634 SNB_FIFO_LINE_SIZE
3635};
d210246a 3636static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3637 SNB_CURSOR_SR_FIFO,
3638 SNB_CURSOR_MAX_SRWM,
3639 SNB_CURSOR_DFT_SRWM,
3640 2,
3641 SNB_FIFO_LINE_SIZE
3642};
3643
3644
dff33cfc
JB		 3645/**
3646 * intel_calculate_wm - calculate watermark level
3647 * @clock_in_khz: pixel clock
3648 * @wm: chip FIFO params
3649 * @pixel_size: display pixel size
3650 * @latency_ns: memory latency for the platform
3651 *
3652 * Calculate the watermark level (the level at which the display plane will
3653 * start fetching from memory again). Each chip has a different display
3654 * FIFO size and allocation, so the caller needs to figure that out and pass
3655 * in the correct intel_watermark_params structure.
3656 *
3657 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3658 * on the pixel size. When it reaches the watermark level, it'll start
3659 * fetching FIFO line sized based chunks from memory until the FIFO fills
3660 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3661 * will occur, and a display engine hang could result.
3662 */
7662c8bd 3663static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3664 const struct intel_watermark_params *wm,
3665 int fifo_size,
7662c8bd
SL		 3666 int pixel_size,
3667 unsigned long latency_ns)
3668{
390c4dd4 3669 long entries_required, wm_size;
dff33cfc 3670
d660467c
JB		 3671 /*
3672 * Note: we need to make sure we don't overflow for various clock &
3673 * latency values.
3674 * clocks go from a few thousand to several hundred thousand.
3675 * latency is usually a few thousand
3676 */
3677 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3678 1000;
8de9b311 3679 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3680
bbb0aef5 3681 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3682
d210246a 3683 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3684
bbb0aef5 3685 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3686
390c4dd4
JB		 3687 /* Don't promote wm_size to unsigned... */
3688 if (wm_size > (long)wm->max_wm)
7662c8bd 3689 wm_size = wm->max_wm;
c3add4b6 3690 if (wm_size <= 0)
7662c8bd
SL		 3691 wm_size = wm->default_wm;
3692 return wm_size;
3693}
3694
3695struct cxsr_latency {
3696 int is_desktop;
95534263 3697 int is_ddr3;
7662c8bd
SL		 3698 unsigned long fsb_freq;
3699 unsigned long mem_freq;
3700 unsigned long display_sr;
3701 unsigned long display_hpll_disable;
3702 unsigned long cursor_sr;
3703 unsigned long cursor_hpll_disable;
3704};
3705
403c89ff 3706static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3707 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3708 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3709 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3710 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3711 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3712
3713 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3714 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3715 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3716 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3717 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3718
3719 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3720 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3721 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3722 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3723 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3724
3725 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3726 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3727 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3728 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3729 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3730
3731 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3732 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3733 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3734 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3735 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3736
3737 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3738 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3739 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3740 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3741 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3742};
3743
403c89ff
CW		 3744static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3745 int is_ddr3,
3746 int fsb,
3747 int mem)
7662c8bd 3748{
403c89ff 3749 const struct cxsr_latency *latency;
7662c8bd 3750 int i;
7662c8bd
SL		 3751
3752 if (fsb == 0 || mem == 0)
3753 return NULL;
3754
3755 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3756 latency = &cxsr_latency_table[i];
3757 if (is_desktop == latency->is_desktop &&
95534263 3758 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3759 fsb == latency->fsb_freq && mem == latency->mem_freq)
3760 return latency;
7662c8bd 3761 }
decbbcda 3762
28c97730 3763 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3764
3765 return NULL;
7662c8bd
SL		 3766}
3767
f2b115e6 3768static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3769{
3770 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3771
3772 /* deactivate cxsr */
3e33d94d 3773 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3774}
3775
bcc24fb4
JB		 3776/*
3777 * Latency for FIFO fetches is dependent on several factors:
3778 * - memory configuration (speed, channels)
3779 * - chipset
3780 * - current MCH state
3781 * It can be fairly high in some situations, so here we assume a fairly
3782 * pessimal value. It's a tradeoff between extra memory fetches (if we
3783 * set this value too high, the FIFO will fetch frequently to stay full)
3784 * and power consumption (set it too low to save power and we might see
3785 * FIFO underruns and display "flicker").
3786 *
3787 * A value of 5us seems to be a good balance; safe for very low end
3788 * platforms but not overly aggressive on lower latency configs.
3789 */
69e302a9 3790static const int latency_ns = 5000;
7662c8bd 3791
e70236a8 3792static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3793{
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 uint32_t dsparb = I915_READ(DSPARB);
3796 int size;
3797
8de9b311
CW		 3798 size = dsparb & 0x7f;
3799 if (plane)
3800 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3801
28c97730 3802 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3803 plane ? "B" : "A", size);
dff33cfc
JB		 3804
3805 return size;
3806}
7662c8bd 3807
e70236a8
JB		 3808static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 uint32_t dsparb = I915_READ(DSPARB);
3812 int size;
3813
8de9b311
CW		 3814 size = dsparb & 0x1ff;
3815 if (plane)
3816 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3817 size >>= 1; /* Convert to cachelines */
dff33cfc 3818
28c97730 3819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3820 plane ? "B" : "A", size);
dff33cfc
JB		 3821
3822 return size;
3823}
7662c8bd 3824
e70236a8
JB		 3825static int i845_get_fifo_size(struct drm_device *dev, int plane)
3826{
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 uint32_t dsparb = I915_READ(DSPARB);
3829 int size;
3830
3831 size = dsparb & 0x7f;
3832 size >>= 2; /* Convert to cachelines */
3833
28c97730 3834 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3835 plane ? "B" : "A",
3836 size);
e70236a8
JB		 3837
3838 return size;
3839}
3840
3841static int i830_get_fifo_size(struct drm_device *dev, int plane)
3842{
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 uint32_t dsparb = I915_READ(DSPARB);
3845 int size;
3846
3847 size = dsparb & 0x7f;
3848 size >>= 1; /* Convert to cachelines */
3849
28c97730 3850 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3851 plane ? "B" : "A", size);
e70236a8
JB		 3852
3853 return size;
3854}
3855
d210246a
CW		 3856static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3857{
3858 struct drm_crtc *crtc, *enabled = NULL;
3859
3860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3861 if (crtc->enabled && crtc->fb) {
3862 if (enabled)
3863 return NULL;
3864 enabled = crtc;
3865 }
3866 }
3867
3868 return enabled;
3869}
3870
3871static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3874 struct drm_crtc *crtc;
403c89ff 3875 const struct cxsr_latency *latency;
d4294342
ZY		 3876 u32 reg;
3877 unsigned long wm;
d4294342 3878
403c89ff 3879 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3880 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3881 if (!latency) {
3882 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3883 pineview_disable_cxsr(dev);
3884 return;
3885 }
3886
d210246a
CW		 3887 crtc = single_enabled_crtc(dev);
3888 if (crtc) {
3889 int clock = crtc->mode.clock;
3890 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3891
3892 /* Display SR */
d210246a
CW		 3893 wm = intel_calculate_wm(clock, &pineview_display_wm,
3894 pineview_display_wm.fifo_size,
d4294342
ZY		 3895 pixel_size, latency->display_sr);
3896 reg = I915_READ(DSPFW1);
3897 reg &= ~DSPFW_SR_MASK;
3898 reg |= wm << DSPFW_SR_SHIFT;
3899 I915_WRITE(DSPFW1, reg);
3900 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3901
3902 /* cursor SR */
d210246a
CW		 3903 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3904 pineview_display_wm.fifo_size,
d4294342
ZY		 3905 pixel_size, latency->cursor_sr);
3906 reg = I915_READ(DSPFW3);
3907 reg &= ~DSPFW_CURSOR_SR_MASK;
3908 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3909 I915_WRITE(DSPFW3, reg);
3910
3911 /* Display HPLL off SR */
d210246a
CW		 3912 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3913 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3914 pixel_size, latency->display_hpll_disable);
3915 reg = I915_READ(DSPFW3);
3916 reg &= ~DSPFW_HPLL_SR_MASK;
3917 reg |= wm & DSPFW_HPLL_SR_MASK;
3918 I915_WRITE(DSPFW3, reg);
3919
3920 /* cursor HPLL off SR */
d210246a
CW		 3921 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3922 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3923 pixel_size, latency->cursor_hpll_disable);
3924 reg = I915_READ(DSPFW3);
3925 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3926 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3927 I915_WRITE(DSPFW3, reg);
3928 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3929
3930 /* activate cxsr */
3e33d94d
CW		 3931 I915_WRITE(DSPFW3,
3932 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3933 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3934 } else {
3935 pineview_disable_cxsr(dev);
3936 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3937 }
3938}
3939
417ae147
CW		 3940static bool g4x_compute_wm0(struct drm_device *dev,
3941 int plane,
3942 const struct intel_watermark_params *display,
3943 int display_latency_ns,
3944 const struct intel_watermark_params *cursor,
3945 int cursor_latency_ns,
3946 int *plane_wm,
3947 int *cursor_wm)
3948{
3949 struct drm_crtc *crtc;
3950 int htotal, hdisplay, clock, pixel_size;
3951 int line_time_us, line_count;
3952 int entries, tlb_miss;
3953
3954 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3955 if (crtc->fb == NULL || !crtc->enabled) {
3956 *cursor_wm = cursor->guard_size;
3957 *plane_wm = display->guard_size;
417ae147 3958 return false;
5c72d064 3959 }
417ae147
CW		 3960
3961 htotal = crtc->mode.htotal;
3962 hdisplay = crtc->mode.hdisplay;
3963 clock = crtc->mode.clock;
3964 pixel_size = crtc->fb->bits_per_pixel / 8;
3965
3966 /* Use the small buffer method to calculate plane watermark */
3967 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3968 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3969 if (tlb_miss > 0)
3970 entries += tlb_miss;
3971 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3972 *plane_wm = entries + display->guard_size;
3973 if (*plane_wm > (int)display->max_wm)
3974 *plane_wm = display->max_wm;
3975
3976 /* Use the large buffer method to calculate cursor watermark */
3977 line_time_us = ((htotal * 1000) / clock);
3978 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3979 entries = line_count * 64 * pixel_size;
3980 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3981 if (tlb_miss > 0)
3982 entries += tlb_miss;
3983 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3984 *cursor_wm = entries + cursor->guard_size;
3985 if (*cursor_wm > (int)cursor->max_wm)
3986 *cursor_wm = (int)cursor->max_wm;
3987
3988 return true;
3989}
3990
3991/*
3992 * Check the wm result.
3993 *
3994 * If any calculated watermark values is larger than the maximum value that
3995 * can be programmed into the associated watermark register, that watermark
3996 * must be disabled.
3997 */
3998static bool g4x_check_srwm(struct drm_device *dev,
3999 int display_wm, int cursor_wm,
4000 const struct intel_watermark_params *display,
4001 const struct intel_watermark_params *cursor)
652c393a 4002{
417ae147
CW		 4003 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4004 display_wm, cursor_wm);
652c393a 4005
417ae147 4006 if (display_wm > display->max_wm) {
bbb0aef5 4007 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4008 display_wm, display->max_wm);
4009 return false;
4010 }
0e442c60 4011
417ae147 4012 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4013 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4014 cursor_wm, cursor->max_wm);
4015 return false;
4016 }
0e442c60 4017
417ae147
CW		 4018 if (!(display_wm || cursor_wm)) {
4019 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4020 return false;
4021 }
0e442c60 4022
417ae147
CW		 4023 return true;
4024}
0e442c60 4025
417ae147 4026static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4027 int plane,
4028 int latency_ns,
417ae147
CW		 4029 const struct intel_watermark_params *display,
4030 const struct intel_watermark_params *cursor,
4031 int *display_wm, int *cursor_wm)
4032{
d210246a
CW		 4033 struct drm_crtc *crtc;
4034 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4035 unsigned long line_time_us;
4036 int line_count, line_size;
4037 int small, large;
4038 int entries;
0e442c60 4039
417ae147
CW		 4040 if (!latency_ns) {
4041 *display_wm = *cursor_wm = 0;
4042 return false;
4043 }
0e442c60 4044
d210246a
CW		 4045 crtc = intel_get_crtc_for_plane(dev, plane);
4046 hdisplay = crtc->mode.hdisplay;
4047 htotal = crtc->mode.htotal;
4048 clock = crtc->mode.clock;
4049 pixel_size = crtc->fb->bits_per_pixel / 8;
4050
417ae147
CW		 4051 line_time_us = (htotal * 1000) / clock;
4052 line_count = (latency_ns / line_time_us + 1000) / 1000;
4053 line_size = hdisplay * pixel_size;
0e442c60 4054
417ae147
CW		 4055 /* Use the minimum of the small and large buffer method for primary */
4056 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4057 large = line_count * line_size;
0e442c60 4058
417ae147
CW		 4059 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4060 *display_wm = entries + display->guard_size;
4fe5e611 4061
417ae147
CW		 4062 /* calculate the self-refresh watermark for display cursor */
4063 entries = line_count * pixel_size * 64;
4064 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4065 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4066
417ae147
CW		 4067 return g4x_check_srwm(dev,
4068 *display_wm, *cursor_wm,
4069 display, cursor);
4070}
4fe5e611 4071
7ccb4a53 4072#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4073
4074static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4075{
4076 static const int sr_latency_ns = 12000;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4079 int plane_sr, cursor_sr;
4080 unsigned int enabled = 0;
417ae147
CW		 4081
4082 if (g4x_compute_wm0(dev, 0,
4083 &g4x_wm_info, latency_ns,
4084 &g4x_cursor_wm_info, latency_ns,
4085 &planea_wm, &cursora_wm))
d210246a 4086 enabled |= 1;
417ae147
CW		 4087
4088 if (g4x_compute_wm0(dev, 1,
4089 &g4x_wm_info, latency_ns,
4090 &g4x_cursor_wm_info, latency_ns,
4091 &planeb_wm, &cursorb_wm))
d210246a 4092 enabled |= 2;
417ae147
CW		 4093
4094 plane_sr = cursor_sr = 0;
d210246a
CW		 4095 if (single_plane_enabled(enabled) &&
4096 g4x_compute_srwm(dev, ffs(enabled) - 1,
4097 sr_latency_ns,
417ae147
CW		 4098 &g4x_wm_info,
4099 &g4x_cursor_wm_info,
4100 &plane_sr, &cursor_sr))
0e442c60 4101 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4102 else
4103 I915_WRITE(FW_BLC_SELF,
4104 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4105
308977ac
CW		 4106 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4107 planea_wm, cursora_wm,
4108 planeb_wm, cursorb_wm,
4109 plane_sr, cursor_sr);
0e442c60 4110
417ae147
CW		 4111 I915_WRITE(DSPFW1,
4112 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4113 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4114 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4115 planea_wm);
4116 I915_WRITE(DSPFW2,
4117 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4118 (cursora_wm << DSPFW_CURSORA_SHIFT));
4119 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4120 I915_WRITE(DSPFW3,
4121 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4122 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4123}
4124
d210246a 4125static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4126{
4127 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4128 struct drm_crtc *crtc;
4129 int srwm = 1;
4fe5e611 4130 int cursor_sr = 16;
1dc7546d
JB		 4131
4132 /* Calc sr entries for one plane configs */
d210246a
CW		 4133 crtc = single_enabled_crtc(dev);
4134 if (crtc) {
1dc7546d 4135 /* self-refresh has much higher latency */
69e302a9 4136 static const int sr_latency_ns = 12000;
d210246a
CW		 4137 int clock = crtc->mode.clock;
4138 int htotal = crtc->mode.htotal;
4139 int hdisplay = crtc->mode.hdisplay;
4140 int pixel_size = crtc->fb->bits_per_pixel / 8;
4141 unsigned long line_time_us;
4142 int entries;
1dc7546d 4143
d210246a 4144 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4145
4146 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4147 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4148 pixel_size * hdisplay;
4149 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4150 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4151 if (srwm < 0)
4152 srwm = 1;
1b07e04e 4153 srwm &= 0x1ff;
308977ac
CW		 4154 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4155 entries, srwm);
4fe5e611 4156
d210246a 4157 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4158 pixel_size * 64;
d210246a 4159 entries = DIV_ROUND_UP(entries,
8de9b311 4160 i965_cursor_wm_info.cacheline_size);
4fe5e611 4161 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4162 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4163
4164 if (cursor_sr > i965_cursor_wm_info.max_wm)
4165 cursor_sr = i965_cursor_wm_info.max_wm;
4166
4167 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4168 "cursor %d\n", srwm, cursor_sr);
4169
a6c45cf0 4170 if (IS_CRESTLINE(dev))
adcdbc66 4171 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4172 } else {
4173 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4174 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4175 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4176 & ~FW_BLC_SELF_EN);
1dc7546d 4177 }
7662c8bd 4178
1dc7546d
JB		 4179 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4180 srwm);
7662c8bd
SL		 4181
4182 /* 965 has limitations... */
417ae147
CW		 4183 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4184 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4185 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4186 /* update cursor SR watermark */
4187 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4188}
4189
d210246a 4190static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4191{
4192 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4193 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4194 uint32_t fwater_lo;
4195 uint32_t fwater_hi;
d210246a
CW		 4196 int cwm, srwm = 1;
4197 int fifo_size;
dff33cfc 4198 int planea_wm, planeb_wm;
d210246a 4199 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4200
72557b4f 4201 if (IS_I945GM(dev))
d210246a 4202 wm_info = &i945_wm_info;
a6c45cf0 4203 else if (!IS_GEN2(dev))
d210246a 4204 wm_info = &i915_wm_info;
7662c8bd 4205 else
d210246a
CW		 4206 wm_info = &i855_wm_info;
4207
4208 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4209 crtc = intel_get_crtc_for_plane(dev, 0);
4210 if (crtc->enabled && crtc->fb) {
4211 planea_wm = intel_calculate_wm(crtc->mode.clock,
4212 wm_info, fifo_size,
4213 crtc->fb->bits_per_pixel / 8,
4214 latency_ns);
4215 enabled = crtc;
4216 } else
4217 planea_wm = fifo_size - wm_info->guard_size;
4218
4219 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4220 crtc = intel_get_crtc_for_plane(dev, 1);
4221 if (crtc->enabled && crtc->fb) {
4222 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4223 wm_info, fifo_size,
4224 crtc->fb->bits_per_pixel / 8,
4225 latency_ns);
4226 if (enabled == NULL)
4227 enabled = crtc;
4228 else
4229 enabled = NULL;
4230 } else
4231 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4232
28c97730 4233 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4234
4235 /*
4236 * Overlay gets an aggressive default since video jitter is bad.
4237 */
4238 cwm = 2;
4239
18b2190c
AL		 4240 /* Play safe and disable self-refresh before adjusting watermarks. */
4241 if (IS_I945G(dev) || IS_I945GM(dev))
4242 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4243 else if (IS_I915GM(dev))
4244 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4245
dff33cfc 4246 /* Calc sr entries for one plane configs */
d210246a 4247 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4248 /* self-refresh has much higher latency */
69e302a9 4249 static const int sr_latency_ns = 6000;
d210246a
CW		 4250 int clock = enabled->mode.clock;
4251 int htotal = enabled->mode.htotal;
4252 int hdisplay = enabled->mode.hdisplay;
4253 int pixel_size = enabled->fb->bits_per_pixel / 8;
4254 unsigned long line_time_us;
4255 int entries;
dff33cfc 4256
d210246a 4257 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4258
4259 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4260 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4261 pixel_size * hdisplay;
4262 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4263 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4264 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4265 if (srwm < 0)
4266 srwm = 1;
ee980b80
LP		 4267
4268 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4269 I915_WRITE(FW_BLC_SELF,
4270 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4271 else if (IS_I915GM(dev))
ee980b80 4272 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4273 }
4274
28c97730 4275 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4276 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4277
dff33cfc
JB		 4278 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4279 fwater_hi = (cwm & 0x1f);
4280
4281 /* Set request length to 8 cachelines per fetch */
4282 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4283 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4284
4285 I915_WRITE(FW_BLC, fwater_lo);
4286 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4287
d210246a
CW		 4288 if (HAS_FW_BLC(dev)) {
4289 if (enabled) {
4290 if (IS_I945G(dev) || IS_I945GM(dev))
4291 I915_WRITE(FW_BLC_SELF,
4292 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4293 else if (IS_I915GM(dev))
4294 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4295 DRM_DEBUG_KMS("memory self refresh enabled\n");
4296 } else
4297 DRM_DEBUG_KMS("memory self refresh disabled\n");
4298 }
7662c8bd
SL		 4299}
4300
d210246a 4301static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4302{
4303 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4304 struct drm_crtc *crtc;
4305 uint32_t fwater_lo;
dff33cfc 4306 int planea_wm;
7662c8bd 4307
d210246a
CW		 4308 crtc = single_enabled_crtc(dev);
4309 if (crtc == NULL)
4310 return;
7662c8bd 4311
d210246a
CW		 4312 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4313 dev_priv->display.get_fifo_size(dev, 0),
4314 crtc->fb->bits_per_pixel / 8,
4315 latency_ns);
4316 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4317 fwater_lo |= (3<<8) | planea_wm;
4318
28c97730 4319 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4320
4321 I915_WRITE(FW_BLC, fwater_lo);
4322}
4323
7f8a8569 4324#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4325#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4326
1398261a
YL		 4327/*
4328 * Check the wm result.
4329 *
4330 * If any calculated watermark values is larger than the maximum value that
4331 * can be programmed into the associated watermark register, that watermark
4332 * must be disabled.
1398261a 4333 */
b79d4990
JB		 4334static bool ironlake_check_srwm(struct drm_device *dev, int level,
4335 int fbc_wm, int display_wm, int cursor_wm,
4336 const struct intel_watermark_params *display,
4337 const struct intel_watermark_params *cursor)
1398261a
YL		 4338{
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340
4341 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4342 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4343
4344 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4345 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4346 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4347
4348 /* fbc has it's own way to disable FBC WM */
4349 I915_WRITE(DISP_ARB_CTL,
4350 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4351 return false;
4352 }
4353
b79d4990 4354 if (display_wm > display->max_wm) {
1398261a 4355 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4356 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4357 return false;
4358 }
4359
b79d4990 4360 if (cursor_wm > cursor->max_wm) {
1398261a 4361 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4362 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4363 return false;
4364 }
4365
4366 if (!(fbc_wm || display_wm || cursor_wm)) {
4367 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4368 return false;
4369 }
4370
4371 return true;
4372}
4373
4374/*
4375 * Compute watermark values of WM[1-3],
4376 */
d210246a
CW		 4377static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4378 int latency_ns,
b79d4990
JB		 4379 const struct intel_watermark_params *display,
4380 const struct intel_watermark_params *cursor,
4381 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4382{
d210246a 4383 struct drm_crtc *crtc;
1398261a 4384 unsigned long line_time_us;
d210246a 4385 int hdisplay, htotal, pixel_size, clock;
b79d4990 4386 int line_count, line_size;
1398261a
YL		 4387 int small, large;
4388 int entries;
1398261a
YL		 4389
4390 if (!latency_ns) {
4391 *fbc_wm = *display_wm = *cursor_wm = 0;
4392 return false;
4393 }
4394
d210246a
CW		 4395 crtc = intel_get_crtc_for_plane(dev, plane);
4396 hdisplay = crtc->mode.hdisplay;
4397 htotal = crtc->mode.htotal;
4398 clock = crtc->mode.clock;
4399 pixel_size = crtc->fb->bits_per_pixel / 8;
4400
1398261a
YL		 4401 line_time_us = (htotal * 1000) / clock;
4402 line_count = (latency_ns / line_time_us + 1000) / 1000;
4403 line_size = hdisplay * pixel_size;
4404
4405 /* Use the minimum of the small and large buffer method for primary */
4406 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4407 large = line_count * line_size;
4408
b79d4990
JB		 4409 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4410 *display_wm = entries + display->guard_size;
1398261a
YL		 4411
4412 /*
b79d4990 4413 * Spec says:
1398261a
YL		 4414 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4415 */
4416 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4417
4418 /* calculate the self-refresh watermark for display cursor */
4419 entries = line_count * pixel_size * 64;
b79d4990
JB		 4420 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4421 *cursor_wm = entries + cursor->guard_size;
1398261a 4422
b79d4990
JB		 4423 return ironlake_check_srwm(dev, level,
4424 *fbc_wm, *display_wm, *cursor_wm,
4425 display, cursor);
4426}
4427
d210246a 4428static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4429{
4430 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4431 int fbc_wm, plane_wm, cursor_wm;
4432 unsigned int enabled;
b79d4990
JB		 4433
4434 enabled = 0;
9f405100
CW		 4435 if (g4x_compute_wm0(dev, 0,
4436 &ironlake_display_wm_info,
4437 ILK_LP0_PLANE_LATENCY,
4438 &ironlake_cursor_wm_info,
4439 ILK_LP0_CURSOR_LATENCY,
4440 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4441 I915_WRITE(WM0_PIPEA_ILK,
4442 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4443 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4444 " plane %d, " "cursor: %d\n",
4445 plane_wm, cursor_wm);
d210246a 4446 enabled |= 1;
b79d4990
JB		 4447 }
4448
9f405100
CW		 4449 if (g4x_compute_wm0(dev, 1,
4450 &ironlake_display_wm_info,
4451 ILK_LP0_PLANE_LATENCY,
4452 &ironlake_cursor_wm_info,
4453 ILK_LP0_CURSOR_LATENCY,
4454 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4455 I915_WRITE(WM0_PIPEB_ILK,
4456 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4457 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4458 " plane %d, cursor: %d\n",
4459 plane_wm, cursor_wm);
d210246a 4460 enabled |= 2;
b79d4990
JB		 4461 }
4462
4463 /*
4464 * Calculate and update the self-refresh watermark only when one
4465 * display plane is used.
4466 */
4467 I915_WRITE(WM3_LP_ILK, 0);
4468 I915_WRITE(WM2_LP_ILK, 0);
4469 I915_WRITE(WM1_LP_ILK, 0);
4470
d210246a 4471 if (!single_plane_enabled(enabled))
b79d4990 4472 return;
d210246a 4473 enabled = ffs(enabled) - 1;
b79d4990
JB		 4474
4475 /* WM1 */
d210246a
CW		 4476 if (!ironlake_compute_srwm(dev, 1, enabled,
4477 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4478 &ironlake_display_srwm_info,
4479 &ironlake_cursor_srwm_info,
4480 &fbc_wm, &plane_wm, &cursor_wm))
4481 return;
4482
4483 I915_WRITE(WM1_LP_ILK,
4484 WM1_LP_SR_EN |
4485 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4486 (fbc_wm << WM1_LP_FBC_SHIFT) |
4487 (plane_wm << WM1_LP_SR_SHIFT) |
4488 cursor_wm);
4489
4490 /* WM2 */
d210246a
CW		 4491 if (!ironlake_compute_srwm(dev, 2, enabled,
4492 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4493 &ironlake_display_srwm_info,
4494 &ironlake_cursor_srwm_info,
4495 &fbc_wm, &plane_wm, &cursor_wm))
4496 return;
4497
4498 I915_WRITE(WM2_LP_ILK,
4499 WM2_LP_EN |
4500 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4501 (fbc_wm << WM1_LP_FBC_SHIFT) |
4502 (plane_wm << WM1_LP_SR_SHIFT) |
4503 cursor_wm);
4504
4505 /*
4506 * WM3 is unsupported on ILK, probably because we don't have latency
4507 * data for that power state
4508 */
1398261a
YL		 4509}
4510
d210246a 4511static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4512{
4513 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4514 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4515 int fbc_wm, plane_wm, cursor_wm;
4516 unsigned int enabled;
1398261a
YL		 4517
4518 enabled = 0;
9f405100
CW		 4519 if (g4x_compute_wm0(dev, 0,
4520 &sandybridge_display_wm_info, latency,
4521 &sandybridge_cursor_wm_info, latency,
4522 &plane_wm, &cursor_wm)) {
1398261a
YL		 4523 I915_WRITE(WM0_PIPEA_ILK,
4524 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4525 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4526 " plane %d, " "cursor: %d\n",
4527 plane_wm, cursor_wm);
d210246a 4528 enabled |= 1;
1398261a
YL		 4529 }
4530
9f405100
CW		 4531 if (g4x_compute_wm0(dev, 1,
4532 &sandybridge_display_wm_info, latency,
4533 &sandybridge_cursor_wm_info, latency,
4534 &plane_wm, &cursor_wm)) {
1398261a
YL		 4535 I915_WRITE(WM0_PIPEB_ILK,
4536 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4537 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4538 " plane %d, cursor: %d\n",
4539 plane_wm, cursor_wm);
d210246a 4540 enabled |= 2;
1398261a
YL		 4541 }
4542
d6c892df
JB		 4543 /* IVB has 3 pipes */
4544 if (IS_IVYBRIDGE(dev) &&
4545 g4x_compute_wm0(dev, 2,
4546 &sandybridge_display_wm_info, latency,
4547 &sandybridge_cursor_wm_info, latency,
4548 &plane_wm, &cursor_wm)) {
4549 I915_WRITE(WM0_PIPEC_IVB,
4550 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4551 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4552 " plane %d, cursor: %d\n",
4553 plane_wm, cursor_wm);
4554 enabled |= 3;
4555 }
4556
1398261a
YL		 4557 /*
4558 * Calculate and update the self-refresh watermark only when one
4559 * display plane is used.
4560 *
4561 * SNB support 3 levels of watermark.
4562 *
4563 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4564 * and disabled in the descending order
4565 *
4566 */
4567 I915_WRITE(WM3_LP_ILK, 0);
4568 I915_WRITE(WM2_LP_ILK, 0);
4569 I915_WRITE(WM1_LP_ILK, 0);
4570
d210246a 4571 if (!single_plane_enabled(enabled))
1398261a 4572 return;
d210246a 4573 enabled = ffs(enabled) - 1;
1398261a
YL		 4574
4575 /* WM1 */
d210246a
CW		 4576 if (!ironlake_compute_srwm(dev, 1, enabled,
4577 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4578 &sandybridge_display_srwm_info,
4579 &sandybridge_cursor_srwm_info,
4580 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4581 return;
4582
4583 I915_WRITE(WM1_LP_ILK,
4584 WM1_LP_SR_EN |
4585 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4586 (fbc_wm << WM1_LP_FBC_SHIFT) |
4587 (plane_wm << WM1_LP_SR_SHIFT) |
4588 cursor_wm);
4589
4590 /* WM2 */
d210246a
CW		 4591 if (!ironlake_compute_srwm(dev, 2, enabled,
4592 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4593 &sandybridge_display_srwm_info,
4594 &sandybridge_cursor_srwm_info,
4595 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4596 return;
4597
4598 I915_WRITE(WM2_LP_ILK,
4599 WM2_LP_EN |
4600 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4601 (fbc_wm << WM1_LP_FBC_SHIFT) |
4602 (plane_wm << WM1_LP_SR_SHIFT) |
4603 cursor_wm);
4604
4605 /* WM3 */
d210246a
CW		 4606 if (!ironlake_compute_srwm(dev, 3, enabled,
4607 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4608 &sandybridge_display_srwm_info,
4609 &sandybridge_cursor_srwm_info,
4610 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4611 return;
4612
4613 I915_WRITE(WM3_LP_ILK,
4614 WM3_LP_EN |
4615 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4616 (fbc_wm << WM1_LP_FBC_SHIFT) |
4617 (plane_wm << WM1_LP_SR_SHIFT) |
4618 cursor_wm);
4619}
4620
7662c8bd
SL		 4621/**
4622 * intel_update_watermarks - update FIFO watermark values based on current modes
4623 *
4624 * Calculate watermark values for the various WM regs based on current mode
4625 * and plane configuration.
4626 *
4627 * There are several cases to deal with here:
4628 * - normal (i.e. non-self-refresh)
4629 * - self-refresh (SR) mode
4630 * - lines are large relative to FIFO size (buffer can hold up to 2)
4631 * - lines are small relative to FIFO size (buffer can hold more than 2
4632 * lines), so need to account for TLB latency
4633 *
4634 * The normal calculation is:
4635 * watermark = dotclock * bytes per pixel * latency
4636 * where latency is platform & configuration dependent (we assume pessimal
4637 * values here).
4638 *
4639 * The SR calculation is:
4640 * watermark = (trunc(latency/line time)+1) * surface width *
4641 * bytes per pixel
4642 * where
4643 * line time = htotal / dotclock
fa143215 4644 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4645 * and latency is assumed to be high, as above.
4646 *
4647 * The final value programmed to the register should always be rounded up,
4648 * and include an extra 2 entries to account for clock crossings.
4649 *
4650 * We don't use the sprite, so we can ignore that. And on Crestline we have
4651 * to set the non-SR watermarks to 8.
5eddb70b 4652 */
7662c8bd
SL		 4653static void intel_update_watermarks(struct drm_device *dev)
4654{
e70236a8 4655 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4656
d210246a
CW		 4657 if (dev_priv->display.update_wm)
4658 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4659}
4660
a7615030
CW		 4661static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4662{
72bbe58c
KP		 4663 if (i915_panel_use_ssc >= 0)
4664 return i915_panel_use_ssc != 0;
4665 return dev_priv->lvds_use_ssc
435793df 4666 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4667}
4668
5a354204
JB		 4669/**
4670 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4671 * @crtc: CRTC structure
4672 *
4673 * A pipe may be connected to one or more outputs. Based on the depth of the
4674 * attached framebuffer, choose a good color depth to use on the pipe.
4675 *
4676 * If possible, match the pipe depth to the fb depth. In some cases, this
4677 * isn't ideal, because the connected output supports a lesser or restricted
4678 * set of depths. Resolve that here:
4679 * LVDS typically supports only 6bpc, so clamp down in that case
4680 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4681 * Displays may support a restricted set as well, check EDID and clamp as
4682 * appropriate.
4683 *
4684 * RETURNS:
4685 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4686 * true if they don't match).
4687 */
4688static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4689 unsigned int *pipe_bpp)
4690{
4691 struct drm_device *dev = crtc->dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693 struct drm_encoder *encoder;
4694 struct drm_connector *connector;
4695 unsigned int display_bpc = UINT_MAX, bpc;
4696
4697 /* Walk the encoders & connectors on this crtc, get min bpc */
4698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4699 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4700
4701 if (encoder->crtc != crtc)
4702 continue;
4703
4704 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4705 unsigned int lvds_bpc;
4706
4707 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4708 LVDS_A3_POWER_UP)
4709 lvds_bpc = 8;
4710 else
4711 lvds_bpc = 6;
4712
4713 if (lvds_bpc < display_bpc) {
4714 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4715 display_bpc = lvds_bpc;
4716 }
4717 continue;
4718 }
4719
4720 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4721 /* Use VBT settings if we have an eDP panel */
4722 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4723
4724 if (edp_bpc < display_bpc) {
4725 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4726 display_bpc = edp_bpc;
4727 }
4728 continue;
4729 }
4730
4731 /* Not one of the known troublemakers, check the EDID */
4732 list_for_each_entry(connector, &dev->mode_config.connector_list,
4733 head) {
4734 if (connector->encoder != encoder)
4735 continue;
4736
62ac41a6
JB		 4737 /* Don't use an invalid EDID bpc value */
4738 if (connector->display_info.bpc &&
4739 connector->display_info.bpc < display_bpc) {
5a354204
JB		 4740 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4741 display_bpc = connector->display_info.bpc;
4742 }
4743 }
4744
4745 /*
4746 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4747 * through, clamp it down. (Note: >12bpc will be caught below.)
4748 */
4749 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4750 if (display_bpc > 8 && display_bpc < 12) {
4751 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4752 display_bpc = 12;
4753 } else {
4754 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4755 display_bpc = 8;
4756 }
4757 }
4758 }
4759
4760 /*
4761 * We could just drive the pipe at the highest bpc all the time and
4762 * enable dithering as needed, but that costs bandwidth. So choose
4763 * the minimum value that expresses the full color range of the fb but
4764 * also stays within the max display bpc discovered above.
4765 */
4766
4767 switch (crtc->fb->depth) {
4768 case 8:
4769 bpc = 8; /* since we go through a colormap */
4770 break;
4771 case 15:
4772 case 16:
4773 bpc = 6; /* min is 18bpp */
4774 break;
4775 case 24:
578393cd 4776 bpc = 8;
5a354204
JB		 4777 break;
4778 case 30:
578393cd 4779 bpc = 10;
5a354204
JB		 4780 break;
4781 case 48:
578393cd 4782 bpc = 12;
5a354204
JB		 4783 break;
4784 default:
4785 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4786 bpc = min((unsigned int)8, display_bpc);
4787 break;
4788 }
4789
578393cd
KP		 4790 display_bpc = min(display_bpc, bpc);
4791
5a354204
JB		 4792 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4793 bpc, display_bpc);
4794
578393cd 4795 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4796
4797 return display_bpc != bpc;
4798}
4799
f564048e
EA		 4800static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4801 struct drm_display_mode *mode,
4802 struct drm_display_mode *adjusted_mode,
4803 int x, int y,
4804 struct drm_framebuffer *old_fb)
79e53945
JB		 4805{
4806 struct drm_device *dev = crtc->dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 int pipe = intel_crtc->pipe;
80824003 4810 int plane = intel_crtc->plane;
c751ce4f 4811 int refclk, num_connectors = 0;
652c393a 4812 intel_clock_t clock, reduced_clock;
5eddb70b 4813 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4814 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4815 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4816 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4817 struct intel_encoder *encoder;
d4906093 4818 const intel_limit_t *limit;
5c3b82e2 4819 int ret;
fae14981 4820 u32 temp;
aa9b500d 4821 u32 lvds_sync = 0;
79e53945 4822
5eddb70b
CW		 4823 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4824 if (encoder->base.crtc != crtc)
79e53945
JB		 4825 continue;
4826
5eddb70b 4827 switch (encoder->type) {
79e53945
JB		 4828 case INTEL_OUTPUT_LVDS:
4829 is_lvds = true;
4830 break;
4831 case INTEL_OUTPUT_SDVO:
7d57382e 4832 case INTEL_OUTPUT_HDMI:
79e53945 4833 is_sdvo = true;
5eddb70b 4834 if (encoder->needs_tv_clock)
e2f0ba97 4835 is_tv = true;
79e53945
JB		 4836 break;
4837 case INTEL_OUTPUT_DVO:
4838 is_dvo = true;
4839 break;
4840 case INTEL_OUTPUT_TVOUT:
4841 is_tv = true;
4842 break;
4843 case INTEL_OUTPUT_ANALOG:
4844 is_crt = true;
4845 break;
a4fc5ed6
KP		 4846 case INTEL_OUTPUT_DISPLAYPORT:
4847 is_dp = true;
4848 break;
79e53945 4849 }
43565a06 4850
c751ce4f 4851 num_connectors++;
79e53945
JB		 4852 }
4853
a7615030 4854 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4855 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4856 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4857 refclk / 1000);
a6c45cf0 4858 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4859 refclk = 96000;
4860 } else {
4861 refclk = 48000;
4862 }
4863
d4906093
ML		 4864 /*
4865 * Returns a set of divisors for the desired target clock with the given
4866 * refclk, or FALSE. The returned values represent the clock equation:
4867 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4868 */
1b894b59 4869 limit = intel_limit(crtc, refclk);
d4906093 4870 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4871 if (!ok) {
4872 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4873 return -EINVAL;
79e53945
JB		 4874 }
4875
cda4b7d3 4876 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4877 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4878
ddc9003c
ZY		 4879 if (is_lvds && dev_priv->lvds_downclock_avail) {
4880 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4881 dev_priv->lvds_downclock,
4882 refclk,
4883 &reduced_clock);
18f9ed12
ZY		 4884 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4885 /*
4886 * If the different P is found, it means that we can't
4887 * switch the display clock by using the FP0/FP1.
4888 * In such case we will disable the LVDS downclock
4889 * feature.
4890 */
4891 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4892 "LVDS clock/downclock\n");
18f9ed12
ZY		 4893 has_reduced_clock = 0;
4894 }
652c393a 4895 }
7026d4ac
ZW		 4896 /* SDVO TV has fixed PLL values depend on its clock range,
4897 this mirrors vbios setting. */
4898 if (is_sdvo && is_tv) {
4899 if (adjusted_mode->clock >= 100000
5eddb70b 4900 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4901 clock.p1 = 2;
4902 clock.p2 = 10;
4903 clock.n = 3;
4904 clock.m1 = 16;
4905 clock.m2 = 8;
4906 } else if (adjusted_mode->clock >= 140500
5eddb70b 4907 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4908 clock.p1 = 1;
4909 clock.p2 = 10;
4910 clock.n = 6;
4911 clock.m1 = 12;
4912 clock.m2 = 8;
4913 }
4914 }
4915
f2b115e6 4916 if (IS_PINEVIEW(dev)) {
2177832f 4917 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4918 if (has_reduced_clock)
4919 fp2 = (1 << reduced_clock.n) << 16 |
4920 reduced_clock.m1 << 8 | reduced_clock.m2;
4921 } else {
2177832f 4922 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4923 if (has_reduced_clock)
4924 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4925 reduced_clock.m2;
4926 }
79e53945 4927
929c77fb 4928 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4929
a6c45cf0 4930 if (!IS_GEN2(dev)) {
79e53945
JB		 4931 if (is_lvds)
4932 dpll |= DPLLB_MODE_LVDS;
4933 else
4934 dpll |= DPLLB_MODE_DAC_SERIAL;
4935 if (is_sdvo) {
6c9547ff
CW		 4936 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4937 if (pixel_multiplier > 1) {
4938 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4939 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4940 }
79e53945 4941 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4942 }
929c77fb 4943 if (is_dp)
a4fc5ed6 4944 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4945
4946 /* compute bitmask from p1 value */
f2b115e6
AJ		 4947 if (IS_PINEVIEW(dev))
4948 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4949 else {
2177832f 4950 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4951 if (IS_G4X(dev) && has_reduced_clock)
4952 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4953 }
79e53945
JB		 4954 switch (clock.p2) {
4955 case 5:
4956 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4957 break;
4958 case 7:
4959 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4960 break;
4961 case 10:
4962 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4963 break;
4964 case 14:
4965 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4966 break;
4967 }
929c77fb 4968 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4969 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4970 } else {
4971 if (is_lvds) {
4972 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4973 } else {
4974 if (clock.p1 == 2)
4975 dpll |= PLL_P1_DIVIDE_BY_TWO;
4976 else
4977 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4978 if (clock.p2 == 4)
4979 dpll |= PLL_P2_DIVIDE_BY_4;
4980 }
4981 }
4982
43565a06
KH		 4983 if (is_sdvo && is_tv)
4984 dpll |= PLL_REF_INPUT_TVCLKINBC;
4985 else if (is_tv)
79e53945 4986 /* XXX: just matching BIOS for now */
43565a06 4987 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4988 dpll |= 3;
a7615030 4989 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4991 else
4992 dpll |= PLL_REF_INPUT_DREFCLK;
4993
4994 /* setup pipeconf */
5eddb70b 4995 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4996
4997 /* Set up the display plane register */
4998 dspcntr = DISPPLANE_GAMMA_ENABLE;
4999
f2b115e6 5000 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 5001 enable color space conversion */
929c77fb
EA		 5002 if (pipe == 0)
5003 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5004 else
5005 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5006
a6c45cf0 5007 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5008 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5009 * core speed.
5010 *
5011 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5012 * pipe == 0 check?
5013 */
e70236a8
JB		 5014 if (mode->clock >
5015 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5016 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5017 else
5eddb70b 5018 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5019 }
5020
929c77fb 5021 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5022
28c97730 5023 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5024 drm_mode_debug_printmodeline(mode);
5025
fae14981
EA		 5026 I915_WRITE(FP0(pipe), fp);
5027 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5028
fae14981 5029 POSTING_READ(DPLL(pipe));
c713bb08 5030 udelay(150);
8db9d77b 5031
79e53945
JB		 5032 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5033 * This is an exception to the general rule that mode_set doesn't turn
5034 * things on.
5035 */
5036 if (is_lvds) {
fae14981 5037 temp = I915_READ(LVDS);
5eddb70b 5038 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5039 if (pipe == 1) {
929c77fb 5040 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5041 } else {
929c77fb 5042 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5043 }
a3e17eb8 5044 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5045 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5046 /* Set the B0-B3 data pairs corresponding to whether we're going to
5047 * set the DPLLs for dual-channel mode or not.
5048 */
5049 if (clock.p2 == 7)
5eddb70b 5050 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5051 else
5eddb70b 5052 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5053
5054 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5055 * appropriately here, but we need to look more thoroughly into how
5056 * panels behave in the two modes.
5057 */
929c77fb
EA		 5058 /* set the dithering flag on LVDS as needed */
5059 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5060 if (dev_priv->lvds_dither)
5eddb70b 5061 temp |= LVDS_ENABLE_DITHER;
434ed097 5062 else
5eddb70b 5063 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5064 }
aa9b500d
BF		 5065 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5066 lvds_sync |= LVDS_HSYNC_POLARITY;
5067 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5068 lvds_sync |= LVDS_VSYNC_POLARITY;
5069 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5070 != lvds_sync) {
5071 char flags[2] = "-+";
5072 DRM_INFO("Changing LVDS panel from "
5073 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5074 flags[!(temp & LVDS_HSYNC_POLARITY)],
5075 flags[!(temp & LVDS_VSYNC_POLARITY)],
5076 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5077 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5078 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5079 temp |= lvds_sync;
5080 }
fae14981 5081 I915_WRITE(LVDS, temp);
79e53945 5082 }
434ed097 5083
929c77fb 5084 if (is_dp) {
a4fc5ed6 5085 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5086 }
5087
fae14981 5088 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5089
c713bb08 5090 /* Wait for the clocks to stabilize. */
fae14981 5091 POSTING_READ(DPLL(pipe));
c713bb08 5092 udelay(150);
32f9d658 5093
c713bb08
EA		 5094 if (INTEL_INFO(dev)->gen >= 4) {
5095 temp = 0;
5096 if (is_sdvo) {
5097 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5098 if (temp > 1)
5099 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5100 else
5101 temp = 0;
32f9d658 5102 }
c713bb08
EA		 5103 I915_WRITE(DPLL_MD(pipe), temp);
5104 } else {
5105 /* The pixel multiplier can only be updated once the
5106 * DPLL is enabled and the clocks are stable.
5107 *
5108 * So write it again.
5109 */
fae14981 5110 I915_WRITE(DPLL(pipe), dpll);
79e53945 5111 }
79e53945 5112
5eddb70b 5113 intel_crtc->lowfreq_avail = false;
652c393a 5114 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5115 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5116 intel_crtc->lowfreq_avail = true;
5117 if (HAS_PIPE_CXSR(dev)) {
28c97730 5118 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5119 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5120 }
5121 } else {
fae14981 5122 I915_WRITE(FP1(pipe), fp);
652c393a 5123 if (HAS_PIPE_CXSR(dev)) {
28c97730 5124 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5125 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5126 }
5127 }
5128
734b4157
KH		 5129 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5130 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5131 /* the chip adds 2 halflines automatically */
5132 adjusted_mode->crtc_vdisplay -= 1;
5133 adjusted_mode->crtc_vtotal -= 1;
5134 adjusted_mode->crtc_vblank_start -= 1;
5135 adjusted_mode->crtc_vblank_end -= 1;
5136 adjusted_mode->crtc_vsync_end -= 1;
5137 adjusted_mode->crtc_vsync_start -= 1;
5138 } else
5139 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5140
5eddb70b
CW		 5141 I915_WRITE(HTOTAL(pipe),
5142 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5143 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5144 I915_WRITE(HBLANK(pipe),
5145 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5146 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5147 I915_WRITE(HSYNC(pipe),
5148 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5149 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5150
5151 I915_WRITE(VTOTAL(pipe),
5152 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5153 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5154 I915_WRITE(VBLANK(pipe),
5155 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5156 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5157 I915_WRITE(VSYNC(pipe),
5158 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5159 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5160
5161 /* pipesrc and dspsize control the size that is scaled from,
5162 * which should always be the user's requested size.
79e53945 5163 */
929c77fb
EA		 5164 I915_WRITE(DSPSIZE(plane),
5165 ((mode->vdisplay - 1) << 16) |
5166 (mode->hdisplay - 1));
5167 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5168 I915_WRITE(PIPESRC(pipe),
5169 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5170
f564048e
EA		 5171 I915_WRITE(PIPECONF(pipe), pipeconf);
5172 POSTING_READ(PIPECONF(pipe));
929c77fb 5173 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5174
5175 intel_wait_for_vblank(dev, pipe);
5176
f564048e
EA		 5177 I915_WRITE(DSPCNTR(plane), dspcntr);
5178 POSTING_READ(DSPCNTR(plane));
284d9529 5179 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5180
5181 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5182
5183 intel_update_watermarks(dev);
5184
f564048e
EA		 5185 return ret;
5186}
5187
9fb526db
KP		 5188/*
5189 * Initialize reference clocks when the driver loads
5190 */
5191void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5192{
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5195 struct intel_encoder *encoder;
13d83a67
JB		 5196 u32 temp;
5197 bool has_lvds = false;
199e5d79
KP		 5198 bool has_cpu_edp = false;
5199 bool has_pch_edp = false;
5200 bool has_panel = false;
99eb6a01
KP		 5201 bool has_ck505 = false;
5202 bool can_ssc = false;
13d83a67
JB		 5203
5204 /* We need to take the global config into account */
199e5d79
KP		 5205 list_for_each_entry(encoder, &mode_config->encoder_list,
5206 base.head) {
5207 switch (encoder->type) {
5208 case INTEL_OUTPUT_LVDS:
5209 has_panel = true;
5210 has_lvds = true;
5211 break;
5212 case INTEL_OUTPUT_EDP:
5213 has_panel = true;
5214 if (intel_encoder_is_pch_edp(&encoder->base))
5215 has_pch_edp = true;
5216 else
5217 has_cpu_edp = true;
5218 break;
13d83a67
JB		 5219 }
5220 }
5221
99eb6a01
KP		 5222 if (HAS_PCH_IBX(dev)) {
5223 has_ck505 = dev_priv->display_clock_mode;
5224 can_ssc = has_ck505;
5225 } else {
5226 has_ck505 = false;
5227 can_ssc = true;
5228 }
5229
5230 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5231 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5232 has_ck505);
13d83a67
JB		 5233
5234 /* Ironlake: try to setup display ref clock before DPLL
5235 * enabling. This is only under driver's control after
5236 * PCH B stepping, previous chipset stepping should be
5237 * ignoring this setting.
5238 */
5239 temp = I915_READ(PCH_DREF_CONTROL);
5240 /* Always enable nonspread source */
5241 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5242
99eb6a01
KP		 5243 if (has_ck505)
5244 temp |= DREF_NONSPREAD_CK505_ENABLE;
5245 else
5246 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5247
199e5d79
KP		 5248 if (has_panel) {
5249 temp &= ~DREF_SSC_SOURCE_MASK;
5250 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5251
199e5d79 5252 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5253 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5254 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5255 temp |= DREF_SSC1_ENABLE;
13d83a67 5256 }
199e5d79
KP		 5257
5258 /* Get SSC going before enabling the outputs */
5259 I915_WRITE(PCH_DREF_CONTROL, temp);
5260 POSTING_READ(PCH_DREF_CONTROL);
5261 udelay(200);
5262
13d83a67
JB		 5263 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5264
5265 /* Enable CPU source on CPU attached eDP */
199e5d79 5266 if (has_cpu_edp) {
99eb6a01 5267 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5268 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5269 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5270 }
13d83a67
JB		 5271 else
5272 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5273 } else
5274 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5275
5276 I915_WRITE(PCH_DREF_CONTROL, temp);
5277 POSTING_READ(PCH_DREF_CONTROL);
5278 udelay(200);
5279 } else {
5280 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5281
5282 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5283
5284 /* Turn off CPU output */
5285 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5286
5287 I915_WRITE(PCH_DREF_CONTROL, temp);
5288 POSTING_READ(PCH_DREF_CONTROL);
5289 udelay(200);
5290
5291 /* Turn off the SSC source */
5292 temp &= ~DREF_SSC_SOURCE_MASK;
5293 temp |= DREF_SSC_SOURCE_DISABLE;
5294
5295 /* Turn off SSC1 */
5296 temp &= ~ DREF_SSC1_ENABLE;
5297
13d83a67
JB		 5298 I915_WRITE(PCH_DREF_CONTROL, temp);
5299 POSTING_READ(PCH_DREF_CONTROL);
5300 udelay(200);
5301 }
5302}
5303
d9d444cb
JB		 5304static int ironlake_get_refclk(struct drm_crtc *crtc)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_encoder *encoder;
5309 struct drm_mode_config *mode_config = &dev->mode_config;
5310 struct intel_encoder *edp_encoder = NULL;
5311 int num_connectors = 0;
5312 bool is_lvds = false;
5313
5314 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5315 if (encoder->base.crtc != crtc)
5316 continue;
5317
5318 switch (encoder->type) {
5319 case INTEL_OUTPUT_LVDS:
5320 is_lvds = true;
5321 break;
5322 case INTEL_OUTPUT_EDP:
5323 edp_encoder = encoder;
5324 break;
5325 }
5326 num_connectors++;
5327 }
5328
5329 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5330 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5331 dev_priv->lvds_ssc_freq);
5332 return dev_priv->lvds_ssc_freq * 1000;
5333 }
5334
5335 return 120000;
5336}
5337
f564048e
EA		 5338static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5339 struct drm_display_mode *mode,
5340 struct drm_display_mode *adjusted_mode,
5341 int x, int y,
5342 struct drm_framebuffer *old_fb)
79e53945
JB		 5343{
5344 struct drm_device *dev = crtc->dev;
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int pipe = intel_crtc->pipe;
80824003 5348 int plane = intel_crtc->plane;
c751ce4f 5349 int refclk, num_connectors = 0;
652c393a 5350 intel_clock_t clock, reduced_clock;
5eddb70b 5351 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5352 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5353 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5354 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5355 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5356 struct intel_encoder *encoder;
d4906093 5357 const intel_limit_t *limit;
5c3b82e2 5358 int ret;
2c07245f 5359 struct fdi_m_n m_n = {0};
fae14981 5360 u32 temp;
aa9b500d 5361 u32 lvds_sync = 0;
5a354204
JB		 5362 int target_clock, pixel_multiplier, lane, link_bw, factor;
5363 unsigned int pipe_bpp;
5364 bool dither;
79e53945 5365
5eddb70b
CW		 5366 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5367 if (encoder->base.crtc != crtc)
79e53945
JB		 5368 continue;
5369
5eddb70b 5370 switch (encoder->type) {
79e53945
JB		 5371 case INTEL_OUTPUT_LVDS:
5372 is_lvds = true;
5373 break;
5374 case INTEL_OUTPUT_SDVO:
7d57382e 5375 case INTEL_OUTPUT_HDMI:
79e53945 5376 is_sdvo = true;
5eddb70b 5377 if (encoder->needs_tv_clock)
e2f0ba97 5378 is_tv = true;
79e53945 5379 break;
79e53945
JB		 5380 case INTEL_OUTPUT_TVOUT:
5381 is_tv = true;
5382 break;
5383 case INTEL_OUTPUT_ANALOG:
5384 is_crt = true;
5385 break;
a4fc5ed6
KP		 5386 case INTEL_OUTPUT_DISPLAYPORT:
5387 is_dp = true;
5388 break;
32f9d658 5389 case INTEL_OUTPUT_EDP:
5eddb70b 5390 has_edp_encoder = encoder;
32f9d658 5391 break;
79e53945 5392 }
43565a06 5393
c751ce4f 5394 num_connectors++;
79e53945
JB		 5395 }
5396
d9d444cb 5397 refclk = ironlake_get_refclk(crtc);
79e53945 5398
d4906093
ML		 5399 /*
5400 * Returns a set of divisors for the desired target clock with the given
5401 * refclk, or FALSE. The returned values represent the clock equation:
5402 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5403 */
1b894b59 5404 limit = intel_limit(crtc, refclk);
d4906093 5405 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5406 if (!ok) {
5407 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5408 return -EINVAL;
79e53945
JB		 5409 }
5410
cda4b7d3 5411 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5412 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5413
ddc9003c
ZY		 5414 if (is_lvds && dev_priv->lvds_downclock_avail) {
5415 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5416 dev_priv->lvds_downclock,
5417 refclk,
5418 &reduced_clock);
18f9ed12
ZY		 5419 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5420 /*
5421 * If the different P is found, it means that we can't
5422 * switch the display clock by using the FP0/FP1.
5423 * In such case we will disable the LVDS downclock
5424 * feature.
5425 */
5426 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5427 "LVDS clock/downclock\n");
18f9ed12
ZY		 5428 has_reduced_clock = 0;
5429 }
652c393a 5430 }
7026d4ac
ZW		 5431 /* SDVO TV has fixed PLL values depend on its clock range,
5432 this mirrors vbios setting. */
5433 if (is_sdvo && is_tv) {
5434 if (adjusted_mode->clock >= 100000
5eddb70b 5435 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5436 clock.p1 = 2;
5437 clock.p2 = 10;
5438 clock.n = 3;
5439 clock.m1 = 16;
5440 clock.m2 = 8;
5441 } else if (adjusted_mode->clock >= 140500
5eddb70b 5442 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5443 clock.p1 = 1;
5444 clock.p2 = 10;
5445 clock.n = 6;
5446 clock.m1 = 12;
5447 clock.m2 = 8;
5448 }
5449 }
5450
2c07245f 5451 /* FDI link */
8febb297
EA		 5452 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5453 lane = 0;
5454 /* CPU eDP doesn't require FDI link, so just set DP M/N
5455 according to current link config */
5456 if (has_edp_encoder &&
5457 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5458 target_clock = mode->clock;
5459 intel_edp_link_config(has_edp_encoder,
5460 &lane, &link_bw);
5461 } else {
5462 /* [e]DP over FDI requires target mode clock
5463 instead of link clock */
5464 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5465 target_clock = mode->clock;
8febb297
EA		 5466 else
5467 target_clock = adjusted_mode->clock;
5468
5469 /* FDI is a binary signal running at ~2.7GHz, encoding
5470 * each output octet as 10 bits. The actual frequency
5471 * is stored as a divider into a 100MHz clock, and the
5472 * mode pixel clock is stored in units of 1KHz.
5473 * Hence the bw of each lane in terms of the mode signal
5474 * is:
5475 */
5476 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5477 }
58a27471 5478
8febb297
EA		 5479 /* determine panel color depth */
5480 temp = I915_READ(PIPECONF(pipe));
5481 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5482 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5483 switch (pipe_bpp) {
5484 case 18:
5485 temp |= PIPE_6BPC;
8febb297 5486 break;
5a354204
JB		 5487 case 24:
5488 temp |= PIPE_8BPC;
8febb297 5489 break;
5a354204
JB		 5490 case 30:
5491 temp |= PIPE_10BPC;
8febb297 5492 break;
5a354204
JB		 5493 case 36:
5494 temp |= PIPE_12BPC;
8febb297
EA		 5495 break;
5496 default:
62ac41a6
JB		 5497 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5498 pipe_bpp);
5a354204
JB		 5499 temp |= PIPE_8BPC;
5500 pipe_bpp = 24;
5501 break;
8febb297 5502 }
77ffb597 5503
5a354204
JB		 5504 intel_crtc->bpp = pipe_bpp;
5505 I915_WRITE(PIPECONF(pipe), temp);
5506
8febb297
EA		 5507 if (!lane) {
5508 /*
5509 * Account for spread spectrum to avoid
5510 * oversubscribing the link. Max center spread
5511 * is 2.5%; use 5% for safety's sake.
5512 */
5a354204 5513 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5514 lane = bps / (link_bw * 8) + 1;
5eb08b69 5515 }
2c07245f 5516
8febb297
EA		 5517 intel_crtc->fdi_lanes = lane;
5518
5519 if (pixel_multiplier > 1)
5520 link_bw *= pixel_multiplier;
5a354204
JB		 5521 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5522 &m_n);
8febb297 5523
a07d6787
EA		 5524 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5525 if (has_reduced_clock)
5526 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5527 reduced_clock.m2;
79e53945 5528
c1858123 5529 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5530 factor = 21;
5531 if (is_lvds) {
5532 if ((intel_panel_use_ssc(dev_priv) &&
5533 dev_priv->lvds_ssc_freq == 100) ||
5534 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5535 factor = 25;
5536 } else if (is_sdvo && is_tv)
5537 factor = 20;
c1858123 5538
cb0e0931 5539 if (clock.m < factor * clock.n)
8febb297 5540 fp |= FP_CB_TUNE;
2c07245f 5541
5eddb70b 5542 dpll = 0;
2c07245f 5543
a07d6787
EA		 5544 if (is_lvds)
5545 dpll |= DPLLB_MODE_LVDS;
5546 else
5547 dpll |= DPLLB_MODE_DAC_SERIAL;
5548 if (is_sdvo) {
5549 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5550 if (pixel_multiplier > 1) {
5551 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5552 }
a07d6787
EA		 5553 dpll |= DPLL_DVO_HIGH_SPEED;
5554 }
5555 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5556 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5557
a07d6787
EA		 5558 /* compute bitmask from p1 value */
5559 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5560 /* also FPA1 */
5561 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5562
5563 switch (clock.p2) {
5564 case 5:
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5566 break;
5567 case 7:
5568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5569 break;
5570 case 10:
5571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5572 break;
5573 case 14:
5574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5575 break;
79e53945
JB		 5576 }
5577
43565a06
KH		 5578 if (is_sdvo && is_tv)
5579 dpll |= PLL_REF_INPUT_TVCLKINBC;
5580 else if (is_tv)
79e53945 5581 /* XXX: just matching BIOS for now */
43565a06 5582 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5583 dpll |= 3;
a7615030 5584 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5585 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5586 else
5587 dpll |= PLL_REF_INPUT_DREFCLK;
5588
5589 /* setup pipeconf */
5eddb70b 5590 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5591
5592 /* Set up the display plane register */
5593 dspcntr = DISPPLANE_GAMMA_ENABLE;
5594
f7cb34d4 5595 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5596 drm_mode_debug_printmodeline(mode);
5597
5c5313c8 5598 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5599 if (!intel_crtc->no_pll) {
5600 if (!has_edp_encoder ||
5601 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5602 I915_WRITE(PCH_FP0(pipe), fp);
5603 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5604
5605 POSTING_READ(PCH_DPLL(pipe));
5606 udelay(150);
5607 }
5608 } else {
5609 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5610 fp == I915_READ(PCH_FP0(0))) {
5611 intel_crtc->use_pll_a = true;
5612 DRM_DEBUG_KMS("using pipe a dpll\n");
5613 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5614 fp == I915_READ(PCH_FP0(1))) {
5615 intel_crtc->use_pll_a = false;
5616 DRM_DEBUG_KMS("using pipe b dpll\n");
5617 } else {
5618 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5619 return -EINVAL;
5620 }
79e53945
JB		 5621 }
5622
5623 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5624 * This is an exception to the general rule that mode_set doesn't turn
5625 * things on.
5626 */
5627 if (is_lvds) {
fae14981 5628 temp = I915_READ(PCH_LVDS);
5eddb70b 5629 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4b645f14
JB		 5630 if (HAS_PCH_CPT(dev))
5631 temp |= PORT_TRANS_SEL_CPT(pipe);
5632 else if (pipe == 1)
5633 temp |= LVDS_PIPEB_SELECT;
5634 else
5635 temp &= ~LVDS_PIPEB_SELECT;
5636
a3e17eb8 5637 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5638 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5639 /* Set the B0-B3 data pairs corresponding to whether we're going to
5640 * set the DPLLs for dual-channel mode or not.
5641 */
5642 if (clock.p2 == 7)
5eddb70b 5643 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5644 else
5eddb70b 5645 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5646
5647 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5648 * appropriately here, but we need to look more thoroughly into how
5649 * panels behave in the two modes.
5650 */
aa9b500d
BF		 5651 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5652 lvds_sync |= LVDS_HSYNC_POLARITY;
5653 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5654 lvds_sync |= LVDS_VSYNC_POLARITY;
5655 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5656 != lvds_sync) {
5657 char flags[2] = "-+";
5658 DRM_INFO("Changing LVDS panel from "
5659 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5660 flags[!(temp & LVDS_HSYNC_POLARITY)],
5661 flags[!(temp & LVDS_VSYNC_POLARITY)],
5662 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5663 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5664 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5665 temp |= lvds_sync;
5666 }
fae14981 5667 I915_WRITE(PCH_LVDS, temp);
79e53945 5668 }
434ed097 5669
8febb297
EA		 5670 pipeconf &= ~PIPECONF_DITHER_EN;
5671 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5672 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5673 pipeconf |= PIPECONF_DITHER_EN;
5674 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5675 }
5c5313c8 5676 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5677 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5678 } else {
8db9d77b 5679 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5680 I915_WRITE(TRANSDATA_M1(pipe), 0);
5681 I915_WRITE(TRANSDATA_N1(pipe), 0);
5682 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5683 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5684 }
79e53945 5685
4b645f14
JB		 5686 if (!intel_crtc->no_pll &&
5687 (!has_edp_encoder ||
5688 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5689 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5690
32f9d658 5691 /* Wait for the clocks to stabilize. */
fae14981 5692 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5693 udelay(150);
5694
8febb297
EA		 5695 /* The pixel multiplier can only be updated once the
5696 * DPLL is enabled and the clocks are stable.
5697 *
5698 * So write it again.
5699 */
fae14981 5700 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5701 }
79e53945 5702
5eddb70b 5703 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5704 if (!intel_crtc->no_pll) {
5705 if (is_lvds && has_reduced_clock && i915_powersave) {
5706 I915_WRITE(PCH_FP1(pipe), fp2);
5707 intel_crtc->lowfreq_avail = true;
5708 if (HAS_PIPE_CXSR(dev)) {
5709 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5710 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5711 }
5712 } else {
5713 I915_WRITE(PCH_FP1(pipe), fp);
5714 if (HAS_PIPE_CXSR(dev)) {
5715 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5716 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5717 }
652c393a
JB		 5718 }
5719 }
5720
734b4157
KH		 5721 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5722 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5723 /* the chip adds 2 halflines automatically */
5724 adjusted_mode->crtc_vdisplay -= 1;
5725 adjusted_mode->crtc_vtotal -= 1;
5726 adjusted_mode->crtc_vblank_start -= 1;
5727 adjusted_mode->crtc_vblank_end -= 1;
5728 adjusted_mode->crtc_vsync_end -= 1;
5729 adjusted_mode->crtc_vsync_start -= 1;
5730 } else
5731 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5732
5eddb70b
CW		 5733 I915_WRITE(HTOTAL(pipe),
5734 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5735 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5736 I915_WRITE(HBLANK(pipe),
5737 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5738 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5739 I915_WRITE(HSYNC(pipe),
5740 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5741 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5742
5743 I915_WRITE(VTOTAL(pipe),
5744 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5745 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5746 I915_WRITE(VBLANK(pipe),
5747 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5748 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5749 I915_WRITE(VSYNC(pipe),
5750 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5751 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5752
8febb297
EA		 5753 /* pipesrc controls the size that is scaled from, which should
5754 * always be the user's requested size.
79e53945 5755 */
5eddb70b
CW		 5756 I915_WRITE(PIPESRC(pipe),
5757 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5758
8febb297
EA		 5759 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5760 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5761 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5762 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5763
8febb297
EA		 5764 if (has_edp_encoder &&
5765 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5766 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5767 }
5768
5eddb70b
CW		 5769 I915_WRITE(PIPECONF(pipe), pipeconf);
5770 POSTING_READ(PIPECONF(pipe));
79e53945 5771
9d0498a2 5772 intel_wait_for_vblank(dev, pipe);
79e53945 5773
f00a3ddf 5774 if (IS_GEN5(dev)) {
553bd149
ZW		 5775 /* enable address swizzle for tiling buffer */
5776 temp = I915_READ(DISP_ARB_CTL);
5777 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5778 }
5779
5eddb70b 5780 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5781 POSTING_READ(DSPCNTR(plane));
79e53945 5782
5c3b82e2 5783 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5784
5785 intel_update_watermarks(dev);
5786
1f803ee5 5787 return ret;
79e53945
JB		 5788}
5789
f564048e
EA		 5790static int intel_crtc_mode_set(struct drm_crtc *crtc,
5791 struct drm_display_mode *mode,
5792 struct drm_display_mode *adjusted_mode,
5793 int x, int y,
5794 struct drm_framebuffer *old_fb)
5795{
5796 struct drm_device *dev = crtc->dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799 int pipe = intel_crtc->pipe;
f564048e
EA		 5800 int ret;
5801
0b701d27 5802 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5803
f564048e
EA		 5804 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5805 x, y, old_fb);
7662c8bd 5806
79e53945 5807 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5808
120eced9
KP		 5809 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5810
1f803ee5 5811 return ret;
79e53945
JB		 5812}
5813
e0dac65e
WF		 5814static void g4x_write_eld(struct drm_connector *connector,
5815 struct drm_crtc *crtc)
5816{
5817 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5818 uint8_t *eld = connector->eld;
5819 uint32_t eldv;
5820 uint32_t len;
5821 uint32_t i;
5822
5823 i = I915_READ(G4X_AUD_VID_DID);
5824
5825 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5826 eldv = G4X_ELDV_DEVCL_DEVBLC;
5827 else
5828 eldv = G4X_ELDV_DEVCTG;
5829
5830 i = I915_READ(G4X_AUD_CNTL_ST);
5831 i &= ~(eldv | G4X_ELD_ADDR);
5832 len = (i >> 9) & 0x1f; /* ELD buffer size */
5833 I915_WRITE(G4X_AUD_CNTL_ST, i);
5834
5835 if (!eld[0])
5836 return;
5837
5838 len = min_t(uint8_t, eld[2], len);
5839 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5840 for (i = 0; i < len; i++)
5841 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5842
5843 i = I915_READ(G4X_AUD_CNTL_ST);
5844 i |= eldv;
5845 I915_WRITE(G4X_AUD_CNTL_ST, i);
5846}
5847
5848static void ironlake_write_eld(struct drm_connector *connector,
5849 struct drm_crtc *crtc)
5850{
5851 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5852 uint8_t *eld = connector->eld;
5853 uint32_t eldv;
5854 uint32_t i;
5855 int len;
5856 int hdmiw_hdmiedid;
5857 int aud_cntl_st;
5858 int aud_cntrl_st2;
5859
5860 if (IS_IVYBRIDGE(connector->dev)) {
5861 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5862 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5863 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5864 } else {
5865 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5866 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5867 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5868 }
5869
5870 i = to_intel_crtc(crtc)->pipe;
5871 hdmiw_hdmiedid += i * 0x100;
5872 aud_cntl_st += i * 0x100;
5873
5874 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5875
5876 i = I915_READ(aud_cntl_st);
5877 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5878 if (!i) {
5879 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5880 /* operate blindly on all ports */
5881 eldv = GEN5_ELD_VALIDB;
5882 eldv |= GEN5_ELD_VALIDB << 4;
5883 eldv |= GEN5_ELD_VALIDB << 8;
5884 } else {
5885 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5886 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5887 }
5888
5889 i = I915_READ(aud_cntrl_st2);
5890 i &= ~eldv;
5891 I915_WRITE(aud_cntrl_st2, i);
5892
5893 if (!eld[0])
5894 return;
5895
5896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5897 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5898 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5899 }
5900
5901 i = I915_READ(aud_cntl_st);
5902 i &= ~GEN5_ELD_ADDRESS;
5903 I915_WRITE(aud_cntl_st, i);
5904
5905 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5906 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5907 for (i = 0; i < len; i++)
5908 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5909
5910 i = I915_READ(aud_cntrl_st2);
5911 i |= eldv;
5912 I915_WRITE(aud_cntrl_st2, i);
5913}
5914
5915void intel_write_eld(struct drm_encoder *encoder,
5916 struct drm_display_mode *mode)
5917{
5918 struct drm_crtc *crtc = encoder->crtc;
5919 struct drm_connector *connector;
5920 struct drm_device *dev = encoder->dev;
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922
5923 connector = drm_select_eld(encoder, mode);
5924 if (!connector)
5925 return;
5926
5927 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5928 connector->base.id,
5929 drm_get_connector_name(connector),
5930 connector->encoder->base.id,
5931 drm_get_encoder_name(connector->encoder));
5932
5933 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5934
5935 if (dev_priv->display.write_eld)
5936 dev_priv->display.write_eld(connector, crtc);
5937}
5938
79e53945
JB		 5939/** Loads the palette/gamma unit for the CRTC with the prepared values */
5940void intel_crtc_load_lut(struct drm_crtc *crtc)
5941{
5942 struct drm_device *dev = crtc->dev;
5943 struct drm_i915_private *dev_priv = dev->dev_private;
5944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5945 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5946 int i;
5947
5948 /* The clocks have to be on to load the palette. */
5949 if (!crtc->enabled)
5950 return;
5951
f2b115e6 5952 /* use legacy palette for Ironlake */
bad720ff 5953 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5954 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5955
79e53945
JB		 5956 for (i = 0; i < 256; i++) {
5957 I915_WRITE(palreg + 4 * i,
5958 (intel_crtc->lut_r[i] << 16) |
5959 (intel_crtc->lut_g[i] << 8) |
5960 intel_crtc->lut_b[i]);
5961 }
5962}
5963
560b85bb
CW		 5964static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5965{
5966 struct drm_device *dev = crtc->dev;
5967 struct drm_i915_private *dev_priv = dev->dev_private;
5968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5969 bool visible = base != 0;
5970 u32 cntl;
5971
5972 if (intel_crtc->cursor_visible == visible)
5973 return;
5974
9db4a9c7 5975 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5976 if (visible) {
5977 /* On these chipsets we can only modify the base whilst
5978 * the cursor is disabled.
5979 */
9db4a9c7 5980 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5981
5982 cntl &= ~(CURSOR_FORMAT_MASK);
5983 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5984 cntl |= CURSOR_ENABLE |
5985 CURSOR_GAMMA_ENABLE |
5986 CURSOR_FORMAT_ARGB;
5987 } else
5988 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5989 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5990
5991 intel_crtc->cursor_visible = visible;
5992}
5993
5994static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5995{
5996 struct drm_device *dev = crtc->dev;
5997 struct drm_i915_private *dev_priv = dev->dev_private;
5998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5999 int pipe = intel_crtc->pipe;
6000 bool visible = base != 0;
6001
6002 if (intel_crtc->cursor_visible != visible) {
548f245b 6003 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6004 if (base) {
6005 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6006 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6007 cntl |= pipe << 28; /* Connect to correct pipe */
6008 } else {
6009 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6010 cntl |= CURSOR_MODE_DISABLE;
6011 }
9db4a9c7 6012 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6013
6014 intel_crtc->cursor_visible = visible;
6015 }
6016 /* and commit changes on next vblank */
9db4a9c7 6017 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6018}
6019
65a21cd6
JB		 6020static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6021{
6022 struct drm_device *dev = crtc->dev;
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6025 int pipe = intel_crtc->pipe;
6026 bool visible = base != 0;
6027
6028 if (intel_crtc->cursor_visible != visible) {
6029 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6030 if (base) {
6031 cntl &= ~CURSOR_MODE;
6032 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6033 } else {
6034 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6035 cntl |= CURSOR_MODE_DISABLE;
6036 }
6037 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6038
6039 intel_crtc->cursor_visible = visible;
6040 }
6041 /* and commit changes on next vblank */
6042 I915_WRITE(CURBASE_IVB(pipe), base);
6043}
6044
cda4b7d3 6045/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6046static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6047 bool on)
cda4b7d3
CW		 6048{
6049 struct drm_device *dev = crtc->dev;
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052 int pipe = intel_crtc->pipe;
6053 int x = intel_crtc->cursor_x;
6054 int y = intel_crtc->cursor_y;
560b85bb 6055 u32 base, pos;
cda4b7d3
CW		 6056 bool visible;
6057
6058 pos = 0;
6059
6b383a7f 6060 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6061 base = intel_crtc->cursor_addr;
6062 if (x > (int) crtc->fb->width)
6063 base = 0;
6064
6065 if (y > (int) crtc->fb->height)
6066 base = 0;
6067 } else
6068 base = 0;
6069
6070 if (x < 0) {
6071 if (x + intel_crtc->cursor_width < 0)
6072 base = 0;
6073
6074 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6075 x = -x;
6076 }
6077 pos |= x << CURSOR_X_SHIFT;
6078
6079 if (y < 0) {
6080 if (y + intel_crtc->cursor_height < 0)
6081 base = 0;
6082
6083 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6084 y = -y;
6085 }
6086 pos |= y << CURSOR_Y_SHIFT;
6087
6088 visible = base != 0;
560b85bb 6089 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6090 return;
6091
65a21cd6
JB		 6092 if (IS_IVYBRIDGE(dev)) {
6093 I915_WRITE(CURPOS_IVB(pipe), pos);
6094 ivb_update_cursor(crtc, base);
6095 } else {
6096 I915_WRITE(CURPOS(pipe), pos);
6097 if (IS_845G(dev) || IS_I865G(dev))
6098 i845_update_cursor(crtc, base);
6099 else
6100 i9xx_update_cursor(crtc, base);
6101 }
cda4b7d3
CW		 6102
6103 if (visible)
6104 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6105}
6106
79e53945 6107static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6108 struct drm_file *file,
79e53945
JB		 6109 uint32_t handle,
6110 uint32_t width, uint32_t height)
6111{
6112 struct drm_device *dev = crtc->dev;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6115 struct drm_i915_gem_object *obj;
cda4b7d3 6116 uint32_t addr;
3f8bc370 6117 int ret;
79e53945 6118
28c97730 6119 DRM_DEBUG_KMS("\n");
79e53945
JB		 6120
6121 /* if we want to turn off the cursor ignore width and height */
6122 if (!handle) {
28c97730 6123 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6124 addr = 0;
05394f39 6125 obj = NULL;
5004417d 6126 mutex_lock(&dev->struct_mutex);
3f8bc370 6127 goto finish;
79e53945
JB		 6128 }
6129
6130 /* Currently we only support 64x64 cursors */
6131 if (width != 64 || height != 64) {
6132 DRM_ERROR("we currently only support 64x64 cursors\n");
6133 return -EINVAL;
6134 }
6135
05394f39 6136 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6137 if (&obj->base == NULL)
79e53945
JB		 6138 return -ENOENT;
6139
05394f39 6140 if (obj->base.size < width * height * 4) {
79e53945 6141 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6142 ret = -ENOMEM;
6143 goto fail;
79e53945
JB		 6144 }
6145
71acb5eb 6146 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6147 mutex_lock(&dev->struct_mutex);
b295d1b6 6148 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6149 if (obj->tiling_mode) {
6150 DRM_ERROR("cursor cannot be tiled\n");
6151 ret = -EINVAL;
6152 goto fail_locked;
6153 }
6154
2da3b9b9 6155 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6156 if (ret) {
6157 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6158 goto fail_locked;
e7b526bb
CW		 6159 }
6160
d9e86c0e
CW		 6161 ret = i915_gem_object_put_fence(obj);
6162 if (ret) {
2da3b9b9 6163 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6164 goto fail_unpin;
6165 }
6166
05394f39 6167 addr = obj->gtt_offset;
71acb5eb 6168 } else {
6eeefaf3 6169 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6170 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6171 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6172 align);
71acb5eb
DA		 6173 if (ret) {
6174 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6175 goto fail_locked;
71acb5eb 6176 }
05394f39 6177 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6178 }
6179
a6c45cf0 6180 if (IS_GEN2(dev))
14b60391
JB		 6181 I915_WRITE(CURSIZE, (height << 12) | width);
6182
3f8bc370 6183 finish:
3f8bc370 6184 if (intel_crtc->cursor_bo) {
b295d1b6 6185 if (dev_priv->info->cursor_needs_physical) {
05394f39 6186 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6187 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6188 } else
6189 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6190 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6191 }
80824003 6192
7f9872e0 6193 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6194
6195 intel_crtc->cursor_addr = addr;
05394f39 6196 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6197 intel_crtc->cursor_width = width;
6198 intel_crtc->cursor_height = height;
6199
6b383a7f 6200 intel_crtc_update_cursor(crtc, true);
3f8bc370 6201
79e53945 6202 return 0;
e7b526bb 6203fail_unpin:
05394f39 6204 i915_gem_object_unpin(obj);
7f9872e0 6205fail_locked:
34b8686e 6206 mutex_unlock(&dev->struct_mutex);
bc9025bd 6207fail:
05394f39 6208 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6209 return ret;
79e53945
JB		 6210}
6211
6212static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6213{
79e53945 6214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6215
cda4b7d3
CW		 6216 intel_crtc->cursor_x = x;
6217 intel_crtc->cursor_y = y;
652c393a 6218
6b383a7f 6219 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6220
6221 return 0;
6222}
6223
6224/** Sets the color ramps on behalf of RandR */
6225void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6226 u16 blue, int regno)
6227{
6228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6229
6230 intel_crtc->lut_r[regno] = red >> 8;
6231 intel_crtc->lut_g[regno] = green >> 8;
6232 intel_crtc->lut_b[regno] = blue >> 8;
6233}
6234
b8c00ac5
DA		 6235void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6236 u16 *blue, int regno)
6237{
6238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6239
6240 *red = intel_crtc->lut_r[regno] << 8;
6241 *green = intel_crtc->lut_g[regno] << 8;
6242 *blue = intel_crtc->lut_b[regno] << 8;
6243}
6244
79e53945 6245static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6246 u16 *blue, uint32_t start, uint32_t size)
79e53945 6247{
7203425a 6248 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6250
7203425a 6251 for (i = start; i < end; i++) {
79e53945
JB		 6252 intel_crtc->lut_r[i] = red[i] >> 8;
6253 intel_crtc->lut_g[i] = green[i] >> 8;
6254 intel_crtc->lut_b[i] = blue[i] >> 8;
6255 }
6256
6257 intel_crtc_load_lut(crtc);
6258}
6259
6260/**
6261 * Get a pipe with a simple mode set on it for doing load-based monitor
6262 * detection.
6263 *
6264 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6265 * its requirements. The pipe will be connected to no other encoders.
79e53945 6266 *
c751ce4f 6267 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6268 * configured for it. In the future, it could choose to temporarily disable
6269 * some outputs to free up a pipe for its use.
6270 *
6271 * \return crtc, or NULL if no pipes are available.
6272 */
6273
6274/* VESA 640x480x72Hz mode to set on the pipe */
6275static struct drm_display_mode load_detect_mode = {
6276 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6277 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6278};
6279
d2dff872
CW		 6280static struct drm_framebuffer *
6281intel_framebuffer_create(struct drm_device *dev,
6282 struct drm_mode_fb_cmd *mode_cmd,
6283 struct drm_i915_gem_object *obj)
6284{
6285 struct intel_framebuffer *intel_fb;
6286 int ret;
6287
6288 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6289 if (!intel_fb) {
6290 drm_gem_object_unreference_unlocked(&obj->base);
6291 return ERR_PTR(-ENOMEM);
6292 }
6293
6294 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6295 if (ret) {
6296 drm_gem_object_unreference_unlocked(&obj->base);
6297 kfree(intel_fb);
6298 return ERR_PTR(ret);
6299 }
6300
6301 return &intel_fb->base;
6302}
6303
6304static u32
6305intel_framebuffer_pitch_for_width(int width, int bpp)
6306{
6307 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6308 return ALIGN(pitch, 64);
6309}
6310
6311static u32
6312intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6313{
6314 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6315 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6316}
6317
6318static struct drm_framebuffer *
6319intel_framebuffer_create_for_mode(struct drm_device *dev,
6320 struct drm_display_mode *mode,
6321 int depth, int bpp)
6322{
6323 struct drm_i915_gem_object *obj;
6324 struct drm_mode_fb_cmd mode_cmd;
6325
6326 obj = i915_gem_alloc_object(dev,
6327 intel_framebuffer_size_for_mode(mode, bpp));
6328 if (obj == NULL)
6329 return ERR_PTR(-ENOMEM);
6330
6331 mode_cmd.width = mode->hdisplay;
6332 mode_cmd.height = mode->vdisplay;
6333 mode_cmd.depth = depth;
6334 mode_cmd.bpp = bpp;
6335 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6336
6337 return intel_framebuffer_create(dev, &mode_cmd, obj);
6338}
6339
6340static struct drm_framebuffer *
6341mode_fits_in_fbdev(struct drm_device *dev,
6342 struct drm_display_mode *mode)
6343{
6344 struct drm_i915_private *dev_priv = dev->dev_private;
6345 struct drm_i915_gem_object *obj;
6346 struct drm_framebuffer *fb;
6347
6348 if (dev_priv->fbdev == NULL)
6349 return NULL;
6350
6351 obj = dev_priv->fbdev->ifb.obj;
6352 if (obj == NULL)
6353 return NULL;
6354
6355 fb = &dev_priv->fbdev->ifb.base;
6356 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6357 fb->bits_per_pixel))
6358 return NULL;
6359
6360 if (obj->base.size < mode->vdisplay * fb->pitch)
6361 return NULL;
6362
6363 return fb;
6364}
6365
7173188d
CW		 6366bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6367 struct drm_connector *connector,
6368 struct drm_display_mode *mode,
8261b191 6369 struct intel_load_detect_pipe *old)
79e53945
JB		 6370{
6371 struct intel_crtc *intel_crtc;
6372 struct drm_crtc *possible_crtc;
4ef69c7a 6373 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6374 struct drm_crtc *crtc = NULL;
6375 struct drm_device *dev = encoder->dev;
d2dff872 6376 struct drm_framebuffer *old_fb;
79e53945
JB		 6377 int i = -1;
6378
d2dff872
CW		 6379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6380 connector->base.id, drm_get_connector_name(connector),
6381 encoder->base.id, drm_get_encoder_name(encoder));
6382
79e53945
JB		 6383 /*
6384 * Algorithm gets a little messy:
7a5e4805 6385 *
79e53945
JB		 6386 * - if the connector already has an assigned crtc, use it (but make
6387 * sure it's on first)
7a5e4805 6388 *
79e53945
JB		 6389 * - try to find the first unused crtc that can drive this connector,
6390 * and use that if we find one
79e53945
JB		 6391 */
6392
6393 /* See if we already have a CRTC for this connector */
6394 if (encoder->crtc) {
6395 crtc = encoder->crtc;
8261b191 6396
79e53945 6397 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6398 old->dpms_mode = intel_crtc->dpms_mode;
6399 old->load_detect_temp = false;
6400
6401 /* Make sure the crtc and connector are running */
79e53945 6402 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6403 struct drm_encoder_helper_funcs *encoder_funcs;
6404 struct drm_crtc_helper_funcs *crtc_funcs;
6405
79e53945
JB		 6406 crtc_funcs = crtc->helper_private;
6407 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6408
6409 encoder_funcs = encoder->helper_private;
79e53945
JB		 6410 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6411 }
8261b191 6412
7173188d 6413 return true;
79e53945
JB		 6414 }
6415
6416 /* Find an unused one (if possible) */
6417 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6418 i++;
6419 if (!(encoder->possible_crtcs & (1 << i)))
6420 continue;
6421 if (!possible_crtc->enabled) {
6422 crtc = possible_crtc;
6423 break;
6424 }
79e53945
JB		 6425 }
6426
6427 /*
6428 * If we didn't find an unused CRTC, don't use any.
6429 */
6430 if (!crtc) {
7173188d
CW		 6431 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6432 return false;
79e53945
JB		 6433 }
6434
6435 encoder->crtc = crtc;
c1c43977 6436 connector->encoder = encoder;
79e53945
JB		 6437
6438 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6439 old->dpms_mode = intel_crtc->dpms_mode;
6440 old->load_detect_temp = true;
d2dff872 6441 old->release_fb = NULL;
79e53945 6442
6492711d
CW		 6443 if (!mode)
6444 mode = &load_detect_mode;
79e53945 6445
d2dff872
CW		 6446 old_fb = crtc->fb;
6447
6448 /* We need a framebuffer large enough to accommodate all accesses
6449 * that the plane may generate whilst we perform load detection.
6450 * We can not rely on the fbcon either being present (we get called
6451 * during its initialisation to detect all boot displays, or it may
6452 * not even exist) or that it is large enough to satisfy the
6453 * requested mode.
6454 */
6455 crtc->fb = mode_fits_in_fbdev(dev, mode);
6456 if (crtc->fb == NULL) {
6457 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6458 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6459 old->release_fb = crtc->fb;
6460 } else
6461 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6462 if (IS_ERR(crtc->fb)) {
6463 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6464 crtc->fb = old_fb;
6465 return false;
79e53945 6466 }
79e53945 6467
d2dff872 6468 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6469 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6470 if (old->release_fb)
6471 old->release_fb->funcs->destroy(old->release_fb);
6472 crtc->fb = old_fb;
6492711d 6473 return false;
79e53945 6474 }
7173188d 6475
79e53945 6476 /* let the connector get through one full cycle before testing */
9d0498a2 6477 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6478
7173188d 6479 return true;
79e53945
JB		 6480}
6481
c1c43977 6482void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6483 struct drm_connector *connector,
6484 struct intel_load_detect_pipe *old)
79e53945 6485{
4ef69c7a 6486 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6487 struct drm_device *dev = encoder->dev;
6488 struct drm_crtc *crtc = encoder->crtc;
6489 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6490 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6491
d2dff872
CW		 6492 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6493 connector->base.id, drm_get_connector_name(connector),
6494 encoder->base.id, drm_get_encoder_name(encoder));
6495
8261b191 6496 if (old->load_detect_temp) {
c1c43977 6497 connector->encoder = NULL;
79e53945 6498 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6499
6500 if (old->release_fb)
6501 old->release_fb->funcs->destroy(old->release_fb);
6502
0622a53c 6503 return;
79e53945
JB		 6504 }
6505
c751ce4f 6506 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6507 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6508 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6509 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6510 }
6511}
6512
6513/* Returns the clock of the currently programmed mode of the given pipe. */
6514static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518 int pipe = intel_crtc->pipe;
548f245b 6519 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6520 u32 fp;
6521 intel_clock_t clock;
6522
6523 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6524 fp = I915_READ(FP0(pipe));
79e53945 6525 else
39adb7a5 6526 fp = I915_READ(FP1(pipe));
79e53945
JB		 6527
6528 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6529 if (IS_PINEVIEW(dev)) {
6530 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6531 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6532 } else {
6533 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6534 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6535 }
6536
a6c45cf0 6537 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6538 if (IS_PINEVIEW(dev))
6539 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6540 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6541 else
6542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6543 DPLL_FPA01_P1_POST_DIV_SHIFT);
6544
6545 switch (dpll & DPLL_MODE_MASK) {
6546 case DPLLB_MODE_DAC_SERIAL:
6547 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6548 5 : 10;
6549 break;
6550 case DPLLB_MODE_LVDS:
6551 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6552 7 : 14;
6553 break;
6554 default:
28c97730 6555 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6556 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6557 return 0;
6558 }
6559
6560 /* XXX: Handle the 100Mhz refclk */
2177832f 6561 intel_clock(dev, 96000, &clock);
79e53945
JB		 6562 } else {
6563 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6564
6565 if (is_lvds) {
6566 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6567 DPLL_FPA01_P1_POST_DIV_SHIFT);
6568 clock.p2 = 14;
6569
6570 if ((dpll & PLL_REF_INPUT_MASK) ==
6571 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6572 /* XXX: might not be 66MHz */
2177832f 6573 intel_clock(dev, 66000, &clock);
79e53945 6574 } else
2177832f 6575 intel_clock(dev, 48000, &clock);
79e53945
JB		 6576 } else {
6577 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6578 clock.p1 = 2;
6579 else {
6580 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6581 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6582 }
6583 if (dpll & PLL_P2_DIVIDE_BY_4)
6584 clock.p2 = 4;
6585 else
6586 clock.p2 = 2;
6587
2177832f 6588 intel_clock(dev, 48000, &clock);
79e53945
JB		 6589 }
6590 }
6591
6592 /* XXX: It would be nice to validate the clocks, but we can't reuse
6593 * i830PllIsValid() because it relies on the xf86_config connector
6594 * configuration being accurate, which it isn't necessarily.
6595 */
6596
6597 return clock.dot;
6598}
6599
6600/** Returns the currently programmed mode of the given pipe. */
6601struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6602 struct drm_crtc *crtc)
6603{
548f245b 6604 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606 int pipe = intel_crtc->pipe;
6607 struct drm_display_mode *mode;
548f245b
JB		 6608 int htot = I915_READ(HTOTAL(pipe));
6609 int hsync = I915_READ(HSYNC(pipe));
6610 int vtot = I915_READ(VTOTAL(pipe));
6611 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6612
6613 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6614 if (!mode)
6615 return NULL;
6616
6617 mode->clock = intel_crtc_clock_get(dev, crtc);
6618 mode->hdisplay = (htot & 0xffff) + 1;
6619 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6620 mode->hsync_start = (hsync & 0xffff) + 1;
6621 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6622 mode->vdisplay = (vtot & 0xffff) + 1;
6623 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6624 mode->vsync_start = (vsync & 0xffff) + 1;
6625 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6626
6627 drm_mode_set_name(mode);
6628 drm_mode_set_crtcinfo(mode, 0);
6629
6630 return mode;
6631}
6632
652c393a
JB		 6633#define GPU_IDLE_TIMEOUT 500 /* ms */
6634
6635/* When this timer fires, we've been idle for awhile */
6636static void intel_gpu_idle_timer(unsigned long arg)
6637{
6638 struct drm_device *dev = (struct drm_device *)arg;
6639 drm_i915_private_t *dev_priv = dev->dev_private;
6640
ff7ea4c0
CW		 6641 if (!list_empty(&dev_priv->mm.active_list)) {
6642 /* Still processing requests, so just re-arm the timer. */
6643 mod_timer(&dev_priv->idle_timer, jiffies +
6644 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6645 return;
6646 }
652c393a 6647
ff7ea4c0 6648 dev_priv->busy = false;
01dfba93 6649 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6650}
6651
652c393a
JB		 6652#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6653
6654static void intel_crtc_idle_timer(unsigned long arg)
6655{
6656 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6657 struct drm_crtc *crtc = &intel_crtc->base;
6658 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6659 struct intel_framebuffer *intel_fb;
652c393a 6660
ff7ea4c0
CW		 6661 intel_fb = to_intel_framebuffer(crtc->fb);
6662 if (intel_fb && intel_fb->obj->active) {
6663 /* The framebuffer is still being accessed by the GPU. */
6664 mod_timer(&intel_crtc->idle_timer, jiffies +
6665 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6666 return;
6667 }
652c393a 6668
ff7ea4c0 6669 intel_crtc->busy = false;
01dfba93 6670 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6671}
6672
3dec0095 6673static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6674{
6675 struct drm_device *dev = crtc->dev;
6676 drm_i915_private_t *dev_priv = dev->dev_private;
6677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6678 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6679 int dpll_reg = DPLL(pipe);
6680 int dpll;
652c393a 6681
bad720ff 6682 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6683 return;
6684
6685 if (!dev_priv->lvds_downclock_avail)
6686 return;
6687
dbdc6479 6688 dpll = I915_READ(dpll_reg);
652c393a 6689 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6690 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6691
6692 /* Unlock panel regs */
dbdc6479
JB		 6693 I915_WRITE(PP_CONTROL,
6694 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6695
6696 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6697 I915_WRITE(dpll_reg, dpll);
9d0498a2 6698 intel_wait_for_vblank(dev, pipe);
dbdc6479 6699
652c393a
JB		 6700 dpll = I915_READ(dpll_reg);
6701 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6702 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6703
6704 /* ...and lock them again */
6705 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6706 }
6707
6708 /* Schedule downclock */
3dec0095
DV		 6709 mod_timer(&intel_crtc->idle_timer, jiffies +
6710 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6711}
6712
6713static void intel_decrease_pllclock(struct drm_crtc *crtc)
6714{
6715 struct drm_device *dev = crtc->dev;
6716 drm_i915_private_t *dev_priv = dev->dev_private;
6717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6718 int pipe = intel_crtc->pipe;
9db4a9c7 6719 int dpll_reg = DPLL(pipe);
652c393a
JB		 6720 int dpll = I915_READ(dpll_reg);
6721
bad720ff 6722 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6723 return;
6724
6725 if (!dev_priv->lvds_downclock_avail)
6726 return;
6727
6728 /*
6729 * Since this is called by a timer, we should never get here in
6730 * the manual case.
6731 */
6732 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6733 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6734
6735 /* Unlock panel regs */
4a655f04
JB		 6736 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6737 PANEL_UNLOCK_REGS);
652c393a
JB		 6738
6739 dpll |= DISPLAY_RATE_SELECT_FPA1;
6740 I915_WRITE(dpll_reg, dpll);
9d0498a2 6741 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6742 dpll = I915_READ(dpll_reg);
6743 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6744 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6745
6746 /* ...and lock them again */
6747 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6748 }
6749
6750}
6751
6752/**
6753 * intel_idle_update - adjust clocks for idleness
6754 * @work: work struct
6755 *
6756 * Either the GPU or display (or both) went idle. Check the busy status
6757 * here and adjust the CRTC and GPU clocks as necessary.
6758 */
6759static void intel_idle_update(struct work_struct *work)
6760{
6761 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6762 idle_work);
6763 struct drm_device *dev = dev_priv->dev;
6764 struct drm_crtc *crtc;
6765 struct intel_crtc *intel_crtc;
6766
6767 if (!i915_powersave)
6768 return;
6769
6770 mutex_lock(&dev->struct_mutex);
6771
7648fa99
JB		 6772 i915_update_gfx_val(dev_priv);
6773
652c393a
JB		 6774 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6775 /* Skip inactive CRTCs */
6776 if (!crtc->fb)
6777 continue;
6778
6779 intel_crtc = to_intel_crtc(crtc);
6780 if (!intel_crtc->busy)
6781 intel_decrease_pllclock(crtc);
6782 }
6783
45ac22c8 6784
652c393a
JB		 6785 mutex_unlock(&dev->struct_mutex);
6786}
6787
6788/**
6789 * intel_mark_busy - mark the GPU and possibly the display busy
6790 * @dev: drm device
6791 * @obj: object we're operating on
6792 *
6793 * Callers can use this function to indicate that the GPU is busy processing
6794 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6795 * buffer), we'll also mark the display as busy, so we know to increase its
6796 * clock frequency.
6797 */
05394f39 6798void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6799{
6800 drm_i915_private_t *dev_priv = dev->dev_private;
6801 struct drm_crtc *crtc = NULL;
6802 struct intel_framebuffer *intel_fb;
6803 struct intel_crtc *intel_crtc;
6804
5e17ee74
ZW		 6805 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6806 return;
6807
18b2190c 6808 if (!dev_priv->busy)
28cf798f 6809 dev_priv->busy = true;
18b2190c 6810 else
28cf798f
CW		 6811 mod_timer(&dev_priv->idle_timer, jiffies +
6812 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6813
6814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6815 if (!crtc->fb)
6816 continue;
6817
6818 intel_crtc = to_intel_crtc(crtc);
6819 intel_fb = to_intel_framebuffer(crtc->fb);
6820 if (intel_fb->obj == obj) {
6821 if (!intel_crtc->busy) {
6822 /* Non-busy -> busy, upclock */
3dec0095 6823 intel_increase_pllclock(crtc);
652c393a
JB		 6824 intel_crtc->busy = true;
6825 } else {
6826 /* Busy -> busy, put off timer */
6827 mod_timer(&intel_crtc->idle_timer, jiffies +
6828 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6829 }
6830 }
6831 }
6832}
6833
79e53945
JB		 6834static void intel_crtc_destroy(struct drm_crtc *crtc)
6835{
6836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6837 struct drm_device *dev = crtc->dev;
6838 struct intel_unpin_work *work;
6839 unsigned long flags;
6840
6841 spin_lock_irqsave(&dev->event_lock, flags);
6842 work = intel_crtc->unpin_work;
6843 intel_crtc->unpin_work = NULL;
6844 spin_unlock_irqrestore(&dev->event_lock, flags);
6845
6846 if (work) {
6847 cancel_work_sync(&work->work);
6848 kfree(work);
6849 }
79e53945
JB		 6850
6851 drm_crtc_cleanup(crtc);
67e77c5a 6852
79e53945
JB		 6853 kfree(intel_crtc);
6854}
6855
6b95a207
KH		 6856static void intel_unpin_work_fn(struct work_struct *__work)
6857{
6858 struct intel_unpin_work *work =
6859 container_of(__work, struct intel_unpin_work, work);
6860
6861 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6862 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6863 drm_gem_object_unreference(&work->pending_flip_obj->base);
6864 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6865
7782de3b 6866 intel_update_fbc(work->dev);
6b95a207
KH		 6867 mutex_unlock(&work->dev->struct_mutex);
6868 kfree(work);
6869}
6870
1afe3e9d 6871static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6872 struct drm_crtc *crtc)
6b95a207
KH		 6873{
6874 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 struct intel_unpin_work *work;
05394f39 6877 struct drm_i915_gem_object *obj;
6b95a207 6878 struct drm_pending_vblank_event *e;
49b14a5c 6879 struct timeval tnow, tvbl;
6b95a207
KH		 6880 unsigned long flags;
6881
6882 /* Ignore early vblank irqs */
6883 if (intel_crtc == NULL)
6884 return;
6885
49b14a5c
MK		 6886 do_gettimeofday(&tnow);
6887
6b95a207
KH		 6888 spin_lock_irqsave(&dev->event_lock, flags);
6889 work = intel_crtc->unpin_work;
6890 if (work == NULL || !work->pending) {
6891 spin_unlock_irqrestore(&dev->event_lock, flags);
6892 return;
6893 }
6894
6895 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6896
6897 if (work->event) {
6898 e = work->event;
49b14a5c 6899 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6900
6901 /* Called before vblank count and timestamps have
6902 * been updated for the vblank interval of flip
6903 * completion? Need to increment vblank count and
6904 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6905 * to account for this. We assume this happened if we
6906 * get called over 0.9 frame durations after the last
6907 * timestamped vblank.
6908 *
6909 * This calculation can not be used with vrefresh rates
6910 * below 5Hz (10Hz to be on the safe side) without
6911 * promoting to 64 integers.
0af7e4df 6912 */
49b14a5c
MK		 6913 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6914 9 * crtc->framedur_ns) {
0af7e4df 6915 e->event.sequence++;
49b14a5c
MK		 6916 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6917 crtc->framedur_ns);
0af7e4df
MK		 6918 }
6919
49b14a5c
MK		 6920 e->event.tv_sec = tvbl.tv_sec;
6921 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6922
6b95a207
KH		 6923 list_add_tail(&e->base.link,
6924 &e->base.file_priv->event_list);
6925 wake_up_interruptible(&e->base.file_priv->event_wait);
6926 }
6927
0af7e4df
MK		 6928 drm_vblank_put(dev, intel_crtc->pipe);
6929
6b95a207
KH		 6930 spin_unlock_irqrestore(&dev->event_lock, flags);
6931
05394f39 6932 obj = work->old_fb_obj;
d9e86c0e 6933
e59f2bac 6934 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6935 &obj->pending_flip.counter);
6936 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6937 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6938
6b95a207 6939 schedule_work(&work->work);
e5510fac
JB		 6940
6941 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6942}
6943
1afe3e9d
JB		 6944void intel_finish_page_flip(struct drm_device *dev, int pipe)
6945{
6946 drm_i915_private_t *dev_priv = dev->dev_private;
6947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6948
49b14a5c 6949 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6950}
6951
6952void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6953{
6954 drm_i915_private_t *dev_priv = dev->dev_private;
6955 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6956
49b14a5c 6957 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6958}
6959
6b95a207
KH		 6960void intel_prepare_page_flip(struct drm_device *dev, int plane)
6961{
6962 drm_i915_private_t *dev_priv = dev->dev_private;
6963 struct intel_crtc *intel_crtc =
6964 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6965 unsigned long flags;
6966
6967 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6968 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6969 if ((++intel_crtc->unpin_work->pending) > 1)
6970 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6971 } else {
6972 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6973 }
6b95a207
KH		 6974 spin_unlock_irqrestore(&dev->event_lock, flags);
6975}
6976
8c9f3aaf
JB		 6977static int intel_gen2_queue_flip(struct drm_device *dev,
6978 struct drm_crtc *crtc,
6979 struct drm_framebuffer *fb,
6980 struct drm_i915_gem_object *obj)
6981{
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6984 unsigned long offset;
6985 u32 flip_mask;
6986 int ret;
6987
6988 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6989 if (ret)
6990 goto out;
6991
6992 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6993 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6994
6995 ret = BEGIN_LP_RING(6);
6996 if (ret)
6997 goto out;
6998
6999 /* Can't queue multiple flips, so wait for the previous
7000 * one to finish before executing the next.
7001 */
7002 if (intel_crtc->plane)
7003 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7004 else
7005 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7006 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7007 OUT_RING(MI_NOOP);
7008 OUT_RING(MI_DISPLAY_FLIP |
7009 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7010 OUT_RING(fb->pitch);
7011 OUT_RING(obj->gtt_offset + offset);
7012 OUT_RING(MI_NOOP);
7013 ADVANCE_LP_RING();
7014out:
7015 return ret;
7016}
7017
7018static int intel_gen3_queue_flip(struct drm_device *dev,
7019 struct drm_crtc *crtc,
7020 struct drm_framebuffer *fb,
7021 struct drm_i915_gem_object *obj)
7022{
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7025 unsigned long offset;
7026 u32 flip_mask;
7027 int ret;
7028
7029 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7030 if (ret)
7031 goto out;
7032
7033 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7034 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7035
7036 ret = BEGIN_LP_RING(6);
7037 if (ret)
7038 goto out;
7039
7040 if (intel_crtc->plane)
7041 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7042 else
7043 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7044 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7045 OUT_RING(MI_NOOP);
7046 OUT_RING(MI_DISPLAY_FLIP_I915 |
7047 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7048 OUT_RING(fb->pitch);
7049 OUT_RING(obj->gtt_offset + offset);
7050 OUT_RING(MI_NOOP);
7051
7052 ADVANCE_LP_RING();
7053out:
7054 return ret;
7055}
7056
7057static int intel_gen4_queue_flip(struct drm_device *dev,
7058 struct drm_crtc *crtc,
7059 struct drm_framebuffer *fb,
7060 struct drm_i915_gem_object *obj)
7061{
7062 struct drm_i915_private *dev_priv = dev->dev_private;
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064 uint32_t pf, pipesrc;
7065 int ret;
7066
7067 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7068 if (ret)
7069 goto out;
7070
7071 ret = BEGIN_LP_RING(4);
7072 if (ret)
7073 goto out;
7074
7075 /* i965+ uses the linear or tiled offsets from the
7076 * Display Registers (which do not change across a page-flip)
7077 * so we need only reprogram the base address.
7078 */
7079 OUT_RING(MI_DISPLAY_FLIP |
7080 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7081 OUT_RING(fb->pitch);
7082 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7083
7084 /* XXX Enabling the panel-fitter across page-flip is so far
7085 * untested on non-native modes, so ignore it for now.
7086 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7087 */
7088 pf = 0;
7089 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7090 OUT_RING(pf | pipesrc);
7091 ADVANCE_LP_RING();
7092out:
7093 return ret;
7094}
7095
7096static int intel_gen6_queue_flip(struct drm_device *dev,
7097 struct drm_crtc *crtc,
7098 struct drm_framebuffer *fb,
7099 struct drm_i915_gem_object *obj)
7100{
7101 struct drm_i915_private *dev_priv = dev->dev_private;
7102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7103 uint32_t pf, pipesrc;
7104 int ret;
7105
7106 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7107 if (ret)
7108 goto out;
7109
7110 ret = BEGIN_LP_RING(4);
7111 if (ret)
7112 goto out;
7113
7114 OUT_RING(MI_DISPLAY_FLIP |
7115 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7116 OUT_RING(fb->pitch | obj->tiling_mode);
7117 OUT_RING(obj->gtt_offset);
7118
7119 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7120 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7121 OUT_RING(pf | pipesrc);
7122 ADVANCE_LP_RING();
7123out:
7124 return ret;
7125}
7126
7c9017e5
JB		 7127/*
7128 * On gen7 we currently use the blit ring because (in early silicon at least)
7129 * the render ring doesn't give us interrpts for page flip completion, which
7130 * means clients will hang after the first flip is queued. Fortunately the
7131 * blit ring generates interrupts properly, so use it instead.
7132 */
7133static int intel_gen7_queue_flip(struct drm_device *dev,
7134 struct drm_crtc *crtc,
7135 struct drm_framebuffer *fb,
7136 struct drm_i915_gem_object *obj)
7137{
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7141 int ret;
7142
7143 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7144 if (ret)
7145 goto out;
7146
7147 ret = intel_ring_begin(ring, 4);
7148 if (ret)
7149 goto out;
7150
7151 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7152 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7153 intel_ring_emit(ring, (obj->gtt_offset));
7154 intel_ring_emit(ring, (MI_NOOP));
7155 intel_ring_advance(ring);
7156out:
7157 return ret;
7158}
7159
8c9f3aaf
JB		 7160static int intel_default_queue_flip(struct drm_device *dev,
7161 struct drm_crtc *crtc,
7162 struct drm_framebuffer *fb,
7163 struct drm_i915_gem_object *obj)
7164{
7165 return -ENODEV;
7166}
7167
6b95a207
KH		 7168static int intel_crtc_page_flip(struct drm_crtc *crtc,
7169 struct drm_framebuffer *fb,
7170 struct drm_pending_vblank_event *event)
7171{
7172 struct drm_device *dev = crtc->dev;
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 struct intel_framebuffer *intel_fb;
05394f39 7175 struct drm_i915_gem_object *obj;
6b95a207
KH		 7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 struct intel_unpin_work *work;
8c9f3aaf 7178 unsigned long flags;
52e68630 7179 int ret;
6b95a207
KH		 7180
7181 work = kzalloc(sizeof *work, GFP_KERNEL);
7182 if (work == NULL)
7183 return -ENOMEM;
7184
6b95a207
KH		 7185 work->event = event;
7186 work->dev = crtc->dev;
7187 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7188 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7189 INIT_WORK(&work->work, intel_unpin_work_fn);
7190
7191 /* We borrow the event spin lock for protecting unpin_work */
7192 spin_lock_irqsave(&dev->event_lock, flags);
7193 if (intel_crtc->unpin_work) {
7194 spin_unlock_irqrestore(&dev->event_lock, flags);
7195 kfree(work);
468f0b44
CW		 7196
7197 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7198 return -EBUSY;
7199 }
7200 intel_crtc->unpin_work = work;
7201 spin_unlock_irqrestore(&dev->event_lock, flags);
7202
7203 intel_fb = to_intel_framebuffer(fb);
7204 obj = intel_fb->obj;
7205
468f0b44 7206 mutex_lock(&dev->struct_mutex);
6b95a207 7207
75dfca80 7208 /* Reference the objects for the scheduled work. */
05394f39
CW		 7209 drm_gem_object_reference(&work->old_fb_obj->base);
7210 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7211
7212 crtc->fb = fb;
96b099fd
CW		 7213
7214 ret = drm_vblank_get(dev, intel_crtc->pipe);
7215 if (ret)
7216 goto cleanup_objs;
7217
e1f99ce6 7218 work->pending_flip_obj = obj;
e1f99ce6 7219
4e5359cd
SF		 7220 work->enable_stall_check = true;
7221
e1f99ce6
CW		 7222 /* Block clients from rendering to the new back buffer until
7223 * the flip occurs and the object is no longer visible.
7224 */
05394f39 7225 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7226
8c9f3aaf
JB		 7227 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7228 if (ret)
7229 goto cleanup_pending;
6b95a207 7230
7782de3b 7231 intel_disable_fbc(dev);
6b95a207
KH		 7232 mutex_unlock(&dev->struct_mutex);
7233
e5510fac
JB		 7234 trace_i915_flip_request(intel_crtc->plane, obj);
7235
6b95a207 7236 return 0;
96b099fd 7237
8c9f3aaf
JB		 7238cleanup_pending:
7239 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 7240cleanup_objs:
05394f39
CW		 7241 drm_gem_object_unreference(&work->old_fb_obj->base);
7242 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7243 mutex_unlock(&dev->struct_mutex);
7244
7245 spin_lock_irqsave(&dev->event_lock, flags);
7246 intel_crtc->unpin_work = NULL;
7247 spin_unlock_irqrestore(&dev->event_lock, flags);
7248
7249 kfree(work);
7250
7251 return ret;
6b95a207
KH		 7252}
7253
47f1c6c9
CW		 7254static void intel_sanitize_modesetting(struct drm_device *dev,
7255 int pipe, int plane)
7256{
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 u32 reg, val;
7259
7260 if (HAS_PCH_SPLIT(dev))
7261 return;
7262
7263 /* Who knows what state these registers were left in by the BIOS or
7264 * grub?
7265 *
7266 * If we leave the registers in a conflicting state (e.g. with the
7267 * display plane reading from the other pipe than the one we intend
7268 * to use) then when we attempt to teardown the active mode, we will
7269 * not disable the pipes and planes in the correct order -- leaving
7270 * a plane reading from a disabled pipe and possibly leading to
7271 * undefined behaviour.
7272 */
7273
7274 reg = DSPCNTR(plane);
7275 val = I915_READ(reg);
7276
7277 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7278 return;
7279 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7280 return;
7281
7282 /* This display plane is active and attached to the other CPU pipe. */
7283 pipe = !pipe;
7284
7285 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7286 intel_disable_plane(dev_priv, plane, pipe);
7287 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7288}
79e53945 7289
f6e5b160
CW		 7290static void intel_crtc_reset(struct drm_crtc *crtc)
7291{
7292 struct drm_device *dev = crtc->dev;
7293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7294
7295 /* Reset flags back to the 'unknown' status so that they
7296 * will be correctly set on the initial modeset.
7297 */
7298 intel_crtc->dpms_mode = -1;
7299
7300 /* We need to fix up any BIOS configuration that conflicts with
7301 * our expectations.
7302 */
7303 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7304}
7305
7306static struct drm_crtc_helper_funcs intel_helper_funcs = {
7307 .dpms = intel_crtc_dpms,
7308 .mode_fixup = intel_crtc_mode_fixup,
7309 .mode_set = intel_crtc_mode_set,
7310 .mode_set_base = intel_pipe_set_base,
7311 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7312 .load_lut = intel_crtc_load_lut,
7313 .disable = intel_crtc_disable,
7314};
7315
7316static const struct drm_crtc_funcs intel_crtc_funcs = {
7317 .reset = intel_crtc_reset,
7318 .cursor_set = intel_crtc_cursor_set,
7319 .cursor_move = intel_crtc_cursor_move,
7320 .gamma_set = intel_crtc_gamma_set,
7321 .set_config = drm_crtc_helper_set_config,
7322 .destroy = intel_crtc_destroy,
7323 .page_flip = intel_crtc_page_flip,
7324};
7325
b358d0a6 7326static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7327{
22fd0fab 7328 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7329 struct intel_crtc *intel_crtc;
7330 int i;
7331
7332 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7333 if (intel_crtc == NULL)
7334 return;
7335
7336 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7337
7338 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7339 for (i = 0; i < 256; i++) {
7340 intel_crtc->lut_r[i] = i;
7341 intel_crtc->lut_g[i] = i;
7342 intel_crtc->lut_b[i] = i;
7343 }
7344
80824003
JB		 7345 /* Swap pipes & planes for FBC on pre-965 */
7346 intel_crtc->pipe = pipe;
7347 intel_crtc->plane = pipe;
e2e767ab 7348 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7349 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7350 intel_crtc->plane = !pipe;
80824003
JB		 7351 }
7352
22fd0fab
JB		 7353 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7354 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7355 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7356 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7357
5d1d0cc8 7358 intel_crtc_reset(&intel_crtc->base);
04dbff52 7359 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7360 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7361
7362 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7363 if (pipe == 2 && IS_IVYBRIDGE(dev))
7364 intel_crtc->no_pll = true;
7e7d76c3
JB		 7365 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7366 intel_helper_funcs.commit = ironlake_crtc_commit;
7367 } else {
7368 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7369 intel_helper_funcs.commit = i9xx_crtc_commit;
7370 }
7371
79e53945
JB		 7372 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7373
652c393a
JB		 7374 intel_crtc->busy = false;
7375
7376 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7377 (unsigned long)intel_crtc);
79e53945
JB		 7378}
7379
08d7b3d1 7380int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7381 struct drm_file *file)
08d7b3d1
CW		 7382{
7383 drm_i915_private_t *dev_priv = dev->dev_private;
7384 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7385 struct drm_mode_object *drmmode_obj;
7386 struct intel_crtc *crtc;
08d7b3d1
CW		 7387
7388 if (!dev_priv) {
7389 DRM_ERROR("called with no initialization\n");
7390 return -EINVAL;
7391 }
7392
c05422d5
DV		 7393 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7394 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7395
c05422d5 7396 if (!drmmode_obj) {
08d7b3d1
CW		 7397 DRM_ERROR("no such CRTC id\n");
7398 return -EINVAL;
7399 }
7400
c05422d5
DV		 7401 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7402 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7403
c05422d5 7404 return 0;
08d7b3d1
CW		 7405}
7406
c5e4df33 7407static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7408{
4ef69c7a 7409 struct intel_encoder *encoder;
79e53945 7410 int index_mask = 0;
79e53945
JB		 7411 int entry = 0;
7412
4ef69c7a
CW		 7413 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7414 if (type_mask & encoder->clone_mask)
79e53945
JB		 7415 index_mask |= (1 << entry);
7416 entry++;
7417 }
4ef69c7a 7418
79e53945
JB		 7419 return index_mask;
7420}
7421
4d302442
CW		 7422static bool has_edp_a(struct drm_device *dev)
7423{
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425
7426 if (!IS_MOBILE(dev))
7427 return false;
7428
7429 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7430 return false;
7431
7432 if (IS_GEN5(dev) &&
7433 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7434 return false;
7435
7436 return true;
7437}
7438
79e53945
JB		 7439static void intel_setup_outputs(struct drm_device *dev)
7440{
725e30ad 7441 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7442 struct intel_encoder *encoder;
cb0953d7 7443 bool dpd_is_edp = false;
c5d1b51d 7444 bool has_lvds = false;
79e53945 7445
541998a1 7446 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7447 has_lvds = intel_lvds_init(dev);
7448 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7449 /* disable the panel fitter on everything but LVDS */
7450 I915_WRITE(PFIT_CONTROL, 0);
7451 }
79e53945 7452
bad720ff 7453 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7454 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7455
4d302442 7456 if (has_edp_a(dev))
32f9d658
ZW		 7457 intel_dp_init(dev, DP_A);
7458
cb0953d7
AJ		 7459 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7460 intel_dp_init(dev, PCH_DP_D);
7461 }
7462
7463 intel_crt_init(dev);
7464
7465 if (HAS_PCH_SPLIT(dev)) {
7466 int found;
7467
30ad48b7 7468 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7469 /* PCH SDVOB multiplex with HDMIB */
7470 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7471 if (!found)
7472 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7473 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7474 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7475 }
7476
7477 if (I915_READ(HDMIC) & PORT_DETECTED)
7478 intel_hdmi_init(dev, HDMIC);
7479
7480 if (I915_READ(HDMID) & PORT_DETECTED)
7481 intel_hdmi_init(dev, HDMID);
7482
5eb08b69
ZW		 7483 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7484 intel_dp_init(dev, PCH_DP_C);
7485
cb0953d7 7486 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7487 intel_dp_init(dev, PCH_DP_D);
7488
103a196f 7489 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7490 bool found = false;
7d57382e 7491
725e30ad 7492 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7493 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7494 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7495 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7496 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7497 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7498 }
27185ae1 7499
b01f2c3a
JB		 7500 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7501 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7502 intel_dp_init(dev, DP_B);
b01f2c3a 7503 }
725e30ad 7504 }
13520b05
KH		 7505
7506 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7507
b01f2c3a
JB		 7508 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7509 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7510 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7511 }
27185ae1
ML		 7512
7513 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7514
b01f2c3a
JB		 7515 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7516 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7517 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7518 }
7519 if (SUPPORTS_INTEGRATED_DP(dev)) {
7520 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7521 intel_dp_init(dev, DP_C);
b01f2c3a 7522 }
725e30ad 7523 }
27185ae1 7524
b01f2c3a
JB		 7525 if (SUPPORTS_INTEGRATED_DP(dev) &&
7526 (I915_READ(DP_D) & DP_DETECTED)) {
7527 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7528 intel_dp_init(dev, DP_D);
b01f2c3a 7529 }
bad720ff 7530 } else if (IS_GEN2(dev))
79e53945
JB		 7531 intel_dvo_init(dev);
7532
103a196f 7533 if (SUPPORTS_TV(dev))
79e53945
JB		 7534 intel_tv_init(dev);
7535
4ef69c7a
CW		 7536 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7537 encoder->base.possible_crtcs = encoder->crtc_mask;
7538 encoder->base.possible_clones =
7539 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7540 }
47356eb6 7541
2c7111db
CW		 7542 /* disable all the possible outputs/crtcs before entering KMS mode */
7543 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7544
7545 if (HAS_PCH_SPLIT(dev))
7546 ironlake_init_pch_refclk(dev);
79e53945
JB		 7547}
7548
7549static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7550{
7551 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7552
7553 drm_framebuffer_cleanup(fb);
05394f39 7554 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7555
7556 kfree(intel_fb);
7557}
7558
7559static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7560 struct drm_file *file,
79e53945
JB		 7561 unsigned int *handle)
7562{
7563 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7564 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7565
05394f39 7566 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7567}
7568
7569static const struct drm_framebuffer_funcs intel_fb_funcs = {
7570 .destroy = intel_user_framebuffer_destroy,
7571 .create_handle = intel_user_framebuffer_create_handle,
7572};
7573
38651674
DA		 7574int intel_framebuffer_init(struct drm_device *dev,
7575 struct intel_framebuffer *intel_fb,
7576 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7577 struct drm_i915_gem_object *obj)
79e53945 7578{
79e53945
JB		 7579 int ret;
7580
05394f39 7581 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7582 return -EINVAL;
7583
7584 if (mode_cmd->pitch & 63)
7585 return -EINVAL;
7586
7587 switch (mode_cmd->bpp) {
7588 case 8:
7589 case 16:
b5626747
JB		 7590 /* Only pre-ILK can handle 5:5:5 */
7591 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7592 return -EINVAL;
7593 break;
7594
57cd6508
CW		 7595 case 24:
7596 case 32:
7597 break;
7598 default:
7599 return -EINVAL;
7600 }
7601
79e53945
JB		 7602 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7603 if (ret) {
7604 DRM_ERROR("framebuffer init failed %d\n", ret);
7605 return ret;
7606 }
7607
7608 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7609 intel_fb->obj = obj;
79e53945
JB		 7610 return 0;
7611}
7612
79e53945
JB		 7613static struct drm_framebuffer *
7614intel_user_framebuffer_create(struct drm_device *dev,
7615 struct drm_file *filp,
7616 struct drm_mode_fb_cmd *mode_cmd)
7617{
05394f39 7618 struct drm_i915_gem_object *obj;
79e53945 7619
05394f39 7620 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7621 if (&obj->base == NULL)
cce13ff7 7622 return ERR_PTR(-ENOENT);
79e53945 7623
d2dff872 7624 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7625}
7626
79e53945 7627static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7628 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7629 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7630};
7631
05394f39 7632static struct drm_i915_gem_object *
aa40d6bb 7633intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7634{
05394f39 7635 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7636 int ret;
7637
2c34b850
BW		 7638 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7639
aa40d6bb
ZN		 7640 ctx = i915_gem_alloc_object(dev, 4096);
7641 if (!ctx) {
9ea8d059
CW		 7642 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7643 return NULL;
7644 }
7645
75e9e915 7646 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7647 if (ret) {
7648 DRM_ERROR("failed to pin power context: %d\n", ret);
7649 goto err_unref;
7650 }
7651
aa40d6bb 7652 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7653 if (ret) {
7654 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7655 goto err_unpin;
7656 }
9ea8d059 7657
aa40d6bb 7658 return ctx;
9ea8d059
CW		 7659
7660err_unpin:
aa40d6bb 7661 i915_gem_object_unpin(ctx);
9ea8d059 7662err_unref:
05394f39 7663 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7664 mutex_unlock(&dev->struct_mutex);
7665 return NULL;
7666}
7667
7648fa99
JB		 7668bool ironlake_set_drps(struct drm_device *dev, u8 val)
7669{
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 u16 rgvswctl;
7672
7673 rgvswctl = I915_READ16(MEMSWCTL);
7674 if (rgvswctl & MEMCTL_CMD_STS) {
7675 DRM_DEBUG("gpu busy, RCS change rejected\n");
7676 return false; /* still busy with another command */
7677 }
7678
7679 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7680 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7681 I915_WRITE16(MEMSWCTL, rgvswctl);
7682 POSTING_READ16(MEMSWCTL);
7683
7684 rgvswctl |= MEMCTL_CMD_STS;
7685 I915_WRITE16(MEMSWCTL, rgvswctl);
7686
7687 return true;
7688}
7689
f97108d1
JB		 7690void ironlake_enable_drps(struct drm_device *dev)
7691{
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7693 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7694 u8 fmax, fmin, fstart, vstart;
f97108d1 7695
ea056c14
JB		 7696 /* Enable temp reporting */
7697 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7698 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7699
f97108d1
JB		 7700 /* 100ms RC evaluation intervals */
7701 I915_WRITE(RCUPEI, 100000);
7702 I915_WRITE(RCDNEI, 100000);
7703
7704 /* Set max/min thresholds to 90ms and 80ms respectively */
7705 I915_WRITE(RCBMAXAVG, 90000);
7706 I915_WRITE(RCBMINAVG, 80000);
7707
7708 I915_WRITE(MEMIHYST, 1);
7709
7710 /* Set up min, max, and cur for interrupt handling */
7711 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7712 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7713 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7714 MEMMODE_FSTART_SHIFT;
7648fa99 7715
f97108d1
JB		 7716 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7717 PXVFREQ_PX_SHIFT;
7718
80dbf4b7 7719 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7720 dev_priv->fstart = fstart;
7721
80dbf4b7 7722 dev_priv->max_delay = fstart;
f97108d1
JB		 7723 dev_priv->min_delay = fmin;
7724 dev_priv->cur_delay = fstart;
7725
80dbf4b7
JB		 7726 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7727 fmax, fmin, fstart);
7648fa99 7728
f97108d1
JB		 7729 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7730
7731 /*
7732 * Interrupts will be enabled in ironlake_irq_postinstall
7733 */
7734
7735 I915_WRITE(VIDSTART, vstart);
7736 POSTING_READ(VIDSTART);
7737
7738 rgvmodectl |= MEMMODE_SWMODE_EN;
7739 I915_WRITE(MEMMODECTL, rgvmodectl);
7740
481b6af3 7741 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7742 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7743 msleep(1);
7744
7648fa99 7745 ironlake_set_drps(dev, fstart);
f97108d1 7746
7648fa99
JB		 7747 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7748 I915_READ(0x112e0);
7749 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7750 dev_priv->last_count2 = I915_READ(0x112f4);
7751 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7752}
7753
7754void ironlake_disable_drps(struct drm_device *dev)
7755{
7756 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7757 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7758
7759 /* Ack interrupts, disable EFC interrupt */
7760 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7761 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7762 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7763 I915_WRITE(DEIIR, DE_PCU_EVENT);
7764 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7765
7766 /* Go back to the starting frequency */
7648fa99 7767 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7768 msleep(1);
7769 rgvswctl |= MEMCTL_CMD_STS;
7770 I915_WRITE(MEMSWCTL, rgvswctl);
7771 msleep(1);
7772
7773}
7774
3b8d8d91
JB		 7775void gen6_set_rps(struct drm_device *dev, u8 val)
7776{
7777 struct drm_i915_private *dev_priv = dev->dev_private;
7778 u32 swreq;
7779
7780 swreq = (val & 0x3ff) << 25;
7781 I915_WRITE(GEN6_RPNSWREQ, swreq);
7782}
7783
7784void gen6_disable_rps(struct drm_device *dev)
7785{
7786 struct drm_i915_private *dev_priv = dev->dev_private;
7787
7788 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7789 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7790 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 7791 /* Complete PM interrupt masking here doesn't race with the rps work
7792 * item again unmasking PM interrupts because that is using a different
7793 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7794 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 7795
7796 spin_lock_irq(&dev_priv->rps_lock);
7797 dev_priv->pm_iir = 0;
7798 spin_unlock_irq(&dev_priv->rps_lock);
7799
3b8d8d91
JB		 7800 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7801}
7802
7648fa99
JB		 7803static unsigned long intel_pxfreq(u32 vidfreq)
7804{
7805 unsigned long freq;
7806 int div = (vidfreq & 0x3f0000) >> 16;
7807 int post = (vidfreq & 0x3000) >> 12;
7808 int pre = (vidfreq & 0x7);
7809
7810 if (!pre)
7811 return 0;
7812
7813 freq = ((div * 133333) / ((1<<post) * pre));
7814
7815 return freq;
7816}
7817
7818void intel_init_emon(struct drm_device *dev)
7819{
7820 struct drm_i915_private *dev_priv = dev->dev_private;
7821 u32 lcfuse;
7822 u8 pxw[16];
7823 int i;
7824
7825 /* Disable to program */
7826 I915_WRITE(ECR, 0);
7827 POSTING_READ(ECR);
7828
7829 /* Program energy weights for various events */
7830 I915_WRITE(SDEW, 0x15040d00);
7831 I915_WRITE(CSIEW0, 0x007f0000);
7832 I915_WRITE(CSIEW1, 0x1e220004);
7833 I915_WRITE(CSIEW2, 0x04000004);
7834
7835 for (i = 0; i < 5; i++)
7836 I915_WRITE(PEW + (i * 4), 0);
7837 for (i = 0; i < 3; i++)
7838 I915_WRITE(DEW + (i * 4), 0);
7839
7840 /* Program P-state weights to account for frequency power adjustment */
7841 for (i = 0; i < 16; i++) {
7842 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7843 unsigned long freq = intel_pxfreq(pxvidfreq);
7844 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7845 PXVFREQ_PX_SHIFT;
7846 unsigned long val;
7847
7848 val = vid * vid;
7849 val *= (freq / 1000);
7850 val *= 255;
7851 val /= (127*127*900);
7852 if (val > 0xff)
7853 DRM_ERROR("bad pxval: %ld\n", val);
7854 pxw[i] = val;
7855 }
7856 /* Render standby states get 0 weight */
7857 pxw[14] = 0;
7858 pxw[15] = 0;
7859
7860 for (i = 0; i < 4; i++) {
7861 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7862 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7863 I915_WRITE(PXW + (i * 4), val);
7864 }
7865
7866 /* Adjust magic regs to magic values (more experimental results) */
7867 I915_WRITE(OGW0, 0);
7868 I915_WRITE(OGW1, 0);
7869 I915_WRITE(EG0, 0x00007f00);
7870 I915_WRITE(EG1, 0x0000000e);
7871 I915_WRITE(EG2, 0x000e0000);
7872 I915_WRITE(EG3, 0x68000300);
7873 I915_WRITE(EG4, 0x42000000);
7874 I915_WRITE(EG5, 0x00140031);
7875 I915_WRITE(EG6, 0);
7876 I915_WRITE(EG7, 0);
7877
7878 for (i = 0; i < 8; i++)
7879 I915_WRITE(PXWL + (i * 4), 0);
7880
7881 /* Enable PMON + select events */
7882 I915_WRITE(ECR, 0x80000019);
7883
7884 lcfuse = I915_READ(LCFUSE02);
7885
7886 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7887}
7888
3b8d8d91 7889void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7890{
a6044e23
JB		 7891 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7892 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7893 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7894 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7895 int i;
7896
7897 /* Here begins a magic sequence of register writes to enable
7898 * auto-downclocking.
7899 *
7900 * Perhaps there might be some value in exposing these to
7901 * userspace...
7902 */
7903 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7904 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7905 gen6_gt_force_wake_get(dev_priv);
8fd26859 7906
3b8d8d91 7907 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7908 I915_WRITE(GEN6_RC_CONTROL, 0);
7909
7910 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7911 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7912 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7913 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7914 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7915
7916 for (i = 0; i < I915_NUM_RINGS; i++)
7917 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7918
7919 I915_WRITE(GEN6_RC_SLEEP, 0);
7920 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7921 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7922 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7923 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7924
7df8721b
JB		 7925 if (i915_enable_rc6)
7926 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7927 GEN6_RC_CTL_RC6_ENABLE;
7928
8fd26859 7929 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7930 rc6_mask |
9c3d2f7f 7931 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7932 GEN6_RC_CTL_HW_ENABLE);
7933
3b8d8d91 7934 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7935 GEN6_FREQUENCY(10) |
7936 GEN6_OFFSET(0) |
7937 GEN6_AGGRESSIVE_TURBO);
7938 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7939 GEN6_FREQUENCY(12));
7940
7941 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7942 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7943 18 << 24 |
7944 6 << 16);
ccab5c82
JB		 7945 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7946 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7947 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7948 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7949 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7950 I915_WRITE(GEN6_RP_CONTROL,
7951 GEN6_RP_MEDIA_TURBO |
7952 GEN6_RP_USE_NORMAL_FREQ |
7953 GEN6_RP_MEDIA_IS_GFX |
7954 GEN6_RP_ENABLE |
ccab5c82
JB		 7955 GEN6_RP_UP_BUSY_AVG |
7956 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7957
7958 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7959 500))
7960 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7961
7962 I915_WRITE(GEN6_PCODE_DATA, 0);
7963 I915_WRITE(GEN6_PCODE_MAILBOX,
7964 GEN6_PCODE_READY |
7965 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7966 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7967 500))
7968 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7969
a6044e23
JB		 7970 min_freq = (rp_state_cap & 0xff0000) >> 16;
7971 max_freq = rp_state_cap & 0xff;
7972 cur_freq = (gt_perf_status & 0xff00) >> 8;
7973
7974 /* Check for overclock support */
7975 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7976 500))
7977 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7978 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7979 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7980 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7981 500))
7982 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7983 if (pcu_mbox & (1<<31)) { /* OC supported */
7984 max_freq = pcu_mbox & 0xff;
e281fcaa 7985 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7986 }
7987
7988 /* In units of 100MHz */
7989 dev_priv->max_delay = max_freq;
7990 dev_priv->min_delay = min_freq;
7991 dev_priv->cur_delay = cur_freq;
7992
8fd26859
CW		 7993 /* requires MSI enabled */
7994 I915_WRITE(GEN6_PMIER,
7995 GEN6_PM_MBOX_EVENT |
7996 GEN6_PM_THERMAL_EVENT |
7997 GEN6_PM_RP_DOWN_TIMEOUT |
7998 GEN6_PM_RP_UP_THRESHOLD |
7999 GEN6_PM_RP_DOWN_THRESHOLD |
8000 GEN6_PM_RP_UP_EI_EXPIRED |
8001 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8002 spin_lock_irq(&dev_priv->rps_lock);
8003 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8004 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8005 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8006 /* enable all PM interrupts */
8007 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8008
fcca7926 8009 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8010 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8011}
8012
23b2f8bb
JB		 8013void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8014{
8015 int min_freq = 15;
8016 int gpu_freq, ia_freq, max_ia_freq;
8017 int scaling_factor = 180;
8018
8019 max_ia_freq = cpufreq_quick_get_max(0);
8020 /*
8021 * Default to measured freq if none found, PCU will ensure we don't go
8022 * over
8023 */
8024 if (!max_ia_freq)
8025 max_ia_freq = tsc_khz;
8026
8027 /* Convert from kHz to MHz */
8028 max_ia_freq /= 1000;
8029
8030 mutex_lock(&dev_priv->dev->struct_mutex);
8031
8032 /*
8033 * For each potential GPU frequency, load a ring frequency we'd like
8034 * to use for memory access. We do this by specifying the IA frequency
8035 * the PCU should use as a reference to determine the ring frequency.
8036 */
8037 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8038 gpu_freq--) {
8039 int diff = dev_priv->max_delay - gpu_freq;
8040
8041 /*
8042 * For GPU frequencies less than 750MHz, just use the lowest
8043 * ring freq.
8044 */
8045 if (gpu_freq < min_freq)
8046 ia_freq = 800;
8047 else
8048 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8049 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8050
8051 I915_WRITE(GEN6_PCODE_DATA,
8052 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8053 gpu_freq);
8054 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8055 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8056 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8057 GEN6_PCODE_READY) == 0, 10)) {
8058 DRM_ERROR("pcode write of freq table timed out\n");
8059 continue;
8060 }
8061 }
8062
8063 mutex_unlock(&dev_priv->dev->struct_mutex);
8064}
8065
6067aaea
JB		 8066static void ironlake_init_clock_gating(struct drm_device *dev)
8067{
8068 struct drm_i915_private *dev_priv = dev->dev_private;
8069 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8070
8071 /* Required for FBC */
8072 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8073 DPFCRUNIT_CLOCK_GATE_DISABLE |
8074 DPFDUNIT_CLOCK_GATE_DISABLE;
8075 /* Required for CxSR */
8076 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8077
8078 I915_WRITE(PCH_3DCGDIS0,
8079 MARIUNIT_CLOCK_GATE_DISABLE |
8080 SVSMUNIT_CLOCK_GATE_DISABLE);
8081 I915_WRITE(PCH_3DCGDIS1,
8082 VFMUNIT_CLOCK_GATE_DISABLE);
8083
8084 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8085
6067aaea
JB		 8086 /*
8087 * According to the spec the following bits should be set in
8088 * order to enable memory self-refresh
8089 * The bit 22/21 of 0x42004
8090 * The bit 5 of 0x42020
8091 * The bit 15 of 0x45000
8092 */
8093 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8094 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8095 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8096 I915_WRITE(ILK_DSPCLK_GATE,
8097 (I915_READ(ILK_DSPCLK_GATE) |
8098 ILK_DPARB_CLK_GATE));
8099 I915_WRITE(DISP_ARB_CTL,
8100 (I915_READ(DISP_ARB_CTL) |
8101 DISP_FBC_WM_DIS));
8102 I915_WRITE(WM3_LP_ILK, 0);
8103 I915_WRITE(WM2_LP_ILK, 0);
8104 I915_WRITE(WM1_LP_ILK, 0);
8105
8106 /*
8107 * Based on the document from hardware guys the following bits
8108 * should be set unconditionally in order to enable FBC.
8109 * The bit 22 of 0x42000
8110 * The bit 22 of 0x42004
8111 * The bit 7,8,9 of 0x42020.
8112 */
8113 if (IS_IRONLAKE_M(dev)) {
8114 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8115 I915_READ(ILK_DISPLAY_CHICKEN1) |
8116 ILK_FBCQ_DIS);
8117 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8118 I915_READ(ILK_DISPLAY_CHICKEN2) |
8119 ILK_DPARB_GATE);
8120 I915_WRITE(ILK_DSPCLK_GATE,
8121 I915_READ(ILK_DSPCLK_GATE) |
8122 ILK_DPFC_DIS1 |
8123 ILK_DPFC_DIS2 |
8124 ILK_CLK_FBC);
8125 }
8126
8127 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8128 I915_READ(ILK_DISPLAY_CHICKEN2) |
8129 ILK_ELPIN_409_SELECT);
8130 I915_WRITE(_3D_CHICKEN2,
8131 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8132 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8133}
8134
6067aaea 8135static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8136{
8137 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8138 int pipe;
6067aaea
JB		 8139 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8140
8141 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8142
6067aaea
JB		 8143 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8144 I915_READ(ILK_DISPLAY_CHICKEN2) |
8145 ILK_ELPIN_409_SELECT);
8956c8bb 8146
6067aaea
JB		 8147 I915_WRITE(WM3_LP_ILK, 0);
8148 I915_WRITE(WM2_LP_ILK, 0);
8149 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 8150
8151 /*
6067aaea
JB		 8152 * According to the spec the following bits should be
8153 * set in order to enable memory self-refresh and fbc:
8154 * The bit21 and bit22 of 0x42000
8155 * The bit21 and bit22 of 0x42004
8156 * The bit5 and bit7 of 0x42020
8157 * The bit14 of 0x70180
8158 * The bit14 of 0x71180
652c393a 8159 */
6067aaea
JB		 8160 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8161 I915_READ(ILK_DISPLAY_CHICKEN1) |
8162 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8163 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8164 I915_READ(ILK_DISPLAY_CHICKEN2) |
8165 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8166 I915_WRITE(ILK_DSPCLK_GATE,
8167 I915_READ(ILK_DSPCLK_GATE) |
8168 ILK_DPARB_CLK_GATE |
8169 ILK_DPFD_CLK_GATE);
8956c8bb 8170
d74362c9 8171 for_each_pipe(pipe) {
6067aaea
JB		 8172 I915_WRITE(DSPCNTR(pipe),
8173 I915_READ(DSPCNTR(pipe)) |
8174 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8175 intel_flush_display_plane(dev_priv, pipe);
8176 }
6067aaea 8177}
8956c8bb 8178
28963a3e
JB		 8179static void ivybridge_init_clock_gating(struct drm_device *dev)
8180{
8181 struct drm_i915_private *dev_priv = dev->dev_private;
8182 int pipe;
8183 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8184
28963a3e 8185 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8186
28963a3e
JB		 8187 I915_WRITE(WM3_LP_ILK, 0);
8188 I915_WRITE(WM2_LP_ILK, 0);
8189 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8190
28963a3e 8191 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8192
d74362c9 8193 for_each_pipe(pipe) {
28963a3e
JB		 8194 I915_WRITE(DSPCNTR(pipe),
8195 I915_READ(DSPCNTR(pipe)) |
8196 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8197 intel_flush_display_plane(dev_priv, pipe);
8198 }
28963a3e
JB		 8199}
8200
6067aaea
JB		 8201static void g4x_init_clock_gating(struct drm_device *dev)
8202{
8203 struct drm_i915_private *dev_priv = dev->dev_private;
8204 uint32_t dspclk_gate;
8fd26859 8205
6067aaea
JB		 8206 I915_WRITE(RENCLK_GATE_D1, 0);
8207 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8208 GS_UNIT_CLOCK_GATE_DISABLE |
8209 CL_UNIT_CLOCK_GATE_DISABLE);
8210 I915_WRITE(RAMCLK_GATE_D, 0);
8211 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8212 OVRUNIT_CLOCK_GATE_DISABLE |
8213 OVCUNIT_CLOCK_GATE_DISABLE;
8214 if (IS_GM45(dev))
8215 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8216 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8217}
1398261a 8218
6067aaea
JB		 8219static void crestline_init_clock_gating(struct drm_device *dev)
8220{
8221 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8222
6067aaea
JB		 8223 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8224 I915_WRITE(RENCLK_GATE_D2, 0);
8225 I915_WRITE(DSPCLK_GATE_D, 0);
8226 I915_WRITE(RAMCLK_GATE_D, 0);
8227 I915_WRITE16(DEUC, 0);
8228}
652c393a 8229
6067aaea
JB		 8230static void broadwater_init_clock_gating(struct drm_device *dev)
8231{
8232 struct drm_i915_private *dev_priv = dev->dev_private;
8233
8234 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8235 I965_RCC_CLOCK_GATE_DISABLE |
8236 I965_RCPB_CLOCK_GATE_DISABLE |
8237 I965_ISC_CLOCK_GATE_DISABLE |
8238 I965_FBC_CLOCK_GATE_DISABLE);
8239 I915_WRITE(RENCLK_GATE_D2, 0);
8240}
8241
8242static void gen3_init_clock_gating(struct drm_device *dev)
8243{
8244 struct drm_i915_private *dev_priv = dev->dev_private;
8245 u32 dstate = I915_READ(D_STATE);
8246
8247 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8248 DSTATE_DOT_CLOCK_GATING;
8249 I915_WRITE(D_STATE, dstate);
8250}
8251
8252static void i85x_init_clock_gating(struct drm_device *dev)
8253{
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255
8256 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8257}
8258
8259static void i830_init_clock_gating(struct drm_device *dev)
8260{
8261 struct drm_i915_private *dev_priv = dev->dev_private;
8262
8263 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8264}
8265
645c62a5
JB		 8266static void ibx_init_clock_gating(struct drm_device *dev)
8267{
8268 struct drm_i915_private *dev_priv = dev->dev_private;
8269
8270 /*
8271 * On Ibex Peak and Cougar Point, we need to disable clock
8272 * gating for the panel power sequencer or it will fail to
8273 * start up when no ports are active.
8274 */
8275 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8276}
8277
8278static void cpt_init_clock_gating(struct drm_device *dev)
8279{
8280 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8281 int pipe;
645c62a5
JB		 8282
8283 /*
8284 * On Ibex Peak and Cougar Point, we need to disable clock
8285 * gating for the panel power sequencer or it will fail to
8286 * start up when no ports are active.
8287 */
8288 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8289 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8290 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8291 /* Without this, mode sets may fail silently on FDI */
8292 for_each_pipe(pipe)
8293 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8294}
8295
ac668088 8296static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8297{
8298 struct drm_i915_private *dev_priv = dev->dev_private;
8299
8300 if (dev_priv->renderctx) {
ac668088
CW		 8301 i915_gem_object_unpin(dev_priv->renderctx);
8302 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8303 dev_priv->renderctx = NULL;
8304 }
8305
8306 if (dev_priv->pwrctx) {
ac668088
CW		 8307 i915_gem_object_unpin(dev_priv->pwrctx);
8308 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8309 dev_priv->pwrctx = NULL;
8310 }
8311}
8312
8313static void ironlake_disable_rc6(struct drm_device *dev)
8314{
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8316
8317 if (I915_READ(PWRCTXA)) {
8318 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8319 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8320 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8321 50);
0cdab21f
CW		 8322
8323 I915_WRITE(PWRCTXA, 0);
8324 POSTING_READ(PWRCTXA);
8325
ac668088
CW		 8326 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8327 POSTING_READ(RSTDBYCTL);
0cdab21f 8328 }
ac668088 8329
99507307 8330 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8331}
8332
ac668088 8333static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8334{
8335 struct drm_i915_private *dev_priv = dev->dev_private;
8336
ac668088
CW		 8337 if (dev_priv->renderctx == NULL)
8338 dev_priv->renderctx = intel_alloc_context_page(dev);
8339 if (!dev_priv->renderctx)
8340 return -ENOMEM;
8341
8342 if (dev_priv->pwrctx == NULL)
8343 dev_priv->pwrctx = intel_alloc_context_page(dev);
8344 if (!dev_priv->pwrctx) {
8345 ironlake_teardown_rc6(dev);
8346 return -ENOMEM;
8347 }
8348
8349 return 0;
d5bb081b
JB		 8350}
8351
8352void ironlake_enable_rc6(struct drm_device *dev)
8353{
8354 struct drm_i915_private *dev_priv = dev->dev_private;
8355 int ret;
8356
ac668088
CW		 8357 /* rc6 disabled by default due to repeated reports of hanging during
8358 * boot and resume.
8359 */
8360 if (!i915_enable_rc6)
8361 return;
8362
2c34b850 8363 mutex_lock(&dev->struct_mutex);
ac668088 8364 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8365 if (ret) {
8366 mutex_unlock(&dev->struct_mutex);
ac668088 8367 return;
2c34b850 8368 }
ac668088 8369
d5bb081b
JB		 8370 /*
8371 * GPU can automatically power down the render unit if given a page
8372 * to save state.
8373 */
8374 ret = BEGIN_LP_RING(6);
8375 if (ret) {
ac668088 8376 ironlake_teardown_rc6(dev);
2c34b850 8377 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8378 return;
8379 }
ac668088 8380
d5bb081b
JB		 8381 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8382 OUT_RING(MI_SET_CONTEXT);
8383 OUT_RING(dev_priv->renderctx->gtt_offset |
8384 MI_MM_SPACE_GTT |
8385 MI_SAVE_EXT_STATE_EN |
8386 MI_RESTORE_EXT_STATE_EN |
8387 MI_RESTORE_INHIBIT);
8388 OUT_RING(MI_SUSPEND_FLUSH);
8389 OUT_RING(MI_NOOP);
8390 OUT_RING(MI_FLUSH);
8391 ADVANCE_LP_RING();
8392
4a246cfc
BW		 8393 /*
8394 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8395 * does an implicit flush, combined with MI_FLUSH above, it should be
8396 * safe to assume that renderctx is valid
8397 */
8398 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8399 if (ret) {
8400 DRM_ERROR("failed to enable ironlake power power savings\n");
8401 ironlake_teardown_rc6(dev);
8402 mutex_unlock(&dev->struct_mutex);
8403 return;
8404 }
8405
d5bb081b
JB		 8406 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8407 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8408 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8409}
8410
645c62a5
JB		 8411void intel_init_clock_gating(struct drm_device *dev)
8412{
8413 struct drm_i915_private *dev_priv = dev->dev_private;
8414
8415 dev_priv->display.init_clock_gating(dev);
8416
8417 if (dev_priv->display.init_pch_clock_gating)
8418 dev_priv->display.init_pch_clock_gating(dev);
8419}
ac668088 8420
e70236a8
JB		 8421/* Set up chip specific display functions */
8422static void intel_init_display(struct drm_device *dev)
8423{
8424 struct drm_i915_private *dev_priv = dev->dev_private;
8425
8426 /* We always want a DPMS function */
f564048e 8427 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8428 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8429 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8430 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8431 } else {
e70236a8 8432 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8433 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8434 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8435 }
e70236a8 8436
ee5382ae 8437 if (I915_HAS_FBC(dev)) {
9c04f015 8438 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8439 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8440 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8441 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8442 } else if (IS_GM45(dev)) {
74dff282
JB		 8443 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8444 dev_priv->display.enable_fbc = g4x_enable_fbc;
8445 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8446 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8447 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8448 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8449 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8450 }
74dff282 8451 /* 855GM needs testing */
e70236a8
JB		 8452 }
8453
8454 /* Returns the core display clock speed */
0206e353 8455 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8456 dev_priv->display.get_display_clock_speed =
8457 i945_get_display_clock_speed;
8458 else if (IS_I915G(dev))
8459 dev_priv->display.get_display_clock_speed =
8460 i915_get_display_clock_speed;
f2b115e6 8461 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8462 dev_priv->display.get_display_clock_speed =
8463 i9xx_misc_get_display_clock_speed;
8464 else if (IS_I915GM(dev))
8465 dev_priv->display.get_display_clock_speed =
8466 i915gm_get_display_clock_speed;
8467 else if (IS_I865G(dev))
8468 dev_priv->display.get_display_clock_speed =
8469 i865_get_display_clock_speed;
f0f8a9ce 8470 else if (IS_I85X(dev))
e70236a8
JB		 8471 dev_priv->display.get_display_clock_speed =
8472 i855_get_display_clock_speed;
8473 else /* 852, 830 */
8474 dev_priv->display.get_display_clock_speed =
8475 i830_get_display_clock_speed;
8476
8477 /* For FIFO watermark updates */
7f8a8569 8478 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8479 if (HAS_PCH_IBX(dev))
8480 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8481 else if (HAS_PCH_CPT(dev))
8482 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8483
f00a3ddf 8484 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8485 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8486 dev_priv->display.update_wm = ironlake_update_wm;
8487 else {
8488 DRM_DEBUG_KMS("Failed to get proper latency. "
8489 "Disable CxSR\n");
8490 dev_priv->display.update_wm = NULL;
1398261a 8491 }
674cf967 8492 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8493 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8494 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8495 } else if (IS_GEN6(dev)) {
8496 if (SNB_READ_WM0_LATENCY()) {
8497 dev_priv->display.update_wm = sandybridge_update_wm;
8498 } else {
8499 DRM_DEBUG_KMS("Failed to read display plane latency. "
8500 "Disable CxSR\n");
8501 dev_priv->display.update_wm = NULL;
7f8a8569 8502 }
674cf967 8503 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8504 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8505 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8506 } else if (IS_IVYBRIDGE(dev)) {
8507 /* FIXME: detect B0+ stepping and use auto training */
8508 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8509 if (SNB_READ_WM0_LATENCY()) {
8510 dev_priv->display.update_wm = sandybridge_update_wm;
8511 } else {
8512 DRM_DEBUG_KMS("Failed to read display plane latency. "
8513 "Disable CxSR\n");
8514 dev_priv->display.update_wm = NULL;
8515 }
28963a3e 8516 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8517 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8518 } else
8519 dev_priv->display.update_wm = NULL;
8520 } else if (IS_PINEVIEW(dev)) {
d4294342 8521 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8522 dev_priv->is_ddr3,
d4294342
ZY		 8523 dev_priv->fsb_freq,
8524 dev_priv->mem_freq)) {
8525 DRM_INFO("failed to find known CxSR latency "
95534263 8526 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8527 "disabling CxSR\n",
0206e353 8528 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8529 dev_priv->fsb_freq, dev_priv->mem_freq);
8530 /* Disable CxSR and never update its watermark again */
8531 pineview_disable_cxsr(dev);
8532 dev_priv->display.update_wm = NULL;
8533 } else
8534 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8535 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8536 } else if (IS_G4X(dev)) {
e0dac65e 8537 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8538 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8539 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8540 } else if (IS_GEN4(dev)) {
e70236a8 8541 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8542 if (IS_CRESTLINE(dev))
8543 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8544 else if (IS_BROADWATER(dev))
8545 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8546 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8547 dev_priv->display.update_wm = i9xx_update_wm;
8548 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8549 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8550 } else if (IS_I865G(dev)) {
8551 dev_priv->display.update_wm = i830_update_wm;
8552 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8553 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8554 } else if (IS_I85X(dev)) {
8555 dev_priv->display.update_wm = i9xx_update_wm;
8556 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8557 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8558 } else {
8f4695ed 8559 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8560 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8561 if (IS_845G(dev))
e70236a8
JB		 8562 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8563 else
8564 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8565 }
8c9f3aaf
JB		 8566
8567 /* Default just returns -ENODEV to indicate unsupported */
8568 dev_priv->display.queue_flip = intel_default_queue_flip;
8569
8570 switch (INTEL_INFO(dev)->gen) {
8571 case 2:
8572 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8573 break;
8574
8575 case 3:
8576 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8577 break;
8578
8579 case 4:
8580 case 5:
8581 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8582 break;
8583
8584 case 6:
8585 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8586 break;
7c9017e5
JB		 8587 case 7:
8588 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8589 break;
8c9f3aaf 8590 }
e70236a8
JB		 8591}
8592
b690e96c
JB		 8593/*
8594 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8595 * resume, or other times. This quirk makes sure that's the case for
8596 * affected systems.
8597 */
0206e353 8598static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601
8602 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8603 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8604}
8605
435793df
KP		 8606/*
8607 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8608 */
8609static void quirk_ssc_force_disable(struct drm_device *dev)
8610{
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8613}
8614
b690e96c
JB		 8615struct intel_quirk {
8616 int device;
8617 int subsystem_vendor;
8618 int subsystem_device;
8619 void (*hook)(struct drm_device *dev);
8620};
8621
8622struct intel_quirk intel_quirks[] = {
8623 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8624 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8625 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8626 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8627
8628 /* Thinkpad R31 needs pipe A force quirk */
8629 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8630 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8631 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8632
8633 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8634 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8635 /* ThinkPad X40 needs pipe A force quirk */
8636
8637 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8638 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8639
8640 /* 855 & before need to leave pipe A & dpll A up */
8641 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8642 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8643
8644 /* Lenovo U160 cannot use SSC on LVDS */
8645 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8646
8647 /* Sony Vaio Y cannot use SSC on LVDS */
8648 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8649};
8650
8651static void intel_init_quirks(struct drm_device *dev)
8652{
8653 struct pci_dev *d = dev->pdev;
8654 int i;
8655
8656 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8657 struct intel_quirk *q = &intel_quirks[i];
8658
8659 if (d->device == q->device &&
8660 (d->subsystem_vendor == q->subsystem_vendor ||
8661 q->subsystem_vendor == PCI_ANY_ID) &&
8662 (d->subsystem_device == q->subsystem_device ||
8663 q->subsystem_device == PCI_ANY_ID))
8664 q->hook(dev);
8665 }
8666}
8667
9cce37f4
JB		 8668/* Disable the VGA plane that we never use */
8669static void i915_disable_vga(struct drm_device *dev)
8670{
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 u8 sr1;
8673 u32 vga_reg;
8674
8675 if (HAS_PCH_SPLIT(dev))
8676 vga_reg = CPU_VGACNTRL;
8677 else
8678 vga_reg = VGACNTRL;
8679
8680 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8681 outb(1, VGA_SR_INDEX);
8682 sr1 = inb(VGA_SR_DATA);
8683 outb(sr1 | 1<<5, VGA_SR_DATA);
8684 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8685 udelay(300);
8686
8687 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8688 POSTING_READ(vga_reg);
8689}
8690
79e53945
JB		 8691void intel_modeset_init(struct drm_device *dev)
8692{
652c393a 8693 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8694 int i;
8695
8696 drm_mode_config_init(dev);
8697
8698 dev->mode_config.min_width = 0;
8699 dev->mode_config.min_height = 0;
8700
8701 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8702
b690e96c
JB		 8703 intel_init_quirks(dev);
8704
e70236a8
JB		 8705 intel_init_display(dev);
8706
a6c45cf0
CW		 8707 if (IS_GEN2(dev)) {
8708 dev->mode_config.max_width = 2048;
8709 dev->mode_config.max_height = 2048;
8710 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8711 dev->mode_config.max_width = 4096;
8712 dev->mode_config.max_height = 4096;
79e53945 8713 } else {
a6c45cf0
CW		 8714 dev->mode_config.max_width = 8192;
8715 dev->mode_config.max_height = 8192;
79e53945 8716 }
35c3047a 8717 dev->mode_config.fb_base = dev->agp->base;
79e53945 8718
28c97730 8719 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8720 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8721
a3524f1b 8722 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8723 intel_crtc_init(dev, i);
8724 }
8725
9cce37f4
JB		 8726 /* Just disable it once at startup */
8727 i915_disable_vga(dev);
79e53945 8728 intel_setup_outputs(dev);
652c393a 8729
645c62a5 8730 intel_init_clock_gating(dev);
9cce37f4 8731
7648fa99 8732 if (IS_IRONLAKE_M(dev)) {
f97108d1 8733 ironlake_enable_drps(dev);
7648fa99
JB		 8734 intel_init_emon(dev);
8735 }
f97108d1 8736
1c70c0ce 8737 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8738 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8739 gen6_update_ring_freq(dev_priv);
8740 }
3b8d8d91 8741
652c393a
JB		 8742 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8743 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8744 (unsigned long)dev);
2c7111db
CW		 8745}
8746
8747void intel_modeset_gem_init(struct drm_device *dev)
8748{
8749 if (IS_IRONLAKE_M(dev))
8750 ironlake_enable_rc6(dev);
02e792fb
DV		 8751
8752 intel_setup_overlay(dev);
79e53945
JB		 8753}
8754
8755void intel_modeset_cleanup(struct drm_device *dev)
8756{
652c393a
JB		 8757 struct drm_i915_private *dev_priv = dev->dev_private;
8758 struct drm_crtc *crtc;
8759 struct intel_crtc *intel_crtc;
8760
f87ea761 8761 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8762 mutex_lock(&dev->struct_mutex);
8763
723bfd70
JB		 8764 intel_unregister_dsm_handler();
8765
8766
652c393a
JB		 8767 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8768 /* Skip inactive CRTCs */
8769 if (!crtc->fb)
8770 continue;
8771
8772 intel_crtc = to_intel_crtc(crtc);
3dec0095 8773 intel_increase_pllclock(crtc);
652c393a
JB		 8774 }
8775
973d04f9 8776 intel_disable_fbc(dev);
e70236a8 8777
f97108d1
JB		 8778 if (IS_IRONLAKE_M(dev))
8779 ironlake_disable_drps(dev);
1c70c0ce 8780 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8781 gen6_disable_rps(dev);
f97108d1 8782
d5bb081b
JB		 8783 if (IS_IRONLAKE_M(dev))
8784 ironlake_disable_rc6(dev);
0cdab21f 8785
69341a5e
KH		 8786 mutex_unlock(&dev->struct_mutex);
8787
6c0d9350
DV		 8788 /* Disable the irq before mode object teardown, for the irq might
8789 * enqueue unpin/hotplug work. */
8790 drm_irq_uninstall(dev);
8791 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 8792 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 8793
1630fe75
CW		 8794 /* flush any delayed tasks or pending work */
8795 flush_scheduled_work();
8796
3dec0095
DV		 8797 /* Shut off idle work before the crtcs get freed. */
8798 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8799 intel_crtc = to_intel_crtc(crtc);
8800 del_timer_sync(&intel_crtc->idle_timer);
8801 }
8802 del_timer_sync(&dev_priv->idle_timer);
8803 cancel_work_sync(&dev_priv->idle_work);
8804
79e53945
JB		 8805 drm_mode_config_cleanup(dev);
8806}
8807
f1c79df3
ZW		 8808/*
8809 * Return which encoder is currently attached for connector.
8810 */
df0e9248 8811struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8812{
df0e9248
CW		 8813 return &intel_attached_encoder(connector)->base;
8814}
f1c79df3 8815
df0e9248
CW		 8816void intel_connector_attach_encoder(struct intel_connector *connector,
8817 struct intel_encoder *encoder)
8818{
8819 connector->encoder = encoder;
8820 drm_mode_connector_attach_encoder(&connector->base,
8821 &encoder->base);
79e53945 8822}
28d52043
DA		 8823
8824/*
8825 * set vga decode state - true == enable VGA decode
8826 */
8827int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8828{
8829 struct drm_i915_private *dev_priv = dev->dev_private;
8830 u16 gmch_ctrl;
8831
8832 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8833 if (state)
8834 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8835 else
8836 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8837 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8838 return 0;
8839}
c4a1d9e4
CW		 8840
8841#ifdef CONFIG_DEBUG_FS
8842#include <linux/seq_file.h>
8843
8844struct intel_display_error_state {
8845 struct intel_cursor_error_state {
8846 u32 control;
8847 u32 position;
8848 u32 base;
8849 u32 size;
8850 } cursor[2];
8851
8852 struct intel_pipe_error_state {
8853 u32 conf;
8854 u32 source;
8855
8856 u32 htotal;
8857 u32 hblank;
8858 u32 hsync;
8859 u32 vtotal;
8860 u32 vblank;
8861 u32 vsync;
8862 } pipe[2];
8863
8864 struct intel_plane_error_state {
8865 u32 control;
8866 u32 stride;
8867 u32 size;
8868 u32 pos;
8869 u32 addr;
8870 u32 surface;
8871 u32 tile_offset;
8872 } plane[2];
8873};
8874
8875struct intel_display_error_state *
8876intel_display_capture_error_state(struct drm_device *dev)
8877{
0206e353 8878 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8879 struct intel_display_error_state *error;
8880 int i;
8881
8882 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8883 if (error == NULL)
8884 return NULL;
8885
8886 for (i = 0; i < 2; i++) {
8887 error->cursor[i].control = I915_READ(CURCNTR(i));
8888 error->cursor[i].position = I915_READ(CURPOS(i));
8889 error->cursor[i].base = I915_READ(CURBASE(i));
8890
8891 error->plane[i].control = I915_READ(DSPCNTR(i));
8892 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8893 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8894 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8895 error->plane[i].addr = I915_READ(DSPADDR(i));
8896 if (INTEL_INFO(dev)->gen >= 4) {
8897 error->plane[i].surface = I915_READ(DSPSURF(i));
8898 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8899 }
8900
8901 error->pipe[i].conf = I915_READ(PIPECONF(i));
8902 error->pipe[i].source = I915_READ(PIPESRC(i));
8903 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8904 error->pipe[i].hblank = I915_READ(HBLANK(i));
8905 error->pipe[i].hsync = I915_READ(HSYNC(i));
8906 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8907 error->pipe[i].vblank = I915_READ(VBLANK(i));
8908 error->pipe[i].vsync = I915_READ(VSYNC(i));
8909 }
8910
8911 return error;
8912}
8913
8914void
8915intel_display_print_error_state(struct seq_file *m,
8916 struct drm_device *dev,
8917 struct intel_display_error_state *error)
8918{
8919 int i;
8920
8921 for (i = 0; i < 2; i++) {
8922 seq_printf(m, "Pipe [%d]:\n", i);
8923 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8924 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8925 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8926 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8927 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8928 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8929 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8930 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8931
8932 seq_printf(m, "Plane [%d]:\n", i);
8933 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8934 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8935 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8936 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8937 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8938 if (INTEL_INFO(dev)->gen >= 4) {
8939 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8940 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8941 }
8942
8943 seq_printf(m, "Cursor [%d]:\n", i);
8944 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8945 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8946 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8947 }
8948}
8949#endif
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