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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
23b2f8bb | 27 | #include <linux/cpufreq.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 47 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
50 | |
51 | typedef struct { | |
0206e353 AJ |
52 | /* given values */ |
53 | int n; | |
54 | int m1, m2; | |
55 | int p1, p2; | |
56 | /* derived values */ | |
57 | int dot; | |
58 | int vco; | |
59 | int m; | |
60 | int p; | |
79e53945 JB |
61 | } intel_clock_t; |
62 | ||
63 | typedef struct { | |
0206e353 | 64 | int min, max; |
79e53945 JB |
65 | } intel_range_t; |
66 | ||
67 | typedef struct { | |
0206e353 AJ |
68 | int dot_limit; |
69 | int p2_slow, p2_fast; | |
79e53945 JB |
70 | } intel_p2_t; |
71 | ||
72 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { | |
0206e353 AJ |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; | |
77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 78 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 79 | }; |
79e53945 | 80 | |
2377b741 JB |
81 | /* FDI */ |
82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
83 | ||
d4906093 ML |
84 | static bool |
85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
86 | int target, int refclk, intel_clock_t *match_clock, |
87 | intel_clock_t *best_clock); | |
d4906093 ML |
88 | static bool |
89 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
90 | int target, int refclk, intel_clock_t *match_clock, |
91 | intel_clock_t *best_clock); | |
79e53945 | 92 | |
a4fc5ed6 KP |
93 | static bool |
94 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
95 | int target, int refclk, intel_clock_t *match_clock, |
96 | intel_clock_t *best_clock); | |
5eb08b69 | 97 | static bool |
f2b115e6 | 98 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
99 | int target, int refclk, intel_clock_t *match_clock, |
100 | intel_clock_t *best_clock); | |
a4fc5ed6 | 101 | |
021357ac CW |
102 | static inline u32 /* units of 100MHz */ |
103 | intel_fdi_link_freq(struct drm_device *dev) | |
104 | { | |
8b99e68c CW |
105 | if (IS_GEN5(dev)) { |
106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
107 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
108 | } else | |
109 | return 27; | |
021357ac CW |
110 | } |
111 | ||
e4b36699 | 112 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
113 | .dot = { .min = 25000, .max = 350000 }, |
114 | .vco = { .min = 930000, .max = 1400000 }, | |
115 | .n = { .min = 3, .max = 16 }, | |
116 | .m = { .min = 96, .max = 140 }, | |
117 | .m1 = { .min = 18, .max = 26 }, | |
118 | .m2 = { .min = 6, .max = 16 }, | |
119 | .p = { .min = 4, .max = 128 }, | |
120 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
121 | .p2 = { .dot_limit = 165000, |
122 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 123 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
124 | }; |
125 | ||
126 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
127 | .dot = { .min = 25000, .max = 350000 }, |
128 | .vco = { .min = 930000, .max = 1400000 }, | |
129 | .n = { .min = 3, .max = 16 }, | |
130 | .m = { .min = 96, .max = 140 }, | |
131 | .m1 = { .min = 18, .max = 26 }, | |
132 | .m2 = { .min = 6, .max = 16 }, | |
133 | .p = { .min = 4, .max = 128 }, | |
134 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
135 | .p2 = { .dot_limit = 165000, |
136 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 137 | .find_pll = intel_find_best_PLL, |
e4b36699 | 138 | }; |
273e27ca | 139 | |
e4b36699 | 140 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
141 | .dot = { .min = 20000, .max = 400000 }, |
142 | .vco = { .min = 1400000, .max = 2800000 }, | |
143 | .n = { .min = 1, .max = 6 }, | |
144 | .m = { .min = 70, .max = 120 }, | |
145 | .m1 = { .min = 10, .max = 22 }, | |
146 | .m2 = { .min = 5, .max = 9 }, | |
147 | .p = { .min = 5, .max = 80 }, | |
148 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
149 | .p2 = { .dot_limit = 200000, |
150 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 151 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
152 | }; |
153 | ||
154 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
155 | .dot = { .min = 20000, .max = 400000 }, |
156 | .vco = { .min = 1400000, .max = 2800000 }, | |
157 | .n = { .min = 1, .max = 6 }, | |
158 | .m = { .min = 70, .max = 120 }, | |
159 | .m1 = { .min = 10, .max = 22 }, | |
160 | .m2 = { .min = 5, .max = 9 }, | |
161 | .p = { .min = 7, .max = 98 }, | |
162 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 112000, |
164 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 165 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
166 | }; |
167 | ||
273e27ca | 168 | |
e4b36699 | 169 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
170 | .dot = { .min = 25000, .max = 270000 }, |
171 | .vco = { .min = 1750000, .max = 3500000}, | |
172 | .n = { .min = 1, .max = 4 }, | |
173 | .m = { .min = 104, .max = 138 }, | |
174 | .m1 = { .min = 17, .max = 23 }, | |
175 | .m2 = { .min = 5, .max = 11 }, | |
176 | .p = { .min = 10, .max = 30 }, | |
177 | .p1 = { .min = 1, .max = 3}, | |
178 | .p2 = { .dot_limit = 270000, | |
179 | .p2_slow = 10, | |
180 | .p2_fast = 10 | |
044c7c41 | 181 | }, |
d4906093 | 182 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
186 | .dot = { .min = 22000, .max = 400000 }, |
187 | .vco = { .min = 1750000, .max = 3500000}, | |
188 | .n = { .min = 1, .max = 4 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 16, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 5, .max = 80 }, | |
193 | .p1 = { .min = 1, .max = 8}, | |
194 | .p2 = { .dot_limit = 165000, | |
195 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 196 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 20000, .max = 115000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 28, .max = 112 }, | |
207 | .p1 = { .min = 2, .max = 8 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 210 | }, |
d4906093 | 211 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
215 | .dot = { .min = 80000, .max = 224000 }, |
216 | .vco = { .min = 1750000, .max = 3500000 }, | |
217 | .n = { .min = 1, .max = 3 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 14, .max = 42 }, | |
222 | .p1 = { .min = 2, .max = 6 }, | |
223 | .p2 = { .dot_limit = 0, | |
224 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 225 | }, |
d4906093 | 226 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
230 | .dot = { .min = 161670, .max = 227000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 2 }, | |
233 | .m = { .min = 97, .max = 108 }, | |
234 | .m1 = { .min = 0x10, .max = 0x12 }, | |
235 | .m2 = { .min = 0x05, .max = 0x06 }, | |
236 | .p = { .min = 10, .max = 20 }, | |
237 | .p1 = { .min = 1, .max = 2}, | |
238 | .p2 = { .dot_limit = 0, | |
273e27ca | 239 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 240 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
241 | }; |
242 | ||
f2b115e6 | 243 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
244 | .dot = { .min = 20000, .max = 400000}, |
245 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 246 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
247 | .n = { .min = 3, .max = 6 }, |
248 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 249 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
250 | .m1 = { .min = 0, .max = 0 }, |
251 | .m2 = { .min = 0, .max = 254 }, | |
252 | .p = { .min = 5, .max = 80 }, | |
253 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
254 | .p2 = { .dot_limit = 200000, |
255 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 256 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
257 | }; |
258 | ||
f2b115e6 | 259 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
260 | .dot = { .min = 20000, .max = 400000 }, |
261 | .vco = { .min = 1700000, .max = 3500000 }, | |
262 | .n = { .min = 3, .max = 6 }, | |
263 | .m = { .min = 2, .max = 256 }, | |
264 | .m1 = { .min = 0, .max = 0 }, | |
265 | .m2 = { .min = 0, .max = 254 }, | |
266 | .p = { .min = 7, .max = 112 }, | |
267 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
268 | .p2 = { .dot_limit = 112000, |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 270 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
271 | }; |
272 | ||
273e27ca EA |
273 | /* Ironlake / Sandybridge |
274 | * | |
275 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
276 | * the range value for them is (actual_value - 2). | |
277 | */ | |
b91ad0ec | 278 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
279 | .dot = { .min = 25000, .max = 350000 }, |
280 | .vco = { .min = 1760000, .max = 3510000 }, | |
281 | .n = { .min = 1, .max = 5 }, | |
282 | .m = { .min = 79, .max = 127 }, | |
283 | .m1 = { .min = 12, .max = 22 }, | |
284 | .m2 = { .min = 5, .max = 9 }, | |
285 | .p = { .min = 5, .max = 80 }, | |
286 | .p1 = { .min = 1, .max = 8 }, | |
287 | .p2 = { .dot_limit = 225000, | |
288 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 289 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
290 | }; |
291 | ||
b91ad0ec | 292 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
293 | .dot = { .min = 25000, .max = 350000 }, |
294 | .vco = { .min = 1760000, .max = 3510000 }, | |
295 | .n = { .min = 1, .max = 3 }, | |
296 | .m = { .min = 79, .max = 118 }, | |
297 | .m1 = { .min = 12, .max = 22 }, | |
298 | .m2 = { .min = 5, .max = 9 }, | |
299 | .p = { .min = 28, .max = 112 }, | |
300 | .p1 = { .min = 2, .max = 8 }, | |
301 | .p2 = { .dot_limit = 225000, | |
302 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
303 | .find_pll = intel_g4x_find_best_PLL, |
304 | }; | |
305 | ||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, | |
309 | .n = { .min = 1, .max = 3 }, | |
310 | .m = { .min = 79, .max = 127 }, | |
311 | .m1 = { .min = 12, .max = 22 }, | |
312 | .m2 = { .min = 5, .max = 9 }, | |
313 | .p = { .min = 14, .max = 56 }, | |
314 | .p1 = { .min = 2, .max = 8 }, | |
315 | .p2 = { .dot_limit = 225000, | |
316 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
317 | .find_pll = intel_g4x_find_best_PLL, |
318 | }; | |
319 | ||
273e27ca | 320 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 321 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
322 | .dot = { .min = 25000, .max = 350000 }, |
323 | .vco = { .min = 1760000, .max = 3510000 }, | |
324 | .n = { .min = 1, .max = 2 }, | |
325 | .m = { .min = 79, .max = 126 }, | |
326 | .m1 = { .min = 12, .max = 22 }, | |
327 | .m2 = { .min = 5, .max = 9 }, | |
328 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 329 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
330 | .p2 = { .dot_limit = 225000, |
331 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
332 | .find_pll = intel_g4x_find_best_PLL, |
333 | }; | |
334 | ||
335 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
336 | .dot = { .min = 25000, .max = 350000 }, |
337 | .vco = { .min = 1760000, .max = 3510000 }, | |
338 | .n = { .min = 1, .max = 3 }, | |
339 | .m = { .min = 79, .max = 126 }, | |
340 | .m1 = { .min = 12, .max = 22 }, | |
341 | .m2 = { .min = 5, .max = 9 }, | |
342 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 343 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
344 | .p2 = { .dot_limit = 225000, |
345 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
346 | .find_pll = intel_g4x_find_best_PLL, |
347 | }; | |
348 | ||
349 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000}, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 81, .max = 90 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 10, .max = 20 }, | |
357 | .p1 = { .min = 1, .max = 2}, | |
358 | .p2 = { .dot_limit = 0, | |
273e27ca | 359 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 360 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
361 | }; |
362 | ||
1b894b59 CW |
363 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
364 | int refclk) | |
2c07245f | 365 | { |
b91ad0ec ZW |
366 | struct drm_device *dev = crtc->dev; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 368 | const intel_limit_t *limit; |
b91ad0ec ZW |
369 | |
370 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
371 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
372 | LVDS_CLKB_POWER_UP) { | |
373 | /* LVDS dual channel */ | |
1b894b59 | 374 | if (refclk == 100000) |
b91ad0ec ZW |
375 | limit = &intel_limits_ironlake_dual_lvds_100m; |
376 | else | |
377 | limit = &intel_limits_ironlake_dual_lvds; | |
378 | } else { | |
1b894b59 | 379 | if (refclk == 100000) |
b91ad0ec ZW |
380 | limit = &intel_limits_ironlake_single_lvds_100m; |
381 | else | |
382 | limit = &intel_limits_ironlake_single_lvds; | |
383 | } | |
384 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
385 | HAS_eDP) |
386 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 387 | else |
b91ad0ec | 388 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
389 | |
390 | return limit; | |
391 | } | |
392 | ||
044c7c41 ML |
393 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
394 | { | |
395 | struct drm_device *dev = crtc->dev; | |
396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
397 | const intel_limit_t *limit; | |
398 | ||
399 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
400 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
401 | LVDS_CLKB_POWER_UP) | |
402 | /* LVDS with dual channel */ | |
e4b36699 | 403 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
404 | else |
405 | /* LVDS with dual channel */ | |
e4b36699 | 406 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
407 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
408 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 409 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 410 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 411 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 412 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 413 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 414 | } else /* The option is for other outputs */ |
e4b36699 | 415 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
416 | |
417 | return limit; | |
418 | } | |
419 | ||
1b894b59 | 420 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
421 | { |
422 | struct drm_device *dev = crtc->dev; | |
423 | const intel_limit_t *limit; | |
424 | ||
bad720ff | 425 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 426 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 427 | else if (IS_G4X(dev)) { |
044c7c41 | 428 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 429 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 431 | limit = &intel_limits_pineview_lvds; |
2177832f | 432 | else |
f2b115e6 | 433 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
434 | } else if (!IS_GEN2(dev)) { |
435 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
436 | limit = &intel_limits_i9xx_lvds; | |
437 | else | |
438 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
439 | } else { |
440 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 441 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 442 | else |
e4b36699 | 443 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
444 | } |
445 | return limit; | |
446 | } | |
447 | ||
f2b115e6 AJ |
448 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
449 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 450 | { |
2177832f SL |
451 | clock->m = clock->m2 + 2; |
452 | clock->p = clock->p1 * clock->p2; | |
453 | clock->vco = refclk * clock->m / clock->n; | |
454 | clock->dot = clock->vco / clock->p; | |
455 | } | |
456 | ||
457 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
458 | { | |
f2b115e6 AJ |
459 | if (IS_PINEVIEW(dev)) { |
460 | pineview_clock(refclk, clock); | |
2177832f SL |
461 | return; |
462 | } | |
79e53945 JB |
463 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
464 | clock->p = clock->p1 * clock->p2; | |
465 | clock->vco = refclk * clock->m / (clock->n + 2); | |
466 | clock->dot = clock->vco / clock->p; | |
467 | } | |
468 | ||
79e53945 JB |
469 | /** |
470 | * Returns whether any output on the specified pipe is of the specified type | |
471 | */ | |
4ef69c7a | 472 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 473 | { |
4ef69c7a CW |
474 | struct drm_device *dev = crtc->dev; |
475 | struct drm_mode_config *mode_config = &dev->mode_config; | |
476 | struct intel_encoder *encoder; | |
477 | ||
478 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
479 | if (encoder->base.crtc == crtc && encoder->type == type) | |
480 | return true; | |
481 | ||
482 | return false; | |
79e53945 JB |
483 | } |
484 | ||
7c04d1d9 | 485 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
486 | /** |
487 | * Returns whether the given set of divisors are valid for a given refclk with | |
488 | * the given connectors. | |
489 | */ | |
490 | ||
1b894b59 CW |
491 | static bool intel_PLL_is_valid(struct drm_device *dev, |
492 | const intel_limit_t *limit, | |
493 | const intel_clock_t *clock) | |
79e53945 | 494 | { |
79e53945 | 495 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 496 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 497 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 498 | INTELPllInvalid("p out of range\n"); |
79e53945 | 499 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 500 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 501 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 502 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 503 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 504 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 505 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 506 | INTELPllInvalid("m out of range\n"); |
79e53945 | 507 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 508 | INTELPllInvalid("n out of range\n"); |
79e53945 | 509 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 510 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
511 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
512 | * connector, etc., rather than just a single range. | |
513 | */ | |
514 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 515 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
516 | |
517 | return true; | |
518 | } | |
519 | ||
d4906093 ML |
520 | static bool |
521 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
522 | int target, int refclk, intel_clock_t *match_clock, |
523 | intel_clock_t *best_clock) | |
d4906093 | 524 | |
79e53945 JB |
525 | { |
526 | struct drm_device *dev = crtc->dev; | |
527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
528 | intel_clock_t clock; | |
79e53945 JB |
529 | int err = target; |
530 | ||
bc5e5718 | 531 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 532 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
533 | /* |
534 | * For LVDS, if the panel is on, just rely on its current | |
535 | * settings for dual-channel. We haven't figured out how to | |
536 | * reliably set up different single/dual channel state, if we | |
537 | * even can. | |
538 | */ | |
539 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
540 | LVDS_CLKB_POWER_UP) | |
541 | clock.p2 = limit->p2.p2_fast; | |
542 | else | |
543 | clock.p2 = limit->p2.p2_slow; | |
544 | } else { | |
545 | if (target < limit->p2.dot_limit) | |
546 | clock.p2 = limit->p2.p2_slow; | |
547 | else | |
548 | clock.p2 = limit->p2.p2_fast; | |
549 | } | |
550 | ||
0206e353 | 551 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 552 | |
42158660 ZY |
553 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
554 | clock.m1++) { | |
555 | for (clock.m2 = limit->m2.min; | |
556 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
557 | /* m1 is always 0 in Pineview */ |
558 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
559 | break; |
560 | for (clock.n = limit->n.min; | |
561 | clock.n <= limit->n.max; clock.n++) { | |
562 | for (clock.p1 = limit->p1.min; | |
563 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
564 | int this_err; |
565 | ||
2177832f | 566 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
567 | if (!intel_PLL_is_valid(dev, limit, |
568 | &clock)) | |
79e53945 | 569 | continue; |
cec2f356 SP |
570 | if (match_clock && |
571 | clock.p != match_clock->p) | |
572 | continue; | |
79e53945 JB |
573 | |
574 | this_err = abs(clock.dot - target); | |
575 | if (this_err < err) { | |
576 | *best_clock = clock; | |
577 | err = this_err; | |
578 | } | |
579 | } | |
580 | } | |
581 | } | |
582 | } | |
583 | ||
584 | return (err != target); | |
585 | } | |
586 | ||
d4906093 ML |
587 | static bool |
588 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
589 | int target, int refclk, intel_clock_t *match_clock, |
590 | intel_clock_t *best_clock) | |
d4906093 ML |
591 | { |
592 | struct drm_device *dev = crtc->dev; | |
593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
594 | intel_clock_t clock; | |
595 | int max_n; | |
596 | bool found; | |
6ba770dc AJ |
597 | /* approximately equals target * 0.00585 */ |
598 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
599 | found = false; |
600 | ||
601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
602 | int lvds_reg; |
603 | ||
c619eed4 | 604 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
605 | lvds_reg = PCH_LVDS; |
606 | else | |
607 | lvds_reg = LVDS; | |
608 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
609 | LVDS_CLKB_POWER_UP) |
610 | clock.p2 = limit->p2.p2_fast; | |
611 | else | |
612 | clock.p2 = limit->p2.p2_slow; | |
613 | } else { | |
614 | if (target < limit->p2.dot_limit) | |
615 | clock.p2 = limit->p2.p2_slow; | |
616 | else | |
617 | clock.p2 = limit->p2.p2_fast; | |
618 | } | |
619 | ||
620 | memset(best_clock, 0, sizeof(*best_clock)); | |
621 | max_n = limit->n.max; | |
f77f13e2 | 622 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 623 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 624 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
625 | for (clock.m1 = limit->m1.max; |
626 | clock.m1 >= limit->m1.min; clock.m1--) { | |
627 | for (clock.m2 = limit->m2.max; | |
628 | clock.m2 >= limit->m2.min; clock.m2--) { | |
629 | for (clock.p1 = limit->p1.max; | |
630 | clock.p1 >= limit->p1.min; clock.p1--) { | |
631 | int this_err; | |
632 | ||
2177832f | 633 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
634 | if (!intel_PLL_is_valid(dev, limit, |
635 | &clock)) | |
d4906093 | 636 | continue; |
cec2f356 SP |
637 | if (match_clock && |
638 | clock.p != match_clock->p) | |
639 | continue; | |
1b894b59 CW |
640 | |
641 | this_err = abs(clock.dot - target); | |
d4906093 ML |
642 | if (this_err < err_most) { |
643 | *best_clock = clock; | |
644 | err_most = this_err; | |
645 | max_n = clock.n; | |
646 | found = true; | |
647 | } | |
648 | } | |
649 | } | |
650 | } | |
651 | } | |
2c07245f ZW |
652 | return found; |
653 | } | |
654 | ||
5eb08b69 | 655 | static bool |
f2b115e6 | 656 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
657 | int target, int refclk, intel_clock_t *match_clock, |
658 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
659 | { |
660 | struct drm_device *dev = crtc->dev; | |
661 | intel_clock_t clock; | |
4547668a | 662 | |
5eb08b69 ZW |
663 | if (target < 200000) { |
664 | clock.n = 1; | |
665 | clock.p1 = 2; | |
666 | clock.p2 = 10; | |
667 | clock.m1 = 12; | |
668 | clock.m2 = 9; | |
669 | } else { | |
670 | clock.n = 2; | |
671 | clock.p1 = 1; | |
672 | clock.p2 = 10; | |
673 | clock.m1 = 14; | |
674 | clock.m2 = 8; | |
675 | } | |
676 | intel_clock(dev, refclk, &clock); | |
677 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
678 | return true; | |
679 | } | |
680 | ||
a4fc5ed6 KP |
681 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
682 | static bool | |
683 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
684 | int target, int refclk, intel_clock_t *match_clock, |
685 | intel_clock_t *best_clock) | |
a4fc5ed6 | 686 | { |
5eddb70b CW |
687 | intel_clock_t clock; |
688 | if (target < 200000) { | |
689 | clock.p1 = 2; | |
690 | clock.p2 = 10; | |
691 | clock.n = 2; | |
692 | clock.m1 = 23; | |
693 | clock.m2 = 8; | |
694 | } else { | |
695 | clock.p1 = 1; | |
696 | clock.p2 = 10; | |
697 | clock.n = 1; | |
698 | clock.m1 = 14; | |
699 | clock.m2 = 2; | |
700 | } | |
701 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
702 | clock.p = (clock.p1 * clock.p2); | |
703 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
704 | clock.vco = 0; | |
705 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
706 | return true; | |
a4fc5ed6 KP |
707 | } |
708 | ||
9d0498a2 JB |
709 | /** |
710 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
711 | * @dev: drm device | |
712 | * @pipe: pipe to wait for | |
713 | * | |
714 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
715 | * mode setting code. | |
716 | */ | |
717 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 718 | { |
9d0498a2 | 719 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 720 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 721 | |
300387c0 CW |
722 | /* Clear existing vblank status. Note this will clear any other |
723 | * sticky status fields as well. | |
724 | * | |
725 | * This races with i915_driver_irq_handler() with the result | |
726 | * that either function could miss a vblank event. Here it is not | |
727 | * fatal, as we will either wait upon the next vblank interrupt or | |
728 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
729 | * called during modeset at which time the GPU should be idle and | |
730 | * should *not* be performing page flips and thus not waiting on | |
731 | * vblanks... | |
732 | * Currently, the result of us stealing a vblank from the irq | |
733 | * handler is that a single frame will be skipped during swapbuffers. | |
734 | */ | |
735 | I915_WRITE(pipestat_reg, | |
736 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
737 | ||
9d0498a2 | 738 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
739 | if (wait_for(I915_READ(pipestat_reg) & |
740 | PIPE_VBLANK_INTERRUPT_STATUS, | |
741 | 50)) | |
9d0498a2 JB |
742 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
743 | } | |
744 | ||
ab7ad7f6 KP |
745 | /* |
746 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
747 | * @dev: drm device |
748 | * @pipe: pipe to wait for | |
749 | * | |
750 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
751 | * spinning on the vblank interrupt status bit, since we won't actually | |
752 | * see an interrupt when the pipe is disabled. | |
753 | * | |
ab7ad7f6 KP |
754 | * On Gen4 and above: |
755 | * wait for the pipe register state bit to turn off | |
756 | * | |
757 | * Otherwise: | |
758 | * wait for the display line value to settle (it usually | |
759 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 760 | * |
9d0498a2 | 761 | */ |
58e10eb9 | 762 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
763 | { |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
765 | |
766 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 767 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
768 | |
769 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
770 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
771 | 100)) | |
ab7ad7f6 KP |
772 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
773 | } else { | |
774 | u32 last_line; | |
58e10eb9 | 775 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
776 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
777 | ||
778 | /* Wait for the display line to settle */ | |
779 | do { | |
58e10eb9 | 780 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 781 | mdelay(5); |
58e10eb9 | 782 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
783 | time_after(timeout, jiffies)); |
784 | if (time_after(jiffies, timeout)) | |
785 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
786 | } | |
79e53945 JB |
787 | } |
788 | ||
b24e7179 JB |
789 | static const char *state_string(bool enabled) |
790 | { | |
791 | return enabled ? "on" : "off"; | |
792 | } | |
793 | ||
794 | /* Only for pre-ILK configs */ | |
795 | static void assert_pll(struct drm_i915_private *dev_priv, | |
796 | enum pipe pipe, bool state) | |
797 | { | |
798 | int reg; | |
799 | u32 val; | |
800 | bool cur_state; | |
801 | ||
802 | reg = DPLL(pipe); | |
803 | val = I915_READ(reg); | |
804 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
805 | WARN(cur_state != state, | |
806 | "PLL state assertion failure (expected %s, current %s)\n", | |
807 | state_string(state), state_string(cur_state)); | |
808 | } | |
809 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
810 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
811 | ||
040484af JB |
812 | /* For ILK+ */ |
813 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
814 | enum pipe pipe, bool state) | |
815 | { | |
816 | int reg; | |
817 | u32 val; | |
818 | bool cur_state; | |
819 | ||
d3ccbe86 JB |
820 | if (HAS_PCH_CPT(dev_priv->dev)) { |
821 | u32 pch_dpll; | |
822 | ||
823 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
824 | ||
825 | /* Make sure the selected PLL is enabled to the transcoder */ | |
826 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
827 | "transcoder %d PLL not enabled\n", pipe); | |
828 | ||
829 | /* Convert the transcoder pipe number to a pll pipe number */ | |
830 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
831 | } | |
832 | ||
040484af JB |
833 | reg = PCH_DPLL(pipe); |
834 | val = I915_READ(reg); | |
835 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
836 | WARN(cur_state != state, | |
837 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
838 | state_string(state), state_string(cur_state)); | |
839 | } | |
840 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
841 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
842 | ||
843 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
844 | enum pipe pipe, bool state) | |
845 | { | |
846 | int reg; | |
847 | u32 val; | |
848 | bool cur_state; | |
849 | ||
850 | reg = FDI_TX_CTL(pipe); | |
851 | val = I915_READ(reg); | |
852 | cur_state = !!(val & FDI_TX_ENABLE); | |
853 | WARN(cur_state != state, | |
854 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
855 | state_string(state), state_string(cur_state)); | |
856 | } | |
857 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
858 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
859 | ||
860 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
861 | enum pipe pipe, bool state) | |
862 | { | |
863 | int reg; | |
864 | u32 val; | |
865 | bool cur_state; | |
866 | ||
867 | reg = FDI_RX_CTL(pipe); | |
868 | val = I915_READ(reg); | |
869 | cur_state = !!(val & FDI_RX_ENABLE); | |
870 | WARN(cur_state != state, | |
871 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
872 | state_string(state), state_string(cur_state)); | |
873 | } | |
874 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
875 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
876 | ||
877 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
878 | enum pipe pipe) | |
879 | { | |
880 | int reg; | |
881 | u32 val; | |
882 | ||
883 | /* ILK FDI PLL is always enabled */ | |
884 | if (dev_priv->info->gen == 5) | |
885 | return; | |
886 | ||
887 | reg = FDI_TX_CTL(pipe); | |
888 | val = I915_READ(reg); | |
889 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
890 | } | |
891 | ||
892 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
893 | enum pipe pipe) | |
894 | { | |
895 | int reg; | |
896 | u32 val; | |
897 | ||
898 | reg = FDI_RX_CTL(pipe); | |
899 | val = I915_READ(reg); | |
900 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
901 | } | |
902 | ||
ea0760cf JB |
903 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
904 | enum pipe pipe) | |
905 | { | |
906 | int pp_reg, lvds_reg; | |
907 | u32 val; | |
908 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 909 | bool locked = true; |
ea0760cf JB |
910 | |
911 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
912 | pp_reg = PCH_PP_CONTROL; | |
913 | lvds_reg = PCH_LVDS; | |
914 | } else { | |
915 | pp_reg = PP_CONTROL; | |
916 | lvds_reg = LVDS; | |
917 | } | |
918 | ||
919 | val = I915_READ(pp_reg); | |
920 | if (!(val & PANEL_POWER_ON) || | |
921 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
922 | locked = false; | |
923 | ||
924 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
925 | panel_pipe = PIPE_B; | |
926 | ||
927 | WARN(panel_pipe == pipe && locked, | |
928 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 929 | pipe_name(pipe)); |
ea0760cf JB |
930 | } |
931 | ||
b840d907 JB |
932 | void assert_pipe(struct drm_i915_private *dev_priv, |
933 | enum pipe pipe, bool state) | |
b24e7179 JB |
934 | { |
935 | int reg; | |
936 | u32 val; | |
63d7bbe9 | 937 | bool cur_state; |
b24e7179 | 938 | |
8e636784 DV |
939 | /* if we need the pipe A quirk it must be always on */ |
940 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
941 | state = true; | |
942 | ||
b24e7179 JB |
943 | reg = PIPECONF(pipe); |
944 | val = I915_READ(reg); | |
63d7bbe9 JB |
945 | cur_state = !!(val & PIPECONF_ENABLE); |
946 | WARN(cur_state != state, | |
947 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 948 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
949 | } |
950 | ||
931872fc CW |
951 | static void assert_plane(struct drm_i915_private *dev_priv, |
952 | enum plane plane, bool state) | |
b24e7179 JB |
953 | { |
954 | int reg; | |
955 | u32 val; | |
931872fc | 956 | bool cur_state; |
b24e7179 JB |
957 | |
958 | reg = DSPCNTR(plane); | |
959 | val = I915_READ(reg); | |
931872fc CW |
960 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
961 | WARN(cur_state != state, | |
962 | "plane %c assertion failure (expected %s, current %s)\n", | |
963 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
964 | } |
965 | ||
931872fc CW |
966 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
967 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
968 | ||
b24e7179 JB |
969 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
970 | enum pipe pipe) | |
971 | { | |
972 | int reg, i; | |
973 | u32 val; | |
974 | int cur_pipe; | |
975 | ||
19ec1358 | 976 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
977 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
978 | reg = DSPCNTR(pipe); | |
979 | val = I915_READ(reg); | |
980 | WARN((val & DISPLAY_PLANE_ENABLE), | |
981 | "plane %c assertion failure, should be disabled but not\n", | |
982 | plane_name(pipe)); | |
19ec1358 | 983 | return; |
28c05794 | 984 | } |
19ec1358 | 985 | |
b24e7179 JB |
986 | /* Need to check both planes against the pipe */ |
987 | for (i = 0; i < 2; i++) { | |
988 | reg = DSPCNTR(i); | |
989 | val = I915_READ(reg); | |
990 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
991 | DISPPLANE_SEL_PIPE_SHIFT; | |
992 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
993 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
994 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
995 | } |
996 | } | |
997 | ||
92f2584a JB |
998 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
999 | { | |
1000 | u32 val; | |
1001 | bool enabled; | |
1002 | ||
1003 | val = I915_READ(PCH_DREF_CONTROL); | |
1004 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1005 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1006 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1007 | } | |
1008 | ||
1009 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool enabled; | |
1015 | ||
1016 | reg = TRANSCONF(pipe); | |
1017 | val = I915_READ(reg); | |
1018 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1019 | WARN(enabled, |
1020 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1021 | pipe_name(pipe)); | |
92f2584a JB |
1022 | } |
1023 | ||
4e634389 KP |
1024 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1025 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1026 | { |
1027 | if ((val & DP_PORT_EN) == 0) | |
1028 | return false; | |
1029 | ||
1030 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1031 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1032 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1033 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1034 | return false; | |
1035 | } else { | |
1036 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1037 | return false; | |
1038 | } | |
1039 | return true; | |
1040 | } | |
1041 | ||
1519b995 KP |
1042 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1043 | enum pipe pipe, u32 val) | |
1044 | { | |
1045 | if ((val & PORT_ENABLE) == 0) | |
1046 | return false; | |
1047 | ||
1048 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1049 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1050 | return false; | |
1051 | } else { | |
1052 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1053 | return false; | |
1054 | } | |
1055 | return true; | |
1056 | } | |
1057 | ||
1058 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1059 | enum pipe pipe, u32 val) | |
1060 | { | |
1061 | if ((val & LVDS_PORT_EN) == 0) | |
1062 | return false; | |
1063 | ||
1064 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1065 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1066 | return false; | |
1067 | } else { | |
1068 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1069 | return false; | |
1070 | } | |
1071 | return true; | |
1072 | } | |
1073 | ||
1074 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1075 | enum pipe pipe, u32 val) | |
1076 | { | |
1077 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1078 | return false; | |
1079 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1080 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1081 | return false; | |
1082 | } else { | |
1083 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1084 | return false; | |
1085 | } | |
1086 | return true; | |
1087 | } | |
1088 | ||
291906f1 | 1089 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1090 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1091 | { |
47a05eca | 1092 | u32 val = I915_READ(reg); |
4e634389 | 1093 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1094 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1095 | reg, pipe_name(pipe)); |
291906f1 JB |
1096 | } |
1097 | ||
1098 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1099 | enum pipe pipe, int reg) | |
1100 | { | |
47a05eca | 1101 | u32 val = I915_READ(reg); |
1519b995 | 1102 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1103 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1104 | reg, pipe_name(pipe)); |
291906f1 JB |
1105 | } |
1106 | ||
1107 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1108 | enum pipe pipe) | |
1109 | { | |
1110 | int reg; | |
1111 | u32 val; | |
291906f1 | 1112 | |
f0575e92 KP |
1113 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1114 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1115 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1116 | |
1117 | reg = PCH_ADPA; | |
1118 | val = I915_READ(reg); | |
1519b995 | 1119 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1120 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1121 | pipe_name(pipe)); |
291906f1 JB |
1122 | |
1123 | reg = PCH_LVDS; | |
1124 | val = I915_READ(reg); | |
1519b995 | 1125 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1126 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1127 | pipe_name(pipe)); |
291906f1 JB |
1128 | |
1129 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1130 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1131 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1132 | } | |
1133 | ||
63d7bbe9 JB |
1134 | /** |
1135 | * intel_enable_pll - enable a PLL | |
1136 | * @dev_priv: i915 private structure | |
1137 | * @pipe: pipe PLL to enable | |
1138 | * | |
1139 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1140 | * make sure the PLL reg is writable first though, since the panel write | |
1141 | * protect mechanism may be enabled. | |
1142 | * | |
1143 | * Note! This is for pre-ILK only. | |
1144 | */ | |
1145 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1146 | { | |
1147 | int reg; | |
1148 | u32 val; | |
1149 | ||
1150 | /* No really, not for ILK+ */ | |
1151 | BUG_ON(dev_priv->info->gen >= 5); | |
1152 | ||
1153 | /* PLL is protected by panel, make sure we can write it */ | |
1154 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1155 | assert_panel_unlocked(dev_priv, pipe); | |
1156 | ||
1157 | reg = DPLL(pipe); | |
1158 | val = I915_READ(reg); | |
1159 | val |= DPLL_VCO_ENABLE; | |
1160 | ||
1161 | /* We do this three times for luck */ | |
1162 | I915_WRITE(reg, val); | |
1163 | POSTING_READ(reg); | |
1164 | udelay(150); /* wait for warmup */ | |
1165 | I915_WRITE(reg, val); | |
1166 | POSTING_READ(reg); | |
1167 | udelay(150); /* wait for warmup */ | |
1168 | I915_WRITE(reg, val); | |
1169 | POSTING_READ(reg); | |
1170 | udelay(150); /* wait for warmup */ | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * intel_disable_pll - disable a PLL | |
1175 | * @dev_priv: i915 private structure | |
1176 | * @pipe: pipe PLL to disable | |
1177 | * | |
1178 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1179 | * | |
1180 | * Note! This is for pre-ILK only. | |
1181 | */ | |
1182 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1183 | { | |
1184 | int reg; | |
1185 | u32 val; | |
1186 | ||
1187 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1188 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1189 | return; | |
1190 | ||
1191 | /* Make sure the pipe isn't still relying on us */ | |
1192 | assert_pipe_disabled(dev_priv, pipe); | |
1193 | ||
1194 | reg = DPLL(pipe); | |
1195 | val = I915_READ(reg); | |
1196 | val &= ~DPLL_VCO_ENABLE; | |
1197 | I915_WRITE(reg, val); | |
1198 | POSTING_READ(reg); | |
1199 | } | |
1200 | ||
92f2584a JB |
1201 | /** |
1202 | * intel_enable_pch_pll - enable PCH PLL | |
1203 | * @dev_priv: i915 private structure | |
1204 | * @pipe: pipe PLL to enable | |
1205 | * | |
1206 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1207 | * drives the transcoder clock. | |
1208 | */ | |
1209 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1210 | enum pipe pipe) | |
1211 | { | |
1212 | int reg; | |
1213 | u32 val; | |
1214 | ||
4c609cb8 JB |
1215 | if (pipe > 1) |
1216 | return; | |
1217 | ||
92f2584a JB |
1218 | /* PCH only available on ILK+ */ |
1219 | BUG_ON(dev_priv->info->gen < 5); | |
1220 | ||
1221 | /* PCH refclock must be enabled first */ | |
1222 | assert_pch_refclk_enabled(dev_priv); | |
1223 | ||
1224 | reg = PCH_DPLL(pipe); | |
1225 | val = I915_READ(reg); | |
1226 | val |= DPLL_VCO_ENABLE; | |
1227 | I915_WRITE(reg, val); | |
1228 | POSTING_READ(reg); | |
1229 | udelay(200); | |
1230 | } | |
1231 | ||
1232 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1233 | enum pipe pipe) | |
1234 | { | |
1235 | int reg; | |
7a419866 JB |
1236 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
1237 | pll_sel = TRANSC_DPLL_ENABLE; | |
92f2584a | 1238 | |
4c609cb8 JB |
1239 | if (pipe > 1) |
1240 | return; | |
1241 | ||
92f2584a JB |
1242 | /* PCH only available on ILK+ */ |
1243 | BUG_ON(dev_priv->info->gen < 5); | |
1244 | ||
1245 | /* Make sure transcoder isn't still depending on us */ | |
1246 | assert_transcoder_disabled(dev_priv, pipe); | |
1247 | ||
7a419866 JB |
1248 | if (pipe == 0) |
1249 | pll_sel |= TRANSC_DPLLA_SEL; | |
1250 | else if (pipe == 1) | |
1251 | pll_sel |= TRANSC_DPLLB_SEL; | |
1252 | ||
1253 | ||
1254 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) | |
1255 | return; | |
1256 | ||
92f2584a JB |
1257 | reg = PCH_DPLL(pipe); |
1258 | val = I915_READ(reg); | |
1259 | val &= ~DPLL_VCO_ENABLE; | |
1260 | I915_WRITE(reg, val); | |
1261 | POSTING_READ(reg); | |
1262 | udelay(200); | |
1263 | } | |
1264 | ||
040484af JB |
1265 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1266 | enum pipe pipe) | |
1267 | { | |
1268 | int reg; | |
1269 | u32 val; | |
1270 | ||
1271 | /* PCH only available on ILK+ */ | |
1272 | BUG_ON(dev_priv->info->gen < 5); | |
1273 | ||
1274 | /* Make sure PCH DPLL is enabled */ | |
1275 | assert_pch_pll_enabled(dev_priv, pipe); | |
1276 | ||
1277 | /* FDI must be feeding us bits for PCH ports */ | |
1278 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1279 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1280 | ||
1281 | reg = TRANSCONF(pipe); | |
1282 | val = I915_READ(reg); | |
e9bcff5c JB |
1283 | |
1284 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1285 | /* | |
1286 | * make the BPC in transcoder be consistent with | |
1287 | * that in pipeconf reg. | |
1288 | */ | |
1289 | val &= ~PIPE_BPC_MASK; | |
1290 | val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; | |
1291 | } | |
040484af JB |
1292 | I915_WRITE(reg, val | TRANS_ENABLE); |
1293 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1294 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1295 | } | |
1296 | ||
1297 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1298 | enum pipe pipe) | |
1299 | { | |
1300 | int reg; | |
1301 | u32 val; | |
1302 | ||
1303 | /* FDI relies on the transcoder */ | |
1304 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1305 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1306 | ||
291906f1 JB |
1307 | /* Ports must be off as well */ |
1308 | assert_pch_ports_disabled(dev_priv, pipe); | |
1309 | ||
040484af JB |
1310 | reg = TRANSCONF(pipe); |
1311 | val = I915_READ(reg); | |
1312 | val &= ~TRANS_ENABLE; | |
1313 | I915_WRITE(reg, val); | |
1314 | /* wait for PCH transcoder off, transcoder state */ | |
1315 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1316 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1317 | } |
1318 | ||
b24e7179 | 1319 | /** |
309cfea8 | 1320 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1321 | * @dev_priv: i915 private structure |
1322 | * @pipe: pipe to enable | |
040484af | 1323 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1324 | * |
1325 | * Enable @pipe, making sure that various hardware specific requirements | |
1326 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1327 | * | |
1328 | * @pipe should be %PIPE_A or %PIPE_B. | |
1329 | * | |
1330 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1331 | * returning. | |
1332 | */ | |
040484af JB |
1333 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1334 | bool pch_port) | |
b24e7179 JB |
1335 | { |
1336 | int reg; | |
1337 | u32 val; | |
1338 | ||
1339 | /* | |
1340 | * A pipe without a PLL won't actually be able to drive bits from | |
1341 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1342 | * need the check. | |
1343 | */ | |
1344 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1345 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1346 | else { |
1347 | if (pch_port) { | |
1348 | /* if driving the PCH, we need FDI enabled */ | |
1349 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1350 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1351 | } | |
1352 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1353 | } | |
b24e7179 JB |
1354 | |
1355 | reg = PIPECONF(pipe); | |
1356 | val = I915_READ(reg); | |
00d70b15 CW |
1357 | if (val & PIPECONF_ENABLE) |
1358 | return; | |
1359 | ||
1360 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1361 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1362 | } | |
1363 | ||
1364 | /** | |
309cfea8 | 1365 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1366 | * @dev_priv: i915 private structure |
1367 | * @pipe: pipe to disable | |
1368 | * | |
1369 | * Disable @pipe, making sure that various hardware specific requirements | |
1370 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1371 | * | |
1372 | * @pipe should be %PIPE_A or %PIPE_B. | |
1373 | * | |
1374 | * Will wait until the pipe has shut down before returning. | |
1375 | */ | |
1376 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1377 | enum pipe pipe) | |
1378 | { | |
1379 | int reg; | |
1380 | u32 val; | |
1381 | ||
1382 | /* | |
1383 | * Make sure planes won't keep trying to pump pixels to us, | |
1384 | * or we might hang the display. | |
1385 | */ | |
1386 | assert_planes_disabled(dev_priv, pipe); | |
1387 | ||
1388 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1389 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1390 | return; | |
1391 | ||
1392 | reg = PIPECONF(pipe); | |
1393 | val = I915_READ(reg); | |
00d70b15 CW |
1394 | if ((val & PIPECONF_ENABLE) == 0) |
1395 | return; | |
1396 | ||
1397 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1398 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1399 | } | |
1400 | ||
d74362c9 KP |
1401 | /* |
1402 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1403 | * trigger in order to latch. The display address reg provides this. | |
1404 | */ | |
1405 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1406 | enum plane plane) | |
1407 | { | |
1408 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1409 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1410 | } | |
1411 | ||
b24e7179 JB |
1412 | /** |
1413 | * intel_enable_plane - enable a display plane on a given pipe | |
1414 | * @dev_priv: i915 private structure | |
1415 | * @plane: plane to enable | |
1416 | * @pipe: pipe being fed | |
1417 | * | |
1418 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1419 | */ | |
1420 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1421 | enum plane plane, enum pipe pipe) | |
1422 | { | |
1423 | int reg; | |
1424 | u32 val; | |
1425 | ||
1426 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1427 | assert_pipe_enabled(dev_priv, pipe); | |
1428 | ||
1429 | reg = DSPCNTR(plane); | |
1430 | val = I915_READ(reg); | |
00d70b15 CW |
1431 | if (val & DISPLAY_PLANE_ENABLE) |
1432 | return; | |
1433 | ||
1434 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1435 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1436 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1437 | } | |
1438 | ||
b24e7179 JB |
1439 | /** |
1440 | * intel_disable_plane - disable a display plane | |
1441 | * @dev_priv: i915 private structure | |
1442 | * @plane: plane to disable | |
1443 | * @pipe: pipe consuming the data | |
1444 | * | |
1445 | * Disable @plane; should be an independent operation. | |
1446 | */ | |
1447 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1448 | enum plane plane, enum pipe pipe) | |
1449 | { | |
1450 | int reg; | |
1451 | u32 val; | |
1452 | ||
1453 | reg = DSPCNTR(plane); | |
1454 | val = I915_READ(reg); | |
00d70b15 CW |
1455 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1456 | return; | |
1457 | ||
1458 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1459 | intel_flush_display_plane(dev_priv, plane); |
1460 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1461 | } | |
1462 | ||
47a05eca | 1463 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1464 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1465 | { |
1466 | u32 val = I915_READ(reg); | |
4e634389 | 1467 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1468 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1469 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1470 | } |
47a05eca JB |
1471 | } |
1472 | ||
1473 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1474 | enum pipe pipe, int reg) | |
1475 | { | |
1476 | u32 val = I915_READ(reg); | |
1519b995 | 1477 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1478 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1479 | reg, pipe); | |
47a05eca | 1480 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1481 | } |
47a05eca JB |
1482 | } |
1483 | ||
1484 | /* Disable any ports connected to this transcoder */ | |
1485 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1486 | enum pipe pipe) | |
1487 | { | |
1488 | u32 reg, val; | |
1489 | ||
1490 | val = I915_READ(PCH_PP_CONTROL); | |
1491 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1492 | ||
f0575e92 KP |
1493 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1494 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1495 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1496 | |
1497 | reg = PCH_ADPA; | |
1498 | val = I915_READ(reg); | |
1519b995 | 1499 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1500 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1501 | ||
1502 | reg = PCH_LVDS; | |
1503 | val = I915_READ(reg); | |
1519b995 KP |
1504 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1505 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1506 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1507 | POSTING_READ(reg); | |
1508 | udelay(100); | |
1509 | } | |
1510 | ||
1511 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1512 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1513 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1514 | } | |
1515 | ||
43a9539f CW |
1516 | static void i8xx_disable_fbc(struct drm_device *dev) |
1517 | { | |
1518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1519 | u32 fbc_ctl; | |
1520 | ||
1521 | /* Disable compression */ | |
1522 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1523 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1524 | return; | |
1525 | ||
1526 | fbc_ctl &= ~FBC_CTL_EN; | |
1527 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1528 | ||
1529 | /* Wait for compressing bit to clear */ | |
1530 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1531 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1532 | return; | |
1533 | } | |
1534 | ||
1535 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1536 | } | |
1537 | ||
80824003 JB |
1538 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1539 | { | |
1540 | struct drm_device *dev = crtc->dev; | |
1541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1542 | struct drm_framebuffer *fb = crtc->fb; | |
1543 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1544 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1546 | int cfb_pitch; |
80824003 JB |
1547 | int plane, i; |
1548 | u32 fbc_ctl, fbc_ctl2; | |
1549 | ||
016b9b61 | 1550 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
01f2c773 VS |
1551 | if (fb->pitches[0] < cfb_pitch) |
1552 | cfb_pitch = fb->pitches[0]; | |
80824003 JB |
1553 | |
1554 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1555 | cfb_pitch = (cfb_pitch / 64) - 1; |
1556 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1557 | |
1558 | /* Clear old tags */ | |
1559 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1560 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1561 | ||
1562 | /* Set it up... */ | |
de568510 CW |
1563 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1564 | fbc_ctl2 |= plane; | |
80824003 JB |
1565 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1566 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1567 | ||
1568 | /* enable it... */ | |
1569 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1570 | if (IS_I945GM(dev)) |
49677901 | 1571 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1572 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1573 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1574 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1575 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1576 | ||
016b9b61 CW |
1577 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1578 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1579 | } |
1580 | ||
ee5382ae | 1581 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1582 | { |
80824003 JB |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; |
1584 | ||
1585 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1586 | } | |
1587 | ||
74dff282 JB |
1588 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1589 | { | |
1590 | struct drm_device *dev = crtc->dev; | |
1591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1592 | struct drm_framebuffer *fb = crtc->fb; | |
1593 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1594 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1596 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1597 | unsigned long stall_watermark = 200; |
1598 | u32 dpfc_ctl; | |
1599 | ||
74dff282 | 1600 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1601 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1602 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1603 | |
74dff282 JB |
1604 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1605 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1606 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1607 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1608 | ||
1609 | /* enable it... */ | |
1610 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1611 | ||
28c97730 | 1612 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1613 | } |
1614 | ||
43a9539f | 1615 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1616 | { |
1617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1618 | u32 dpfc_ctl; | |
1619 | ||
1620 | /* Disable compression */ | |
1621 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1622 | if (dpfc_ctl & DPFC_CTL_EN) { |
1623 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1624 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1625 | |
bed4a673 CW |
1626 | DRM_DEBUG_KMS("disabled FBC\n"); |
1627 | } | |
74dff282 JB |
1628 | } |
1629 | ||
ee5382ae | 1630 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1631 | { |
74dff282 JB |
1632 | struct drm_i915_private *dev_priv = dev->dev_private; |
1633 | ||
1634 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1635 | } | |
1636 | ||
4efe0708 JB |
1637 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1638 | { | |
1639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1640 | u32 blt_ecoskpd; | |
1641 | ||
1642 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1643 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1644 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1645 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1646 | GEN6_BLITTER_LOCK_SHIFT; | |
1647 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1648 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1649 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1650 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1651 | GEN6_BLITTER_LOCK_SHIFT); | |
1652 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1653 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1654 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1655 | } |
1656 | ||
b52eb4dc ZY |
1657 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1658 | { | |
1659 | struct drm_device *dev = crtc->dev; | |
1660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1661 | struct drm_framebuffer *fb = crtc->fb; | |
1662 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1663 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1665 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1666 | unsigned long stall_watermark = 200; |
1667 | u32 dpfc_ctl; | |
1668 | ||
bed4a673 | 1669 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1670 | dpfc_ctl &= DPFC_RESERVED; |
1671 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1672 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1673 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1674 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1675 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1676 | |
b52eb4dc ZY |
1677 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1678 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1679 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1680 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1681 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1682 | /* enable it... */ |
bed4a673 | 1683 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1684 | |
9c04f015 YL |
1685 | if (IS_GEN6(dev)) { |
1686 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1687 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1688 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1689 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1690 | } |
1691 | ||
b52eb4dc ZY |
1692 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1693 | } | |
1694 | ||
43a9539f | 1695 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1696 | { |
1697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1698 | u32 dpfc_ctl; | |
1699 | ||
1700 | /* Disable compression */ | |
1701 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1702 | if (dpfc_ctl & DPFC_CTL_EN) { |
1703 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1704 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1705 | |
bed4a673 CW |
1706 | DRM_DEBUG_KMS("disabled FBC\n"); |
1707 | } | |
b52eb4dc ZY |
1708 | } |
1709 | ||
1710 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1711 | { | |
1712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1713 | ||
1714 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1715 | } | |
1716 | ||
ee5382ae AJ |
1717 | bool intel_fbc_enabled(struct drm_device *dev) |
1718 | { | |
1719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1720 | ||
1721 | if (!dev_priv->display.fbc_enabled) | |
1722 | return false; | |
1723 | ||
1724 | return dev_priv->display.fbc_enabled(dev); | |
1725 | } | |
1726 | ||
1630fe75 CW |
1727 | static void intel_fbc_work_fn(struct work_struct *__work) |
1728 | { | |
1729 | struct intel_fbc_work *work = | |
1730 | container_of(to_delayed_work(__work), | |
1731 | struct intel_fbc_work, work); | |
1732 | struct drm_device *dev = work->crtc->dev; | |
1733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1734 | ||
1735 | mutex_lock(&dev->struct_mutex); | |
1736 | if (work == dev_priv->fbc_work) { | |
1737 | /* Double check that we haven't switched fb without cancelling | |
1738 | * the prior work. | |
1739 | */ | |
016b9b61 | 1740 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1741 | dev_priv->display.enable_fbc(work->crtc, |
1742 | work->interval); | |
1743 | ||
016b9b61 CW |
1744 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1745 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1746 | dev_priv->cfb_y = work->crtc->y; | |
1747 | } | |
1748 | ||
1630fe75 CW |
1749 | dev_priv->fbc_work = NULL; |
1750 | } | |
1751 | mutex_unlock(&dev->struct_mutex); | |
1752 | ||
1753 | kfree(work); | |
1754 | } | |
1755 | ||
1756 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1757 | { | |
1758 | if (dev_priv->fbc_work == NULL) | |
1759 | return; | |
1760 | ||
1761 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1762 | ||
1763 | /* Synchronisation is provided by struct_mutex and checking of | |
1764 | * dev_priv->fbc_work, so we can perform the cancellation | |
1765 | * entirely asynchronously. | |
1766 | */ | |
1767 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1768 | /* tasklet was killed before being run, clean up */ | |
1769 | kfree(dev_priv->fbc_work); | |
1770 | ||
1771 | /* Mark the work as no longer wanted so that if it does | |
1772 | * wake-up (because the work was already running and waiting | |
1773 | * for our mutex), it will discover that is no longer | |
1774 | * necessary to run. | |
1775 | */ | |
1776 | dev_priv->fbc_work = NULL; | |
1777 | } | |
1778 | ||
43a9539f | 1779 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1780 | { |
1630fe75 CW |
1781 | struct intel_fbc_work *work; |
1782 | struct drm_device *dev = crtc->dev; | |
1783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1784 | |
1785 | if (!dev_priv->display.enable_fbc) | |
1786 | return; | |
1787 | ||
1630fe75 CW |
1788 | intel_cancel_fbc_work(dev_priv); |
1789 | ||
1790 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1791 | if (work == NULL) { | |
1792 | dev_priv->display.enable_fbc(crtc, interval); | |
1793 | return; | |
1794 | } | |
1795 | ||
1796 | work->crtc = crtc; | |
1797 | work->fb = crtc->fb; | |
1798 | work->interval = interval; | |
1799 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1800 | ||
1801 | dev_priv->fbc_work = work; | |
1802 | ||
1803 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1804 | ||
1805 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1806 | * display to settle before starting the compression. Note that |
1807 | * this delay also serves a second purpose: it allows for a | |
1808 | * vblank to pass after disabling the FBC before we attempt | |
1809 | * to modify the control registers. | |
1630fe75 CW |
1810 | * |
1811 | * A more complicated solution would involve tracking vblanks | |
1812 | * following the termination of the page-flipping sequence | |
1813 | * and indeed performing the enable as a co-routine and not | |
1814 | * waiting synchronously upon the vblank. | |
1815 | */ | |
1816 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1817 | } |
1818 | ||
1819 | void intel_disable_fbc(struct drm_device *dev) | |
1820 | { | |
1821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1822 | ||
1630fe75 CW |
1823 | intel_cancel_fbc_work(dev_priv); |
1824 | ||
ee5382ae AJ |
1825 | if (!dev_priv->display.disable_fbc) |
1826 | return; | |
1827 | ||
1828 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1829 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1830 | } |
1831 | ||
80824003 JB |
1832 | /** |
1833 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1834 | * @dev: the drm_device |
80824003 JB |
1835 | * |
1836 | * Set up the framebuffer compression hardware at mode set time. We | |
1837 | * enable it if possible: | |
1838 | * - plane A only (on pre-965) | |
1839 | * - no pixel mulitply/line duplication | |
1840 | * - no alpha buffer discard | |
1841 | * - no dual wide | |
1842 | * - framebuffer <= 2048 in width, 1536 in height | |
1843 | * | |
1844 | * We can't assume that any compression will take place (worst case), | |
1845 | * so the compressed buffer has to be the same size as the uncompressed | |
1846 | * one. It also must reside (along with the line length buffer) in | |
1847 | * stolen memory. | |
1848 | * | |
1849 | * We need to enable/disable FBC on a global basis. | |
1850 | */ | |
bed4a673 | 1851 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1852 | { |
80824003 | 1853 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1854 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1855 | struct intel_crtc *intel_crtc; | |
1856 | struct drm_framebuffer *fb; | |
80824003 | 1857 | struct intel_framebuffer *intel_fb; |
05394f39 | 1858 | struct drm_i915_gem_object *obj; |
cd0de039 | 1859 | int enable_fbc; |
9c928d16 JB |
1860 | |
1861 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1862 | |
1863 | if (!i915_powersave) | |
1864 | return; | |
1865 | ||
ee5382ae | 1866 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1867 | return; |
1868 | ||
80824003 JB |
1869 | /* |
1870 | * If FBC is already on, we just have to verify that we can | |
1871 | * keep it that way... | |
1872 | * Need to disable if: | |
9c928d16 | 1873 | * - more than one pipe is active |
80824003 JB |
1874 | * - changing FBC params (stride, fence, mode) |
1875 | * - new fb is too large to fit in compressed buffer | |
1876 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1877 | */ | |
9c928d16 | 1878 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1879 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1880 | if (crtc) { |
1881 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1882 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1883 | goto out_disable; | |
1884 | } | |
1885 | crtc = tmp_crtc; | |
1886 | } | |
9c928d16 | 1887 | } |
bed4a673 CW |
1888 | |
1889 | if (!crtc || crtc->fb == NULL) { | |
1890 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1891 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1892 | goto out_disable; |
1893 | } | |
bed4a673 CW |
1894 | |
1895 | intel_crtc = to_intel_crtc(crtc); | |
1896 | fb = crtc->fb; | |
1897 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1898 | obj = intel_fb->obj; |
bed4a673 | 1899 | |
cd0de039 KP |
1900 | enable_fbc = i915_enable_fbc; |
1901 | if (enable_fbc < 0) { | |
1902 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
1903 | enable_fbc = 1; | |
1904 | if (INTEL_INFO(dev)->gen <= 5) | |
1905 | enable_fbc = 0; | |
1906 | } | |
1907 | if (!enable_fbc) { | |
1908 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
1909 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
1910 | goto out_disable; | |
1911 | } | |
05394f39 | 1912 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1913 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1914 | "compression\n"); |
b5e50c3f | 1915 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1916 | goto out_disable; |
1917 | } | |
bed4a673 CW |
1918 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1919 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1920 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1921 | "disabling\n"); |
b5e50c3f | 1922 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1923 | goto out_disable; |
1924 | } | |
bed4a673 CW |
1925 | if ((crtc->mode.hdisplay > 2048) || |
1926 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1927 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1928 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1929 | goto out_disable; |
1930 | } | |
bed4a673 | 1931 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1932 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1933 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1934 | goto out_disable; |
1935 | } | |
de568510 CW |
1936 | |
1937 | /* The use of a CPU fence is mandatory in order to detect writes | |
1938 | * by the CPU to the scanout and trigger updates to the FBC. | |
1939 | */ | |
1940 | if (obj->tiling_mode != I915_TILING_X || | |
1941 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1942 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 1943 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1944 | goto out_disable; |
1945 | } | |
1946 | ||
c924b934 JW |
1947 | /* If the kernel debugger is active, always disable compression */ |
1948 | if (in_dbg_master()) | |
1949 | goto out_disable; | |
1950 | ||
016b9b61 CW |
1951 | /* If the scanout has not changed, don't modify the FBC settings. |
1952 | * Note that we make the fundamental assumption that the fb->obj | |
1953 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
1954 | * without first being decoupled from the scanout and FBC disabled. | |
1955 | */ | |
1956 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
1957 | dev_priv->cfb_fb == fb->base.id && | |
1958 | dev_priv->cfb_y == crtc->y) | |
1959 | return; | |
1960 | ||
1961 | if (intel_fbc_enabled(dev)) { | |
1962 | /* We update FBC along two paths, after changing fb/crtc | |
1963 | * configuration (modeswitching) and after page-flipping | |
1964 | * finishes. For the latter, we know that not only did | |
1965 | * we disable the FBC at the start of the page-flip | |
1966 | * sequence, but also more than one vblank has passed. | |
1967 | * | |
1968 | * For the former case of modeswitching, it is possible | |
1969 | * to switch between two FBC valid configurations | |
1970 | * instantaneously so we do need to disable the FBC | |
1971 | * before we can modify its control registers. We also | |
1972 | * have to wait for the next vblank for that to take | |
1973 | * effect. However, since we delay enabling FBC we can | |
1974 | * assume that a vblank has passed since disabling and | |
1975 | * that we can safely alter the registers in the deferred | |
1976 | * callback. | |
1977 | * | |
1978 | * In the scenario that we go from a valid to invalid | |
1979 | * and then back to valid FBC configuration we have | |
1980 | * no strict enforcement that a vblank occurred since | |
1981 | * disabling the FBC. However, along all current pipe | |
1982 | * disabling paths we do need to wait for a vblank at | |
1983 | * some point. And we wait before enabling FBC anyway. | |
1984 | */ | |
1985 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
1986 | intel_disable_fbc(dev); | |
1987 | } | |
1988 | ||
bed4a673 | 1989 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1990 | return; |
1991 | ||
1992 | out_disable: | |
80824003 | 1993 | /* Multiple disables should be harmless */ |
a939406f CW |
1994 | if (intel_fbc_enabled(dev)) { |
1995 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1996 | intel_disable_fbc(dev); |
a939406f | 1997 | } |
80824003 JB |
1998 | } |
1999 | ||
127bd2ac | 2000 | int |
48b956c5 | 2001 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2002 | struct drm_i915_gem_object *obj, |
919926ae | 2003 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2004 | { |
ce453d81 | 2005 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2006 | u32 alignment; |
2007 | int ret; | |
2008 | ||
05394f39 | 2009 | switch (obj->tiling_mode) { |
6b95a207 | 2010 | case I915_TILING_NONE: |
534843da CW |
2011 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2012 | alignment = 128 * 1024; | |
a6c45cf0 | 2013 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2014 | alignment = 4 * 1024; |
2015 | else | |
2016 | alignment = 64 * 1024; | |
6b95a207 KH |
2017 | break; |
2018 | case I915_TILING_X: | |
2019 | /* pin() will align the object as required by fence */ | |
2020 | alignment = 0; | |
2021 | break; | |
2022 | case I915_TILING_Y: | |
2023 | /* FIXME: Is this true? */ | |
2024 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
2025 | return -EINVAL; | |
2026 | default: | |
2027 | BUG(); | |
2028 | } | |
2029 | ||
ce453d81 | 2030 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2031 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2032 | if (ret) |
ce453d81 | 2033 | goto err_interruptible; |
6b95a207 KH |
2034 | |
2035 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2036 | * fence, whereas 965+ only requires a fence if using | |
2037 | * framebuffer compression. For simplicity, we always install | |
2038 | * a fence as the cost is not that onerous. | |
2039 | */ | |
05394f39 | 2040 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2041 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2042 | if (ret) |
2043 | goto err_unpin; | |
1690e1eb CW |
2044 | |
2045 | i915_gem_object_pin_fence(obj); | |
6b95a207 KH |
2046 | } |
2047 | ||
ce453d81 | 2048 | dev_priv->mm.interruptible = true; |
6b95a207 | 2049 | return 0; |
48b956c5 CW |
2050 | |
2051 | err_unpin: | |
2052 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2053 | err_interruptible: |
2054 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2055 | return ret; |
6b95a207 KH |
2056 | } |
2057 | ||
1690e1eb CW |
2058 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2059 | { | |
2060 | i915_gem_object_unpin_fence(obj); | |
2061 | i915_gem_object_unpin(obj); | |
2062 | } | |
2063 | ||
17638cd6 JB |
2064 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2065 | int x, int y) | |
81255565 JB |
2066 | { |
2067 | struct drm_device *dev = crtc->dev; | |
2068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2070 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2071 | struct drm_i915_gem_object *obj; |
81255565 JB |
2072 | int plane = intel_crtc->plane; |
2073 | unsigned long Start, Offset; | |
81255565 | 2074 | u32 dspcntr; |
5eddb70b | 2075 | u32 reg; |
81255565 JB |
2076 | |
2077 | switch (plane) { | |
2078 | case 0: | |
2079 | case 1: | |
2080 | break; | |
2081 | default: | |
2082 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2083 | return -EINVAL; | |
2084 | } | |
2085 | ||
2086 | intel_fb = to_intel_framebuffer(fb); | |
2087 | obj = intel_fb->obj; | |
81255565 | 2088 | |
5eddb70b CW |
2089 | reg = DSPCNTR(plane); |
2090 | dspcntr = I915_READ(reg); | |
81255565 JB |
2091 | /* Mask out pixel format bits in case we change it */ |
2092 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2093 | switch (fb->bits_per_pixel) { | |
2094 | case 8: | |
2095 | dspcntr |= DISPPLANE_8BPP; | |
2096 | break; | |
2097 | case 16: | |
2098 | if (fb->depth == 15) | |
2099 | dspcntr |= DISPPLANE_15_16BPP; | |
2100 | else | |
2101 | dspcntr |= DISPPLANE_16BPP; | |
2102 | break; | |
2103 | case 24: | |
2104 | case 32: | |
2105 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2106 | break; | |
2107 | default: | |
17638cd6 | 2108 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2109 | return -EINVAL; |
2110 | } | |
a6c45cf0 | 2111 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2112 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2113 | dspcntr |= DISPPLANE_TILED; |
2114 | else | |
2115 | dspcntr &= ~DISPPLANE_TILED; | |
2116 | } | |
2117 | ||
5eddb70b | 2118 | I915_WRITE(reg, dspcntr); |
81255565 | 2119 | |
05394f39 | 2120 | Start = obj->gtt_offset; |
01f2c773 | 2121 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2122 | |
4e6cfefc | 2123 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
01f2c773 VS |
2124 | Start, Offset, x, y, fb->pitches[0]); |
2125 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
a6c45cf0 | 2126 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2127 | I915_WRITE(DSPSURF(plane), Start); |
2128 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2129 | I915_WRITE(DSPADDR(plane), Offset); | |
2130 | } else | |
2131 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2132 | POSTING_READ(reg); | |
81255565 | 2133 | |
17638cd6 JB |
2134 | return 0; |
2135 | } | |
2136 | ||
2137 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2138 | struct drm_framebuffer *fb, int x, int y) | |
2139 | { | |
2140 | struct drm_device *dev = crtc->dev; | |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2143 | struct intel_framebuffer *intel_fb; | |
2144 | struct drm_i915_gem_object *obj; | |
2145 | int plane = intel_crtc->plane; | |
2146 | unsigned long Start, Offset; | |
2147 | u32 dspcntr; | |
2148 | u32 reg; | |
2149 | ||
2150 | switch (plane) { | |
2151 | case 0: | |
2152 | case 1: | |
27f8227b | 2153 | case 2: |
17638cd6 JB |
2154 | break; |
2155 | default: | |
2156 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2157 | return -EINVAL; | |
2158 | } | |
2159 | ||
2160 | intel_fb = to_intel_framebuffer(fb); | |
2161 | obj = intel_fb->obj; | |
2162 | ||
2163 | reg = DSPCNTR(plane); | |
2164 | dspcntr = I915_READ(reg); | |
2165 | /* Mask out pixel format bits in case we change it */ | |
2166 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2167 | switch (fb->bits_per_pixel) { | |
2168 | case 8: | |
2169 | dspcntr |= DISPPLANE_8BPP; | |
2170 | break; | |
2171 | case 16: | |
2172 | if (fb->depth != 16) | |
2173 | return -EINVAL; | |
2174 | ||
2175 | dspcntr |= DISPPLANE_16BPP; | |
2176 | break; | |
2177 | case 24: | |
2178 | case 32: | |
2179 | if (fb->depth == 24) | |
2180 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2181 | else if (fb->depth == 30) | |
2182 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2183 | else | |
2184 | return -EINVAL; | |
2185 | break; | |
2186 | default: | |
2187 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2188 | return -EINVAL; | |
2189 | } | |
2190 | ||
2191 | if (obj->tiling_mode != I915_TILING_NONE) | |
2192 | dspcntr |= DISPPLANE_TILED; | |
2193 | else | |
2194 | dspcntr &= ~DISPPLANE_TILED; | |
2195 | ||
2196 | /* must disable */ | |
2197 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2198 | ||
2199 | I915_WRITE(reg, dspcntr); | |
2200 | ||
2201 | Start = obj->gtt_offset; | |
01f2c773 | 2202 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
17638cd6 JB |
2203 | |
2204 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
01f2c773 VS |
2205 | Start, Offset, x, y, fb->pitches[0]); |
2206 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
17638cd6 JB |
2207 | I915_WRITE(DSPSURF(plane), Start); |
2208 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2209 | I915_WRITE(DSPADDR(plane), Offset); | |
2210 | POSTING_READ(reg); | |
2211 | ||
2212 | return 0; | |
2213 | } | |
2214 | ||
2215 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2216 | static int | |
2217 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2218 | int x, int y, enum mode_set_atomic state) | |
2219 | { | |
2220 | struct drm_device *dev = crtc->dev; | |
2221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2222 | int ret; | |
2223 | ||
2224 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2225 | if (ret) | |
2226 | return ret; | |
2227 | ||
bed4a673 | 2228 | intel_update_fbc(dev); |
3dec0095 | 2229 | intel_increase_pllclock(crtc); |
81255565 JB |
2230 | |
2231 | return 0; | |
2232 | } | |
2233 | ||
5c3b82e2 | 2234 | static int |
3c4fdcfb KH |
2235 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2236 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2237 | { |
2238 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2239 | struct drm_i915_master_private *master_priv; |
2240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2241 | int ret; |
79e53945 JB |
2242 | |
2243 | /* no fb bound */ | |
2244 | if (!crtc->fb) { | |
a5071c2f | 2245 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2246 | return 0; |
2247 | } | |
2248 | ||
265db958 | 2249 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2250 | case 0: |
2251 | case 1: | |
2252 | break; | |
27f8227b JB |
2253 | case 2: |
2254 | if (IS_IVYBRIDGE(dev)) | |
2255 | break; | |
2256 | /* fall through otherwise */ | |
5c3b82e2 | 2257 | default: |
a5071c2f | 2258 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2259 | return -EINVAL; |
79e53945 JB |
2260 | } |
2261 | ||
5c3b82e2 | 2262 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2263 | ret = intel_pin_and_fence_fb_obj(dev, |
2264 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2265 | NULL); |
5c3b82e2 CW |
2266 | if (ret != 0) { |
2267 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2268 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2269 | return ret; |
2270 | } | |
79e53945 | 2271 | |
265db958 | 2272 | if (old_fb) { |
e6c3a2a6 | 2273 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2274 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2275 | |
e6c3a2a6 | 2276 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2277 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2278 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2279 | |
2280 | /* Big Hammer, we also need to ensure that any pending | |
2281 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2282 | * current scanout is retired before unpinning the old | |
2283 | * framebuffer. | |
01eec727 CW |
2284 | * |
2285 | * This should only fail upon a hung GPU, in which case we | |
2286 | * can safely continue. | |
85345517 | 2287 | */ |
a8198eea | 2288 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2289 | (void) ret; |
265db958 CW |
2290 | } |
2291 | ||
21c74a8e JW |
2292 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2293 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2294 | if (ret) { |
1690e1eb | 2295 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2296 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2297 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2298 | return ret; |
79e53945 | 2299 | } |
3c4fdcfb | 2300 | |
b7f1de28 CW |
2301 | if (old_fb) { |
2302 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2303 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2304 | } |
652c393a | 2305 | |
5c3b82e2 | 2306 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2307 | |
2308 | if (!dev->primary->master) | |
5c3b82e2 | 2309 | return 0; |
79e53945 JB |
2310 | |
2311 | master_priv = dev->primary->master->driver_priv; | |
2312 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2313 | return 0; |
79e53945 | 2314 | |
265db958 | 2315 | if (intel_crtc->pipe) { |
79e53945 JB |
2316 | master_priv->sarea_priv->pipeB_x = x; |
2317 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2318 | } else { |
2319 | master_priv->sarea_priv->pipeA_x = x; | |
2320 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2321 | } |
5c3b82e2 CW |
2322 | |
2323 | return 0; | |
79e53945 JB |
2324 | } |
2325 | ||
5eddb70b | 2326 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2327 | { |
2328 | struct drm_device *dev = crtc->dev; | |
2329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2330 | u32 dpa_ctl; | |
2331 | ||
28c97730 | 2332 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2333 | dpa_ctl = I915_READ(DP_A); |
2334 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2335 | ||
2336 | if (clock < 200000) { | |
2337 | u32 temp; | |
2338 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2339 | /* workaround for 160Mhz: | |
2340 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2341 | 2) program 0x46010 bit 0 = 1 | |
2342 | 3) program 0x46034 bit 24 = 1 | |
2343 | 4) program 0x64000 bit 14 = 1 | |
2344 | */ | |
2345 | temp = I915_READ(0x4600c); | |
2346 | temp &= 0xffff0000; | |
2347 | I915_WRITE(0x4600c, temp | 0x8124); | |
2348 | ||
2349 | temp = I915_READ(0x46010); | |
2350 | I915_WRITE(0x46010, temp | 1); | |
2351 | ||
2352 | temp = I915_READ(0x46034); | |
2353 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2354 | } else { | |
2355 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2356 | } | |
2357 | I915_WRITE(DP_A, dpa_ctl); | |
2358 | ||
5eddb70b | 2359 | POSTING_READ(DP_A); |
32f9d658 ZW |
2360 | udelay(500); |
2361 | } | |
2362 | ||
5e84e1a4 ZW |
2363 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2364 | { | |
2365 | struct drm_device *dev = crtc->dev; | |
2366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2368 | int pipe = intel_crtc->pipe; | |
2369 | u32 reg, temp; | |
2370 | ||
2371 | /* enable normal train */ | |
2372 | reg = FDI_TX_CTL(pipe); | |
2373 | temp = I915_READ(reg); | |
61e499bf | 2374 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2375 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2376 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2377 | } else { |
2378 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2379 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2380 | } |
5e84e1a4 ZW |
2381 | I915_WRITE(reg, temp); |
2382 | ||
2383 | reg = FDI_RX_CTL(pipe); | |
2384 | temp = I915_READ(reg); | |
2385 | if (HAS_PCH_CPT(dev)) { | |
2386 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2387 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2388 | } else { | |
2389 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2390 | temp |= FDI_LINK_TRAIN_NONE; | |
2391 | } | |
2392 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2393 | ||
2394 | /* wait one idle pattern time */ | |
2395 | POSTING_READ(reg); | |
2396 | udelay(1000); | |
357555c0 JB |
2397 | |
2398 | /* IVB wants error correction enabled */ | |
2399 | if (IS_IVYBRIDGE(dev)) | |
2400 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2401 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2402 | } |
2403 | ||
291427f5 JB |
2404 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2405 | { | |
2406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2407 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2408 | ||
2409 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2410 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2411 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2412 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2413 | POSTING_READ(SOUTH_CHICKEN1); | |
2414 | } | |
2415 | ||
8db9d77b ZW |
2416 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2417 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2418 | { | |
2419 | struct drm_device *dev = crtc->dev; | |
2420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2422 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2423 | int plane = intel_crtc->plane; |
5eddb70b | 2424 | u32 reg, temp, tries; |
8db9d77b | 2425 | |
0fc932b8 JB |
2426 | /* FDI needs bits from pipe & plane first */ |
2427 | assert_pipe_enabled(dev_priv, pipe); | |
2428 | assert_plane_enabled(dev_priv, plane); | |
2429 | ||
e1a44743 AJ |
2430 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2431 | for train result */ | |
5eddb70b CW |
2432 | reg = FDI_RX_IMR(pipe); |
2433 | temp = I915_READ(reg); | |
e1a44743 AJ |
2434 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2435 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2436 | I915_WRITE(reg, temp); |
2437 | I915_READ(reg); | |
e1a44743 AJ |
2438 | udelay(150); |
2439 | ||
8db9d77b | 2440 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2441 | reg = FDI_TX_CTL(pipe); |
2442 | temp = I915_READ(reg); | |
77ffb597 AJ |
2443 | temp &= ~(7 << 19); |
2444 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2445 | temp &= ~FDI_LINK_TRAIN_NONE; |
2446 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2447 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2448 | |
5eddb70b CW |
2449 | reg = FDI_RX_CTL(pipe); |
2450 | temp = I915_READ(reg); | |
8db9d77b ZW |
2451 | temp &= ~FDI_LINK_TRAIN_NONE; |
2452 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2453 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2454 | ||
2455 | POSTING_READ(reg); | |
8db9d77b ZW |
2456 | udelay(150); |
2457 | ||
5b2adf89 | 2458 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2459 | if (HAS_PCH_IBX(dev)) { |
2460 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2461 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2462 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2463 | } | |
5b2adf89 | 2464 | |
5eddb70b | 2465 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2466 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2467 | temp = I915_READ(reg); |
8db9d77b ZW |
2468 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2469 | ||
2470 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2471 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2472 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2473 | break; |
2474 | } | |
8db9d77b | 2475 | } |
e1a44743 | 2476 | if (tries == 5) |
5eddb70b | 2477 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2478 | |
2479 | /* Train 2 */ | |
5eddb70b CW |
2480 | reg = FDI_TX_CTL(pipe); |
2481 | temp = I915_READ(reg); | |
8db9d77b ZW |
2482 | temp &= ~FDI_LINK_TRAIN_NONE; |
2483 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2484 | I915_WRITE(reg, temp); |
8db9d77b | 2485 | |
5eddb70b CW |
2486 | reg = FDI_RX_CTL(pipe); |
2487 | temp = I915_READ(reg); | |
8db9d77b ZW |
2488 | temp &= ~FDI_LINK_TRAIN_NONE; |
2489 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2490 | I915_WRITE(reg, temp); |
8db9d77b | 2491 | |
5eddb70b CW |
2492 | POSTING_READ(reg); |
2493 | udelay(150); | |
8db9d77b | 2494 | |
5eddb70b | 2495 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2496 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2497 | temp = I915_READ(reg); |
8db9d77b ZW |
2498 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2499 | ||
2500 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2501 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2502 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2503 | break; | |
2504 | } | |
8db9d77b | 2505 | } |
e1a44743 | 2506 | if (tries == 5) |
5eddb70b | 2507 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2508 | |
2509 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2510 | |
8db9d77b ZW |
2511 | } |
2512 | ||
0206e353 | 2513 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2514 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2515 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2516 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2517 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2518 | }; | |
2519 | ||
2520 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2521 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2522 | { | |
2523 | struct drm_device *dev = crtc->dev; | |
2524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2526 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2527 | u32 reg, temp, i; |
8db9d77b | 2528 | |
e1a44743 AJ |
2529 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2530 | for train result */ | |
5eddb70b CW |
2531 | reg = FDI_RX_IMR(pipe); |
2532 | temp = I915_READ(reg); | |
e1a44743 AJ |
2533 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2534 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2535 | I915_WRITE(reg, temp); |
2536 | ||
2537 | POSTING_READ(reg); | |
e1a44743 AJ |
2538 | udelay(150); |
2539 | ||
8db9d77b | 2540 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2541 | reg = FDI_TX_CTL(pipe); |
2542 | temp = I915_READ(reg); | |
77ffb597 AJ |
2543 | temp &= ~(7 << 19); |
2544 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2545 | temp &= ~FDI_LINK_TRAIN_NONE; |
2546 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2547 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2548 | /* SNB-B */ | |
2549 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2550 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2551 | |
5eddb70b CW |
2552 | reg = FDI_RX_CTL(pipe); |
2553 | temp = I915_READ(reg); | |
8db9d77b ZW |
2554 | if (HAS_PCH_CPT(dev)) { |
2555 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2556 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2557 | } else { | |
2558 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2559 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2560 | } | |
5eddb70b CW |
2561 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2562 | ||
2563 | POSTING_READ(reg); | |
8db9d77b ZW |
2564 | udelay(150); |
2565 | ||
291427f5 JB |
2566 | if (HAS_PCH_CPT(dev)) |
2567 | cpt_phase_pointer_enable(dev, pipe); | |
2568 | ||
0206e353 | 2569 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2570 | reg = FDI_TX_CTL(pipe); |
2571 | temp = I915_READ(reg); | |
8db9d77b ZW |
2572 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2573 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2574 | I915_WRITE(reg, temp); |
2575 | ||
2576 | POSTING_READ(reg); | |
8db9d77b ZW |
2577 | udelay(500); |
2578 | ||
5eddb70b CW |
2579 | reg = FDI_RX_IIR(pipe); |
2580 | temp = I915_READ(reg); | |
8db9d77b ZW |
2581 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2582 | ||
2583 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2584 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2585 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2586 | break; | |
2587 | } | |
2588 | } | |
2589 | if (i == 4) | |
5eddb70b | 2590 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2591 | |
2592 | /* Train 2 */ | |
5eddb70b CW |
2593 | reg = FDI_TX_CTL(pipe); |
2594 | temp = I915_READ(reg); | |
8db9d77b ZW |
2595 | temp &= ~FDI_LINK_TRAIN_NONE; |
2596 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2597 | if (IS_GEN6(dev)) { | |
2598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2599 | /* SNB-B */ | |
2600 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2601 | } | |
5eddb70b | 2602 | I915_WRITE(reg, temp); |
8db9d77b | 2603 | |
5eddb70b CW |
2604 | reg = FDI_RX_CTL(pipe); |
2605 | temp = I915_READ(reg); | |
8db9d77b ZW |
2606 | if (HAS_PCH_CPT(dev)) { |
2607 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2608 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2609 | } else { | |
2610 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2611 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2612 | } | |
5eddb70b CW |
2613 | I915_WRITE(reg, temp); |
2614 | ||
2615 | POSTING_READ(reg); | |
8db9d77b ZW |
2616 | udelay(150); |
2617 | ||
0206e353 | 2618 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2619 | reg = FDI_TX_CTL(pipe); |
2620 | temp = I915_READ(reg); | |
8db9d77b ZW |
2621 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2622 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2623 | I915_WRITE(reg, temp); |
2624 | ||
2625 | POSTING_READ(reg); | |
8db9d77b ZW |
2626 | udelay(500); |
2627 | ||
5eddb70b CW |
2628 | reg = FDI_RX_IIR(pipe); |
2629 | temp = I915_READ(reg); | |
8db9d77b ZW |
2630 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2631 | ||
2632 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2633 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2634 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2635 | break; | |
2636 | } | |
2637 | } | |
2638 | if (i == 4) | |
5eddb70b | 2639 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2640 | |
2641 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2642 | } | |
2643 | ||
357555c0 JB |
2644 | /* Manual link training for Ivy Bridge A0 parts */ |
2645 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2646 | { | |
2647 | struct drm_device *dev = crtc->dev; | |
2648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2650 | int pipe = intel_crtc->pipe; | |
2651 | u32 reg, temp, i; | |
2652 | ||
2653 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2654 | for train result */ | |
2655 | reg = FDI_RX_IMR(pipe); | |
2656 | temp = I915_READ(reg); | |
2657 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2658 | temp &= ~FDI_RX_BIT_LOCK; | |
2659 | I915_WRITE(reg, temp); | |
2660 | ||
2661 | POSTING_READ(reg); | |
2662 | udelay(150); | |
2663 | ||
2664 | /* enable CPU FDI TX and PCH FDI RX */ | |
2665 | reg = FDI_TX_CTL(pipe); | |
2666 | temp = I915_READ(reg); | |
2667 | temp &= ~(7 << 19); | |
2668 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2669 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2670 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2671 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2672 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2673 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2674 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2675 | ||
2676 | reg = FDI_RX_CTL(pipe); | |
2677 | temp = I915_READ(reg); | |
2678 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2679 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2680 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2681 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2682 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2683 | ||
2684 | POSTING_READ(reg); | |
2685 | udelay(150); | |
2686 | ||
291427f5 JB |
2687 | if (HAS_PCH_CPT(dev)) |
2688 | cpt_phase_pointer_enable(dev, pipe); | |
2689 | ||
0206e353 | 2690 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2691 | reg = FDI_TX_CTL(pipe); |
2692 | temp = I915_READ(reg); | |
2693 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2694 | temp |= snb_b_fdi_train_param[i]; | |
2695 | I915_WRITE(reg, temp); | |
2696 | ||
2697 | POSTING_READ(reg); | |
2698 | udelay(500); | |
2699 | ||
2700 | reg = FDI_RX_IIR(pipe); | |
2701 | temp = I915_READ(reg); | |
2702 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2703 | ||
2704 | if (temp & FDI_RX_BIT_LOCK || | |
2705 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2706 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2707 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2708 | break; | |
2709 | } | |
2710 | } | |
2711 | if (i == 4) | |
2712 | DRM_ERROR("FDI train 1 fail!\n"); | |
2713 | ||
2714 | /* Train 2 */ | |
2715 | reg = FDI_TX_CTL(pipe); | |
2716 | temp = I915_READ(reg); | |
2717 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2718 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2719 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2720 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2721 | I915_WRITE(reg, temp); | |
2722 | ||
2723 | reg = FDI_RX_CTL(pipe); | |
2724 | temp = I915_READ(reg); | |
2725 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2726 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2727 | I915_WRITE(reg, temp); | |
2728 | ||
2729 | POSTING_READ(reg); | |
2730 | udelay(150); | |
2731 | ||
0206e353 | 2732 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2733 | reg = FDI_TX_CTL(pipe); |
2734 | temp = I915_READ(reg); | |
2735 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2736 | temp |= snb_b_fdi_train_param[i]; | |
2737 | I915_WRITE(reg, temp); | |
2738 | ||
2739 | POSTING_READ(reg); | |
2740 | udelay(500); | |
2741 | ||
2742 | reg = FDI_RX_IIR(pipe); | |
2743 | temp = I915_READ(reg); | |
2744 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2745 | ||
2746 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2747 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2748 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2749 | break; | |
2750 | } | |
2751 | } | |
2752 | if (i == 4) | |
2753 | DRM_ERROR("FDI train 2 fail!\n"); | |
2754 | ||
2755 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2756 | } | |
2757 | ||
2758 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2759 | { |
2760 | struct drm_device *dev = crtc->dev; | |
2761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2763 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2764 | u32 reg, temp; |
79e53945 | 2765 | |
c64e311e | 2766 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2767 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2768 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2769 | |
c98e9dcf | 2770 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2771 | reg = FDI_RX_CTL(pipe); |
2772 | temp = I915_READ(reg); | |
2773 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2774 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2775 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2776 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2777 | ||
2778 | POSTING_READ(reg); | |
c98e9dcf JB |
2779 | udelay(200); |
2780 | ||
2781 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2782 | temp = I915_READ(reg); |
2783 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2784 | ||
2785 | POSTING_READ(reg); | |
c98e9dcf JB |
2786 | udelay(200); |
2787 | ||
2788 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2789 | reg = FDI_TX_CTL(pipe); |
2790 | temp = I915_READ(reg); | |
c98e9dcf | 2791 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2792 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2793 | ||
2794 | POSTING_READ(reg); | |
c98e9dcf | 2795 | udelay(100); |
6be4a607 | 2796 | } |
0e23b99d JB |
2797 | } |
2798 | ||
291427f5 JB |
2799 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2800 | { | |
2801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2802 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2803 | ||
2804 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2805 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2806 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2807 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2808 | POSTING_READ(SOUTH_CHICKEN1); | |
2809 | } | |
0fc932b8 JB |
2810 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2811 | { | |
2812 | struct drm_device *dev = crtc->dev; | |
2813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2815 | int pipe = intel_crtc->pipe; | |
2816 | u32 reg, temp; | |
2817 | ||
2818 | /* disable CPU FDI tx and PCH FDI rx */ | |
2819 | reg = FDI_TX_CTL(pipe); | |
2820 | temp = I915_READ(reg); | |
2821 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2822 | POSTING_READ(reg); | |
2823 | ||
2824 | reg = FDI_RX_CTL(pipe); | |
2825 | temp = I915_READ(reg); | |
2826 | temp &= ~(0x7 << 16); | |
2827 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2828 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2829 | ||
2830 | POSTING_READ(reg); | |
2831 | udelay(100); | |
2832 | ||
2833 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2834 | if (HAS_PCH_IBX(dev)) { |
2835 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2836 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2837 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2838 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2839 | } else if (HAS_PCH_CPT(dev)) { |
2840 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2841 | } |
0fc932b8 JB |
2842 | |
2843 | /* still set train pattern 1 */ | |
2844 | reg = FDI_TX_CTL(pipe); | |
2845 | temp = I915_READ(reg); | |
2846 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2847 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2848 | I915_WRITE(reg, temp); | |
2849 | ||
2850 | reg = FDI_RX_CTL(pipe); | |
2851 | temp = I915_READ(reg); | |
2852 | if (HAS_PCH_CPT(dev)) { | |
2853 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2854 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2855 | } else { | |
2856 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2857 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2858 | } | |
2859 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2860 | temp &= ~(0x07 << 16); | |
2861 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2862 | I915_WRITE(reg, temp); | |
2863 | ||
2864 | POSTING_READ(reg); | |
2865 | udelay(100); | |
2866 | } | |
2867 | ||
6b383a7f CW |
2868 | /* |
2869 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2870 | * to avoid hanging the ring, which we assume we are waiting on. | |
2871 | */ | |
2872 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2873 | { | |
2874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2875 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2876 | u32 tmp; |
2877 | ||
2878 | if (IS_GEN2(dev)) | |
2879 | /* Can't break the hang on i8xx */ | |
2880 | return; | |
2881 | ||
1ec14ad3 | 2882 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2883 | tmp = I915_READ_CTL(ring); |
2884 | if (tmp & RING_WAIT) | |
2885 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2886 | } |
2887 | ||
e6c3a2a6 CW |
2888 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2889 | { | |
05394f39 | 2890 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2891 | struct drm_i915_private *dev_priv; |
2892 | ||
2893 | if (crtc->fb == NULL) | |
2894 | return; | |
2895 | ||
05394f39 | 2896 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2897 | dev_priv = crtc->dev->dev_private; |
2898 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2899 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2900 | } |
2901 | ||
040484af JB |
2902 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2903 | { | |
2904 | struct drm_device *dev = crtc->dev; | |
2905 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2906 | struct intel_encoder *encoder; | |
2907 | ||
2908 | /* | |
2909 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2910 | * must be driven by its own crtc; no sharing is possible. | |
2911 | */ | |
2912 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2913 | if (encoder->base.crtc != crtc) | |
2914 | continue; | |
2915 | ||
2916 | switch (encoder->type) { | |
2917 | case INTEL_OUTPUT_EDP: | |
2918 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2919 | return false; | |
2920 | continue; | |
2921 | } | |
2922 | } | |
2923 | ||
2924 | return true; | |
2925 | } | |
2926 | ||
f67a559d JB |
2927 | /* |
2928 | * Enable PCH resources required for PCH ports: | |
2929 | * - PCH PLLs | |
2930 | * - FDI training & RX/TX | |
2931 | * - update transcoder timings | |
2932 | * - DP transcoding bits | |
2933 | * - transcoder | |
2934 | */ | |
2935 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2936 | { |
2937 | struct drm_device *dev = crtc->dev; | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2939 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2940 | int pipe = intel_crtc->pipe; | |
4b645f14 | 2941 | u32 reg, temp, transc_sel; |
2c07245f | 2942 | |
c98e9dcf | 2943 | /* For PCH output, training FDI link */ |
674cf967 | 2944 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2945 | |
92f2584a | 2946 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2947 | |
c98e9dcf | 2948 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
2949 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
2950 | TRANSC_DPLLB_SEL; | |
2951 | ||
c98e9dcf JB |
2952 | /* Be sure PCH DPLL SEL is set */ |
2953 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
2954 | if (pipe == 0) { |
2955 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 2956 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
2957 | } else if (pipe == 1) { |
2958 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 2959 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
2960 | } else if (pipe == 2) { |
2961 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 2962 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 2963 | } |
c98e9dcf | 2964 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 2965 | } |
5eddb70b | 2966 | |
d9b6cb56 JB |
2967 | /* set transcoder timing, panel must allow it */ |
2968 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2969 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2970 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2971 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2972 | |
5eddb70b CW |
2973 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2974 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2975 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2976 | |
5e84e1a4 ZW |
2977 | intel_fdi_normal_train(crtc); |
2978 | ||
c98e9dcf JB |
2979 | /* For PCH DP, enable TRANS_DP_CTL */ |
2980 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
2981 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
2982 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 2983 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
2984 | reg = TRANS_DP_CTL(pipe); |
2985 | temp = I915_READ(reg); | |
2986 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2987 | TRANS_DP_SYNC_MASK | |
2988 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2989 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2990 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 2991 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
2992 | |
2993 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2994 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2995 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2996 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2997 | |
2998 | switch (intel_trans_dp_port_sel(crtc)) { | |
2999 | case PCH_DP_B: | |
5eddb70b | 3000 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3001 | break; |
3002 | case PCH_DP_C: | |
5eddb70b | 3003 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3004 | break; |
3005 | case PCH_DP_D: | |
5eddb70b | 3006 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3007 | break; |
3008 | default: | |
3009 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3010 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3011 | break; |
32f9d658 | 3012 | } |
2c07245f | 3013 | |
5eddb70b | 3014 | I915_WRITE(reg, temp); |
6be4a607 | 3015 | } |
b52eb4dc | 3016 | |
040484af | 3017 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3018 | } |
3019 | ||
d4270e57 JB |
3020 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3021 | { | |
3022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3023 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3024 | u32 temp; | |
3025 | ||
3026 | temp = I915_READ(dslreg); | |
3027 | udelay(500); | |
3028 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3029 | /* Without this, mode sets may fail silently on FDI */ | |
3030 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3031 | udelay(250); | |
3032 | I915_WRITE(tc2reg, 0); | |
3033 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3034 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3035 | } | |
3036 | } | |
3037 | ||
f67a559d JB |
3038 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3039 | { | |
3040 | struct drm_device *dev = crtc->dev; | |
3041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3043 | int pipe = intel_crtc->pipe; | |
3044 | int plane = intel_crtc->plane; | |
3045 | u32 temp; | |
3046 | bool is_pch_port; | |
3047 | ||
3048 | if (intel_crtc->active) | |
3049 | return; | |
3050 | ||
3051 | intel_crtc->active = true; | |
3052 | intel_update_watermarks(dev); | |
3053 | ||
3054 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3055 | temp = I915_READ(PCH_LVDS); | |
3056 | if ((temp & LVDS_PORT_EN) == 0) | |
3057 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3058 | } | |
3059 | ||
3060 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3061 | ||
3062 | if (is_pch_port) | |
357555c0 | 3063 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3064 | else |
3065 | ironlake_fdi_disable(crtc); | |
3066 | ||
3067 | /* Enable panel fitting for LVDS */ | |
3068 | if (dev_priv->pch_pf_size && | |
3069 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3070 | /* Force use of hard-coded filter coefficients | |
3071 | * as some pre-programmed values are broken, | |
3072 | * e.g. x201. | |
3073 | */ | |
9db4a9c7 JB |
3074 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3075 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3076 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3077 | } |
3078 | ||
9c54c0dd JB |
3079 | /* |
3080 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3081 | * clocks enabled | |
3082 | */ | |
3083 | intel_crtc_load_lut(crtc); | |
3084 | ||
f67a559d JB |
3085 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3086 | intel_enable_plane(dev_priv, plane, pipe); | |
3087 | ||
3088 | if (is_pch_port) | |
3089 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3090 | |
d1ebd816 | 3091 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3092 | intel_update_fbc(dev); |
d1ebd816 BW |
3093 | mutex_unlock(&dev->struct_mutex); |
3094 | ||
6b383a7f | 3095 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3096 | } |
3097 | ||
3098 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3099 | { | |
3100 | struct drm_device *dev = crtc->dev; | |
3101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3103 | int pipe = intel_crtc->pipe; | |
3104 | int plane = intel_crtc->plane; | |
5eddb70b | 3105 | u32 reg, temp; |
b52eb4dc | 3106 | |
f7abfe8b CW |
3107 | if (!intel_crtc->active) |
3108 | return; | |
3109 | ||
e6c3a2a6 | 3110 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3111 | drm_vblank_off(dev, pipe); |
6b383a7f | 3112 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3113 | |
b24e7179 | 3114 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3115 | |
973d04f9 CW |
3116 | if (dev_priv->cfb_plane == plane) |
3117 | intel_disable_fbc(dev); | |
2c07245f | 3118 | |
b24e7179 | 3119 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3120 | |
6be4a607 | 3121 | /* Disable PF */ |
9db4a9c7 JB |
3122 | I915_WRITE(PF_CTL(pipe), 0); |
3123 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3124 | |
0fc932b8 | 3125 | ironlake_fdi_disable(crtc); |
2c07245f | 3126 | |
47a05eca JB |
3127 | /* This is a horrible layering violation; we should be doing this in |
3128 | * the connector/encoder ->prepare instead, but we don't always have | |
3129 | * enough information there about the config to know whether it will | |
3130 | * actually be necessary or just cause undesired flicker. | |
3131 | */ | |
3132 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3133 | |
040484af | 3134 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3135 | |
6be4a607 JB |
3136 | if (HAS_PCH_CPT(dev)) { |
3137 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3138 | reg = TRANS_DP_CTL(pipe); |
3139 | temp = I915_READ(reg); | |
3140 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3141 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3142 | I915_WRITE(reg, temp); |
6be4a607 JB |
3143 | |
3144 | /* disable DPLL_SEL */ | |
3145 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3146 | switch (pipe) { |
3147 | case 0: | |
d64311ab | 3148 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3149 | break; |
3150 | case 1: | |
6be4a607 | 3151 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3152 | break; |
3153 | case 2: | |
4b645f14 | 3154 | /* C shares PLL A or B */ |
d64311ab | 3155 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3156 | break; |
3157 | default: | |
3158 | BUG(); /* wtf */ | |
3159 | } | |
6be4a607 | 3160 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3161 | } |
e3421a18 | 3162 | |
6be4a607 | 3163 | /* disable PCH DPLL */ |
4b645f14 JB |
3164 | if (!intel_crtc->no_pll) |
3165 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 3166 | |
6be4a607 | 3167 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3168 | reg = FDI_RX_CTL(pipe); |
3169 | temp = I915_READ(reg); | |
3170 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3171 | |
6be4a607 | 3172 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3173 | reg = FDI_TX_CTL(pipe); |
3174 | temp = I915_READ(reg); | |
3175 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3176 | ||
3177 | POSTING_READ(reg); | |
6be4a607 | 3178 | udelay(100); |
8db9d77b | 3179 | |
5eddb70b CW |
3180 | reg = FDI_RX_CTL(pipe); |
3181 | temp = I915_READ(reg); | |
3182 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3183 | |
6be4a607 | 3184 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3185 | POSTING_READ(reg); |
6be4a607 | 3186 | udelay(100); |
6b383a7f | 3187 | |
f7abfe8b | 3188 | intel_crtc->active = false; |
6b383a7f | 3189 | intel_update_watermarks(dev); |
d1ebd816 BW |
3190 | |
3191 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3192 | intel_update_fbc(dev); |
3193 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3194 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3195 | } |
1b3c7a47 | 3196 | |
6be4a607 JB |
3197 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3198 | { | |
3199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3200 | int pipe = intel_crtc->pipe; | |
3201 | int plane = intel_crtc->plane; | |
8db9d77b | 3202 | |
6be4a607 JB |
3203 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3204 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3205 | */ | |
3206 | switch (mode) { | |
3207 | case DRM_MODE_DPMS_ON: | |
3208 | case DRM_MODE_DPMS_STANDBY: | |
3209 | case DRM_MODE_DPMS_SUSPEND: | |
3210 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3211 | ironlake_crtc_enable(crtc); | |
3212 | break; | |
1b3c7a47 | 3213 | |
6be4a607 JB |
3214 | case DRM_MODE_DPMS_OFF: |
3215 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3216 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3217 | break; |
3218 | } | |
3219 | } | |
3220 | ||
02e792fb DV |
3221 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3222 | { | |
02e792fb | 3223 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3224 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3225 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3226 | |
23f09ce3 | 3227 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3228 | dev_priv->mm.interruptible = false; |
3229 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3230 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3231 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3232 | } |
02e792fb | 3233 | |
5dcdbcb0 CW |
3234 | /* Let userspace switch the overlay on again. In most cases userspace |
3235 | * has to recompute where to put it anyway. | |
3236 | */ | |
02e792fb DV |
3237 | } |
3238 | ||
0b8765c6 | 3239 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3240 | { |
3241 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3242 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3244 | int pipe = intel_crtc->pipe; | |
80824003 | 3245 | int plane = intel_crtc->plane; |
79e53945 | 3246 | |
f7abfe8b CW |
3247 | if (intel_crtc->active) |
3248 | return; | |
3249 | ||
3250 | intel_crtc->active = true; | |
6b383a7f CW |
3251 | intel_update_watermarks(dev); |
3252 | ||
63d7bbe9 | 3253 | intel_enable_pll(dev_priv, pipe); |
040484af | 3254 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3255 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3256 | |
0b8765c6 | 3257 | intel_crtc_load_lut(crtc); |
bed4a673 | 3258 | intel_update_fbc(dev); |
79e53945 | 3259 | |
0b8765c6 JB |
3260 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3261 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3262 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3263 | } |
79e53945 | 3264 | |
0b8765c6 JB |
3265 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3266 | { | |
3267 | struct drm_device *dev = crtc->dev; | |
3268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3270 | int pipe = intel_crtc->pipe; | |
3271 | int plane = intel_crtc->plane; | |
b690e96c | 3272 | |
f7abfe8b CW |
3273 | if (!intel_crtc->active) |
3274 | return; | |
3275 | ||
0b8765c6 | 3276 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3277 | intel_crtc_wait_for_pending_flips(crtc); |
3278 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3279 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3280 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3281 | |
973d04f9 CW |
3282 | if (dev_priv->cfb_plane == plane) |
3283 | intel_disable_fbc(dev); | |
79e53945 | 3284 | |
b24e7179 | 3285 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3286 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3287 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3288 | |
f7abfe8b | 3289 | intel_crtc->active = false; |
6b383a7f CW |
3290 | intel_update_fbc(dev); |
3291 | intel_update_watermarks(dev); | |
3292 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3293 | } |
3294 | ||
3295 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3296 | { | |
3297 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3298 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3299 | */ | |
3300 | switch (mode) { | |
3301 | case DRM_MODE_DPMS_ON: | |
3302 | case DRM_MODE_DPMS_STANDBY: | |
3303 | case DRM_MODE_DPMS_SUSPEND: | |
3304 | i9xx_crtc_enable(crtc); | |
3305 | break; | |
3306 | case DRM_MODE_DPMS_OFF: | |
3307 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3308 | break; |
3309 | } | |
2c07245f ZW |
3310 | } |
3311 | ||
3312 | /** | |
3313 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3314 | */ |
3315 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3316 | { | |
3317 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3318 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3319 | struct drm_i915_master_private *master_priv; |
3320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3321 | int pipe = intel_crtc->pipe; | |
3322 | bool enabled; | |
3323 | ||
032d2a0d CW |
3324 | if (intel_crtc->dpms_mode == mode) |
3325 | return; | |
3326 | ||
65655d4a | 3327 | intel_crtc->dpms_mode = mode; |
debcaddc | 3328 | |
e70236a8 | 3329 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3330 | |
3331 | if (!dev->primary->master) | |
3332 | return; | |
3333 | ||
3334 | master_priv = dev->primary->master->driver_priv; | |
3335 | if (!master_priv->sarea_priv) | |
3336 | return; | |
3337 | ||
3338 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3339 | ||
3340 | switch (pipe) { | |
3341 | case 0: | |
3342 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3343 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3344 | break; | |
3345 | case 1: | |
3346 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3347 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3348 | break; | |
3349 | default: | |
9db4a9c7 | 3350 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3351 | break; |
3352 | } | |
79e53945 JB |
3353 | } |
3354 | ||
cdd59983 CW |
3355 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3356 | { | |
3357 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3358 | struct drm_device *dev = crtc->dev; | |
3359 | ||
3360 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
931872fc CW |
3361 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3362 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3363 | |
3364 | if (crtc->fb) { | |
3365 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3366 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3367 | mutex_unlock(&dev->struct_mutex); |
3368 | } | |
3369 | } | |
3370 | ||
7e7d76c3 JB |
3371 | /* Prepare for a mode set. |
3372 | * | |
3373 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3374 | * will be enabled, which disabled (in short, how the config will changes) | |
3375 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3376 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3377 | * panel fitting is in the proper state, etc. | |
3378 | */ | |
3379 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3380 | { |
7e7d76c3 | 3381 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3382 | } |
3383 | ||
7e7d76c3 | 3384 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3385 | { |
7e7d76c3 | 3386 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3387 | } |
3388 | ||
3389 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3390 | { | |
7e7d76c3 | 3391 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3392 | } |
3393 | ||
3394 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3395 | { | |
7e7d76c3 | 3396 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3397 | } |
3398 | ||
0206e353 | 3399 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3400 | { |
3401 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3402 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3403 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3404 | } | |
3405 | ||
0206e353 | 3406 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3407 | { |
3408 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 JB |
3409 | struct drm_device *dev = encoder->dev; |
3410 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3411 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
3412 | ||
79e53945 JB |
3413 | /* lvds has its own version of commit see intel_lvds_commit */ |
3414 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3415 | |
3416 | if (HAS_PCH_CPT(dev)) | |
3417 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3418 | } |
3419 | ||
ea5b213a CW |
3420 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3421 | { | |
4ef69c7a | 3422 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3423 | |
ea5b213a CW |
3424 | drm_encoder_cleanup(encoder); |
3425 | kfree(intel_encoder); | |
3426 | } | |
3427 | ||
79e53945 JB |
3428 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3429 | struct drm_display_mode *mode, | |
3430 | struct drm_display_mode *adjusted_mode) | |
3431 | { | |
2c07245f | 3432 | struct drm_device *dev = crtc->dev; |
89749350 | 3433 | |
bad720ff | 3434 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3435 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3436 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3437 | return false; | |
2c07245f | 3438 | } |
89749350 CW |
3439 | |
3440 | /* XXX some encoders set the crtcinfo, others don't. | |
3441 | * Obviously we need some form of conflict resolution here... | |
3442 | */ | |
3443 | if (adjusted_mode->crtc_htotal == 0) | |
3444 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
3445 | ||
79e53945 JB |
3446 | return true; |
3447 | } | |
3448 | ||
e70236a8 JB |
3449 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3450 | { | |
3451 | return 400000; | |
3452 | } | |
79e53945 | 3453 | |
e70236a8 | 3454 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3455 | { |
e70236a8 JB |
3456 | return 333000; |
3457 | } | |
79e53945 | 3458 | |
e70236a8 JB |
3459 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3460 | { | |
3461 | return 200000; | |
3462 | } | |
79e53945 | 3463 | |
e70236a8 JB |
3464 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3465 | { | |
3466 | u16 gcfgc = 0; | |
79e53945 | 3467 | |
e70236a8 JB |
3468 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3469 | ||
3470 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3471 | return 133000; | |
3472 | else { | |
3473 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3474 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3475 | return 333000; | |
3476 | default: | |
3477 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3478 | return 190000; | |
79e53945 | 3479 | } |
e70236a8 JB |
3480 | } |
3481 | } | |
3482 | ||
3483 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3484 | { | |
3485 | return 266000; | |
3486 | } | |
3487 | ||
3488 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3489 | { | |
3490 | u16 hpllcc = 0; | |
3491 | /* Assume that the hardware is in the high speed state. This | |
3492 | * should be the default. | |
3493 | */ | |
3494 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3495 | case GC_CLOCK_133_200: | |
3496 | case GC_CLOCK_100_200: | |
3497 | return 200000; | |
3498 | case GC_CLOCK_166_250: | |
3499 | return 250000; | |
3500 | case GC_CLOCK_100_133: | |
79e53945 | 3501 | return 133000; |
e70236a8 | 3502 | } |
79e53945 | 3503 | |
e70236a8 JB |
3504 | /* Shouldn't happen */ |
3505 | return 0; | |
3506 | } | |
79e53945 | 3507 | |
e70236a8 JB |
3508 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3509 | { | |
3510 | return 133000; | |
79e53945 JB |
3511 | } |
3512 | ||
2c07245f ZW |
3513 | struct fdi_m_n { |
3514 | u32 tu; | |
3515 | u32 gmch_m; | |
3516 | u32 gmch_n; | |
3517 | u32 link_m; | |
3518 | u32 link_n; | |
3519 | }; | |
3520 | ||
3521 | static void | |
3522 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3523 | { | |
3524 | while (*num > 0xffffff || *den > 0xffffff) { | |
3525 | *num >>= 1; | |
3526 | *den >>= 1; | |
3527 | } | |
3528 | } | |
3529 | ||
2c07245f | 3530 | static void |
f2b115e6 AJ |
3531 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3532 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3533 | { |
2c07245f ZW |
3534 | m_n->tu = 64; /* default size */ |
3535 | ||
22ed1113 CW |
3536 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3537 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3538 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3539 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3540 | ||
22ed1113 CW |
3541 | m_n->link_m = pixel_clock; |
3542 | m_n->link_n = link_clock; | |
2c07245f ZW |
3543 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3544 | } | |
3545 | ||
3546 | ||
7662c8bd SL |
3547 | struct intel_watermark_params { |
3548 | unsigned long fifo_size; | |
3549 | unsigned long max_wm; | |
3550 | unsigned long default_wm; | |
3551 | unsigned long guard_size; | |
3552 | unsigned long cacheline_size; | |
3553 | }; | |
3554 | ||
f2b115e6 | 3555 | /* Pineview has different values for various configs */ |
d210246a | 3556 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3557 | PINEVIEW_DISPLAY_FIFO, |
3558 | PINEVIEW_MAX_WM, | |
3559 | PINEVIEW_DFT_WM, | |
3560 | PINEVIEW_GUARD_WM, | |
3561 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3562 | }; |
d210246a | 3563 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3564 | PINEVIEW_DISPLAY_FIFO, |
3565 | PINEVIEW_MAX_WM, | |
3566 | PINEVIEW_DFT_HPLLOFF_WM, | |
3567 | PINEVIEW_GUARD_WM, | |
3568 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3569 | }; |
d210246a | 3570 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3571 | PINEVIEW_CURSOR_FIFO, |
3572 | PINEVIEW_CURSOR_MAX_WM, | |
3573 | PINEVIEW_CURSOR_DFT_WM, | |
3574 | PINEVIEW_CURSOR_GUARD_WM, | |
3575 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3576 | }; |
d210246a | 3577 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3578 | PINEVIEW_CURSOR_FIFO, |
3579 | PINEVIEW_CURSOR_MAX_WM, | |
3580 | PINEVIEW_CURSOR_DFT_WM, | |
3581 | PINEVIEW_CURSOR_GUARD_WM, | |
3582 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3583 | }; |
d210246a | 3584 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3585 | G4X_FIFO_SIZE, |
3586 | G4X_MAX_WM, | |
3587 | G4X_MAX_WM, | |
3588 | 2, | |
3589 | G4X_FIFO_LINE_SIZE, | |
3590 | }; | |
d210246a | 3591 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3592 | I965_CURSOR_FIFO, |
3593 | I965_CURSOR_MAX_WM, | |
3594 | I965_CURSOR_DFT_WM, | |
3595 | 2, | |
3596 | G4X_FIFO_LINE_SIZE, | |
3597 | }; | |
d210246a | 3598 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3599 | I965_CURSOR_FIFO, |
3600 | I965_CURSOR_MAX_WM, | |
3601 | I965_CURSOR_DFT_WM, | |
3602 | 2, | |
3603 | I915_FIFO_LINE_SIZE, | |
3604 | }; | |
d210246a | 3605 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3606 | I945_FIFO_SIZE, |
7662c8bd SL |
3607 | I915_MAX_WM, |
3608 | 1, | |
dff33cfc JB |
3609 | 2, |
3610 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3611 | }; |
d210246a | 3612 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3613 | I915_FIFO_SIZE, |
7662c8bd SL |
3614 | I915_MAX_WM, |
3615 | 1, | |
dff33cfc | 3616 | 2, |
7662c8bd SL |
3617 | I915_FIFO_LINE_SIZE |
3618 | }; | |
d210246a | 3619 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3620 | I855GM_FIFO_SIZE, |
3621 | I915_MAX_WM, | |
3622 | 1, | |
dff33cfc | 3623 | 2, |
7662c8bd SL |
3624 | I830_FIFO_LINE_SIZE |
3625 | }; | |
d210246a | 3626 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3627 | I830_FIFO_SIZE, |
3628 | I915_MAX_WM, | |
3629 | 1, | |
dff33cfc | 3630 | 2, |
7662c8bd SL |
3631 | I830_FIFO_LINE_SIZE |
3632 | }; | |
3633 | ||
d210246a | 3634 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3635 | ILK_DISPLAY_FIFO, |
3636 | ILK_DISPLAY_MAXWM, | |
3637 | ILK_DISPLAY_DFTWM, | |
3638 | 2, | |
3639 | ILK_FIFO_LINE_SIZE | |
3640 | }; | |
d210246a | 3641 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3642 | ILK_CURSOR_FIFO, |
3643 | ILK_CURSOR_MAXWM, | |
3644 | ILK_CURSOR_DFTWM, | |
3645 | 2, | |
3646 | ILK_FIFO_LINE_SIZE | |
3647 | }; | |
d210246a | 3648 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3649 | ILK_DISPLAY_SR_FIFO, |
3650 | ILK_DISPLAY_MAX_SRWM, | |
3651 | ILK_DISPLAY_DFT_SRWM, | |
3652 | 2, | |
3653 | ILK_FIFO_LINE_SIZE | |
3654 | }; | |
d210246a | 3655 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3656 | ILK_CURSOR_SR_FIFO, |
3657 | ILK_CURSOR_MAX_SRWM, | |
3658 | ILK_CURSOR_DFT_SRWM, | |
3659 | 2, | |
3660 | ILK_FIFO_LINE_SIZE | |
3661 | }; | |
3662 | ||
d210246a | 3663 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3664 | SNB_DISPLAY_FIFO, |
3665 | SNB_DISPLAY_MAXWM, | |
3666 | SNB_DISPLAY_DFTWM, | |
3667 | 2, | |
3668 | SNB_FIFO_LINE_SIZE | |
3669 | }; | |
d210246a | 3670 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3671 | SNB_CURSOR_FIFO, |
3672 | SNB_CURSOR_MAXWM, | |
3673 | SNB_CURSOR_DFTWM, | |
3674 | 2, | |
3675 | SNB_FIFO_LINE_SIZE | |
3676 | }; | |
d210246a | 3677 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3678 | SNB_DISPLAY_SR_FIFO, |
3679 | SNB_DISPLAY_MAX_SRWM, | |
3680 | SNB_DISPLAY_DFT_SRWM, | |
3681 | 2, | |
3682 | SNB_FIFO_LINE_SIZE | |
3683 | }; | |
d210246a | 3684 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3685 | SNB_CURSOR_SR_FIFO, |
3686 | SNB_CURSOR_MAX_SRWM, | |
3687 | SNB_CURSOR_DFT_SRWM, | |
3688 | 2, | |
3689 | SNB_FIFO_LINE_SIZE | |
3690 | }; | |
3691 | ||
3692 | ||
dff33cfc JB |
3693 | /** |
3694 | * intel_calculate_wm - calculate watermark level | |
3695 | * @clock_in_khz: pixel clock | |
3696 | * @wm: chip FIFO params | |
3697 | * @pixel_size: display pixel size | |
3698 | * @latency_ns: memory latency for the platform | |
3699 | * | |
3700 | * Calculate the watermark level (the level at which the display plane will | |
3701 | * start fetching from memory again). Each chip has a different display | |
3702 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3703 | * in the correct intel_watermark_params structure. | |
3704 | * | |
3705 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3706 | * on the pixel size. When it reaches the watermark level, it'll start | |
3707 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3708 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3709 | * will occur, and a display engine hang could result. | |
3710 | */ | |
7662c8bd | 3711 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3712 | const struct intel_watermark_params *wm, |
3713 | int fifo_size, | |
7662c8bd SL |
3714 | int pixel_size, |
3715 | unsigned long latency_ns) | |
3716 | { | |
390c4dd4 | 3717 | long entries_required, wm_size; |
dff33cfc | 3718 | |
d660467c JB |
3719 | /* |
3720 | * Note: we need to make sure we don't overflow for various clock & | |
3721 | * latency values. | |
3722 | * clocks go from a few thousand to several hundred thousand. | |
3723 | * latency is usually a few thousand | |
3724 | */ | |
3725 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3726 | 1000; | |
8de9b311 | 3727 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3728 | |
bbb0aef5 | 3729 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3730 | |
d210246a | 3731 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3732 | |
bbb0aef5 | 3733 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3734 | |
390c4dd4 JB |
3735 | /* Don't promote wm_size to unsigned... */ |
3736 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3737 | wm_size = wm->max_wm; |
c3add4b6 | 3738 | if (wm_size <= 0) |
7662c8bd SL |
3739 | wm_size = wm->default_wm; |
3740 | return wm_size; | |
3741 | } | |
3742 | ||
3743 | struct cxsr_latency { | |
3744 | int is_desktop; | |
95534263 | 3745 | int is_ddr3; |
7662c8bd SL |
3746 | unsigned long fsb_freq; |
3747 | unsigned long mem_freq; | |
3748 | unsigned long display_sr; | |
3749 | unsigned long display_hpll_disable; | |
3750 | unsigned long cursor_sr; | |
3751 | unsigned long cursor_hpll_disable; | |
3752 | }; | |
3753 | ||
403c89ff | 3754 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3755 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3756 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3757 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3758 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3759 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3760 | ||
3761 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3762 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3763 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3764 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3765 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3766 | ||
3767 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3768 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3769 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3770 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3771 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3772 | ||
3773 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3774 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3775 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3776 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3777 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3778 | ||
3779 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3780 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3781 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3782 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3783 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3784 | ||
3785 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3786 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3787 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3788 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3789 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3790 | }; |
3791 | ||
403c89ff CW |
3792 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3793 | int is_ddr3, | |
3794 | int fsb, | |
3795 | int mem) | |
7662c8bd | 3796 | { |
403c89ff | 3797 | const struct cxsr_latency *latency; |
7662c8bd | 3798 | int i; |
7662c8bd SL |
3799 | |
3800 | if (fsb == 0 || mem == 0) | |
3801 | return NULL; | |
3802 | ||
3803 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3804 | latency = &cxsr_latency_table[i]; | |
3805 | if (is_desktop == latency->is_desktop && | |
95534263 | 3806 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3807 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3808 | return latency; | |
7662c8bd | 3809 | } |
decbbcda | 3810 | |
28c97730 | 3811 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3812 | |
3813 | return NULL; | |
7662c8bd SL |
3814 | } |
3815 | ||
f2b115e6 | 3816 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3817 | { |
3818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3819 | |
3820 | /* deactivate cxsr */ | |
3e33d94d | 3821 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3822 | } |
3823 | ||
bcc24fb4 JB |
3824 | /* |
3825 | * Latency for FIFO fetches is dependent on several factors: | |
3826 | * - memory configuration (speed, channels) | |
3827 | * - chipset | |
3828 | * - current MCH state | |
3829 | * It can be fairly high in some situations, so here we assume a fairly | |
3830 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3831 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3832 | * and power consumption (set it too low to save power and we might see | |
3833 | * FIFO underruns and display "flicker"). | |
3834 | * | |
3835 | * A value of 5us seems to be a good balance; safe for very low end | |
3836 | * platforms but not overly aggressive on lower latency configs. | |
3837 | */ | |
69e302a9 | 3838 | static const int latency_ns = 5000; |
7662c8bd | 3839 | |
e70236a8 | 3840 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3841 | { |
3842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3843 | uint32_t dsparb = I915_READ(DSPARB); | |
3844 | int size; | |
3845 | ||
8de9b311 CW |
3846 | size = dsparb & 0x7f; |
3847 | if (plane) | |
3848 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3849 | |
28c97730 | 3850 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3851 | plane ? "B" : "A", size); |
dff33cfc JB |
3852 | |
3853 | return size; | |
3854 | } | |
7662c8bd | 3855 | |
e70236a8 JB |
3856 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3857 | { | |
3858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3859 | uint32_t dsparb = I915_READ(DSPARB); | |
3860 | int size; | |
3861 | ||
8de9b311 CW |
3862 | size = dsparb & 0x1ff; |
3863 | if (plane) | |
3864 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3865 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3866 | |
28c97730 | 3867 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3868 | plane ? "B" : "A", size); |
dff33cfc JB |
3869 | |
3870 | return size; | |
3871 | } | |
7662c8bd | 3872 | |
e70236a8 JB |
3873 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3874 | { | |
3875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3876 | uint32_t dsparb = I915_READ(DSPARB); | |
3877 | int size; | |
3878 | ||
3879 | size = dsparb & 0x7f; | |
3880 | size >>= 2; /* Convert to cachelines */ | |
3881 | ||
28c97730 | 3882 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3883 | plane ? "B" : "A", |
3884 | size); | |
e70236a8 JB |
3885 | |
3886 | return size; | |
3887 | } | |
3888 | ||
3889 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3890 | { | |
3891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3892 | uint32_t dsparb = I915_READ(DSPARB); | |
3893 | int size; | |
3894 | ||
3895 | size = dsparb & 0x7f; | |
3896 | size >>= 1; /* Convert to cachelines */ | |
3897 | ||
28c97730 | 3898 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3899 | plane ? "B" : "A", size); |
e70236a8 JB |
3900 | |
3901 | return size; | |
3902 | } | |
3903 | ||
d210246a CW |
3904 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3905 | { | |
3906 | struct drm_crtc *crtc, *enabled = NULL; | |
3907 | ||
3908 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3909 | if (crtc->enabled && crtc->fb) { | |
3910 | if (enabled) | |
3911 | return NULL; | |
3912 | enabled = crtc; | |
3913 | } | |
3914 | } | |
3915 | ||
3916 | return enabled; | |
3917 | } | |
3918 | ||
3919 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3920 | { |
3921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3922 | struct drm_crtc *crtc; |
403c89ff | 3923 | const struct cxsr_latency *latency; |
d4294342 ZY |
3924 | u32 reg; |
3925 | unsigned long wm; | |
d4294342 | 3926 | |
403c89ff | 3927 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3928 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3929 | if (!latency) { |
3930 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3931 | pineview_disable_cxsr(dev); | |
3932 | return; | |
3933 | } | |
3934 | ||
d210246a CW |
3935 | crtc = single_enabled_crtc(dev); |
3936 | if (crtc) { | |
3937 | int clock = crtc->mode.clock; | |
3938 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3939 | |
3940 | /* Display SR */ | |
d210246a CW |
3941 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3942 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3943 | pixel_size, latency->display_sr); |
3944 | reg = I915_READ(DSPFW1); | |
3945 | reg &= ~DSPFW_SR_MASK; | |
3946 | reg |= wm << DSPFW_SR_SHIFT; | |
3947 | I915_WRITE(DSPFW1, reg); | |
3948 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3949 | ||
3950 | /* cursor SR */ | |
d210246a CW |
3951 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3952 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3953 | pixel_size, latency->cursor_sr); |
3954 | reg = I915_READ(DSPFW3); | |
3955 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3956 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3957 | I915_WRITE(DSPFW3, reg); | |
3958 | ||
3959 | /* Display HPLL off SR */ | |
d210246a CW |
3960 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
3961 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3962 | pixel_size, latency->display_hpll_disable); |
3963 | reg = I915_READ(DSPFW3); | |
3964 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3965 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3966 | I915_WRITE(DSPFW3, reg); | |
3967 | ||
3968 | /* cursor HPLL off SR */ | |
d210246a CW |
3969 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
3970 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3971 | pixel_size, latency->cursor_hpll_disable); |
3972 | reg = I915_READ(DSPFW3); | |
3973 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3974 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3975 | I915_WRITE(DSPFW3, reg); | |
3976 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3977 | ||
3978 | /* activate cxsr */ | |
3e33d94d CW |
3979 | I915_WRITE(DSPFW3, |
3980 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3981 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3982 | } else { | |
3983 | pineview_disable_cxsr(dev); | |
3984 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3985 | } | |
3986 | } | |
3987 | ||
417ae147 CW |
3988 | static bool g4x_compute_wm0(struct drm_device *dev, |
3989 | int plane, | |
3990 | const struct intel_watermark_params *display, | |
3991 | int display_latency_ns, | |
3992 | const struct intel_watermark_params *cursor, | |
3993 | int cursor_latency_ns, | |
3994 | int *plane_wm, | |
3995 | int *cursor_wm) | |
3996 | { | |
3997 | struct drm_crtc *crtc; | |
3998 | int htotal, hdisplay, clock, pixel_size; | |
3999 | int line_time_us, line_count; | |
4000 | int entries, tlb_miss; | |
4001 | ||
4002 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
4003 | if (crtc->fb == NULL || !crtc->enabled) { |
4004 | *cursor_wm = cursor->guard_size; | |
4005 | *plane_wm = display->guard_size; | |
417ae147 | 4006 | return false; |
5c72d064 | 4007 | } |
417ae147 CW |
4008 | |
4009 | htotal = crtc->mode.htotal; | |
4010 | hdisplay = crtc->mode.hdisplay; | |
4011 | clock = crtc->mode.clock; | |
4012 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4013 | ||
4014 | /* Use the small buffer method to calculate plane watermark */ | |
4015 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4016 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
4017 | if (tlb_miss > 0) | |
4018 | entries += tlb_miss; | |
4019 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4020 | *plane_wm = entries + display->guard_size; | |
4021 | if (*plane_wm > (int)display->max_wm) | |
4022 | *plane_wm = display->max_wm; | |
4023 | ||
4024 | /* Use the large buffer method to calculate cursor watermark */ | |
4025 | line_time_us = ((htotal * 1000) / clock); | |
4026 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
4027 | entries = line_count * 64 * pixel_size; | |
4028 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
4029 | if (tlb_miss > 0) | |
4030 | entries += tlb_miss; | |
4031 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4032 | *cursor_wm = entries + cursor->guard_size; | |
4033 | if (*cursor_wm > (int)cursor->max_wm) | |
4034 | *cursor_wm = (int)cursor->max_wm; | |
4035 | ||
4036 | return true; | |
4037 | } | |
4038 | ||
4039 | /* | |
4040 | * Check the wm result. | |
4041 | * | |
4042 | * If any calculated watermark values is larger than the maximum value that | |
4043 | * can be programmed into the associated watermark register, that watermark | |
4044 | * must be disabled. | |
4045 | */ | |
4046 | static bool g4x_check_srwm(struct drm_device *dev, | |
4047 | int display_wm, int cursor_wm, | |
4048 | const struct intel_watermark_params *display, | |
4049 | const struct intel_watermark_params *cursor) | |
652c393a | 4050 | { |
417ae147 CW |
4051 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
4052 | display_wm, cursor_wm); | |
652c393a | 4053 | |
417ae147 | 4054 | if (display_wm > display->max_wm) { |
bbb0aef5 | 4055 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4056 | display_wm, display->max_wm); |
4057 | return false; | |
4058 | } | |
0e442c60 | 4059 | |
417ae147 | 4060 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 4061 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4062 | cursor_wm, cursor->max_wm); |
4063 | return false; | |
4064 | } | |
0e442c60 | 4065 | |
417ae147 CW |
4066 | if (!(display_wm || cursor_wm)) { |
4067 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
4068 | return false; | |
4069 | } | |
0e442c60 | 4070 | |
417ae147 CW |
4071 | return true; |
4072 | } | |
0e442c60 | 4073 | |
417ae147 | 4074 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
4075 | int plane, |
4076 | int latency_ns, | |
417ae147 CW |
4077 | const struct intel_watermark_params *display, |
4078 | const struct intel_watermark_params *cursor, | |
4079 | int *display_wm, int *cursor_wm) | |
4080 | { | |
d210246a CW |
4081 | struct drm_crtc *crtc; |
4082 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
4083 | unsigned long line_time_us; |
4084 | int line_count, line_size; | |
4085 | int small, large; | |
4086 | int entries; | |
0e442c60 | 4087 | |
417ae147 CW |
4088 | if (!latency_ns) { |
4089 | *display_wm = *cursor_wm = 0; | |
4090 | return false; | |
4091 | } | |
0e442c60 | 4092 | |
d210246a CW |
4093 | crtc = intel_get_crtc_for_plane(dev, plane); |
4094 | hdisplay = crtc->mode.hdisplay; | |
4095 | htotal = crtc->mode.htotal; | |
4096 | clock = crtc->mode.clock; | |
4097 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4098 | ||
417ae147 CW |
4099 | line_time_us = (htotal * 1000) / clock; |
4100 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4101 | line_size = hdisplay * pixel_size; | |
0e442c60 | 4102 | |
417ae147 CW |
4103 | /* Use the minimum of the small and large buffer method for primary */ |
4104 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4105 | large = line_count * line_size; | |
0e442c60 | 4106 | |
417ae147 CW |
4107 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4108 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4109 | |
417ae147 CW |
4110 | /* calculate the self-refresh watermark for display cursor */ |
4111 | entries = line_count * pixel_size * 64; | |
4112 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4113 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4114 | |
417ae147 CW |
4115 | return g4x_check_srwm(dev, |
4116 | *display_wm, *cursor_wm, | |
4117 | display, cursor); | |
4118 | } | |
4fe5e611 | 4119 | |
7ccb4a53 | 4120 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
4121 | |
4122 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
4123 | { |
4124 | static const int sr_latency_ns = 12000; | |
4125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4126 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4127 | int plane_sr, cursor_sr; |
4128 | unsigned int enabled = 0; | |
417ae147 CW |
4129 | |
4130 | if (g4x_compute_wm0(dev, 0, | |
4131 | &g4x_wm_info, latency_ns, | |
4132 | &g4x_cursor_wm_info, latency_ns, | |
4133 | &planea_wm, &cursora_wm)) | |
d210246a | 4134 | enabled |= 1; |
417ae147 CW |
4135 | |
4136 | if (g4x_compute_wm0(dev, 1, | |
4137 | &g4x_wm_info, latency_ns, | |
4138 | &g4x_cursor_wm_info, latency_ns, | |
4139 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4140 | enabled |= 2; |
417ae147 CW |
4141 | |
4142 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4143 | if (single_plane_enabled(enabled) && |
4144 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4145 | sr_latency_ns, | |
417ae147 CW |
4146 | &g4x_wm_info, |
4147 | &g4x_cursor_wm_info, | |
4148 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4149 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4150 | else |
4151 | I915_WRITE(FW_BLC_SELF, | |
4152 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4153 | |
308977ac CW |
4154 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4155 | planea_wm, cursora_wm, | |
4156 | planeb_wm, cursorb_wm, | |
4157 | plane_sr, cursor_sr); | |
0e442c60 | 4158 | |
417ae147 CW |
4159 | I915_WRITE(DSPFW1, |
4160 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4161 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4162 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4163 | planea_wm); | |
4164 | I915_WRITE(DSPFW2, | |
4165 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4166 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4167 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4168 | I915_WRITE(DSPFW3, |
4169 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4170 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4171 | } |
4172 | ||
d210246a | 4173 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4174 | { |
4175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4176 | struct drm_crtc *crtc; |
4177 | int srwm = 1; | |
4fe5e611 | 4178 | int cursor_sr = 16; |
1dc7546d JB |
4179 | |
4180 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4181 | crtc = single_enabled_crtc(dev); |
4182 | if (crtc) { | |
1dc7546d | 4183 | /* self-refresh has much higher latency */ |
69e302a9 | 4184 | static const int sr_latency_ns = 12000; |
d210246a CW |
4185 | int clock = crtc->mode.clock; |
4186 | int htotal = crtc->mode.htotal; | |
4187 | int hdisplay = crtc->mode.hdisplay; | |
4188 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4189 | unsigned long line_time_us; | |
4190 | int entries; | |
1dc7546d | 4191 | |
d210246a | 4192 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4193 | |
4194 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4195 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4196 | pixel_size * hdisplay; | |
4197 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4198 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4199 | if (srwm < 0) |
4200 | srwm = 1; | |
1b07e04e | 4201 | srwm &= 0x1ff; |
308977ac CW |
4202 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4203 | entries, srwm); | |
4fe5e611 | 4204 | |
d210246a | 4205 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4206 | pixel_size * 64; |
d210246a | 4207 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4208 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4209 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4210 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4211 | |
4212 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4213 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4214 | ||
4215 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4216 | "cursor %d\n", srwm, cursor_sr); | |
4217 | ||
a6c45cf0 | 4218 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4219 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4220 | } else { |
4221 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4222 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4223 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4224 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4225 | } |
7662c8bd | 4226 | |
1dc7546d JB |
4227 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4228 | srwm); | |
7662c8bd SL |
4229 | |
4230 | /* 965 has limitations... */ | |
417ae147 CW |
4231 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4232 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4233 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4234 | /* update cursor SR watermark */ |
4235 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4236 | } |
4237 | ||
d210246a | 4238 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4239 | { |
4240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4241 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4242 | uint32_t fwater_lo; |
4243 | uint32_t fwater_hi; | |
d210246a CW |
4244 | int cwm, srwm = 1; |
4245 | int fifo_size; | |
dff33cfc | 4246 | int planea_wm, planeb_wm; |
d210246a | 4247 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4248 | |
72557b4f | 4249 | if (IS_I945GM(dev)) |
d210246a | 4250 | wm_info = &i945_wm_info; |
a6c45cf0 | 4251 | else if (!IS_GEN2(dev)) |
d210246a | 4252 | wm_info = &i915_wm_info; |
7662c8bd | 4253 | else |
d210246a CW |
4254 | wm_info = &i855_wm_info; |
4255 | ||
4256 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4257 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4258 | if (crtc->enabled && crtc->fb) { | |
4259 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4260 | wm_info, fifo_size, | |
4261 | crtc->fb->bits_per_pixel / 8, | |
4262 | latency_ns); | |
4263 | enabled = crtc; | |
4264 | } else | |
4265 | planea_wm = fifo_size - wm_info->guard_size; | |
4266 | ||
4267 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4268 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4269 | if (crtc->enabled && crtc->fb) { | |
4270 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4271 | wm_info, fifo_size, | |
4272 | crtc->fb->bits_per_pixel / 8, | |
4273 | latency_ns); | |
4274 | if (enabled == NULL) | |
4275 | enabled = crtc; | |
4276 | else | |
4277 | enabled = NULL; | |
4278 | } else | |
4279 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4280 | |
28c97730 | 4281 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4282 | |
4283 | /* | |
4284 | * Overlay gets an aggressive default since video jitter is bad. | |
4285 | */ | |
4286 | cwm = 2; | |
4287 | ||
18b2190c AL |
4288 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4289 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4290 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4291 | else if (IS_I915GM(dev)) | |
4292 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4293 | ||
dff33cfc | 4294 | /* Calc sr entries for one plane configs */ |
d210246a | 4295 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4296 | /* self-refresh has much higher latency */ |
69e302a9 | 4297 | static const int sr_latency_ns = 6000; |
d210246a CW |
4298 | int clock = enabled->mode.clock; |
4299 | int htotal = enabled->mode.htotal; | |
4300 | int hdisplay = enabled->mode.hdisplay; | |
4301 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4302 | unsigned long line_time_us; | |
4303 | int entries; | |
dff33cfc | 4304 | |
d210246a | 4305 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4306 | |
4307 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4308 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4309 | pixel_size * hdisplay; | |
4310 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4311 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4312 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4313 | if (srwm < 0) |
4314 | srwm = 1; | |
ee980b80 LP |
4315 | |
4316 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4317 | I915_WRITE(FW_BLC_SELF, |
4318 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4319 | else if (IS_I915GM(dev)) | |
ee980b80 | 4320 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4321 | } |
4322 | ||
28c97730 | 4323 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4324 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4325 | |
dff33cfc JB |
4326 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4327 | fwater_hi = (cwm & 0x1f); | |
4328 | ||
4329 | /* Set request length to 8 cachelines per fetch */ | |
4330 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4331 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4332 | |
4333 | I915_WRITE(FW_BLC, fwater_lo); | |
4334 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4335 | |
d210246a CW |
4336 | if (HAS_FW_BLC(dev)) { |
4337 | if (enabled) { | |
4338 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4339 | I915_WRITE(FW_BLC_SELF, | |
4340 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4341 | else if (IS_I915GM(dev)) | |
4342 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4343 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4344 | } else | |
4345 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4346 | } | |
7662c8bd SL |
4347 | } |
4348 | ||
d210246a | 4349 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4350 | { |
4351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4352 | struct drm_crtc *crtc; |
4353 | uint32_t fwater_lo; | |
dff33cfc | 4354 | int planea_wm; |
7662c8bd | 4355 | |
d210246a CW |
4356 | crtc = single_enabled_crtc(dev); |
4357 | if (crtc == NULL) | |
4358 | return; | |
7662c8bd | 4359 | |
d210246a CW |
4360 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4361 | dev_priv->display.get_fifo_size(dev, 0), | |
4362 | crtc->fb->bits_per_pixel / 8, | |
4363 | latency_ns); | |
4364 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4365 | fwater_lo |= (3<<8) | planea_wm; |
4366 | ||
28c97730 | 4367 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4368 | |
4369 | I915_WRITE(FW_BLC, fwater_lo); | |
4370 | } | |
4371 | ||
7f8a8569 | 4372 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4373 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4374 | |
1398261a YL |
4375 | /* |
4376 | * Check the wm result. | |
4377 | * | |
4378 | * If any calculated watermark values is larger than the maximum value that | |
4379 | * can be programmed into the associated watermark register, that watermark | |
4380 | * must be disabled. | |
1398261a | 4381 | */ |
b79d4990 JB |
4382 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4383 | int fbc_wm, int display_wm, int cursor_wm, | |
4384 | const struct intel_watermark_params *display, | |
4385 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4386 | { |
4387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4388 | ||
4389 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4390 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4391 | ||
4392 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4393 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4394 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4395 | |
4396 | /* fbc has it's own way to disable FBC WM */ | |
4397 | I915_WRITE(DISP_ARB_CTL, | |
4398 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4399 | return false; | |
4400 | } | |
4401 | ||
b79d4990 | 4402 | if (display_wm > display->max_wm) { |
1398261a | 4403 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4404 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4405 | return false; |
4406 | } | |
4407 | ||
b79d4990 | 4408 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4409 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4410 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4411 | return false; |
4412 | } | |
4413 | ||
4414 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4415 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4416 | return false; | |
4417 | } | |
4418 | ||
4419 | return true; | |
4420 | } | |
4421 | ||
4422 | /* | |
4423 | * Compute watermark values of WM[1-3], | |
4424 | */ | |
d210246a CW |
4425 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4426 | int latency_ns, | |
b79d4990 JB |
4427 | const struct intel_watermark_params *display, |
4428 | const struct intel_watermark_params *cursor, | |
4429 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4430 | { |
d210246a | 4431 | struct drm_crtc *crtc; |
1398261a | 4432 | unsigned long line_time_us; |
d210246a | 4433 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4434 | int line_count, line_size; |
1398261a YL |
4435 | int small, large; |
4436 | int entries; | |
1398261a YL |
4437 | |
4438 | if (!latency_ns) { | |
4439 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4440 | return false; | |
4441 | } | |
4442 | ||
d210246a CW |
4443 | crtc = intel_get_crtc_for_plane(dev, plane); |
4444 | hdisplay = crtc->mode.hdisplay; | |
4445 | htotal = crtc->mode.htotal; | |
4446 | clock = crtc->mode.clock; | |
4447 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4448 | ||
1398261a YL |
4449 | line_time_us = (htotal * 1000) / clock; |
4450 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4451 | line_size = hdisplay * pixel_size; | |
4452 | ||
4453 | /* Use the minimum of the small and large buffer method for primary */ | |
4454 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4455 | large = line_count * line_size; | |
4456 | ||
b79d4990 JB |
4457 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4458 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4459 | |
4460 | /* | |
b79d4990 | 4461 | * Spec says: |
1398261a YL |
4462 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4463 | */ | |
4464 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4465 | ||
4466 | /* calculate the self-refresh watermark for display cursor */ | |
4467 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4468 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4469 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4470 | |
b79d4990 JB |
4471 | return ironlake_check_srwm(dev, level, |
4472 | *fbc_wm, *display_wm, *cursor_wm, | |
4473 | display, cursor); | |
4474 | } | |
4475 | ||
d210246a | 4476 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4477 | { |
4478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4479 | int fbc_wm, plane_wm, cursor_wm; |
4480 | unsigned int enabled; | |
b79d4990 JB |
4481 | |
4482 | enabled = 0; | |
9f405100 CW |
4483 | if (g4x_compute_wm0(dev, 0, |
4484 | &ironlake_display_wm_info, | |
4485 | ILK_LP0_PLANE_LATENCY, | |
4486 | &ironlake_cursor_wm_info, | |
4487 | ILK_LP0_CURSOR_LATENCY, | |
4488 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4489 | I915_WRITE(WM0_PIPEA_ILK, |
4490 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4491 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4492 | " plane %d, " "cursor: %d\n", | |
4493 | plane_wm, cursor_wm); | |
d210246a | 4494 | enabled |= 1; |
b79d4990 JB |
4495 | } |
4496 | ||
9f405100 CW |
4497 | if (g4x_compute_wm0(dev, 1, |
4498 | &ironlake_display_wm_info, | |
4499 | ILK_LP0_PLANE_LATENCY, | |
4500 | &ironlake_cursor_wm_info, | |
4501 | ILK_LP0_CURSOR_LATENCY, | |
4502 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4503 | I915_WRITE(WM0_PIPEB_ILK, |
4504 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4505 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4506 | " plane %d, cursor: %d\n", | |
4507 | plane_wm, cursor_wm); | |
d210246a | 4508 | enabled |= 2; |
b79d4990 JB |
4509 | } |
4510 | ||
4511 | /* | |
4512 | * Calculate and update the self-refresh watermark only when one | |
4513 | * display plane is used. | |
4514 | */ | |
4515 | I915_WRITE(WM3_LP_ILK, 0); | |
4516 | I915_WRITE(WM2_LP_ILK, 0); | |
4517 | I915_WRITE(WM1_LP_ILK, 0); | |
4518 | ||
d210246a | 4519 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4520 | return; |
d210246a | 4521 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4522 | |
4523 | /* WM1 */ | |
d210246a CW |
4524 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4525 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4526 | &ironlake_display_srwm_info, |
4527 | &ironlake_cursor_srwm_info, | |
4528 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4529 | return; | |
4530 | ||
4531 | I915_WRITE(WM1_LP_ILK, | |
4532 | WM1_LP_SR_EN | | |
4533 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4534 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4535 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4536 | cursor_wm); | |
4537 | ||
4538 | /* WM2 */ | |
d210246a CW |
4539 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4540 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4541 | &ironlake_display_srwm_info, |
4542 | &ironlake_cursor_srwm_info, | |
4543 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4544 | return; | |
4545 | ||
4546 | I915_WRITE(WM2_LP_ILK, | |
4547 | WM2_LP_EN | | |
4548 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4549 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4550 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4551 | cursor_wm); | |
4552 | ||
4553 | /* | |
4554 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4555 | * data for that power state | |
4556 | */ | |
1398261a YL |
4557 | } |
4558 | ||
b840d907 | 4559 | void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4560 | { |
4561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4562 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
47842649 | 4563 | u32 val; |
d210246a CW |
4564 | int fbc_wm, plane_wm, cursor_wm; |
4565 | unsigned int enabled; | |
1398261a YL |
4566 | |
4567 | enabled = 0; | |
9f405100 CW |
4568 | if (g4x_compute_wm0(dev, 0, |
4569 | &sandybridge_display_wm_info, latency, | |
4570 | &sandybridge_cursor_wm_info, latency, | |
4571 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4572 | val = I915_READ(WM0_PIPEA_ILK); |
4573 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4574 | I915_WRITE(WM0_PIPEA_ILK, val | | |
4575 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4576 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
4577 | " plane %d, " "cursor: %d\n", | |
4578 | plane_wm, cursor_wm); | |
d210246a | 4579 | enabled |= 1; |
1398261a YL |
4580 | } |
4581 | ||
9f405100 CW |
4582 | if (g4x_compute_wm0(dev, 1, |
4583 | &sandybridge_display_wm_info, latency, | |
4584 | &sandybridge_cursor_wm_info, latency, | |
4585 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4586 | val = I915_READ(WM0_PIPEB_ILK); |
4587 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4588 | I915_WRITE(WM0_PIPEB_ILK, val | | |
4589 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4590 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
4591 | " plane %d, cursor: %d\n", | |
4592 | plane_wm, cursor_wm); | |
d210246a | 4593 | enabled |= 2; |
1398261a YL |
4594 | } |
4595 | ||
d6c892df JB |
4596 | /* IVB has 3 pipes */ |
4597 | if (IS_IVYBRIDGE(dev) && | |
4598 | g4x_compute_wm0(dev, 2, | |
4599 | &sandybridge_display_wm_info, latency, | |
4600 | &sandybridge_cursor_wm_info, latency, | |
4601 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4602 | val = I915_READ(WM0_PIPEC_IVB); |
4603 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4604 | I915_WRITE(WM0_PIPEC_IVB, val | | |
4605 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
d6c892df JB |
4606 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
4607 | " plane %d, cursor: %d\n", | |
4608 | plane_wm, cursor_wm); | |
4609 | enabled |= 3; | |
4610 | } | |
4611 | ||
1398261a YL |
4612 | /* |
4613 | * Calculate and update the self-refresh watermark only when one | |
4614 | * display plane is used. | |
4615 | * | |
4616 | * SNB support 3 levels of watermark. | |
4617 | * | |
4618 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4619 | * and disabled in the descending order | |
4620 | * | |
4621 | */ | |
4622 | I915_WRITE(WM3_LP_ILK, 0); | |
4623 | I915_WRITE(WM2_LP_ILK, 0); | |
4624 | I915_WRITE(WM1_LP_ILK, 0); | |
4625 | ||
b840d907 JB |
4626 | if (!single_plane_enabled(enabled) || |
4627 | dev_priv->sprite_scaling_enabled) | |
1398261a | 4628 | return; |
d210246a | 4629 | enabled = ffs(enabled) - 1; |
1398261a YL |
4630 | |
4631 | /* WM1 */ | |
d210246a CW |
4632 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4633 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4634 | &sandybridge_display_srwm_info, |
4635 | &sandybridge_cursor_srwm_info, | |
4636 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4637 | return; |
4638 | ||
4639 | I915_WRITE(WM1_LP_ILK, | |
4640 | WM1_LP_SR_EN | | |
4641 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4642 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4643 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4644 | cursor_wm); | |
4645 | ||
4646 | /* WM2 */ | |
d210246a CW |
4647 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4648 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4649 | &sandybridge_display_srwm_info, |
4650 | &sandybridge_cursor_srwm_info, | |
4651 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4652 | return; |
4653 | ||
4654 | I915_WRITE(WM2_LP_ILK, | |
4655 | WM2_LP_EN | | |
4656 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4657 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4658 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4659 | cursor_wm); | |
4660 | ||
4661 | /* WM3 */ | |
d210246a CW |
4662 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4663 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4664 | &sandybridge_display_srwm_info, |
4665 | &sandybridge_cursor_srwm_info, | |
4666 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4667 | return; |
4668 | ||
4669 | I915_WRITE(WM3_LP_ILK, | |
4670 | WM3_LP_EN | | |
4671 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4672 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4673 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4674 | cursor_wm); | |
4675 | } | |
4676 | ||
b840d907 JB |
4677 | static bool |
4678 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
4679 | uint32_t sprite_width, int pixel_size, | |
4680 | const struct intel_watermark_params *display, | |
4681 | int display_latency_ns, int *sprite_wm) | |
4682 | { | |
4683 | struct drm_crtc *crtc; | |
4684 | int clock; | |
4685 | int entries, tlb_miss; | |
4686 | ||
4687 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4688 | if (crtc->fb == NULL || !crtc->enabled) { | |
4689 | *sprite_wm = display->guard_size; | |
4690 | return false; | |
4691 | } | |
4692 | ||
4693 | clock = crtc->mode.clock; | |
4694 | ||
4695 | /* Use the small buffer method to calculate the sprite watermark */ | |
4696 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4697 | tlb_miss = display->fifo_size*display->cacheline_size - | |
4698 | sprite_width * 8; | |
4699 | if (tlb_miss > 0) | |
4700 | entries += tlb_miss; | |
4701 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4702 | *sprite_wm = entries + display->guard_size; | |
4703 | if (*sprite_wm > (int)display->max_wm) | |
4704 | *sprite_wm = display->max_wm; | |
4705 | ||
4706 | return true; | |
4707 | } | |
4708 | ||
4709 | static bool | |
4710 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
4711 | uint32_t sprite_width, int pixel_size, | |
4712 | const struct intel_watermark_params *display, | |
4713 | int latency_ns, int *sprite_wm) | |
4714 | { | |
4715 | struct drm_crtc *crtc; | |
4716 | unsigned long line_time_us; | |
4717 | int clock; | |
4718 | int line_count, line_size; | |
4719 | int small, large; | |
4720 | int entries; | |
4721 | ||
4722 | if (!latency_ns) { | |
4723 | *sprite_wm = 0; | |
4724 | return false; | |
4725 | } | |
4726 | ||
4727 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4728 | clock = crtc->mode.clock; | |
4729 | ||
4730 | line_time_us = (sprite_width * 1000) / clock; | |
4731 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4732 | line_size = sprite_width * pixel_size; | |
4733 | ||
4734 | /* Use the minimum of the small and large buffer method for primary */ | |
4735 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4736 | large = line_count * line_size; | |
4737 | ||
4738 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
4739 | *sprite_wm = entries + display->guard_size; | |
4740 | ||
4741 | return *sprite_wm > 0x3ff ? false : true; | |
4742 | } | |
4743 | ||
4744 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |
4745 | uint32_t sprite_width, int pixel_size) | |
4746 | { | |
4747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4748 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
47842649 | 4749 | u32 val; |
b840d907 JB |
4750 | int sprite_wm, reg; |
4751 | int ret; | |
4752 | ||
4753 | switch (pipe) { | |
4754 | case 0: | |
4755 | reg = WM0_PIPEA_ILK; | |
4756 | break; | |
4757 | case 1: | |
4758 | reg = WM0_PIPEB_ILK; | |
4759 | break; | |
4760 | case 2: | |
4761 | reg = WM0_PIPEC_IVB; | |
4762 | break; | |
4763 | default: | |
4764 | return; /* bad pipe */ | |
4765 | } | |
4766 | ||
4767 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
4768 | &sandybridge_display_wm_info, | |
4769 | latency, &sprite_wm); | |
4770 | if (!ret) { | |
4771 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", | |
4772 | pipe); | |
4773 | return; | |
4774 | } | |
4775 | ||
47842649 JB |
4776 | val = I915_READ(reg); |
4777 | val &= ~WM0_PIPE_SPRITE_MASK; | |
4778 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
b840d907 JB |
4779 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
4780 | ||
4781 | ||
4782 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4783 | pixel_size, | |
4784 | &sandybridge_display_srwm_info, | |
4785 | SNB_READ_WM1_LATENCY() * 500, | |
4786 | &sprite_wm); | |
4787 | if (!ret) { | |
4788 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", | |
4789 | pipe); | |
4790 | return; | |
4791 | } | |
4792 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
4793 | ||
4794 | /* Only IVB has two more LP watermarks for sprite */ | |
4795 | if (!IS_IVYBRIDGE(dev)) | |
4796 | return; | |
4797 | ||
4798 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4799 | pixel_size, | |
4800 | &sandybridge_display_srwm_info, | |
4801 | SNB_READ_WM2_LATENCY() * 500, | |
4802 | &sprite_wm); | |
4803 | if (!ret) { | |
4804 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", | |
4805 | pipe); | |
4806 | return; | |
4807 | } | |
4808 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
4809 | ||
4810 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4811 | pixel_size, | |
4812 | &sandybridge_display_srwm_info, | |
4813 | SNB_READ_WM3_LATENCY() * 500, | |
4814 | &sprite_wm); | |
4815 | if (!ret) { | |
4816 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", | |
4817 | pipe); | |
4818 | return; | |
4819 | } | |
4820 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
4821 | } | |
4822 | ||
7662c8bd SL |
4823 | /** |
4824 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4825 | * | |
4826 | * Calculate watermark values for the various WM regs based on current mode | |
4827 | * and plane configuration. | |
4828 | * | |
4829 | * There are several cases to deal with here: | |
4830 | * - normal (i.e. non-self-refresh) | |
4831 | * - self-refresh (SR) mode | |
4832 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4833 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4834 | * lines), so need to account for TLB latency | |
4835 | * | |
4836 | * The normal calculation is: | |
4837 | * watermark = dotclock * bytes per pixel * latency | |
4838 | * where latency is platform & configuration dependent (we assume pessimal | |
4839 | * values here). | |
4840 | * | |
4841 | * The SR calculation is: | |
4842 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4843 | * bytes per pixel | |
4844 | * where | |
4845 | * line time = htotal / dotclock | |
fa143215 | 4846 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4847 | * and latency is assumed to be high, as above. |
4848 | * | |
4849 | * The final value programmed to the register should always be rounded up, | |
4850 | * and include an extra 2 entries to account for clock crossings. | |
4851 | * | |
4852 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4853 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4854 | */ |
7662c8bd SL |
4855 | static void intel_update_watermarks(struct drm_device *dev) |
4856 | { | |
e70236a8 | 4857 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4858 | |
d210246a CW |
4859 | if (dev_priv->display.update_wm) |
4860 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4861 | } |
4862 | ||
b840d907 JB |
4863 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
4864 | uint32_t sprite_width, int pixel_size) | |
4865 | { | |
4866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4867 | ||
4868 | if (dev_priv->display.update_sprite_wm) | |
4869 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
4870 | pixel_size); | |
4871 | } | |
4872 | ||
a7615030 CW |
4873 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4874 | { | |
72bbe58c KP |
4875 | if (i915_panel_use_ssc >= 0) |
4876 | return i915_panel_use_ssc != 0; | |
4877 | return dev_priv->lvds_use_ssc | |
435793df | 4878 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4879 | } |
4880 | ||
5a354204 JB |
4881 | /** |
4882 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
4883 | * @crtc: CRTC structure | |
3b5c78a3 | 4884 | * @mode: requested mode |
5a354204 JB |
4885 | * |
4886 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
4887 | * attached framebuffer, choose a good color depth to use on the pipe. | |
4888 | * | |
4889 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4890 | * isn't ideal, because the connected output supports a lesser or restricted | |
4891 | * set of depths. Resolve that here: | |
4892 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4893 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4894 | * Displays may support a restricted set as well, check EDID and clamp as | |
4895 | * appropriate. | |
3b5c78a3 | 4896 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4897 | * |
4898 | * RETURNS: | |
4899 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4900 | * true if they don't match). | |
4901 | */ | |
4902 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
4903 | unsigned int *pipe_bpp, |
4904 | struct drm_display_mode *mode) | |
5a354204 JB |
4905 | { |
4906 | struct drm_device *dev = crtc->dev; | |
4907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4908 | struct drm_encoder *encoder; | |
4909 | struct drm_connector *connector; | |
4910 | unsigned int display_bpc = UINT_MAX, bpc; | |
4911 | ||
4912 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
4913 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4914 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
4915 | ||
4916 | if (encoder->crtc != crtc) | |
4917 | continue; | |
4918 | ||
4919 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4920 | unsigned int lvds_bpc; | |
4921 | ||
4922 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4923 | LVDS_A3_POWER_UP) | |
4924 | lvds_bpc = 8; | |
4925 | else | |
4926 | lvds_bpc = 6; | |
4927 | ||
4928 | if (lvds_bpc < display_bpc) { | |
82820490 | 4929 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4930 | display_bpc = lvds_bpc; |
4931 | } | |
4932 | continue; | |
4933 | } | |
4934 | ||
4935 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
4936 | /* Use VBT settings if we have an eDP panel */ | |
4937 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4938 | ||
4939 | if (edp_bpc < display_bpc) { | |
82820490 | 4940 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
4941 | display_bpc = edp_bpc; |
4942 | } | |
4943 | continue; | |
4944 | } | |
4945 | ||
4946 | /* Not one of the known troublemakers, check the EDID */ | |
4947 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4948 | head) { | |
4949 | if (connector->encoder != encoder) | |
4950 | continue; | |
4951 | ||
62ac41a6 JB |
4952 | /* Don't use an invalid EDID bpc value */ |
4953 | if (connector->display_info.bpc && | |
4954 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4955 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4956 | display_bpc = connector->display_info.bpc; |
4957 | } | |
4958 | } | |
4959 | ||
4960 | /* | |
4961 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4962 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4963 | */ | |
4964 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4965 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 4966 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
4967 | display_bpc = 12; |
4968 | } else { | |
82820490 | 4969 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
4970 | display_bpc = 8; |
4971 | } | |
4972 | } | |
4973 | } | |
4974 | ||
3b5c78a3 AJ |
4975 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4976 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
4977 | display_bpc = 6; | |
4978 | } | |
4979 | ||
5a354204 JB |
4980 | /* |
4981 | * We could just drive the pipe at the highest bpc all the time and | |
4982 | * enable dithering as needed, but that costs bandwidth. So choose | |
4983 | * the minimum value that expresses the full color range of the fb but | |
4984 | * also stays within the max display bpc discovered above. | |
4985 | */ | |
4986 | ||
4987 | switch (crtc->fb->depth) { | |
4988 | case 8: | |
4989 | bpc = 8; /* since we go through a colormap */ | |
4990 | break; | |
4991 | case 15: | |
4992 | case 16: | |
4993 | bpc = 6; /* min is 18bpp */ | |
4994 | break; | |
4995 | case 24: | |
578393cd | 4996 | bpc = 8; |
5a354204 JB |
4997 | break; |
4998 | case 30: | |
578393cd | 4999 | bpc = 10; |
5a354204 JB |
5000 | break; |
5001 | case 48: | |
578393cd | 5002 | bpc = 12; |
5a354204 JB |
5003 | break; |
5004 | default: | |
5005 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
5006 | bpc = min((unsigned int)8, display_bpc); | |
5007 | break; | |
5008 | } | |
5009 | ||
578393cd KP |
5010 | display_bpc = min(display_bpc, bpc); |
5011 | ||
82820490 AJ |
5012 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
5013 | bpc, display_bpc); | |
5a354204 | 5014 | |
578393cd | 5015 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
5016 | |
5017 | return display_bpc != bpc; | |
5018 | } | |
5019 | ||
c65d77d8 JB |
5020 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5021 | { | |
5022 | struct drm_device *dev = crtc->dev; | |
5023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5024 | int refclk; | |
5025 | ||
5026 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5027 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5028 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
5029 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5030 | refclk / 1000); | |
5031 | } else if (!IS_GEN2(dev)) { | |
5032 | refclk = 96000; | |
5033 | } else { | |
5034 | refclk = 48000; | |
5035 | } | |
5036 | ||
5037 | return refclk; | |
5038 | } | |
5039 | ||
5040 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
5041 | intel_clock_t *clock) | |
5042 | { | |
5043 | /* SDVO TV has fixed PLL values depend on its clock range, | |
5044 | this mirrors vbios setting. */ | |
5045 | if (adjusted_mode->clock >= 100000 | |
5046 | && adjusted_mode->clock < 140500) { | |
5047 | clock->p1 = 2; | |
5048 | clock->p2 = 10; | |
5049 | clock->n = 3; | |
5050 | clock->m1 = 16; | |
5051 | clock->m2 = 8; | |
5052 | } else if (adjusted_mode->clock >= 140500 | |
5053 | && adjusted_mode->clock <= 200000) { | |
5054 | clock->p1 = 1; | |
5055 | clock->p2 = 10; | |
5056 | clock->n = 6; | |
5057 | clock->m1 = 12; | |
5058 | clock->m2 = 8; | |
5059 | } | |
5060 | } | |
5061 | ||
a7516a05 JB |
5062 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
5063 | intel_clock_t *clock, | |
5064 | intel_clock_t *reduced_clock) | |
5065 | { | |
5066 | struct drm_device *dev = crtc->dev; | |
5067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5069 | int pipe = intel_crtc->pipe; | |
5070 | u32 fp, fp2 = 0; | |
5071 | ||
5072 | if (IS_PINEVIEW(dev)) { | |
5073 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
5074 | if (reduced_clock) | |
5075 | fp2 = (1 << reduced_clock->n) << 16 | | |
5076 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
5077 | } else { | |
5078 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
5079 | if (reduced_clock) | |
5080 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
5081 | reduced_clock->m2; | |
5082 | } | |
5083 | ||
5084 | I915_WRITE(FP0(pipe), fp); | |
5085 | ||
5086 | intel_crtc->lowfreq_avail = false; | |
5087 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5088 | reduced_clock && i915_powersave) { | |
5089 | I915_WRITE(FP1(pipe), fp2); | |
5090 | intel_crtc->lowfreq_avail = true; | |
5091 | } else { | |
5092 | I915_WRITE(FP1(pipe), fp); | |
5093 | } | |
5094 | } | |
5095 | ||
f564048e EA |
5096 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5097 | struct drm_display_mode *mode, | |
5098 | struct drm_display_mode *adjusted_mode, | |
5099 | int x, int y, | |
5100 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5101 | { |
5102 | struct drm_device *dev = crtc->dev; | |
5103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5105 | int pipe = intel_crtc->pipe; | |
80824003 | 5106 | int plane = intel_crtc->plane; |
c751ce4f | 5107 | int refclk, num_connectors = 0; |
652c393a | 5108 | intel_clock_t clock, reduced_clock; |
a7516a05 | 5109 | u32 dpll, dspcntr, pipeconf; |
652c393a | 5110 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 5111 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 5112 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5113 | struct intel_encoder *encoder; |
d4906093 | 5114 | const intel_limit_t *limit; |
5c3b82e2 | 5115 | int ret; |
fae14981 | 5116 | u32 temp; |
aa9b500d | 5117 | u32 lvds_sync = 0; |
79e53945 | 5118 | |
5eddb70b CW |
5119 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5120 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5121 | continue; |
5122 | ||
5eddb70b | 5123 | switch (encoder->type) { |
79e53945 JB |
5124 | case INTEL_OUTPUT_LVDS: |
5125 | is_lvds = true; | |
5126 | break; | |
5127 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5128 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5129 | is_sdvo = true; |
5eddb70b | 5130 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5131 | is_tv = true; |
79e53945 JB |
5132 | break; |
5133 | case INTEL_OUTPUT_DVO: | |
5134 | is_dvo = true; | |
5135 | break; | |
5136 | case INTEL_OUTPUT_TVOUT: | |
5137 | is_tv = true; | |
5138 | break; | |
5139 | case INTEL_OUTPUT_ANALOG: | |
5140 | is_crt = true; | |
5141 | break; | |
a4fc5ed6 KP |
5142 | case INTEL_OUTPUT_DISPLAYPORT: |
5143 | is_dp = true; | |
5144 | break; | |
79e53945 | 5145 | } |
43565a06 | 5146 | |
c751ce4f | 5147 | num_connectors++; |
79e53945 JB |
5148 | } |
5149 | ||
c65d77d8 | 5150 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 5151 | |
d4906093 ML |
5152 | /* |
5153 | * Returns a set of divisors for the desired target clock with the given | |
5154 | * refclk, or FALSE. The returned values represent the clock equation: | |
5155 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5156 | */ | |
1b894b59 | 5157 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5158 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5159 | &clock); | |
79e53945 JB |
5160 | if (!ok) { |
5161 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5162 | return -EINVAL; |
79e53945 JB |
5163 | } |
5164 | ||
cda4b7d3 | 5165 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5166 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5167 | |
ddc9003c | 5168 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5169 | /* |
5170 | * Ensure we match the reduced clock's P to the target clock. | |
5171 | * If the clocks don't match, we can't switch the display clock | |
5172 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5173 | * downclock feature. | |
5174 | */ | |
ddc9003c | 5175 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5176 | dev_priv->lvds_downclock, |
5177 | refclk, | |
cec2f356 | 5178 | &clock, |
5eddb70b | 5179 | &reduced_clock); |
7026d4ac ZW |
5180 | } |
5181 | ||
c65d77d8 JB |
5182 | if (is_sdvo && is_tv) |
5183 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 5184 | |
a7516a05 JB |
5185 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
5186 | &reduced_clock : NULL); | |
79e53945 | 5187 | |
929c77fb | 5188 | dpll = DPLL_VGA_MODE_DIS; |
2c07245f | 5189 | |
a6c45cf0 | 5190 | if (!IS_GEN2(dev)) { |
79e53945 JB |
5191 | if (is_lvds) |
5192 | dpll |= DPLLB_MODE_LVDS; | |
5193 | else | |
5194 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5195 | if (is_sdvo) { | |
6c9547ff CW |
5196 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5197 | if (pixel_multiplier > 1) { | |
5198 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
5199 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
6c9547ff | 5200 | } |
79e53945 | 5201 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5202 | } |
929c77fb | 5203 | if (is_dp) |
a4fc5ed6 | 5204 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
5205 | |
5206 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
5207 | if (IS_PINEVIEW(dev)) |
5208 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 5209 | else { |
2177832f | 5210 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
652c393a JB |
5211 | if (IS_G4X(dev) && has_reduced_clock) |
5212 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 5213 | } |
79e53945 JB |
5214 | switch (clock.p2) { |
5215 | case 5: | |
5216 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5217 | break; | |
5218 | case 7: | |
5219 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5220 | break; | |
5221 | case 10: | |
5222 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5223 | break; | |
5224 | case 14: | |
5225 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5226 | break; | |
5227 | } | |
929c77fb | 5228 | if (INTEL_INFO(dev)->gen >= 4) |
79e53945 JB |
5229 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5230 | } else { | |
5231 | if (is_lvds) { | |
5232 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5233 | } else { | |
5234 | if (clock.p1 == 2) | |
5235 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5236 | else | |
5237 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5238 | if (clock.p2 == 4) | |
5239 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5240 | } | |
5241 | } | |
5242 | ||
43565a06 KH |
5243 | if (is_sdvo && is_tv) |
5244 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5245 | else if (is_tv) | |
79e53945 | 5246 | /* XXX: just matching BIOS for now */ |
43565a06 | 5247 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5248 | dpll |= 3; |
a7615030 | 5249 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5250 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5251 | else |
5252 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5253 | ||
5254 | /* setup pipeconf */ | |
5eddb70b | 5255 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5256 | |
5257 | /* Set up the display plane register */ | |
5258 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5259 | ||
929c77fb EA |
5260 | if (pipe == 0) |
5261 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5262 | else | |
5263 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 5264 | |
a6c45cf0 | 5265 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
5266 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
5267 | * core speed. | |
5268 | * | |
5269 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
5270 | * pipe == 0 check? | |
5271 | */ | |
e70236a8 JB |
5272 | if (mode->clock > |
5273 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 5274 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 5275 | else |
5eddb70b | 5276 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
5277 | } |
5278 | ||
3b5c78a3 AJ |
5279 | /* default to 8bpc */ |
5280 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
5281 | if (is_dp) { | |
5282 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
5283 | pipeconf |= PIPECONF_BPP_6 | | |
5284 | PIPECONF_DITHER_EN | | |
5285 | PIPECONF_DITHER_TYPE_SP; | |
5286 | } | |
5287 | } | |
5288 | ||
929c77fb | 5289 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 5290 | |
28c97730 | 5291 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5292 | drm_mode_debug_printmodeline(mode); |
5293 | ||
fae14981 | 5294 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
5eddb70b | 5295 | |
fae14981 | 5296 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5297 | udelay(150); |
8db9d77b | 5298 | |
79e53945 JB |
5299 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5300 | * This is an exception to the general rule that mode_set doesn't turn | |
5301 | * things on. | |
5302 | */ | |
5303 | if (is_lvds) { | |
fae14981 | 5304 | temp = I915_READ(LVDS); |
5eddb70b | 5305 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 | 5306 | if (pipe == 1) { |
929c77fb | 5307 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 | 5308 | } else { |
929c77fb | 5309 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5310 | } |
a3e17eb8 | 5311 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5312 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5313 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5314 | * set the DPLLs for dual-channel mode or not. | |
5315 | */ | |
5316 | if (clock.p2 == 7) | |
5eddb70b | 5317 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5318 | else |
5eddb70b | 5319 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5320 | |
5321 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5322 | * appropriately here, but we need to look more thoroughly into how | |
5323 | * panels behave in the two modes. | |
5324 | */ | |
929c77fb EA |
5325 | /* set the dithering flag on LVDS as needed */ |
5326 | if (INTEL_INFO(dev)->gen >= 4) { | |
434ed097 | 5327 | if (dev_priv->lvds_dither) |
5eddb70b | 5328 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 5329 | else |
5eddb70b | 5330 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 5331 | } |
aa9b500d BF |
5332 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5333 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5334 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5335 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5336 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5337 | != lvds_sync) { | |
5338 | char flags[2] = "-+"; | |
5339 | DRM_INFO("Changing LVDS panel from " | |
5340 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5341 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5342 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5343 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5344 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5345 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5346 | temp |= lvds_sync; | |
5347 | } | |
fae14981 | 5348 | I915_WRITE(LVDS, temp); |
79e53945 | 5349 | } |
434ed097 | 5350 | |
929c77fb | 5351 | if (is_dp) { |
a4fc5ed6 | 5352 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
434ed097 JB |
5353 | } |
5354 | ||
fae14981 | 5355 | I915_WRITE(DPLL(pipe), dpll); |
5eddb70b | 5356 | |
c713bb08 | 5357 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5358 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5359 | udelay(150); |
32f9d658 | 5360 | |
c713bb08 EA |
5361 | if (INTEL_INFO(dev)->gen >= 4) { |
5362 | temp = 0; | |
5363 | if (is_sdvo) { | |
5364 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5365 | if (temp > 1) | |
5366 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5367 | else | |
5368 | temp = 0; | |
32f9d658 | 5369 | } |
c713bb08 EA |
5370 | I915_WRITE(DPLL_MD(pipe), temp); |
5371 | } else { | |
5372 | /* The pixel multiplier can only be updated once the | |
5373 | * DPLL is enabled and the clocks are stable. | |
5374 | * | |
5375 | * So write it again. | |
5376 | */ | |
fae14981 | 5377 | I915_WRITE(DPLL(pipe), dpll); |
79e53945 | 5378 | } |
79e53945 | 5379 | |
a7516a05 JB |
5380 | if (HAS_PIPE_CXSR(dev)) { |
5381 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 5382 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 5383 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 5384 | } else { |
28c97730 | 5385 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5386 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5387 | } | |
5388 | } | |
5389 | ||
734b4157 KH |
5390 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5391 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5392 | /* the chip adds 2 halflines automatically */ | |
5393 | adjusted_mode->crtc_vdisplay -= 1; | |
5394 | adjusted_mode->crtc_vtotal -= 1; | |
5395 | adjusted_mode->crtc_vblank_start -= 1; | |
5396 | adjusted_mode->crtc_vblank_end -= 1; | |
5397 | adjusted_mode->crtc_vsync_end -= 1; | |
5398 | adjusted_mode->crtc_vsync_start -= 1; | |
5399 | } else | |
59df7b17 | 5400 | pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */ |
734b4157 | 5401 | |
5eddb70b CW |
5402 | I915_WRITE(HTOTAL(pipe), |
5403 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5404 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5405 | I915_WRITE(HBLANK(pipe), |
5406 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5407 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5408 | I915_WRITE(HSYNC(pipe), |
5409 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5410 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5411 | |
5412 | I915_WRITE(VTOTAL(pipe), | |
5413 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5414 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5415 | I915_WRITE(VBLANK(pipe), |
5416 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5417 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5418 | I915_WRITE(VSYNC(pipe), |
5419 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5420 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5421 | |
5422 | /* pipesrc and dspsize control the size that is scaled from, | |
5423 | * which should always be the user's requested size. | |
79e53945 | 5424 | */ |
929c77fb EA |
5425 | I915_WRITE(DSPSIZE(plane), |
5426 | ((mode->vdisplay - 1) << 16) | | |
5427 | (mode->hdisplay - 1)); | |
5428 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5429 | I915_WRITE(PIPESRC(pipe), |
5430 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5431 | |
f564048e EA |
5432 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5433 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5434 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5435 | |
5436 | intel_wait_for_vblank(dev, pipe); | |
5437 | ||
f564048e EA |
5438 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5439 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5440 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5441 | |
5442 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5443 | ||
5444 | intel_update_watermarks(dev); | |
5445 | ||
f564048e EA |
5446 | return ret; |
5447 | } | |
5448 | ||
9fb526db KP |
5449 | /* |
5450 | * Initialize reference clocks when the driver loads | |
5451 | */ | |
5452 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5453 | { |
5454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5455 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5456 | struct intel_encoder *encoder; |
13d83a67 JB |
5457 | u32 temp; |
5458 | bool has_lvds = false; | |
199e5d79 KP |
5459 | bool has_cpu_edp = false; |
5460 | bool has_pch_edp = false; | |
5461 | bool has_panel = false; | |
99eb6a01 KP |
5462 | bool has_ck505 = false; |
5463 | bool can_ssc = false; | |
13d83a67 JB |
5464 | |
5465 | /* We need to take the global config into account */ | |
199e5d79 KP |
5466 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5467 | base.head) { | |
5468 | switch (encoder->type) { | |
5469 | case INTEL_OUTPUT_LVDS: | |
5470 | has_panel = true; | |
5471 | has_lvds = true; | |
5472 | break; | |
5473 | case INTEL_OUTPUT_EDP: | |
5474 | has_panel = true; | |
5475 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5476 | has_pch_edp = true; | |
5477 | else | |
5478 | has_cpu_edp = true; | |
5479 | break; | |
13d83a67 JB |
5480 | } |
5481 | } | |
5482 | ||
99eb6a01 KP |
5483 | if (HAS_PCH_IBX(dev)) { |
5484 | has_ck505 = dev_priv->display_clock_mode; | |
5485 | can_ssc = has_ck505; | |
5486 | } else { | |
5487 | has_ck505 = false; | |
5488 | can_ssc = true; | |
5489 | } | |
5490 | ||
5491 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5492 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5493 | has_ck505); | |
13d83a67 JB |
5494 | |
5495 | /* Ironlake: try to setup display ref clock before DPLL | |
5496 | * enabling. This is only under driver's control after | |
5497 | * PCH B stepping, previous chipset stepping should be | |
5498 | * ignoring this setting. | |
5499 | */ | |
5500 | temp = I915_READ(PCH_DREF_CONTROL); | |
5501 | /* Always enable nonspread source */ | |
5502 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5503 | |
99eb6a01 KP |
5504 | if (has_ck505) |
5505 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5506 | else | |
5507 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5508 | |
199e5d79 KP |
5509 | if (has_panel) { |
5510 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5511 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5512 | |
199e5d79 | 5513 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5514 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5515 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5516 | temp |= DREF_SSC1_ENABLE; |
13d83a67 | 5517 | } |
199e5d79 KP |
5518 | |
5519 | /* Get SSC going before enabling the outputs */ | |
5520 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5521 | POSTING_READ(PCH_DREF_CONTROL); | |
5522 | udelay(200); | |
5523 | ||
13d83a67 JB |
5524 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5525 | ||
5526 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5527 | if (has_cpu_edp) { |
99eb6a01 | 5528 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5529 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5530 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5531 | } |
13d83a67 JB |
5532 | else |
5533 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5534 | } else |
5535 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5536 | ||
5537 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5538 | POSTING_READ(PCH_DREF_CONTROL); | |
5539 | udelay(200); | |
5540 | } else { | |
5541 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5542 | ||
5543 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5544 | ||
5545 | /* Turn off CPU output */ | |
5546 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5547 | ||
5548 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5549 | POSTING_READ(PCH_DREF_CONTROL); | |
5550 | udelay(200); | |
5551 | ||
5552 | /* Turn off the SSC source */ | |
5553 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5554 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5555 | ||
5556 | /* Turn off SSC1 */ | |
5557 | temp &= ~ DREF_SSC1_ENABLE; | |
5558 | ||
13d83a67 JB |
5559 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5560 | POSTING_READ(PCH_DREF_CONTROL); | |
5561 | udelay(200); | |
5562 | } | |
5563 | } | |
5564 | ||
d9d444cb JB |
5565 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5566 | { | |
5567 | struct drm_device *dev = crtc->dev; | |
5568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5569 | struct intel_encoder *encoder; | |
5570 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5571 | struct intel_encoder *edp_encoder = NULL; | |
5572 | int num_connectors = 0; | |
5573 | bool is_lvds = false; | |
5574 | ||
5575 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5576 | if (encoder->base.crtc != crtc) | |
5577 | continue; | |
5578 | ||
5579 | switch (encoder->type) { | |
5580 | case INTEL_OUTPUT_LVDS: | |
5581 | is_lvds = true; | |
5582 | break; | |
5583 | case INTEL_OUTPUT_EDP: | |
5584 | edp_encoder = encoder; | |
5585 | break; | |
5586 | } | |
5587 | num_connectors++; | |
5588 | } | |
5589 | ||
5590 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5591 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5592 | dev_priv->lvds_ssc_freq); | |
5593 | return dev_priv->lvds_ssc_freq * 1000; | |
5594 | } | |
5595 | ||
5596 | return 120000; | |
5597 | } | |
5598 | ||
f564048e EA |
5599 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5600 | struct drm_display_mode *mode, | |
5601 | struct drm_display_mode *adjusted_mode, | |
5602 | int x, int y, | |
5603 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5604 | { |
5605 | struct drm_device *dev = crtc->dev; | |
5606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5608 | int pipe = intel_crtc->pipe; | |
80824003 | 5609 | int plane = intel_crtc->plane; |
c751ce4f | 5610 | int refclk, num_connectors = 0; |
652c393a | 5611 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5612 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5613 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5614 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5615 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5616 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5617 | struct intel_encoder *encoder; |
d4906093 | 5618 | const intel_limit_t *limit; |
5c3b82e2 | 5619 | int ret; |
2c07245f | 5620 | struct fdi_m_n m_n = {0}; |
fae14981 | 5621 | u32 temp; |
aa9b500d | 5622 | u32 lvds_sync = 0; |
5a354204 JB |
5623 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5624 | unsigned int pipe_bpp; | |
5625 | bool dither; | |
79e53945 | 5626 | |
5eddb70b CW |
5627 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5628 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5629 | continue; |
5630 | ||
5eddb70b | 5631 | switch (encoder->type) { |
79e53945 JB |
5632 | case INTEL_OUTPUT_LVDS: |
5633 | is_lvds = true; | |
5634 | break; | |
5635 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5636 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5637 | is_sdvo = true; |
5eddb70b | 5638 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5639 | is_tv = true; |
79e53945 | 5640 | break; |
79e53945 JB |
5641 | case INTEL_OUTPUT_TVOUT: |
5642 | is_tv = true; | |
5643 | break; | |
5644 | case INTEL_OUTPUT_ANALOG: | |
5645 | is_crt = true; | |
5646 | break; | |
a4fc5ed6 KP |
5647 | case INTEL_OUTPUT_DISPLAYPORT: |
5648 | is_dp = true; | |
5649 | break; | |
32f9d658 | 5650 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5651 | has_edp_encoder = encoder; |
32f9d658 | 5652 | break; |
79e53945 | 5653 | } |
43565a06 | 5654 | |
c751ce4f | 5655 | num_connectors++; |
79e53945 JB |
5656 | } |
5657 | ||
d9d444cb | 5658 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5659 | |
d4906093 ML |
5660 | /* |
5661 | * Returns a set of divisors for the desired target clock with the given | |
5662 | * refclk, or FALSE. The returned values represent the clock equation: | |
5663 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5664 | */ | |
1b894b59 | 5665 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5666 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5667 | &clock); | |
79e53945 JB |
5668 | if (!ok) { |
5669 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5670 | return -EINVAL; |
79e53945 JB |
5671 | } |
5672 | ||
cda4b7d3 | 5673 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5674 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5675 | |
ddc9003c | 5676 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5677 | /* |
5678 | * Ensure we match the reduced clock's P to the target clock. | |
5679 | * If the clocks don't match, we can't switch the display clock | |
5680 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5681 | * downclock feature. | |
5682 | */ | |
ddc9003c | 5683 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5684 | dev_priv->lvds_downclock, |
5685 | refclk, | |
cec2f356 | 5686 | &clock, |
5eddb70b | 5687 | &reduced_clock); |
652c393a | 5688 | } |
7026d4ac ZW |
5689 | /* SDVO TV has fixed PLL values depend on its clock range, |
5690 | this mirrors vbios setting. */ | |
5691 | if (is_sdvo && is_tv) { | |
5692 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5693 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5694 | clock.p1 = 2; |
5695 | clock.p2 = 10; | |
5696 | clock.n = 3; | |
5697 | clock.m1 = 16; | |
5698 | clock.m2 = 8; | |
5699 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5700 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5701 | clock.p1 = 1; |
5702 | clock.p2 = 10; | |
5703 | clock.n = 6; | |
5704 | clock.m1 = 12; | |
5705 | clock.m2 = 8; | |
5706 | } | |
5707 | } | |
5708 | ||
2c07245f | 5709 | /* FDI link */ |
8febb297 EA |
5710 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5711 | lane = 0; | |
5712 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5713 | according to current link config */ | |
5714 | if (has_edp_encoder && | |
5715 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5716 | target_clock = mode->clock; | |
5717 | intel_edp_link_config(has_edp_encoder, | |
5718 | &lane, &link_bw); | |
5719 | } else { | |
5720 | /* [e]DP over FDI requires target mode clock | |
5721 | instead of link clock */ | |
5722 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 5723 | target_clock = mode->clock; |
8febb297 EA |
5724 | else |
5725 | target_clock = adjusted_mode->clock; | |
5726 | ||
5727 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5728 | * each output octet as 10 bits. The actual frequency | |
5729 | * is stored as a divider into a 100MHz clock, and the | |
5730 | * mode pixel clock is stored in units of 1KHz. | |
5731 | * Hence the bw of each lane in terms of the mode signal | |
5732 | * is: | |
5733 | */ | |
5734 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5735 | } | |
58a27471 | 5736 | |
8febb297 EA |
5737 | /* determine panel color depth */ |
5738 | temp = I915_READ(PIPECONF(pipe)); | |
5739 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 5740 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
5741 | switch (pipe_bpp) { |
5742 | case 18: | |
5743 | temp |= PIPE_6BPC; | |
8febb297 | 5744 | break; |
5a354204 JB |
5745 | case 24: |
5746 | temp |= PIPE_8BPC; | |
8febb297 | 5747 | break; |
5a354204 JB |
5748 | case 30: |
5749 | temp |= PIPE_10BPC; | |
8febb297 | 5750 | break; |
5a354204 JB |
5751 | case 36: |
5752 | temp |= PIPE_12BPC; | |
8febb297 EA |
5753 | break; |
5754 | default: | |
62ac41a6 JB |
5755 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
5756 | pipe_bpp); | |
5a354204 JB |
5757 | temp |= PIPE_8BPC; |
5758 | pipe_bpp = 24; | |
5759 | break; | |
8febb297 | 5760 | } |
77ffb597 | 5761 | |
5a354204 JB |
5762 | intel_crtc->bpp = pipe_bpp; |
5763 | I915_WRITE(PIPECONF(pipe), temp); | |
5764 | ||
8febb297 EA |
5765 | if (!lane) { |
5766 | /* | |
5767 | * Account for spread spectrum to avoid | |
5768 | * oversubscribing the link. Max center spread | |
5769 | * is 2.5%; use 5% for safety's sake. | |
5770 | */ | |
5a354204 | 5771 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5772 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5773 | } |
2c07245f | 5774 | |
8febb297 EA |
5775 | intel_crtc->fdi_lanes = lane; |
5776 | ||
5777 | if (pixel_multiplier > 1) | |
5778 | link_bw *= pixel_multiplier; | |
5a354204 JB |
5779 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
5780 | &m_n); | |
8febb297 | 5781 | |
a07d6787 EA |
5782 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
5783 | if (has_reduced_clock) | |
5784 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5785 | reduced_clock.m2; | |
79e53945 | 5786 | |
c1858123 | 5787 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5788 | factor = 21; |
5789 | if (is_lvds) { | |
5790 | if ((intel_panel_use_ssc(dev_priv) && | |
5791 | dev_priv->lvds_ssc_freq == 100) || | |
5792 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5793 | factor = 25; | |
5794 | } else if (is_sdvo && is_tv) | |
5795 | factor = 20; | |
c1858123 | 5796 | |
cb0e0931 | 5797 | if (clock.m < factor * clock.n) |
8febb297 | 5798 | fp |= FP_CB_TUNE; |
2c07245f | 5799 | |
5eddb70b | 5800 | dpll = 0; |
2c07245f | 5801 | |
a07d6787 EA |
5802 | if (is_lvds) |
5803 | dpll |= DPLLB_MODE_LVDS; | |
5804 | else | |
5805 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5806 | if (is_sdvo) { | |
5807 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5808 | if (pixel_multiplier > 1) { | |
5809 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5810 | } |
a07d6787 EA |
5811 | dpll |= DPLL_DVO_HIGH_SPEED; |
5812 | } | |
5813 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5814 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 5815 | |
a07d6787 EA |
5816 | /* compute bitmask from p1 value */ |
5817 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5818 | /* also FPA1 */ | |
5819 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5820 | ||
5821 | switch (clock.p2) { | |
5822 | case 5: | |
5823 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5824 | break; | |
5825 | case 7: | |
5826 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5827 | break; | |
5828 | case 10: | |
5829 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5830 | break; | |
5831 | case 14: | |
5832 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5833 | break; | |
79e53945 JB |
5834 | } |
5835 | ||
43565a06 KH |
5836 | if (is_sdvo && is_tv) |
5837 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5838 | else if (is_tv) | |
79e53945 | 5839 | /* XXX: just matching BIOS for now */ |
43565a06 | 5840 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5841 | dpll |= 3; |
a7615030 | 5842 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5843 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5844 | else |
5845 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5846 | ||
5847 | /* setup pipeconf */ | |
5eddb70b | 5848 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5849 | |
5850 | /* Set up the display plane register */ | |
5851 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5852 | ||
f7cb34d4 | 5853 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5854 | drm_mode_debug_printmodeline(mode); |
5855 | ||
5c5313c8 | 5856 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 JB |
5857 | if (!intel_crtc->no_pll) { |
5858 | if (!has_edp_encoder || | |
5859 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5860 | I915_WRITE(PCH_FP0(pipe), fp); | |
5861 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5862 | ||
5863 | POSTING_READ(PCH_DPLL(pipe)); | |
5864 | udelay(150); | |
5865 | } | |
5866 | } else { | |
5867 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
5868 | fp == I915_READ(PCH_FP0(0))) { | |
5869 | intel_crtc->use_pll_a = true; | |
5870 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
5871 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
5872 | fp == I915_READ(PCH_FP0(1))) { | |
5873 | intel_crtc->use_pll_a = false; | |
5874 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
5875 | } else { | |
5876 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
5877 | return -EINVAL; | |
5878 | } | |
79e53945 JB |
5879 | } |
5880 | ||
5881 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
5882 | * This is an exception to the general rule that mode_set doesn't turn | |
5883 | * things on. | |
5884 | */ | |
5885 | if (is_lvds) { | |
fae14981 | 5886 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 5887 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
5888 | if (HAS_PCH_CPT(dev)) { |
5889 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 5890 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
5891 | } else { |
5892 | if (pipe == 1) | |
5893 | temp |= LVDS_PIPEB_SELECT; | |
5894 | else | |
5895 | temp &= ~LVDS_PIPEB_SELECT; | |
5896 | } | |
4b645f14 | 5897 | |
a3e17eb8 | 5898 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5899 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5900 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5901 | * set the DPLLs for dual-channel mode or not. | |
5902 | */ | |
5903 | if (clock.p2 == 7) | |
5eddb70b | 5904 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5905 | else |
5eddb70b | 5906 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5907 | |
5908 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5909 | * appropriately here, but we need to look more thoroughly into how | |
5910 | * panels behave in the two modes. | |
5911 | */ | |
aa9b500d BF |
5912 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5913 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5914 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5915 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5916 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5917 | != lvds_sync) { | |
5918 | char flags[2] = "-+"; | |
5919 | DRM_INFO("Changing LVDS panel from " | |
5920 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5921 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5922 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5923 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5924 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5925 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5926 | temp |= lvds_sync; | |
5927 | } | |
fae14981 | 5928 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 5929 | } |
434ed097 | 5930 | |
8febb297 EA |
5931 | pipeconf &= ~PIPECONF_DITHER_EN; |
5932 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 5933 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 5934 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 5935 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 5936 | } |
5c5313c8 | 5937 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5938 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 5939 | } else { |
8db9d77b | 5940 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5941 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5942 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5943 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5944 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5945 | } |
79e53945 | 5946 | |
4b645f14 JB |
5947 | if (!intel_crtc->no_pll && |
5948 | (!has_edp_encoder || | |
5949 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { | |
fae14981 | 5950 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 5951 | |
32f9d658 | 5952 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5953 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
5954 | udelay(150); |
5955 | ||
8febb297 EA |
5956 | /* The pixel multiplier can only be updated once the |
5957 | * DPLL is enabled and the clocks are stable. | |
5958 | * | |
5959 | * So write it again. | |
5960 | */ | |
fae14981 | 5961 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 5962 | } |
79e53945 | 5963 | |
5eddb70b | 5964 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
5965 | if (!intel_crtc->no_pll) { |
5966 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
5967 | I915_WRITE(PCH_FP1(pipe), fp2); | |
5968 | intel_crtc->lowfreq_avail = true; | |
5969 | if (HAS_PIPE_CXSR(dev)) { | |
5970 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5971 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5972 | } | |
5973 | } else { | |
5974 | I915_WRITE(PCH_FP1(pipe), fp); | |
5975 | if (HAS_PIPE_CXSR(dev)) { | |
5976 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
5977 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
5978 | } | |
652c393a JB |
5979 | } |
5980 | } | |
5981 | ||
734b4157 KH |
5982 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5983 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5984 | /* the chip adds 2 halflines automatically */ | |
5985 | adjusted_mode->crtc_vdisplay -= 1; | |
5986 | adjusted_mode->crtc_vtotal -= 1; | |
5987 | adjusted_mode->crtc_vblank_start -= 1; | |
5988 | adjusted_mode->crtc_vblank_end -= 1; | |
5989 | adjusted_mode->crtc_vsync_end -= 1; | |
5990 | adjusted_mode->crtc_vsync_start -= 1; | |
5991 | } else | |
5992 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5993 | ||
5eddb70b CW |
5994 | I915_WRITE(HTOTAL(pipe), |
5995 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5996 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5997 | I915_WRITE(HBLANK(pipe), |
5998 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5999 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
6000 | I915_WRITE(HSYNC(pipe), |
6001 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 6002 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
6003 | |
6004 | I915_WRITE(VTOTAL(pipe), | |
6005 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 6006 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
6007 | I915_WRITE(VBLANK(pipe), |
6008 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 6009 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
6010 | I915_WRITE(VSYNC(pipe), |
6011 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 6012 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 6013 | |
8febb297 EA |
6014 | /* pipesrc controls the size that is scaled from, which should |
6015 | * always be the user's requested size. | |
79e53945 | 6016 | */ |
5eddb70b CW |
6017 | I915_WRITE(PIPESRC(pipe), |
6018 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 6019 | |
8febb297 EA |
6020 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
6021 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
6022 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
6023 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 6024 | |
8febb297 EA |
6025 | if (has_edp_encoder && |
6026 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6027 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
6028 | } |
6029 | ||
5eddb70b CW |
6030 | I915_WRITE(PIPECONF(pipe), pipeconf); |
6031 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 6032 | |
9d0498a2 | 6033 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 6034 | |
f00a3ddf | 6035 | if (IS_GEN5(dev)) { |
553bd149 ZW |
6036 | /* enable address swizzle for tiling buffer */ |
6037 | temp = I915_READ(DISP_ARB_CTL); | |
6038 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
6039 | } | |
6040 | ||
5eddb70b | 6041 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 6042 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6043 | |
5c3b82e2 | 6044 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
6045 | |
6046 | intel_update_watermarks(dev); | |
6047 | ||
1f803ee5 | 6048 | return ret; |
79e53945 JB |
6049 | } |
6050 | ||
f564048e EA |
6051 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6052 | struct drm_display_mode *mode, | |
6053 | struct drm_display_mode *adjusted_mode, | |
6054 | int x, int y, | |
6055 | struct drm_framebuffer *old_fb) | |
6056 | { | |
6057 | struct drm_device *dev = crtc->dev; | |
6058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
6059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6060 | int pipe = intel_crtc->pipe; | |
f564048e EA |
6061 | int ret; |
6062 | ||
0b701d27 | 6063 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6064 | |
f564048e EA |
6065 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
6066 | x, y, old_fb); | |
79e53945 | 6067 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6068 | |
d8e70a25 JB |
6069 | if (ret) |
6070 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
6071 | else | |
6072 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 6073 | |
1f803ee5 | 6074 | return ret; |
79e53945 JB |
6075 | } |
6076 | ||
3a9627f4 WF |
6077 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6078 | int reg_eldv, uint32_t bits_eldv, | |
6079 | int reg_elda, uint32_t bits_elda, | |
6080 | int reg_edid) | |
6081 | { | |
6082 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6083 | uint8_t *eld = connector->eld; | |
6084 | uint32_t i; | |
6085 | ||
6086 | i = I915_READ(reg_eldv); | |
6087 | i &= bits_eldv; | |
6088 | ||
6089 | if (!eld[0]) | |
6090 | return !i; | |
6091 | ||
6092 | if (!i) | |
6093 | return false; | |
6094 | ||
6095 | i = I915_READ(reg_elda); | |
6096 | i &= ~bits_elda; | |
6097 | I915_WRITE(reg_elda, i); | |
6098 | ||
6099 | for (i = 0; i < eld[2]; i++) | |
6100 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6101 | return false; | |
6102 | ||
6103 | return true; | |
6104 | } | |
6105 | ||
e0dac65e WF |
6106 | static void g4x_write_eld(struct drm_connector *connector, |
6107 | struct drm_crtc *crtc) | |
6108 | { | |
6109 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6110 | uint8_t *eld = connector->eld; | |
6111 | uint32_t eldv; | |
6112 | uint32_t len; | |
6113 | uint32_t i; | |
6114 | ||
6115 | i = I915_READ(G4X_AUD_VID_DID); | |
6116 | ||
6117 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6118 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6119 | else | |
6120 | eldv = G4X_ELDV_DEVCTG; | |
6121 | ||
3a9627f4 WF |
6122 | if (intel_eld_uptodate(connector, |
6123 | G4X_AUD_CNTL_ST, eldv, | |
6124 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6125 | G4X_HDMIW_HDMIEDID)) | |
6126 | return; | |
6127 | ||
e0dac65e WF |
6128 | i = I915_READ(G4X_AUD_CNTL_ST); |
6129 | i &= ~(eldv | G4X_ELD_ADDR); | |
6130 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6131 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6132 | ||
6133 | if (!eld[0]) | |
6134 | return; | |
6135 | ||
6136 | len = min_t(uint8_t, eld[2], len); | |
6137 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6138 | for (i = 0; i < len; i++) | |
6139 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6140 | ||
6141 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6142 | i |= eldv; | |
6143 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6144 | } | |
6145 | ||
6146 | static void ironlake_write_eld(struct drm_connector *connector, | |
6147 | struct drm_crtc *crtc) | |
6148 | { | |
6149 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6150 | uint8_t *eld = connector->eld; | |
6151 | uint32_t eldv; | |
6152 | uint32_t i; | |
6153 | int len; | |
6154 | int hdmiw_hdmiedid; | |
b6daa025 | 6155 | int aud_config; |
e0dac65e WF |
6156 | int aud_cntl_st; |
6157 | int aud_cntrl_st2; | |
6158 | ||
b3f33cbf | 6159 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 6160 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 6161 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
6162 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
6163 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 6164 | } else { |
1202b4c6 | 6165 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 6166 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
6167 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
6168 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
6169 | } |
6170 | ||
6171 | i = to_intel_crtc(crtc)->pipe; | |
6172 | hdmiw_hdmiedid += i * 0x100; | |
6173 | aud_cntl_st += i * 0x100; | |
b6daa025 | 6174 | aud_config += i * 0x100; |
e0dac65e WF |
6175 | |
6176 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
6177 | ||
6178 | i = I915_READ(aud_cntl_st); | |
6179 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
6180 | if (!i) { | |
6181 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6182 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6183 | eldv = IBX_ELD_VALIDB; |
6184 | eldv |= IBX_ELD_VALIDB << 4; | |
6185 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
6186 | } else { |
6187 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 6188 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6189 | } |
6190 | ||
3a9627f4 WF |
6191 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6192 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6193 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6194 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6195 | } else | |
6196 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6197 | |
3a9627f4 WF |
6198 | if (intel_eld_uptodate(connector, |
6199 | aud_cntrl_st2, eldv, | |
6200 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6201 | hdmiw_hdmiedid)) | |
6202 | return; | |
6203 | ||
e0dac65e WF |
6204 | i = I915_READ(aud_cntrl_st2); |
6205 | i &= ~eldv; | |
6206 | I915_WRITE(aud_cntrl_st2, i); | |
6207 | ||
6208 | if (!eld[0]) | |
6209 | return; | |
6210 | ||
e0dac65e | 6211 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6212 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6213 | I915_WRITE(aud_cntl_st, i); |
6214 | ||
6215 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6216 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6217 | for (i = 0; i < len; i++) | |
6218 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6219 | ||
6220 | i = I915_READ(aud_cntrl_st2); | |
6221 | i |= eldv; | |
6222 | I915_WRITE(aud_cntrl_st2, i); | |
6223 | } | |
6224 | ||
6225 | void intel_write_eld(struct drm_encoder *encoder, | |
6226 | struct drm_display_mode *mode) | |
6227 | { | |
6228 | struct drm_crtc *crtc = encoder->crtc; | |
6229 | struct drm_connector *connector; | |
6230 | struct drm_device *dev = encoder->dev; | |
6231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6232 | ||
6233 | connector = drm_select_eld(encoder, mode); | |
6234 | if (!connector) | |
6235 | return; | |
6236 | ||
6237 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6238 | connector->base.id, | |
6239 | drm_get_connector_name(connector), | |
6240 | connector->encoder->base.id, | |
6241 | drm_get_encoder_name(connector->encoder)); | |
6242 | ||
6243 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6244 | ||
6245 | if (dev_priv->display.write_eld) | |
6246 | dev_priv->display.write_eld(connector, crtc); | |
6247 | } | |
6248 | ||
79e53945 JB |
6249 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6250 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6251 | { | |
6252 | struct drm_device *dev = crtc->dev; | |
6253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6255 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6256 | int i; |
6257 | ||
6258 | /* The clocks have to be on to load the palette. */ | |
6259 | if (!crtc->enabled) | |
6260 | return; | |
6261 | ||
f2b115e6 | 6262 | /* use legacy palette for Ironlake */ |
bad720ff | 6263 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6264 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6265 | |
79e53945 JB |
6266 | for (i = 0; i < 256; i++) { |
6267 | I915_WRITE(palreg + 4 * i, | |
6268 | (intel_crtc->lut_r[i] << 16) | | |
6269 | (intel_crtc->lut_g[i] << 8) | | |
6270 | intel_crtc->lut_b[i]); | |
6271 | } | |
6272 | } | |
6273 | ||
560b85bb CW |
6274 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6275 | { | |
6276 | struct drm_device *dev = crtc->dev; | |
6277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6279 | bool visible = base != 0; | |
6280 | u32 cntl; | |
6281 | ||
6282 | if (intel_crtc->cursor_visible == visible) | |
6283 | return; | |
6284 | ||
9db4a9c7 | 6285 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6286 | if (visible) { |
6287 | /* On these chipsets we can only modify the base whilst | |
6288 | * the cursor is disabled. | |
6289 | */ | |
9db4a9c7 | 6290 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6291 | |
6292 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6293 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6294 | cntl |= CURSOR_ENABLE | | |
6295 | CURSOR_GAMMA_ENABLE | | |
6296 | CURSOR_FORMAT_ARGB; | |
6297 | } else | |
6298 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6299 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6300 | |
6301 | intel_crtc->cursor_visible = visible; | |
6302 | } | |
6303 | ||
6304 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6305 | { | |
6306 | struct drm_device *dev = crtc->dev; | |
6307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6309 | int pipe = intel_crtc->pipe; | |
6310 | bool visible = base != 0; | |
6311 | ||
6312 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6313 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6314 | if (base) { |
6315 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6316 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6317 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6318 | } else { | |
6319 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6320 | cntl |= CURSOR_MODE_DISABLE; | |
6321 | } | |
9db4a9c7 | 6322 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6323 | |
6324 | intel_crtc->cursor_visible = visible; | |
6325 | } | |
6326 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6327 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6328 | } |
6329 | ||
65a21cd6 JB |
6330 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6331 | { | |
6332 | struct drm_device *dev = crtc->dev; | |
6333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6335 | int pipe = intel_crtc->pipe; | |
6336 | bool visible = base != 0; | |
6337 | ||
6338 | if (intel_crtc->cursor_visible != visible) { | |
6339 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6340 | if (base) { | |
6341 | cntl &= ~CURSOR_MODE; | |
6342 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6343 | } else { | |
6344 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6345 | cntl |= CURSOR_MODE_DISABLE; | |
6346 | } | |
6347 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6348 | ||
6349 | intel_crtc->cursor_visible = visible; | |
6350 | } | |
6351 | /* and commit changes on next vblank */ | |
6352 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6353 | } | |
6354 | ||
cda4b7d3 | 6355 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6356 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6357 | bool on) | |
cda4b7d3 CW |
6358 | { |
6359 | struct drm_device *dev = crtc->dev; | |
6360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6361 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6362 | int pipe = intel_crtc->pipe; | |
6363 | int x = intel_crtc->cursor_x; | |
6364 | int y = intel_crtc->cursor_y; | |
560b85bb | 6365 | u32 base, pos; |
cda4b7d3 CW |
6366 | bool visible; |
6367 | ||
6368 | pos = 0; | |
6369 | ||
6b383a7f | 6370 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6371 | base = intel_crtc->cursor_addr; |
6372 | if (x > (int) crtc->fb->width) | |
6373 | base = 0; | |
6374 | ||
6375 | if (y > (int) crtc->fb->height) | |
6376 | base = 0; | |
6377 | } else | |
6378 | base = 0; | |
6379 | ||
6380 | if (x < 0) { | |
6381 | if (x + intel_crtc->cursor_width < 0) | |
6382 | base = 0; | |
6383 | ||
6384 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6385 | x = -x; | |
6386 | } | |
6387 | pos |= x << CURSOR_X_SHIFT; | |
6388 | ||
6389 | if (y < 0) { | |
6390 | if (y + intel_crtc->cursor_height < 0) | |
6391 | base = 0; | |
6392 | ||
6393 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6394 | y = -y; | |
6395 | } | |
6396 | pos |= y << CURSOR_Y_SHIFT; | |
6397 | ||
6398 | visible = base != 0; | |
560b85bb | 6399 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6400 | return; |
6401 | ||
65a21cd6 JB |
6402 | if (IS_IVYBRIDGE(dev)) { |
6403 | I915_WRITE(CURPOS_IVB(pipe), pos); | |
6404 | ivb_update_cursor(crtc, base); | |
6405 | } else { | |
6406 | I915_WRITE(CURPOS(pipe), pos); | |
6407 | if (IS_845G(dev) || IS_I865G(dev)) | |
6408 | i845_update_cursor(crtc, base); | |
6409 | else | |
6410 | i9xx_update_cursor(crtc, base); | |
6411 | } | |
cda4b7d3 CW |
6412 | |
6413 | if (visible) | |
6414 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
6415 | } | |
6416 | ||
79e53945 | 6417 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6418 | struct drm_file *file, |
79e53945 JB |
6419 | uint32_t handle, |
6420 | uint32_t width, uint32_t height) | |
6421 | { | |
6422 | struct drm_device *dev = crtc->dev; | |
6423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6425 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6426 | uint32_t addr; |
3f8bc370 | 6427 | int ret; |
79e53945 | 6428 | |
28c97730 | 6429 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
6430 | |
6431 | /* if we want to turn off the cursor ignore width and height */ | |
6432 | if (!handle) { | |
28c97730 | 6433 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6434 | addr = 0; |
05394f39 | 6435 | obj = NULL; |
5004417d | 6436 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6437 | goto finish; |
79e53945 JB |
6438 | } |
6439 | ||
6440 | /* Currently we only support 64x64 cursors */ | |
6441 | if (width != 64 || height != 64) { | |
6442 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6443 | return -EINVAL; | |
6444 | } | |
6445 | ||
05394f39 | 6446 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6447 | if (&obj->base == NULL) |
79e53945 JB |
6448 | return -ENOENT; |
6449 | ||
05394f39 | 6450 | if (obj->base.size < width * height * 4) { |
79e53945 | 6451 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6452 | ret = -ENOMEM; |
6453 | goto fail; | |
79e53945 JB |
6454 | } |
6455 | ||
71acb5eb | 6456 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6457 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6458 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6459 | if (obj->tiling_mode) { |
6460 | DRM_ERROR("cursor cannot be tiled\n"); | |
6461 | ret = -EINVAL; | |
6462 | goto fail_locked; | |
6463 | } | |
6464 | ||
2da3b9b9 | 6465 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6466 | if (ret) { |
6467 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6468 | goto fail_locked; |
e7b526bb CW |
6469 | } |
6470 | ||
d9e86c0e CW |
6471 | ret = i915_gem_object_put_fence(obj); |
6472 | if (ret) { | |
2da3b9b9 | 6473 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6474 | goto fail_unpin; |
6475 | } | |
6476 | ||
05394f39 | 6477 | addr = obj->gtt_offset; |
71acb5eb | 6478 | } else { |
6eeefaf3 | 6479 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6480 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6481 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6482 | align); | |
71acb5eb DA |
6483 | if (ret) { |
6484 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6485 | goto fail_locked; |
71acb5eb | 6486 | } |
05394f39 | 6487 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6488 | } |
6489 | ||
a6c45cf0 | 6490 | if (IS_GEN2(dev)) |
14b60391 JB |
6491 | I915_WRITE(CURSIZE, (height << 12) | width); |
6492 | ||
3f8bc370 | 6493 | finish: |
3f8bc370 | 6494 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6495 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6496 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6497 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6498 | } else | |
6499 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6500 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6501 | } |
80824003 | 6502 | |
7f9872e0 | 6503 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6504 | |
6505 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6506 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6507 | intel_crtc->cursor_width = width; |
6508 | intel_crtc->cursor_height = height; | |
6509 | ||
6b383a7f | 6510 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6511 | |
79e53945 | 6512 | return 0; |
e7b526bb | 6513 | fail_unpin: |
05394f39 | 6514 | i915_gem_object_unpin(obj); |
7f9872e0 | 6515 | fail_locked: |
34b8686e | 6516 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6517 | fail: |
05394f39 | 6518 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6519 | return ret; |
79e53945 JB |
6520 | } |
6521 | ||
6522 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6523 | { | |
79e53945 | 6524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6525 | |
cda4b7d3 CW |
6526 | intel_crtc->cursor_x = x; |
6527 | intel_crtc->cursor_y = y; | |
652c393a | 6528 | |
6b383a7f | 6529 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6530 | |
6531 | return 0; | |
6532 | } | |
6533 | ||
6534 | /** Sets the color ramps on behalf of RandR */ | |
6535 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6536 | u16 blue, int regno) | |
6537 | { | |
6538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6539 | ||
6540 | intel_crtc->lut_r[regno] = red >> 8; | |
6541 | intel_crtc->lut_g[regno] = green >> 8; | |
6542 | intel_crtc->lut_b[regno] = blue >> 8; | |
6543 | } | |
6544 | ||
b8c00ac5 DA |
6545 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6546 | u16 *blue, int regno) | |
6547 | { | |
6548 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6549 | ||
6550 | *red = intel_crtc->lut_r[regno] << 8; | |
6551 | *green = intel_crtc->lut_g[regno] << 8; | |
6552 | *blue = intel_crtc->lut_b[regno] << 8; | |
6553 | } | |
6554 | ||
79e53945 | 6555 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6556 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6557 | { |
7203425a | 6558 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6560 | |
7203425a | 6561 | for (i = start; i < end; i++) { |
79e53945 JB |
6562 | intel_crtc->lut_r[i] = red[i] >> 8; |
6563 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6564 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6565 | } | |
6566 | ||
6567 | intel_crtc_load_lut(crtc); | |
6568 | } | |
6569 | ||
6570 | /** | |
6571 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6572 | * detection. | |
6573 | * | |
6574 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6575 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6576 | * |
c751ce4f | 6577 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6578 | * configured for it. In the future, it could choose to temporarily disable |
6579 | * some outputs to free up a pipe for its use. | |
6580 | * | |
6581 | * \return crtc, or NULL if no pipes are available. | |
6582 | */ | |
6583 | ||
6584 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6585 | static struct drm_display_mode load_detect_mode = { | |
6586 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6587 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6588 | }; | |
6589 | ||
d2dff872 CW |
6590 | static struct drm_framebuffer * |
6591 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6592 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6593 | struct drm_i915_gem_object *obj) |
6594 | { | |
6595 | struct intel_framebuffer *intel_fb; | |
6596 | int ret; | |
6597 | ||
6598 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6599 | if (!intel_fb) { | |
6600 | drm_gem_object_unreference_unlocked(&obj->base); | |
6601 | return ERR_PTR(-ENOMEM); | |
6602 | } | |
6603 | ||
6604 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6605 | if (ret) { | |
6606 | drm_gem_object_unreference_unlocked(&obj->base); | |
6607 | kfree(intel_fb); | |
6608 | return ERR_PTR(ret); | |
6609 | } | |
6610 | ||
6611 | return &intel_fb->base; | |
6612 | } | |
6613 | ||
6614 | static u32 | |
6615 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6616 | { | |
6617 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6618 | return ALIGN(pitch, 64); | |
6619 | } | |
6620 | ||
6621 | static u32 | |
6622 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6623 | { | |
6624 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6625 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6626 | } | |
6627 | ||
6628 | static struct drm_framebuffer * | |
6629 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6630 | struct drm_display_mode *mode, | |
6631 | int depth, int bpp) | |
6632 | { | |
6633 | struct drm_i915_gem_object *obj; | |
308e5bcb | 6634 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
6635 | |
6636 | obj = i915_gem_alloc_object(dev, | |
6637 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6638 | if (obj == NULL) | |
6639 | return ERR_PTR(-ENOMEM); | |
6640 | ||
6641 | mode_cmd.width = mode->hdisplay; | |
6642 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6643 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6644 | bpp); | |
6645 | mode_cmd.pixel_format = 0; | |
d2dff872 CW |
6646 | |
6647 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6648 | } | |
6649 | ||
6650 | static struct drm_framebuffer * | |
6651 | mode_fits_in_fbdev(struct drm_device *dev, | |
6652 | struct drm_display_mode *mode) | |
6653 | { | |
6654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6655 | struct drm_i915_gem_object *obj; | |
6656 | struct drm_framebuffer *fb; | |
6657 | ||
6658 | if (dev_priv->fbdev == NULL) | |
6659 | return NULL; | |
6660 | ||
6661 | obj = dev_priv->fbdev->ifb.obj; | |
6662 | if (obj == NULL) | |
6663 | return NULL; | |
6664 | ||
6665 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6666 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6667 | fb->bits_per_pixel)) | |
d2dff872 CW |
6668 | return NULL; |
6669 | ||
01f2c773 | 6670 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6671 | return NULL; |
6672 | ||
6673 | return fb; | |
6674 | } | |
6675 | ||
7173188d CW |
6676 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6677 | struct drm_connector *connector, | |
6678 | struct drm_display_mode *mode, | |
8261b191 | 6679 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6680 | { |
6681 | struct intel_crtc *intel_crtc; | |
6682 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6683 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6684 | struct drm_crtc *crtc = NULL; |
6685 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6686 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6687 | int i = -1; |
6688 | ||
d2dff872 CW |
6689 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6690 | connector->base.id, drm_get_connector_name(connector), | |
6691 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6692 | ||
79e53945 JB |
6693 | /* |
6694 | * Algorithm gets a little messy: | |
7a5e4805 | 6695 | * |
79e53945 JB |
6696 | * - if the connector already has an assigned crtc, use it (but make |
6697 | * sure it's on first) | |
7a5e4805 | 6698 | * |
79e53945 JB |
6699 | * - try to find the first unused crtc that can drive this connector, |
6700 | * and use that if we find one | |
79e53945 JB |
6701 | */ |
6702 | ||
6703 | /* See if we already have a CRTC for this connector */ | |
6704 | if (encoder->crtc) { | |
6705 | crtc = encoder->crtc; | |
8261b191 | 6706 | |
79e53945 | 6707 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6708 | old->dpms_mode = intel_crtc->dpms_mode; |
6709 | old->load_detect_temp = false; | |
6710 | ||
6711 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6712 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6713 | struct drm_encoder_helper_funcs *encoder_funcs; |
6714 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6715 | ||
79e53945 JB |
6716 | crtc_funcs = crtc->helper_private; |
6717 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6718 | |
6719 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6720 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6721 | } | |
8261b191 | 6722 | |
7173188d | 6723 | return true; |
79e53945 JB |
6724 | } |
6725 | ||
6726 | /* Find an unused one (if possible) */ | |
6727 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6728 | i++; | |
6729 | if (!(encoder->possible_crtcs & (1 << i))) | |
6730 | continue; | |
6731 | if (!possible_crtc->enabled) { | |
6732 | crtc = possible_crtc; | |
6733 | break; | |
6734 | } | |
79e53945 JB |
6735 | } |
6736 | ||
6737 | /* | |
6738 | * If we didn't find an unused CRTC, don't use any. | |
6739 | */ | |
6740 | if (!crtc) { | |
7173188d CW |
6741 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6742 | return false; | |
79e53945 JB |
6743 | } |
6744 | ||
6745 | encoder->crtc = crtc; | |
c1c43977 | 6746 | connector->encoder = encoder; |
79e53945 JB |
6747 | |
6748 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6749 | old->dpms_mode = intel_crtc->dpms_mode; |
6750 | old->load_detect_temp = true; | |
d2dff872 | 6751 | old->release_fb = NULL; |
79e53945 | 6752 | |
6492711d CW |
6753 | if (!mode) |
6754 | mode = &load_detect_mode; | |
79e53945 | 6755 | |
d2dff872 CW |
6756 | old_fb = crtc->fb; |
6757 | ||
6758 | /* We need a framebuffer large enough to accommodate all accesses | |
6759 | * that the plane may generate whilst we perform load detection. | |
6760 | * We can not rely on the fbcon either being present (we get called | |
6761 | * during its initialisation to detect all boot displays, or it may | |
6762 | * not even exist) or that it is large enough to satisfy the | |
6763 | * requested mode. | |
6764 | */ | |
6765 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6766 | if (crtc->fb == NULL) { | |
6767 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6768 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6769 | old->release_fb = crtc->fb; | |
6770 | } else | |
6771 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6772 | if (IS_ERR(crtc->fb)) { | |
6773 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6774 | crtc->fb = old_fb; | |
6775 | return false; | |
79e53945 | 6776 | } |
79e53945 | 6777 | |
d2dff872 | 6778 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 6779 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6780 | if (old->release_fb) |
6781 | old->release_fb->funcs->destroy(old->release_fb); | |
6782 | crtc->fb = old_fb; | |
6492711d | 6783 | return false; |
79e53945 | 6784 | } |
7173188d | 6785 | |
79e53945 | 6786 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6787 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6788 | |
7173188d | 6789 | return true; |
79e53945 JB |
6790 | } |
6791 | ||
c1c43977 | 6792 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6793 | struct drm_connector *connector, |
6794 | struct intel_load_detect_pipe *old) | |
79e53945 | 6795 | { |
4ef69c7a | 6796 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6797 | struct drm_device *dev = encoder->dev; |
6798 | struct drm_crtc *crtc = encoder->crtc; | |
6799 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6800 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6801 | ||
d2dff872 CW |
6802 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6803 | connector->base.id, drm_get_connector_name(connector), | |
6804 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6805 | ||
8261b191 | 6806 | if (old->load_detect_temp) { |
c1c43977 | 6807 | connector->encoder = NULL; |
79e53945 | 6808 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6809 | |
6810 | if (old->release_fb) | |
6811 | old->release_fb->funcs->destroy(old->release_fb); | |
6812 | ||
0622a53c | 6813 | return; |
79e53945 JB |
6814 | } |
6815 | ||
c751ce4f | 6816 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6817 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6818 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6819 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6820 | } |
6821 | } | |
6822 | ||
6823 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6824 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6825 | { | |
6826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6828 | int pipe = intel_crtc->pipe; | |
548f245b | 6829 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6830 | u32 fp; |
6831 | intel_clock_t clock; | |
6832 | ||
6833 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6834 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6835 | else |
39adb7a5 | 6836 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6837 | |
6838 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6839 | if (IS_PINEVIEW(dev)) { |
6840 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6841 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6842 | } else { |
6843 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6844 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6845 | } | |
6846 | ||
a6c45cf0 | 6847 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6848 | if (IS_PINEVIEW(dev)) |
6849 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6850 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6851 | else |
6852 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6853 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6854 | ||
6855 | switch (dpll & DPLL_MODE_MASK) { | |
6856 | case DPLLB_MODE_DAC_SERIAL: | |
6857 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6858 | 5 : 10; | |
6859 | break; | |
6860 | case DPLLB_MODE_LVDS: | |
6861 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6862 | 7 : 14; | |
6863 | break; | |
6864 | default: | |
28c97730 | 6865 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6866 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6867 | return 0; | |
6868 | } | |
6869 | ||
6870 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6871 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6872 | } else { |
6873 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6874 | ||
6875 | if (is_lvds) { | |
6876 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6877 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6878 | clock.p2 = 14; | |
6879 | ||
6880 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6881 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6882 | /* XXX: might not be 66MHz */ | |
2177832f | 6883 | intel_clock(dev, 66000, &clock); |
79e53945 | 6884 | } else |
2177832f | 6885 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6886 | } else { |
6887 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6888 | clock.p1 = 2; | |
6889 | else { | |
6890 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6891 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6892 | } | |
6893 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6894 | clock.p2 = 4; | |
6895 | else | |
6896 | clock.p2 = 2; | |
6897 | ||
2177832f | 6898 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6899 | } |
6900 | } | |
6901 | ||
6902 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6903 | * i830PllIsValid() because it relies on the xf86_config connector | |
6904 | * configuration being accurate, which it isn't necessarily. | |
6905 | */ | |
6906 | ||
6907 | return clock.dot; | |
6908 | } | |
6909 | ||
6910 | /** Returns the currently programmed mode of the given pipe. */ | |
6911 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6912 | struct drm_crtc *crtc) | |
6913 | { | |
548f245b | 6914 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6916 | int pipe = intel_crtc->pipe; | |
6917 | struct drm_display_mode *mode; | |
548f245b JB |
6918 | int htot = I915_READ(HTOTAL(pipe)); |
6919 | int hsync = I915_READ(HSYNC(pipe)); | |
6920 | int vtot = I915_READ(VTOTAL(pipe)); | |
6921 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6922 | |
6923 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6924 | if (!mode) | |
6925 | return NULL; | |
6926 | ||
6927 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6928 | mode->hdisplay = (htot & 0xffff) + 1; | |
6929 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6930 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6931 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6932 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6933 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6934 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6935 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6936 | ||
6937 | drm_mode_set_name(mode); | |
6938 | drm_mode_set_crtcinfo(mode, 0); | |
6939 | ||
6940 | return mode; | |
6941 | } | |
6942 | ||
652c393a JB |
6943 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6944 | ||
6945 | /* When this timer fires, we've been idle for awhile */ | |
6946 | static void intel_gpu_idle_timer(unsigned long arg) | |
6947 | { | |
6948 | struct drm_device *dev = (struct drm_device *)arg; | |
6949 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6950 | ||
ff7ea4c0 CW |
6951 | if (!list_empty(&dev_priv->mm.active_list)) { |
6952 | /* Still processing requests, so just re-arm the timer. */ | |
6953 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6954 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6955 | return; | |
6956 | } | |
652c393a | 6957 | |
ff7ea4c0 | 6958 | dev_priv->busy = false; |
01dfba93 | 6959 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6960 | } |
6961 | ||
652c393a JB |
6962 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
6963 | ||
6964 | static void intel_crtc_idle_timer(unsigned long arg) | |
6965 | { | |
6966 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
6967 | struct drm_crtc *crtc = &intel_crtc->base; | |
6968 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 6969 | struct intel_framebuffer *intel_fb; |
652c393a | 6970 | |
ff7ea4c0 CW |
6971 | intel_fb = to_intel_framebuffer(crtc->fb); |
6972 | if (intel_fb && intel_fb->obj->active) { | |
6973 | /* The framebuffer is still being accessed by the GPU. */ | |
6974 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6975 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6976 | return; | |
6977 | } | |
652c393a | 6978 | |
ff7ea4c0 | 6979 | intel_crtc->busy = false; |
01dfba93 | 6980 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6981 | } |
6982 | ||
3dec0095 | 6983 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6984 | { |
6985 | struct drm_device *dev = crtc->dev; | |
6986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6987 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6988 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6989 | int dpll_reg = DPLL(pipe); |
6990 | int dpll; | |
652c393a | 6991 | |
bad720ff | 6992 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6993 | return; |
6994 | ||
6995 | if (!dev_priv->lvds_downclock_avail) | |
6996 | return; | |
6997 | ||
dbdc6479 | 6998 | dpll = I915_READ(dpll_reg); |
652c393a | 6999 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7000 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
7001 | |
7002 | /* Unlock panel regs */ | |
dbdc6479 JB |
7003 | I915_WRITE(PP_CONTROL, |
7004 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
7005 | |
7006 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7007 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7008 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7009 | |
652c393a JB |
7010 | dpll = I915_READ(dpll_reg); |
7011 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7012 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
7013 | |
7014 | /* ...and lock them again */ | |
7015 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
7016 | } | |
7017 | ||
7018 | /* Schedule downclock */ | |
3dec0095 DV |
7019 | mod_timer(&intel_crtc->idle_timer, jiffies + |
7020 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
7021 | } |
7022 | ||
7023 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7024 | { | |
7025 | struct drm_device *dev = crtc->dev; | |
7026 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7028 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 7029 | int dpll_reg = DPLL(pipe); |
652c393a JB |
7030 | int dpll = I915_READ(dpll_reg); |
7031 | ||
bad720ff | 7032 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7033 | return; |
7034 | ||
7035 | if (!dev_priv->lvds_downclock_avail) | |
7036 | return; | |
7037 | ||
7038 | /* | |
7039 | * Since this is called by a timer, we should never get here in | |
7040 | * the manual case. | |
7041 | */ | |
7042 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 7043 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
7044 | |
7045 | /* Unlock panel regs */ | |
4a655f04 JB |
7046 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
7047 | PANEL_UNLOCK_REGS); | |
652c393a JB |
7048 | |
7049 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
7050 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7051 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7052 | dpll = I915_READ(dpll_reg); |
7053 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7054 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7055 | |
7056 | /* ...and lock them again */ | |
7057 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
7058 | } | |
7059 | ||
7060 | } | |
7061 | ||
7062 | /** | |
7063 | * intel_idle_update - adjust clocks for idleness | |
7064 | * @work: work struct | |
7065 | * | |
7066 | * Either the GPU or display (or both) went idle. Check the busy status | |
7067 | * here and adjust the CRTC and GPU clocks as necessary. | |
7068 | */ | |
7069 | static void intel_idle_update(struct work_struct *work) | |
7070 | { | |
7071 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
7072 | idle_work); | |
7073 | struct drm_device *dev = dev_priv->dev; | |
7074 | struct drm_crtc *crtc; | |
7075 | struct intel_crtc *intel_crtc; | |
7076 | ||
7077 | if (!i915_powersave) | |
7078 | return; | |
7079 | ||
7080 | mutex_lock(&dev->struct_mutex); | |
7081 | ||
7648fa99 JB |
7082 | i915_update_gfx_val(dev_priv); |
7083 | ||
652c393a JB |
7084 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7085 | /* Skip inactive CRTCs */ | |
7086 | if (!crtc->fb) | |
7087 | continue; | |
7088 | ||
7089 | intel_crtc = to_intel_crtc(crtc); | |
7090 | if (!intel_crtc->busy) | |
7091 | intel_decrease_pllclock(crtc); | |
7092 | } | |
7093 | ||
45ac22c8 | 7094 | |
652c393a JB |
7095 | mutex_unlock(&dev->struct_mutex); |
7096 | } | |
7097 | ||
7098 | /** | |
7099 | * intel_mark_busy - mark the GPU and possibly the display busy | |
7100 | * @dev: drm device | |
7101 | * @obj: object we're operating on | |
7102 | * | |
7103 | * Callers can use this function to indicate that the GPU is busy processing | |
7104 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
7105 | * buffer), we'll also mark the display as busy, so we know to increase its | |
7106 | * clock frequency. | |
7107 | */ | |
05394f39 | 7108 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
7109 | { |
7110 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7111 | struct drm_crtc *crtc = NULL; | |
7112 | struct intel_framebuffer *intel_fb; | |
7113 | struct intel_crtc *intel_crtc; | |
7114 | ||
5e17ee74 ZW |
7115 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7116 | return; | |
7117 | ||
18b2190c | 7118 | if (!dev_priv->busy) |
28cf798f | 7119 | dev_priv->busy = true; |
18b2190c | 7120 | else |
28cf798f CW |
7121 | mod_timer(&dev_priv->idle_timer, jiffies + |
7122 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
7123 | |
7124 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
7125 | if (!crtc->fb) | |
7126 | continue; | |
7127 | ||
7128 | intel_crtc = to_intel_crtc(crtc); | |
7129 | intel_fb = to_intel_framebuffer(crtc->fb); | |
7130 | if (intel_fb->obj == obj) { | |
7131 | if (!intel_crtc->busy) { | |
7132 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 7133 | intel_increase_pllclock(crtc); |
652c393a JB |
7134 | intel_crtc->busy = true; |
7135 | } else { | |
7136 | /* Busy -> busy, put off timer */ | |
7137 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7138 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7139 | } | |
7140 | } | |
7141 | } | |
7142 | } | |
7143 | ||
79e53945 JB |
7144 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7145 | { | |
7146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7147 | struct drm_device *dev = crtc->dev; |
7148 | struct intel_unpin_work *work; | |
7149 | unsigned long flags; | |
7150 | ||
7151 | spin_lock_irqsave(&dev->event_lock, flags); | |
7152 | work = intel_crtc->unpin_work; | |
7153 | intel_crtc->unpin_work = NULL; | |
7154 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7155 | ||
7156 | if (work) { | |
7157 | cancel_work_sync(&work->work); | |
7158 | kfree(work); | |
7159 | } | |
79e53945 JB |
7160 | |
7161 | drm_crtc_cleanup(crtc); | |
67e77c5a | 7162 | |
79e53945 JB |
7163 | kfree(intel_crtc); |
7164 | } | |
7165 | ||
6b95a207 KH |
7166 | static void intel_unpin_work_fn(struct work_struct *__work) |
7167 | { | |
7168 | struct intel_unpin_work *work = | |
7169 | container_of(__work, struct intel_unpin_work, work); | |
7170 | ||
7171 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 7172 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7173 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7174 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7175 | |
7782de3b | 7176 | intel_update_fbc(work->dev); |
6b95a207 KH |
7177 | mutex_unlock(&work->dev->struct_mutex); |
7178 | kfree(work); | |
7179 | } | |
7180 | ||
1afe3e9d | 7181 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7182 | struct drm_crtc *crtc) |
6b95a207 KH |
7183 | { |
7184 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7186 | struct intel_unpin_work *work; | |
05394f39 | 7187 | struct drm_i915_gem_object *obj; |
6b95a207 | 7188 | struct drm_pending_vblank_event *e; |
49b14a5c | 7189 | struct timeval tnow, tvbl; |
6b95a207 KH |
7190 | unsigned long flags; |
7191 | ||
7192 | /* Ignore early vblank irqs */ | |
7193 | if (intel_crtc == NULL) | |
7194 | return; | |
7195 | ||
49b14a5c MK |
7196 | do_gettimeofday(&tnow); |
7197 | ||
6b95a207 KH |
7198 | spin_lock_irqsave(&dev->event_lock, flags); |
7199 | work = intel_crtc->unpin_work; | |
7200 | if (work == NULL || !work->pending) { | |
7201 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7202 | return; | |
7203 | } | |
7204 | ||
7205 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
7206 | |
7207 | if (work->event) { | |
7208 | e = work->event; | |
49b14a5c | 7209 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
7210 | |
7211 | /* Called before vblank count and timestamps have | |
7212 | * been updated for the vblank interval of flip | |
7213 | * completion? Need to increment vblank count and | |
7214 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
7215 | * to account for this. We assume this happened if we |
7216 | * get called over 0.9 frame durations after the last | |
7217 | * timestamped vblank. | |
7218 | * | |
7219 | * This calculation can not be used with vrefresh rates | |
7220 | * below 5Hz (10Hz to be on the safe side) without | |
7221 | * promoting to 64 integers. | |
0af7e4df | 7222 | */ |
49b14a5c MK |
7223 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
7224 | 9 * crtc->framedur_ns) { | |
0af7e4df | 7225 | e->event.sequence++; |
49b14a5c MK |
7226 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
7227 | crtc->framedur_ns); | |
0af7e4df MK |
7228 | } |
7229 | ||
49b14a5c MK |
7230 | e->event.tv_sec = tvbl.tv_sec; |
7231 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 7232 | |
6b95a207 KH |
7233 | list_add_tail(&e->base.link, |
7234 | &e->base.file_priv->event_list); | |
7235 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
7236 | } | |
7237 | ||
0af7e4df MK |
7238 | drm_vblank_put(dev, intel_crtc->pipe); |
7239 | ||
6b95a207 KH |
7240 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7241 | ||
05394f39 | 7242 | obj = work->old_fb_obj; |
d9e86c0e | 7243 | |
e59f2bac | 7244 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
7245 | &obj->pending_flip.counter); |
7246 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 7247 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 7248 | |
6b95a207 | 7249 | schedule_work(&work->work); |
e5510fac JB |
7250 | |
7251 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7252 | } |
7253 | ||
1afe3e9d JB |
7254 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7255 | { | |
7256 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7257 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7258 | ||
49b14a5c | 7259 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7260 | } |
7261 | ||
7262 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7263 | { | |
7264 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7265 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7266 | ||
49b14a5c | 7267 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7268 | } |
7269 | ||
6b95a207 KH |
7270 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7271 | { | |
7272 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7273 | struct intel_crtc *intel_crtc = | |
7274 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7275 | unsigned long flags; | |
7276 | ||
7277 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 7278 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
7279 | if ((++intel_crtc->unpin_work->pending) > 1) |
7280 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
7281 | } else { |
7282 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
7283 | } | |
6b95a207 KH |
7284 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7285 | } | |
7286 | ||
8c9f3aaf JB |
7287 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7288 | struct drm_crtc *crtc, | |
7289 | struct drm_framebuffer *fb, | |
7290 | struct drm_i915_gem_object *obj) | |
7291 | { | |
7292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7294 | unsigned long offset; | |
7295 | u32 flip_mask; | |
7296 | int ret; | |
7297 | ||
7298 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7299 | if (ret) | |
7300 | goto out; | |
7301 | ||
7302 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7303 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7304 | |
7305 | ret = BEGIN_LP_RING(6); | |
7306 | if (ret) | |
7307 | goto out; | |
7308 | ||
7309 | /* Can't queue multiple flips, so wait for the previous | |
7310 | * one to finish before executing the next. | |
7311 | */ | |
7312 | if (intel_crtc->plane) | |
7313 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7314 | else | |
7315 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7316 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7317 | OUT_RING(MI_NOOP); | |
7318 | OUT_RING(MI_DISPLAY_FLIP | | |
7319 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7320 | OUT_RING(fb->pitches[0]); |
8c9f3aaf | 7321 | OUT_RING(obj->gtt_offset + offset); |
c6a32fcb | 7322 | OUT_RING(0); /* aux display base address, unused */ |
8c9f3aaf JB |
7323 | ADVANCE_LP_RING(); |
7324 | out: | |
7325 | return ret; | |
7326 | } | |
7327 | ||
7328 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7329 | struct drm_crtc *crtc, | |
7330 | struct drm_framebuffer *fb, | |
7331 | struct drm_i915_gem_object *obj) | |
7332 | { | |
7333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7335 | unsigned long offset; | |
7336 | u32 flip_mask; | |
7337 | int ret; | |
7338 | ||
7339 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7340 | if (ret) | |
7341 | goto out; | |
7342 | ||
7343 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7344 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7345 | |
7346 | ret = BEGIN_LP_RING(6); | |
7347 | if (ret) | |
7348 | goto out; | |
7349 | ||
7350 | if (intel_crtc->plane) | |
7351 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7352 | else | |
7353 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7354 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7355 | OUT_RING(MI_NOOP); | |
7356 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
7357 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7358 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7359 | OUT_RING(obj->gtt_offset + offset); |
7360 | OUT_RING(MI_NOOP); | |
7361 | ||
7362 | ADVANCE_LP_RING(); | |
7363 | out: | |
7364 | return ret; | |
7365 | } | |
7366 | ||
7367 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7368 | struct drm_crtc *crtc, | |
7369 | struct drm_framebuffer *fb, | |
7370 | struct drm_i915_gem_object *obj) | |
7371 | { | |
7372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7374 | uint32_t pf, pipesrc; | |
7375 | int ret; | |
7376 | ||
7377 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7378 | if (ret) | |
7379 | goto out; | |
7380 | ||
7381 | ret = BEGIN_LP_RING(4); | |
7382 | if (ret) | |
7383 | goto out; | |
7384 | ||
7385 | /* i965+ uses the linear or tiled offsets from the | |
7386 | * Display Registers (which do not change across a page-flip) | |
7387 | * so we need only reprogram the base address. | |
7388 | */ | |
7389 | OUT_RING(MI_DISPLAY_FLIP | | |
7390 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7391 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7392 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
7393 | ||
7394 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7395 | * untested on non-native modes, so ignore it for now. | |
7396 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7397 | */ | |
7398 | pf = 0; | |
7399 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7400 | OUT_RING(pf | pipesrc); | |
7401 | ADVANCE_LP_RING(); | |
7402 | out: | |
7403 | return ret; | |
7404 | } | |
7405 | ||
7406 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7407 | struct drm_crtc *crtc, | |
7408 | struct drm_framebuffer *fb, | |
7409 | struct drm_i915_gem_object *obj) | |
7410 | { | |
7411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7413 | uint32_t pf, pipesrc; | |
7414 | int ret; | |
7415 | ||
7416 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7417 | if (ret) | |
7418 | goto out; | |
7419 | ||
7420 | ret = BEGIN_LP_RING(4); | |
7421 | if (ret) | |
7422 | goto out; | |
7423 | ||
7424 | OUT_RING(MI_DISPLAY_FLIP | | |
7425 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7426 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
8c9f3aaf JB |
7427 | OUT_RING(obj->gtt_offset); |
7428 | ||
7429 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7430 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7431 | OUT_RING(pf | pipesrc); | |
7432 | ADVANCE_LP_RING(); | |
7433 | out: | |
7434 | return ret; | |
7435 | } | |
7436 | ||
7c9017e5 JB |
7437 | /* |
7438 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7439 | * the render ring doesn't give us interrpts for page flip completion, which | |
7440 | * means clients will hang after the first flip is queued. Fortunately the | |
7441 | * blit ring generates interrupts properly, so use it instead. | |
7442 | */ | |
7443 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7444 | struct drm_crtc *crtc, | |
7445 | struct drm_framebuffer *fb, | |
7446 | struct drm_i915_gem_object *obj) | |
7447 | { | |
7448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7450 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7451 | int ret; | |
7452 | ||
7453 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7454 | if (ret) | |
7455 | goto out; | |
7456 | ||
7457 | ret = intel_ring_begin(ring, 4); | |
7458 | if (ret) | |
7459 | goto out; | |
7460 | ||
7461 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
01f2c773 | 7462 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7c9017e5 JB |
7463 | intel_ring_emit(ring, (obj->gtt_offset)); |
7464 | intel_ring_emit(ring, (MI_NOOP)); | |
7465 | intel_ring_advance(ring); | |
7466 | out: | |
7467 | return ret; | |
7468 | } | |
7469 | ||
8c9f3aaf JB |
7470 | static int intel_default_queue_flip(struct drm_device *dev, |
7471 | struct drm_crtc *crtc, | |
7472 | struct drm_framebuffer *fb, | |
7473 | struct drm_i915_gem_object *obj) | |
7474 | { | |
7475 | return -ENODEV; | |
7476 | } | |
7477 | ||
6b95a207 KH |
7478 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7479 | struct drm_framebuffer *fb, | |
7480 | struct drm_pending_vblank_event *event) | |
7481 | { | |
7482 | struct drm_device *dev = crtc->dev; | |
7483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7484 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7485 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7487 | struct intel_unpin_work *work; | |
8c9f3aaf | 7488 | unsigned long flags; |
52e68630 | 7489 | int ret; |
6b95a207 KH |
7490 | |
7491 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7492 | if (work == NULL) | |
7493 | return -ENOMEM; | |
7494 | ||
6b95a207 KH |
7495 | work->event = event; |
7496 | work->dev = crtc->dev; | |
7497 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7498 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7499 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7500 | ||
7317c75e JB |
7501 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7502 | if (ret) | |
7503 | goto free_work; | |
7504 | ||
6b95a207 KH |
7505 | /* We borrow the event spin lock for protecting unpin_work */ |
7506 | spin_lock_irqsave(&dev->event_lock, flags); | |
7507 | if (intel_crtc->unpin_work) { | |
7508 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7509 | kfree(work); | |
7317c75e | 7510 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7511 | |
7512 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7513 | return -EBUSY; |
7514 | } | |
7515 | intel_crtc->unpin_work = work; | |
7516 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7517 | ||
7518 | intel_fb = to_intel_framebuffer(fb); | |
7519 | obj = intel_fb->obj; | |
7520 | ||
468f0b44 | 7521 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7522 | |
75dfca80 | 7523 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7524 | drm_gem_object_reference(&work->old_fb_obj->base); |
7525 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7526 | |
7527 | crtc->fb = fb; | |
96b099fd | 7528 | |
e1f99ce6 | 7529 | work->pending_flip_obj = obj; |
e1f99ce6 | 7530 | |
4e5359cd SF |
7531 | work->enable_stall_check = true; |
7532 | ||
e1f99ce6 CW |
7533 | /* Block clients from rendering to the new back buffer until |
7534 | * the flip occurs and the object is no longer visible. | |
7535 | */ | |
05394f39 | 7536 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7537 | |
8c9f3aaf JB |
7538 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7539 | if (ret) | |
7540 | goto cleanup_pending; | |
6b95a207 | 7541 | |
7782de3b | 7542 | intel_disable_fbc(dev); |
6b95a207 KH |
7543 | mutex_unlock(&dev->struct_mutex); |
7544 | ||
e5510fac JB |
7545 | trace_i915_flip_request(intel_crtc->plane, obj); |
7546 | ||
6b95a207 | 7547 | return 0; |
96b099fd | 7548 | |
8c9f3aaf JB |
7549 | cleanup_pending: |
7550 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
7551 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7552 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7553 | mutex_unlock(&dev->struct_mutex); |
7554 | ||
7555 | spin_lock_irqsave(&dev->event_lock, flags); | |
7556 | intel_crtc->unpin_work = NULL; | |
7557 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7558 | ||
7317c75e JB |
7559 | drm_vblank_put(dev, intel_crtc->pipe); |
7560 | free_work: | |
96b099fd CW |
7561 | kfree(work); |
7562 | ||
7563 | return ret; | |
6b95a207 KH |
7564 | } |
7565 | ||
47f1c6c9 CW |
7566 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7567 | int pipe, int plane) | |
7568 | { | |
7569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7570 | u32 reg, val; | |
7571 | ||
7572 | if (HAS_PCH_SPLIT(dev)) | |
7573 | return; | |
7574 | ||
7575 | /* Who knows what state these registers were left in by the BIOS or | |
7576 | * grub? | |
7577 | * | |
7578 | * If we leave the registers in a conflicting state (e.g. with the | |
7579 | * display plane reading from the other pipe than the one we intend | |
7580 | * to use) then when we attempt to teardown the active mode, we will | |
7581 | * not disable the pipes and planes in the correct order -- leaving | |
7582 | * a plane reading from a disabled pipe and possibly leading to | |
7583 | * undefined behaviour. | |
7584 | */ | |
7585 | ||
7586 | reg = DSPCNTR(plane); | |
7587 | val = I915_READ(reg); | |
7588 | ||
7589 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7590 | return; | |
7591 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7592 | return; | |
7593 | ||
7594 | /* This display plane is active and attached to the other CPU pipe. */ | |
7595 | pipe = !pipe; | |
7596 | ||
7597 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7598 | intel_disable_plane(dev_priv, plane, pipe); |
7599 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7600 | } |
79e53945 | 7601 | |
f6e5b160 CW |
7602 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7603 | { | |
7604 | struct drm_device *dev = crtc->dev; | |
7605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7606 | ||
7607 | /* Reset flags back to the 'unknown' status so that they | |
7608 | * will be correctly set on the initial modeset. | |
7609 | */ | |
7610 | intel_crtc->dpms_mode = -1; | |
7611 | ||
7612 | /* We need to fix up any BIOS configuration that conflicts with | |
7613 | * our expectations. | |
7614 | */ | |
7615 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7616 | } | |
7617 | ||
7618 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7619 | .dpms = intel_crtc_dpms, | |
7620 | .mode_fixup = intel_crtc_mode_fixup, | |
7621 | .mode_set = intel_crtc_mode_set, | |
7622 | .mode_set_base = intel_pipe_set_base, | |
7623 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7624 | .load_lut = intel_crtc_load_lut, | |
7625 | .disable = intel_crtc_disable, | |
7626 | }; | |
7627 | ||
7628 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7629 | .reset = intel_crtc_reset, | |
7630 | .cursor_set = intel_crtc_cursor_set, | |
7631 | .cursor_move = intel_crtc_cursor_move, | |
7632 | .gamma_set = intel_crtc_gamma_set, | |
7633 | .set_config = drm_crtc_helper_set_config, | |
7634 | .destroy = intel_crtc_destroy, | |
7635 | .page_flip = intel_crtc_page_flip, | |
7636 | }; | |
7637 | ||
b358d0a6 | 7638 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7639 | { |
22fd0fab | 7640 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7641 | struct intel_crtc *intel_crtc; |
7642 | int i; | |
7643 | ||
7644 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7645 | if (intel_crtc == NULL) | |
7646 | return; | |
7647 | ||
7648 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7649 | ||
7650 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7651 | for (i = 0; i < 256; i++) { |
7652 | intel_crtc->lut_r[i] = i; | |
7653 | intel_crtc->lut_g[i] = i; | |
7654 | intel_crtc->lut_b[i] = i; | |
7655 | } | |
7656 | ||
80824003 JB |
7657 | /* Swap pipes & planes for FBC on pre-965 */ |
7658 | intel_crtc->pipe = pipe; | |
7659 | intel_crtc->plane = pipe; | |
e2e767ab | 7660 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7661 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7662 | intel_crtc->plane = !pipe; |
80824003 JB |
7663 | } |
7664 | ||
22fd0fab JB |
7665 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7666 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7667 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7668 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7669 | ||
5d1d0cc8 | 7670 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7671 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 7672 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
7673 | |
7674 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
7675 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
7676 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
7677 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
7678 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7679 | } else { | |
7680 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7681 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7682 | } | |
7683 | ||
79e53945 JB |
7684 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7685 | ||
652c393a JB |
7686 | intel_crtc->busy = false; |
7687 | ||
7688 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7689 | (unsigned long)intel_crtc); | |
79e53945 JB |
7690 | } |
7691 | ||
08d7b3d1 | 7692 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7693 | struct drm_file *file) |
08d7b3d1 CW |
7694 | { |
7695 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7696 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7697 | struct drm_mode_object *drmmode_obj; |
7698 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7699 | |
7700 | if (!dev_priv) { | |
7701 | DRM_ERROR("called with no initialization\n"); | |
7702 | return -EINVAL; | |
7703 | } | |
7704 | ||
c05422d5 DV |
7705 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7706 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7707 | |
c05422d5 | 7708 | if (!drmmode_obj) { |
08d7b3d1 CW |
7709 | DRM_ERROR("no such CRTC id\n"); |
7710 | return -EINVAL; | |
7711 | } | |
7712 | ||
c05422d5 DV |
7713 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7714 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7715 | |
c05422d5 | 7716 | return 0; |
08d7b3d1 CW |
7717 | } |
7718 | ||
c5e4df33 | 7719 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7720 | { |
4ef69c7a | 7721 | struct intel_encoder *encoder; |
79e53945 | 7722 | int index_mask = 0; |
79e53945 JB |
7723 | int entry = 0; |
7724 | ||
4ef69c7a CW |
7725 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7726 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7727 | index_mask |= (1 << entry); |
7728 | entry++; | |
7729 | } | |
4ef69c7a | 7730 | |
79e53945 JB |
7731 | return index_mask; |
7732 | } | |
7733 | ||
4d302442 CW |
7734 | static bool has_edp_a(struct drm_device *dev) |
7735 | { | |
7736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7737 | ||
7738 | if (!IS_MOBILE(dev)) | |
7739 | return false; | |
7740 | ||
7741 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7742 | return false; | |
7743 | ||
7744 | if (IS_GEN5(dev) && | |
7745 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7746 | return false; | |
7747 | ||
7748 | return true; | |
7749 | } | |
7750 | ||
79e53945 JB |
7751 | static void intel_setup_outputs(struct drm_device *dev) |
7752 | { | |
725e30ad | 7753 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7754 | struct intel_encoder *encoder; |
cb0953d7 | 7755 | bool dpd_is_edp = false; |
c5d1b51d | 7756 | bool has_lvds = false; |
79e53945 | 7757 | |
541998a1 | 7758 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
7759 | has_lvds = intel_lvds_init(dev); |
7760 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
7761 | /* disable the panel fitter on everything but LVDS */ | |
7762 | I915_WRITE(PFIT_CONTROL, 0); | |
7763 | } | |
79e53945 | 7764 | |
bad720ff | 7765 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7766 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7767 | |
4d302442 | 7768 | if (has_edp_a(dev)) |
32f9d658 ZW |
7769 | intel_dp_init(dev, DP_A); |
7770 | ||
cb0953d7 AJ |
7771 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7772 | intel_dp_init(dev, PCH_DP_D); | |
7773 | } | |
7774 | ||
7775 | intel_crt_init(dev); | |
7776 | ||
7777 | if (HAS_PCH_SPLIT(dev)) { | |
7778 | int found; | |
7779 | ||
30ad48b7 | 7780 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
7781 | /* PCH SDVOB multiplex with HDMIB */ |
7782 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
7783 | if (!found) |
7784 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7785 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7786 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7787 | } |
7788 | ||
7789 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7790 | intel_hdmi_init(dev, HDMIC); | |
7791 | ||
7792 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7793 | intel_hdmi_init(dev, HDMID); | |
7794 | ||
5eb08b69 ZW |
7795 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7796 | intel_dp_init(dev, PCH_DP_C); | |
7797 | ||
cb0953d7 | 7798 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7799 | intel_dp_init(dev, PCH_DP_D); |
7800 | ||
103a196f | 7801 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7802 | bool found = false; |
7d57382e | 7803 | |
725e30ad | 7804 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7805 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 7806 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
7807 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7808 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7809 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7810 | } |
27185ae1 | 7811 | |
b01f2c3a JB |
7812 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7813 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7814 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7815 | } |
725e30ad | 7816 | } |
13520b05 KH |
7817 | |
7818 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7819 | |
b01f2c3a JB |
7820 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7821 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 7822 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 7823 | } |
27185ae1 ML |
7824 | |
7825 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7826 | ||
b01f2c3a JB |
7827 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7828 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7829 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7830 | } |
7831 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7832 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7833 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7834 | } |
725e30ad | 7835 | } |
27185ae1 | 7836 | |
b01f2c3a JB |
7837 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7838 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7839 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7840 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7841 | } |
bad720ff | 7842 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7843 | intel_dvo_init(dev); |
7844 | ||
103a196f | 7845 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7846 | intel_tv_init(dev); |
7847 | ||
4ef69c7a CW |
7848 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7849 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7850 | encoder->base.possible_clones = | |
7851 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7852 | } |
47356eb6 | 7853 | |
2c7111db CW |
7854 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
7855 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
7856 | |
7857 | if (HAS_PCH_SPLIT(dev)) | |
7858 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
7859 | } |
7860 | ||
7861 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7862 | { | |
7863 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7864 | |
7865 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7866 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7867 | |
7868 | kfree(intel_fb); | |
7869 | } | |
7870 | ||
7871 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7872 | struct drm_file *file, |
79e53945 JB |
7873 | unsigned int *handle) |
7874 | { | |
7875 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7876 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7877 | |
05394f39 | 7878 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7879 | } |
7880 | ||
7881 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7882 | .destroy = intel_user_framebuffer_destroy, | |
7883 | .create_handle = intel_user_framebuffer_create_handle, | |
7884 | }; | |
7885 | ||
38651674 DA |
7886 | int intel_framebuffer_init(struct drm_device *dev, |
7887 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 7888 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 7889 | struct drm_i915_gem_object *obj) |
79e53945 | 7890 | { |
79e53945 JB |
7891 | int ret; |
7892 | ||
05394f39 | 7893 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7894 | return -EINVAL; |
7895 | ||
308e5bcb | 7896 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
7897 | return -EINVAL; |
7898 | ||
308e5bcb | 7899 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
7900 | case DRM_FORMAT_RGB332: |
7901 | case DRM_FORMAT_RGB565: | |
7902 | case DRM_FORMAT_XRGB8888: | |
7903 | case DRM_FORMAT_ARGB8888: | |
7904 | case DRM_FORMAT_XRGB2101010: | |
7905 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 7906 | /* RGB formats are common across chipsets */ |
b5626747 | 7907 | break; |
04b3924d VS |
7908 | case DRM_FORMAT_YUYV: |
7909 | case DRM_FORMAT_UYVY: | |
7910 | case DRM_FORMAT_YVYU: | |
7911 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
7912 | break; |
7913 | default: | |
aca25848 ED |
7914 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7915 | mode_cmd->pixel_format); | |
57cd6508 CW |
7916 | return -EINVAL; |
7917 | } | |
7918 | ||
79e53945 JB |
7919 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7920 | if (ret) { | |
7921 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7922 | return ret; | |
7923 | } | |
7924 | ||
7925 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7926 | intel_fb->obj = obj; |
79e53945 JB |
7927 | return 0; |
7928 | } | |
7929 | ||
79e53945 JB |
7930 | static struct drm_framebuffer * |
7931 | intel_user_framebuffer_create(struct drm_device *dev, | |
7932 | struct drm_file *filp, | |
308e5bcb | 7933 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 7934 | { |
05394f39 | 7935 | struct drm_i915_gem_object *obj; |
79e53945 | 7936 | |
308e5bcb JB |
7937 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
7938 | mode_cmd->handles[0])); | |
c8725226 | 7939 | if (&obj->base == NULL) |
cce13ff7 | 7940 | return ERR_PTR(-ENOENT); |
79e53945 | 7941 | |
d2dff872 | 7942 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7943 | } |
7944 | ||
79e53945 | 7945 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7946 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7947 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7948 | }; |
7949 | ||
05394f39 | 7950 | static struct drm_i915_gem_object * |
aa40d6bb | 7951 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7952 | { |
05394f39 | 7953 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7954 | int ret; |
7955 | ||
2c34b850 BW |
7956 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
7957 | ||
aa40d6bb ZN |
7958 | ctx = i915_gem_alloc_object(dev, 4096); |
7959 | if (!ctx) { | |
9ea8d059 CW |
7960 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7961 | return NULL; | |
7962 | } | |
7963 | ||
75e9e915 | 7964 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7965 | if (ret) { |
7966 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7967 | goto err_unref; | |
7968 | } | |
7969 | ||
aa40d6bb | 7970 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
7971 | if (ret) { |
7972 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
7973 | goto err_unpin; | |
7974 | } | |
9ea8d059 | 7975 | |
aa40d6bb | 7976 | return ctx; |
9ea8d059 CW |
7977 | |
7978 | err_unpin: | |
aa40d6bb | 7979 | i915_gem_object_unpin(ctx); |
9ea8d059 | 7980 | err_unref: |
05394f39 | 7981 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
7982 | mutex_unlock(&dev->struct_mutex); |
7983 | return NULL; | |
7984 | } | |
7985 | ||
7648fa99 JB |
7986 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
7987 | { | |
7988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7989 | u16 rgvswctl; | |
7990 | ||
7991 | rgvswctl = I915_READ16(MEMSWCTL); | |
7992 | if (rgvswctl & MEMCTL_CMD_STS) { | |
7993 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
7994 | return false; /* still busy with another command */ | |
7995 | } | |
7996 | ||
7997 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
7998 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
7999 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8000 | POSTING_READ16(MEMSWCTL); | |
8001 | ||
8002 | rgvswctl |= MEMCTL_CMD_STS; | |
8003 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8004 | ||
8005 | return true; | |
8006 | } | |
8007 | ||
f97108d1 JB |
8008 | void ironlake_enable_drps(struct drm_device *dev) |
8009 | { | |
8010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8011 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 8012 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 8013 | |
ea056c14 JB |
8014 | /* Enable temp reporting */ |
8015 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
8016 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
8017 | ||
f97108d1 JB |
8018 | /* 100ms RC evaluation intervals */ |
8019 | I915_WRITE(RCUPEI, 100000); | |
8020 | I915_WRITE(RCDNEI, 100000); | |
8021 | ||
8022 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
8023 | I915_WRITE(RCBMAXAVG, 90000); | |
8024 | I915_WRITE(RCBMINAVG, 80000); | |
8025 | ||
8026 | I915_WRITE(MEMIHYST, 1); | |
8027 | ||
8028 | /* Set up min, max, and cur for interrupt handling */ | |
8029 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
8030 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
8031 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
8032 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 8033 | |
f97108d1 JB |
8034 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
8035 | PXVFREQ_PX_SHIFT; | |
8036 | ||
80dbf4b7 | 8037 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
8038 | dev_priv->fstart = fstart; |
8039 | ||
80dbf4b7 | 8040 | dev_priv->max_delay = fstart; |
f97108d1 JB |
8041 | dev_priv->min_delay = fmin; |
8042 | dev_priv->cur_delay = fstart; | |
8043 | ||
80dbf4b7 JB |
8044 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
8045 | fmax, fmin, fstart); | |
7648fa99 | 8046 | |
f97108d1 JB |
8047 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
8048 | ||
8049 | /* | |
8050 | * Interrupts will be enabled in ironlake_irq_postinstall | |
8051 | */ | |
8052 | ||
8053 | I915_WRITE(VIDSTART, vstart); | |
8054 | POSTING_READ(VIDSTART); | |
8055 | ||
8056 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
8057 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
8058 | ||
481b6af3 | 8059 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 8060 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
8061 | msleep(1); |
8062 | ||
7648fa99 | 8063 | ironlake_set_drps(dev, fstart); |
f97108d1 | 8064 | |
7648fa99 JB |
8065 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
8066 | I915_READ(0x112e0); | |
8067 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
8068 | dev_priv->last_count2 = I915_READ(0x112f4); | |
8069 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
8070 | } |
8071 | ||
8072 | void ironlake_disable_drps(struct drm_device *dev) | |
8073 | { | |
8074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8075 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
8076 | |
8077 | /* Ack interrupts, disable EFC interrupt */ | |
8078 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
8079 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
8080 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
8081 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
8082 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
8083 | ||
8084 | /* Go back to the starting frequency */ | |
7648fa99 | 8085 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
8086 | msleep(1); |
8087 | rgvswctl |= MEMCTL_CMD_STS; | |
8088 | I915_WRITE(MEMSWCTL, rgvswctl); | |
8089 | msleep(1); | |
8090 | ||
8091 | } | |
8092 | ||
3b8d8d91 JB |
8093 | void gen6_set_rps(struct drm_device *dev, u8 val) |
8094 | { | |
8095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8096 | u32 swreq; | |
8097 | ||
8098 | swreq = (val & 0x3ff) << 25; | |
8099 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
8100 | } | |
8101 | ||
8102 | void gen6_disable_rps(struct drm_device *dev) | |
8103 | { | |
8104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8105 | ||
8106 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
8107 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
8108 | I915_WRITE(GEN6_PMIER, 0); | |
6fdd4d98 DV |
8109 | /* Complete PM interrupt masking here doesn't race with the rps work |
8110 | * item again unmasking PM interrupts because that is using a different | |
8111 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
8112 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4912d041 BW |
8113 | |
8114 | spin_lock_irq(&dev_priv->rps_lock); | |
8115 | dev_priv->pm_iir = 0; | |
8116 | spin_unlock_irq(&dev_priv->rps_lock); | |
8117 | ||
3b8d8d91 JB |
8118 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
8119 | } | |
8120 | ||
7648fa99 JB |
8121 | static unsigned long intel_pxfreq(u32 vidfreq) |
8122 | { | |
8123 | unsigned long freq; | |
8124 | int div = (vidfreq & 0x3f0000) >> 16; | |
8125 | int post = (vidfreq & 0x3000) >> 12; | |
8126 | int pre = (vidfreq & 0x7); | |
8127 | ||
8128 | if (!pre) | |
8129 | return 0; | |
8130 | ||
8131 | freq = ((div * 133333) / ((1<<post) * pre)); | |
8132 | ||
8133 | return freq; | |
8134 | } | |
8135 | ||
8136 | void intel_init_emon(struct drm_device *dev) | |
8137 | { | |
8138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8139 | u32 lcfuse; | |
8140 | u8 pxw[16]; | |
8141 | int i; | |
8142 | ||
8143 | /* Disable to program */ | |
8144 | I915_WRITE(ECR, 0); | |
8145 | POSTING_READ(ECR); | |
8146 | ||
8147 | /* Program energy weights for various events */ | |
8148 | I915_WRITE(SDEW, 0x15040d00); | |
8149 | I915_WRITE(CSIEW0, 0x007f0000); | |
8150 | I915_WRITE(CSIEW1, 0x1e220004); | |
8151 | I915_WRITE(CSIEW2, 0x04000004); | |
8152 | ||
8153 | for (i = 0; i < 5; i++) | |
8154 | I915_WRITE(PEW + (i * 4), 0); | |
8155 | for (i = 0; i < 3; i++) | |
8156 | I915_WRITE(DEW + (i * 4), 0); | |
8157 | ||
8158 | /* Program P-state weights to account for frequency power adjustment */ | |
8159 | for (i = 0; i < 16; i++) { | |
8160 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
8161 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
8162 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
8163 | PXVFREQ_PX_SHIFT; | |
8164 | unsigned long val; | |
8165 | ||
8166 | val = vid * vid; | |
8167 | val *= (freq / 1000); | |
8168 | val *= 255; | |
8169 | val /= (127*127*900); | |
8170 | if (val > 0xff) | |
8171 | DRM_ERROR("bad pxval: %ld\n", val); | |
8172 | pxw[i] = val; | |
8173 | } | |
8174 | /* Render standby states get 0 weight */ | |
8175 | pxw[14] = 0; | |
8176 | pxw[15] = 0; | |
8177 | ||
8178 | for (i = 0; i < 4; i++) { | |
8179 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
8180 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
8181 | I915_WRITE(PXW + (i * 4), val); | |
8182 | } | |
8183 | ||
8184 | /* Adjust magic regs to magic values (more experimental results) */ | |
8185 | I915_WRITE(OGW0, 0); | |
8186 | I915_WRITE(OGW1, 0); | |
8187 | I915_WRITE(EG0, 0x00007f00); | |
8188 | I915_WRITE(EG1, 0x0000000e); | |
8189 | I915_WRITE(EG2, 0x000e0000); | |
8190 | I915_WRITE(EG3, 0x68000300); | |
8191 | I915_WRITE(EG4, 0x42000000); | |
8192 | I915_WRITE(EG5, 0x00140031); | |
8193 | I915_WRITE(EG6, 0); | |
8194 | I915_WRITE(EG7, 0); | |
8195 | ||
8196 | for (i = 0; i < 8; i++) | |
8197 | I915_WRITE(PXWL + (i * 4), 0); | |
8198 | ||
8199 | /* Enable PMON + select events */ | |
8200 | I915_WRITE(ECR, 0x80000019); | |
8201 | ||
8202 | lcfuse = I915_READ(LCFUSE02); | |
8203 | ||
8204 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
8205 | } | |
8206 | ||
c0f372b3 KP |
8207 | static bool intel_enable_rc6(struct drm_device *dev) |
8208 | { | |
8209 | /* | |
8210 | * Respect the kernel parameter if it is set | |
8211 | */ | |
8212 | if (i915_enable_rc6 >= 0) | |
8213 | return i915_enable_rc6; | |
8214 | ||
8215 | /* | |
8216 | * Disable RC6 on Ironlake | |
8217 | */ | |
8218 | if (INTEL_INFO(dev)->gen == 5) | |
8219 | return 0; | |
8220 | ||
8221 | /* | |
371de6e4 | 8222 | * Disable rc6 on Sandybridge |
c0f372b3 KP |
8223 | */ |
8224 | if (INTEL_INFO(dev)->gen == 6) { | |
371de6e4 KP |
8225 | DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n"); |
8226 | return 0; | |
c0f372b3 KP |
8227 | } |
8228 | DRM_DEBUG_DRIVER("RC6 enabled\n"); | |
8229 | return 1; | |
8230 | } | |
8231 | ||
3b8d8d91 | 8232 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 8233 | { |
a6044e23 JB |
8234 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
8235 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 8236 | u32 pcu_mbox, rc6_mask = 0; |
a6044e23 | 8237 | int cur_freq, min_freq, max_freq; |
8fd26859 CW |
8238 | int i; |
8239 | ||
8240 | /* Here begins a magic sequence of register writes to enable | |
8241 | * auto-downclocking. | |
8242 | * | |
8243 | * Perhaps there might be some value in exposing these to | |
8244 | * userspace... | |
8245 | */ | |
8246 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 8247 | mutex_lock(&dev_priv->dev->struct_mutex); |
fcca7926 | 8248 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 8249 | |
3b8d8d91 | 8250 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
8251 | I915_WRITE(GEN6_RC_CONTROL, 0); |
8252 | ||
8253 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
8254 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
8255 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
8256 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
8257 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
8258 | ||
8259 | for (i = 0; i < I915_NUM_RINGS; i++) | |
8260 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
8261 | ||
8262 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
8263 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
8264 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
8265 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
8266 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
8267 | ||
c0f372b3 | 8268 | if (intel_enable_rc6(dev_priv->dev)) |
7df8721b JB |
8269 | rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | |
8270 | GEN6_RC_CTL_RC6_ENABLE; | |
8271 | ||
8fd26859 | 8272 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 8273 | rc6_mask | |
9c3d2f7f | 8274 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
8275 | GEN6_RC_CTL_HW_ENABLE); |
8276 | ||
3b8d8d91 | 8277 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
8278 | GEN6_FREQUENCY(10) | |
8279 | GEN6_OFFSET(0) | | |
8280 | GEN6_AGGRESSIVE_TURBO); | |
8281 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
8282 | GEN6_FREQUENCY(12)); | |
8283 | ||
8284 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
8285 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
8286 | 18 << 24 | | |
8287 | 6 << 16); | |
ccab5c82 JB |
8288 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
8289 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 8290 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 8291 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
8292 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
8293 | I915_WRITE(GEN6_RP_CONTROL, | |
8294 | GEN6_RP_MEDIA_TURBO | | |
6ed55ee7 | 8295 | GEN6_RP_MEDIA_HW_MODE | |
8fd26859 CW |
8296 | GEN6_RP_MEDIA_IS_GFX | |
8297 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
8298 | GEN6_RP_UP_BUSY_AVG | |
8299 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
8300 | |
8301 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8302 | 500)) | |
8303 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8304 | ||
8305 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
8306 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
8307 | GEN6_PCODE_READY | | |
8308 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8309 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8310 | 500)) | |
8311 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8312 | ||
a6044e23 JB |
8313 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
8314 | max_freq = rp_state_cap & 0xff; | |
8315 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
8316 | ||
8317 | /* Check for overclock support */ | |
8318 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8319 | 500)) | |
8320 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8321 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
8322 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
8323 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8324 | 500)) | |
8325 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8326 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
8327 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 8328 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
8329 | } |
8330 | ||
8331 | /* In units of 100MHz */ | |
8332 | dev_priv->max_delay = max_freq; | |
8333 | dev_priv->min_delay = min_freq; | |
8334 | dev_priv->cur_delay = cur_freq; | |
8335 | ||
8fd26859 CW |
8336 | /* requires MSI enabled */ |
8337 | I915_WRITE(GEN6_PMIER, | |
8338 | GEN6_PM_MBOX_EVENT | | |
8339 | GEN6_PM_THERMAL_EVENT | | |
8340 | GEN6_PM_RP_DOWN_TIMEOUT | | |
8341 | GEN6_PM_RP_UP_THRESHOLD | | |
8342 | GEN6_PM_RP_DOWN_THRESHOLD | | |
8343 | GEN6_PM_RP_UP_EI_EXPIRED | | |
8344 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
8345 | spin_lock_irq(&dev_priv->rps_lock); |
8346 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 8347 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 8348 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
8349 | /* enable all PM interrupts */ |
8350 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 8351 | |
fcca7926 | 8352 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 8353 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
8354 | } |
8355 | ||
23b2f8bb JB |
8356 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
8357 | { | |
8358 | int min_freq = 15; | |
8359 | int gpu_freq, ia_freq, max_ia_freq; | |
8360 | int scaling_factor = 180; | |
8361 | ||
8362 | max_ia_freq = cpufreq_quick_get_max(0); | |
8363 | /* | |
8364 | * Default to measured freq if none found, PCU will ensure we don't go | |
8365 | * over | |
8366 | */ | |
8367 | if (!max_ia_freq) | |
8368 | max_ia_freq = tsc_khz; | |
8369 | ||
8370 | /* Convert from kHz to MHz */ | |
8371 | max_ia_freq /= 1000; | |
8372 | ||
8373 | mutex_lock(&dev_priv->dev->struct_mutex); | |
8374 | ||
8375 | /* | |
8376 | * For each potential GPU frequency, load a ring frequency we'd like | |
8377 | * to use for memory access. We do this by specifying the IA frequency | |
8378 | * the PCU should use as a reference to determine the ring frequency. | |
8379 | */ | |
8380 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
8381 | gpu_freq--) { | |
8382 | int diff = dev_priv->max_delay - gpu_freq; | |
8383 | ||
8384 | /* | |
8385 | * For GPU frequencies less than 750MHz, just use the lowest | |
8386 | * ring freq. | |
8387 | */ | |
8388 | if (gpu_freq < min_freq) | |
8389 | ia_freq = 800; | |
8390 | else | |
8391 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
8392 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
8393 | ||
8394 | I915_WRITE(GEN6_PCODE_DATA, | |
8395 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
8396 | gpu_freq); | |
8397 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
8398 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8399 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
8400 | GEN6_PCODE_READY) == 0, 10)) { | |
8401 | DRM_ERROR("pcode write of freq table timed out\n"); | |
8402 | continue; | |
8403 | } | |
8404 | } | |
8405 | ||
8406 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
8407 | } | |
8408 | ||
6067aaea JB |
8409 | static void ironlake_init_clock_gating(struct drm_device *dev) |
8410 | { | |
8411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8412 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8413 | ||
8414 | /* Required for FBC */ | |
8415 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
8416 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
8417 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8418 | /* Required for CxSR */ | |
8419 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
8420 | ||
8421 | I915_WRITE(PCH_3DCGDIS0, | |
8422 | MARIUNIT_CLOCK_GATE_DISABLE | | |
8423 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
8424 | I915_WRITE(PCH_3DCGDIS1, | |
8425 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8426 | ||
8427 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8428 | ||
6067aaea JB |
8429 | /* |
8430 | * According to the spec the following bits should be set in | |
8431 | * order to enable memory self-refresh | |
8432 | * The bit 22/21 of 0x42004 | |
8433 | * The bit 5 of 0x42020 | |
8434 | * The bit 15 of 0x45000 | |
8435 | */ | |
8436 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8437 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8438 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
8439 | I915_WRITE(ILK_DSPCLK_GATE, | |
8440 | (I915_READ(ILK_DSPCLK_GATE) | | |
8441 | ILK_DPARB_CLK_GATE)); | |
8442 | I915_WRITE(DISP_ARB_CTL, | |
8443 | (I915_READ(DISP_ARB_CTL) | | |
8444 | DISP_FBC_WM_DIS)); | |
8445 | I915_WRITE(WM3_LP_ILK, 0); | |
8446 | I915_WRITE(WM2_LP_ILK, 0); | |
8447 | I915_WRITE(WM1_LP_ILK, 0); | |
8448 | ||
8449 | /* | |
8450 | * Based on the document from hardware guys the following bits | |
8451 | * should be set unconditionally in order to enable FBC. | |
8452 | * The bit 22 of 0x42000 | |
8453 | * The bit 22 of 0x42004 | |
8454 | * The bit 7,8,9 of 0x42020. | |
8455 | */ | |
8456 | if (IS_IRONLAKE_M(dev)) { | |
8457 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8458 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8459 | ILK_FBCQ_DIS); | |
8460 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8461 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8462 | ILK_DPARB_GATE); | |
8463 | I915_WRITE(ILK_DSPCLK_GATE, | |
8464 | I915_READ(ILK_DSPCLK_GATE) | | |
8465 | ILK_DPFC_DIS1 | | |
8466 | ILK_DPFC_DIS2 | | |
8467 | ILK_CLK_FBC); | |
8468 | } | |
8469 | ||
8470 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8471 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8472 | ILK_ELPIN_409_SELECT); | |
8473 | I915_WRITE(_3D_CHICKEN2, | |
8474 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8475 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
8476 | } |
8477 | ||
6067aaea | 8478 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8479 | { |
8480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8481 | int pipe; |
6067aaea JB |
8482 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8483 | ||
8484 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8485 | |
6067aaea JB |
8486 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8487 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8488 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8489 | |
6067aaea JB |
8490 | I915_WRITE(WM3_LP_ILK, 0); |
8491 | I915_WRITE(WM2_LP_ILK, 0); | |
8492 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a | 8493 | |
406478dc EA |
8494 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
8495 | * gating disable must be set. Failure to set it results in | |
8496 | * flickering pixels due to Z write ordering failures after | |
8497 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
8498 | * Sanctuary and Tropics, and apparently anything else with | |
8499 | * alpha test or pixel discard. | |
9ca1d10d EA |
8500 | * |
8501 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
8502 | * but we didn't debug actual testcases to find it out. | |
406478dc | 8503 | */ |
9ca1d10d EA |
8504 | I915_WRITE(GEN6_UCGCTL2, |
8505 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
8506 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
406478dc | 8507 | |
652c393a | 8508 | /* |
6067aaea JB |
8509 | * According to the spec the following bits should be |
8510 | * set in order to enable memory self-refresh and fbc: | |
8511 | * The bit21 and bit22 of 0x42000 | |
8512 | * The bit21 and bit22 of 0x42004 | |
8513 | * The bit5 and bit7 of 0x42020 | |
8514 | * The bit14 of 0x70180 | |
8515 | * The bit14 of 0x71180 | |
652c393a | 8516 | */ |
6067aaea JB |
8517 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8518 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8519 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8520 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8521 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8522 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8523 | I915_WRITE(ILK_DSPCLK_GATE, | |
8524 | I915_READ(ILK_DSPCLK_GATE) | | |
8525 | ILK_DPARB_CLK_GATE | | |
8526 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8527 | |
d74362c9 | 8528 | for_each_pipe(pipe) { |
6067aaea JB |
8529 | I915_WRITE(DSPCNTR(pipe), |
8530 | I915_READ(DSPCNTR(pipe)) | | |
8531 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8532 | intel_flush_display_plane(dev_priv, pipe); |
8533 | } | |
6067aaea | 8534 | } |
8956c8bb | 8535 | |
28963a3e JB |
8536 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8537 | { | |
8538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8539 | int pipe; | |
8540 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8541 | |
28963a3e | 8542 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8543 | |
28963a3e JB |
8544 | I915_WRITE(WM3_LP_ILK, 0); |
8545 | I915_WRITE(WM2_LP_ILK, 0); | |
8546 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8547 | |
28963a3e | 8548 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8549 | |
116ac8d2 EA |
8550 | I915_WRITE(IVB_CHICKEN3, |
8551 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8552 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8553 | ||
d74362c9 | 8554 | for_each_pipe(pipe) { |
28963a3e JB |
8555 | I915_WRITE(DSPCNTR(pipe), |
8556 | I915_READ(DSPCNTR(pipe)) | | |
8557 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8558 | intel_flush_display_plane(dev_priv, pipe); |
8559 | } | |
28963a3e JB |
8560 | } |
8561 | ||
6067aaea JB |
8562 | static void g4x_init_clock_gating(struct drm_device *dev) |
8563 | { | |
8564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8565 | uint32_t dspclk_gate; | |
8fd26859 | 8566 | |
6067aaea JB |
8567 | I915_WRITE(RENCLK_GATE_D1, 0); |
8568 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8569 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8570 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8571 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8572 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8573 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8574 | OVCUNIT_CLOCK_GATE_DISABLE; | |
8575 | if (IS_GM45(dev)) | |
8576 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
8577 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
8578 | } | |
1398261a | 8579 | |
6067aaea JB |
8580 | static void crestline_init_clock_gating(struct drm_device *dev) |
8581 | { | |
8582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 8583 | |
6067aaea JB |
8584 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8585 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8586 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8587 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8588 | I915_WRITE16(DEUC, 0); | |
8589 | } | |
652c393a | 8590 | |
6067aaea JB |
8591 | static void broadwater_init_clock_gating(struct drm_device *dev) |
8592 | { | |
8593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8594 | ||
8595 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
8596 | I965_RCC_CLOCK_GATE_DISABLE | | |
8597 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8598 | I965_ISC_CLOCK_GATE_DISABLE | | |
8599 | I965_FBC_CLOCK_GATE_DISABLE); | |
8600 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8601 | } | |
8602 | ||
8603 | static void gen3_init_clock_gating(struct drm_device *dev) | |
8604 | { | |
8605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8606 | u32 dstate = I915_READ(D_STATE); | |
8607 | ||
8608 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8609 | DSTATE_DOT_CLOCK_GATING; | |
8610 | I915_WRITE(D_STATE, dstate); | |
8611 | } | |
8612 | ||
8613 | static void i85x_init_clock_gating(struct drm_device *dev) | |
8614 | { | |
8615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8616 | ||
8617 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
8618 | } | |
8619 | ||
8620 | static void i830_init_clock_gating(struct drm_device *dev) | |
8621 | { | |
8622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8623 | ||
8624 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
8625 | } |
8626 | ||
645c62a5 JB |
8627 | static void ibx_init_clock_gating(struct drm_device *dev) |
8628 | { | |
8629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8630 | ||
8631 | /* | |
8632 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8633 | * gating for the panel power sequencer or it will fail to | |
8634 | * start up when no ports are active. | |
8635 | */ | |
8636 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8637 | } | |
8638 | ||
8639 | static void cpt_init_clock_gating(struct drm_device *dev) | |
8640 | { | |
8641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 8642 | int pipe; |
645c62a5 JB |
8643 | |
8644 | /* | |
8645 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8646 | * gating for the panel power sequencer or it will fail to | |
8647 | * start up when no ports are active. | |
8648 | */ | |
8649 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8650 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
8651 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
8652 | /* Without this, mode sets may fail silently on FDI */ |
8653 | for_each_pipe(pipe) | |
8654 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
8655 | } |
8656 | ||
ac668088 | 8657 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
8658 | { |
8659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8660 | ||
8661 | if (dev_priv->renderctx) { | |
ac668088 CW |
8662 | i915_gem_object_unpin(dev_priv->renderctx); |
8663 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
8664 | dev_priv->renderctx = NULL; |
8665 | } | |
8666 | ||
8667 | if (dev_priv->pwrctx) { | |
ac668088 CW |
8668 | i915_gem_object_unpin(dev_priv->pwrctx); |
8669 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
8670 | dev_priv->pwrctx = NULL; | |
8671 | } | |
8672 | } | |
8673 | ||
8674 | static void ironlake_disable_rc6(struct drm_device *dev) | |
8675 | { | |
8676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8677 | ||
8678 | if (I915_READ(PWRCTXA)) { | |
8679 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
8680 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
8681 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
8682 | 50); | |
0cdab21f CW |
8683 | |
8684 | I915_WRITE(PWRCTXA, 0); | |
8685 | POSTING_READ(PWRCTXA); | |
8686 | ||
ac668088 CW |
8687 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
8688 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 8689 | } |
ac668088 | 8690 | |
99507307 | 8691 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
8692 | } |
8693 | ||
ac668088 | 8694 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
8695 | { |
8696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8697 | ||
ac668088 CW |
8698 | if (dev_priv->renderctx == NULL) |
8699 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
8700 | if (!dev_priv->renderctx) | |
8701 | return -ENOMEM; | |
8702 | ||
8703 | if (dev_priv->pwrctx == NULL) | |
8704 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
8705 | if (!dev_priv->pwrctx) { | |
8706 | ironlake_teardown_rc6(dev); | |
8707 | return -ENOMEM; | |
8708 | } | |
8709 | ||
8710 | return 0; | |
d5bb081b JB |
8711 | } |
8712 | ||
8713 | void ironlake_enable_rc6(struct drm_device *dev) | |
8714 | { | |
8715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8716 | int ret; | |
8717 | ||
ac668088 CW |
8718 | /* rc6 disabled by default due to repeated reports of hanging during |
8719 | * boot and resume. | |
8720 | */ | |
c0f372b3 | 8721 | if (!intel_enable_rc6(dev)) |
ac668088 CW |
8722 | return; |
8723 | ||
2c34b850 | 8724 | mutex_lock(&dev->struct_mutex); |
ac668088 | 8725 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
8726 | if (ret) { |
8727 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 8728 | return; |
2c34b850 | 8729 | } |
ac668088 | 8730 | |
d5bb081b JB |
8731 | /* |
8732 | * GPU can automatically power down the render unit if given a page | |
8733 | * to save state. | |
8734 | */ | |
8735 | ret = BEGIN_LP_RING(6); | |
8736 | if (ret) { | |
ac668088 | 8737 | ironlake_teardown_rc6(dev); |
2c34b850 | 8738 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8739 | return; |
8740 | } | |
ac668088 | 8741 | |
d5bb081b JB |
8742 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
8743 | OUT_RING(MI_SET_CONTEXT); | |
8744 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
8745 | MI_MM_SPACE_GTT | | |
8746 | MI_SAVE_EXT_STATE_EN | | |
8747 | MI_RESTORE_EXT_STATE_EN | | |
8748 | MI_RESTORE_INHIBIT); | |
8749 | OUT_RING(MI_SUSPEND_FLUSH); | |
8750 | OUT_RING(MI_NOOP); | |
8751 | OUT_RING(MI_FLUSH); | |
8752 | ADVANCE_LP_RING(); | |
8753 | ||
4a246cfc BW |
8754 | /* |
8755 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
8756 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
8757 | * safe to assume that renderctx is valid | |
8758 | */ | |
8759 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
8760 | if (ret) { | |
8761 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
8762 | ironlake_teardown_rc6(dev); | |
8763 | mutex_unlock(&dev->struct_mutex); | |
8764 | return; | |
8765 | } | |
8766 | ||
d5bb081b JB |
8767 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
8768 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 8769 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8770 | } |
8771 | ||
645c62a5 JB |
8772 | void intel_init_clock_gating(struct drm_device *dev) |
8773 | { | |
8774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8775 | ||
8776 | dev_priv->display.init_clock_gating(dev); | |
8777 | ||
8778 | if (dev_priv->display.init_pch_clock_gating) | |
8779 | dev_priv->display.init_pch_clock_gating(dev); | |
8780 | } | |
ac668088 | 8781 | |
e70236a8 JB |
8782 | /* Set up chip specific display functions */ |
8783 | static void intel_init_display(struct drm_device *dev) | |
8784 | { | |
8785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8786 | ||
8787 | /* We always want a DPMS function */ | |
f564048e | 8788 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 8789 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 8790 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 8791 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8792 | } else { |
e70236a8 | 8793 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 8794 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 8795 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8796 | } |
e70236a8 | 8797 | |
ee5382ae | 8798 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8799 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8800 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8801 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8802 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8803 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8804 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8805 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8806 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8807 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8808 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8809 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8810 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8811 | } | |
74dff282 | 8812 | /* 855GM needs testing */ |
e70236a8 JB |
8813 | } |
8814 | ||
8815 | /* Returns the core display clock speed */ | |
0206e353 | 8816 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8817 | dev_priv->display.get_display_clock_speed = |
8818 | i945_get_display_clock_speed; | |
8819 | else if (IS_I915G(dev)) | |
8820 | dev_priv->display.get_display_clock_speed = | |
8821 | i915_get_display_clock_speed; | |
f2b115e6 | 8822 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8823 | dev_priv->display.get_display_clock_speed = |
8824 | i9xx_misc_get_display_clock_speed; | |
8825 | else if (IS_I915GM(dev)) | |
8826 | dev_priv->display.get_display_clock_speed = | |
8827 | i915gm_get_display_clock_speed; | |
8828 | else if (IS_I865G(dev)) | |
8829 | dev_priv->display.get_display_clock_speed = | |
8830 | i865_get_display_clock_speed; | |
f0f8a9ce | 8831 | else if (IS_I85X(dev)) |
e70236a8 JB |
8832 | dev_priv->display.get_display_clock_speed = |
8833 | i855_get_display_clock_speed; | |
8834 | else /* 852, 830 */ | |
8835 | dev_priv->display.get_display_clock_speed = | |
8836 | i830_get_display_clock_speed; | |
8837 | ||
8838 | /* For FIFO watermark updates */ | |
7f8a8569 | 8839 | if (HAS_PCH_SPLIT(dev)) { |
8d715f00 KP |
8840 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |
8841 | dev_priv->display.force_wake_put = __gen6_gt_force_wake_put; | |
8842 | ||
8843 | /* IVB configs may use multi-threaded forcewake */ | |
8844 | if (IS_IVYBRIDGE(dev)) { | |
8845 | u32 ecobus; | |
8846 | ||
c7dffff7 KP |
8847 | /* A small trick here - if the bios hasn't configured MT forcewake, |
8848 | * and if the device is in RC6, then force_wake_mt_get will not wake | |
8849 | * the device and the ECOBUS read will return zero. Which will be | |
8850 | * (correctly) interpreted by the test below as MT forcewake being | |
8851 | * disabled. | |
8852 | */ | |
8d715f00 KP |
8853 | mutex_lock(&dev->struct_mutex); |
8854 | __gen6_gt_force_wake_mt_get(dev_priv); | |
c7dffff7 | 8855 | ecobus = I915_READ_NOTRACE(ECOBUS); |
8d715f00 KP |
8856 | __gen6_gt_force_wake_mt_put(dev_priv); |
8857 | mutex_unlock(&dev->struct_mutex); | |
8858 | ||
8859 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
8860 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); | |
8861 | dev_priv->display.force_wake_get = | |
8862 | __gen6_gt_force_wake_mt_get; | |
8863 | dev_priv->display.force_wake_put = | |
8864 | __gen6_gt_force_wake_mt_put; | |
8865 | } | |
8866 | } | |
8867 | ||
645c62a5 JB |
8868 | if (HAS_PCH_IBX(dev)) |
8869 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
8870 | else if (HAS_PCH_CPT(dev)) | |
8871 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
8872 | ||
f00a3ddf | 8873 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8874 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8875 | dev_priv->display.update_wm = ironlake_update_wm; | |
8876 | else { | |
8877 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8878 | "Disable CxSR\n"); | |
8879 | dev_priv->display.update_wm = NULL; | |
1398261a | 8880 | } |
674cf967 | 8881 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 8882 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 8883 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
8884 | } else if (IS_GEN6(dev)) { |
8885 | if (SNB_READ_WM0_LATENCY()) { | |
8886 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8887 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
1398261a YL |
8888 | } else { |
8889 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8890 | "Disable CxSR\n"); | |
8891 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 8892 | } |
674cf967 | 8893 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 8894 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 8895 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8896 | } else if (IS_IVYBRIDGE(dev)) { |
8897 | /* FIXME: detect B0+ stepping and use auto training */ | |
8898 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
8899 | if (SNB_READ_WM0_LATENCY()) { |
8900 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8901 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
fe100d4d JB |
8902 | } else { |
8903 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8904 | "Disable CxSR\n"); | |
8905 | dev_priv->display.update_wm = NULL; | |
8906 | } | |
28963a3e | 8907 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 8908 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
8909 | } else |
8910 | dev_priv->display.update_wm = NULL; | |
8911 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8912 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8913 | dev_priv->is_ddr3, |
d4294342 ZY |
8914 | dev_priv->fsb_freq, |
8915 | dev_priv->mem_freq)) { | |
8916 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8917 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8918 | "disabling CxSR\n", |
0206e353 | 8919 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
8920 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8921 | /* Disable CxSR and never update its watermark again */ | |
8922 | pineview_disable_cxsr(dev); | |
8923 | dev_priv->display.update_wm = NULL; | |
8924 | } else | |
8925 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 8926 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 8927 | } else if (IS_G4X(dev)) { |
e0dac65e | 8928 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8929 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
8930 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
8931 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 8932 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
8933 | if (IS_CRESTLINE(dev)) |
8934 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
8935 | else if (IS_BROADWATER(dev)) | |
8936 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
8937 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
8938 | dev_priv->display.update_wm = i9xx_update_wm; |
8939 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
8940 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
8941 | } else if (IS_I865G(dev)) { | |
8942 | dev_priv->display.update_wm = i830_update_wm; | |
8943 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8944 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
8945 | } else if (IS_I85X(dev)) { |
8946 | dev_priv->display.update_wm = i9xx_update_wm; | |
8947 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 8948 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 8949 | } else { |
8f4695ed | 8950 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 8951 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 8952 | if (IS_845G(dev)) |
e70236a8 JB |
8953 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8954 | else | |
8955 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 8956 | } |
8c9f3aaf JB |
8957 | |
8958 | /* Default just returns -ENODEV to indicate unsupported */ | |
8959 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8960 | ||
8961 | switch (INTEL_INFO(dev)->gen) { | |
8962 | case 2: | |
8963 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8964 | break; | |
8965 | ||
8966 | case 3: | |
8967 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8968 | break; | |
8969 | ||
8970 | case 4: | |
8971 | case 5: | |
8972 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8973 | break; | |
8974 | ||
8975 | case 6: | |
8976 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8977 | break; | |
7c9017e5 JB |
8978 | case 7: |
8979 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8980 | break; | |
8c9f3aaf | 8981 | } |
e70236a8 JB |
8982 | } |
8983 | ||
b690e96c JB |
8984 | /* |
8985 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8986 | * resume, or other times. This quirk makes sure that's the case for | |
8987 | * affected systems. | |
8988 | */ | |
0206e353 | 8989 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8990 | { |
8991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8992 | ||
8993 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
8994 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
8995 | } | |
8996 | ||
435793df KP |
8997 | /* |
8998 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8999 | */ | |
9000 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9001 | { | |
9002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9003 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
9004 | } | |
9005 | ||
b690e96c JB |
9006 | struct intel_quirk { |
9007 | int device; | |
9008 | int subsystem_vendor; | |
9009 | int subsystem_device; | |
9010 | void (*hook)(struct drm_device *dev); | |
9011 | }; | |
9012 | ||
9013 | struct intel_quirk intel_quirks[] = { | |
9014 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
9015 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
9016 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
0206e353 | 9017 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
9018 | |
9019 | /* Thinkpad R31 needs pipe A force quirk */ | |
9020 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
9021 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
9022 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9023 | ||
9024 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
9025 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
9026 | /* ThinkPad X40 needs pipe A force quirk */ | |
9027 | ||
9028 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
9029 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9030 | ||
9031 | /* 855 & before need to leave pipe A & dpll A up */ | |
9032 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
9033 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
9034 | |
9035 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9036 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9037 | |
9038 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9039 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
b690e96c JB |
9040 | }; |
9041 | ||
9042 | static void intel_init_quirks(struct drm_device *dev) | |
9043 | { | |
9044 | struct pci_dev *d = dev->pdev; | |
9045 | int i; | |
9046 | ||
9047 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
9048 | struct intel_quirk *q = &intel_quirks[i]; | |
9049 | ||
9050 | if (d->device == q->device && | |
9051 | (d->subsystem_vendor == q->subsystem_vendor || | |
9052 | q->subsystem_vendor == PCI_ANY_ID) && | |
9053 | (d->subsystem_device == q->subsystem_device || | |
9054 | q->subsystem_device == PCI_ANY_ID)) | |
9055 | q->hook(dev); | |
9056 | } | |
9057 | } | |
9058 | ||
9cce37f4 JB |
9059 | /* Disable the VGA plane that we never use */ |
9060 | static void i915_disable_vga(struct drm_device *dev) | |
9061 | { | |
9062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9063 | u8 sr1; | |
9064 | u32 vga_reg; | |
9065 | ||
9066 | if (HAS_PCH_SPLIT(dev)) | |
9067 | vga_reg = CPU_VGACNTRL; | |
9068 | else | |
9069 | vga_reg = VGACNTRL; | |
9070 | ||
9071 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9072 | outb(1, VGA_SR_INDEX); | |
9073 | sr1 = inb(VGA_SR_DATA); | |
9074 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
9075 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9076 | udelay(300); | |
9077 | ||
9078 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
9079 | POSTING_READ(vga_reg); | |
9080 | } | |
9081 | ||
79e53945 JB |
9082 | void intel_modeset_init(struct drm_device *dev) |
9083 | { | |
652c393a | 9084 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 9085 | int i, ret; |
79e53945 JB |
9086 | |
9087 | drm_mode_config_init(dev); | |
9088 | ||
9089 | dev->mode_config.min_width = 0; | |
9090 | dev->mode_config.min_height = 0; | |
9091 | ||
9092 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
9093 | ||
b690e96c JB |
9094 | intel_init_quirks(dev); |
9095 | ||
e70236a8 JB |
9096 | intel_init_display(dev); |
9097 | ||
a6c45cf0 CW |
9098 | if (IS_GEN2(dev)) { |
9099 | dev->mode_config.max_width = 2048; | |
9100 | dev->mode_config.max_height = 2048; | |
9101 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9102 | dev->mode_config.max_width = 4096; |
9103 | dev->mode_config.max_height = 4096; | |
79e53945 | 9104 | } else { |
a6c45cf0 CW |
9105 | dev->mode_config.max_width = 8192; |
9106 | dev->mode_config.max_height = 8192; | |
79e53945 | 9107 | } |
35c3047a | 9108 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 9109 | |
28c97730 | 9110 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 9111 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 9112 | |
a3524f1b | 9113 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 9114 | intel_crtc_init(dev, i); |
00c2064b JB |
9115 | ret = intel_plane_init(dev, i); |
9116 | if (ret) | |
9117 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
9118 | } |
9119 | ||
9cce37f4 JB |
9120 | /* Just disable it once at startup */ |
9121 | i915_disable_vga(dev); | |
79e53945 | 9122 | intel_setup_outputs(dev); |
652c393a | 9123 | |
645c62a5 | 9124 | intel_init_clock_gating(dev); |
9cce37f4 | 9125 | |
7648fa99 | 9126 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 9127 | ironlake_enable_drps(dev); |
7648fa99 JB |
9128 | intel_init_emon(dev); |
9129 | } | |
f97108d1 | 9130 | |
1c70c0ce | 9131 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 9132 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
9133 | gen6_update_ring_freq(dev_priv); |
9134 | } | |
3b8d8d91 | 9135 | |
652c393a JB |
9136 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
9137 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
9138 | (unsigned long)dev); | |
2c7111db CW |
9139 | } |
9140 | ||
9141 | void intel_modeset_gem_init(struct drm_device *dev) | |
9142 | { | |
9143 | if (IS_IRONLAKE_M(dev)) | |
9144 | ironlake_enable_rc6(dev); | |
02e792fb DV |
9145 | |
9146 | intel_setup_overlay(dev); | |
79e53945 JB |
9147 | } |
9148 | ||
9149 | void intel_modeset_cleanup(struct drm_device *dev) | |
9150 | { | |
652c393a JB |
9151 | struct drm_i915_private *dev_priv = dev->dev_private; |
9152 | struct drm_crtc *crtc; | |
9153 | struct intel_crtc *intel_crtc; | |
9154 | ||
f87ea761 | 9155 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9156 | mutex_lock(&dev->struct_mutex); |
9157 | ||
723bfd70 JB |
9158 | intel_unregister_dsm_handler(); |
9159 | ||
9160 | ||
652c393a JB |
9161 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9162 | /* Skip inactive CRTCs */ | |
9163 | if (!crtc->fb) | |
9164 | continue; | |
9165 | ||
9166 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9167 | intel_increase_pllclock(crtc); |
652c393a JB |
9168 | } |
9169 | ||
973d04f9 | 9170 | intel_disable_fbc(dev); |
e70236a8 | 9171 | |
f97108d1 JB |
9172 | if (IS_IRONLAKE_M(dev)) |
9173 | ironlake_disable_drps(dev); | |
1c70c0ce | 9174 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 9175 | gen6_disable_rps(dev); |
f97108d1 | 9176 | |
d5bb081b JB |
9177 | if (IS_IRONLAKE_M(dev)) |
9178 | ironlake_disable_rc6(dev); | |
0cdab21f | 9179 | |
69341a5e KH |
9180 | mutex_unlock(&dev->struct_mutex); |
9181 | ||
6c0d9350 DV |
9182 | /* Disable the irq before mode object teardown, for the irq might |
9183 | * enqueue unpin/hotplug work. */ | |
9184 | drm_irq_uninstall(dev); | |
9185 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 9186 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 9187 | |
1630fe75 CW |
9188 | /* flush any delayed tasks or pending work */ |
9189 | flush_scheduled_work(); | |
9190 | ||
3dec0095 DV |
9191 | /* Shut off idle work before the crtcs get freed. */ |
9192 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9193 | intel_crtc = to_intel_crtc(crtc); | |
9194 | del_timer_sync(&intel_crtc->idle_timer); | |
9195 | } | |
9196 | del_timer_sync(&dev_priv->idle_timer); | |
9197 | cancel_work_sync(&dev_priv->idle_work); | |
9198 | ||
79e53945 JB |
9199 | drm_mode_config_cleanup(dev); |
9200 | } | |
9201 | ||
f1c79df3 ZW |
9202 | /* |
9203 | * Return which encoder is currently attached for connector. | |
9204 | */ | |
df0e9248 | 9205 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9206 | { |
df0e9248 CW |
9207 | return &intel_attached_encoder(connector)->base; |
9208 | } | |
f1c79df3 | 9209 | |
df0e9248 CW |
9210 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9211 | struct intel_encoder *encoder) | |
9212 | { | |
9213 | connector->encoder = encoder; | |
9214 | drm_mode_connector_attach_encoder(&connector->base, | |
9215 | &encoder->base); | |
79e53945 | 9216 | } |
28d52043 DA |
9217 | |
9218 | /* | |
9219 | * set vga decode state - true == enable VGA decode | |
9220 | */ | |
9221 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9222 | { | |
9223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9224 | u16 gmch_ctrl; | |
9225 | ||
9226 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9227 | if (state) | |
9228 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9229 | else | |
9230 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9231 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9232 | return 0; | |
9233 | } | |
c4a1d9e4 CW |
9234 | |
9235 | #ifdef CONFIG_DEBUG_FS | |
9236 | #include <linux/seq_file.h> | |
9237 | ||
9238 | struct intel_display_error_state { | |
9239 | struct intel_cursor_error_state { | |
9240 | u32 control; | |
9241 | u32 position; | |
9242 | u32 base; | |
9243 | u32 size; | |
9244 | } cursor[2]; | |
9245 | ||
9246 | struct intel_pipe_error_state { | |
9247 | u32 conf; | |
9248 | u32 source; | |
9249 | ||
9250 | u32 htotal; | |
9251 | u32 hblank; | |
9252 | u32 hsync; | |
9253 | u32 vtotal; | |
9254 | u32 vblank; | |
9255 | u32 vsync; | |
9256 | } pipe[2]; | |
9257 | ||
9258 | struct intel_plane_error_state { | |
9259 | u32 control; | |
9260 | u32 stride; | |
9261 | u32 size; | |
9262 | u32 pos; | |
9263 | u32 addr; | |
9264 | u32 surface; | |
9265 | u32 tile_offset; | |
9266 | } plane[2]; | |
9267 | }; | |
9268 | ||
9269 | struct intel_display_error_state * | |
9270 | intel_display_capture_error_state(struct drm_device *dev) | |
9271 | { | |
0206e353 | 9272 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9273 | struct intel_display_error_state *error; |
9274 | int i; | |
9275 | ||
9276 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9277 | if (error == NULL) | |
9278 | return NULL; | |
9279 | ||
9280 | for (i = 0; i < 2; i++) { | |
9281 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9282 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9283 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9284 | ||
9285 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9286 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9287 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9288 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9289 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9290 | if (INTEL_INFO(dev)->gen >= 4) { | |
9291 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9292 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9293 | } | |
9294 | ||
9295 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
9296 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
9297 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
9298 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
9299 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
9300 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
9301 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
9302 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
9303 | } | |
9304 | ||
9305 | return error; | |
9306 | } | |
9307 | ||
9308 | void | |
9309 | intel_display_print_error_state(struct seq_file *m, | |
9310 | struct drm_device *dev, | |
9311 | struct intel_display_error_state *error) | |
9312 | { | |
9313 | int i; | |
9314 | ||
9315 | for (i = 0; i < 2; i++) { | |
9316 | seq_printf(m, "Pipe [%d]:\n", i); | |
9317 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9318 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9319 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9320 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9321 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9322 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9323 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9324 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9325 | ||
9326 | seq_printf(m, "Plane [%d]:\n", i); | |
9327 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9328 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9329 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9330 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9331 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9332 | if (INTEL_INFO(dev)->gen >= 4) { | |
9333 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9334 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9335 | } | |
9336 | ||
9337 | seq_printf(m, "Cursor [%d]:\n", i); | |
9338 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9339 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9340 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9341 | } | |
9342 | } | |
9343 | #endif |