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drm: bpp and depth changes require full mode sets
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
291906f1
JB		 983static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985{
47a05eca
JB		 986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 989 reg, pipe_name(pipe));
291906f1
JB		 990}
991
992static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994{
47a05eca
JB		 995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 998 reg, pipe_name(pipe));
291906f1
JB		 999}
1000
1001static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
291906f1
JB		 1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
47a05eca 1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 pipe_name(pipe));
291906f1
JB		 1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
47a05eca 1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1021 pipe_name(pipe));
291906f1
JB		 1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026}
1027
63d7bbe9
JB		 1028/**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040{
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065}
1066
1067/**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077{
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093}
1094
92f2584a
JB		 1095/**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121}
1122
1123static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125{
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141}
1142
040484af
JB		 1143static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
e9bcff5c
JB		 1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
040484af
JB		 1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173}
1174
1175static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
291906f1
JB		 1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
040484af
JB		 1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195}
1196
b24e7179 1197/**
309cfea8 1198 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
040484af 1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
040484af
JB		 1211static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
b24e7179
JB		 1213{
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
b24e7179
JB		 1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
00d70b15
CW		 1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240}
1241
1242/**
309cfea8 1243 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
00d70b15
CW		 1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277}
1278
1279/**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
00d70b15
CW		 1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303}
1304
1305/*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311{
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314}
1315
1316/**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
00d70b15
CW		 1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338}
1339
47a05eca
JB		 1340static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342{
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346}
1347
1348static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350{
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354}
1355
1356/* Disable any ports connected to this transcoder */
1357static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385}
1386
80824003
JB		 1387static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1388{
1389 struct drm_device *dev = crtc->dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 struct drm_framebuffer *fb = crtc->fb;
1392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1393 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1395 int plane, i;
1396 u32 fbc_ctl, fbc_ctl2;
1397
bed4a673 1398 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1399 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1400 intel_crtc->plane == dev_priv->cfb_plane &&
1401 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1402 return;
1403
1404 i8xx_disable_fbc(dev);
1405
80824003
JB		 1406 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1407
1408 if (fb->pitch < dev_priv->cfb_pitch)
1409 dev_priv->cfb_pitch = fb->pitch;
1410
1411 /* FBC_CTL wants 64B units */
1412 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1413 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1414 dev_priv->cfb_plane = intel_crtc->plane;
1415 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1416
1417 /* Clear old tags */
1418 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1419 I915_WRITE(FBC_TAG + (i * 4), 0);
1420
1421 /* Set it up... */
1422 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1423 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1424 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1425 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1426 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1427
1428 /* enable it... */
1429 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1430 if (IS_I945GM(dev))
49677901 1431 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1432 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1433 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1434 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1435 fbc_ctl |= dev_priv->cfb_fence;
1436 I915_WRITE(FBC_CONTROL, fbc_ctl);
1437
28c97730 1438 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1439 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1440}
1441
1442void i8xx_disable_fbc(struct drm_device *dev)
1443{
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 fbc_ctl;
1446
1447 /* Disable compression */
1448 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1449 if ((fbc_ctl & FBC_CTL_EN) == 0)
1450 return;
1451
80824003
JB		 1452 fbc_ctl &= ~FBC_CTL_EN;
1453 I915_WRITE(FBC_CONTROL, fbc_ctl);
1454
1455 /* Wait for compressing bit to clear */
481b6af3 1456 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1457 DRM_DEBUG_KMS("FBC idle timed out\n");
1458 return;
9517a92f 1459 }
80824003 1460
28c97730 1461 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1462}
1463
ee5382ae 1464static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1465{
80824003
JB		 1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1469}
1470
74dff282
JB		 1471static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1472{
1473 struct drm_device *dev = crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_framebuffer *fb = crtc->fb;
1476 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1477 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1479 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1480 unsigned long stall_watermark = 200;
1481 u32 dpfc_ctl;
1482
bed4a673
CW		 1483 dpfc_ctl = I915_READ(DPFC_CONTROL);
1484 if (dpfc_ctl & DPFC_CTL_EN) {
1485 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1486 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1487 dev_priv->cfb_plane == intel_crtc->plane &&
1488 dev_priv->cfb_y == crtc->y)
1489 return;
1490
1491 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1492 intel_wait_for_vblank(dev, intel_crtc->pipe);
1493 }
1494
74dff282 1495 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1496 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1497 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1498 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1499
1500 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1501 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1502 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1503 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1504 } else {
1505 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1506 }
1507
74dff282
JB		 1508 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1509 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1510 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1511 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1512
1513 /* enable it... */
1514 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1515
28c97730 1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1517}
1518
1519void g4x_disable_fbc(struct drm_device *dev)
1520{
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 u32 dpfc_ctl;
1523
1524 /* Disable compression */
1525 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1526 if (dpfc_ctl & DPFC_CTL_EN) {
1527 dpfc_ctl &= ~DPFC_CTL_EN;
1528 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1529
bed4a673
CW		 1530 DRM_DEBUG_KMS("disabled FBC\n");
1531 }
74dff282
JB		 1532}
1533
ee5382ae 1534static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1535{
74dff282
JB		 1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1539}
1540
4efe0708
JB		 1541static void sandybridge_blit_fbc_update(struct drm_device *dev)
1542{
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 u32 blt_ecoskpd;
1545
1546 /* Make sure blitter notifies FBC of writes */
fcca7926 1547 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1548 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1549 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1550 GEN6_BLITTER_LOCK_SHIFT;
1551 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1552 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1553 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1554 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1555 GEN6_BLITTER_LOCK_SHIFT);
1556 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1557 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1558 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1559}
1560
b52eb4dc
ZY		 1561static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1562{
1563 struct drm_device *dev = crtc->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 struct drm_framebuffer *fb = crtc->fb;
1566 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1567 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1569 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1570 unsigned long stall_watermark = 200;
1571 u32 dpfc_ctl;
1572
bed4a673
CW		 1573 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1574 if (dpfc_ctl & DPFC_CTL_EN) {
1575 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1576 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1577 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1578 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1579 dev_priv->cfb_y == crtc->y)
1580 return;
1581
1582 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1583 intel_wait_for_vblank(dev, intel_crtc->pipe);
1584 }
1585
b52eb4dc 1586 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1587 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1588 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1589 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1590 dev_priv->cfb_y = crtc->y;
b52eb4dc 1591
b52eb4dc
ZY		 1592 dpfc_ctl &= DPFC_RESERVED;
1593 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1594 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1595 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1596 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1597 } else {
1598 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1599 }
1600
b52eb4dc
ZY		 1601 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1602 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1603 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1604 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1605 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1606 /* enable it... */
bed4a673 1607 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1608
9c04f015
YL		 1609 if (IS_GEN6(dev)) {
1610 I915_WRITE(SNB_DPFC_CTL_SA,
1611 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1612 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1613 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1614 }
1615
b52eb4dc
ZY		 1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1617}
1618
1619void ironlake_disable_fbc(struct drm_device *dev)
1620{
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 dpfc_ctl;
1623
1624 /* Disable compression */
1625 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1626 if (dpfc_ctl & DPFC_CTL_EN) {
1627 dpfc_ctl &= ~DPFC_CTL_EN;
1628 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1629
bed4a673
CW		 1630 DRM_DEBUG_KMS("disabled FBC\n");
1631 }
b52eb4dc
ZY		 1632}
1633
1634static bool ironlake_fbc_enabled(struct drm_device *dev)
1635{
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1639}
1640
ee5382ae
AJ		 1641bool intel_fbc_enabled(struct drm_device *dev)
1642{
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (!dev_priv->display.fbc_enabled)
1646 return false;
1647
1648 return dev_priv->display.fbc_enabled(dev);
1649}
1650
1651void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652{
1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1654
1655 if (!dev_priv->display.enable_fbc)
1656 return;
1657
1658 dev_priv->display.enable_fbc(crtc, interval);
1659}
1660
1661void intel_disable_fbc(struct drm_device *dev)
1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.disable_fbc)
1666 return;
1667
1668 dev_priv->display.disable_fbc(dev);
1669}
1670
80824003
JB		 1671/**
1672 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1673 * @dev: the drm_device
80824003
JB		 1674 *
1675 * Set up the framebuffer compression hardware at mode set time. We
1676 * enable it if possible:
1677 * - plane A only (on pre-965)
1678 * - no pixel mulitply/line duplication
1679 * - no alpha buffer discard
1680 * - no dual wide
1681 * - framebuffer <= 2048 in width, 1536 in height
1682 *
1683 * We can't assume that any compression will take place (worst case),
1684 * so the compressed buffer has to be the same size as the uncompressed
1685 * one. It also must reside (along with the line length buffer) in
1686 * stolen memory.
1687 *
1688 * We need to enable/disable FBC on a global basis.
1689 */
bed4a673 1690static void intel_update_fbc(struct drm_device *dev)
80824003 1691{
80824003 1692 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1693 struct drm_crtc *crtc = NULL, *tmp_crtc;
1694 struct intel_crtc *intel_crtc;
1695 struct drm_framebuffer *fb;
80824003 1696 struct intel_framebuffer *intel_fb;
05394f39 1697 struct drm_i915_gem_object *obj;
9c928d16
JB		 1698
1699 DRM_DEBUG_KMS("\n");
80824003
JB		 1700
1701 if (!i915_powersave)
1702 return;
1703
ee5382ae 1704 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1705 return;
1706
80824003
JB		 1707 /*
1708 * If FBC is already on, we just have to verify that we can
1709 * keep it that way...
1710 * Need to disable if:
9c928d16 1711 * - more than one pipe is active
80824003
JB		 1712 * - changing FBC params (stride, fence, mode)
1713 * - new fb is too large to fit in compressed buffer
1714 * - going to an unsupported config (interlace, pixel multiply, etc.)
1715 */
9c928d16 1716 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1717 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1718 if (crtc) {
1719 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1720 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1721 goto out_disable;
1722 }
1723 crtc = tmp_crtc;
1724 }
9c928d16 1725 }
bed4a673
CW		 1726
1727 if (!crtc || crtc->fb == NULL) {
1728 DRM_DEBUG_KMS("no output, disabling\n");
1729 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1730 goto out_disable;
1731 }
bed4a673
CW		 1732
1733 intel_crtc = to_intel_crtc(crtc);
1734 fb = crtc->fb;
1735 intel_fb = to_intel_framebuffer(fb);
05394f39 1736 obj = intel_fb->obj;
bed4a673 1737
c1a9f047
JB		 1738 if (!i915_enable_fbc) {
1739 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1740 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1741 goto out_disable;
1742 }
05394f39 1743 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1744 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1745 "compression\n");
b5e50c3f 1746 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1747 goto out_disable;
1748 }
bed4a673
CW		 1749 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1750 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1751 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1752 "disabling\n");
b5e50c3f 1753 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1754 goto out_disable;
1755 }
bed4a673
CW		 1756 if ((crtc->mode.hdisplay > 2048) ||
1757 (crtc->mode.vdisplay > 1536)) {
28c97730 1758 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1759 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1760 goto out_disable;
1761 }
bed4a673 1762 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1763 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1764 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1765 goto out_disable;
1766 }
05394f39 1767 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1768 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1769 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1770 goto out_disable;
1771 }
1772
c924b934
JW		 1773 /* If the kernel debugger is active, always disable compression */
1774 if (in_dbg_master())
1775 goto out_disable;
1776
bed4a673 1777 intel_enable_fbc(crtc, 500);
80824003
JB		 1778 return;
1779
1780out_disable:
80824003 1781 /* Multiple disables should be harmless */
a939406f
CW		 1782 if (intel_fbc_enabled(dev)) {
1783 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1784 intel_disable_fbc(dev);
a939406f 1785 }
80824003
JB		 1786}
1787
127bd2ac 1788int
48b956c5 1789intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1790 struct drm_i915_gem_object *obj,
919926ae 1791 struct intel_ring_buffer *pipelined)
6b95a207 1792{
ce453d81 1793 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1794 u32 alignment;
1795 int ret;
1796
05394f39 1797 switch (obj->tiling_mode) {
6b95a207 1798 case I915_TILING_NONE:
534843da
CW		 1799 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1800 alignment = 128 * 1024;
a6c45cf0 1801 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1802 alignment = 4 * 1024;
1803 else
1804 alignment = 64 * 1024;
6b95a207
KH		 1805 break;
1806 case I915_TILING_X:
1807 /* pin() will align the object as required by fence */
1808 alignment = 0;
1809 break;
1810 case I915_TILING_Y:
1811 /* FIXME: Is this true? */
1812 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1813 return -EINVAL;
1814 default:
1815 BUG();
1816 }
1817
ce453d81 1818 dev_priv->mm.interruptible = false;
2da3b9b9 1819 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1820 if (ret)
ce453d81 1821 goto err_interruptible;
6b95a207
KH		 1822
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1827 */
05394f39 1828 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1829 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1830 if (ret)
1831 goto err_unpin;
6b95a207
KH		 1832 }
1833
ce453d81 1834 dev_priv->mm.interruptible = true;
6b95a207 1835 return 0;
48b956c5
CW		 1836
1837err_unpin:
1838 i915_gem_object_unpin(obj);
ce453d81
CW		 1839err_interruptible:
1840 dev_priv->mm.interruptible = true;
48b956c5 1841 return ret;
6b95a207
KH		 1842}
1843
17638cd6
JB		 1844static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1845 int x, int y)
81255565
JB		 1846{
1847 struct drm_device *dev = crtc->dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850 struct intel_framebuffer *intel_fb;
05394f39 1851 struct drm_i915_gem_object *obj;
81255565
JB		 1852 int plane = intel_crtc->plane;
1853 unsigned long Start, Offset;
81255565 1854 u32 dspcntr;
5eddb70b 1855 u32 reg;
81255565
JB		 1856
1857 switch (plane) {
1858 case 0:
1859 case 1:
1860 break;
1861 default:
1862 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1863 return -EINVAL;
1864 }
1865
1866 intel_fb = to_intel_framebuffer(fb);
1867 obj = intel_fb->obj;
81255565 1868
5eddb70b
CW		 1869 reg = DSPCNTR(plane);
1870 dspcntr = I915_READ(reg);
81255565
JB		 1871 /* Mask out pixel format bits in case we change it */
1872 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1873 switch (fb->bits_per_pixel) {
1874 case 8:
1875 dspcntr |= DISPPLANE_8BPP;
1876 break;
1877 case 16:
1878 if (fb->depth == 15)
1879 dspcntr |= DISPPLANE_15_16BPP;
1880 else
1881 dspcntr |= DISPPLANE_16BPP;
1882 break;
1883 case 24:
1884 case 32:
1885 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1886 break;
1887 default:
17638cd6 1888 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1889 return -EINVAL;
1890 }
a6c45cf0 1891 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1892 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1893 dspcntr |= DISPPLANE_TILED;
1894 else
1895 dspcntr &= ~DISPPLANE_TILED;
1896 }
1897
5eddb70b 1898 I915_WRITE(reg, dspcntr);
81255565 1899
05394f39 1900 Start = obj->gtt_offset;
81255565
JB		 1901 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1902
4e6cfefc
CW		 1903 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1904 Start, Offset, x, y, fb->pitch);
5eddb70b 1905 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1906 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1907 I915_WRITE(DSPSURF(plane), Start);
1908 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1909 I915_WRITE(DSPADDR(plane), Offset);
1910 } else
1911 I915_WRITE(DSPADDR(plane), Start + Offset);
1912 POSTING_READ(reg);
81255565 1913
17638cd6
JB		 1914 return 0;
1915}
1916
1917static int ironlake_update_plane(struct drm_crtc *crtc,
1918 struct drm_framebuffer *fb, int x, int y)
1919{
1920 struct drm_device *dev = crtc->dev;
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1923 struct intel_framebuffer *intel_fb;
1924 struct drm_i915_gem_object *obj;
1925 int plane = intel_crtc->plane;
1926 unsigned long Start, Offset;
1927 u32 dspcntr;
1928 u32 reg;
1929
1930 switch (plane) {
1931 case 0:
1932 case 1:
1933 break;
1934 default:
1935 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1936 return -EINVAL;
1937 }
1938
1939 intel_fb = to_intel_framebuffer(fb);
1940 obj = intel_fb->obj;
1941
1942 reg = DSPCNTR(plane);
1943 dspcntr = I915_READ(reg);
1944 /* Mask out pixel format bits in case we change it */
1945 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1946 switch (fb->bits_per_pixel) {
1947 case 8:
1948 dspcntr |= DISPPLANE_8BPP;
1949 break;
1950 case 16:
1951 if (fb->depth != 16)
1952 return -EINVAL;
1953
1954 dspcntr |= DISPPLANE_16BPP;
1955 break;
1956 case 24:
1957 case 32:
1958 if (fb->depth == 24)
1959 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1960 else if (fb->depth == 30)
1961 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1962 else
1963 return -EINVAL;
1964 break;
1965 default:
1966 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1967 return -EINVAL;
1968 }
1969
1970 if (obj->tiling_mode != I915_TILING_NONE)
1971 dspcntr |= DISPPLANE_TILED;
1972 else
1973 dspcntr &= ~DISPPLANE_TILED;
1974
1975 /* must disable */
1976 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1977
1978 I915_WRITE(reg, dspcntr);
1979
1980 Start = obj->gtt_offset;
1981 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1982
1983 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1984 Start, Offset, x, y, fb->pitch);
1985 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1986 I915_WRITE(DSPSURF(plane), Start);
1987 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1988 I915_WRITE(DSPADDR(plane), Offset);
1989 POSTING_READ(reg);
1990
1991 return 0;
1992}
1993
1994/* Assume fb object is pinned & idle & fenced and just update base pointers */
1995static int
1996intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1997 int x, int y, enum mode_set_atomic state)
1998{
1999 struct drm_device *dev = crtc->dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 int ret;
2002
2003 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2004 if (ret)
2005 return ret;
2006
bed4a673 2007 intel_update_fbc(dev);
3dec0095 2008 intel_increase_pllclock(crtc);
81255565
JB		 2009
2010 return 0;
2011}
2012
5c3b82e2 2013static int
3c4fdcfb
KH		 2014intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2015 struct drm_framebuffer *old_fb)
79e53945
JB		 2016{
2017 struct drm_device *dev = crtc->dev;
79e53945
JB		 2018 struct drm_i915_master_private *master_priv;
2019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2020 int ret;
79e53945
JB		 2021
2022 /* no fb bound */
2023 if (!crtc->fb) {
28c97730 2024 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 2025 return 0;
2026 }
2027
265db958 2028 switch (intel_crtc->plane) {
5c3b82e2
CW		 2029 case 0:
2030 case 1:
2031 break;
2032 default:
5c3b82e2 2033 return -EINVAL;
79e53945
JB		 2034 }
2035
5c3b82e2 2036 mutex_lock(&dev->struct_mutex);
265db958
CW		 2037 ret = intel_pin_and_fence_fb_obj(dev,
2038 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2039 NULL);
5c3b82e2
CW		 2040 if (ret != 0) {
2041 mutex_unlock(&dev->struct_mutex);
2042 return ret;
2043 }
79e53945 2044
265db958 2045 if (old_fb) {
e6c3a2a6 2046 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2047 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2048
e6c3a2a6 2049 wait_event(dev_priv->pending_flip_queue,
01eec727 2050 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2051 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2052
2053 /* Big Hammer, we also need to ensure that any pending
2054 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2055 * current scanout is retired before unpinning the old
2056 * framebuffer.
01eec727
CW		 2057 *
2058 * This should only fail upon a hung GPU, in which case we
2059 * can safely continue.
85345517 2060 */
a8198eea 2061 ret = i915_gem_object_finish_gpu(obj);
01eec727 2062 (void) ret;
265db958
CW		 2063 }
2064
21c74a8e
JW		 2065 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2066 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2067 if (ret) {
265db958 2068 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2069 mutex_unlock(&dev->struct_mutex);
4e6cfefc 2070 return ret;
79e53945 2071 }
3c4fdcfb 2072
b7f1de28
CW		 2073 if (old_fb) {
2074 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2075 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2076 }
652c393a 2077
5c3b82e2 2078 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2079
2080 if (!dev->primary->master)
5c3b82e2 2081 return 0;
79e53945
JB		 2082
2083 master_priv = dev->primary->master->driver_priv;
2084 if (!master_priv->sarea_priv)
5c3b82e2 2085 return 0;
79e53945 2086
265db958 2087 if (intel_crtc->pipe) {
79e53945
JB		 2088 master_priv->sarea_priv->pipeB_x = x;
2089 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2090 } else {
2091 master_priv->sarea_priv->pipeA_x = x;
2092 master_priv->sarea_priv->pipeA_y = y;
79e53945 2093 }
5c3b82e2
CW		 2094
2095 return 0;
79e53945
JB		 2096}
2097
5eddb70b 2098static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2099{
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 u32 dpa_ctl;
2103
28c97730 2104 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2105 dpa_ctl = I915_READ(DP_A);
2106 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2107
2108 if (clock < 200000) {
2109 u32 temp;
2110 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2111 /* workaround for 160Mhz:
2112 1) program 0x4600c bits 15:0 = 0x8124
2113 2) program 0x46010 bit 0 = 1
2114 3) program 0x46034 bit 24 = 1
2115 4) program 0x64000 bit 14 = 1
2116 */
2117 temp = I915_READ(0x4600c);
2118 temp &= 0xffff0000;
2119 I915_WRITE(0x4600c, temp | 0x8124);
2120
2121 temp = I915_READ(0x46010);
2122 I915_WRITE(0x46010, temp | 1);
2123
2124 temp = I915_READ(0x46034);
2125 I915_WRITE(0x46034, temp | (1 << 24));
2126 } else {
2127 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2128 }
2129 I915_WRITE(DP_A, dpa_ctl);
2130
5eddb70b 2131 POSTING_READ(DP_A);
32f9d658
ZW		 2132 udelay(500);
2133}
2134
5e84e1a4
ZW		 2135static void intel_fdi_normal_train(struct drm_crtc *crtc)
2136{
2137 struct drm_device *dev = crtc->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 int pipe = intel_crtc->pipe;
2141 u32 reg, temp;
2142
2143 /* enable normal train */
2144 reg = FDI_TX_CTL(pipe);
2145 temp = I915_READ(reg);
61e499bf 2146 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2147 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2148 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2149 } else {
2150 temp &= ~FDI_LINK_TRAIN_NONE;
2151 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2152 }
5e84e1a4
ZW		 2153 I915_WRITE(reg, temp);
2154
2155 reg = FDI_RX_CTL(pipe);
2156 temp = I915_READ(reg);
2157 if (HAS_PCH_CPT(dev)) {
2158 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2159 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2160 } else {
2161 temp &= ~FDI_LINK_TRAIN_NONE;
2162 temp |= FDI_LINK_TRAIN_NONE;
2163 }
2164 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2165
2166 /* wait one idle pattern time */
2167 POSTING_READ(reg);
2168 udelay(1000);
357555c0
JB		 2169
2170 /* IVB wants error correction enabled */
2171 if (IS_IVYBRIDGE(dev))
2172 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2173 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2174}
2175
8db9d77b
ZW		 2176/* The FDI link training functions for ILK/Ibexpeak. */
2177static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2178{
2179 struct drm_device *dev = crtc->dev;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2182 int pipe = intel_crtc->pipe;
0fc932b8 2183 int plane = intel_crtc->plane;
5eddb70b 2184 u32 reg, temp, tries;
8db9d77b 2185
0fc932b8
JB		 2186 /* FDI needs bits from pipe & plane first */
2187 assert_pipe_enabled(dev_priv, pipe);
2188 assert_plane_enabled(dev_priv, plane);
2189
e1a44743
AJ		 2190 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2191 for train result */
5eddb70b
CW		 2192 reg = FDI_RX_IMR(pipe);
2193 temp = I915_READ(reg);
e1a44743
AJ		 2194 temp &= ~FDI_RX_SYMBOL_LOCK;
2195 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2196 I915_WRITE(reg, temp);
2197 I915_READ(reg);
e1a44743
AJ		 2198 udelay(150);
2199
8db9d77b 2200 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2201 reg = FDI_TX_CTL(pipe);
2202 temp = I915_READ(reg);
77ffb597
AJ		 2203 temp &= ~(7 << 19);
2204 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2205 temp &= ~FDI_LINK_TRAIN_NONE;
2206 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2207 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2208
5eddb70b
CW		 2209 reg = FDI_RX_CTL(pipe);
2210 temp = I915_READ(reg);
8db9d77b
ZW		 2211 temp &= ~FDI_LINK_TRAIN_NONE;
2212 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2213 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2214
2215 POSTING_READ(reg);
8db9d77b
ZW		 2216 udelay(150);
2217
5b2adf89 2218 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2219 if (HAS_PCH_IBX(dev)) {
2220 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2221 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2222 FDI_RX_PHASE_SYNC_POINTER_EN);
2223 }
5b2adf89 2224
5eddb70b 2225 reg = FDI_RX_IIR(pipe);
e1a44743 2226 for (tries = 0; tries < 5; tries++) {
5eddb70b 2227 temp = I915_READ(reg);
8db9d77b
ZW		 2228 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2229
2230 if ((temp & FDI_RX_BIT_LOCK)) {
2231 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2232 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2233 break;
2234 }
8db9d77b 2235 }
e1a44743 2236 if (tries == 5)
5eddb70b 2237 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2238
2239 /* Train 2 */
5eddb70b
CW		 2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
8db9d77b
ZW		 2242 temp &= ~FDI_LINK_TRAIN_NONE;
2243 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2244 I915_WRITE(reg, temp);
8db9d77b 2245
5eddb70b
CW		 2246 reg = FDI_RX_CTL(pipe);
2247 temp = I915_READ(reg);
8db9d77b
ZW		 2248 temp &= ~FDI_LINK_TRAIN_NONE;
2249 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2250 I915_WRITE(reg, temp);
8db9d77b 2251
5eddb70b
CW		 2252 POSTING_READ(reg);
2253 udelay(150);
8db9d77b 2254
5eddb70b 2255 reg = FDI_RX_IIR(pipe);
e1a44743 2256 for (tries = 0; tries < 5; tries++) {
5eddb70b 2257 temp = I915_READ(reg);
8db9d77b
ZW		 2258 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2259
2260 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2261 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2262 DRM_DEBUG_KMS("FDI train 2 done.\n");
2263 break;
2264 }
8db9d77b 2265 }
e1a44743 2266 if (tries == 5)
5eddb70b 2267 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2268
2269 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2270
8db9d77b
ZW		 2271}
2272
311bd68e 2273static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2274 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2275 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2276 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2277 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2278};
2279
2280/* The FDI link training functions for SNB/Cougarpoint. */
2281static void gen6_fdi_link_train(struct drm_crtc *crtc)
2282{
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2286 int pipe = intel_crtc->pipe;
5eddb70b 2287 u32 reg, temp, i;
8db9d77b 2288
e1a44743
AJ		 2289 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2290 for train result */
5eddb70b
CW		 2291 reg = FDI_RX_IMR(pipe);
2292 temp = I915_READ(reg);
e1a44743
AJ		 2293 temp &= ~FDI_RX_SYMBOL_LOCK;
2294 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2295 I915_WRITE(reg, temp);
2296
2297 POSTING_READ(reg);
e1a44743
AJ		 2298 udelay(150);
2299
8db9d77b 2300 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2301 reg = FDI_TX_CTL(pipe);
2302 temp = I915_READ(reg);
77ffb597
AJ		 2303 temp &= ~(7 << 19);
2304 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2305 temp &= ~FDI_LINK_TRAIN_NONE;
2306 temp |= FDI_LINK_TRAIN_PATTERN_1;
2307 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2308 /* SNB-B */
2309 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2310 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2311
5eddb70b
CW		 2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
8db9d77b
ZW		 2314 if (HAS_PCH_CPT(dev)) {
2315 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2316 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2317 } else {
2318 temp &= ~FDI_LINK_TRAIN_NONE;
2319 temp |= FDI_LINK_TRAIN_PATTERN_1;
2320 }
5eddb70b
CW		 2321 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2322
2323 POSTING_READ(reg);
8db9d77b
ZW		 2324 udelay(150);
2325
8db9d77b 2326 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
8db9d77b
ZW		 2329 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2330 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2331 I915_WRITE(reg, temp);
2332
2333 POSTING_READ(reg);
8db9d77b
ZW		 2334 udelay(500);
2335
5eddb70b
CW		 2336 reg = FDI_RX_IIR(pipe);
2337 temp = I915_READ(reg);
8db9d77b
ZW		 2338 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2339
2340 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2341 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2342 DRM_DEBUG_KMS("FDI train 1 done.\n");
2343 break;
2344 }
2345 }
2346 if (i == 4)
5eddb70b 2347 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2348
2349 /* Train 2 */
5eddb70b
CW		 2350 reg = FDI_TX_CTL(pipe);
2351 temp = I915_READ(reg);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_2;
2354 if (IS_GEN6(dev)) {
2355 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2356 /* SNB-B */
2357 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2358 }
5eddb70b 2359 I915_WRITE(reg, temp);
8db9d77b 2360
5eddb70b
CW		 2361 reg = FDI_RX_CTL(pipe);
2362 temp = I915_READ(reg);
8db9d77b
ZW		 2363 if (HAS_PCH_CPT(dev)) {
2364 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2365 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2366 } else {
2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
2369 }
5eddb70b
CW		 2370 I915_WRITE(reg, temp);
2371
2372 POSTING_READ(reg);
8db9d77b
ZW		 2373 udelay(150);
2374
2375 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2376 reg = FDI_TX_CTL(pipe);
2377 temp = I915_READ(reg);
8db9d77b
ZW		 2378 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2379 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2380 I915_WRITE(reg, temp);
2381
2382 POSTING_READ(reg);
8db9d77b
ZW		 2383 udelay(500);
2384
5eddb70b
CW		 2385 reg = FDI_RX_IIR(pipe);
2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2388
2389 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2390 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2391 DRM_DEBUG_KMS("FDI train 2 done.\n");
2392 break;
2393 }
2394 }
2395 if (i == 4)
5eddb70b 2396 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2397
2398 DRM_DEBUG_KMS("FDI train done.\n");
2399}
2400
357555c0
JB		 2401/* Manual link training for Ivy Bridge A0 parts */
2402static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2403{
2404 struct drm_device *dev = crtc->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407 int pipe = intel_crtc->pipe;
2408 u32 reg, temp, i;
2409
2410 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411 for train result */
2412 reg = FDI_RX_IMR(pipe);
2413 temp = I915_READ(reg);
2414 temp &= ~FDI_RX_SYMBOL_LOCK;
2415 temp &= ~FDI_RX_BIT_LOCK;
2416 I915_WRITE(reg, temp);
2417
2418 POSTING_READ(reg);
2419 udelay(150);
2420
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~(7 << 19);
2425 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2426 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2427 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2429 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2430 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_AUTO;
2435 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2437 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2438
2439 POSTING_READ(reg);
2440 udelay(150);
2441
2442 for (i = 0; i < 4; i++ ) {
2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
2445 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2446 temp |= snb_b_fdi_train_param[i];
2447 I915_WRITE(reg, temp);
2448
2449 POSTING_READ(reg);
2450 udelay(500);
2451
2452 reg = FDI_RX_IIR(pipe);
2453 temp = I915_READ(reg);
2454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455
2456 if (temp & FDI_RX_BIT_LOCK ||
2457 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2458 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2459 DRM_DEBUG_KMS("FDI train 1 done.\n");
2460 break;
2461 }
2462 }
2463 if (i == 4)
2464 DRM_ERROR("FDI train 1 fail!\n");
2465
2466 /* Train 2 */
2467 reg = FDI_TX_CTL(pipe);
2468 temp = I915_READ(reg);
2469 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2470 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2471 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2472 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2473 I915_WRITE(reg, temp);
2474
2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
2482 udelay(150);
2483
2484 for (i = 0; i < 4; i++ ) {
2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 temp |= snb_b_fdi_train_param[i];
2489 I915_WRITE(reg, temp);
2490
2491 POSTING_READ(reg);
2492 udelay(500);
2493
2494 reg = FDI_RX_IIR(pipe);
2495 temp = I915_READ(reg);
2496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2497
2498 if (temp & FDI_RX_SYMBOL_LOCK) {
2499 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2500 DRM_DEBUG_KMS("FDI train 2 done.\n");
2501 break;
2502 }
2503 }
2504 if (i == 4)
2505 DRM_ERROR("FDI train 2 fail!\n");
2506
2507 DRM_DEBUG_KMS("FDI train done.\n");
2508}
2509
2510static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2511{
2512 struct drm_device *dev = crtc->dev;
2513 struct drm_i915_private *dev_priv = dev->dev_private;
2514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2515 int pipe = intel_crtc->pipe;
5eddb70b 2516 u32 reg, temp;
79e53945 2517
c64e311e 2518 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2519 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2520 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2521
c98e9dcf 2522 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
2525 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2526 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2527 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2528 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2529
2530 POSTING_READ(reg);
c98e9dcf
JB		 2531 udelay(200);
2532
2533 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2534 temp = I915_READ(reg);
2535 I915_WRITE(reg, temp | FDI_PCDCLK);
2536
2537 POSTING_READ(reg);
c98e9dcf
JB		 2538 udelay(200);
2539
2540 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
c98e9dcf 2543 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2544 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2545
2546 POSTING_READ(reg);
c98e9dcf 2547 udelay(100);
6be4a607 2548 }
0e23b99d
JB		 2549}
2550
0fc932b8
JB		 2551static void ironlake_fdi_disable(struct drm_crtc *crtc)
2552{
2553 struct drm_device *dev = crtc->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556 int pipe = intel_crtc->pipe;
2557 u32 reg, temp;
2558
2559 /* disable CPU FDI tx and PCH FDI rx */
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2563 POSTING_READ(reg);
2564
2565 reg = FDI_RX_CTL(pipe);
2566 temp = I915_READ(reg);
2567 temp &= ~(0x7 << 16);
2568 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2569 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2570
2571 POSTING_READ(reg);
2572 udelay(100);
2573
2574 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2575 if (HAS_PCH_IBX(dev)) {
2576 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2577 I915_WRITE(FDI_RX_CHICKEN(pipe),
2578 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2579 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2580 }
0fc932b8
JB		 2581
2582 /* still set train pattern 1 */
2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_LINK_TRAIN_NONE;
2586 temp |= FDI_LINK_TRAIN_PATTERN_1;
2587 I915_WRITE(reg, temp);
2588
2589 reg = FDI_RX_CTL(pipe);
2590 temp = I915_READ(reg);
2591 if (HAS_PCH_CPT(dev)) {
2592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594 } else {
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597 }
2598 /* BPC in FDI rx is consistent with that in PIPECONF */
2599 temp &= ~(0x07 << 16);
2600 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2601 I915_WRITE(reg, temp);
2602
2603 POSTING_READ(reg);
2604 udelay(100);
2605}
2606
6b383a7f
CW		 2607/*
2608 * When we disable a pipe, we need to clear any pending scanline wait events
2609 * to avoid hanging the ring, which we assume we are waiting on.
2610 */
2611static void intel_clear_scanline_wait(struct drm_device *dev)
2612{
2613 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2614 struct intel_ring_buffer *ring;
6b383a7f
CW		 2615 u32 tmp;
2616
2617 if (IS_GEN2(dev))
2618 /* Can't break the hang on i8xx */
2619 return;
2620
1ec14ad3 2621 ring = LP_RING(dev_priv);
8168bd48
CW		 2622 tmp = I915_READ_CTL(ring);
2623 if (tmp & RING_WAIT)
2624 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2625}
2626
e6c3a2a6
CW		 2627static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2628{
05394f39 2629 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2630 struct drm_i915_private *dev_priv;
2631
2632 if (crtc->fb == NULL)
2633 return;
2634
05394f39 2635 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2636 dev_priv = crtc->dev->dev_private;
2637 wait_event(dev_priv->pending_flip_queue,
05394f39 2638 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2639}
2640
040484af
JB		 2641static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2642{
2643 struct drm_device *dev = crtc->dev;
2644 struct drm_mode_config *mode_config = &dev->mode_config;
2645 struct intel_encoder *encoder;
2646
2647 /*
2648 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2649 * must be driven by its own crtc; no sharing is possible.
2650 */
2651 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2652 if (encoder->base.crtc != crtc)
2653 continue;
2654
2655 switch (encoder->type) {
2656 case INTEL_OUTPUT_EDP:
2657 if (!intel_encoder_is_pch_edp(&encoder->base))
2658 return false;
2659 continue;
2660 }
2661 }
2662
2663 return true;
2664}
2665
f67a559d
JB		 2666/*
2667 * Enable PCH resources required for PCH ports:
2668 * - PCH PLLs
2669 * - FDI training & RX/TX
2670 * - update transcoder timings
2671 * - DP transcoding bits
2672 * - transcoder
2673 */
2674static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2675{
2676 struct drm_device *dev = crtc->dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679 int pipe = intel_crtc->pipe;
5eddb70b 2680 u32 reg, temp;
2c07245f 2681
c98e9dcf 2682 /* For PCH output, training FDI link */
674cf967 2683 dev_priv->display.fdi_link_train(crtc);
2c07245f 2684
92f2584a 2685 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2686
c98e9dcf
JB		 2687 if (HAS_PCH_CPT(dev)) {
2688 /* Be sure PCH DPLL SEL is set */
2689 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2690 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2691 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2692 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2693 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2694 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2695 }
5eddb70b 2696
d9b6cb56
JB		 2697 /* set transcoder timing, panel must allow it */
2698 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2699 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2700 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2701 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2702
5eddb70b
CW		 2703 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2704 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2705 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2706
5e84e1a4
ZW		 2707 intel_fdi_normal_train(crtc);
2708
c98e9dcf
JB		 2709 /* For PCH DP, enable TRANS_DP_CTL */
2710 if (HAS_PCH_CPT(dev) &&
2711 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2712 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2713 reg = TRANS_DP_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2716 TRANS_DP_SYNC_MASK |
2717 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2718 temp |= (TRANS_DP_OUTPUT_ENABLE |
2719 TRANS_DP_ENH_FRAMING);
9325c9f0 2720 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2721
2722 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2723 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2724 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2725 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2726
2727 switch (intel_trans_dp_port_sel(crtc)) {
2728 case PCH_DP_B:
5eddb70b 2729 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2730 break;
2731 case PCH_DP_C:
5eddb70b 2732 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2733 break;
2734 case PCH_DP_D:
5eddb70b 2735 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2736 break;
2737 default:
2738 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2739 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2740 break;
32f9d658 2741 }
2c07245f 2742
5eddb70b 2743 I915_WRITE(reg, temp);
6be4a607 2744 }
b52eb4dc 2745
040484af 2746 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2747}
2748
2749static void ironlake_crtc_enable(struct drm_crtc *crtc)
2750{
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int pipe = intel_crtc->pipe;
2755 int plane = intel_crtc->plane;
2756 u32 temp;
2757 bool is_pch_port;
2758
2759 if (intel_crtc->active)
2760 return;
2761
2762 intel_crtc->active = true;
2763 intel_update_watermarks(dev);
2764
2765 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2766 temp = I915_READ(PCH_LVDS);
2767 if ((temp & LVDS_PORT_EN) == 0)
2768 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2769 }
2770
2771 is_pch_port = intel_crtc_driving_pch(crtc);
2772
2773 if (is_pch_port)
357555c0 2774 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2775 else
2776 ironlake_fdi_disable(crtc);
2777
2778 /* Enable panel fitting for LVDS */
2779 if (dev_priv->pch_pf_size &&
2780 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2781 /* Force use of hard-coded filter coefficients
2782 * as some pre-programmed values are broken,
2783 * e.g. x201.
2784 */
9db4a9c7
JB		 2785 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2786 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2787 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2788 }
2789
2790 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2791 intel_enable_plane(dev_priv, plane, pipe);
2792
2793 if (is_pch_port)
2794 ironlake_pch_enable(crtc);
c98e9dcf 2795
6be4a607 2796 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2797
2798 mutex_lock(&dev->struct_mutex);
bed4a673 2799 intel_update_fbc(dev);
d1ebd816
BW		 2800 mutex_unlock(&dev->struct_mutex);
2801
6b383a7f 2802 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2803}
2804
2805static void ironlake_crtc_disable(struct drm_crtc *crtc)
2806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 int plane = intel_crtc->plane;
5eddb70b 2812 u32 reg, temp;
b52eb4dc 2813
f7abfe8b
CW		 2814 if (!intel_crtc->active)
2815 return;
2816
e6c3a2a6 2817 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2818 drm_vblank_off(dev, pipe);
6b383a7f 2819 intel_crtc_update_cursor(crtc, false);
5eddb70b 2820
b24e7179 2821 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2822
6be4a607
JB		 2823 if (dev_priv->cfb_plane == plane &&
2824 dev_priv->display.disable_fbc)
2825 dev_priv->display.disable_fbc(dev);
2c07245f 2826
b24e7179 2827 intel_disable_pipe(dev_priv, pipe);
32f9d658 2828
6be4a607 2829 /* Disable PF */
9db4a9c7
JB		 2830 I915_WRITE(PF_CTL(pipe), 0);
2831 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2832
0fc932b8 2833 ironlake_fdi_disable(crtc);
2c07245f 2834
47a05eca
JB		 2835 /* This is a horrible layering violation; we should be doing this in
2836 * the connector/encoder ->prepare instead, but we don't always have
2837 * enough information there about the config to know whether it will
2838 * actually be necessary or just cause undesired flicker.
2839 */
2840 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2841
040484af 2842 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2843
6be4a607
JB		 2844 if (HAS_PCH_CPT(dev)) {
2845 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2846 reg = TRANS_DP_CTL(pipe);
2847 temp = I915_READ(reg);
2848 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2849 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2850 I915_WRITE(reg, temp);
6be4a607
JB		 2851
2852 /* disable DPLL_SEL */
2853 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2854 switch (pipe) {
2855 case 0:
2856 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2857 break;
2858 case 1:
6be4a607 2859 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2860 break;
2861 case 2:
2862 /* FIXME: manage transcoder PLLs? */
2863 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2864 break;
2865 default:
2866 BUG(); /* wtf */
2867 }
6be4a607 2868 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2869 }
e3421a18 2870
6be4a607 2871 /* disable PCH DPLL */
92f2584a 2872 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2873
6be4a607 2874 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2878
6be4a607 2879 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2883
2884 POSTING_READ(reg);
6be4a607 2885 udelay(100);
8db9d77b 2886
5eddb70b
CW		 2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2890
6be4a607 2891 /* Wait for the clocks to turn off. */
5eddb70b 2892 POSTING_READ(reg);
6be4a607 2893 udelay(100);
6b383a7f 2894
f7abfe8b 2895 intel_crtc->active = false;
6b383a7f 2896 intel_update_watermarks(dev);
d1ebd816
BW		 2897
2898 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2899 intel_update_fbc(dev);
2900 intel_clear_scanline_wait(dev);
d1ebd816 2901 mutex_unlock(&dev->struct_mutex);
6be4a607 2902}
1b3c7a47 2903
6be4a607
JB		 2904static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2905{
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 int pipe = intel_crtc->pipe;
2908 int plane = intel_crtc->plane;
8db9d77b 2909
6be4a607
JB		 2910 /* XXX: When our outputs are all unaware of DPMS modes other than off
2911 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2912 */
2913 switch (mode) {
2914 case DRM_MODE_DPMS_ON:
2915 case DRM_MODE_DPMS_STANDBY:
2916 case DRM_MODE_DPMS_SUSPEND:
2917 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2918 ironlake_crtc_enable(crtc);
2919 break;
1b3c7a47 2920
6be4a607
JB		 2921 case DRM_MODE_DPMS_OFF:
2922 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2923 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2924 break;
2925 }
2926}
2927
02e792fb
DV		 2928static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2929{
02e792fb 2930 if (!enable && intel_crtc->overlay) {
23f09ce3 2931 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2932 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2933
23f09ce3 2934 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2935 dev_priv->mm.interruptible = false;
2936 (void) intel_overlay_switch_off(intel_crtc->overlay);
2937 dev_priv->mm.interruptible = true;
23f09ce3 2938 mutex_unlock(&dev->struct_mutex);
02e792fb 2939 }
02e792fb 2940
5dcdbcb0
CW		 2941 /* Let userspace switch the overlay on again. In most cases userspace
2942 * has to recompute where to put it anyway.
2943 */
02e792fb
DV		 2944}
2945
0b8765c6 2946static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2947{
2948 struct drm_device *dev = crtc->dev;
79e53945
JB		 2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
80824003 2952 int plane = intel_crtc->plane;
79e53945 2953
f7abfe8b
CW		 2954 if (intel_crtc->active)
2955 return;
2956
2957 intel_crtc->active = true;
6b383a7f
CW		 2958 intel_update_watermarks(dev);
2959
63d7bbe9 2960 intel_enable_pll(dev_priv, pipe);
040484af 2961 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2962 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2963
0b8765c6 2964 intel_crtc_load_lut(crtc);
bed4a673 2965 intel_update_fbc(dev);
79e53945 2966
0b8765c6
JB		 2967 /* Give the overlay scaler a chance to enable if it's on this pipe */
2968 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2969 intel_crtc_update_cursor(crtc, true);
0b8765c6 2970}
79e53945 2971
0b8765c6
JB		 2972static void i9xx_crtc_disable(struct drm_crtc *crtc)
2973{
2974 struct drm_device *dev = crtc->dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2977 int pipe = intel_crtc->pipe;
2978 int plane = intel_crtc->plane;
b690e96c 2979
f7abfe8b
CW		 2980 if (!intel_crtc->active)
2981 return;
2982
0b8765c6 2983 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2984 intel_crtc_wait_for_pending_flips(crtc);
2985 drm_vblank_off(dev, pipe);
0b8765c6 2986 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2987 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2988
2989 if (dev_priv->cfb_plane == plane &&
2990 dev_priv->display.disable_fbc)
2991 dev_priv->display.disable_fbc(dev);
79e53945 2992
b24e7179 2993 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2994 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2995 intel_disable_pll(dev_priv, pipe);
0b8765c6 2996
f7abfe8b 2997 intel_crtc->active = false;
6b383a7f
CW		 2998 intel_update_fbc(dev);
2999 intel_update_watermarks(dev);
3000 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3001}
3002
3003static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3004{
3005 /* XXX: When our outputs are all unaware of DPMS modes other than off
3006 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3007 */
3008 switch (mode) {
3009 case DRM_MODE_DPMS_ON:
3010 case DRM_MODE_DPMS_STANDBY:
3011 case DRM_MODE_DPMS_SUSPEND:
3012 i9xx_crtc_enable(crtc);
3013 break;
3014 case DRM_MODE_DPMS_OFF:
3015 i9xx_crtc_disable(crtc);
79e53945
JB		 3016 break;
3017 }
2c07245f
ZW		 3018}
3019
3020/**
3021 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3022 */
3023static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3024{
3025 struct drm_device *dev = crtc->dev;
e70236a8 3026 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3027 struct drm_i915_master_private *master_priv;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
3030 bool enabled;
3031
032d2a0d
CW		 3032 if (intel_crtc->dpms_mode == mode)
3033 return;
3034
65655d4a 3035 intel_crtc->dpms_mode = mode;
debcaddc 3036
e70236a8 3037 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3038
3039 if (!dev->primary->master)
3040 return;
3041
3042 master_priv = dev->primary->master->driver_priv;
3043 if (!master_priv->sarea_priv)
3044 return;
3045
3046 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3047
3048 switch (pipe) {
3049 case 0:
3050 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3051 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3052 break;
3053 case 1:
3054 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3055 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3056 break;
3057 default:
9db4a9c7 3058 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3059 break;
3060 }
79e53945
JB		 3061}
3062
cdd59983
CW		 3063static void intel_crtc_disable(struct drm_crtc *crtc)
3064{
3065 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3066 struct drm_device *dev = crtc->dev;
3067
3068 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3069
3070 if (crtc->fb) {
3071 mutex_lock(&dev->struct_mutex);
3072 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3073 mutex_unlock(&dev->struct_mutex);
3074 }
3075}
3076
7e7d76c3
JB		 3077/* Prepare for a mode set.
3078 *
3079 * Note we could be a lot smarter here. We need to figure out which outputs
3080 * will be enabled, which disabled (in short, how the config will changes)
3081 * and perform the minimum necessary steps to accomplish that, e.g. updating
3082 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3083 * panel fitting is in the proper state, etc.
3084 */
3085static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3086{
7e7d76c3 3087 i9xx_crtc_disable(crtc);
79e53945
JB		 3088}
3089
7e7d76c3 3090static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3091{
7e7d76c3 3092 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3093}
3094
3095static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3096{
7e7d76c3 3097 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3098}
3099
3100static void ironlake_crtc_commit(struct drm_crtc *crtc)
3101{
7e7d76c3 3102 ironlake_crtc_enable(crtc);
79e53945
JB		 3103}
3104
3105void intel_encoder_prepare (struct drm_encoder *encoder)
3106{
3107 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3108 /* lvds has its own version of prepare see intel_lvds_prepare */
3109 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3110}
3111
3112void intel_encoder_commit (struct drm_encoder *encoder)
3113{
3114 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3115 /* lvds has its own version of commit see intel_lvds_commit */
3116 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3117}
3118
ea5b213a
CW		 3119void intel_encoder_destroy(struct drm_encoder *encoder)
3120{
4ef69c7a 3121 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3122
ea5b213a
CW		 3123 drm_encoder_cleanup(encoder);
3124 kfree(intel_encoder);
3125}
3126
79e53945
JB		 3127static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3128 struct drm_display_mode *mode,
3129 struct drm_display_mode *adjusted_mode)
3130{
2c07245f 3131 struct drm_device *dev = crtc->dev;
89749350 3132
bad720ff 3133 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3134 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3135 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3136 return false;
2c07245f 3137 }
89749350
CW		 3138
3139 /* XXX some encoders set the crtcinfo, others don't.
3140 * Obviously we need some form of conflict resolution here...
3141 */
3142 if (adjusted_mode->crtc_htotal == 0)
3143 drm_mode_set_crtcinfo(adjusted_mode, 0);
3144
79e53945
JB		 3145 return true;
3146}
3147
e70236a8
JB		 3148static int i945_get_display_clock_speed(struct drm_device *dev)
3149{
3150 return 400000;
3151}
79e53945 3152
e70236a8 3153static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3154{
e70236a8
JB		 3155 return 333000;
3156}
79e53945 3157
e70236a8
JB		 3158static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3159{
3160 return 200000;
3161}
79e53945 3162
e70236a8
JB		 3163static int i915gm_get_display_clock_speed(struct drm_device *dev)
3164{
3165 u16 gcfgc = 0;
79e53945 3166
e70236a8
JB		 3167 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3168
3169 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3170 return 133000;
3171 else {
3172 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3173 case GC_DISPLAY_CLOCK_333_MHZ:
3174 return 333000;
3175 default:
3176 case GC_DISPLAY_CLOCK_190_200_MHZ:
3177 return 190000;
79e53945 3178 }
e70236a8
JB		 3179 }
3180}
3181
3182static int i865_get_display_clock_speed(struct drm_device *dev)
3183{
3184 return 266000;
3185}
3186
3187static int i855_get_display_clock_speed(struct drm_device *dev)
3188{
3189 u16 hpllcc = 0;
3190 /* Assume that the hardware is in the high speed state. This
3191 * should be the default.
3192 */
3193 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3194 case GC_CLOCK_133_200:
3195 case GC_CLOCK_100_200:
3196 return 200000;
3197 case GC_CLOCK_166_250:
3198 return 250000;
3199 case GC_CLOCK_100_133:
79e53945 3200 return 133000;
e70236a8 3201 }
79e53945 3202
e70236a8
JB		 3203 /* Shouldn't happen */
3204 return 0;
3205}
79e53945 3206
e70236a8
JB		 3207static int i830_get_display_clock_speed(struct drm_device *dev)
3208{
3209 return 133000;
79e53945
JB		 3210}
3211
2c07245f
ZW		 3212struct fdi_m_n {
3213 u32 tu;
3214 u32 gmch_m;
3215 u32 gmch_n;
3216 u32 link_m;
3217 u32 link_n;
3218};
3219
3220static void
3221fdi_reduce_ratio(u32 *num, u32 *den)
3222{
3223 while (*num > 0xffffff || *den > 0xffffff) {
3224 *num >>= 1;
3225 *den >>= 1;
3226 }
3227}
3228
2c07245f 3229static void
f2b115e6
AJ		 3230ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3231 int link_clock, struct fdi_m_n *m_n)
2c07245f 3232{
2c07245f
ZW		 3233 m_n->tu = 64; /* default size */
3234
22ed1113
CW		 3235 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3236 m_n->gmch_m = bits_per_pixel * pixel_clock;
3237 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3238 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3239
22ed1113
CW		 3240 m_n->link_m = pixel_clock;
3241 m_n->link_n = link_clock;
2c07245f
ZW		 3242 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3243}
3244
3245
7662c8bd
SL		 3246struct intel_watermark_params {
3247 unsigned long fifo_size;
3248 unsigned long max_wm;
3249 unsigned long default_wm;
3250 unsigned long guard_size;
3251 unsigned long cacheline_size;
3252};
3253
f2b115e6 3254/* Pineview has different values for various configs */
d210246a 3255static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3256 PINEVIEW_DISPLAY_FIFO,
3257 PINEVIEW_MAX_WM,
3258 PINEVIEW_DFT_WM,
3259 PINEVIEW_GUARD_WM,
3260 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3261};
d210246a 3262static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3263 PINEVIEW_DISPLAY_FIFO,
3264 PINEVIEW_MAX_WM,
3265 PINEVIEW_DFT_HPLLOFF_WM,
3266 PINEVIEW_GUARD_WM,
3267 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3268};
d210246a 3269static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3270 PINEVIEW_CURSOR_FIFO,
3271 PINEVIEW_CURSOR_MAX_WM,
3272 PINEVIEW_CURSOR_DFT_WM,
3273 PINEVIEW_CURSOR_GUARD_WM,
3274 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3275};
d210246a 3276static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3277 PINEVIEW_CURSOR_FIFO,
3278 PINEVIEW_CURSOR_MAX_WM,
3279 PINEVIEW_CURSOR_DFT_WM,
3280 PINEVIEW_CURSOR_GUARD_WM,
3281 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3282};
d210246a 3283static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3284 G4X_FIFO_SIZE,
3285 G4X_MAX_WM,
3286 G4X_MAX_WM,
3287 2,
3288 G4X_FIFO_LINE_SIZE,
3289};
d210246a 3290static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3291 I965_CURSOR_FIFO,
3292 I965_CURSOR_MAX_WM,
3293 I965_CURSOR_DFT_WM,
3294 2,
3295 G4X_FIFO_LINE_SIZE,
3296};
d210246a 3297static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3298 I965_CURSOR_FIFO,
3299 I965_CURSOR_MAX_WM,
3300 I965_CURSOR_DFT_WM,
3301 2,
3302 I915_FIFO_LINE_SIZE,
3303};
d210246a 3304static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3305 I945_FIFO_SIZE,
7662c8bd
SL		 3306 I915_MAX_WM,
3307 1,
dff33cfc
JB		 3308 2,
3309 I915_FIFO_LINE_SIZE
7662c8bd 3310};
d210246a 3311static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3312 I915_FIFO_SIZE,
7662c8bd
SL		 3313 I915_MAX_WM,
3314 1,
dff33cfc 3315 2,
7662c8bd
SL		 3316 I915_FIFO_LINE_SIZE
3317};
d210246a 3318static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3319 I855GM_FIFO_SIZE,
3320 I915_MAX_WM,
3321 1,
dff33cfc 3322 2,
7662c8bd
SL		 3323 I830_FIFO_LINE_SIZE
3324};
d210246a 3325static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3326 I830_FIFO_SIZE,
3327 I915_MAX_WM,
3328 1,
dff33cfc 3329 2,
7662c8bd
SL		 3330 I830_FIFO_LINE_SIZE
3331};
3332
d210246a 3333static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3334 ILK_DISPLAY_FIFO,
3335 ILK_DISPLAY_MAXWM,
3336 ILK_DISPLAY_DFTWM,
3337 2,
3338 ILK_FIFO_LINE_SIZE
3339};
d210246a 3340static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3341 ILK_CURSOR_FIFO,
3342 ILK_CURSOR_MAXWM,
3343 ILK_CURSOR_DFTWM,
3344 2,
3345 ILK_FIFO_LINE_SIZE
3346};
d210246a 3347static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3348 ILK_DISPLAY_SR_FIFO,
3349 ILK_DISPLAY_MAX_SRWM,
3350 ILK_DISPLAY_DFT_SRWM,
3351 2,
3352 ILK_FIFO_LINE_SIZE
3353};
d210246a 3354static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3355 ILK_CURSOR_SR_FIFO,
3356 ILK_CURSOR_MAX_SRWM,
3357 ILK_CURSOR_DFT_SRWM,
3358 2,
3359 ILK_FIFO_LINE_SIZE
3360};
3361
d210246a 3362static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3363 SNB_DISPLAY_FIFO,
3364 SNB_DISPLAY_MAXWM,
3365 SNB_DISPLAY_DFTWM,
3366 2,
3367 SNB_FIFO_LINE_SIZE
3368};
d210246a 3369static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3370 SNB_CURSOR_FIFO,
3371 SNB_CURSOR_MAXWM,
3372 SNB_CURSOR_DFTWM,
3373 2,
3374 SNB_FIFO_LINE_SIZE
3375};
d210246a 3376static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3377 SNB_DISPLAY_SR_FIFO,
3378 SNB_DISPLAY_MAX_SRWM,
3379 SNB_DISPLAY_DFT_SRWM,
3380 2,
3381 SNB_FIFO_LINE_SIZE
3382};
d210246a 3383static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3384 SNB_CURSOR_SR_FIFO,
3385 SNB_CURSOR_MAX_SRWM,
3386 SNB_CURSOR_DFT_SRWM,
3387 2,
3388 SNB_FIFO_LINE_SIZE
3389};
3390
3391
dff33cfc
JB		 3392/**
3393 * intel_calculate_wm - calculate watermark level
3394 * @clock_in_khz: pixel clock
3395 * @wm: chip FIFO params
3396 * @pixel_size: display pixel size
3397 * @latency_ns: memory latency for the platform
3398 *
3399 * Calculate the watermark level (the level at which the display plane will
3400 * start fetching from memory again). Each chip has a different display
3401 * FIFO size and allocation, so the caller needs to figure that out and pass
3402 * in the correct intel_watermark_params structure.
3403 *
3404 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3405 * on the pixel size. When it reaches the watermark level, it'll start
3406 * fetching FIFO line sized based chunks from memory until the FIFO fills
3407 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3408 * will occur, and a display engine hang could result.
3409 */
7662c8bd 3410static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3411 const struct intel_watermark_params *wm,
3412 int fifo_size,
7662c8bd
SL		 3413 int pixel_size,
3414 unsigned long latency_ns)
3415{
390c4dd4 3416 long entries_required, wm_size;
dff33cfc 3417
d660467c
JB		 3418 /*
3419 * Note: we need to make sure we don't overflow for various clock &
3420 * latency values.
3421 * clocks go from a few thousand to several hundred thousand.
3422 * latency is usually a few thousand
3423 */
3424 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3425 1000;
8de9b311 3426 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3427
bbb0aef5 3428 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3429
d210246a 3430 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3431
bbb0aef5 3432 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3433
390c4dd4
JB		 3434 /* Don't promote wm_size to unsigned... */
3435 if (wm_size > (long)wm->max_wm)
7662c8bd 3436 wm_size = wm->max_wm;
c3add4b6 3437 if (wm_size <= 0)
7662c8bd
SL		 3438 wm_size = wm->default_wm;
3439 return wm_size;
3440}
3441
3442struct cxsr_latency {
3443 int is_desktop;
95534263 3444 int is_ddr3;
7662c8bd
SL		 3445 unsigned long fsb_freq;
3446 unsigned long mem_freq;
3447 unsigned long display_sr;
3448 unsigned long display_hpll_disable;
3449 unsigned long cursor_sr;
3450 unsigned long cursor_hpll_disable;
3451};
3452
403c89ff 3453static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3454 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3455 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3456 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3457 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3458 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3459
3460 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3461 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3462 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3463 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3464 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3465
3466 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3467 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3468 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3469 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3470 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3471
3472 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3473 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3474 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3475 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3476 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3477
3478 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3479 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3480 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3481 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3482 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3483
3484 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3485 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3486 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3487 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3488 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3489};
3490
403c89ff
CW		 3491static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3492 int is_ddr3,
3493 int fsb,
3494 int mem)
7662c8bd 3495{
403c89ff 3496 const struct cxsr_latency *latency;
7662c8bd 3497 int i;
7662c8bd
SL		 3498
3499 if (fsb == 0 || mem == 0)
3500 return NULL;
3501
3502 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3503 latency = &cxsr_latency_table[i];
3504 if (is_desktop == latency->is_desktop &&
95534263 3505 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3506 fsb == latency->fsb_freq && mem == latency->mem_freq)
3507 return latency;
7662c8bd 3508 }
decbbcda 3509
28c97730 3510 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3511
3512 return NULL;
7662c8bd
SL		 3513}
3514
f2b115e6 3515static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3516{
3517 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3518
3519 /* deactivate cxsr */
3e33d94d 3520 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3521}
3522
bcc24fb4
JB		 3523/*
3524 * Latency for FIFO fetches is dependent on several factors:
3525 * - memory configuration (speed, channels)
3526 * - chipset
3527 * - current MCH state
3528 * It can be fairly high in some situations, so here we assume a fairly
3529 * pessimal value. It's a tradeoff between extra memory fetches (if we
3530 * set this value too high, the FIFO will fetch frequently to stay full)
3531 * and power consumption (set it too low to save power and we might see
3532 * FIFO underruns and display "flicker").
3533 *
3534 * A value of 5us seems to be a good balance; safe for very low end
3535 * platforms but not overly aggressive on lower latency configs.
3536 */
69e302a9 3537static const int latency_ns = 5000;
7662c8bd 3538
e70236a8 3539static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3540{
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 uint32_t dsparb = I915_READ(DSPARB);
3543 int size;
3544
8de9b311
CW		 3545 size = dsparb & 0x7f;
3546 if (plane)
3547 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3548
28c97730 3549 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3550 plane ? "B" : "A", size);
dff33cfc
JB		 3551
3552 return size;
3553}
7662c8bd 3554
e70236a8
JB		 3555static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3556{
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 uint32_t dsparb = I915_READ(DSPARB);
3559 int size;
3560
8de9b311
CW		 3561 size = dsparb & 0x1ff;
3562 if (plane)
3563 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3564 size >>= 1; /* Convert to cachelines */
dff33cfc 3565
28c97730 3566 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3567 plane ? "B" : "A", size);
dff33cfc
JB		 3568
3569 return size;
3570}
7662c8bd 3571
e70236a8
JB		 3572static int i845_get_fifo_size(struct drm_device *dev, int plane)
3573{
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 uint32_t dsparb = I915_READ(DSPARB);
3576 int size;
3577
3578 size = dsparb & 0x7f;
3579 size >>= 2; /* Convert to cachelines */
3580
28c97730 3581 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3582 plane ? "B" : "A",
3583 size);
e70236a8
JB		 3584
3585 return size;
3586}
3587
3588static int i830_get_fifo_size(struct drm_device *dev, int plane)
3589{
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3591 uint32_t dsparb = I915_READ(DSPARB);
3592 int size;
3593
3594 size = dsparb & 0x7f;
3595 size >>= 1; /* Convert to cachelines */
3596
28c97730 3597 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3598 plane ? "B" : "A", size);
e70236a8
JB		 3599
3600 return size;
3601}
3602
d210246a
CW		 3603static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3604{
3605 struct drm_crtc *crtc, *enabled = NULL;
3606
3607 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3608 if (crtc->enabled && crtc->fb) {
3609 if (enabled)
3610 return NULL;
3611 enabled = crtc;
3612 }
3613 }
3614
3615 return enabled;
3616}
3617
3618static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3619{
3620 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3621 struct drm_crtc *crtc;
403c89ff 3622 const struct cxsr_latency *latency;
d4294342
ZY		 3623 u32 reg;
3624 unsigned long wm;
d4294342 3625
403c89ff 3626 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3627 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3628 if (!latency) {
3629 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3630 pineview_disable_cxsr(dev);
3631 return;
3632 }
3633
d210246a
CW		 3634 crtc = single_enabled_crtc(dev);
3635 if (crtc) {
3636 int clock = crtc->mode.clock;
3637 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3638
3639 /* Display SR */
d210246a
CW		 3640 wm = intel_calculate_wm(clock, &pineview_display_wm,
3641 pineview_display_wm.fifo_size,
d4294342
ZY		 3642 pixel_size, latency->display_sr);
3643 reg = I915_READ(DSPFW1);
3644 reg &= ~DSPFW_SR_MASK;
3645 reg |= wm << DSPFW_SR_SHIFT;
3646 I915_WRITE(DSPFW1, reg);
3647 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3648
3649 /* cursor SR */
d210246a
CW		 3650 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3651 pineview_display_wm.fifo_size,
d4294342
ZY		 3652 pixel_size, latency->cursor_sr);
3653 reg = I915_READ(DSPFW3);
3654 reg &= ~DSPFW_CURSOR_SR_MASK;
3655 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3656 I915_WRITE(DSPFW3, reg);
3657
3658 /* Display HPLL off SR */
d210246a
CW		 3659 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3660 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3661 pixel_size, latency->display_hpll_disable);
3662 reg = I915_READ(DSPFW3);
3663 reg &= ~DSPFW_HPLL_SR_MASK;
3664 reg |= wm & DSPFW_HPLL_SR_MASK;
3665 I915_WRITE(DSPFW3, reg);
3666
3667 /* cursor HPLL off SR */
d210246a
CW		 3668 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3669 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3670 pixel_size, latency->cursor_hpll_disable);
3671 reg = I915_READ(DSPFW3);
3672 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3673 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3674 I915_WRITE(DSPFW3, reg);
3675 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3676
3677 /* activate cxsr */
3e33d94d
CW		 3678 I915_WRITE(DSPFW3,
3679 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3680 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3681 } else {
3682 pineview_disable_cxsr(dev);
3683 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3684 }
3685}
3686
417ae147
CW		 3687static bool g4x_compute_wm0(struct drm_device *dev,
3688 int plane,
3689 const struct intel_watermark_params *display,
3690 int display_latency_ns,
3691 const struct intel_watermark_params *cursor,
3692 int cursor_latency_ns,
3693 int *plane_wm,
3694 int *cursor_wm)
3695{
3696 struct drm_crtc *crtc;
3697 int htotal, hdisplay, clock, pixel_size;
3698 int line_time_us, line_count;
3699 int entries, tlb_miss;
3700
3701 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3702 if (crtc->fb == NULL || !crtc->enabled) {
3703 *cursor_wm = cursor->guard_size;
3704 *plane_wm = display->guard_size;
417ae147 3705 return false;
5c72d064 3706 }
417ae147
CW		 3707
3708 htotal = crtc->mode.htotal;
3709 hdisplay = crtc->mode.hdisplay;
3710 clock = crtc->mode.clock;
3711 pixel_size = crtc->fb->bits_per_pixel / 8;
3712
3713 /* Use the small buffer method to calculate plane watermark */
3714 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3715 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3716 if (tlb_miss > 0)
3717 entries += tlb_miss;
3718 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3719 *plane_wm = entries + display->guard_size;
3720 if (*plane_wm > (int)display->max_wm)
3721 *plane_wm = display->max_wm;
3722
3723 /* Use the large buffer method to calculate cursor watermark */
3724 line_time_us = ((htotal * 1000) / clock);
3725 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3726 entries = line_count * 64 * pixel_size;
3727 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3728 if (tlb_miss > 0)
3729 entries += tlb_miss;
3730 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3731 *cursor_wm = entries + cursor->guard_size;
3732 if (*cursor_wm > (int)cursor->max_wm)
3733 *cursor_wm = (int)cursor->max_wm;
3734
3735 return true;
3736}
3737
3738/*
3739 * Check the wm result.
3740 *
3741 * If any calculated watermark values is larger than the maximum value that
3742 * can be programmed into the associated watermark register, that watermark
3743 * must be disabled.
3744 */
3745static bool g4x_check_srwm(struct drm_device *dev,
3746 int display_wm, int cursor_wm,
3747 const struct intel_watermark_params *display,
3748 const struct intel_watermark_params *cursor)
652c393a 3749{
417ae147
CW		 3750 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3751 display_wm, cursor_wm);
652c393a 3752
417ae147 3753 if (display_wm > display->max_wm) {
bbb0aef5 3754 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3755 display_wm, display->max_wm);
3756 return false;
3757 }
0e442c60 3758
417ae147 3759 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3760 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3761 cursor_wm, cursor->max_wm);
3762 return false;
3763 }
0e442c60 3764
417ae147
CW		 3765 if (!(display_wm || cursor_wm)) {
3766 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3767 return false;
3768 }
0e442c60 3769
417ae147
CW		 3770 return true;
3771}
0e442c60 3772
417ae147 3773static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3774 int plane,
3775 int latency_ns,
417ae147
CW		 3776 const struct intel_watermark_params *display,
3777 const struct intel_watermark_params *cursor,
3778 int *display_wm, int *cursor_wm)
3779{
d210246a
CW		 3780 struct drm_crtc *crtc;
3781 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3782 unsigned long line_time_us;
3783 int line_count, line_size;
3784 int small, large;
3785 int entries;
0e442c60 3786
417ae147
CW		 3787 if (!latency_ns) {
3788 *display_wm = *cursor_wm = 0;
3789 return false;
3790 }
0e442c60 3791
d210246a
CW		 3792 crtc = intel_get_crtc_for_plane(dev, plane);
3793 hdisplay = crtc->mode.hdisplay;
3794 htotal = crtc->mode.htotal;
3795 clock = crtc->mode.clock;
3796 pixel_size = crtc->fb->bits_per_pixel / 8;
3797
417ae147
CW		 3798 line_time_us = (htotal * 1000) / clock;
3799 line_count = (latency_ns / line_time_us + 1000) / 1000;
3800 line_size = hdisplay * pixel_size;
0e442c60 3801
417ae147
CW		 3802 /* Use the minimum of the small and large buffer method for primary */
3803 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3804 large = line_count * line_size;
0e442c60 3805
417ae147
CW		 3806 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3807 *display_wm = entries + display->guard_size;
4fe5e611 3808
417ae147
CW		 3809 /* calculate the self-refresh watermark for display cursor */
3810 entries = line_count * pixel_size * 64;
3811 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3812 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3813
417ae147
CW		 3814 return g4x_check_srwm(dev,
3815 *display_wm, *cursor_wm,
3816 display, cursor);
3817}
4fe5e611 3818
7ccb4a53 3819#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3820
3821static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3822{
3823 static const int sr_latency_ns = 12000;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3826 int plane_sr, cursor_sr;
3827 unsigned int enabled = 0;
417ae147
CW		 3828
3829 if (g4x_compute_wm0(dev, 0,
3830 &g4x_wm_info, latency_ns,
3831 &g4x_cursor_wm_info, latency_ns,
3832 &planea_wm, &cursora_wm))
d210246a 3833 enabled |= 1;
417ae147
CW		 3834
3835 if (g4x_compute_wm0(dev, 1,
3836 &g4x_wm_info, latency_ns,
3837 &g4x_cursor_wm_info, latency_ns,
3838 &planeb_wm, &cursorb_wm))
d210246a 3839 enabled |= 2;
417ae147
CW		 3840
3841 plane_sr = cursor_sr = 0;
d210246a
CW		 3842 if (single_plane_enabled(enabled) &&
3843 g4x_compute_srwm(dev, ffs(enabled) - 1,
3844 sr_latency_ns,
417ae147
CW		 3845 &g4x_wm_info,
3846 &g4x_cursor_wm_info,
3847 &plane_sr, &cursor_sr))
0e442c60 3848 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3849 else
3850 I915_WRITE(FW_BLC_SELF,
3851 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3852
308977ac
CW		 3853 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3854 planea_wm, cursora_wm,
3855 planeb_wm, cursorb_wm,
3856 plane_sr, cursor_sr);
0e442c60 3857
417ae147
CW		 3858 I915_WRITE(DSPFW1,
3859 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3860 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3861 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3862 planea_wm);
3863 I915_WRITE(DSPFW2,
3864 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3865 (cursora_wm << DSPFW_CURSORA_SHIFT));
3866 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3867 I915_WRITE(DSPFW3,
3868 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3869 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3870}
3871
d210246a 3872static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3873{
3874 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3875 struct drm_crtc *crtc;
3876 int srwm = 1;
4fe5e611 3877 int cursor_sr = 16;
1dc7546d
JB		 3878
3879 /* Calc sr entries for one plane configs */
d210246a
CW		 3880 crtc = single_enabled_crtc(dev);
3881 if (crtc) {
1dc7546d 3882 /* self-refresh has much higher latency */
69e302a9 3883 static const int sr_latency_ns = 12000;
d210246a
CW		 3884 int clock = crtc->mode.clock;
3885 int htotal = crtc->mode.htotal;
3886 int hdisplay = crtc->mode.hdisplay;
3887 int pixel_size = crtc->fb->bits_per_pixel / 8;
3888 unsigned long line_time_us;
3889 int entries;
1dc7546d 3890
d210246a 3891 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3892
3893 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3894 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3895 pixel_size * hdisplay;
3896 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3897 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3898 if (srwm < 0)
3899 srwm = 1;
1b07e04e 3900 srwm &= 0x1ff;
308977ac
CW		 3901 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3902 entries, srwm);
4fe5e611 3903
d210246a 3904 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3905 pixel_size * 64;
d210246a 3906 entries = DIV_ROUND_UP(entries,
8de9b311 3907 i965_cursor_wm_info.cacheline_size);
4fe5e611 3908 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3909 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3910
3911 if (cursor_sr > i965_cursor_wm_info.max_wm)
3912 cursor_sr = i965_cursor_wm_info.max_wm;
3913
3914 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3915 "cursor %d\n", srwm, cursor_sr);
3916
a6c45cf0 3917 if (IS_CRESTLINE(dev))
adcdbc66 3918 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3919 } else {
3920 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3921 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3922 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3923 & ~FW_BLC_SELF_EN);
1dc7546d 3924 }
7662c8bd 3925
1dc7546d
JB		 3926 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3927 srwm);
7662c8bd
SL		 3928
3929 /* 965 has limitations... */
417ae147
CW		 3930 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3931 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3932 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3933 /* update cursor SR watermark */
3934 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3935}
3936
d210246a 3937static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3938{
3939 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3940 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3941 uint32_t fwater_lo;
3942 uint32_t fwater_hi;
d210246a
CW		 3943 int cwm, srwm = 1;
3944 int fifo_size;
dff33cfc 3945 int planea_wm, planeb_wm;
d210246a 3946 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3947
72557b4f 3948 if (IS_I945GM(dev))
d210246a 3949 wm_info = &i945_wm_info;
a6c45cf0 3950 else if (!IS_GEN2(dev))
d210246a 3951 wm_info = &i915_wm_info;
7662c8bd 3952 else
d210246a
CW		 3953 wm_info = &i855_wm_info;
3954
3955 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3956 crtc = intel_get_crtc_for_plane(dev, 0);
3957 if (crtc->enabled && crtc->fb) {
3958 planea_wm = intel_calculate_wm(crtc->mode.clock,
3959 wm_info, fifo_size,
3960 crtc->fb->bits_per_pixel / 8,
3961 latency_ns);
3962 enabled = crtc;
3963 } else
3964 planea_wm = fifo_size - wm_info->guard_size;
3965
3966 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3967 crtc = intel_get_crtc_for_plane(dev, 1);
3968 if (crtc->enabled && crtc->fb) {
3969 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3970 wm_info, fifo_size,
3971 crtc->fb->bits_per_pixel / 8,
3972 latency_ns);
3973 if (enabled == NULL)
3974 enabled = crtc;
3975 else
3976 enabled = NULL;
3977 } else
3978 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3979
28c97730 3980 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3981
3982 /*
3983 * Overlay gets an aggressive default since video jitter is bad.
3984 */
3985 cwm = 2;
3986
18b2190c
AL		 3987 /* Play safe and disable self-refresh before adjusting watermarks. */
3988 if (IS_I945G(dev) || IS_I945GM(dev))
3989 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3990 else if (IS_I915GM(dev))
3991 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3992
dff33cfc 3993 /* Calc sr entries for one plane configs */
d210246a 3994 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3995 /* self-refresh has much higher latency */
69e302a9 3996 static const int sr_latency_ns = 6000;
d210246a
CW		 3997 int clock = enabled->mode.clock;
3998 int htotal = enabled->mode.htotal;
3999 int hdisplay = enabled->mode.hdisplay;
4000 int pixel_size = enabled->fb->bits_per_pixel / 8;
4001 unsigned long line_time_us;
4002 int entries;
dff33cfc 4003
d210246a 4004 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4005
4006 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4007 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4008 pixel_size * hdisplay;
4009 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4010 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4011 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4012 if (srwm < 0)
4013 srwm = 1;
ee980b80
LP		 4014
4015 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4016 I915_WRITE(FW_BLC_SELF,
4017 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4018 else if (IS_I915GM(dev))
ee980b80 4019 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4020 }
4021
28c97730 4022 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4023 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4024
dff33cfc
JB		 4025 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4026 fwater_hi = (cwm & 0x1f);
4027
4028 /* Set request length to 8 cachelines per fetch */
4029 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4030 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4031
4032 I915_WRITE(FW_BLC, fwater_lo);
4033 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4034
d210246a
CW		 4035 if (HAS_FW_BLC(dev)) {
4036 if (enabled) {
4037 if (IS_I945G(dev) || IS_I945GM(dev))
4038 I915_WRITE(FW_BLC_SELF,
4039 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4040 else if (IS_I915GM(dev))
4041 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4042 DRM_DEBUG_KMS("memory self refresh enabled\n");
4043 } else
4044 DRM_DEBUG_KMS("memory self refresh disabled\n");
4045 }
7662c8bd
SL		 4046}
4047
d210246a 4048static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4049{
4050 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4051 struct drm_crtc *crtc;
4052 uint32_t fwater_lo;
dff33cfc 4053 int planea_wm;
7662c8bd 4054
d210246a
CW		 4055 crtc = single_enabled_crtc(dev);
4056 if (crtc == NULL)
4057 return;
7662c8bd 4058
d210246a
CW		 4059 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4060 dev_priv->display.get_fifo_size(dev, 0),
4061 crtc->fb->bits_per_pixel / 8,
4062 latency_ns);
4063 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4064 fwater_lo |= (3<<8) | planea_wm;
4065
28c97730 4066 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4067
4068 I915_WRITE(FW_BLC, fwater_lo);
4069}
4070
7f8a8569 4071#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4072#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4073
1398261a
YL		 4074/*
4075 * Check the wm result.
4076 *
4077 * If any calculated watermark values is larger than the maximum value that
4078 * can be programmed into the associated watermark register, that watermark
4079 * must be disabled.
1398261a 4080 */
b79d4990
JB		 4081static bool ironlake_check_srwm(struct drm_device *dev, int level,
4082 int fbc_wm, int display_wm, int cursor_wm,
4083 const struct intel_watermark_params *display,
4084 const struct intel_watermark_params *cursor)
1398261a
YL		 4085{
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087
4088 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4089 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4090
4091 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4092 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4093 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4094
4095 /* fbc has it's own way to disable FBC WM */
4096 I915_WRITE(DISP_ARB_CTL,
4097 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4098 return false;
4099 }
4100
b79d4990 4101 if (display_wm > display->max_wm) {
1398261a 4102 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4103 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4104 return false;
4105 }
4106
b79d4990 4107 if (cursor_wm > cursor->max_wm) {
1398261a 4108 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4109 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4110 return false;
4111 }
4112
4113 if (!(fbc_wm || display_wm || cursor_wm)) {
4114 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4115 return false;
4116 }
4117
4118 return true;
4119}
4120
4121/*
4122 * Compute watermark values of WM[1-3],
4123 */
d210246a
CW		 4124static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4125 int latency_ns,
b79d4990
JB		 4126 const struct intel_watermark_params *display,
4127 const struct intel_watermark_params *cursor,
4128 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4129{
d210246a 4130 struct drm_crtc *crtc;
1398261a 4131 unsigned long line_time_us;
d210246a 4132 int hdisplay, htotal, pixel_size, clock;
b79d4990 4133 int line_count, line_size;
1398261a
YL		 4134 int small, large;
4135 int entries;
1398261a
YL		 4136
4137 if (!latency_ns) {
4138 *fbc_wm = *display_wm = *cursor_wm = 0;
4139 return false;
4140 }
4141
d210246a
CW		 4142 crtc = intel_get_crtc_for_plane(dev, plane);
4143 hdisplay = crtc->mode.hdisplay;
4144 htotal = crtc->mode.htotal;
4145 clock = crtc->mode.clock;
4146 pixel_size = crtc->fb->bits_per_pixel / 8;
4147
1398261a
YL		 4148 line_time_us = (htotal * 1000) / clock;
4149 line_count = (latency_ns / line_time_us + 1000) / 1000;
4150 line_size = hdisplay * pixel_size;
4151
4152 /* Use the minimum of the small and large buffer method for primary */
4153 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4154 large = line_count * line_size;
4155
b79d4990
JB		 4156 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4157 *display_wm = entries + display->guard_size;
1398261a
YL		 4158
4159 /*
b79d4990 4160 * Spec says:
1398261a
YL		 4161 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4162 */
4163 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4164
4165 /* calculate the self-refresh watermark for display cursor */
4166 entries = line_count * pixel_size * 64;
b79d4990
JB		 4167 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4168 *cursor_wm = entries + cursor->guard_size;
1398261a 4169
b79d4990
JB		 4170 return ironlake_check_srwm(dev, level,
4171 *fbc_wm, *display_wm, *cursor_wm,
4172 display, cursor);
4173}
4174
d210246a 4175static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4176{
4177 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4178 int fbc_wm, plane_wm, cursor_wm;
4179 unsigned int enabled;
b79d4990
JB		 4180
4181 enabled = 0;
9f405100
CW		 4182 if (g4x_compute_wm0(dev, 0,
4183 &ironlake_display_wm_info,
4184 ILK_LP0_PLANE_LATENCY,
4185 &ironlake_cursor_wm_info,
4186 ILK_LP0_CURSOR_LATENCY,
4187 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4188 I915_WRITE(WM0_PIPEA_ILK,
4189 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4190 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4191 " plane %d, " "cursor: %d\n",
4192 plane_wm, cursor_wm);
d210246a 4193 enabled |= 1;
b79d4990
JB		 4194 }
4195
9f405100
CW		 4196 if (g4x_compute_wm0(dev, 1,
4197 &ironlake_display_wm_info,
4198 ILK_LP0_PLANE_LATENCY,
4199 &ironlake_cursor_wm_info,
4200 ILK_LP0_CURSOR_LATENCY,
4201 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4202 I915_WRITE(WM0_PIPEB_ILK,
4203 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4204 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4205 " plane %d, cursor: %d\n",
4206 plane_wm, cursor_wm);
d210246a 4207 enabled |= 2;
b79d4990
JB		 4208 }
4209
4210 /*
4211 * Calculate and update the self-refresh watermark only when one
4212 * display plane is used.
4213 */
4214 I915_WRITE(WM3_LP_ILK, 0);
4215 I915_WRITE(WM2_LP_ILK, 0);
4216 I915_WRITE(WM1_LP_ILK, 0);
4217
d210246a 4218 if (!single_plane_enabled(enabled))
b79d4990 4219 return;
d210246a 4220 enabled = ffs(enabled) - 1;
b79d4990
JB		 4221
4222 /* WM1 */
d210246a
CW		 4223 if (!ironlake_compute_srwm(dev, 1, enabled,
4224 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4225 &ironlake_display_srwm_info,
4226 &ironlake_cursor_srwm_info,
4227 &fbc_wm, &plane_wm, &cursor_wm))
4228 return;
4229
4230 I915_WRITE(WM1_LP_ILK,
4231 WM1_LP_SR_EN |
4232 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4233 (fbc_wm << WM1_LP_FBC_SHIFT) |
4234 (plane_wm << WM1_LP_SR_SHIFT) |
4235 cursor_wm);
4236
4237 /* WM2 */
d210246a
CW		 4238 if (!ironlake_compute_srwm(dev, 2, enabled,
4239 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4240 &ironlake_display_srwm_info,
4241 &ironlake_cursor_srwm_info,
4242 &fbc_wm, &plane_wm, &cursor_wm))
4243 return;
4244
4245 I915_WRITE(WM2_LP_ILK,
4246 WM2_LP_EN |
4247 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4248 (fbc_wm << WM1_LP_FBC_SHIFT) |
4249 (plane_wm << WM1_LP_SR_SHIFT) |
4250 cursor_wm);
4251
4252 /*
4253 * WM3 is unsupported on ILK, probably because we don't have latency
4254 * data for that power state
4255 */
1398261a
YL		 4256}
4257
d210246a 4258static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4259{
4260 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4261 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4262 int fbc_wm, plane_wm, cursor_wm;
4263 unsigned int enabled;
1398261a
YL		 4264
4265 enabled = 0;
9f405100
CW		 4266 if (g4x_compute_wm0(dev, 0,
4267 &sandybridge_display_wm_info, latency,
4268 &sandybridge_cursor_wm_info, latency,
4269 &plane_wm, &cursor_wm)) {
1398261a
YL		 4270 I915_WRITE(WM0_PIPEA_ILK,
4271 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4272 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4273 " plane %d, " "cursor: %d\n",
4274 plane_wm, cursor_wm);
d210246a 4275 enabled |= 1;
1398261a
YL		 4276 }
4277
9f405100
CW		 4278 if (g4x_compute_wm0(dev, 1,
4279 &sandybridge_display_wm_info, latency,
4280 &sandybridge_cursor_wm_info, latency,
4281 &plane_wm, &cursor_wm)) {
1398261a
YL		 4282 I915_WRITE(WM0_PIPEB_ILK,
4283 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4284 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4285 " plane %d, cursor: %d\n",
4286 plane_wm, cursor_wm);
d210246a 4287 enabled |= 2;
1398261a
YL		 4288 }
4289
4290 /*
4291 * Calculate and update the self-refresh watermark only when one
4292 * display plane is used.
4293 *
4294 * SNB support 3 levels of watermark.
4295 *
4296 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4297 * and disabled in the descending order
4298 *
4299 */
4300 I915_WRITE(WM3_LP_ILK, 0);
4301 I915_WRITE(WM2_LP_ILK, 0);
4302 I915_WRITE(WM1_LP_ILK, 0);
4303
d210246a 4304 if (!single_plane_enabled(enabled))
1398261a 4305 return;
d210246a 4306 enabled = ffs(enabled) - 1;
1398261a
YL		 4307
4308 /* WM1 */
d210246a
CW		 4309 if (!ironlake_compute_srwm(dev, 1, enabled,
4310 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4311 &sandybridge_display_srwm_info,
4312 &sandybridge_cursor_srwm_info,
4313 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4314 return;
4315
4316 I915_WRITE(WM1_LP_ILK,
4317 WM1_LP_SR_EN |
4318 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4319 (fbc_wm << WM1_LP_FBC_SHIFT) |
4320 (plane_wm << WM1_LP_SR_SHIFT) |
4321 cursor_wm);
4322
4323 /* WM2 */
d210246a
CW		 4324 if (!ironlake_compute_srwm(dev, 2, enabled,
4325 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4326 &sandybridge_display_srwm_info,
4327 &sandybridge_cursor_srwm_info,
4328 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4329 return;
4330
4331 I915_WRITE(WM2_LP_ILK,
4332 WM2_LP_EN |
4333 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4334 (fbc_wm << WM1_LP_FBC_SHIFT) |
4335 (plane_wm << WM1_LP_SR_SHIFT) |
4336 cursor_wm);
4337
4338 /* WM3 */
d210246a
CW		 4339 if (!ironlake_compute_srwm(dev, 3, enabled,
4340 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4341 &sandybridge_display_srwm_info,
4342 &sandybridge_cursor_srwm_info,
4343 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4344 return;
4345
4346 I915_WRITE(WM3_LP_ILK,
4347 WM3_LP_EN |
4348 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4349 (fbc_wm << WM1_LP_FBC_SHIFT) |
4350 (plane_wm << WM1_LP_SR_SHIFT) |
4351 cursor_wm);
4352}
4353
7662c8bd
SL		 4354/**
4355 * intel_update_watermarks - update FIFO watermark values based on current modes
4356 *
4357 * Calculate watermark values for the various WM regs based on current mode
4358 * and plane configuration.
4359 *
4360 * There are several cases to deal with here:
4361 * - normal (i.e. non-self-refresh)
4362 * - self-refresh (SR) mode
4363 * - lines are large relative to FIFO size (buffer can hold up to 2)
4364 * - lines are small relative to FIFO size (buffer can hold more than 2
4365 * lines), so need to account for TLB latency
4366 *
4367 * The normal calculation is:
4368 * watermark = dotclock * bytes per pixel * latency
4369 * where latency is platform & configuration dependent (we assume pessimal
4370 * values here).
4371 *
4372 * The SR calculation is:
4373 * watermark = (trunc(latency/line time)+1) * surface width *
4374 * bytes per pixel
4375 * where
4376 * line time = htotal / dotclock
fa143215 4377 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4378 * and latency is assumed to be high, as above.
4379 *
4380 * The final value programmed to the register should always be rounded up,
4381 * and include an extra 2 entries to account for clock crossings.
4382 *
4383 * We don't use the sprite, so we can ignore that. And on Crestline we have
4384 * to set the non-SR watermarks to 8.
5eddb70b 4385 */
7662c8bd
SL		 4386static void intel_update_watermarks(struct drm_device *dev)
4387{
e70236a8 4388 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4389
d210246a
CW		 4390 if (dev_priv->display.update_wm)
4391 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4392}
4393
a7615030
CW		 4394static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4395{
4396 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4397}
4398
5a354204
JB		 4399/**
4400 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4401 * @crtc: CRTC structure
4402 *
4403 * A pipe may be connected to one or more outputs. Based on the depth of the
4404 * attached framebuffer, choose a good color depth to use on the pipe.
4405 *
4406 * If possible, match the pipe depth to the fb depth. In some cases, this
4407 * isn't ideal, because the connected output supports a lesser or restricted
4408 * set of depths. Resolve that here:
4409 * LVDS typically supports only 6bpc, so clamp down in that case
4410 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4411 * Displays may support a restricted set as well, check EDID and clamp as
4412 * appropriate.
4413 *
4414 * RETURNS:
4415 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4416 * true if they don't match).
4417 */
4418static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4419 unsigned int *pipe_bpp)
4420{
4421 struct drm_device *dev = crtc->dev;
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423 struct drm_encoder *encoder;
4424 struct drm_connector *connector;
4425 unsigned int display_bpc = UINT_MAX, bpc;
4426
4427 /* Walk the encoders & connectors on this crtc, get min bpc */
4428 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4429 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4430
4431 if (encoder->crtc != crtc)
4432 continue;
4433
4434 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4435 unsigned int lvds_bpc;
4436
4437 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4438 LVDS_A3_POWER_UP)
4439 lvds_bpc = 8;
4440 else
4441 lvds_bpc = 6;
4442
4443 if (lvds_bpc < display_bpc) {
4444 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4445 display_bpc = lvds_bpc;
4446 }
4447 continue;
4448 }
4449
4450 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4451 /* Use VBT settings if we have an eDP panel */
4452 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4453
4454 if (edp_bpc < display_bpc) {
4455 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4456 display_bpc = edp_bpc;
4457 }
4458 continue;
4459 }
4460
4461 /* Not one of the known troublemakers, check the EDID */
4462 list_for_each_entry(connector, &dev->mode_config.connector_list,
4463 head) {
4464 if (connector->encoder != encoder)
4465 continue;
4466
4467 if (connector->display_info.bpc < display_bpc) {
4468 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4469 display_bpc = connector->display_info.bpc;
4470 }
4471 }
4472
4473 /*
4474 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4475 * through, clamp it down. (Note: >12bpc will be caught below.)
4476 */
4477 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4478 if (display_bpc > 8 && display_bpc < 12) {
4479 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4480 display_bpc = 12;
4481 } else {
4482 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4483 display_bpc = 8;
4484 }
4485 }
4486 }
4487
4488 /*
4489 * We could just drive the pipe at the highest bpc all the time and
4490 * enable dithering as needed, but that costs bandwidth. So choose
4491 * the minimum value that expresses the full color range of the fb but
4492 * also stays within the max display bpc discovered above.
4493 */
4494
4495 switch (crtc->fb->depth) {
4496 case 8:
4497 bpc = 8; /* since we go through a colormap */
4498 break;
4499 case 15:
4500 case 16:
4501 bpc = 6; /* min is 18bpp */
4502 break;
4503 case 24:
4504 bpc = min((unsigned int)8, display_bpc);
4505 break;
4506 case 30:
4507 bpc = min((unsigned int)10, display_bpc);
4508 break;
4509 case 48:
4510 bpc = min((unsigned int)12, display_bpc);
4511 break;
4512 default:
4513 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4514 bpc = min((unsigned int)8, display_bpc);
4515 break;
4516 }
4517
4518 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4519 bpc, display_bpc);
4520
4521 *pipe_bpp = bpc * 3;
4522
4523 return display_bpc != bpc;
4524}
4525
f564048e
EA		 4526static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4527 struct drm_display_mode *mode,
4528 struct drm_display_mode *adjusted_mode,
4529 int x, int y,
4530 struct drm_framebuffer *old_fb)
79e53945
JB		 4531{
4532 struct drm_device *dev = crtc->dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4535 int pipe = intel_crtc->pipe;
80824003 4536 int plane = intel_crtc->plane;
c751ce4f 4537 int refclk, num_connectors = 0;
652c393a 4538 intel_clock_t clock, reduced_clock;
5eddb70b 4539 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4540 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4541 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4542 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4543 struct intel_encoder *encoder;
d4906093 4544 const intel_limit_t *limit;
5c3b82e2 4545 int ret;
fae14981 4546 u32 temp;
aa9b500d 4547 u32 lvds_sync = 0;
79e53945 4548
5eddb70b
CW		 4549 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4550 if (encoder->base.crtc != crtc)
79e53945
JB		 4551 continue;
4552
5eddb70b 4553 switch (encoder->type) {
79e53945
JB		 4554 case INTEL_OUTPUT_LVDS:
4555 is_lvds = true;
4556 break;
4557 case INTEL_OUTPUT_SDVO:
7d57382e 4558 case INTEL_OUTPUT_HDMI:
79e53945 4559 is_sdvo = true;
5eddb70b 4560 if (encoder->needs_tv_clock)
e2f0ba97 4561 is_tv = true;
79e53945
JB		 4562 break;
4563 case INTEL_OUTPUT_DVO:
4564 is_dvo = true;
4565 break;
4566 case INTEL_OUTPUT_TVOUT:
4567 is_tv = true;
4568 break;
4569 case INTEL_OUTPUT_ANALOG:
4570 is_crt = true;
4571 break;
a4fc5ed6
KP		 4572 case INTEL_OUTPUT_DISPLAYPORT:
4573 is_dp = true;
4574 break;
79e53945 4575 }
43565a06 4576
c751ce4f 4577 num_connectors++;
79e53945
JB		 4578 }
4579
a7615030 4580 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4581 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4582 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4583 refclk / 1000);
a6c45cf0 4584 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4585 refclk = 96000;
4586 } else {
4587 refclk = 48000;
4588 }
4589
d4906093
ML		 4590 /*
4591 * Returns a set of divisors for the desired target clock with the given
4592 * refclk, or FALSE. The returned values represent the clock equation:
4593 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4594 */
1b894b59 4595 limit = intel_limit(crtc, refclk);
d4906093 4596 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4597 if (!ok) {
4598 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4599 return -EINVAL;
79e53945
JB		 4600 }
4601
cda4b7d3 4602 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4603 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4604
ddc9003c
ZY		 4605 if (is_lvds && dev_priv->lvds_downclock_avail) {
4606 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4607 dev_priv->lvds_downclock,
4608 refclk,
4609 &reduced_clock);
18f9ed12
ZY		 4610 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4611 /*
4612 * If the different P is found, it means that we can't
4613 * switch the display clock by using the FP0/FP1.
4614 * In such case we will disable the LVDS downclock
4615 * feature.
4616 */
4617 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4618 "LVDS clock/downclock\n");
18f9ed12
ZY		 4619 has_reduced_clock = 0;
4620 }
652c393a 4621 }
7026d4ac
ZW		 4622 /* SDVO TV has fixed PLL values depend on its clock range,
4623 this mirrors vbios setting. */
4624 if (is_sdvo && is_tv) {
4625 if (adjusted_mode->clock >= 100000
5eddb70b 4626 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4627 clock.p1 = 2;
4628 clock.p2 = 10;
4629 clock.n = 3;
4630 clock.m1 = 16;
4631 clock.m2 = 8;
4632 } else if (adjusted_mode->clock >= 140500
5eddb70b 4633 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4634 clock.p1 = 1;
4635 clock.p2 = 10;
4636 clock.n = 6;
4637 clock.m1 = 12;
4638 clock.m2 = 8;
4639 }
4640 }
4641
f2b115e6 4642 if (IS_PINEVIEW(dev)) {
2177832f 4643 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4644 if (has_reduced_clock)
4645 fp2 = (1 << reduced_clock.n) << 16 |
4646 reduced_clock.m1 << 8 | reduced_clock.m2;
4647 } else {
2177832f 4648 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4649 if (has_reduced_clock)
4650 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4651 reduced_clock.m2;
4652 }
79e53945 4653
929c77fb 4654 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4655
a6c45cf0 4656 if (!IS_GEN2(dev)) {
79e53945
JB		 4657 if (is_lvds)
4658 dpll |= DPLLB_MODE_LVDS;
4659 else
4660 dpll |= DPLLB_MODE_DAC_SERIAL;
4661 if (is_sdvo) {
6c9547ff
CW		 4662 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4663 if (pixel_multiplier > 1) {
4664 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4665 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4666 }
79e53945 4667 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4668 }
929c77fb 4669 if (is_dp)
a4fc5ed6 4670 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4671
4672 /* compute bitmask from p1 value */
f2b115e6
AJ		 4673 if (IS_PINEVIEW(dev))
4674 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4675 else {
2177832f 4676 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4677 if (IS_G4X(dev) && has_reduced_clock)
4678 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4679 }
79e53945
JB		 4680 switch (clock.p2) {
4681 case 5:
4682 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4683 break;
4684 case 7:
4685 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4686 break;
4687 case 10:
4688 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4689 break;
4690 case 14:
4691 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4692 break;
4693 }
929c77fb 4694 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4695 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4696 } else {
4697 if (is_lvds) {
4698 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4699 } else {
4700 if (clock.p1 == 2)
4701 dpll |= PLL_P1_DIVIDE_BY_TWO;
4702 else
4703 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4704 if (clock.p2 == 4)
4705 dpll |= PLL_P2_DIVIDE_BY_4;
4706 }
4707 }
4708
43565a06
KH		 4709 if (is_sdvo && is_tv)
4710 dpll |= PLL_REF_INPUT_TVCLKINBC;
4711 else if (is_tv)
79e53945 4712 /* XXX: just matching BIOS for now */
43565a06 4713 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4714 dpll |= 3;
a7615030 4715 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4716 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4717 else
4718 dpll |= PLL_REF_INPUT_DREFCLK;
4719
4720 /* setup pipeconf */
5eddb70b 4721 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4722
4723 /* Set up the display plane register */
4724 dspcntr = DISPPLANE_GAMMA_ENABLE;
4725
f2b115e6 4726 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4727 enable color space conversion */
929c77fb
EA		 4728 if (pipe == 0)
4729 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4730 else
4731 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4732
a6c45cf0 4733 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4734 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4735 * core speed.
4736 *
4737 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4738 * pipe == 0 check?
4739 */
e70236a8
JB		 4740 if (mode->clock >
4741 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4742 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4743 else
5eddb70b 4744 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4745 }
4746
929c77fb 4747 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4748
28c97730 4749 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4750 drm_mode_debug_printmodeline(mode);
4751
fae14981
EA		 4752 I915_WRITE(FP0(pipe), fp);
4753 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4754
fae14981 4755 POSTING_READ(DPLL(pipe));
c713bb08 4756 udelay(150);
8db9d77b 4757
79e53945
JB		 4758 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4759 * This is an exception to the general rule that mode_set doesn't turn
4760 * things on.
4761 */
4762 if (is_lvds) {
fae14981 4763 temp = I915_READ(LVDS);
5eddb70b 4764 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4765 if (pipe == 1) {
929c77fb 4766 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4767 } else {
929c77fb 4768 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4769 }
a3e17eb8 4770 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4771 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4772 /* Set the B0-B3 data pairs corresponding to whether we're going to
4773 * set the DPLLs for dual-channel mode or not.
4774 */
4775 if (clock.p2 == 7)
5eddb70b 4776 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4777 else
5eddb70b 4778 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4779
4780 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4781 * appropriately here, but we need to look more thoroughly into how
4782 * panels behave in the two modes.
4783 */
929c77fb
EA		 4784 /* set the dithering flag on LVDS as needed */
4785 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4786 if (dev_priv->lvds_dither)
5eddb70b 4787 temp |= LVDS_ENABLE_DITHER;
434ed097 4788 else
5eddb70b 4789 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4790 }
aa9b500d
BF		 4791 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4792 lvds_sync |= LVDS_HSYNC_POLARITY;
4793 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4794 lvds_sync |= LVDS_VSYNC_POLARITY;
4795 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4796 != lvds_sync) {
4797 char flags[2] = "-+";
4798 DRM_INFO("Changing LVDS panel from "
4799 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4800 flags[!(temp & LVDS_HSYNC_POLARITY)],
4801 flags[!(temp & LVDS_VSYNC_POLARITY)],
4802 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4803 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4804 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4805 temp |= lvds_sync;
4806 }
fae14981 4807 I915_WRITE(LVDS, temp);
79e53945 4808 }
434ed097 4809
929c77fb 4810 if (is_dp) {
a4fc5ed6 4811 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4812 }
4813
fae14981 4814 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4815
c713bb08 4816 /* Wait for the clocks to stabilize. */
fae14981 4817 POSTING_READ(DPLL(pipe));
c713bb08 4818 udelay(150);
32f9d658 4819
c713bb08
EA		 4820 if (INTEL_INFO(dev)->gen >= 4) {
4821 temp = 0;
4822 if (is_sdvo) {
4823 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4824 if (temp > 1)
4825 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4826 else
4827 temp = 0;
32f9d658 4828 }
c713bb08
EA		 4829 I915_WRITE(DPLL_MD(pipe), temp);
4830 } else {
4831 /* The pixel multiplier can only be updated once the
4832 * DPLL is enabled and the clocks are stable.
4833 *
4834 * So write it again.
4835 */
fae14981 4836 I915_WRITE(DPLL(pipe), dpll);
79e53945 4837 }
79e53945 4838
5eddb70b 4839 intel_crtc->lowfreq_avail = false;
652c393a 4840 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4841 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4842 intel_crtc->lowfreq_avail = true;
4843 if (HAS_PIPE_CXSR(dev)) {
28c97730 4844 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4845 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4846 }
4847 } else {
fae14981 4848 I915_WRITE(FP1(pipe), fp);
652c393a 4849 if (HAS_PIPE_CXSR(dev)) {
28c97730 4850 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4851 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4852 }
4853 }
4854
734b4157
KH		 4855 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4856 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4857 /* the chip adds 2 halflines automatically */
4858 adjusted_mode->crtc_vdisplay -= 1;
4859 adjusted_mode->crtc_vtotal -= 1;
4860 adjusted_mode->crtc_vblank_start -= 1;
4861 adjusted_mode->crtc_vblank_end -= 1;
4862 adjusted_mode->crtc_vsync_end -= 1;
4863 adjusted_mode->crtc_vsync_start -= 1;
4864 } else
4865 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4866
5eddb70b
CW		 4867 I915_WRITE(HTOTAL(pipe),
4868 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4869 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4870 I915_WRITE(HBLANK(pipe),
4871 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4872 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4873 I915_WRITE(HSYNC(pipe),
4874 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4875 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4876
4877 I915_WRITE(VTOTAL(pipe),
4878 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4879 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4880 I915_WRITE(VBLANK(pipe),
4881 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4882 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4883 I915_WRITE(VSYNC(pipe),
4884 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4885 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4886
4887 /* pipesrc and dspsize control the size that is scaled from,
4888 * which should always be the user's requested size.
79e53945 4889 */
929c77fb
EA		 4890 I915_WRITE(DSPSIZE(plane),
4891 ((mode->vdisplay - 1) << 16) |
4892 (mode->hdisplay - 1));
4893 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4894 I915_WRITE(PIPESRC(pipe),
4895 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4896
f564048e
EA		 4897 I915_WRITE(PIPECONF(pipe), pipeconf);
4898 POSTING_READ(PIPECONF(pipe));
929c77fb 4899 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4900
4901 intel_wait_for_vblank(dev, pipe);
4902
f564048e
EA		 4903 I915_WRITE(DSPCNTR(plane), dspcntr);
4904 POSTING_READ(DSPCNTR(plane));
284d9529 4905 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4906
4907 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4908
4909 intel_update_watermarks(dev);
4910
f564048e
EA		 4911 return ret;
4912}
4913
4914static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4915 struct drm_display_mode *mode,
4916 struct drm_display_mode *adjusted_mode,
4917 int x, int y,
4918 struct drm_framebuffer *old_fb)
79e53945
JB		 4919{
4920 struct drm_device *dev = crtc->dev;
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923 int pipe = intel_crtc->pipe;
80824003 4924 int plane = intel_crtc->plane;
c751ce4f 4925 int refclk, num_connectors = 0;
652c393a 4926 intel_clock_t clock, reduced_clock;
5eddb70b 4927 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4928 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4929 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4930 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4931 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4932 struct intel_encoder *encoder;
d4906093 4933 const intel_limit_t *limit;
5c3b82e2 4934 int ret;
2c07245f 4935 struct fdi_m_n m_n = {0};
fae14981 4936 u32 temp;
aa9b500d 4937 u32 lvds_sync = 0;
5a354204
JB		 4938 int target_clock, pixel_multiplier, lane, link_bw, factor;
4939 unsigned int pipe_bpp;
4940 bool dither;
79e53945 4941
5eddb70b
CW		 4942 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4943 if (encoder->base.crtc != crtc)
79e53945
JB		 4944 continue;
4945
5eddb70b 4946 switch (encoder->type) {
79e53945
JB		 4947 case INTEL_OUTPUT_LVDS:
4948 is_lvds = true;
4949 break;
4950 case INTEL_OUTPUT_SDVO:
7d57382e 4951 case INTEL_OUTPUT_HDMI:
79e53945 4952 is_sdvo = true;
5eddb70b 4953 if (encoder->needs_tv_clock)
e2f0ba97 4954 is_tv = true;
79e53945 4955 break;
79e53945
JB		 4956 case INTEL_OUTPUT_TVOUT:
4957 is_tv = true;
4958 break;
4959 case INTEL_OUTPUT_ANALOG:
4960 is_crt = true;
4961 break;
a4fc5ed6
KP		 4962 case INTEL_OUTPUT_DISPLAYPORT:
4963 is_dp = true;
4964 break;
32f9d658 4965 case INTEL_OUTPUT_EDP:
5eddb70b 4966 has_edp_encoder = encoder;
32f9d658 4967 break;
79e53945 4968 }
43565a06 4969
c751ce4f 4970 num_connectors++;
79e53945
JB		 4971 }
4972
a7615030 4973 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4974 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4975 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4976 refclk / 1000);
a07d6787 4977 } else {
79e53945 4978 refclk = 96000;
8febb297
EA		 4979 if (!has_edp_encoder ||
4980 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4981 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4982 }
4983
d4906093
ML		 4984 /*
4985 * Returns a set of divisors for the desired target clock with the given
4986 * refclk, or FALSE. The returned values represent the clock equation:
4987 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4988 */
1b894b59 4989 limit = intel_limit(crtc, refclk);
d4906093 4990 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4991 if (!ok) {
4992 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4993 return -EINVAL;
79e53945
JB		 4994 }
4995
cda4b7d3 4996 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4997 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4998
ddc9003c
ZY		 4999 if (is_lvds && dev_priv->lvds_downclock_avail) {
5000 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5001 dev_priv->lvds_downclock,
5002 refclk,
5003 &reduced_clock);
18f9ed12
ZY		 5004 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5005 /*
5006 * If the different P is found, it means that we can't
5007 * switch the display clock by using the FP0/FP1.
5008 * In such case we will disable the LVDS downclock
5009 * feature.
5010 */
5011 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5012 "LVDS clock/downclock\n");
18f9ed12
ZY		 5013 has_reduced_clock = 0;
5014 }
652c393a 5015 }
7026d4ac
ZW		 5016 /* SDVO TV has fixed PLL values depend on its clock range,
5017 this mirrors vbios setting. */
5018 if (is_sdvo && is_tv) {
5019 if (adjusted_mode->clock >= 100000
5eddb70b 5020 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5021 clock.p1 = 2;
5022 clock.p2 = 10;
5023 clock.n = 3;
5024 clock.m1 = 16;
5025 clock.m2 = 8;
5026 } else if (adjusted_mode->clock >= 140500
5eddb70b 5027 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5028 clock.p1 = 1;
5029 clock.p2 = 10;
5030 clock.n = 6;
5031 clock.m1 = 12;
5032 clock.m2 = 8;
5033 }
5034 }
5035
2c07245f 5036 /* FDI link */
8febb297
EA		 5037 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5038 lane = 0;
5039 /* CPU eDP doesn't require FDI link, so just set DP M/N
5040 according to current link config */
5041 if (has_edp_encoder &&
5042 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5043 target_clock = mode->clock;
5044 intel_edp_link_config(has_edp_encoder,
5045 &lane, &link_bw);
5046 } else {
5047 /* [e]DP over FDI requires target mode clock
5048 instead of link clock */
5049 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5050 target_clock = mode->clock;
8febb297
EA		 5051 else
5052 target_clock = adjusted_mode->clock;
5053
5054 /* FDI is a binary signal running at ~2.7GHz, encoding
5055 * each output octet as 10 bits. The actual frequency
5056 * is stored as a divider into a 100MHz clock, and the
5057 * mode pixel clock is stored in units of 1KHz.
5058 * Hence the bw of each lane in terms of the mode signal
5059 * is:
5060 */
5061 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5062 }
58a27471 5063
8febb297
EA		 5064 /* determine panel color depth */
5065 temp = I915_READ(PIPECONF(pipe));
5066 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5067 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5068 switch (pipe_bpp) {
5069 case 18:
5070 temp |= PIPE_6BPC;
8febb297 5071 break;
5a354204
JB		 5072 case 24:
5073 temp |= PIPE_8BPC;
8febb297 5074 break;
5a354204
JB		 5075 case 30:
5076 temp |= PIPE_10BPC;
8febb297 5077 break;
5a354204
JB		 5078 case 36:
5079 temp |= PIPE_12BPC;
8febb297
EA		 5080 break;
5081 default:
5a354204
JB		 5082 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5083 temp |= PIPE_8BPC;
5084 pipe_bpp = 24;
5085 break;
8febb297 5086 }
77ffb597 5087
5a354204
JB		 5088 intel_crtc->bpp = pipe_bpp;
5089 I915_WRITE(PIPECONF(pipe), temp);
5090
8febb297
EA		 5091 if (!lane) {
5092 /*
5093 * Account for spread spectrum to avoid
5094 * oversubscribing the link. Max center spread
5095 * is 2.5%; use 5% for safety's sake.
5096 */
5a354204 5097 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5098 lane = bps / (link_bw * 8) + 1;
5eb08b69 5099 }
2c07245f 5100
8febb297
EA		 5101 intel_crtc->fdi_lanes = lane;
5102
5103 if (pixel_multiplier > 1)
5104 link_bw *= pixel_multiplier;
5a354204
JB		 5105 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5106 &m_n);
8febb297 5107
c038e51e
ZW		 5108 /* Ironlake: try to setup display ref clock before DPLL
5109 * enabling. This is only under driver's control after
5110 * PCH B stepping, previous chipset stepping should be
5111 * ignoring this setting.
5112 */
8febb297
EA		 5113 temp = I915_READ(PCH_DREF_CONTROL);
5114 /* Always enable nonspread source */
5115 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5116 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5117 temp &= ~DREF_SSC_SOURCE_MASK;
5118 temp |= DREF_SSC_SOURCE_ENABLE;
5119 I915_WRITE(PCH_DREF_CONTROL, temp);
5120
5121 POSTING_READ(PCH_DREF_CONTROL);
5122 udelay(200);
fc9a2228 5123
8febb297
EA		 5124 if (has_edp_encoder) {
5125 if (intel_panel_use_ssc(dev_priv)) {
5126 temp |= DREF_SSC1_ENABLE;
fc9a2228 5127 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 5128
fc9a2228
CW		 5129 POSTING_READ(PCH_DREF_CONTROL);
5130 udelay(200);
5131 }
8febb297
EA		 5132 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133
5134 /* Enable CPU source on CPU attached eDP */
5135 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5136 if (intel_panel_use_ssc(dev_priv))
5137 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5138 else
5139 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5140 } else {
5141 /* Enable SSC on PCH eDP if needed */
5142 if (intel_panel_use_ssc(dev_priv)) {
5143 DRM_ERROR("enabling SSC on PCH\n");
5144 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5145 }
5146 }
5147 I915_WRITE(PCH_DREF_CONTROL, temp);
5148 POSTING_READ(PCH_DREF_CONTROL);
5149 udelay(200);
fc9a2228 5150 }
c038e51e 5151
a07d6787
EA		 5152 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5153 if (has_reduced_clock)
5154 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5155 reduced_clock.m2;
79e53945 5156
c1858123 5157 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5158 factor = 21;
5159 if (is_lvds) {
5160 if ((intel_panel_use_ssc(dev_priv) &&
5161 dev_priv->lvds_ssc_freq == 100) ||
5162 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5163 factor = 25;
5164 } else if (is_sdvo && is_tv)
5165 factor = 20;
c1858123 5166
8febb297
EA		 5167 if (clock.m1 < factor * clock.n)
5168 fp |= FP_CB_TUNE;
2c07245f 5169
5eddb70b 5170 dpll = 0;
2c07245f 5171
a07d6787
EA		 5172 if (is_lvds)
5173 dpll |= DPLLB_MODE_LVDS;
5174 else
5175 dpll |= DPLLB_MODE_DAC_SERIAL;
5176 if (is_sdvo) {
5177 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5178 if (pixel_multiplier > 1) {
5179 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5180 }
a07d6787
EA		 5181 dpll |= DPLL_DVO_HIGH_SPEED;
5182 }
5183 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5184 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5185
a07d6787
EA		 5186 /* compute bitmask from p1 value */
5187 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5188 /* also FPA1 */
5189 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5190
5191 switch (clock.p2) {
5192 case 5:
5193 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5194 break;
5195 case 7:
5196 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5197 break;
5198 case 10:
5199 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5200 break;
5201 case 14:
5202 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5203 break;
79e53945
JB		 5204 }
5205
43565a06
KH		 5206 if (is_sdvo && is_tv)
5207 dpll |= PLL_REF_INPUT_TVCLKINBC;
5208 else if (is_tv)
79e53945 5209 /* XXX: just matching BIOS for now */
43565a06 5210 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5211 dpll |= 3;
a7615030 5212 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5213 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5214 else
5215 dpll |= PLL_REF_INPUT_DREFCLK;
5216
5217 /* setup pipeconf */
5eddb70b 5218 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5219
5220 /* Set up the display plane register */
5221 dspcntr = DISPPLANE_GAMMA_ENABLE;
5222
28c97730 5223 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5224 drm_mode_debug_printmodeline(mode);
5225
5c5313c8
JB		 5226 /* PCH eDP needs FDI, but CPU eDP does not */
5227 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5228 I915_WRITE(PCH_FP0(pipe), fp);
5229 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5230
fae14981 5231 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5232 udelay(150);
5233 }
5234
8db9d77b
ZW		 5235 /* enable transcoder DPLL */
5236 if (HAS_PCH_CPT(dev)) {
5237 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5238 switch (pipe) {
5239 case 0:
5eddb70b 5240 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5241 break;
5242 case 1:
5eddb70b 5243 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5244 break;
5245 case 2:
5246 /* FIXME: manage transcoder PLLs? */
5247 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5248 break;
5249 default:
5250 BUG();
32f9d658 5251 }
8db9d77b 5252 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5253
5254 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5255 udelay(150);
5256 }
5257
79e53945
JB		 5258 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5259 * This is an exception to the general rule that mode_set doesn't turn
5260 * things on.
5261 */
5262 if (is_lvds) {
fae14981 5263 temp = I915_READ(PCH_LVDS);
5eddb70b 5264 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5265 if (pipe == 1) {
5266 if (HAS_PCH_CPT(dev))
5eddb70b 5267 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5268 else
5eddb70b 5269 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5270 } else {
5271 if (HAS_PCH_CPT(dev))
5eddb70b 5272 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5273 else
5eddb70b 5274 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5275 }
a3e17eb8 5276 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5277 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5278 /* Set the B0-B3 data pairs corresponding to whether we're going to
5279 * set the DPLLs for dual-channel mode or not.
5280 */
5281 if (clock.p2 == 7)
5eddb70b 5282 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5283 else
5eddb70b 5284 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5285
5286 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5287 * appropriately here, but we need to look more thoroughly into how
5288 * panels behave in the two modes.
5289 */
aa9b500d
BF		 5290 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5291 lvds_sync |= LVDS_HSYNC_POLARITY;
5292 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5293 lvds_sync |= LVDS_VSYNC_POLARITY;
5294 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5295 != lvds_sync) {
5296 char flags[2] = "-+";
5297 DRM_INFO("Changing LVDS panel from "
5298 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5299 flags[!(temp & LVDS_HSYNC_POLARITY)],
5300 flags[!(temp & LVDS_VSYNC_POLARITY)],
5301 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5302 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5303 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5304 temp |= lvds_sync;
5305 }
fae14981 5306 I915_WRITE(PCH_LVDS, temp);
79e53945 5307 }
434ed097 5308
8febb297
EA		 5309 pipeconf &= ~PIPECONF_DITHER_EN;
5310 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5311 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5312 pipeconf |= PIPECONF_DITHER_EN;
5313 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5314 }
5c5313c8 5315 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5316 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5317 } else {
8db9d77b 5318 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5319 I915_WRITE(TRANSDATA_M1(pipe), 0);
5320 I915_WRITE(TRANSDATA_N1(pipe), 0);
5321 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5322 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5323 }
79e53945 5324
8febb297
EA		 5325 if (!has_edp_encoder ||
5326 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5327 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5328
32f9d658 5329 /* Wait for the clocks to stabilize. */
fae14981 5330 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5331 udelay(150);
5332
8febb297
EA		 5333 /* The pixel multiplier can only be updated once the
5334 * DPLL is enabled and the clocks are stable.
5335 *
5336 * So write it again.
5337 */
fae14981 5338 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5339 }
79e53945 5340
5eddb70b 5341 intel_crtc->lowfreq_avail = false;
652c393a 5342 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5343 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5344 intel_crtc->lowfreq_avail = true;
5345 if (HAS_PIPE_CXSR(dev)) {
28c97730 5346 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5347 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5348 }
5349 } else {
fae14981 5350 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5351 if (HAS_PIPE_CXSR(dev)) {
28c97730 5352 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5353 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5354 }
5355 }
5356
734b4157
KH		 5357 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5358 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5359 /* the chip adds 2 halflines automatically */
5360 adjusted_mode->crtc_vdisplay -= 1;
5361 adjusted_mode->crtc_vtotal -= 1;
5362 adjusted_mode->crtc_vblank_start -= 1;
5363 adjusted_mode->crtc_vblank_end -= 1;
5364 adjusted_mode->crtc_vsync_end -= 1;
5365 adjusted_mode->crtc_vsync_start -= 1;
5366 } else
5367 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5368
5eddb70b
CW		 5369 I915_WRITE(HTOTAL(pipe),
5370 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5371 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5372 I915_WRITE(HBLANK(pipe),
5373 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5374 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5375 I915_WRITE(HSYNC(pipe),
5376 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5377 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5378
5379 I915_WRITE(VTOTAL(pipe),
5380 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5381 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5382 I915_WRITE(VBLANK(pipe),
5383 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5384 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5385 I915_WRITE(VSYNC(pipe),
5386 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5387 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5388
8febb297
EA		 5389 /* pipesrc controls the size that is scaled from, which should
5390 * always be the user's requested size.
79e53945 5391 */
5eddb70b
CW		 5392 I915_WRITE(PIPESRC(pipe),
5393 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5394
8febb297
EA		 5395 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5396 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5397 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5398 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5399
8febb297
EA		 5400 if (has_edp_encoder &&
5401 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5402 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5403 }
5404
5eddb70b
CW		 5405 I915_WRITE(PIPECONF(pipe), pipeconf);
5406 POSTING_READ(PIPECONF(pipe));
79e53945 5407
9d0498a2 5408 intel_wait_for_vblank(dev, pipe);
79e53945 5409
f00a3ddf 5410 if (IS_GEN5(dev)) {
553bd149
ZW		 5411 /* enable address swizzle for tiling buffer */
5412 temp = I915_READ(DISP_ARB_CTL);
5413 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5414 }
5415
5eddb70b 5416 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5417 POSTING_READ(DSPCNTR(plane));
79e53945 5418
5c3b82e2 5419 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5420
5421 intel_update_watermarks(dev);
5422
1f803ee5 5423 return ret;
79e53945
JB		 5424}
5425
f564048e
EA		 5426static int intel_crtc_mode_set(struct drm_crtc *crtc,
5427 struct drm_display_mode *mode,
5428 struct drm_display_mode *adjusted_mode,
5429 int x, int y,
5430 struct drm_framebuffer *old_fb)
5431{
5432 struct drm_device *dev = crtc->dev;
5433 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5435 int pipe = intel_crtc->pipe;
f564048e
EA		 5436 int ret;
5437
0b701d27 5438 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5439
f564048e
EA		 5440 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5441 x, y, old_fb);
7662c8bd 5442
79e53945 5443 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5444
1f803ee5 5445 return ret;
79e53945
JB		 5446}
5447
5448/** Loads the palette/gamma unit for the CRTC with the prepared values */
5449void intel_crtc_load_lut(struct drm_crtc *crtc)
5450{
5451 struct drm_device *dev = crtc->dev;
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5454 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5455 int i;
5456
5457 /* The clocks have to be on to load the palette. */
5458 if (!crtc->enabled)
5459 return;
5460
f2b115e6 5461 /* use legacy palette for Ironlake */
bad720ff 5462 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5463 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5464
79e53945
JB		 5465 for (i = 0; i < 256; i++) {
5466 I915_WRITE(palreg + 4 * i,
5467 (intel_crtc->lut_r[i] << 16) |
5468 (intel_crtc->lut_g[i] << 8) |
5469 intel_crtc->lut_b[i]);
5470 }
5471}
5472
560b85bb
CW		 5473static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5474{
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 bool visible = base != 0;
5479 u32 cntl;
5480
5481 if (intel_crtc->cursor_visible == visible)
5482 return;
5483
9db4a9c7 5484 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5485 if (visible) {
5486 /* On these chipsets we can only modify the base whilst
5487 * the cursor is disabled.
5488 */
9db4a9c7 5489 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5490
5491 cntl &= ~(CURSOR_FORMAT_MASK);
5492 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5493 cntl |= CURSOR_ENABLE |
5494 CURSOR_GAMMA_ENABLE |
5495 CURSOR_FORMAT_ARGB;
5496 } else
5497 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5498 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5499
5500 intel_crtc->cursor_visible = visible;
5501}
5502
5503static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5504{
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508 int pipe = intel_crtc->pipe;
5509 bool visible = base != 0;
5510
5511 if (intel_crtc->cursor_visible != visible) {
548f245b 5512 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5513 if (base) {
5514 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5515 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5516 cntl |= pipe << 28; /* Connect to correct pipe */
5517 } else {
5518 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5519 cntl |= CURSOR_MODE_DISABLE;
5520 }
9db4a9c7 5521 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5522
5523 intel_crtc->cursor_visible = visible;
5524 }
5525 /* and commit changes on next vblank */
9db4a9c7 5526 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5527}
5528
cda4b7d3 5529/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5530static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5531 bool on)
cda4b7d3
CW		 5532{
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536 int pipe = intel_crtc->pipe;
5537 int x = intel_crtc->cursor_x;
5538 int y = intel_crtc->cursor_y;
560b85bb 5539 u32 base, pos;
cda4b7d3
CW		 5540 bool visible;
5541
5542 pos = 0;
5543
6b383a7f 5544 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5545 base = intel_crtc->cursor_addr;
5546 if (x > (int) crtc->fb->width)
5547 base = 0;
5548
5549 if (y > (int) crtc->fb->height)
5550 base = 0;
5551 } else
5552 base = 0;
5553
5554 if (x < 0) {
5555 if (x + intel_crtc->cursor_width < 0)
5556 base = 0;
5557
5558 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5559 x = -x;
5560 }
5561 pos |= x << CURSOR_X_SHIFT;
5562
5563 if (y < 0) {
5564 if (y + intel_crtc->cursor_height < 0)
5565 base = 0;
5566
5567 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5568 y = -y;
5569 }
5570 pos |= y << CURSOR_Y_SHIFT;
5571
5572 visible = base != 0;
560b85bb 5573 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5574 return;
5575
9db4a9c7 5576 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5577 if (IS_845G(dev) || IS_I865G(dev))
5578 i845_update_cursor(crtc, base);
5579 else
5580 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5581
5582 if (visible)
5583 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5584}
5585
79e53945 5586static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5587 struct drm_file *file,
79e53945
JB		 5588 uint32_t handle,
5589 uint32_t width, uint32_t height)
5590{
5591 struct drm_device *dev = crtc->dev;
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5594 struct drm_i915_gem_object *obj;
cda4b7d3 5595 uint32_t addr;
3f8bc370 5596 int ret;
79e53945 5597
28c97730 5598 DRM_DEBUG_KMS("\n");
79e53945
JB		 5599
5600 /* if we want to turn off the cursor ignore width and height */
5601 if (!handle) {
28c97730 5602 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5603 addr = 0;
05394f39 5604 obj = NULL;
5004417d 5605 mutex_lock(&dev->struct_mutex);
3f8bc370 5606 goto finish;
79e53945
JB		 5607 }
5608
5609 /* Currently we only support 64x64 cursors */
5610 if (width != 64 || height != 64) {
5611 DRM_ERROR("we currently only support 64x64 cursors\n");
5612 return -EINVAL;
5613 }
5614
05394f39 5615 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5616 if (&obj->base == NULL)
79e53945
JB		 5617 return -ENOENT;
5618
05394f39 5619 if (obj->base.size < width * height * 4) {
79e53945 5620 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5621 ret = -ENOMEM;
5622 goto fail;
79e53945
JB		 5623 }
5624
71acb5eb 5625 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5626 mutex_lock(&dev->struct_mutex);
b295d1b6 5627 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5628 if (obj->tiling_mode) {
5629 DRM_ERROR("cursor cannot be tiled\n");
5630 ret = -EINVAL;
5631 goto fail_locked;
5632 }
5633
2da3b9b9 5634 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5635 if (ret) {
5636 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5637 goto fail_locked;
e7b526bb
CW		 5638 }
5639
d9e86c0e
CW		 5640 ret = i915_gem_object_put_fence(obj);
5641 if (ret) {
2da3b9b9 5642 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5643 goto fail_unpin;
5644 }
5645
05394f39 5646 addr = obj->gtt_offset;
71acb5eb 5647 } else {
6eeefaf3 5648 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5649 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5650 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5651 align);
71acb5eb
DA		 5652 if (ret) {
5653 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5654 goto fail_locked;
71acb5eb 5655 }
05394f39 5656 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5657 }
5658
a6c45cf0 5659 if (IS_GEN2(dev))
14b60391
JB		 5660 I915_WRITE(CURSIZE, (height << 12) | width);
5661
3f8bc370 5662 finish:
3f8bc370 5663 if (intel_crtc->cursor_bo) {
b295d1b6 5664 if (dev_priv->info->cursor_needs_physical) {
05394f39 5665 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5666 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5667 } else
5668 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5669 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5670 }
80824003 5671
7f9872e0 5672 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5673
5674 intel_crtc->cursor_addr = addr;
05394f39 5675 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5676 intel_crtc->cursor_width = width;
5677 intel_crtc->cursor_height = height;
5678
6b383a7f 5679 intel_crtc_update_cursor(crtc, true);
3f8bc370 5680
79e53945 5681 return 0;
e7b526bb 5682fail_unpin:
05394f39 5683 i915_gem_object_unpin(obj);
7f9872e0 5684fail_locked:
34b8686e 5685 mutex_unlock(&dev->struct_mutex);
bc9025bd 5686fail:
05394f39 5687 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5688 return ret;
79e53945
JB		 5689}
5690
5691static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5692{
79e53945 5693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5694
cda4b7d3
CW		 5695 intel_crtc->cursor_x = x;
5696 intel_crtc->cursor_y = y;
652c393a 5697
6b383a7f 5698 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5699
5700 return 0;
5701}
5702
5703/** Sets the color ramps on behalf of RandR */
5704void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5705 u16 blue, int regno)
5706{
5707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5708
5709 intel_crtc->lut_r[regno] = red >> 8;
5710 intel_crtc->lut_g[regno] = green >> 8;
5711 intel_crtc->lut_b[regno] = blue >> 8;
5712}
5713
b8c00ac5
DA		 5714void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5715 u16 *blue, int regno)
5716{
5717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5718
5719 *red = intel_crtc->lut_r[regno] << 8;
5720 *green = intel_crtc->lut_g[regno] << 8;
5721 *blue = intel_crtc->lut_b[regno] << 8;
5722}
5723
79e53945 5724static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5725 u16 *blue, uint32_t start, uint32_t size)
79e53945 5726{
7203425a 5727 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5729
7203425a 5730 for (i = start; i < end; i++) {
79e53945
JB		 5731 intel_crtc->lut_r[i] = red[i] >> 8;
5732 intel_crtc->lut_g[i] = green[i] >> 8;
5733 intel_crtc->lut_b[i] = blue[i] >> 8;
5734 }
5735
5736 intel_crtc_load_lut(crtc);
5737}
5738
5739/**
5740 * Get a pipe with a simple mode set on it for doing load-based monitor
5741 * detection.
5742 *
5743 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5744 * its requirements. The pipe will be connected to no other encoders.
79e53945 5745 *
c751ce4f 5746 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5747 * configured for it. In the future, it could choose to temporarily disable
5748 * some outputs to free up a pipe for its use.
5749 *
5750 * \return crtc, or NULL if no pipes are available.
5751 */
5752
5753/* VESA 640x480x72Hz mode to set on the pipe */
5754static struct drm_display_mode load_detect_mode = {
5755 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5756 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5757};
5758
d2dff872
CW		 5759static struct drm_framebuffer *
5760intel_framebuffer_create(struct drm_device *dev,
5761 struct drm_mode_fb_cmd *mode_cmd,
5762 struct drm_i915_gem_object *obj)
5763{
5764 struct intel_framebuffer *intel_fb;
5765 int ret;
5766
5767 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5768 if (!intel_fb) {
5769 drm_gem_object_unreference_unlocked(&obj->base);
5770 return ERR_PTR(-ENOMEM);
5771 }
5772
5773 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5774 if (ret) {
5775 drm_gem_object_unreference_unlocked(&obj->base);
5776 kfree(intel_fb);
5777 return ERR_PTR(ret);
5778 }
5779
5780 return &intel_fb->base;
5781}
5782
5783static u32
5784intel_framebuffer_pitch_for_width(int width, int bpp)
5785{
5786 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5787 return ALIGN(pitch, 64);
5788}
5789
5790static u32
5791intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5792{
5793 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5794 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5795}
5796
5797static struct drm_framebuffer *
5798intel_framebuffer_create_for_mode(struct drm_device *dev,
5799 struct drm_display_mode *mode,
5800 int depth, int bpp)
5801{
5802 struct drm_i915_gem_object *obj;
5803 struct drm_mode_fb_cmd mode_cmd;
5804
5805 obj = i915_gem_alloc_object(dev,
5806 intel_framebuffer_size_for_mode(mode, bpp));
5807 if (obj == NULL)
5808 return ERR_PTR(-ENOMEM);
5809
5810 mode_cmd.width = mode->hdisplay;
5811 mode_cmd.height = mode->vdisplay;
5812 mode_cmd.depth = depth;
5813 mode_cmd.bpp = bpp;
5814 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5815
5816 return intel_framebuffer_create(dev, &mode_cmd, obj);
5817}
5818
5819static struct drm_framebuffer *
5820mode_fits_in_fbdev(struct drm_device *dev,
5821 struct drm_display_mode *mode)
5822{
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 struct drm_i915_gem_object *obj;
5825 struct drm_framebuffer *fb;
5826
5827 if (dev_priv->fbdev == NULL)
5828 return NULL;
5829
5830 obj = dev_priv->fbdev->ifb.obj;
5831 if (obj == NULL)
5832 return NULL;
5833
5834 fb = &dev_priv->fbdev->ifb.base;
5835 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5836 fb->bits_per_pixel))
5837 return NULL;
5838
5839 if (obj->base.size < mode->vdisplay * fb->pitch)
5840 return NULL;
5841
5842 return fb;
5843}
5844
7173188d
CW		 5845bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5846 struct drm_connector *connector,
5847 struct drm_display_mode *mode,
8261b191 5848 struct intel_load_detect_pipe *old)
79e53945
JB		 5849{
5850 struct intel_crtc *intel_crtc;
5851 struct drm_crtc *possible_crtc;
4ef69c7a 5852 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5853 struct drm_crtc *crtc = NULL;
5854 struct drm_device *dev = encoder->dev;
d2dff872 5855 struct drm_framebuffer *old_fb;
79e53945
JB		 5856 int i = -1;
5857
d2dff872
CW		 5858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5859 connector->base.id, drm_get_connector_name(connector),
5860 encoder->base.id, drm_get_encoder_name(encoder));
5861
79e53945
JB		 5862 /*
5863 * Algorithm gets a little messy:
7a5e4805 5864 *
79e53945
JB		 5865 * - if the connector already has an assigned crtc, use it (but make
5866 * sure it's on first)
7a5e4805 5867 *
79e53945
JB		 5868 * - try to find the first unused crtc that can drive this connector,
5869 * and use that if we find one
79e53945
JB		 5870 */
5871
5872 /* See if we already have a CRTC for this connector */
5873 if (encoder->crtc) {
5874 crtc = encoder->crtc;
8261b191 5875
79e53945 5876 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5877 old->dpms_mode = intel_crtc->dpms_mode;
5878 old->load_detect_temp = false;
5879
5880 /* Make sure the crtc and connector are running */
79e53945 5881 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5882 struct drm_encoder_helper_funcs *encoder_funcs;
5883 struct drm_crtc_helper_funcs *crtc_funcs;
5884
79e53945
JB		 5885 crtc_funcs = crtc->helper_private;
5886 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5887
5888 encoder_funcs = encoder->helper_private;
79e53945
JB		 5889 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5890 }
8261b191 5891
7173188d 5892 return true;
79e53945
JB		 5893 }
5894
5895 /* Find an unused one (if possible) */
5896 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5897 i++;
5898 if (!(encoder->possible_crtcs & (1 << i)))
5899 continue;
5900 if (!possible_crtc->enabled) {
5901 crtc = possible_crtc;
5902 break;
5903 }
79e53945
JB		 5904 }
5905
5906 /*
5907 * If we didn't find an unused CRTC, don't use any.
5908 */
5909 if (!crtc) {
7173188d
CW		 5910 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5911 return false;
79e53945
JB		 5912 }
5913
5914 encoder->crtc = crtc;
c1c43977 5915 connector->encoder = encoder;
79e53945
JB		 5916
5917 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5918 old->dpms_mode = intel_crtc->dpms_mode;
5919 old->load_detect_temp = true;
d2dff872 5920 old->release_fb = NULL;
79e53945 5921
6492711d
CW		 5922 if (!mode)
5923 mode = &load_detect_mode;
79e53945 5924
d2dff872
CW		 5925 old_fb = crtc->fb;
5926
5927 /* We need a framebuffer large enough to accommodate all accesses
5928 * that the plane may generate whilst we perform load detection.
5929 * We can not rely on the fbcon either being present (we get called
5930 * during its initialisation to detect all boot displays, or it may
5931 * not even exist) or that it is large enough to satisfy the
5932 * requested mode.
5933 */
5934 crtc->fb = mode_fits_in_fbdev(dev, mode);
5935 if (crtc->fb == NULL) {
5936 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5937 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5938 old->release_fb = crtc->fb;
5939 } else
5940 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5941 if (IS_ERR(crtc->fb)) {
5942 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5943 crtc->fb = old_fb;
5944 return false;
79e53945 5945 }
79e53945 5946
d2dff872 5947 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5948 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5949 if (old->release_fb)
5950 old->release_fb->funcs->destroy(old->release_fb);
5951 crtc->fb = old_fb;
6492711d 5952 return false;
79e53945 5953 }
7173188d 5954
79e53945 5955 /* let the connector get through one full cycle before testing */
9d0498a2 5956 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5957
7173188d 5958 return true;
79e53945
JB		 5959}
5960
c1c43977 5961void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5962 struct drm_connector *connector,
5963 struct intel_load_detect_pipe *old)
79e53945 5964{
4ef69c7a 5965 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5966 struct drm_device *dev = encoder->dev;
5967 struct drm_crtc *crtc = encoder->crtc;
5968 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5969 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5970
d2dff872
CW		 5971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5972 connector->base.id, drm_get_connector_name(connector),
5973 encoder->base.id, drm_get_encoder_name(encoder));
5974
8261b191 5975 if (old->load_detect_temp) {
c1c43977 5976 connector->encoder = NULL;
79e53945 5977 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5978
5979 if (old->release_fb)
5980 old->release_fb->funcs->destroy(old->release_fb);
5981
0622a53c 5982 return;
79e53945
JB		 5983 }
5984
c751ce4f 5985 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5986 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5987 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5988 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5989 }
5990}
5991
5992/* Returns the clock of the currently programmed mode of the given pipe. */
5993static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5994{
5995 struct drm_i915_private *dev_priv = dev->dev_private;
5996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997 int pipe = intel_crtc->pipe;
548f245b 5998 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5999 u32 fp;
6000 intel_clock_t clock;
6001
6002 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6003 fp = I915_READ(FP0(pipe));
79e53945 6004 else
39adb7a5 6005 fp = I915_READ(FP1(pipe));
79e53945
JB		 6006
6007 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6008 if (IS_PINEVIEW(dev)) {
6009 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6010 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6011 } else {
6012 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6013 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6014 }
6015
a6c45cf0 6016 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6017 if (IS_PINEVIEW(dev))
6018 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6019 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6020 else
6021 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6022 DPLL_FPA01_P1_POST_DIV_SHIFT);
6023
6024 switch (dpll & DPLL_MODE_MASK) {
6025 case DPLLB_MODE_DAC_SERIAL:
6026 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6027 5 : 10;
6028 break;
6029 case DPLLB_MODE_LVDS:
6030 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6031 7 : 14;
6032 break;
6033 default:
28c97730 6034 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6035 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6036 return 0;
6037 }
6038
6039 /* XXX: Handle the 100Mhz refclk */
2177832f 6040 intel_clock(dev, 96000, &clock);
79e53945
JB		 6041 } else {
6042 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6043
6044 if (is_lvds) {
6045 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6046 DPLL_FPA01_P1_POST_DIV_SHIFT);
6047 clock.p2 = 14;
6048
6049 if ((dpll & PLL_REF_INPUT_MASK) ==
6050 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6051 /* XXX: might not be 66MHz */
2177832f 6052 intel_clock(dev, 66000, &clock);
79e53945 6053 } else
2177832f 6054 intel_clock(dev, 48000, &clock);
79e53945
JB		 6055 } else {
6056 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6057 clock.p1 = 2;
6058 else {
6059 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6060 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6061 }
6062 if (dpll & PLL_P2_DIVIDE_BY_4)
6063 clock.p2 = 4;
6064 else
6065 clock.p2 = 2;
6066
2177832f 6067 intel_clock(dev, 48000, &clock);
79e53945
JB		 6068 }
6069 }
6070
6071 /* XXX: It would be nice to validate the clocks, but we can't reuse
6072 * i830PllIsValid() because it relies on the xf86_config connector
6073 * configuration being accurate, which it isn't necessarily.
6074 */
6075
6076 return clock.dot;
6077}
6078
6079/** Returns the currently programmed mode of the given pipe. */
6080struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6081 struct drm_crtc *crtc)
6082{
548f245b 6083 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6085 int pipe = intel_crtc->pipe;
6086 struct drm_display_mode *mode;
548f245b
JB		 6087 int htot = I915_READ(HTOTAL(pipe));
6088 int hsync = I915_READ(HSYNC(pipe));
6089 int vtot = I915_READ(VTOTAL(pipe));
6090 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6091
6092 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6093 if (!mode)
6094 return NULL;
6095
6096 mode->clock = intel_crtc_clock_get(dev, crtc);
6097 mode->hdisplay = (htot & 0xffff) + 1;
6098 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6099 mode->hsync_start = (hsync & 0xffff) + 1;
6100 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6101 mode->vdisplay = (vtot & 0xffff) + 1;
6102 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6103 mode->vsync_start = (vsync & 0xffff) + 1;
6104 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6105
6106 drm_mode_set_name(mode);
6107 drm_mode_set_crtcinfo(mode, 0);
6108
6109 return mode;
6110}
6111
652c393a
JB		 6112#define GPU_IDLE_TIMEOUT 500 /* ms */
6113
6114/* When this timer fires, we've been idle for awhile */
6115static void intel_gpu_idle_timer(unsigned long arg)
6116{
6117 struct drm_device *dev = (struct drm_device *)arg;
6118 drm_i915_private_t *dev_priv = dev->dev_private;
6119
ff7ea4c0
CW		 6120 if (!list_empty(&dev_priv->mm.active_list)) {
6121 /* Still processing requests, so just re-arm the timer. */
6122 mod_timer(&dev_priv->idle_timer, jiffies +
6123 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6124 return;
6125 }
652c393a 6126
ff7ea4c0 6127 dev_priv->busy = false;
01dfba93 6128 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6129}
6130
652c393a
JB		 6131#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6132
6133static void intel_crtc_idle_timer(unsigned long arg)
6134{
6135 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6136 struct drm_crtc *crtc = &intel_crtc->base;
6137 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6138 struct intel_framebuffer *intel_fb;
652c393a 6139
ff7ea4c0
CW		 6140 intel_fb = to_intel_framebuffer(crtc->fb);
6141 if (intel_fb && intel_fb->obj->active) {
6142 /* The framebuffer is still being accessed by the GPU. */
6143 mod_timer(&intel_crtc->idle_timer, jiffies +
6144 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6145 return;
6146 }
652c393a 6147
ff7ea4c0 6148 intel_crtc->busy = false;
01dfba93 6149 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6150}
6151
3dec0095 6152static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6153{
6154 struct drm_device *dev = crtc->dev;
6155 drm_i915_private_t *dev_priv = dev->dev_private;
6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6158 int dpll_reg = DPLL(pipe);
6159 int dpll;
652c393a 6160
bad720ff 6161 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6162 return;
6163
6164 if (!dev_priv->lvds_downclock_avail)
6165 return;
6166
dbdc6479 6167 dpll = I915_READ(dpll_reg);
652c393a 6168 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6169 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6170
6171 /* Unlock panel regs */
dbdc6479
JB		 6172 I915_WRITE(PP_CONTROL,
6173 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6174
6175 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6176 I915_WRITE(dpll_reg, dpll);
9d0498a2 6177 intel_wait_for_vblank(dev, pipe);
dbdc6479 6178
652c393a
JB		 6179 dpll = I915_READ(dpll_reg);
6180 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6181 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6182
6183 /* ...and lock them again */
6184 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6185 }
6186
6187 /* Schedule downclock */
3dec0095
DV		 6188 mod_timer(&intel_crtc->idle_timer, jiffies +
6189 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6190}
6191
6192static void intel_decrease_pllclock(struct drm_crtc *crtc)
6193{
6194 struct drm_device *dev = crtc->dev;
6195 drm_i915_private_t *dev_priv = dev->dev_private;
6196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197 int pipe = intel_crtc->pipe;
9db4a9c7 6198 int dpll_reg = DPLL(pipe);
652c393a
JB		 6199 int dpll = I915_READ(dpll_reg);
6200
bad720ff 6201 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6202 return;
6203
6204 if (!dev_priv->lvds_downclock_avail)
6205 return;
6206
6207 /*
6208 * Since this is called by a timer, we should never get here in
6209 * the manual case.
6210 */
6211 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6212 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6213
6214 /* Unlock panel regs */
4a655f04
JB		 6215 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6216 PANEL_UNLOCK_REGS);
652c393a
JB		 6217
6218 dpll |= DISPLAY_RATE_SELECT_FPA1;
6219 I915_WRITE(dpll_reg, dpll);
9d0498a2 6220 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6221 dpll = I915_READ(dpll_reg);
6222 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6223 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6224
6225 /* ...and lock them again */
6226 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6227 }
6228
6229}
6230
6231/**
6232 * intel_idle_update - adjust clocks for idleness
6233 * @work: work struct
6234 *
6235 * Either the GPU or display (or both) went idle. Check the busy status
6236 * here and adjust the CRTC and GPU clocks as necessary.
6237 */
6238static void intel_idle_update(struct work_struct *work)
6239{
6240 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6241 idle_work);
6242 struct drm_device *dev = dev_priv->dev;
6243 struct drm_crtc *crtc;
6244 struct intel_crtc *intel_crtc;
6245
6246 if (!i915_powersave)
6247 return;
6248
6249 mutex_lock(&dev->struct_mutex);
6250
7648fa99
JB		 6251 i915_update_gfx_val(dev_priv);
6252
652c393a
JB		 6253 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6254 /* Skip inactive CRTCs */
6255 if (!crtc->fb)
6256 continue;
6257
6258 intel_crtc = to_intel_crtc(crtc);
6259 if (!intel_crtc->busy)
6260 intel_decrease_pllclock(crtc);
6261 }
6262
45ac22c8 6263
652c393a
JB		 6264 mutex_unlock(&dev->struct_mutex);
6265}
6266
6267/**
6268 * intel_mark_busy - mark the GPU and possibly the display busy
6269 * @dev: drm device
6270 * @obj: object we're operating on
6271 *
6272 * Callers can use this function to indicate that the GPU is busy processing
6273 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6274 * buffer), we'll also mark the display as busy, so we know to increase its
6275 * clock frequency.
6276 */
05394f39 6277void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6278{
6279 drm_i915_private_t *dev_priv = dev->dev_private;
6280 struct drm_crtc *crtc = NULL;
6281 struct intel_framebuffer *intel_fb;
6282 struct intel_crtc *intel_crtc;
6283
5e17ee74
ZW		 6284 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6285 return;
6286
18b2190c 6287 if (!dev_priv->busy)
28cf798f 6288 dev_priv->busy = true;
18b2190c 6289 else
28cf798f
CW		 6290 mod_timer(&dev_priv->idle_timer, jiffies +
6291 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6292
6293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6294 if (!crtc->fb)
6295 continue;
6296
6297 intel_crtc = to_intel_crtc(crtc);
6298 intel_fb = to_intel_framebuffer(crtc->fb);
6299 if (intel_fb->obj == obj) {
6300 if (!intel_crtc->busy) {
6301 /* Non-busy -> busy, upclock */
3dec0095 6302 intel_increase_pllclock(crtc);
652c393a
JB		 6303 intel_crtc->busy = true;
6304 } else {
6305 /* Busy -> busy, put off timer */
6306 mod_timer(&intel_crtc->idle_timer, jiffies +
6307 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6308 }
6309 }
6310 }
6311}
6312
79e53945
JB		 6313static void intel_crtc_destroy(struct drm_crtc *crtc)
6314{
6315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6316 struct drm_device *dev = crtc->dev;
6317 struct intel_unpin_work *work;
6318 unsigned long flags;
6319
6320 spin_lock_irqsave(&dev->event_lock, flags);
6321 work = intel_crtc->unpin_work;
6322 intel_crtc->unpin_work = NULL;
6323 spin_unlock_irqrestore(&dev->event_lock, flags);
6324
6325 if (work) {
6326 cancel_work_sync(&work->work);
6327 kfree(work);
6328 }
79e53945
JB		 6329
6330 drm_crtc_cleanup(crtc);
67e77c5a 6331
79e53945
JB		 6332 kfree(intel_crtc);
6333}
6334
6b95a207
KH		 6335static void intel_unpin_work_fn(struct work_struct *__work)
6336{
6337 struct intel_unpin_work *work =
6338 container_of(__work, struct intel_unpin_work, work);
6339
6340 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6341 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6342 drm_gem_object_unreference(&work->pending_flip_obj->base);
6343 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6344
6b95a207
KH		 6345 mutex_unlock(&work->dev->struct_mutex);
6346 kfree(work);
6347}
6348
1afe3e9d 6349static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6350 struct drm_crtc *crtc)
6b95a207
KH		 6351{
6352 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6354 struct intel_unpin_work *work;
05394f39 6355 struct drm_i915_gem_object *obj;
6b95a207 6356 struct drm_pending_vblank_event *e;
49b14a5c 6357 struct timeval tnow, tvbl;
6b95a207
KH		 6358 unsigned long flags;
6359
6360 /* Ignore early vblank irqs */
6361 if (intel_crtc == NULL)
6362 return;
6363
49b14a5c
MK		 6364 do_gettimeofday(&tnow);
6365
6b95a207
KH		 6366 spin_lock_irqsave(&dev->event_lock, flags);
6367 work = intel_crtc->unpin_work;
6368 if (work == NULL || !work->pending) {
6369 spin_unlock_irqrestore(&dev->event_lock, flags);
6370 return;
6371 }
6372
6373 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6374
6375 if (work->event) {
6376 e = work->event;
49b14a5c 6377 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6378
6379 /* Called before vblank count and timestamps have
6380 * been updated for the vblank interval of flip
6381 * completion? Need to increment vblank count and
6382 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6383 * to account for this. We assume this happened if we
6384 * get called over 0.9 frame durations after the last
6385 * timestamped vblank.
6386 *
6387 * This calculation can not be used with vrefresh rates
6388 * below 5Hz (10Hz to be on the safe side) without
6389 * promoting to 64 integers.
0af7e4df 6390 */
49b14a5c
MK		 6391 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6392 9 * crtc->framedur_ns) {
0af7e4df 6393 e->event.sequence++;
49b14a5c
MK		 6394 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6395 crtc->framedur_ns);
0af7e4df
MK		 6396 }
6397
49b14a5c
MK		 6398 e->event.tv_sec = tvbl.tv_sec;
6399 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6400
6b95a207
KH		 6401 list_add_tail(&e->base.link,
6402 &e->base.file_priv->event_list);
6403 wake_up_interruptible(&e->base.file_priv->event_wait);
6404 }
6405
0af7e4df
MK		 6406 drm_vblank_put(dev, intel_crtc->pipe);
6407
6b95a207
KH		 6408 spin_unlock_irqrestore(&dev->event_lock, flags);
6409
05394f39 6410 obj = work->old_fb_obj;
d9e86c0e 6411
e59f2bac 6412 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6413 &obj->pending_flip.counter);
6414 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6415 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6416
6b95a207 6417 schedule_work(&work->work);
e5510fac
JB		 6418
6419 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6420}
6421
1afe3e9d
JB		 6422void intel_finish_page_flip(struct drm_device *dev, int pipe)
6423{
6424 drm_i915_private_t *dev_priv = dev->dev_private;
6425 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6426
49b14a5c 6427 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6428}
6429
6430void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6431{
6432 drm_i915_private_t *dev_priv = dev->dev_private;
6433 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6434
49b14a5c 6435 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6436}
6437
6b95a207
KH		 6438void intel_prepare_page_flip(struct drm_device *dev, int plane)
6439{
6440 drm_i915_private_t *dev_priv = dev->dev_private;
6441 struct intel_crtc *intel_crtc =
6442 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6443 unsigned long flags;
6444
6445 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6446 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6447 if ((++intel_crtc->unpin_work->pending) > 1)
6448 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6449 } else {
6450 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6451 }
6b95a207
KH		 6452 spin_unlock_irqrestore(&dev->event_lock, flags);
6453}
6454
8c9f3aaf
JB		 6455static int intel_gen2_queue_flip(struct drm_device *dev,
6456 struct drm_crtc *crtc,
6457 struct drm_framebuffer *fb,
6458 struct drm_i915_gem_object *obj)
6459{
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6462 unsigned long offset;
6463 u32 flip_mask;
6464 int ret;
6465
6466 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6467 if (ret)
6468 goto out;
6469
6470 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6471 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6472
6473 ret = BEGIN_LP_RING(6);
6474 if (ret)
6475 goto out;
6476
6477 /* Can't queue multiple flips, so wait for the previous
6478 * one to finish before executing the next.
6479 */
6480 if (intel_crtc->plane)
6481 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6482 else
6483 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6484 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6485 OUT_RING(MI_NOOP);
6486 OUT_RING(MI_DISPLAY_FLIP |
6487 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6488 OUT_RING(fb->pitch);
6489 OUT_RING(obj->gtt_offset + offset);
6490 OUT_RING(MI_NOOP);
6491 ADVANCE_LP_RING();
6492out:
6493 return ret;
6494}
6495
6496static int intel_gen3_queue_flip(struct drm_device *dev,
6497 struct drm_crtc *crtc,
6498 struct drm_framebuffer *fb,
6499 struct drm_i915_gem_object *obj)
6500{
6501 struct drm_i915_private *dev_priv = dev->dev_private;
6502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6503 unsigned long offset;
6504 u32 flip_mask;
6505 int ret;
6506
6507 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6508 if (ret)
6509 goto out;
6510
6511 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6512 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6513
6514 ret = BEGIN_LP_RING(6);
6515 if (ret)
6516 goto out;
6517
6518 if (intel_crtc->plane)
6519 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6520 else
6521 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6522 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6523 OUT_RING(MI_NOOP);
6524 OUT_RING(MI_DISPLAY_FLIP_I915 |
6525 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6526 OUT_RING(fb->pitch);
6527 OUT_RING(obj->gtt_offset + offset);
6528 OUT_RING(MI_NOOP);
6529
6530 ADVANCE_LP_RING();
6531out:
6532 return ret;
6533}
6534
6535static int intel_gen4_queue_flip(struct drm_device *dev,
6536 struct drm_crtc *crtc,
6537 struct drm_framebuffer *fb,
6538 struct drm_i915_gem_object *obj)
6539{
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6542 uint32_t pf, pipesrc;
6543 int ret;
6544
6545 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6546 if (ret)
6547 goto out;
6548
6549 ret = BEGIN_LP_RING(4);
6550 if (ret)
6551 goto out;
6552
6553 /* i965+ uses the linear or tiled offsets from the
6554 * Display Registers (which do not change across a page-flip)
6555 * so we need only reprogram the base address.
6556 */
6557 OUT_RING(MI_DISPLAY_FLIP |
6558 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6559 OUT_RING(fb->pitch);
6560 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6561
6562 /* XXX Enabling the panel-fitter across page-flip is so far
6563 * untested on non-native modes, so ignore it for now.
6564 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6565 */
6566 pf = 0;
6567 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6568 OUT_RING(pf | pipesrc);
6569 ADVANCE_LP_RING();
6570out:
6571 return ret;
6572}
6573
6574static int intel_gen6_queue_flip(struct drm_device *dev,
6575 struct drm_crtc *crtc,
6576 struct drm_framebuffer *fb,
6577 struct drm_i915_gem_object *obj)
6578{
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6581 uint32_t pf, pipesrc;
6582 int ret;
6583
6584 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6585 if (ret)
6586 goto out;
6587
6588 ret = BEGIN_LP_RING(4);
6589 if (ret)
6590 goto out;
6591
6592 OUT_RING(MI_DISPLAY_FLIP |
6593 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6594 OUT_RING(fb->pitch | obj->tiling_mode);
6595 OUT_RING(obj->gtt_offset);
6596
6597 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6598 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6599 OUT_RING(pf | pipesrc);
6600 ADVANCE_LP_RING();
6601out:
6602 return ret;
6603}
6604
7c9017e5
JB		 6605/*
6606 * On gen7 we currently use the blit ring because (in early silicon at least)
6607 * the render ring doesn't give us interrpts for page flip completion, which
6608 * means clients will hang after the first flip is queued. Fortunately the
6609 * blit ring generates interrupts properly, so use it instead.
6610 */
6611static int intel_gen7_queue_flip(struct drm_device *dev,
6612 struct drm_crtc *crtc,
6613 struct drm_framebuffer *fb,
6614 struct drm_i915_gem_object *obj)
6615{
6616 struct drm_i915_private *dev_priv = dev->dev_private;
6617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6618 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6619 int ret;
6620
6621 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6622 if (ret)
6623 goto out;
6624
6625 ret = intel_ring_begin(ring, 4);
6626 if (ret)
6627 goto out;
6628
6629 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6630 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6631 intel_ring_emit(ring, (obj->gtt_offset));
6632 intel_ring_emit(ring, (MI_NOOP));
6633 intel_ring_advance(ring);
6634out:
6635 return ret;
6636}
6637
8c9f3aaf
JB		 6638static int intel_default_queue_flip(struct drm_device *dev,
6639 struct drm_crtc *crtc,
6640 struct drm_framebuffer *fb,
6641 struct drm_i915_gem_object *obj)
6642{
6643 return -ENODEV;
6644}
6645
6b95a207
KH		 6646static int intel_crtc_page_flip(struct drm_crtc *crtc,
6647 struct drm_framebuffer *fb,
6648 struct drm_pending_vblank_event *event)
6649{
6650 struct drm_device *dev = crtc->dev;
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6652 struct intel_framebuffer *intel_fb;
05394f39 6653 struct drm_i915_gem_object *obj;
6b95a207
KH		 6654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655 struct intel_unpin_work *work;
8c9f3aaf 6656 unsigned long flags;
52e68630 6657 int ret;
6b95a207
KH		 6658
6659 work = kzalloc(sizeof *work, GFP_KERNEL);
6660 if (work == NULL)
6661 return -ENOMEM;
6662
6b95a207
KH		 6663 work->event = event;
6664 work->dev = crtc->dev;
6665 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6666 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6667 INIT_WORK(&work->work, intel_unpin_work_fn);
6668
6669 /* We borrow the event spin lock for protecting unpin_work */
6670 spin_lock_irqsave(&dev->event_lock, flags);
6671 if (intel_crtc->unpin_work) {
6672 spin_unlock_irqrestore(&dev->event_lock, flags);
6673 kfree(work);
468f0b44
CW		 6674
6675 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6676 return -EBUSY;
6677 }
6678 intel_crtc->unpin_work = work;
6679 spin_unlock_irqrestore(&dev->event_lock, flags);
6680
6681 intel_fb = to_intel_framebuffer(fb);
6682 obj = intel_fb->obj;
6683
468f0b44 6684 mutex_lock(&dev->struct_mutex);
6b95a207 6685
75dfca80 6686 /* Reference the objects for the scheduled work. */
05394f39
CW		 6687 drm_gem_object_reference(&work->old_fb_obj->base);
6688 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6689
6690 crtc->fb = fb;
96b099fd
CW		 6691
6692 ret = drm_vblank_get(dev, intel_crtc->pipe);
6693 if (ret)
6694 goto cleanup_objs;
6695
e1f99ce6 6696 work->pending_flip_obj = obj;
e1f99ce6 6697
4e5359cd
SF		 6698 work->enable_stall_check = true;
6699
e1f99ce6
CW		 6700 /* Block clients from rendering to the new back buffer until
6701 * the flip occurs and the object is no longer visible.
6702 */
05394f39 6703 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6704
8c9f3aaf
JB		 6705 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6706 if (ret)
6707 goto cleanup_pending;
6b95a207
KH		 6708
6709 mutex_unlock(&dev->struct_mutex);
6710
e5510fac
JB		 6711 trace_i915_flip_request(intel_crtc->plane, obj);
6712
6b95a207 6713 return 0;
96b099fd 6714
8c9f3aaf
JB		 6715cleanup_pending:
6716 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6717cleanup_objs:
05394f39
CW		 6718 drm_gem_object_unreference(&work->old_fb_obj->base);
6719 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6720 mutex_unlock(&dev->struct_mutex);
6721
6722 spin_lock_irqsave(&dev->event_lock, flags);
6723 intel_crtc->unpin_work = NULL;
6724 spin_unlock_irqrestore(&dev->event_lock, flags);
6725
6726 kfree(work);
6727
6728 return ret;
6b95a207
KH		 6729}
6730
47f1c6c9
CW		 6731static void intel_sanitize_modesetting(struct drm_device *dev,
6732 int pipe, int plane)
6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 u32 reg, val;
6736
6737 if (HAS_PCH_SPLIT(dev))
6738 return;
6739
6740 /* Who knows what state these registers were left in by the BIOS or
6741 * grub?
6742 *
6743 * If we leave the registers in a conflicting state (e.g. with the
6744 * display plane reading from the other pipe than the one we intend
6745 * to use) then when we attempt to teardown the active mode, we will
6746 * not disable the pipes and planes in the correct order -- leaving
6747 * a plane reading from a disabled pipe and possibly leading to
6748 * undefined behaviour.
6749 */
6750
6751 reg = DSPCNTR(plane);
6752 val = I915_READ(reg);
6753
6754 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6755 return;
6756 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6757 return;
6758
6759 /* This display plane is active and attached to the other CPU pipe. */
6760 pipe = !pipe;
6761
6762 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6763 intel_disable_plane(dev_priv, plane, pipe);
6764 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6765}
79e53945 6766
f6e5b160
CW		 6767static void intel_crtc_reset(struct drm_crtc *crtc)
6768{
6769 struct drm_device *dev = crtc->dev;
6770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6771
6772 /* Reset flags back to the 'unknown' status so that they
6773 * will be correctly set on the initial modeset.
6774 */
6775 intel_crtc->dpms_mode = -1;
6776
6777 /* We need to fix up any BIOS configuration that conflicts with
6778 * our expectations.
6779 */
6780 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6781}
6782
6783static struct drm_crtc_helper_funcs intel_helper_funcs = {
6784 .dpms = intel_crtc_dpms,
6785 .mode_fixup = intel_crtc_mode_fixup,
6786 .mode_set = intel_crtc_mode_set,
6787 .mode_set_base = intel_pipe_set_base,
6788 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6789 .load_lut = intel_crtc_load_lut,
6790 .disable = intel_crtc_disable,
6791};
6792
6793static const struct drm_crtc_funcs intel_crtc_funcs = {
6794 .reset = intel_crtc_reset,
6795 .cursor_set = intel_crtc_cursor_set,
6796 .cursor_move = intel_crtc_cursor_move,
6797 .gamma_set = intel_crtc_gamma_set,
6798 .set_config = drm_crtc_helper_set_config,
6799 .destroy = intel_crtc_destroy,
6800 .page_flip = intel_crtc_page_flip,
6801};
6802
b358d0a6 6803static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6804{
22fd0fab 6805 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6806 struct intel_crtc *intel_crtc;
6807 int i;
6808
6809 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6810 if (intel_crtc == NULL)
6811 return;
6812
6813 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6814
6815 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6816 for (i = 0; i < 256; i++) {
6817 intel_crtc->lut_r[i] = i;
6818 intel_crtc->lut_g[i] = i;
6819 intel_crtc->lut_b[i] = i;
6820 }
6821
80824003
JB		 6822 /* Swap pipes & planes for FBC on pre-965 */
6823 intel_crtc->pipe = pipe;
6824 intel_crtc->plane = pipe;
e2e767ab 6825 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6826 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6827 intel_crtc->plane = !pipe;
80824003
JB		 6828 }
6829
22fd0fab
JB		 6830 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6831 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6832 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6833 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6834
5d1d0cc8 6835 intel_crtc_reset(&intel_crtc->base);
04dbff52 6836 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6837 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6838
6839 if (HAS_PCH_SPLIT(dev)) {
6840 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6841 intel_helper_funcs.commit = ironlake_crtc_commit;
6842 } else {
6843 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6844 intel_helper_funcs.commit = i9xx_crtc_commit;
6845 }
6846
79e53945
JB		 6847 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6848
652c393a
JB		 6849 intel_crtc->busy = false;
6850
6851 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6852 (unsigned long)intel_crtc);
79e53945
JB		 6853}
6854
08d7b3d1 6855int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6856 struct drm_file *file)
08d7b3d1
CW		 6857{
6858 drm_i915_private_t *dev_priv = dev->dev_private;
6859 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6860 struct drm_mode_object *drmmode_obj;
6861 struct intel_crtc *crtc;
08d7b3d1
CW		 6862
6863 if (!dev_priv) {
6864 DRM_ERROR("called with no initialization\n");
6865 return -EINVAL;
6866 }
6867
c05422d5
DV		 6868 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6869 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6870
c05422d5 6871 if (!drmmode_obj) {
08d7b3d1
CW		 6872 DRM_ERROR("no such CRTC id\n");
6873 return -EINVAL;
6874 }
6875
c05422d5
DV		 6876 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6877 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6878
c05422d5 6879 return 0;
08d7b3d1
CW		 6880}
6881
c5e4df33 6882static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6883{
4ef69c7a 6884 struct intel_encoder *encoder;
79e53945 6885 int index_mask = 0;
79e53945
JB		 6886 int entry = 0;
6887
4ef69c7a
CW		 6888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6889 if (type_mask & encoder->clone_mask)
79e53945
JB		 6890 index_mask |= (1 << entry);
6891 entry++;
6892 }
4ef69c7a 6893
79e53945
JB		 6894 return index_mask;
6895}
6896
4d302442
CW		 6897static bool has_edp_a(struct drm_device *dev)
6898{
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900
6901 if (!IS_MOBILE(dev))
6902 return false;
6903
6904 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6905 return false;
6906
6907 if (IS_GEN5(dev) &&
6908 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6909 return false;
6910
6911 return true;
6912}
6913
79e53945
JB		 6914static void intel_setup_outputs(struct drm_device *dev)
6915{
725e30ad 6916 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6917 struct intel_encoder *encoder;
cb0953d7 6918 bool dpd_is_edp = false;
c5d1b51d 6919 bool has_lvds = false;
79e53945 6920
541998a1 6921 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6922 has_lvds = intel_lvds_init(dev);
6923 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6924 /* disable the panel fitter on everything but LVDS */
6925 I915_WRITE(PFIT_CONTROL, 0);
6926 }
79e53945 6927
bad720ff 6928 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6929 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6930
4d302442 6931 if (has_edp_a(dev))
32f9d658
ZW		 6932 intel_dp_init(dev, DP_A);
6933
cb0953d7
AJ		 6934 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6935 intel_dp_init(dev, PCH_DP_D);
6936 }
6937
6938 intel_crt_init(dev);
6939
6940 if (HAS_PCH_SPLIT(dev)) {
6941 int found;
6942
30ad48b7 6943 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6944 /* PCH SDVOB multiplex with HDMIB */
6945 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6946 if (!found)
6947 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6948 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6949 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6950 }
6951
6952 if (I915_READ(HDMIC) & PORT_DETECTED)
6953 intel_hdmi_init(dev, HDMIC);
6954
6955 if (I915_READ(HDMID) & PORT_DETECTED)
6956 intel_hdmi_init(dev, HDMID);
6957
5eb08b69
ZW		 6958 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6959 intel_dp_init(dev, PCH_DP_C);
6960
cb0953d7 6961 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6962 intel_dp_init(dev, PCH_DP_D);
6963
103a196f 6964 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6965 bool found = false;
7d57382e 6966
725e30ad 6967 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6968 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6969 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6970 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6971 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6972 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6973 }
27185ae1 6974
b01f2c3a
JB		 6975 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6976 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6977 intel_dp_init(dev, DP_B);
b01f2c3a 6978 }
725e30ad 6979 }
13520b05
KH		 6980
6981 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6982
b01f2c3a
JB		 6983 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6984 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6985 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6986 }
27185ae1
ML		 6987
6988 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6989
b01f2c3a
JB		 6990 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6991 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6992 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6993 }
6994 if (SUPPORTS_INTEGRATED_DP(dev)) {
6995 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6996 intel_dp_init(dev, DP_C);
b01f2c3a 6997 }
725e30ad 6998 }
27185ae1 6999
b01f2c3a
JB		 7000 if (SUPPORTS_INTEGRATED_DP(dev) &&
7001 (I915_READ(DP_D) & DP_DETECTED)) {
7002 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7003 intel_dp_init(dev, DP_D);
b01f2c3a 7004 }
bad720ff 7005 } else if (IS_GEN2(dev))
79e53945
JB		 7006 intel_dvo_init(dev);
7007
103a196f 7008 if (SUPPORTS_TV(dev))
79e53945
JB		 7009 intel_tv_init(dev);
7010
4ef69c7a
CW		 7011 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7012 encoder->base.possible_crtcs = encoder->crtc_mask;
7013 encoder->base.possible_clones =
7014 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7015 }
47356eb6
CW		 7016
7017 intel_panel_setup_backlight(dev);
2c7111db
CW		 7018
7019 /* disable all the possible outputs/crtcs before entering KMS mode */
7020 drm_helper_disable_unused_functions(dev);
79e53945
JB		 7021}
7022
7023static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7024{
7025 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7026
7027 drm_framebuffer_cleanup(fb);
05394f39 7028 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7029
7030 kfree(intel_fb);
7031}
7032
7033static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7034 struct drm_file *file,
79e53945
JB		 7035 unsigned int *handle)
7036{
7037 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7038 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7039
05394f39 7040 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7041}
7042
7043static const struct drm_framebuffer_funcs intel_fb_funcs = {
7044 .destroy = intel_user_framebuffer_destroy,
7045 .create_handle = intel_user_framebuffer_create_handle,
7046};
7047
38651674
DA		 7048int intel_framebuffer_init(struct drm_device *dev,
7049 struct intel_framebuffer *intel_fb,
7050 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7051 struct drm_i915_gem_object *obj)
79e53945 7052{
79e53945
JB		 7053 int ret;
7054
05394f39 7055 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7056 return -EINVAL;
7057
7058 if (mode_cmd->pitch & 63)
7059 return -EINVAL;
7060
7061 switch (mode_cmd->bpp) {
7062 case 8:
7063 case 16:
7064 case 24:
7065 case 32:
7066 break;
7067 default:
7068 return -EINVAL;
7069 }
7070
79e53945
JB		 7071 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7072 if (ret) {
7073 DRM_ERROR("framebuffer init failed %d\n", ret);
7074 return ret;
7075 }
7076
7077 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7078 intel_fb->obj = obj;
79e53945
JB		 7079 return 0;
7080}
7081
79e53945
JB		 7082static struct drm_framebuffer *
7083intel_user_framebuffer_create(struct drm_device *dev,
7084 struct drm_file *filp,
7085 struct drm_mode_fb_cmd *mode_cmd)
7086{
05394f39 7087 struct drm_i915_gem_object *obj;
79e53945 7088
05394f39 7089 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7090 if (&obj->base == NULL)
cce13ff7 7091 return ERR_PTR(-ENOENT);
79e53945 7092
d2dff872 7093 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7094}
7095
79e53945 7096static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7097 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7098 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7099};
7100
05394f39 7101static struct drm_i915_gem_object *
aa40d6bb 7102intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7103{
05394f39 7104 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7105 int ret;
7106
2c34b850
BW		 7107 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7108
aa40d6bb
ZN		 7109 ctx = i915_gem_alloc_object(dev, 4096);
7110 if (!ctx) {
9ea8d059
CW		 7111 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7112 return NULL;
7113 }
7114
75e9e915 7115 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7116 if (ret) {
7117 DRM_ERROR("failed to pin power context: %d\n", ret);
7118 goto err_unref;
7119 }
7120
aa40d6bb 7121 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7122 if (ret) {
7123 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7124 goto err_unpin;
7125 }
9ea8d059 7126
aa40d6bb 7127 return ctx;
9ea8d059
CW		 7128
7129err_unpin:
aa40d6bb 7130 i915_gem_object_unpin(ctx);
9ea8d059 7131err_unref:
05394f39 7132 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7133 mutex_unlock(&dev->struct_mutex);
7134 return NULL;
7135}
7136
7648fa99
JB		 7137bool ironlake_set_drps(struct drm_device *dev, u8 val)
7138{
7139 struct drm_i915_private *dev_priv = dev->dev_private;
7140 u16 rgvswctl;
7141
7142 rgvswctl = I915_READ16(MEMSWCTL);
7143 if (rgvswctl & MEMCTL_CMD_STS) {
7144 DRM_DEBUG("gpu busy, RCS change rejected\n");
7145 return false; /* still busy with another command */
7146 }
7147
7148 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7149 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7150 I915_WRITE16(MEMSWCTL, rgvswctl);
7151 POSTING_READ16(MEMSWCTL);
7152
7153 rgvswctl |= MEMCTL_CMD_STS;
7154 I915_WRITE16(MEMSWCTL, rgvswctl);
7155
7156 return true;
7157}
7158
f97108d1
JB		 7159void ironlake_enable_drps(struct drm_device *dev)
7160{
7161 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7162 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7163 u8 fmax, fmin, fstart, vstart;
f97108d1 7164
ea056c14
JB		 7165 /* Enable temp reporting */
7166 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7167 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7168
f97108d1
JB		 7169 /* 100ms RC evaluation intervals */
7170 I915_WRITE(RCUPEI, 100000);
7171 I915_WRITE(RCDNEI, 100000);
7172
7173 /* Set max/min thresholds to 90ms and 80ms respectively */
7174 I915_WRITE(RCBMAXAVG, 90000);
7175 I915_WRITE(RCBMINAVG, 80000);
7176
7177 I915_WRITE(MEMIHYST, 1);
7178
7179 /* Set up min, max, and cur for interrupt handling */
7180 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7181 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7182 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7183 MEMMODE_FSTART_SHIFT;
7648fa99 7184
f97108d1
JB		 7185 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7186 PXVFREQ_PX_SHIFT;
7187
80dbf4b7 7188 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7189 dev_priv->fstart = fstart;
7190
80dbf4b7 7191 dev_priv->max_delay = fstart;
f97108d1
JB		 7192 dev_priv->min_delay = fmin;
7193 dev_priv->cur_delay = fstart;
7194
80dbf4b7
JB		 7195 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7196 fmax, fmin, fstart);
7648fa99 7197
f97108d1
JB		 7198 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7199
7200 /*
7201 * Interrupts will be enabled in ironlake_irq_postinstall
7202 */
7203
7204 I915_WRITE(VIDSTART, vstart);
7205 POSTING_READ(VIDSTART);
7206
7207 rgvmodectl |= MEMMODE_SWMODE_EN;
7208 I915_WRITE(MEMMODECTL, rgvmodectl);
7209
481b6af3 7210 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7211 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7212 msleep(1);
7213
7648fa99 7214 ironlake_set_drps(dev, fstart);
f97108d1 7215
7648fa99
JB		 7216 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7217 I915_READ(0x112e0);
7218 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7219 dev_priv->last_count2 = I915_READ(0x112f4);
7220 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7221}
7222
7223void ironlake_disable_drps(struct drm_device *dev)
7224{
7225 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7226 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7227
7228 /* Ack interrupts, disable EFC interrupt */
7229 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7230 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7231 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7232 I915_WRITE(DEIIR, DE_PCU_EVENT);
7233 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7234
7235 /* Go back to the starting frequency */
7648fa99 7236 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7237 msleep(1);
7238 rgvswctl |= MEMCTL_CMD_STS;
7239 I915_WRITE(MEMSWCTL, rgvswctl);
7240 msleep(1);
7241
7242}
7243
3b8d8d91
JB		 7244void gen6_set_rps(struct drm_device *dev, u8 val)
7245{
7246 struct drm_i915_private *dev_priv = dev->dev_private;
7247 u32 swreq;
7248
7249 swreq = (val & 0x3ff) << 25;
7250 I915_WRITE(GEN6_RPNSWREQ, swreq);
7251}
7252
7253void gen6_disable_rps(struct drm_device *dev)
7254{
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256
7257 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7258 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7259 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7260
7261 spin_lock_irq(&dev_priv->rps_lock);
7262 dev_priv->pm_iir = 0;
7263 spin_unlock_irq(&dev_priv->rps_lock);
7264
3b8d8d91
JB		 7265 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7266}
7267
7648fa99
JB		 7268static unsigned long intel_pxfreq(u32 vidfreq)
7269{
7270 unsigned long freq;
7271 int div = (vidfreq & 0x3f0000) >> 16;
7272 int post = (vidfreq & 0x3000) >> 12;
7273 int pre = (vidfreq & 0x7);
7274
7275 if (!pre)
7276 return 0;
7277
7278 freq = ((div * 133333) / ((1<<post) * pre));
7279
7280 return freq;
7281}
7282
7283void intel_init_emon(struct drm_device *dev)
7284{
7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 u32 lcfuse;
7287 u8 pxw[16];
7288 int i;
7289
7290 /* Disable to program */
7291 I915_WRITE(ECR, 0);
7292 POSTING_READ(ECR);
7293
7294 /* Program energy weights for various events */
7295 I915_WRITE(SDEW, 0x15040d00);
7296 I915_WRITE(CSIEW0, 0x007f0000);
7297 I915_WRITE(CSIEW1, 0x1e220004);
7298 I915_WRITE(CSIEW2, 0x04000004);
7299
7300 for (i = 0; i < 5; i++)
7301 I915_WRITE(PEW + (i * 4), 0);
7302 for (i = 0; i < 3; i++)
7303 I915_WRITE(DEW + (i * 4), 0);
7304
7305 /* Program P-state weights to account for frequency power adjustment */
7306 for (i = 0; i < 16; i++) {
7307 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7308 unsigned long freq = intel_pxfreq(pxvidfreq);
7309 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7310 PXVFREQ_PX_SHIFT;
7311 unsigned long val;
7312
7313 val = vid * vid;
7314 val *= (freq / 1000);
7315 val *= 255;
7316 val /= (127*127*900);
7317 if (val > 0xff)
7318 DRM_ERROR("bad pxval: %ld\n", val);
7319 pxw[i] = val;
7320 }
7321 /* Render standby states get 0 weight */
7322 pxw[14] = 0;
7323 pxw[15] = 0;
7324
7325 for (i = 0; i < 4; i++) {
7326 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7327 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7328 I915_WRITE(PXW + (i * 4), val);
7329 }
7330
7331 /* Adjust magic regs to magic values (more experimental results) */
7332 I915_WRITE(OGW0, 0);
7333 I915_WRITE(OGW1, 0);
7334 I915_WRITE(EG0, 0x00007f00);
7335 I915_WRITE(EG1, 0x0000000e);
7336 I915_WRITE(EG2, 0x000e0000);
7337 I915_WRITE(EG3, 0x68000300);
7338 I915_WRITE(EG4, 0x42000000);
7339 I915_WRITE(EG5, 0x00140031);
7340 I915_WRITE(EG6, 0);
7341 I915_WRITE(EG7, 0);
7342
7343 for (i = 0; i < 8; i++)
7344 I915_WRITE(PXWL + (i * 4), 0);
7345
7346 /* Enable PMON + select events */
7347 I915_WRITE(ECR, 0x80000019);
7348
7349 lcfuse = I915_READ(LCFUSE02);
7350
7351 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7352}
7353
3b8d8d91 7354void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7355{
a6044e23
JB		 7356 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7357 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7358 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7359 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7360 int i;
7361
7362 /* Here begins a magic sequence of register writes to enable
7363 * auto-downclocking.
7364 *
7365 * Perhaps there might be some value in exposing these to
7366 * userspace...
7367 */
7368 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7369 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7370 gen6_gt_force_wake_get(dev_priv);
8fd26859 7371
3b8d8d91 7372 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7373 I915_WRITE(GEN6_RC_CONTROL, 0);
7374
7375 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7376 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7377 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7378 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7379 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7380
7381 for (i = 0; i < I915_NUM_RINGS; i++)
7382 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7383
7384 I915_WRITE(GEN6_RC_SLEEP, 0);
7385 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7386 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7387 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7388 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7389
7df8721b
JB		 7390 if (i915_enable_rc6)
7391 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7392 GEN6_RC_CTL_RC6_ENABLE;
7393
8fd26859 7394 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7395 rc6_mask |
9c3d2f7f 7396 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7397 GEN6_RC_CTL_HW_ENABLE);
7398
3b8d8d91 7399 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7400 GEN6_FREQUENCY(10) |
7401 GEN6_OFFSET(0) |
7402 GEN6_AGGRESSIVE_TURBO);
7403 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7404 GEN6_FREQUENCY(12));
7405
7406 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7407 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7408 18 << 24 |
7409 6 << 16);
ccab5c82
JB		 7410 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7411 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7412 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7413 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7414 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7415 I915_WRITE(GEN6_RP_CONTROL,
7416 GEN6_RP_MEDIA_TURBO |
7417 GEN6_RP_USE_NORMAL_FREQ |
7418 GEN6_RP_MEDIA_IS_GFX |
7419 GEN6_RP_ENABLE |
ccab5c82
JB		 7420 GEN6_RP_UP_BUSY_AVG |
7421 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7422
7423 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7424 500))
7425 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7426
7427 I915_WRITE(GEN6_PCODE_DATA, 0);
7428 I915_WRITE(GEN6_PCODE_MAILBOX,
7429 GEN6_PCODE_READY |
7430 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7431 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7432 500))
7433 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7434
a6044e23
JB		 7435 min_freq = (rp_state_cap & 0xff0000) >> 16;
7436 max_freq = rp_state_cap & 0xff;
7437 cur_freq = (gt_perf_status & 0xff00) >> 8;
7438
7439 /* Check for overclock support */
7440 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7441 500))
7442 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7443 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7444 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7445 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7446 500))
7447 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7448 if (pcu_mbox & (1<<31)) { /* OC supported */
7449 max_freq = pcu_mbox & 0xff;
e281fcaa 7450 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7451 }
7452
7453 /* In units of 100MHz */
7454 dev_priv->max_delay = max_freq;
7455 dev_priv->min_delay = min_freq;
7456 dev_priv->cur_delay = cur_freq;
7457
8fd26859
CW		 7458 /* requires MSI enabled */
7459 I915_WRITE(GEN6_PMIER,
7460 GEN6_PM_MBOX_EVENT |
7461 GEN6_PM_THERMAL_EVENT |
7462 GEN6_PM_RP_DOWN_TIMEOUT |
7463 GEN6_PM_RP_UP_THRESHOLD |
7464 GEN6_PM_RP_DOWN_THRESHOLD |
7465 GEN6_PM_RP_UP_EI_EXPIRED |
7466 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7467 spin_lock_irq(&dev_priv->rps_lock);
7468 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7469 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7470 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7471 /* enable all PM interrupts */
7472 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7473
fcca7926 7474 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7475 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7476}
7477
23b2f8bb
JB		 7478void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7479{
7480 int min_freq = 15;
7481 int gpu_freq, ia_freq, max_ia_freq;
7482 int scaling_factor = 180;
7483
7484 max_ia_freq = cpufreq_quick_get_max(0);
7485 /*
7486 * Default to measured freq if none found, PCU will ensure we don't go
7487 * over
7488 */
7489 if (!max_ia_freq)
7490 max_ia_freq = tsc_khz;
7491
7492 /* Convert from kHz to MHz */
7493 max_ia_freq /= 1000;
7494
7495 mutex_lock(&dev_priv->dev->struct_mutex);
7496
7497 /*
7498 * For each potential GPU frequency, load a ring frequency we'd like
7499 * to use for memory access. We do this by specifying the IA frequency
7500 * the PCU should use as a reference to determine the ring frequency.
7501 */
7502 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7503 gpu_freq--) {
7504 int diff = dev_priv->max_delay - gpu_freq;
7505
7506 /*
7507 * For GPU frequencies less than 750MHz, just use the lowest
7508 * ring freq.
7509 */
7510 if (gpu_freq < min_freq)
7511 ia_freq = 800;
7512 else
7513 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7514 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7515
7516 I915_WRITE(GEN6_PCODE_DATA,
7517 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7518 gpu_freq);
7519 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7520 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7521 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7522 GEN6_PCODE_READY) == 0, 10)) {
7523 DRM_ERROR("pcode write of freq table timed out\n");
7524 continue;
7525 }
7526 }
7527
7528 mutex_unlock(&dev_priv->dev->struct_mutex);
7529}
7530
6067aaea
JB		 7531static void ironlake_init_clock_gating(struct drm_device *dev)
7532{
7533 struct drm_i915_private *dev_priv = dev->dev_private;
7534 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7535
7536 /* Required for FBC */
7537 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7538 DPFCRUNIT_CLOCK_GATE_DISABLE |
7539 DPFDUNIT_CLOCK_GATE_DISABLE;
7540 /* Required for CxSR */
7541 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7542
7543 I915_WRITE(PCH_3DCGDIS0,
7544 MARIUNIT_CLOCK_GATE_DISABLE |
7545 SVSMUNIT_CLOCK_GATE_DISABLE);
7546 I915_WRITE(PCH_3DCGDIS1,
7547 VFMUNIT_CLOCK_GATE_DISABLE);
7548
7549 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7550
6067aaea
JB		 7551 /*
7552 * According to the spec the following bits should be set in
7553 * order to enable memory self-refresh
7554 * The bit 22/21 of 0x42004
7555 * The bit 5 of 0x42020
7556 * The bit 15 of 0x45000
7557 */
7558 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7559 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7560 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7561 I915_WRITE(ILK_DSPCLK_GATE,
7562 (I915_READ(ILK_DSPCLK_GATE) |
7563 ILK_DPARB_CLK_GATE));
7564 I915_WRITE(DISP_ARB_CTL,
7565 (I915_READ(DISP_ARB_CTL) |
7566 DISP_FBC_WM_DIS));
7567 I915_WRITE(WM3_LP_ILK, 0);
7568 I915_WRITE(WM2_LP_ILK, 0);
7569 I915_WRITE(WM1_LP_ILK, 0);
7570
7571 /*
7572 * Based on the document from hardware guys the following bits
7573 * should be set unconditionally in order to enable FBC.
7574 * The bit 22 of 0x42000
7575 * The bit 22 of 0x42004
7576 * The bit 7,8,9 of 0x42020.
7577 */
7578 if (IS_IRONLAKE_M(dev)) {
7579 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7580 I915_READ(ILK_DISPLAY_CHICKEN1) |
7581 ILK_FBCQ_DIS);
7582 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7583 I915_READ(ILK_DISPLAY_CHICKEN2) |
7584 ILK_DPARB_GATE);
7585 I915_WRITE(ILK_DSPCLK_GATE,
7586 I915_READ(ILK_DSPCLK_GATE) |
7587 ILK_DPFC_DIS1 |
7588 ILK_DPFC_DIS2 |
7589 ILK_CLK_FBC);
7590 }
7591
7592 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7593 I915_READ(ILK_DISPLAY_CHICKEN2) |
7594 ILK_ELPIN_409_SELECT);
7595 I915_WRITE(_3D_CHICKEN2,
7596 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7597 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7598}
7599
6067aaea 7600static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7601{
7602 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7603 int pipe;
6067aaea
JB		 7604 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7605
7606 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7607
6067aaea
JB		 7608 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7609 I915_READ(ILK_DISPLAY_CHICKEN2) |
7610 ILK_ELPIN_409_SELECT);
8956c8bb 7611
6067aaea
JB		 7612 I915_WRITE(WM3_LP_ILK, 0);
7613 I915_WRITE(WM2_LP_ILK, 0);
7614 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7615
7616 /*
6067aaea
JB		 7617 * According to the spec the following bits should be
7618 * set in order to enable memory self-refresh and fbc:
7619 * The bit21 and bit22 of 0x42000
7620 * The bit21 and bit22 of 0x42004
7621 * The bit5 and bit7 of 0x42020
7622 * The bit14 of 0x70180
7623 * The bit14 of 0x71180
652c393a 7624 */
6067aaea
JB		 7625 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7626 I915_READ(ILK_DISPLAY_CHICKEN1) |
7627 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7628 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7629 I915_READ(ILK_DISPLAY_CHICKEN2) |
7630 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7631 I915_WRITE(ILK_DSPCLK_GATE,
7632 I915_READ(ILK_DSPCLK_GATE) |
7633 ILK_DPARB_CLK_GATE |
7634 ILK_DPFD_CLK_GATE);
8956c8bb 7635
6067aaea
JB		 7636 for_each_pipe(pipe)
7637 I915_WRITE(DSPCNTR(pipe),
7638 I915_READ(DSPCNTR(pipe)) |
7639 DISPPLANE_TRICKLE_FEED_DISABLE);
7640}
8956c8bb 7641
28963a3e
JB		 7642static void ivybridge_init_clock_gating(struct drm_device *dev)
7643{
7644 struct drm_i915_private *dev_priv = dev->dev_private;
7645 int pipe;
7646 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7647
28963a3e 7648 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7649
28963a3e
JB		 7650 I915_WRITE(WM3_LP_ILK, 0);
7651 I915_WRITE(WM2_LP_ILK, 0);
7652 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7653
28963a3e 7654 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7655
28963a3e
JB		 7656 for_each_pipe(pipe)
7657 I915_WRITE(DSPCNTR(pipe),
7658 I915_READ(DSPCNTR(pipe)) |
7659 DISPPLANE_TRICKLE_FEED_DISABLE);
7660}
7661
6067aaea
JB		 7662static void g4x_init_clock_gating(struct drm_device *dev)
7663{
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665 uint32_t dspclk_gate;
8fd26859 7666
6067aaea
JB		 7667 I915_WRITE(RENCLK_GATE_D1, 0);
7668 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7669 GS_UNIT_CLOCK_GATE_DISABLE |
7670 CL_UNIT_CLOCK_GATE_DISABLE);
7671 I915_WRITE(RAMCLK_GATE_D, 0);
7672 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7673 OVRUNIT_CLOCK_GATE_DISABLE |
7674 OVCUNIT_CLOCK_GATE_DISABLE;
7675 if (IS_GM45(dev))
7676 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7677 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7678}
1398261a 7679
6067aaea
JB		 7680static void crestline_init_clock_gating(struct drm_device *dev)
7681{
7682 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7683
6067aaea
JB		 7684 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7685 I915_WRITE(RENCLK_GATE_D2, 0);
7686 I915_WRITE(DSPCLK_GATE_D, 0);
7687 I915_WRITE(RAMCLK_GATE_D, 0);
7688 I915_WRITE16(DEUC, 0);
7689}
652c393a 7690
6067aaea
JB		 7691static void broadwater_init_clock_gating(struct drm_device *dev)
7692{
7693 struct drm_i915_private *dev_priv = dev->dev_private;
7694
7695 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7696 I965_RCC_CLOCK_GATE_DISABLE |
7697 I965_RCPB_CLOCK_GATE_DISABLE |
7698 I965_ISC_CLOCK_GATE_DISABLE |
7699 I965_FBC_CLOCK_GATE_DISABLE);
7700 I915_WRITE(RENCLK_GATE_D2, 0);
7701}
7702
7703static void gen3_init_clock_gating(struct drm_device *dev)
7704{
7705 struct drm_i915_private *dev_priv = dev->dev_private;
7706 u32 dstate = I915_READ(D_STATE);
7707
7708 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7709 DSTATE_DOT_CLOCK_GATING;
7710 I915_WRITE(D_STATE, dstate);
7711}
7712
7713static void i85x_init_clock_gating(struct drm_device *dev)
7714{
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716
7717 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7718}
7719
7720static void i830_init_clock_gating(struct drm_device *dev)
7721{
7722 struct drm_i915_private *dev_priv = dev->dev_private;
7723
7724 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7725}
7726
645c62a5
JB		 7727static void ibx_init_clock_gating(struct drm_device *dev)
7728{
7729 struct drm_i915_private *dev_priv = dev->dev_private;
7730
7731 /*
7732 * On Ibex Peak and Cougar Point, we need to disable clock
7733 * gating for the panel power sequencer or it will fail to
7734 * start up when no ports are active.
7735 */
7736 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7737}
7738
7739static void cpt_init_clock_gating(struct drm_device *dev)
7740{
7741 struct drm_i915_private *dev_priv = dev->dev_private;
7742
7743 /*
7744 * On Ibex Peak and Cougar Point, we need to disable clock
7745 * gating for the panel power sequencer or it will fail to
7746 * start up when no ports are active.
7747 */
7748 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7749 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7750 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7751}
7752
ac668088 7753static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7754{
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756
7757 if (dev_priv->renderctx) {
ac668088
CW		 7758 i915_gem_object_unpin(dev_priv->renderctx);
7759 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7760 dev_priv->renderctx = NULL;
7761 }
7762
7763 if (dev_priv->pwrctx) {
ac668088
CW		 7764 i915_gem_object_unpin(dev_priv->pwrctx);
7765 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7766 dev_priv->pwrctx = NULL;
7767 }
7768}
7769
7770static void ironlake_disable_rc6(struct drm_device *dev)
7771{
7772 struct drm_i915_private *dev_priv = dev->dev_private;
7773
7774 if (I915_READ(PWRCTXA)) {
7775 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7776 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7777 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7778 50);
0cdab21f
CW		 7779
7780 I915_WRITE(PWRCTXA, 0);
7781 POSTING_READ(PWRCTXA);
7782
ac668088
CW		 7783 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7784 POSTING_READ(RSTDBYCTL);
0cdab21f 7785 }
ac668088 7786
99507307 7787 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7788}
7789
ac668088 7790static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7791{
7792 struct drm_i915_private *dev_priv = dev->dev_private;
7793
ac668088
CW		 7794 if (dev_priv->renderctx == NULL)
7795 dev_priv->renderctx = intel_alloc_context_page(dev);
7796 if (!dev_priv->renderctx)
7797 return -ENOMEM;
7798
7799 if (dev_priv->pwrctx == NULL)
7800 dev_priv->pwrctx = intel_alloc_context_page(dev);
7801 if (!dev_priv->pwrctx) {
7802 ironlake_teardown_rc6(dev);
7803 return -ENOMEM;
7804 }
7805
7806 return 0;
d5bb081b
JB		 7807}
7808
7809void ironlake_enable_rc6(struct drm_device *dev)
7810{
7811 struct drm_i915_private *dev_priv = dev->dev_private;
7812 int ret;
7813
ac668088
CW		 7814 /* rc6 disabled by default due to repeated reports of hanging during
7815 * boot and resume.
7816 */
7817 if (!i915_enable_rc6)
7818 return;
7819
2c34b850 7820 mutex_lock(&dev->struct_mutex);
ac668088 7821 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7822 if (ret) {
7823 mutex_unlock(&dev->struct_mutex);
ac668088 7824 return;
2c34b850 7825 }
ac668088 7826
d5bb081b
JB		 7827 /*
7828 * GPU can automatically power down the render unit if given a page
7829 * to save state.
7830 */
7831 ret = BEGIN_LP_RING(6);
7832 if (ret) {
ac668088 7833 ironlake_teardown_rc6(dev);
2c34b850 7834 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7835 return;
7836 }
ac668088 7837
d5bb081b
JB		 7838 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7839 OUT_RING(MI_SET_CONTEXT);
7840 OUT_RING(dev_priv->renderctx->gtt_offset |
7841 MI_MM_SPACE_GTT |
7842 MI_SAVE_EXT_STATE_EN |
7843 MI_RESTORE_EXT_STATE_EN |
7844 MI_RESTORE_INHIBIT);
7845 OUT_RING(MI_SUSPEND_FLUSH);
7846 OUT_RING(MI_NOOP);
7847 OUT_RING(MI_FLUSH);
7848 ADVANCE_LP_RING();
7849
4a246cfc
BW		 7850 /*
7851 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7852 * does an implicit flush, combined with MI_FLUSH above, it should be
7853 * safe to assume that renderctx is valid
7854 */
7855 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7856 if (ret) {
7857 DRM_ERROR("failed to enable ironlake power power savings\n");
7858 ironlake_teardown_rc6(dev);
7859 mutex_unlock(&dev->struct_mutex);
7860 return;
7861 }
7862
d5bb081b
JB		 7863 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7864 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7865 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7866}
7867
645c62a5
JB		 7868void intel_init_clock_gating(struct drm_device *dev)
7869{
7870 struct drm_i915_private *dev_priv = dev->dev_private;
7871
7872 dev_priv->display.init_clock_gating(dev);
7873
7874 if (dev_priv->display.init_pch_clock_gating)
7875 dev_priv->display.init_pch_clock_gating(dev);
7876}
ac668088 7877
e70236a8
JB		 7878/* Set up chip specific display functions */
7879static void intel_init_display(struct drm_device *dev)
7880{
7881 struct drm_i915_private *dev_priv = dev->dev_private;
7882
7883 /* We always want a DPMS function */
f564048e 7884 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7885 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 7886 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 7887 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7888 } else {
e70236a8 7889 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 7890 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 7891 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7892 }
e70236a8 7893
ee5382ae 7894 if (I915_HAS_FBC(dev)) {
9c04f015 7895 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7896 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7897 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7898 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7899 } else if (IS_GM45(dev)) {
74dff282
JB		 7900 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7901 dev_priv->display.enable_fbc = g4x_enable_fbc;
7902 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7903 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7904 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7905 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7906 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7907 }
74dff282 7908 /* 855GM needs testing */
e70236a8
JB		 7909 }
7910
7911 /* Returns the core display clock speed */
f2b115e6 7912 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7913 dev_priv->display.get_display_clock_speed =
7914 i945_get_display_clock_speed;
7915 else if (IS_I915G(dev))
7916 dev_priv->display.get_display_clock_speed =
7917 i915_get_display_clock_speed;
f2b115e6 7918 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7919 dev_priv->display.get_display_clock_speed =
7920 i9xx_misc_get_display_clock_speed;
7921 else if (IS_I915GM(dev))
7922 dev_priv->display.get_display_clock_speed =
7923 i915gm_get_display_clock_speed;
7924 else if (IS_I865G(dev))
7925 dev_priv->display.get_display_clock_speed =
7926 i865_get_display_clock_speed;
f0f8a9ce 7927 else if (IS_I85X(dev))
e70236a8
JB		 7928 dev_priv->display.get_display_clock_speed =
7929 i855_get_display_clock_speed;
7930 else /* 852, 830 */
7931 dev_priv->display.get_display_clock_speed =
7932 i830_get_display_clock_speed;
7933
7934 /* For FIFO watermark updates */
7f8a8569 7935 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7936 if (HAS_PCH_IBX(dev))
7937 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7938 else if (HAS_PCH_CPT(dev))
7939 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7940
f00a3ddf 7941 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7942 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7943 dev_priv->display.update_wm = ironlake_update_wm;
7944 else {
7945 DRM_DEBUG_KMS("Failed to get proper latency. "
7946 "Disable CxSR\n");
7947 dev_priv->display.update_wm = NULL;
1398261a 7948 }
674cf967 7949 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7950 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7951 } else if (IS_GEN6(dev)) {
7952 if (SNB_READ_WM0_LATENCY()) {
7953 dev_priv->display.update_wm = sandybridge_update_wm;
7954 } else {
7955 DRM_DEBUG_KMS("Failed to read display plane latency. "
7956 "Disable CxSR\n");
7957 dev_priv->display.update_wm = NULL;
7f8a8569 7958 }
674cf967 7959 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7960 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7961 } else if (IS_IVYBRIDGE(dev)) {
7962 /* FIXME: detect B0+ stepping and use auto training */
7963 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7964 if (SNB_READ_WM0_LATENCY()) {
7965 dev_priv->display.update_wm = sandybridge_update_wm;
7966 } else {
7967 DRM_DEBUG_KMS("Failed to read display plane latency. "
7968 "Disable CxSR\n");
7969 dev_priv->display.update_wm = NULL;
7970 }
28963a3e 7971 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7972
7f8a8569
ZW		 7973 } else
7974 dev_priv->display.update_wm = NULL;
7975 } else if (IS_PINEVIEW(dev)) {
d4294342 7976 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7977 dev_priv->is_ddr3,
d4294342
ZY		 7978 dev_priv->fsb_freq,
7979 dev_priv->mem_freq)) {
7980 DRM_INFO("failed to find known CxSR latency "
95534263 7981 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7982 "disabling CxSR\n",
95534263 7983 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7984 dev_priv->fsb_freq, dev_priv->mem_freq);
7985 /* Disable CxSR and never update its watermark again */
7986 pineview_disable_cxsr(dev);
7987 dev_priv->display.update_wm = NULL;
7988 } else
7989 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7990 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7991 } else if (IS_G4X(dev)) {
e70236a8 7992 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7993 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7994 } else if (IS_GEN4(dev)) {
e70236a8 7995 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7996 if (IS_CRESTLINE(dev))
7997 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7998 else if (IS_BROADWATER(dev))
7999 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8000 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8001 dev_priv->display.update_wm = i9xx_update_wm;
8002 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8003 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8004 } else if (IS_I865G(dev)) {
8005 dev_priv->display.update_wm = i830_update_wm;
8006 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8007 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8008 } else if (IS_I85X(dev)) {
8009 dev_priv->display.update_wm = i9xx_update_wm;
8010 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8011 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8012 } else {
8f4695ed 8013 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8014 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8015 if (IS_845G(dev))
e70236a8
JB		 8016 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8017 else
8018 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8019 }
8c9f3aaf
JB		 8020
8021 /* Default just returns -ENODEV to indicate unsupported */
8022 dev_priv->display.queue_flip = intel_default_queue_flip;
8023
8024 switch (INTEL_INFO(dev)->gen) {
8025 case 2:
8026 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8027 break;
8028
8029 case 3:
8030 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8031 break;
8032
8033 case 4:
8034 case 5:
8035 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8036 break;
8037
8038 case 6:
8039 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8040 break;
7c9017e5
JB		 8041 case 7:
8042 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8043 break;
8c9f3aaf 8044 }
e70236a8
JB		 8045}
8046
b690e96c
JB		 8047/*
8048 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8049 * resume, or other times. This quirk makes sure that's the case for
8050 * affected systems.
8051 */
8052static void quirk_pipea_force (struct drm_device *dev)
8053{
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055
8056 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8057 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8058}
8059
8060struct intel_quirk {
8061 int device;
8062 int subsystem_vendor;
8063 int subsystem_device;
8064 void (*hook)(struct drm_device *dev);
8065};
8066
8067struct intel_quirk intel_quirks[] = {
8068 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8069 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8070 /* HP Mini needs pipe A force quirk (LP: #322104) */
8071 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8072
8073 /* Thinkpad R31 needs pipe A force quirk */
8074 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8075 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8076 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8077
8078 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8079 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8080 /* ThinkPad X40 needs pipe A force quirk */
8081
8082 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8083 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8084
8085 /* 855 & before need to leave pipe A & dpll A up */
8086 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8087 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8088};
8089
8090static void intel_init_quirks(struct drm_device *dev)
8091{
8092 struct pci_dev *d = dev->pdev;
8093 int i;
8094
8095 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8096 struct intel_quirk *q = &intel_quirks[i];
8097
8098 if (d->device == q->device &&
8099 (d->subsystem_vendor == q->subsystem_vendor ||
8100 q->subsystem_vendor == PCI_ANY_ID) &&
8101 (d->subsystem_device == q->subsystem_device ||
8102 q->subsystem_device == PCI_ANY_ID))
8103 q->hook(dev);
8104 }
8105}
8106
9cce37f4
JB		 8107/* Disable the VGA plane that we never use */
8108static void i915_disable_vga(struct drm_device *dev)
8109{
8110 struct drm_i915_private *dev_priv = dev->dev_private;
8111 u8 sr1;
8112 u32 vga_reg;
8113
8114 if (HAS_PCH_SPLIT(dev))
8115 vga_reg = CPU_VGACNTRL;
8116 else
8117 vga_reg = VGACNTRL;
8118
8119 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8120 outb(1, VGA_SR_INDEX);
8121 sr1 = inb(VGA_SR_DATA);
8122 outb(sr1 | 1<<5, VGA_SR_DATA);
8123 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8124 udelay(300);
8125
8126 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8127 POSTING_READ(vga_reg);
8128}
8129
79e53945
JB		 8130void intel_modeset_init(struct drm_device *dev)
8131{
652c393a 8132 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8133 int i;
8134
8135 drm_mode_config_init(dev);
8136
8137 dev->mode_config.min_width = 0;
8138 dev->mode_config.min_height = 0;
8139
8140 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8141
b690e96c
JB		 8142 intel_init_quirks(dev);
8143
e70236a8
JB		 8144 intel_init_display(dev);
8145
a6c45cf0
CW		 8146 if (IS_GEN2(dev)) {
8147 dev->mode_config.max_width = 2048;
8148 dev->mode_config.max_height = 2048;
8149 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8150 dev->mode_config.max_width = 4096;
8151 dev->mode_config.max_height = 4096;
79e53945 8152 } else {
a6c45cf0
CW		 8153 dev->mode_config.max_width = 8192;
8154 dev->mode_config.max_height = 8192;
79e53945 8155 }
35c3047a 8156 dev->mode_config.fb_base = dev->agp->base;
79e53945 8157
28c97730 8158 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8159 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8160
a3524f1b 8161 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8162 intel_crtc_init(dev, i);
8163 }
8164
9cce37f4
JB		 8165 /* Just disable it once at startup */
8166 i915_disable_vga(dev);
79e53945 8167 intel_setup_outputs(dev);
652c393a 8168
645c62a5 8169 intel_init_clock_gating(dev);
9cce37f4 8170
7648fa99 8171 if (IS_IRONLAKE_M(dev)) {
f97108d1 8172 ironlake_enable_drps(dev);
7648fa99
JB		 8173 intel_init_emon(dev);
8174 }
f97108d1 8175
1c70c0ce 8176 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8177 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8178 gen6_update_ring_freq(dev_priv);
8179 }
3b8d8d91 8180
652c393a
JB		 8181 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8182 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8183 (unsigned long)dev);
2c7111db
CW		 8184}
8185
8186void intel_modeset_gem_init(struct drm_device *dev)
8187{
8188 if (IS_IRONLAKE_M(dev))
8189 ironlake_enable_rc6(dev);
02e792fb
DV		 8190
8191 intel_setup_overlay(dev);
79e53945
JB		 8192}
8193
8194void intel_modeset_cleanup(struct drm_device *dev)
8195{
652c393a
JB		 8196 struct drm_i915_private *dev_priv = dev->dev_private;
8197 struct drm_crtc *crtc;
8198 struct intel_crtc *intel_crtc;
8199
f87ea761 8200 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8201 mutex_lock(&dev->struct_mutex);
8202
723bfd70
JB		 8203 intel_unregister_dsm_handler();
8204
8205
652c393a
JB		 8206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8207 /* Skip inactive CRTCs */
8208 if (!crtc->fb)
8209 continue;
8210
8211 intel_crtc = to_intel_crtc(crtc);
3dec0095 8212 intel_increase_pllclock(crtc);
652c393a
JB		 8213 }
8214
e70236a8
JB		 8215 if (dev_priv->display.disable_fbc)
8216 dev_priv->display.disable_fbc(dev);
8217
f97108d1
JB		 8218 if (IS_IRONLAKE_M(dev))
8219 ironlake_disable_drps(dev);
1c70c0ce 8220 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8221 gen6_disable_rps(dev);
f97108d1 8222
d5bb081b
JB		 8223 if (IS_IRONLAKE_M(dev))
8224 ironlake_disable_rc6(dev);
0cdab21f 8225
69341a5e
KH		 8226 mutex_unlock(&dev->struct_mutex);
8227
6c0d9350
DV		 8228 /* Disable the irq before mode object teardown, for the irq might
8229 * enqueue unpin/hotplug work. */
8230 drm_irq_uninstall(dev);
8231 cancel_work_sync(&dev_priv->hotplug_work);
8232
3dec0095
DV		 8233 /* Shut off idle work before the crtcs get freed. */
8234 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8235 intel_crtc = to_intel_crtc(crtc);
8236 del_timer_sync(&intel_crtc->idle_timer);
8237 }
8238 del_timer_sync(&dev_priv->idle_timer);
8239 cancel_work_sync(&dev_priv->idle_work);
8240
79e53945
JB		 8241 drm_mode_config_cleanup(dev);
8242}
8243
f1c79df3
ZW		 8244/*
8245 * Return which encoder is currently attached for connector.
8246 */
df0e9248 8247struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8248{
df0e9248
CW		 8249 return &intel_attached_encoder(connector)->base;
8250}
f1c79df3 8251
df0e9248
CW		 8252void intel_connector_attach_encoder(struct intel_connector *connector,
8253 struct intel_encoder *encoder)
8254{
8255 connector->encoder = encoder;
8256 drm_mode_connector_attach_encoder(&connector->base,
8257 &encoder->base);
79e53945 8258}
28d52043
DA		 8259
8260/*
8261 * set vga decode state - true == enable VGA decode
8262 */
8263int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8264{
8265 struct drm_i915_private *dev_priv = dev->dev_private;
8266 u16 gmch_ctrl;
8267
8268 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8269 if (state)
8270 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8271 else
8272 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8273 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8274 return 0;
8275}
c4a1d9e4
CW		 8276
8277#ifdef CONFIG_DEBUG_FS
8278#include <linux/seq_file.h>
8279
8280struct intel_display_error_state {
8281 struct intel_cursor_error_state {
8282 u32 control;
8283 u32 position;
8284 u32 base;
8285 u32 size;
8286 } cursor[2];
8287
8288 struct intel_pipe_error_state {
8289 u32 conf;
8290 u32 source;
8291
8292 u32 htotal;
8293 u32 hblank;
8294 u32 hsync;
8295 u32 vtotal;
8296 u32 vblank;
8297 u32 vsync;
8298 } pipe[2];
8299
8300 struct intel_plane_error_state {
8301 u32 control;
8302 u32 stride;
8303 u32 size;
8304 u32 pos;
8305 u32 addr;
8306 u32 surface;
8307 u32 tile_offset;
8308 } plane[2];
8309};
8310
8311struct intel_display_error_state *
8312intel_display_capture_error_state(struct drm_device *dev)
8313{
8314 drm_i915_private_t *dev_priv = dev->dev_private;
8315 struct intel_display_error_state *error;
8316 int i;
8317
8318 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8319 if (error == NULL)
8320 return NULL;
8321
8322 for (i = 0; i < 2; i++) {
8323 error->cursor[i].control = I915_READ(CURCNTR(i));
8324 error->cursor[i].position = I915_READ(CURPOS(i));
8325 error->cursor[i].base = I915_READ(CURBASE(i));
8326
8327 error->plane[i].control = I915_READ(DSPCNTR(i));
8328 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8329 error->plane[i].size = I915_READ(DSPSIZE(i));
8330 error->plane[i].pos= I915_READ(DSPPOS(i));
8331 error->plane[i].addr = I915_READ(DSPADDR(i));
8332 if (INTEL_INFO(dev)->gen >= 4) {
8333 error->plane[i].surface = I915_READ(DSPSURF(i));
8334 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8335 }
8336
8337 error->pipe[i].conf = I915_READ(PIPECONF(i));
8338 error->pipe[i].source = I915_READ(PIPESRC(i));
8339 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8340 error->pipe[i].hblank = I915_READ(HBLANK(i));
8341 error->pipe[i].hsync = I915_READ(HSYNC(i));
8342 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8343 error->pipe[i].vblank = I915_READ(VBLANK(i));
8344 error->pipe[i].vsync = I915_READ(VSYNC(i));
8345 }
8346
8347 return error;
8348}
8349
8350void
8351intel_display_print_error_state(struct seq_file *m,
8352 struct drm_device *dev,
8353 struct intel_display_error_state *error)
8354{
8355 int i;
8356
8357 for (i = 0; i < 2; i++) {
8358 seq_printf(m, "Pipe [%d]:\n", i);
8359 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8360 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8361 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8362 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8363 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8364 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8365 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8366 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8367
8368 seq_printf(m, "Plane [%d]:\n", i);
8369 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8370 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8371 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8372 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8373 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8374 if (INTEL_INFO(dev)->gen >= 4) {
8375 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8376 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8377 }
8378
8379 seq_printf(m, "Cursor [%d]:\n", i);
8380 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8381 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8382 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8383 }
8384}
8385#endif
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