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drm/i915/dp: Log the DPCD only if we have successfully retrieved one
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
1000 /* XXX: IBX has different SDEISR bits */
1001 if (HAS_PCH_IBX(dev_priv->dev))
1002 return true;
1003
1004 switch(port->port) {
1005 case PORT_B:
1006 bit = SDE_PORTB_HOTPLUG_CPT;
1007 break;
1008 case PORT_C:
1009 bit = SDE_PORTC_HOTPLUG_CPT;
1010 break;
1011 case PORT_D:
1012 bit = SDE_PORTD_HOTPLUG_CPT;
1013 break;
1014 default:
1015 return true;
1016 }
1017
1018 return I915_READ(SDEISR) & bit;
1019}
1020
b24e7179
JB		 1021static const char *state_string(bool enabled)
1022{
1023 return enabled ? "on" : "off";
1024}
1025
1026/* Only for pre-ILK configs */
1027static void assert_pll(struct drm_i915_private *dev_priv,
1028 enum pipe pipe, bool state)
1029{
1030 int reg;
1031 u32 val;
1032 bool cur_state;
1033
1034 reg = DPLL(pipe);
1035 val = I915_READ(reg);
1036 cur_state = !!(val & DPLL_VCO_ENABLE);
1037 WARN(cur_state != state,
1038 "PLL state assertion failure (expected %s, current %s)\n",
1039 state_string(state), state_string(cur_state));
1040}
1041#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1042#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1043
040484af
JB		 1044/* For ILK+ */
1045static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1046 struct intel_pch_pll *pll,
1047 struct intel_crtc *crtc,
1048 bool state)
040484af 1049{
040484af
JB		 1050 u32 val;
1051 bool cur_state;
1052
9d82aa17
ED		 1053 if (HAS_PCH_LPT(dev_priv->dev)) {
1054 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1055 return;
1056 }
1057
92b27b08
CW		 1058 if (WARN (!pll,
1059 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1060 return;
ee7b9f93 1061
92b27b08
CW		 1062 val = I915_READ(pll->pll_reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1066 pll->pll_reg, state_string(state), state_string(cur_state), val);
1067
1068 /* Make sure the selected PLL is correctly attached to the transcoder */
1069 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1070 u32 pch_dpll;
1071
1072 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1073 cur_state = pll->pll_reg == _PCH_DPLL_B;
1074 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1075 "PLL[%d] not attached to this transcoder %d: %08x\n",
1076 cur_state, crtc->pipe, pch_dpll)) {
1077 cur_state = !!(val >> (4*crtc->pipe + 3));
1078 WARN(cur_state != state,
1079 "PLL[%d] not %s on this transcoder %d: %08x\n",
1080 pll->pll_reg == _PCH_DPLL_B,
1081 state_string(state),
1082 crtc->pipe,
1083 val);
1084 }
d3ccbe86 1085 }
040484af 1086}
92b27b08
CW		 1087#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1088#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1089
1090static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
1092{
1093 int reg;
1094 u32 val;
1095 bool cur_state;
ad80a810
PZ		 1096 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1097 pipe);
040484af 1098
affa9354
PZ		 1099 if (HAS_DDI(dev_priv->dev)) {
1100 /* DDI does not have a specific FDI_TX register */
ad80a810 1101 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1102 val = I915_READ(reg);
ad80a810 1103 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1104 } else {
1105 reg = FDI_TX_CTL(pipe);
1106 val = I915_READ(reg);
1107 cur_state = !!(val & FDI_TX_ENABLE);
1108 }
040484af
JB		 1109 WARN(cur_state != state,
1110 "FDI TX state assertion failure (expected %s, current %s)\n",
1111 state_string(state), state_string(cur_state));
1112}
1113#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1114#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1115
1116static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118{
1119 int reg;
1120 u32 val;
1121 bool cur_state;
1122
d63fa0dc
PZ		 1123 reg = FDI_RX_CTL(pipe);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1126 WARN(cur_state != state,
1127 "FDI RX state assertion failure (expected %s, current %s)\n",
1128 state_string(state), state_string(cur_state));
1129}
1130#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1131#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1132
1133static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1134 enum pipe pipe)
1135{
1136 int reg;
1137 u32 val;
1138
1139 /* ILK FDI PLL is always enabled */
1140 if (dev_priv->info->gen == 5)
1141 return;
1142
bf507ef7 1143 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1144 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1145 return;
1146
040484af
JB		 1147 reg = FDI_TX_CTL(pipe);
1148 val = I915_READ(reg);
1149 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1150}
1151
1152static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1153 enum pipe pipe)
1154{
1155 int reg;
1156 u32 val;
1157
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1161}
1162
ea0760cf
JB		 1163static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 enum pipe pipe)
1165{
1166 int pp_reg, lvds_reg;
1167 u32 val;
1168 enum pipe panel_pipe = PIPE_A;
0de3b485 1169 bool locked = true;
ea0760cf
JB		 1170
1171 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1172 pp_reg = PCH_PP_CONTROL;
1173 lvds_reg = PCH_LVDS;
1174 } else {
1175 pp_reg = PP_CONTROL;
1176 lvds_reg = LVDS;
1177 }
1178
1179 val = I915_READ(pp_reg);
1180 if (!(val & PANEL_POWER_ON) ||
1181 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1182 locked = false;
1183
1184 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1186
1187 WARN(panel_pipe == pipe && locked,
1188 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1189 pipe_name(pipe));
ea0760cf
JB		 1190}
1191
b840d907
JB		 1192void assert_pipe(struct drm_i915_private *dev_priv,
1193 enum pipe pipe, bool state)
b24e7179
JB		 1194{
1195 int reg;
1196 u32 val;
63d7bbe9 1197 bool cur_state;
702e7a56
PZ		 1198 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1199 pipe);
b24e7179 1200
8e636784
DV		 1201 /* if we need the pipe A quirk it must be always on */
1202 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1203 state = true;
1204
702e7a56 1205 reg = PIPECONF(cpu_transcoder);
b24e7179 1206 val = I915_READ(reg);
63d7bbe9
JB		 1207 cur_state = !!(val & PIPECONF_ENABLE);
1208 WARN(cur_state != state,
1209 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1210 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1211}
1212
931872fc
CW		 1213static void assert_plane(struct drm_i915_private *dev_priv,
1214 enum plane plane, bool state)
b24e7179
JB		 1215{
1216 int reg;
1217 u32 val;
931872fc 1218 bool cur_state;
b24e7179
JB		 1219
1220 reg = DSPCNTR(plane);
1221 val = I915_READ(reg);
931872fc
CW		 1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
b24e7179
JB		 1231static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233{
1234 int reg, i;
1235 u32 val;
1236 int cur_pipe;
1237
19ec1358 1238 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1239 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1240 reg = DSPCNTR(pipe);
1241 val = I915_READ(reg);
1242 WARN((val & DISPLAY_PLANE_ENABLE),
1243 "plane %c assertion failure, should be disabled but not\n",
1244 plane_name(pipe));
19ec1358 1245 return;
28c05794 1246 }
19ec1358 1247
b24e7179
JB		 1248 /* Need to check both planes against the pipe */
1249 for (i = 0; i < 2; i++) {
1250 reg = DSPCNTR(i);
1251 val = I915_READ(reg);
1252 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1253 DISPPLANE_SEL_PIPE_SHIFT;
1254 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1255 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1256 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1257 }
1258}
1259
92f2584a
JB		 1260static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1261{
1262 u32 val;
1263 bool enabled;
1264
9d82aa17
ED		 1265 if (HAS_PCH_LPT(dev_priv->dev)) {
1266 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1267 return;
1268 }
1269
92f2584a
JB		 1270 val = I915_READ(PCH_DREF_CONTROL);
1271 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1272 DREF_SUPERSPREAD_SOURCE_MASK));
1273 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1274}
1275
1276static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe)
1278{
1279 int reg;
1280 u32 val;
1281 bool enabled;
1282
1283 reg = TRANSCONF(pipe);
1284 val = I915_READ(reg);
1285 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1286 WARN(enabled,
1287 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1288 pipe_name(pipe));
92f2584a
JB		 1289}
1290
4e634389
KP		 1291static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1293{
1294 if ((val & DP_PORT_EN) == 0)
1295 return false;
1296
1297 if (HAS_PCH_CPT(dev_priv->dev)) {
1298 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1299 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1300 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1301 return false;
1302 } else {
1303 if ((val & DP_PIPE_MASK) != (pipe << 30))
1304 return false;
1305 }
1306 return true;
1307}
1308
1519b995
KP		 1309static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 val)
1311{
1312 if ((val & PORT_ENABLE) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1317 return false;
1318 } else {
1319 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1320 return false;
1321 }
1322 return true;
1323}
1324
1325static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1326 enum pipe pipe, u32 val)
1327{
1328 if ((val & LVDS_PORT_EN) == 0)
1329 return false;
1330
1331 if (HAS_PCH_CPT(dev_priv->dev)) {
1332 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1333 return false;
1334 } else {
1335 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1336 return false;
1337 }
1338 return true;
1339}
1340
1341static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 val)
1343{
1344 if ((val & ADPA_DAC_ENABLE) == 0)
1345 return false;
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
291906f1 1356static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1357 enum pipe pipe, int reg, u32 port_sel)
291906f1 1358{
47a05eca 1359 u32 val = I915_READ(reg);
4e634389 1360 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1361 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1362 reg, pipe_name(pipe));
de9a35ab 1363
75c5da27
DV		 1364 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1365 && (val & DP_PIPEB_SELECT),
de9a35ab 1366 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1367}
1368
1369static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, int reg)
1371{
47a05eca 1372 u32 val = I915_READ(reg);
b70ad586 1373 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1374 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1375 reg, pipe_name(pipe));
de9a35ab 1376
75c5da27
DV		 1377 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1378 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1379 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1380}
1381
1382static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384{
1385 int reg;
1386 u32 val;
291906f1 1387
f0575e92
KP		 1388 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1389 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1390 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1391
1392 reg = PCH_ADPA;
1393 val = I915_READ(reg);
b70ad586 1394 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1395 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1396 pipe_name(pipe));
291906f1
JB		 1397
1398 reg = PCH_LVDS;
1399 val = I915_READ(reg);
b70ad586 1400 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1401 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 pipe_name(pipe));
291906f1
JB		 1403
1404 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1405 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1406 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1407}
1408
63d7bbe9
JB		 1409/**
1410 * intel_enable_pll - enable a PLL
1411 * @dev_priv: i915 private structure
1412 * @pipe: pipe PLL to enable
1413 *
1414 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1415 * make sure the PLL reg is writable first though, since the panel write
1416 * protect mechanism may be enabled.
1417 *
1418 * Note! This is for pre-ILK only.
7434a255
TR		 1419 *
1420 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1421 */
1422static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1423{
1424 int reg;
1425 u32 val;
1426
1427 /* No really, not for ILK+ */
a0c4da24 1428 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1429
1430 /* PLL is protected by panel, make sure we can write it */
1431 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1432 assert_panel_unlocked(dev_priv, pipe);
1433
1434 reg = DPLL(pipe);
1435 val = I915_READ(reg);
1436 val |= DPLL_VCO_ENABLE;
1437
1438 /* We do this three times for luck */
1439 I915_WRITE(reg, val);
1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
1442 I915_WRITE(reg, val);
1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445 I915_WRITE(reg, val);
1446 POSTING_READ(reg);
1447 udelay(150); /* wait for warmup */
1448}
1449
1450/**
1451 * intel_disable_pll - disable a PLL
1452 * @dev_priv: i915 private structure
1453 * @pipe: pipe PLL to disable
1454 *
1455 * Disable the PLL for @pipe, making sure the pipe is off first.
1456 *
1457 * Note! This is for pre-ILK only.
1458 */
1459static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1460{
1461 int reg;
1462 u32 val;
1463
1464 /* Don't disable pipe A or pipe A PLLs if needed */
1465 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1466 return;
1467
1468 /* Make sure the pipe isn't still relying on us */
1469 assert_pipe_disabled(dev_priv, pipe);
1470
1471 reg = DPLL(pipe);
1472 val = I915_READ(reg);
1473 val &= ~DPLL_VCO_ENABLE;
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476}
1477
a416edef
ED		 1478/* SBI access */
1479static void
1480intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1481{
09153000 1482 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1483
39fb50f6 1484 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1485 100)) {
1486 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1487 return;
a416edef
ED		 1488 }
1489
1490 I915_WRITE(SBI_ADDR,
1491 (reg << 16));
1492 I915_WRITE(SBI_DATA,
1493 value);
1494 I915_WRITE(SBI_CTL_STAT,
1495 SBI_BUSY |
1496 SBI_CTL_OP_CRWR);
1497
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1501 return;
a416edef 1502 }
a416edef
ED		 1503}
1504
1505static u32
1506intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1507{
09153000 1508 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1509
39fb50f6 1510 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1511 100)) {
1512 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1513 return 0;
a416edef
ED		 1514 }
1515
1516 I915_WRITE(SBI_ADDR,
1517 (reg << 16));
1518 I915_WRITE(SBI_CTL_STAT,
1519 SBI_BUSY |
1520 SBI_CTL_OP_CRRD);
1521
39fb50f6 1522 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1523 100)) {
1524 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1525 return 0;
a416edef
ED		 1526 }
1527
09153000 1528 return I915_READ(SBI_DATA);
a416edef
ED		 1529}
1530
92f2584a 1531/**
b6b4e185 1532 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1533 * @dev_priv: i915 private structure
1534 * @pipe: pipe PLL to enable
1535 *
1536 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1537 * drives the transcoder clock.
1538 */
b6b4e185 1539static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1540{
ee7b9f93 1541 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1542 struct intel_pch_pll *pll;
92f2584a
JB		 1543 int reg;
1544 u32 val;
1545
48da64a8 1546 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1547 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1548 pll = intel_crtc->pch_pll;
1549 if (pll == NULL)
1550 return;
1551
1552 if (WARN_ON(pll->refcount == 0))
1553 return;
ee7b9f93
JB		 1554
1555 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1556 pll->pll_reg, pll->active, pll->on,
1557 intel_crtc->base.base.id);
92f2584a
JB		 1558
1559 /* PCH refclock must be enabled first */
1560 assert_pch_refclk_enabled(dev_priv);
1561
ee7b9f93 1562 if (pll->active++ && pll->on) {
92b27b08 1563 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1564 return;
1565 }
1566
1567 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1568
1569 reg = pll->pll_reg;
92f2584a
JB		 1570 val = I915_READ(reg);
1571 val |= DPLL_VCO_ENABLE;
1572 I915_WRITE(reg, val);
1573 POSTING_READ(reg);
1574 udelay(200);
ee7b9f93
JB		 1575
1576 pll->on = true;
92f2584a
JB		 1577}
1578
ee7b9f93 1579static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1580{
ee7b9f93
JB		 1581 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1582 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1583 int reg;
ee7b9f93 1584 u32 val;
4c609cb8 1585
92f2584a
JB		 1586 /* PCH only available on ILK+ */
1587 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1588 if (pll == NULL)
1589 return;
92f2584a 1590
48da64a8
CW		 1591 if (WARN_ON(pll->refcount == 0))
1592 return;
7a419866 1593
ee7b9f93
JB		 1594 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
7a419866 1597
48da64a8 1598 if (WARN_ON(pll->active == 0)) {
92b27b08 1599 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1600 return;
1601 }
1602
ee7b9f93 1603 if (--pll->active) {
92b27b08 1604 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1605 return;
ee7b9f93
JB		 1606 }
1607
1608 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1609
1610 /* Make sure transcoder isn't still depending on us */
1611 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1612
ee7b9f93 1613 reg = pll->pll_reg;
92f2584a
JB		 1614 val = I915_READ(reg);
1615 val &= ~DPLL_VCO_ENABLE;
1616 I915_WRITE(reg, val);
1617 POSTING_READ(reg);
1618 udelay(200);
ee7b9f93
JB		 1619
1620 pll->on = false;
92f2584a
JB		 1621}
1622
b8a4f404
PZ		 1623static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1624 enum pipe pipe)
040484af 1625{
23670b32 1626 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1627 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1628 uint32_t reg, val, pipeconf_val;
040484af
JB		 1629
1630 /* PCH only available on ILK+ */
1631 BUG_ON(dev_priv->info->gen < 5);
1632
1633 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1634 assert_pch_pll_enabled(dev_priv,
1635 to_intel_crtc(crtc)->pch_pll,
1636 to_intel_crtc(crtc));
040484af
JB		 1637
1638 /* FDI must be feeding us bits for PCH ports */
1639 assert_fdi_tx_enabled(dev_priv, pipe);
1640 assert_fdi_rx_enabled(dev_priv, pipe);
1641
23670b32
DV		 1642 if (HAS_PCH_CPT(dev)) {
1643 /* Workaround: Set the timing override bit before enabling the
1644 * pch transcoder. */
1645 reg = TRANS_CHICKEN2(pipe);
1646 val = I915_READ(reg);
1647 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1648 I915_WRITE(reg, val);
59c859d6 1649 }
23670b32 1650
040484af
JB		 1651 reg = TRANSCONF(pipe);
1652 val = I915_READ(reg);
5f7f726d 1653 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1654
1655 if (HAS_PCH_IBX(dev_priv->dev)) {
1656 /*
1657 * make the BPC in transcoder be consistent with
1658 * that in pipeconf reg.
1659 */
1660 val &= ~PIPE_BPC_MASK;
5f7f726d 1661 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1662 }
5f7f726d
PZ		 1663
1664 val &= ~TRANS_INTERLACE_MASK;
1665 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1666 if (HAS_PCH_IBX(dev_priv->dev) &&
1667 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1668 val |= TRANS_LEGACY_INTERLACED_ILK;
1669 else
1670 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1671 else
1672 val |= TRANS_PROGRESSIVE;
1673
040484af
JB		 1674 I915_WRITE(reg, val | TRANS_ENABLE);
1675 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1676 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1677}
1678
8fb033d7 1679static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1680 enum transcoder cpu_transcoder)
040484af 1681{
8fb033d7 1682 u32 val, pipeconf_val;
8fb033d7
PZ		 1683
1684 /* PCH only available on ILK+ */
1685 BUG_ON(dev_priv->info->gen < 5);
1686
8fb033d7 1687 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1688 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1689 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1690
223a6fdf
PZ		 1691 /* Workaround: set timing override bit. */
1692 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1693 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1694 I915_WRITE(_TRANSA_CHICKEN2, val);
1695
25f3ef11 1696 val = TRANS_ENABLE;
937bb610 1697 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1698
9a76b1c6
PZ		 1699 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1700 PIPECONF_INTERLACED_ILK)
a35f2679 1701 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1702 else
1703 val |= TRANS_PROGRESSIVE;
1704
25f3ef11 1705 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1706 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1707 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1708}
1709
b8a4f404
PZ		 1710static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1711 enum pipe pipe)
040484af 1712{
23670b32
DV		 1713 struct drm_device *dev = dev_priv->dev;
1714 uint32_t reg, val;
040484af
JB		 1715
1716 /* FDI relies on the transcoder */
1717 assert_fdi_tx_disabled(dev_priv, pipe);
1718 assert_fdi_rx_disabled(dev_priv, pipe);
1719
291906f1
JB		 1720 /* Ports must be off as well */
1721 assert_pch_ports_disabled(dev_priv, pipe);
1722
040484af
JB		 1723 reg = TRANSCONF(pipe);
1724 val = I915_READ(reg);
1725 val &= ~TRANS_ENABLE;
1726 I915_WRITE(reg, val);
1727 /* wait for PCH transcoder off, transcoder state */
1728 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1729 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1730
1731 if (!HAS_PCH_IBX(dev)) {
1732 /* Workaround: Clear the timing override chicken bit again. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
040484af
JB		 1738}
1739
ab4d966c 1740static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1741{
8fb033d7
PZ		 1742 u32 val;
1743
8a52fd9f 1744 val = I915_READ(_TRANSACONF);
8fb033d7 1745 val &= ~TRANS_ENABLE;
8a52fd9f 1746 I915_WRITE(_TRANSACONF, val);
8fb033d7 1747 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1748 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1749 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1750
1751 /* Workaround: clear timing override bit. */
1752 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1753 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1754 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1755}
1756
b24e7179 1757/**
309cfea8 1758 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe to enable
040484af 1761 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1762 *
1763 * Enable @pipe, making sure that various hardware specific requirements
1764 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1765 *
1766 * @pipe should be %PIPE_A or %PIPE_B.
1767 *
1768 * Will wait until the pipe is actually running (i.e. first vblank) before
1769 * returning.
1770 */
040484af
JB		 1771static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1772 bool pch_port)
b24e7179 1773{
702e7a56
PZ		 1774 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1775 pipe);
1a240d4d 1776 enum pipe pch_transcoder;
b24e7179
JB		 1777 int reg;
1778 u32 val;
1779
cc391bbb
PZ		 1780 if (IS_HASWELL(dev_priv->dev))
1781 pch_transcoder = TRANSCODER_A;
1782 else
1783 pch_transcoder = pipe;
1784
b24e7179
JB		 1785 /*
1786 * A pipe without a PLL won't actually be able to drive bits from
1787 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1788 * need the check.
1789 */
1790 if (!HAS_PCH_SPLIT(dev_priv->dev))
1791 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1792 else {
1793 if (pch_port) {
1794 /* if driving the PCH, we need FDI enabled */
cc391bbb 1795 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1796 assert_fdi_tx_pll_enabled(dev_priv,
1797 (enum pipe) cpu_transcoder);
040484af
JB		 1798 }
1799 /* FIXME: assert CPU port conditions for SNB+ */
1800 }
b24e7179 1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if (val & PIPECONF_ENABLE)
1805 return;
1806
1807 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_vblank(dev_priv->dev, pipe);
1809}
1810
1811/**
309cfea8 1812 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1813 * @dev_priv: i915 private structure
1814 * @pipe: pipe to disable
1815 *
1816 * Disable @pipe, making sure that various hardware specific requirements
1817 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1818 *
1819 * @pipe should be %PIPE_A or %PIPE_B.
1820 *
1821 * Will wait until the pipe has shut down before returning.
1822 */
1823static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1824 enum pipe pipe)
1825{
702e7a56
PZ		 1826 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1827 pipe);
b24e7179
JB		 1828 int reg;
1829 u32 val;
1830
1831 /*
1832 * Make sure planes won't keep trying to pump pixels to us,
1833 * or we might hang the display.
1834 */
1835 assert_planes_disabled(dev_priv, pipe);
1836
1837 /* Don't disable pipe A or pipe A PLLs if needed */
1838 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1839 return;
1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if ((val & PIPECONF_ENABLE) == 0)
1844 return;
1845
1846 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1848}
1849
d74362c9
KP		 1850/*
1851 * Plane regs are double buffered, going from enabled->disabled needs a
1852 * trigger in order to latch. The display address reg provides this.
1853 */
6f1d69b0 1854void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1855 enum plane plane)
1856{
14f86147
DL		 1857 if (dev_priv->info->gen >= 4)
1858 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1859 else
1860 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1861}
1862
b24e7179
JB		 1863/**
1864 * intel_enable_plane - enable a display plane on a given pipe
1865 * @dev_priv: i915 private structure
1866 * @plane: plane to enable
1867 * @pipe: pipe being fed
1868 *
1869 * Enable @plane on @pipe, making sure that @pipe is running first.
1870 */
1871static void intel_enable_plane(struct drm_i915_private *dev_priv,
1872 enum plane plane, enum pipe pipe)
1873{
1874 int reg;
1875 u32 val;
1876
1877 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1878 assert_pipe_enabled(dev_priv, pipe);
1879
1880 reg = DSPCNTR(plane);
1881 val = I915_READ(reg);
00d70b15
CW		 1882 if (val & DISPLAY_PLANE_ENABLE)
1883 return;
1884
1885 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1886 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1887 intel_wait_for_vblank(dev_priv->dev, pipe);
1888}
1889
b24e7179
JB		 1890/**
1891 * intel_disable_plane - disable a display plane
1892 * @dev_priv: i915 private structure
1893 * @plane: plane to disable
1894 * @pipe: pipe consuming the data
1895 *
1896 * Disable @plane; should be an independent operation.
1897 */
1898static void intel_disable_plane(struct drm_i915_private *dev_priv,
1899 enum plane plane, enum pipe pipe)
1900{
1901 int reg;
1902 u32 val;
1903
1904 reg = DSPCNTR(plane);
1905 val = I915_READ(reg);
00d70b15
CW		 1906 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1907 return;
1908
1909 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1910 intel_flush_display_plane(dev_priv, plane);
1911 intel_wait_for_vblank(dev_priv->dev, pipe);
1912}
1913
127bd2ac 1914int
48b956c5 1915intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1916 struct drm_i915_gem_object *obj,
919926ae 1917 struct intel_ring_buffer *pipelined)
6b95a207 1918{
ce453d81 1919 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1920 u32 alignment;
1921 int ret;
1922
05394f39 1923 switch (obj->tiling_mode) {
6b95a207 1924 case I915_TILING_NONE:
534843da
CW		 1925 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1926 alignment = 128 * 1024;
a6c45cf0 1927 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1928 alignment = 4 * 1024;
1929 else
1930 alignment = 64 * 1024;
6b95a207
KH		 1931 break;
1932 case I915_TILING_X:
1933 /* pin() will align the object as required by fence */
1934 alignment = 0;
1935 break;
1936 case I915_TILING_Y:
1937 /* FIXME: Is this true? */
1938 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1939 return -EINVAL;
1940 default:
1941 BUG();
1942 }
1943
ce453d81 1944 dev_priv->mm.interruptible = false;
2da3b9b9 1945 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1946 if (ret)
ce453d81 1947 goto err_interruptible;
6b95a207
KH		 1948
1949 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950 * fence, whereas 965+ only requires a fence if using
1951 * framebuffer compression. For simplicity, we always install
1952 * a fence as the cost is not that onerous.
1953 */
06d98131 1954 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1955 if (ret)
1956 goto err_unpin;
1690e1eb 1957
9a5a53b3 1958 i915_gem_object_pin_fence(obj);
6b95a207 1959
ce453d81 1960 dev_priv->mm.interruptible = true;
6b95a207 1961 return 0;
48b956c5
CW		 1962
1963err_unpin:
1964 i915_gem_object_unpin(obj);
ce453d81
CW		 1965err_interruptible:
1966 dev_priv->mm.interruptible = true;
48b956c5 1967 return ret;
6b95a207
KH		 1968}
1969
1690e1eb
CW		 1970void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1971{
1972 i915_gem_object_unpin_fence(obj);
1973 i915_gem_object_unpin(obj);
1974}
1975
c2c75131
DV		 1976/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1977 * is assumed to be a power-of-two. */
5a35e99e
DL		 1978unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1979 unsigned int bpp,
1980 unsigned int pitch)
c2c75131
DV		 1981{
1982 int tile_rows, tiles;
1983
1984 tile_rows = *y / 8;
1985 *y %= 8;
1986 tiles = *x / (512/bpp);
1987 *x %= 512/bpp;
1988
1989 return tile_rows * pitch * 8 + tiles * 4096;
1990}
1991
17638cd6
JB		 1992static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993 int x, int y)
81255565
JB		 1994{
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998 struct intel_framebuffer *intel_fb;
05394f39 1999 struct drm_i915_gem_object *obj;
81255565 2000 int plane = intel_crtc->plane;
e506a0c6 2001 unsigned long linear_offset;
81255565 2002 u32 dspcntr;
5eddb70b 2003 u32 reg;
81255565
JB		 2004
2005 switch (plane) {
2006 case 0:
2007 case 1:
2008 break;
2009 default:
2010 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011 return -EINVAL;
2012 }
2013
2014 intel_fb = to_intel_framebuffer(fb);
2015 obj = intel_fb->obj;
81255565 2016
5eddb70b
CW		 2017 reg = DSPCNTR(plane);
2018 dspcntr = I915_READ(reg);
81255565
JB		 2019 /* Mask out pixel format bits in case we change it */
2020 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2021 switch (fb->pixel_format) {
2022 case DRM_FORMAT_C8:
81255565
JB		 2023 dspcntr |= DISPPLANE_8BPP;
2024 break;
57779d06
VS		 2025 case DRM_FORMAT_XRGB1555:
2026 case DRM_FORMAT_ARGB1555:
2027 dspcntr |= DISPPLANE_BGRX555;
81255565 2028 break;
57779d06
VS		 2029 case DRM_FORMAT_RGB565:
2030 dspcntr |= DISPPLANE_BGRX565;
2031 break;
2032 case DRM_FORMAT_XRGB8888:
2033 case DRM_FORMAT_ARGB8888:
2034 dspcntr |= DISPPLANE_BGRX888;
2035 break;
2036 case DRM_FORMAT_XBGR8888:
2037 case DRM_FORMAT_ABGR8888:
2038 dspcntr |= DISPPLANE_RGBX888;
2039 break;
2040 case DRM_FORMAT_XRGB2101010:
2041 case DRM_FORMAT_ARGB2101010:
2042 dspcntr |= DISPPLANE_BGRX101010;
2043 break;
2044 case DRM_FORMAT_XBGR2101010:
2045 case DRM_FORMAT_ABGR2101010:
2046 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2047 break;
2048 default:
57779d06 2049 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2050 return -EINVAL;
2051 }
57779d06 2052
a6c45cf0 2053 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2054 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2055 dspcntr |= DISPPLANE_TILED;
2056 else
2057 dspcntr &= ~DISPPLANE_TILED;
2058 }
2059
5eddb70b 2060 I915_WRITE(reg, dspcntr);
81255565 2061
e506a0c6 2062 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2063
c2c75131
DV		 2064 if (INTEL_INFO(dev)->gen >= 4) {
2065 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2066 intel_gen4_compute_offset_xtiled(&x, &y,
2067 fb->bits_per_pixel / 8,
2068 fb->pitches[0]);
c2c75131
DV		 2069 linear_offset -= intel_crtc->dspaddr_offset;
2070 } else {
e506a0c6 2071 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2072 }
e506a0c6
DV		 2073
2074 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2075 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2076 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2077 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2078 I915_MODIFY_DISPBASE(DSPSURF(plane),
2079 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2082 } else
e506a0c6 2083 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2084 POSTING_READ(reg);
81255565 2085
17638cd6
JB		 2086 return 0;
2087}
2088
2089static int ironlake_update_plane(struct drm_crtc *crtc,
2090 struct drm_framebuffer *fb, int x, int y)
2091{
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 struct intel_framebuffer *intel_fb;
2096 struct drm_i915_gem_object *obj;
2097 int plane = intel_crtc->plane;
e506a0c6 2098 unsigned long linear_offset;
17638cd6
JB		 2099 u32 dspcntr;
2100 u32 reg;
2101
2102 switch (plane) {
2103 case 0:
2104 case 1:
27f8227b 2105 case 2:
17638cd6
JB		 2106 break;
2107 default:
2108 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2109 return -EINVAL;
2110 }
2111
2112 intel_fb = to_intel_framebuffer(fb);
2113 obj = intel_fb->obj;
2114
2115 reg = DSPCNTR(plane);
2116 dspcntr = I915_READ(reg);
2117 /* Mask out pixel format bits in case we change it */
2118 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2119 switch (fb->pixel_format) {
2120 case DRM_FORMAT_C8:
17638cd6
JB		 2121 dspcntr |= DISPPLANE_8BPP;
2122 break;
57779d06
VS		 2123 case DRM_FORMAT_RGB565:
2124 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2125 break;
57779d06
VS		 2126 case DRM_FORMAT_XRGB8888:
2127 case DRM_FORMAT_ARGB8888:
2128 dspcntr |= DISPPLANE_BGRX888;
2129 break;
2130 case DRM_FORMAT_XBGR8888:
2131 case DRM_FORMAT_ABGR8888:
2132 dspcntr |= DISPPLANE_RGBX888;
2133 break;
2134 case DRM_FORMAT_XRGB2101010:
2135 case DRM_FORMAT_ARGB2101010:
2136 dspcntr |= DISPPLANE_BGRX101010;
2137 break;
2138 case DRM_FORMAT_XBGR2101010:
2139 case DRM_FORMAT_ABGR2101010:
2140 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2141 break;
2142 default:
57779d06 2143 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2144 return -EINVAL;
2145 }
2146
2147 if (obj->tiling_mode != I915_TILING_NONE)
2148 dspcntr |= DISPPLANE_TILED;
2149 else
2150 dspcntr &= ~DISPPLANE_TILED;
2151
2152 /* must disable */
2153 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2154
2155 I915_WRITE(reg, dspcntr);
2156
e506a0c6 2157 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2158 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2159 intel_gen4_compute_offset_xtiled(&x, &y,
2160 fb->bits_per_pixel / 8,
2161 fb->pitches[0]);
c2c75131 2162 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2163
e506a0c6
DV		 2164 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2165 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2166 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2167 I915_MODIFY_DISPBASE(DSPSURF(plane),
2168 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2169 if (IS_HASWELL(dev)) {
2170 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2171 } else {
2172 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2173 I915_WRITE(DSPLINOFF(plane), linear_offset);
2174 }
17638cd6
JB		 2175 POSTING_READ(reg);
2176
2177 return 0;
2178}
2179
2180/* Assume fb object is pinned & idle & fenced and just update base pointers */
2181static int
2182intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2183 int x, int y, enum mode_set_atomic state)
2184{
2185 struct drm_device *dev = crtc->dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2187
6b8e6ed0
CW		 2188 if (dev_priv->display.disable_fbc)
2189 dev_priv->display.disable_fbc(dev);
3dec0095 2190 intel_increase_pllclock(crtc);
81255565 2191
6b8e6ed0 2192 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2193}
2194
14667a4b
CW		 2195static int
2196intel_finish_fb(struct drm_framebuffer *old_fb)
2197{
2198 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2199 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2200 bool was_interruptible = dev_priv->mm.interruptible;
2201 int ret;
2202
2203 wait_event(dev_priv->pending_flip_queue,
2204 atomic_read(&dev_priv->mm.wedged) ||
2205 atomic_read(&obj->pending_flip) == 0);
2206
2207 /* Big Hammer, we also need to ensure that any pending
2208 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2209 * current scanout is retired before unpinning the old
2210 * framebuffer.
2211 *
2212 * This should only fail upon a hung GPU, in which case we
2213 * can safely continue.
2214 */
2215 dev_priv->mm.interruptible = false;
2216 ret = i915_gem_object_finish_gpu(obj);
2217 dev_priv->mm.interruptible = was_interruptible;
2218
2219 return ret;
2220}
2221
198598d0
VS		 2222static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2223{
2224 struct drm_device *dev = crtc->dev;
2225 struct drm_i915_master_private *master_priv;
2226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2227
2228 if (!dev->primary->master)
2229 return;
2230
2231 master_priv = dev->primary->master->driver_priv;
2232 if (!master_priv->sarea_priv)
2233 return;
2234
2235 switch (intel_crtc->pipe) {
2236 case 0:
2237 master_priv->sarea_priv->pipeA_x = x;
2238 master_priv->sarea_priv->pipeA_y = y;
2239 break;
2240 case 1:
2241 master_priv->sarea_priv->pipeB_x = x;
2242 master_priv->sarea_priv->pipeB_y = y;
2243 break;
2244 default:
2245 break;
2246 }
2247}
2248
5c3b82e2 2249static int
3c4fdcfb 2250intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2251 struct drm_framebuffer *fb)
79e53945
JB		 2252{
2253 struct drm_device *dev = crtc->dev;
6b8e6ed0 2254 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2256 struct drm_framebuffer *old_fb;
5c3b82e2 2257 int ret;
79e53945
JB		 2258
2259 /* no fb bound */
94352cf9 2260 if (!fb) {
a5071c2f 2261 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2262 return 0;
2263 }
2264
5826eca5
ED		 2265 if(intel_crtc->plane > dev_priv->num_pipe) {
2266 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2267 intel_crtc->plane,
2268 dev_priv->num_pipe);
5c3b82e2 2269 return -EINVAL;
79e53945
JB		 2270 }
2271
5c3b82e2 2272 mutex_lock(&dev->struct_mutex);
265db958 2273 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2274 to_intel_framebuffer(fb)->obj,
919926ae 2275 NULL);
5c3b82e2
CW		 2276 if (ret != 0) {
2277 mutex_unlock(&dev->struct_mutex);
a5071c2f 2278 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2279 return ret;
2280 }
79e53945 2281
94352cf9
DV		 2282 if (crtc->fb)
2283 intel_finish_fb(crtc->fb);
265db958 2284
94352cf9 2285 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2286 if (ret) {
94352cf9 2287 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2288 mutex_unlock(&dev->struct_mutex);
a5071c2f 2289 DRM_ERROR("failed to update base address\n");
4e6cfefc 2290 return ret;
79e53945 2291 }
3c4fdcfb 2292
94352cf9
DV		 2293 old_fb = crtc->fb;
2294 crtc->fb = fb;
6c4c86f5
DV		 2295 crtc->x = x;
2296 crtc->y = y;
94352cf9 2297
b7f1de28
CW		 2298 if (old_fb) {
2299 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2300 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2301 }
652c393a 2302
6b8e6ed0 2303 intel_update_fbc(dev);
5c3b82e2 2304 mutex_unlock(&dev->struct_mutex);
79e53945 2305
198598d0 2306 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2307
2308 return 0;
79e53945
JB		 2309}
2310
5e84e1a4
ZW		 2311static void intel_fdi_normal_train(struct drm_crtc *crtc)
2312{
2313 struct drm_device *dev = crtc->dev;
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2316 int pipe = intel_crtc->pipe;
2317 u32 reg, temp;
2318
2319 /* enable normal train */
2320 reg = FDI_TX_CTL(pipe);
2321 temp = I915_READ(reg);
61e499bf 2322 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2323 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2324 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2325 } else {
2326 temp &= ~FDI_LINK_TRAIN_NONE;
2327 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2328 }
5e84e1a4
ZW		 2329 I915_WRITE(reg, temp);
2330
2331 reg = FDI_RX_CTL(pipe);
2332 temp = I915_READ(reg);
2333 if (HAS_PCH_CPT(dev)) {
2334 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2335 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2336 } else {
2337 temp &= ~FDI_LINK_TRAIN_NONE;
2338 temp |= FDI_LINK_TRAIN_NONE;
2339 }
2340 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2341
2342 /* wait one idle pattern time */
2343 POSTING_READ(reg);
2344 udelay(1000);
357555c0
JB		 2345
2346 /* IVB wants error correction enabled */
2347 if (IS_IVYBRIDGE(dev))
2348 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2349 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2350}
2351
291427f5
JB		 2352static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2353{
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 u32 flags = I915_READ(SOUTH_CHICKEN1);
2356
2357 flags |= FDI_PHASE_SYNC_OVR(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2359 flags |= FDI_PHASE_SYNC_EN(pipe);
2360 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2361 POSTING_READ(SOUTH_CHICKEN1);
2362}
2363
01a415fd
DV		 2364static void ivb_modeset_global_resources(struct drm_device *dev)
2365{
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *pipe_B_crtc =
2368 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2369 struct intel_crtc *pipe_C_crtc =
2370 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2371 uint32_t temp;
2372
2373 /* When everything is off disable fdi C so that we could enable fdi B
2374 * with all lanes. XXX: This misses the case where a pipe is not using
2375 * any pch resources and so doesn't need any fdi lanes. */
2376 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2378 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2379
2380 temp = I915_READ(SOUTH_CHICKEN1);
2381 temp &= ~FDI_BC_BIFURCATION_SELECT;
2382 DRM_DEBUG_KMS("disabling fdi C rx\n");
2383 I915_WRITE(SOUTH_CHICKEN1, temp);
2384 }
2385}
2386
8db9d77b
ZW		 2387/* The FDI link training functions for ILK/Ibexpeak. */
2388static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2389{
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
0fc932b8 2394 int plane = intel_crtc->plane;
5eddb70b 2395 u32 reg, temp, tries;
8db9d77b 2396
0fc932b8
JB		 2397 /* FDI needs bits from pipe & plane first */
2398 assert_pipe_enabled(dev_priv, pipe);
2399 assert_plane_enabled(dev_priv, plane);
2400
e1a44743
AJ		 2401 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2402 for train result */
5eddb70b
CW		 2403 reg = FDI_RX_IMR(pipe);
2404 temp = I915_READ(reg);
e1a44743
AJ		 2405 temp &= ~FDI_RX_SYMBOL_LOCK;
2406 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2407 I915_WRITE(reg, temp);
2408 I915_READ(reg);
e1a44743
AJ		 2409 udelay(150);
2410
8db9d77b 2411 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2412 reg = FDI_TX_CTL(pipe);
2413 temp = I915_READ(reg);
77ffb597
AJ		 2414 temp &= ~(7 << 19);
2415 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2418 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2419
5eddb70b
CW		 2420 reg = FDI_RX_CTL(pipe);
2421 temp = I915_READ(reg);
8db9d77b
ZW		 2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2424 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2425
2426 POSTING_READ(reg);
8db9d77b
ZW		 2427 udelay(150);
2428
5b2adf89 2429 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2432 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2433
5eddb70b 2434 reg = FDI_RX_IIR(pipe);
e1a44743 2435 for (tries = 0; tries < 5; tries++) {
5eddb70b 2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439 if ((temp & FDI_RX_BIT_LOCK)) {
2440 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2441 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2442 break;
2443 }
8db9d77b 2444 }
e1a44743 2445 if (tries == 5)
5eddb70b 2446 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2447
2448 /* Train 2 */
5eddb70b
CW		 2449 reg = FDI_TX_CTL(pipe);
2450 temp = I915_READ(reg);
8db9d77b
ZW		 2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2453 I915_WRITE(reg, temp);
8db9d77b 2454
5eddb70b
CW		 2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 temp &= ~FDI_LINK_TRAIN_NONE;
2458 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2459 I915_WRITE(reg, temp);
8db9d77b 2460
5eddb70b
CW		 2461 POSTING_READ(reg);
2462 udelay(150);
8db9d77b 2463
5eddb70b 2464 reg = FDI_RX_IIR(pipe);
e1a44743 2465 for (tries = 0; tries < 5; tries++) {
5eddb70b 2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2470 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2471 DRM_DEBUG_KMS("FDI train 2 done.\n");
2472 break;
2473 }
8db9d77b 2474 }
e1a44743 2475 if (tries == 5)
5eddb70b 2476 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2477
2478 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2479
8db9d77b
ZW		 2480}
2481
0206e353 2482static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2483 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2484 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2485 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2486 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2487};
2488
2489/* The FDI link training functions for SNB/Cougarpoint. */
2490static void gen6_fdi_link_train(struct drm_crtc *crtc)
2491{
2492 struct drm_device *dev = crtc->dev;
2493 struct drm_i915_private *dev_priv = dev->dev_private;
2494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2495 int pipe = intel_crtc->pipe;
fa37d39e 2496 u32 reg, temp, i, retry;
8db9d77b 2497
e1a44743
AJ		 2498 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2499 for train result */
5eddb70b
CW		 2500 reg = FDI_RX_IMR(pipe);
2501 temp = I915_READ(reg);
e1a44743
AJ		 2502 temp &= ~FDI_RX_SYMBOL_LOCK;
2503 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
e1a44743
AJ		 2507 udelay(150);
2508
8db9d77b 2509 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
77ffb597
AJ		 2512 temp &= ~(7 << 19);
2513 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_1;
2516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517 /* SNB-B */
2518 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2520
d74cf324
DV		 2521 I915_WRITE(FDI_RX_MISC(pipe),
2522 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 if (HAS_PCH_CPT(dev)) {
2527 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2528 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2529 } else {
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 }
5eddb70b
CW		 2533 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2534
2535 POSTING_READ(reg);
8db9d77b
ZW		 2536 udelay(150);
2537
8f5718a6 2538 cpt_phase_pointer_enable(dev, pipe);
291427f5 2539
0206e353 2540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2545 I915_WRITE(reg, temp);
2546
2547 POSTING_READ(reg);
8db9d77b
ZW		 2548 udelay(500);
2549
fa37d39e
SP		 2550 for (retry = 0; retry < 5; retry++) {
2551 reg = FDI_RX_IIR(pipe);
2552 temp = I915_READ(reg);
2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554 if (temp & FDI_RX_BIT_LOCK) {
2555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2556 DRM_DEBUG_KMS("FDI train 1 done.\n");
2557 break;
2558 }
2559 udelay(50);
8db9d77b 2560 }
fa37d39e
SP		 2561 if (retry < 5)
2562 break;
8db9d77b
ZW		 2563 }
2564 if (i == 4)
5eddb70b 2565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2566
2567 /* Train 2 */
5eddb70b
CW		 2568 reg = FDI_TX_CTL(pipe);
2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2;
2572 if (IS_GEN6(dev)) {
2573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2574 /* SNB-B */
2575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2576 }
5eddb70b 2577 I915_WRITE(reg, temp);
8db9d77b 2578
5eddb70b
CW		 2579 reg = FDI_RX_CTL(pipe);
2580 temp = I915_READ(reg);
8db9d77b
ZW		 2581 if (HAS_PCH_CPT(dev)) {
2582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2584 } else {
2585 temp &= ~FDI_LINK_TRAIN_NONE;
2586 temp |= FDI_LINK_TRAIN_PATTERN_2;
2587 }
5eddb70b
CW		 2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
8db9d77b
ZW		 2591 udelay(150);
2592
0206e353 2593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
8db9d77b
ZW		 2596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2598 I915_WRITE(reg, temp);
2599
2600 POSTING_READ(reg);
8db9d77b
ZW		 2601 udelay(500);
2602
fa37d39e
SP		 2603 for (retry = 0; retry < 5; retry++) {
2604 reg = FDI_RX_IIR(pipe);
2605 temp = I915_READ(reg);
2606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2607 if (temp & FDI_RX_SYMBOL_LOCK) {
2608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2609 DRM_DEBUG_KMS("FDI train 2 done.\n");
2610 break;
2611 }
2612 udelay(50);
8db9d77b 2613 }
fa37d39e
SP		 2614 if (retry < 5)
2615 break;
8db9d77b
ZW		 2616 }
2617 if (i == 4)
5eddb70b 2618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2619
2620 DRM_DEBUG_KMS("FDI train done.\n");
2621}
2622
357555c0
JB		 2623/* Manual link training for Ivy Bridge A0 parts */
2624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2625{
2626 struct drm_device *dev = crtc->dev;
2627 struct drm_i915_private *dev_priv = dev->dev_private;
2628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2629 int pipe = intel_crtc->pipe;
2630 u32 reg, temp, i;
2631
2632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2633 for train result */
2634 reg = FDI_RX_IMR(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_RX_SYMBOL_LOCK;
2637 temp &= ~FDI_RX_BIT_LOCK;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
01a415fd
DV		 2643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2644 I915_READ(FDI_RX_IIR(pipe)));
2645
357555c0
JB		 2646 /* enable CPU FDI TX and PCH FDI RX */
2647 reg = FDI_TX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~(7 << 19);
2650 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2652 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2653 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2654 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2655 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2656 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2657
d74cf324
DV		 2658 I915_WRITE(FDI_RX_MISC(pipe),
2659 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2660
357555c0
JB		 2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_AUTO;
2664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2666 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2667 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2668
2669 POSTING_READ(reg);
2670 udelay(150);
2671
8f5718a6 2672 cpt_phase_pointer_enable(dev, pipe);
291427f5 2673
0206e353 2674 for (i = 0; i < 4; i++) {
357555c0
JB		 2675 reg = FDI_TX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 temp |= snb_b_fdi_train_param[i];
2679 I915_WRITE(reg, temp);
2680
2681 POSTING_READ(reg);
2682 udelay(500);
2683
2684 reg = FDI_RX_IIR(pipe);
2685 temp = I915_READ(reg);
2686 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2687
2688 if (temp & FDI_RX_BIT_LOCK ||
2689 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2690 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2691 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2692 break;
2693 }
2694 }
2695 if (i == 4)
2696 DRM_ERROR("FDI train 1 fail!\n");
2697
2698 /* Train 2 */
2699 reg = FDI_TX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2702 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2703 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2704 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2705 I915_WRITE(reg, temp);
2706
2707 reg = FDI_RX_CTL(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2710 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2711 I915_WRITE(reg, temp);
2712
2713 POSTING_READ(reg);
2714 udelay(150);
2715
0206e353 2716 for (i = 0; i < 4; i++) {
357555c0
JB		 2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= snb_b_fdi_train_param[i];
2721 I915_WRITE(reg, temp);
2722
2723 POSTING_READ(reg);
2724 udelay(500);
2725
2726 reg = FDI_RX_IIR(pipe);
2727 temp = I915_READ(reg);
2728 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2729
2730 if (temp & FDI_RX_SYMBOL_LOCK) {
2731 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2732 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2733 break;
2734 }
2735 }
2736 if (i == 4)
2737 DRM_ERROR("FDI train 2 fail!\n");
2738
2739 DRM_DEBUG_KMS("FDI train done.\n");
2740}
2741
88cefb6c 2742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2743{
88cefb6c 2744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2746 int pipe = intel_crtc->pipe;
5eddb70b 2747 u32 reg, temp;
79e53945 2748
c64e311e 2749
c98e9dcf 2750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2751 reg = FDI_RX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2754 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2755 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2757
2758 POSTING_READ(reg);
c98e9dcf
JB		 2759 udelay(200);
2760
2761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2762 temp = I915_READ(reg);
2763 I915_WRITE(reg, temp | FDI_PCDCLK);
2764
2765 POSTING_READ(reg);
c98e9dcf
JB		 2766 udelay(200);
2767
20749730
PZ		 2768 /* Enable CPU FDI TX PLL, always on for Ironlake */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2773
20749730
PZ		 2774 POSTING_READ(reg);
2775 udelay(100);
6be4a607 2776 }
0e23b99d
JB		 2777}
2778
88cefb6c
DV		 2779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2780{
2781 struct drm_device *dev = intel_crtc->base.dev;
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 int pipe = intel_crtc->pipe;
2784 u32 reg, temp;
2785
2786 /* Switch from PCDclk to Rawclk */
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2790
2791 /* Disable CPU FDI TX PLL */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2795
2796 POSTING_READ(reg);
2797 udelay(100);
2798
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2802
2803 /* Wait for the clocks to turn off. */
2804 POSTING_READ(reg);
2805 udelay(100);
2806}
2807
291427f5
JB		 2808static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2809{
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 u32 flags = I915_READ(SOUTH_CHICKEN1);
2812
2813 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2814 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2815 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2816 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2817 POSTING_READ(SOUTH_CHICKEN1);
2818}
0fc932b8
JB		 2819static void ironlake_fdi_disable(struct drm_crtc *crtc)
2820{
2821 struct drm_device *dev = crtc->dev;
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2824 int pipe = intel_crtc->pipe;
2825 u32 reg, temp;
2826
2827 /* disable CPU FDI tx and PCH FDI rx */
2828 reg = FDI_TX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2831 POSTING_READ(reg);
2832
2833 reg = FDI_RX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 temp &= ~(0x7 << 16);
2836 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2837 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2838
2839 POSTING_READ(reg);
2840 udelay(100);
2841
2842 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2843 if (HAS_PCH_IBX(dev)) {
2844 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2845 } else if (HAS_PCH_CPT(dev)) {
2846 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2847 }
0fc932b8
JB		 2848
2849 /* still set train pattern 1 */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~FDI_LINK_TRAIN_NONE;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1;
2854 I915_WRITE(reg, temp);
2855
2856 reg = FDI_RX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 if (HAS_PCH_CPT(dev)) {
2859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2861 } else {
2862 temp &= ~FDI_LINK_TRAIN_NONE;
2863 temp |= FDI_LINK_TRAIN_PATTERN_1;
2864 }
2865 /* BPC in FDI rx is consistent with that in PIPECONF */
2866 temp &= ~(0x07 << 16);
2867 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2868 I915_WRITE(reg, temp);
2869
2870 POSTING_READ(reg);
2871 udelay(100);
2872}
2873
5bb61643
CW		 2874static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 unsigned long flags;
2879 bool pending;
2880
2881 if (atomic_read(&dev_priv->mm.wedged))
2882 return false;
2883
2884 spin_lock_irqsave(&dev->event_lock, flags);
2885 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2886 spin_unlock_irqrestore(&dev->event_lock, flags);
2887
2888 return pending;
2889}
2890
e6c3a2a6
CW		 2891static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2892{
0f91128d 2893 struct drm_device *dev = crtc->dev;
5bb61643 2894 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2895
2896 if (crtc->fb == NULL)
2897 return;
2898
5bb61643
CW		 2899 wait_event(dev_priv->pending_flip_queue,
2900 !intel_crtc_has_pending_flip(crtc));
2901
0f91128d
CW		 2902 mutex_lock(&dev->struct_mutex);
2903 intel_finish_fb(crtc->fb);
2904 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2905}
2906
fc316cbe 2907static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2908{
2909 struct drm_device *dev = crtc->dev;
228d3e36 2910 struct intel_encoder *intel_encoder;
040484af
JB		 2911
2912 /*
2913 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2914 * must be driven by its own crtc; no sharing is possible.
2915 */
228d3e36 2916 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2917 switch (intel_encoder->type) {
040484af 2918 case INTEL_OUTPUT_EDP:
228d3e36 2919 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2920 return false;
2921 continue;
2922 }
2923 }
2924
2925 return true;
2926}
2927
fc316cbe
PZ		 2928static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2929{
2930 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2931}
2932
e615efe4
ED		 2933/* Program iCLKIP clock to the desired frequency */
2934static void lpt_program_iclkip(struct drm_crtc *crtc)
2935{
2936 struct drm_device *dev = crtc->dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2939 u32 temp;
2940
09153000
DV		 2941 mutex_lock(&dev_priv->dpio_lock);
2942
e615efe4
ED		 2943 /* It is necessary to ungate the pixclk gate prior to programming
2944 * the divisors, and gate it back when it is done.
2945 */
2946 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2947
2948 /* Disable SSCCTL */
2949 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2950 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2951 SBI_SSCCTL_DISABLE);
2952
2953 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2954 if (crtc->mode.clock == 20000) {
2955 auxdiv = 1;
2956 divsel = 0x41;
2957 phaseinc = 0x20;
2958 } else {
2959 /* The iCLK virtual clock root frequency is in MHz,
2960 * but the crtc->mode.clock in in KHz. To get the divisors,
2961 * it is necessary to divide one by another, so we
2962 * convert the virtual clock precision to KHz here for higher
2963 * precision.
2964 */
2965 u32 iclk_virtual_root_freq = 172800 * 1000;
2966 u32 iclk_pi_range = 64;
2967 u32 desired_divisor, msb_divisor_value, pi_value;
2968
2969 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2970 msb_divisor_value = desired_divisor / iclk_pi_range;
2971 pi_value = desired_divisor % iclk_pi_range;
2972
2973 auxdiv = 0;
2974 divsel = msb_divisor_value - 2;
2975 phaseinc = pi_value;
2976 }
2977
2978 /* This should not happen with any sane values */
2979 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2980 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2981 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2982 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2983
2984 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2985 crtc->mode.clock,
2986 auxdiv,
2987 divsel,
2988 phasedir,
2989 phaseinc);
2990
2991 /* Program SSCDIVINTPHASE6 */
2992 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2993 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2994 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2995 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2996 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2997 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2998 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2999
3000 intel_sbi_write(dev_priv,
3001 SBI_SSCDIVINTPHASE6,
3002 temp);
3003
3004 /* Program SSCAUXDIV */
3005 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3006 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3007 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3008 intel_sbi_write(dev_priv,
3009 SBI_SSCAUXDIV6,
3010 temp);
3011
3012
3013 /* Enable modulator and associated divider */
3014 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3015 temp &= ~SBI_SSCCTL_DISABLE;
3016 intel_sbi_write(dev_priv,
3017 SBI_SSCCTL6,
3018 temp);
3019
3020 /* Wait for initialization time */
3021 udelay(24);
3022
3023 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3024
3025 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3026}
3027
f67a559d
JB		 3028/*
3029 * Enable PCH resources required for PCH ports:
3030 * - PCH PLLs
3031 * - FDI training & RX/TX
3032 * - update transcoder timings
3033 * - DP transcoding bits
3034 * - transcoder
3035 */
3036static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3037{
3038 struct drm_device *dev = crtc->dev;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041 int pipe = intel_crtc->pipe;
ee7b9f93 3042 u32 reg, temp;
2c07245f 3043
e7e164db
CW		 3044 assert_transcoder_disabled(dev_priv, pipe);
3045
cd986abb
DV		 3046 /* Write the TU size bits before fdi link training, so that error
3047 * detection works. */
3048 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3049 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3050
c98e9dcf 3051 /* For PCH output, training FDI link */
674cf967 3052 dev_priv->display.fdi_link_train(crtc);
2c07245f 3053
572deb37
DV		 3054 /* XXX: pch pll's can be enabled any time before we enable the PCH
3055 * transcoder, and we actually should do this to not upset any PCH
3056 * transcoder that already use the clock when we share it.
3057 *
3058 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3059 * unconditionally resets the pll - we need that to have the right LVDS
3060 * enable sequence. */
b6b4e185 3061 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3062
303b81e0 3063 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3064 u32 sel;
4b645f14 3065
c98e9dcf 3066 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3067 switch (pipe) {
3068 default:
3069 case 0:
3070 temp |= TRANSA_DPLL_ENABLE;
3071 sel = TRANSA_DPLLB_SEL;
3072 break;
3073 case 1:
3074 temp |= TRANSB_DPLL_ENABLE;
3075 sel = TRANSB_DPLLB_SEL;
3076 break;
3077 case 2:
3078 temp |= TRANSC_DPLL_ENABLE;
3079 sel = TRANSC_DPLLB_SEL;
3080 break;
d64311ab 3081 }
ee7b9f93
JB		 3082 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3083 temp |= sel;
3084 else
3085 temp &= ~sel;
c98e9dcf 3086 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3087 }
5eddb70b 3088
d9b6cb56
JB		 3089 /* set transcoder timing, panel must allow it */
3090 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3091 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3092 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3093 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3094
5eddb70b
CW		 3095 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3096 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3097 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3098 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3099
303b81e0 3100 intel_fdi_normal_train(crtc);
5e84e1a4 3101
c98e9dcf
JB		 3102 /* For PCH DP, enable TRANS_DP_CTL */
3103 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3104 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3105 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3106 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3107 reg = TRANS_DP_CTL(pipe);
3108 temp = I915_READ(reg);
3109 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3110 TRANS_DP_SYNC_MASK |
3111 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3112 temp |= (TRANS_DP_OUTPUT_ENABLE |
3113 TRANS_DP_ENH_FRAMING);
9325c9f0 3114 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3115
3116 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3117 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3118 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3119 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3120
3121 switch (intel_trans_dp_port_sel(crtc)) {
3122 case PCH_DP_B:
5eddb70b 3123 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3124 break;
3125 case PCH_DP_C:
5eddb70b 3126 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3127 break;
3128 case PCH_DP_D:
5eddb70b 3129 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3130 break;
3131 default:
e95d41e1 3132 BUG();
32f9d658 3133 }
2c07245f 3134
5eddb70b 3135 I915_WRITE(reg, temp);
6be4a607 3136 }
b52eb4dc 3137
b8a4f404 3138 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3139}
3140
1507e5bd
PZ		 3141static void lpt_pch_enable(struct drm_crtc *crtc)
3142{
3143 struct drm_device *dev = crtc->dev;
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3146 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3147
daed2dbb 3148 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3149
8c52b5e8 3150 lpt_program_iclkip(crtc);
1507e5bd 3151
0540e488 3152 /* Set transcoder timing. */
daed2dbb
PZ		 3153 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3154 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3155 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3156
daed2dbb
PZ		 3157 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3158 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3159 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3160 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3161
937bb610 3162 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3163}
3164
ee7b9f93
JB		 3165static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3166{
3167 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3168
3169 if (pll == NULL)
3170 return;
3171
3172 if (pll->refcount == 0) {
3173 WARN(1, "bad PCH PLL refcount\n");
3174 return;
3175 }
3176
3177 --pll->refcount;
3178 intel_crtc->pch_pll = NULL;
3179}
3180
3181static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3182{
3183 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3184 struct intel_pch_pll *pll;
3185 int i;
3186
3187 pll = intel_crtc->pch_pll;
3188 if (pll) {
3189 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3190 intel_crtc->base.base.id, pll->pll_reg);
3191 goto prepare;
3192 }
3193
98b6bd99
DV		 3194 if (HAS_PCH_IBX(dev_priv->dev)) {
3195 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3196 i = intel_crtc->pipe;
3197 pll = &dev_priv->pch_plls[i];
3198
3199 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3200 intel_crtc->base.base.id, pll->pll_reg);
3201
3202 goto found;
3203 }
3204
ee7b9f93
JB		 3205 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3206 pll = &dev_priv->pch_plls[i];
3207
3208 /* Only want to check enabled timings first */
3209 if (pll->refcount == 0)
3210 continue;
3211
3212 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3213 fp == I915_READ(pll->fp0_reg)) {
3214 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3215 intel_crtc->base.base.id,
3216 pll->pll_reg, pll->refcount, pll->active);
3217
3218 goto found;
3219 }
3220 }
3221
3222 /* Ok no matching timings, maybe there's a free one? */
3223 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3224 pll = &dev_priv->pch_plls[i];
3225 if (pll->refcount == 0) {
3226 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3227 intel_crtc->base.base.id, pll->pll_reg);
3228 goto found;
3229 }
3230 }
3231
3232 return NULL;
3233
3234found:
3235 intel_crtc->pch_pll = pll;
3236 pll->refcount++;
3237 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3238prepare: /* separate function? */
3239 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3240
e04c7350
CW		 3241 /* Wait for the clocks to stabilize before rewriting the regs */
3242 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3243 POSTING_READ(pll->pll_reg);
3244 udelay(150);
e04c7350
CW		 3245
3246 I915_WRITE(pll->fp0_reg, fp);
3247 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3248 pll->on = false;
3249 return pll;
3250}
3251
d4270e57
JB		 3252void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3253{
3254 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3255 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3256 u32 temp;
3257
3258 temp = I915_READ(dslreg);
3259 udelay(500);
3260 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3261 if (wait_for(I915_READ(dslreg) != temp, 5))
3262 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3263 }
3264}
3265
f67a559d
JB		 3266static void ironlake_crtc_enable(struct drm_crtc *crtc)
3267{
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3271 struct intel_encoder *encoder;
f67a559d
JB		 3272 int pipe = intel_crtc->pipe;
3273 int plane = intel_crtc->plane;
3274 u32 temp;
3275 bool is_pch_port;
3276
08a48469
DV		 3277 WARN_ON(!crtc->enabled);
3278
f67a559d
JB		 3279 if (intel_crtc->active)
3280 return;
3281
3282 intel_crtc->active = true;
3283 intel_update_watermarks(dev);
3284
3285 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3286 temp = I915_READ(PCH_LVDS);
3287 if ((temp & LVDS_PORT_EN) == 0)
3288 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3289 }
3290
fc316cbe 3291 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3292
46b6f814 3293 if (is_pch_port) {
fff367c7
DV		 3294 /* Note: FDI PLL enabling _must_ be done before we enable the
3295 * cpu pipes, hence this is separate from all the other fdi/pch
3296 * enabling. */
88cefb6c 3297 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3298 } else {
3299 assert_fdi_tx_disabled(dev_priv, pipe);
3300 assert_fdi_rx_disabled(dev_priv, pipe);
3301 }
f67a559d 3302
bf49ec8c
DV		 3303 for_each_encoder_on_crtc(dev, crtc, encoder)
3304 if (encoder->pre_enable)
3305 encoder->pre_enable(encoder);
f67a559d
JB		 3306
3307 /* Enable panel fitting for LVDS */
3308 if (dev_priv->pch_pf_size &&
547dc041
JN		 3309 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3311 /* Force use of hard-coded filter coefficients
3312 * as some pre-programmed values are broken,
3313 * e.g. x201.
3314 */
13888d78
PZ		 3315 if (IS_IVYBRIDGE(dev))
3316 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3317 PF_PIPE_SEL_IVB(pipe));
3318 else
3319 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3320 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3321 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3322 }
3323
9c54c0dd
JB		 3324 /*
3325 * On ILK+ LUT must be loaded before the pipe is running but with
3326 * clocks enabled
3327 */
3328 intel_crtc_load_lut(crtc);
3329
f67a559d
JB		 3330 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3331 intel_enable_plane(dev_priv, plane, pipe);
3332
3333 if (is_pch_port)
3334 ironlake_pch_enable(crtc);
c98e9dcf 3335
d1ebd816 3336 mutex_lock(&dev->struct_mutex);
bed4a673 3337 intel_update_fbc(dev);
d1ebd816
BW		 3338 mutex_unlock(&dev->struct_mutex);
3339
6b383a7f 3340 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3341
fa5c73b1
DV		 3342 for_each_encoder_on_crtc(dev, crtc, encoder)
3343 encoder->enable(encoder);
61b77ddd
DV		 3344
3345 if (HAS_PCH_CPT(dev))
3346 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3347
3348 /*
3349 * There seems to be a race in PCH platform hw (at least on some
3350 * outputs) where an enabled pipe still completes any pageflip right
3351 * away (as if the pipe is off) instead of waiting for vblank. As soon
3352 * as the first vblank happend, everything works as expected. Hence just
3353 * wait for one vblank before returning to avoid strange things
3354 * happening.
3355 */
3356 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3357}
3358
4f771f10
PZ		 3359static void haswell_crtc_enable(struct drm_crtc *crtc)
3360{
3361 struct drm_device *dev = crtc->dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364 struct intel_encoder *encoder;
3365 int pipe = intel_crtc->pipe;
3366 int plane = intel_crtc->plane;
4f771f10
PZ		 3367 bool is_pch_port;
3368
3369 WARN_ON(!crtc->enabled);
3370
3371 if (intel_crtc->active)
3372 return;
3373
3374 intel_crtc->active = true;
3375 intel_update_watermarks(dev);
3376
fc316cbe 3377 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3378
83616634 3379 if (is_pch_port)
04945641 3380 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3381
3382 for_each_encoder_on_crtc(dev, crtc, encoder)
3383 if (encoder->pre_enable)
3384 encoder->pre_enable(encoder);
3385
1f544388 3386 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3387
1f544388 3388 /* Enable panel fitting for eDP */
547dc041
JN		 3389 if (dev_priv->pch_pf_size &&
3390 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3391 /* Force use of hard-coded filter coefficients
3392 * as some pre-programmed values are broken,
3393 * e.g. x201.
3394 */
54075a7d
PZ		 3395 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3396 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3397 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3398 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3399 }
3400
3401 /*
3402 * On ILK+ LUT must be loaded before the pipe is running but with
3403 * clocks enabled
3404 */
3405 intel_crtc_load_lut(crtc);
3406
1f544388
PZ		 3407 intel_ddi_set_pipe_settings(crtc);
3408 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3409
3410 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3411 intel_enable_plane(dev_priv, plane, pipe);
3412
3413 if (is_pch_port)
1507e5bd 3414 lpt_pch_enable(crtc);
4f771f10
PZ		 3415
3416 mutex_lock(&dev->struct_mutex);
3417 intel_update_fbc(dev);
3418 mutex_unlock(&dev->struct_mutex);
3419
3420 intel_crtc_update_cursor(crtc, true);
3421
3422 for_each_encoder_on_crtc(dev, crtc, encoder)
3423 encoder->enable(encoder);
3424
4f771f10
PZ		 3425 /*
3426 * There seems to be a race in PCH platform hw (at least on some
3427 * outputs) where an enabled pipe still completes any pageflip right
3428 * away (as if the pipe is off) instead of waiting for vblank. As soon
3429 * as the first vblank happend, everything works as expected. Hence just
3430 * wait for one vblank before returning to avoid strange things
3431 * happening.
3432 */
3433 intel_wait_for_vblank(dev, intel_crtc->pipe);
3434}
3435
6be4a607
JB		 3436static void ironlake_crtc_disable(struct drm_crtc *crtc)
3437{
3438 struct drm_device *dev = crtc->dev;
3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3441 struct intel_encoder *encoder;
6be4a607
JB		 3442 int pipe = intel_crtc->pipe;
3443 int plane = intel_crtc->plane;
5eddb70b 3444 u32 reg, temp;
b52eb4dc 3445
ef9c3aee 3446
f7abfe8b
CW		 3447 if (!intel_crtc->active)
3448 return;
3449
ea9d758d
DV		 3450 for_each_encoder_on_crtc(dev, crtc, encoder)
3451 encoder->disable(encoder);
3452
e6c3a2a6 3453 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3454 drm_vblank_off(dev, pipe);
6b383a7f 3455 intel_crtc_update_cursor(crtc, false);
5eddb70b 3456
b24e7179 3457 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3458
973d04f9
CW		 3459 if (dev_priv->cfb_plane == plane)
3460 intel_disable_fbc(dev);
2c07245f 3461
b24e7179 3462 intel_disable_pipe(dev_priv, pipe);
32f9d658 3463
6be4a607 3464 /* Disable PF */
9db4a9c7
JB		 3465 I915_WRITE(PF_CTL(pipe), 0);
3466 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3467
bf49ec8c
DV		 3468 for_each_encoder_on_crtc(dev, crtc, encoder)
3469 if (encoder->post_disable)
3470 encoder->post_disable(encoder);
2c07245f 3471
0fc932b8 3472 ironlake_fdi_disable(crtc);
249c0e64 3473
b8a4f404 3474 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3475
6be4a607
JB		 3476 if (HAS_PCH_CPT(dev)) {
3477 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3478 reg = TRANS_DP_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3481 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3482 I915_WRITE(reg, temp);
6be4a607
JB		 3483
3484 /* disable DPLL_SEL */
3485 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3486 switch (pipe) {
3487 case 0:
d64311ab 3488 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3489 break;
3490 case 1:
6be4a607 3491 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3492 break;
3493 case 2:
4b645f14 3494 /* C shares PLL A or B */
d64311ab 3495 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3496 break;
3497 default:
3498 BUG(); /* wtf */
3499 }
6be4a607 3500 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3501 }
e3421a18 3502
6be4a607 3503 /* disable PCH DPLL */
ee7b9f93 3504 intel_disable_pch_pll(intel_crtc);
8db9d77b 3505
88cefb6c 3506 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3507
f7abfe8b 3508 intel_crtc->active = false;
6b383a7f 3509 intel_update_watermarks(dev);
d1ebd816
BW		 3510
3511 mutex_lock(&dev->struct_mutex);
6b383a7f 3512 intel_update_fbc(dev);
d1ebd816 3513 mutex_unlock(&dev->struct_mutex);
6be4a607 3514}
1b3c7a47 3515
4f771f10 3516static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3517{
4f771f10
PZ		 3518 struct drm_device *dev = crtc->dev;
3519 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3521 struct intel_encoder *encoder;
3522 int pipe = intel_crtc->pipe;
3523 int plane = intel_crtc->plane;
ad80a810 3524 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3525 bool is_pch_port;
ee7b9f93 3526
4f771f10
PZ		 3527 if (!intel_crtc->active)
3528 return;
3529
83616634
PZ		 3530 is_pch_port = haswell_crtc_driving_pch(crtc);
3531
4f771f10
PZ		 3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 encoder->disable(encoder);
3534
3535 intel_crtc_wait_for_pending_flips(crtc);
3536 drm_vblank_off(dev, pipe);
3537 intel_crtc_update_cursor(crtc, false);
3538
3539 intel_disable_plane(dev_priv, plane, pipe);
3540
3541 if (dev_priv->cfb_plane == plane)
3542 intel_disable_fbc(dev);
3543
3544 intel_disable_pipe(dev_priv, pipe);
3545
ad80a810 3546 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3547
3548 /* Disable PF */
3549 I915_WRITE(PF_CTL(pipe), 0);
3550 I915_WRITE(PF_WIN_SZ(pipe), 0);
3551
1f544388 3552 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3553
3554 for_each_encoder_on_crtc(dev, crtc, encoder)
3555 if (encoder->post_disable)
3556 encoder->post_disable(encoder);
3557
83616634 3558 if (is_pch_port) {
ab4d966c 3559 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3560 intel_ddi_fdi_disable(crtc);
83616634 3561 }
4f771f10
PZ		 3562
3563 intel_crtc->active = false;
3564 intel_update_watermarks(dev);
3565
3566 mutex_lock(&dev->struct_mutex);
3567 intel_update_fbc(dev);
3568 mutex_unlock(&dev->struct_mutex);
3569}
3570
ee7b9f93
JB		 3571static void ironlake_crtc_off(struct drm_crtc *crtc)
3572{
3573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574 intel_put_pch_pll(intel_crtc);
3575}
3576
6441ab5f
PZ		 3577static void haswell_crtc_off(struct drm_crtc *crtc)
3578{
a5c961d1
PZ		 3579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580
3581 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3582 * start using it. */
1a240d4d 3583 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3584
6441ab5f
PZ		 3585 intel_ddi_put_crtc_pll(crtc);
3586}
3587
02e792fb
DV		 3588static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3589{
02e792fb 3590 if (!enable && intel_crtc->overlay) {
23f09ce3 3591 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3592 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3593
23f09ce3 3594 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3595 dev_priv->mm.interruptible = false;
3596 (void) intel_overlay_switch_off(intel_crtc->overlay);
3597 dev_priv->mm.interruptible = true;
23f09ce3 3598 mutex_unlock(&dev->struct_mutex);
02e792fb 3599 }
02e792fb 3600
5dcdbcb0
CW		 3601 /* Let userspace switch the overlay on again. In most cases userspace
3602 * has to recompute where to put it anyway.
3603 */
02e792fb
DV		 3604}
3605
0b8765c6 3606static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3607{
3608 struct drm_device *dev = crtc->dev;
79e53945
JB		 3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3611 struct intel_encoder *encoder;
79e53945 3612 int pipe = intel_crtc->pipe;
80824003 3613 int plane = intel_crtc->plane;
79e53945 3614
08a48469
DV		 3615 WARN_ON(!crtc->enabled);
3616
f7abfe8b
CW		 3617 if (intel_crtc->active)
3618 return;
3619
3620 intel_crtc->active = true;
6b383a7f
CW		 3621 intel_update_watermarks(dev);
3622
63d7bbe9 3623 intel_enable_pll(dev_priv, pipe);
040484af 3624 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3625 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3626
0b8765c6 3627 intel_crtc_load_lut(crtc);
bed4a673 3628 intel_update_fbc(dev);
79e53945 3629
0b8765c6
JB		 3630 /* Give the overlay scaler a chance to enable if it's on this pipe */
3631 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3632 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3633
fa5c73b1
DV		 3634 for_each_encoder_on_crtc(dev, crtc, encoder)
3635 encoder->enable(encoder);
0b8765c6 3636}
79e53945 3637
0b8765c6
JB		 3638static void i9xx_crtc_disable(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3643 struct intel_encoder *encoder;
0b8765c6
JB		 3644 int pipe = intel_crtc->pipe;
3645 int plane = intel_crtc->plane;
b690e96c 3646
ef9c3aee 3647
f7abfe8b
CW		 3648 if (!intel_crtc->active)
3649 return;
3650
ea9d758d
DV		 3651 for_each_encoder_on_crtc(dev, crtc, encoder)
3652 encoder->disable(encoder);
3653
0b8765c6 3654 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3655 intel_crtc_wait_for_pending_flips(crtc);
3656 drm_vblank_off(dev, pipe);
0b8765c6 3657 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3658 intel_crtc_update_cursor(crtc, false);
0b8765c6 3659
973d04f9
CW		 3660 if (dev_priv->cfb_plane == plane)
3661 intel_disable_fbc(dev);
79e53945 3662
b24e7179 3663 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3664 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3665 intel_disable_pll(dev_priv, pipe);
0b8765c6 3666
f7abfe8b 3667 intel_crtc->active = false;
6b383a7f
CW		 3668 intel_update_fbc(dev);
3669 intel_update_watermarks(dev);
0b8765c6
JB		 3670}
3671
ee7b9f93
JB		 3672static void i9xx_crtc_off(struct drm_crtc *crtc)
3673{
3674}
3675
976f8a20
DV		 3676static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3677 bool enabled)
2c07245f
ZW		 3678{
3679 struct drm_device *dev = crtc->dev;
3680 struct drm_i915_master_private *master_priv;
3681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3682 int pipe = intel_crtc->pipe;
79e53945
JB		 3683
3684 if (!dev->primary->master)
3685 return;
3686
3687 master_priv = dev->primary->master->driver_priv;
3688 if (!master_priv->sarea_priv)
3689 return;
3690
79e53945
JB		 3691 switch (pipe) {
3692 case 0:
3693 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3694 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3695 break;
3696 case 1:
3697 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3698 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3699 break;
3700 default:
9db4a9c7 3701 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3702 break;
3703 }
79e53945
JB		 3704}
3705
976f8a20
DV		 3706/**
3707 * Sets the power management mode of the pipe and plane.
3708 */
3709void intel_crtc_update_dpms(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_encoder *intel_encoder;
3714 bool enable = false;
3715
3716 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3717 enable |= intel_encoder->connectors_active;
3718
3719 if (enable)
3720 dev_priv->display.crtc_enable(crtc);
3721 else
3722 dev_priv->display.crtc_disable(crtc);
3723
3724 intel_crtc_update_sarea(crtc, enable);
3725}
3726
3727static void intel_crtc_noop(struct drm_crtc *crtc)
3728{
3729}
3730
cdd59983
CW		 3731static void intel_crtc_disable(struct drm_crtc *crtc)
3732{
cdd59983 3733 struct drm_device *dev = crtc->dev;
976f8a20 3734 struct drm_connector *connector;
ee7b9f93 3735 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3736
976f8a20
DV		 3737 /* crtc should still be enabled when we disable it. */
3738 WARN_ON(!crtc->enabled);
3739
3740 dev_priv->display.crtc_disable(crtc);
3741 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3742 dev_priv->display.off(crtc);
3743
931872fc
CW		 3744 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3745 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3746
3747 if (crtc->fb) {
3748 mutex_lock(&dev->struct_mutex);
1690e1eb 3749 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3750 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3751 crtc->fb = NULL;
3752 }
3753
3754 /* Update computed state. */
3755 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3756 if (!connector->encoder || !connector->encoder->crtc)
3757 continue;
3758
3759 if (connector->encoder->crtc != crtc)
3760 continue;
3761
3762 connector->dpms = DRM_MODE_DPMS_OFF;
3763 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3764 }
3765}
3766
a261b246 3767void intel_modeset_disable(struct drm_device *dev)
79e53945 3768{
a261b246
DV		 3769 struct drm_crtc *crtc;
3770
3771 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3772 if (crtc->enabled)
3773 intel_crtc_disable(crtc);
3774 }
79e53945
JB		 3775}
3776
1f703855 3777void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3778{
7e7d76c3
JB		 3779}
3780
ea5b213a 3781void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3782{
4ef69c7a 3783 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3784
ea5b213a
CW		 3785 drm_encoder_cleanup(encoder);
3786 kfree(intel_encoder);
7e7d76c3
JB		 3787}
3788
5ab432ef
DV		 3789/* Simple dpms helper for encodres with just one connector, no cloning and only
3790 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3791 * state of the entire output pipe. */
3792void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3793{
5ab432ef
DV		 3794 if (mode == DRM_MODE_DPMS_ON) {
3795 encoder->connectors_active = true;
3796
b2cabb0e 3797 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3798 } else {
3799 encoder->connectors_active = false;
3800
b2cabb0e 3801 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3802 }
79e53945
JB		 3803}
3804
0a91ca29
DV		 3805/* Cross check the actual hw state with our own modeset state tracking (and it's
3806 * internal consistency). */
b980514c 3807static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3808{
0a91ca29
DV		 3809 if (connector->get_hw_state(connector)) {
3810 struct intel_encoder *encoder = connector->encoder;
3811 struct drm_crtc *crtc;
3812 bool encoder_enabled;
3813 enum pipe pipe;
3814
3815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3816 connector->base.base.id,
3817 drm_get_connector_name(&connector->base));
3818
3819 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3820 "wrong connector dpms state\n");
3821 WARN(connector->base.encoder != &encoder->base,
3822 "active connector not linked to encoder\n");
3823 WARN(!encoder->connectors_active,
3824 "encoder->connectors_active not set\n");
3825
3826 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3827 WARN(!encoder_enabled, "encoder not enabled\n");
3828 if (WARN_ON(!encoder->base.crtc))
3829 return;
3830
3831 crtc = encoder->base.crtc;
3832
3833 WARN(!crtc->enabled, "crtc not enabled\n");
3834 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3835 WARN(pipe != to_intel_crtc(crtc)->pipe,
3836 "encoder active on the wrong pipe\n");
3837 }
79e53945
JB		 3838}
3839
5ab432ef
DV		 3840/* Even simpler default implementation, if there's really no special case to
3841 * consider. */
3842void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3843{
5ab432ef 3844 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3845
5ab432ef
DV		 3846 /* All the simple cases only support two dpms states. */
3847 if (mode != DRM_MODE_DPMS_ON)
3848 mode = DRM_MODE_DPMS_OFF;
d4270e57 3849
5ab432ef
DV		 3850 if (mode == connector->dpms)
3851 return;
3852
3853 connector->dpms = mode;
3854
3855 /* Only need to change hw state when actually enabled */
3856 if (encoder->base.crtc)
3857 intel_encoder_dpms(encoder, mode);
3858 else
8af6cf88 3859 WARN_ON(encoder->connectors_active != false);
0a91ca29 3860
b980514c 3861 intel_modeset_check_state(connector->dev);
79e53945
JB		 3862}
3863
f0947c37
DV		 3864/* Simple connector->get_hw_state implementation for encoders that support only
3865 * one connector and no cloning and hence the encoder state determines the state
3866 * of the connector. */
3867bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3868{
24929352 3869 enum pipe pipe = 0;
f0947c37 3870 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3871
f0947c37 3872 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3873}
3874
79e53945 3875static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3876 const struct drm_display_mode *mode,
79e53945
JB		 3877 struct drm_display_mode *adjusted_mode)
3878{
2c07245f 3879 struct drm_device *dev = crtc->dev;
89749350 3880
bad720ff 3881 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3882 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3883 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3884 return false;
2c07245f 3885 }
89749350 3886
f9bef081
DV		 3887 /* All interlaced capable intel hw wants timings in frames. Note though
3888 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3889 * timings, so we need to be careful not to clobber these.*/
3890 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3891 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3892
44f46b42
CW		 3893 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3894 * with a hsync front porch of 0.
3895 */
3896 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3897 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3898 return false;
3899
79e53945
JB		 3900 return true;
3901}
3902
25eb05fc
JB		 3903static int valleyview_get_display_clock_speed(struct drm_device *dev)
3904{
3905 return 400000; /* FIXME */
3906}
3907
e70236a8
JB		 3908static int i945_get_display_clock_speed(struct drm_device *dev)
3909{
3910 return 400000;
3911}
79e53945 3912
e70236a8 3913static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3914{
e70236a8
JB		 3915 return 333000;
3916}
79e53945 3917
e70236a8
JB		 3918static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3919{
3920 return 200000;
3921}
79e53945 3922
e70236a8
JB		 3923static int i915gm_get_display_clock_speed(struct drm_device *dev)
3924{
3925 u16 gcfgc = 0;
79e53945 3926
e70236a8
JB		 3927 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3928
3929 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3930 return 133000;
3931 else {
3932 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3933 case GC_DISPLAY_CLOCK_333_MHZ:
3934 return 333000;
3935 default:
3936 case GC_DISPLAY_CLOCK_190_200_MHZ:
3937 return 190000;
79e53945 3938 }
e70236a8
JB		 3939 }
3940}
3941
3942static int i865_get_display_clock_speed(struct drm_device *dev)
3943{
3944 return 266000;
3945}
3946
3947static int i855_get_display_clock_speed(struct drm_device *dev)
3948{
3949 u16 hpllcc = 0;
3950 /* Assume that the hardware is in the high speed state. This
3951 * should be the default.
3952 */
3953 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3954 case GC_CLOCK_133_200:
3955 case GC_CLOCK_100_200:
3956 return 200000;
3957 case GC_CLOCK_166_250:
3958 return 250000;
3959 case GC_CLOCK_100_133:
79e53945 3960 return 133000;
e70236a8 3961 }
79e53945 3962
e70236a8
JB		 3963 /* Shouldn't happen */
3964 return 0;
3965}
79e53945 3966
e70236a8
JB		 3967static int i830_get_display_clock_speed(struct drm_device *dev)
3968{
3969 return 133000;
79e53945
JB		 3970}
3971
2c07245f 3972static void
e69d0bc1 3973intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3974{
3975 while (*num > 0xffffff || *den > 0xffffff) {
3976 *num >>= 1;
3977 *den >>= 1;
3978 }
3979}
3980
e69d0bc1
DV		 3981void
3982intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3983 int pixel_clock, int link_clock,
3984 struct intel_link_m_n *m_n)
2c07245f 3985{
e69d0bc1 3986 m_n->tu = 64;
22ed1113
CW		 3987 m_n->gmch_m = bits_per_pixel * pixel_clock;
3988 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3989 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3990 m_n->link_m = pixel_clock;
3991 m_n->link_n = link_clock;
e69d0bc1 3992 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3993}
3994
a7615030
CW		 3995static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3996{
72bbe58c
KP		 3997 if (i915_panel_use_ssc >= 0)
3998 return i915_panel_use_ssc != 0;
3999 return dev_priv->lvds_use_ssc
435793df 4000 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4001}
4002
5a354204
JB		 4003/**
4004 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4005 * @crtc: CRTC structure
3b5c78a3 4006 * @mode: requested mode
5a354204
JB		 4007 *
4008 * A pipe may be connected to one or more outputs. Based on the depth of the
4009 * attached framebuffer, choose a good color depth to use on the pipe.
4010 *
4011 * If possible, match the pipe depth to the fb depth. In some cases, this
4012 * isn't ideal, because the connected output supports a lesser or restricted
4013 * set of depths. Resolve that here:
4014 * LVDS typically supports only 6bpc, so clamp down in that case
4015 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4016 * Displays may support a restricted set as well, check EDID and clamp as
4017 * appropriate.
3b5c78a3 4018 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4019 *
4020 * RETURNS:
4021 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4022 * true if they don't match).
4023 */
4024static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4025 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4026 unsigned int *pipe_bpp,
4027 struct drm_display_mode *mode)
5a354204
JB		 4028{
4029 struct drm_device *dev = crtc->dev;
4030 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4031 struct drm_connector *connector;
6c2b7c12 4032 struct intel_encoder *intel_encoder;
5a354204
JB		 4033 unsigned int display_bpc = UINT_MAX, bpc;
4034
4035 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4036 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4037
4038 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4039 unsigned int lvds_bpc;
4040
4041 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4042 LVDS_A3_POWER_UP)
4043 lvds_bpc = 8;
4044 else
4045 lvds_bpc = 6;
4046
4047 if (lvds_bpc < display_bpc) {
82820490 4048 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4049 display_bpc = lvds_bpc;
4050 }
4051 continue;
4052 }
4053
5a354204
JB		 4054 /* Not one of the known troublemakers, check the EDID */
4055 list_for_each_entry(connector, &dev->mode_config.connector_list,
4056 head) {
6c2b7c12 4057 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4058 continue;
4059
62ac41a6
JB		 4060 /* Don't use an invalid EDID bpc value */
4061 if (connector->display_info.bpc &&
4062 connector->display_info.bpc < display_bpc) {
82820490 4063 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4064 display_bpc = connector->display_info.bpc;
4065 }
4066 }
4067
4068 /*
4069 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4070 * through, clamp it down. (Note: >12bpc will be caught below.)
4071 */
4072 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4073 if (display_bpc > 8 && display_bpc < 12) {
82820490 4074 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4075 display_bpc = 12;
4076 } else {
82820490 4077 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4078 display_bpc = 8;
4079 }
4080 }
4081 }
4082
3b5c78a3
AJ		 4083 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4084 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4085 display_bpc = 6;
4086 }
4087
5a354204
JB		 4088 /*
4089 * We could just drive the pipe at the highest bpc all the time and
4090 * enable dithering as needed, but that costs bandwidth. So choose
4091 * the minimum value that expresses the full color range of the fb but
4092 * also stays within the max display bpc discovered above.
4093 */
4094
94352cf9 4095 switch (fb->depth) {
5a354204
JB		 4096 case 8:
4097 bpc = 8; /* since we go through a colormap */
4098 break;
4099 case 15:
4100 case 16:
4101 bpc = 6; /* min is 18bpp */
4102 break;
4103 case 24:
578393cd 4104 bpc = 8;
5a354204
JB		 4105 break;
4106 case 30:
578393cd 4107 bpc = 10;
5a354204
JB		 4108 break;
4109 case 48:
578393cd 4110 bpc = 12;
5a354204
JB		 4111 break;
4112 default:
4113 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4114 bpc = min((unsigned int)8, display_bpc);
4115 break;
4116 }
4117
578393cd
KP		 4118 display_bpc = min(display_bpc, bpc);
4119
82820490
AJ		 4120 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4121 bpc, display_bpc);
5a354204 4122
578393cd 4123 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4124
4125 return display_bpc != bpc;
4126}
4127
a0c4da24
JB		 4128static int vlv_get_refclk(struct drm_crtc *crtc)
4129{
4130 struct drm_device *dev = crtc->dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 int refclk = 27000; /* for DP & HDMI */
4133
4134 return 100000; /* only one validated so far */
4135
4136 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4137 refclk = 96000;
4138 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4139 if (intel_panel_use_ssc(dev_priv))
4140 refclk = 100000;
4141 else
4142 refclk = 96000;
4143 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4144 refclk = 100000;
4145 }
4146
4147 return refclk;
4148}
4149
c65d77d8
JB		 4150static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4151{
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 int refclk;
4155
a0c4da24
JB		 4156 if (IS_VALLEYVIEW(dev)) {
4157 refclk = vlv_get_refclk(crtc);
4158 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4159 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4160 refclk = dev_priv->lvds_ssc_freq * 1000;
4161 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4162 refclk / 1000);
4163 } else if (!IS_GEN2(dev)) {
4164 refclk = 96000;
4165 } else {
4166 refclk = 48000;
4167 }
4168
4169 return refclk;
4170}
4171
4172static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4173 intel_clock_t *clock)
4174{
4175 /* SDVO TV has fixed PLL values depend on its clock range,
4176 this mirrors vbios setting. */
4177 if (adjusted_mode->clock >= 100000
4178 && adjusted_mode->clock < 140500) {
4179 clock->p1 = 2;
4180 clock->p2 = 10;
4181 clock->n = 3;
4182 clock->m1 = 16;
4183 clock->m2 = 8;
4184 } else if (adjusted_mode->clock >= 140500
4185 && adjusted_mode->clock <= 200000) {
4186 clock->p1 = 1;
4187 clock->p2 = 10;
4188 clock->n = 6;
4189 clock->m1 = 12;
4190 clock->m2 = 8;
4191 }
4192}
4193
a7516a05
JB		 4194static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4195 intel_clock_t *clock,
4196 intel_clock_t *reduced_clock)
4197{
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201 int pipe = intel_crtc->pipe;
4202 u32 fp, fp2 = 0;
4203
4204 if (IS_PINEVIEW(dev)) {
4205 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4206 if (reduced_clock)
4207 fp2 = (1 << reduced_clock->n) << 16 |
4208 reduced_clock->m1 << 8 | reduced_clock->m2;
4209 } else {
4210 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4211 if (reduced_clock)
4212 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4213 reduced_clock->m2;
4214 }
4215
4216 I915_WRITE(FP0(pipe), fp);
4217
4218 intel_crtc->lowfreq_avail = false;
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4220 reduced_clock && i915_powersave) {
4221 I915_WRITE(FP1(pipe), fp2);
4222 intel_crtc->lowfreq_avail = true;
4223 } else {
4224 I915_WRITE(FP1(pipe), fp);
4225 }
4226}
4227
a0c4da24
JB		 4228static void vlv_update_pll(struct drm_crtc *crtc,
4229 struct drm_display_mode *mode,
4230 struct drm_display_mode *adjusted_mode,
4231 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4232 int num_connectors)
a0c4da24
JB		 4233{
4234 struct drm_device *dev = crtc->dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4237 int pipe = intel_crtc->pipe;
4238 u32 dpll, mdiv, pdiv;
4239 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4240 bool is_sdvo;
4241 u32 temp;
a0c4da24 4242
09153000
DV		 4243 mutex_lock(&dev_priv->dpio_lock);
4244
2a8f64ca
VP		 4245 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4246 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4247
2a8f64ca
VP		 4248 dpll = DPLL_VGA_MODE_DIS;
4249 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4250 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4251 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4252
4253 I915_WRITE(DPLL(pipe), dpll);
4254 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4255
4256 bestn = clock->n;
4257 bestm1 = clock->m1;
4258 bestm2 = clock->m2;
4259 bestp1 = clock->p1;
4260 bestp2 = clock->p2;
4261
2a8f64ca
VP		 4262 /*
4263 * In Valleyview PLL and program lane counter registers are exposed
4264 * through DPIO interface
4265 */
a0c4da24
JB		 4266 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4267 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4268 mdiv |= ((bestn << DPIO_N_SHIFT));
4269 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4270 mdiv |= (1 << DPIO_K_SHIFT);
4271 mdiv |= DPIO_ENABLE_CALIBRATION;
4272 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4273
4274 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4275
2a8f64ca 4276 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4277 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4278 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4279 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4280 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4281
2a8f64ca 4282 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4283
4284 dpll |= DPLL_VCO_ENABLE;
4285 I915_WRITE(DPLL(pipe), dpll);
4286 POSTING_READ(DPLL(pipe));
4287 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4288 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4289
2a8f64ca
VP		 4290 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4291
4292 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4293 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4294
4295 I915_WRITE(DPLL(pipe), dpll);
4296
4297 /* Wait for the clocks to stabilize. */
4298 POSTING_READ(DPLL(pipe));
4299 udelay(150);
a0c4da24 4300
2a8f64ca
VP		 4301 temp = 0;
4302 if (is_sdvo) {
4303 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4304 if (temp > 1)
4305 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4306 else
4307 temp = 0;
a0c4da24 4308 }
2a8f64ca
VP		 4309 I915_WRITE(DPLL_MD(pipe), temp);
4310 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4311
2a8f64ca
VP		 4312 /* Now program lane control registers */
4313 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4314 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4315 {
4316 temp = 0x1000C4;
4317 if(pipe == 1)
4318 temp |= (1 << 21);
4319 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4320 }
4321 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4322 {
4323 temp = 0x1000C4;
4324 if(pipe == 1)
4325 temp |= (1 << 21);
4326 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4327 }
09153000
DV		 4328
4329 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4330}
4331
eb1cbe48
DV		 4332static void i9xx_update_pll(struct drm_crtc *crtc,
4333 struct drm_display_mode *mode,
4334 struct drm_display_mode *adjusted_mode,
4335 intel_clock_t *clock, intel_clock_t *reduced_clock,
4336 int num_connectors)
4337{
4338 struct drm_device *dev = crtc->dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4341 struct intel_encoder *encoder;
eb1cbe48
DV		 4342 int pipe = intel_crtc->pipe;
4343 u32 dpll;
4344 bool is_sdvo;
4345
2a8f64ca
VP		 4346 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4347
eb1cbe48
DV		 4348 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4349 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4350
4351 dpll = DPLL_VGA_MODE_DIS;
4352
4353 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4354 dpll |= DPLLB_MODE_LVDS;
4355 else
4356 dpll |= DPLLB_MODE_DAC_SERIAL;
4357 if (is_sdvo) {
4358 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4359 if (pixel_multiplier > 1) {
4360 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4361 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4362 }
4363 dpll |= DPLL_DVO_HIGH_SPEED;
4364 }
4365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4366 dpll |= DPLL_DVO_HIGH_SPEED;
4367
4368 /* compute bitmask from p1 value */
4369 if (IS_PINEVIEW(dev))
4370 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4371 else {
4372 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4373 if (IS_G4X(dev) && reduced_clock)
4374 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4375 }
4376 switch (clock->p2) {
4377 case 5:
4378 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4379 break;
4380 case 7:
4381 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4382 break;
4383 case 10:
4384 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4385 break;
4386 case 14:
4387 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4388 break;
4389 }
4390 if (INTEL_INFO(dev)->gen >= 4)
4391 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4392
4393 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4394 dpll |= PLL_REF_INPUT_TVCLKINBC;
4395 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4396 /* XXX: just matching BIOS for now */
4397 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4398 dpll |= 3;
4399 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4400 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4401 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4402 else
4403 dpll |= PLL_REF_INPUT_DREFCLK;
4404
4405 dpll |= DPLL_VCO_ENABLE;
4406 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4407 POSTING_READ(DPLL(pipe));
4408 udelay(150);
4409
dafd226c
DV		 4410 for_each_encoder_on_crtc(dev, crtc, encoder)
4411 if (encoder->pre_pll_enable)
4412 encoder->pre_pll_enable(encoder);
4413
eb1cbe48
DV		 4414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4415 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4416
4417 I915_WRITE(DPLL(pipe), dpll);
4418
4419 /* Wait for the clocks to stabilize. */
4420 POSTING_READ(DPLL(pipe));
4421 udelay(150);
4422
4423 if (INTEL_INFO(dev)->gen >= 4) {
4424 u32 temp = 0;
4425 if (is_sdvo) {
4426 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4427 if (temp > 1)
4428 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4429 else
4430 temp = 0;
4431 }
4432 I915_WRITE(DPLL_MD(pipe), temp);
4433 } else {
4434 /* The pixel multiplier can only be updated once the
4435 * DPLL is enabled and the clocks are stable.
4436 *
4437 * So write it again.
4438 */
4439 I915_WRITE(DPLL(pipe), dpll);
4440 }
4441}
4442
4443static void i8xx_update_pll(struct drm_crtc *crtc,
4444 struct drm_display_mode *adjusted_mode,
2a8f64ca 4445 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4446 int num_connectors)
4447{
4448 struct drm_device *dev = crtc->dev;
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4451 struct intel_encoder *encoder;
eb1cbe48
DV		 4452 int pipe = intel_crtc->pipe;
4453 u32 dpll;
4454
2a8f64ca
VP		 4455 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4456
eb1cbe48
DV		 4457 dpll = DPLL_VGA_MODE_DIS;
4458
4459 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4460 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4461 } else {
4462 if (clock->p1 == 2)
4463 dpll |= PLL_P1_DIVIDE_BY_TWO;
4464 else
4465 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4466 if (clock->p2 == 4)
4467 dpll |= PLL_P2_DIVIDE_BY_4;
4468 }
4469
4470 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4471 /* XXX: just matching BIOS for now */
4472 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4473 dpll |= 3;
4474 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4475 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4476 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4477 else
4478 dpll |= PLL_REF_INPUT_DREFCLK;
4479
4480 dpll |= DPLL_VCO_ENABLE;
4481 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4482 POSTING_READ(DPLL(pipe));
4483 udelay(150);
4484
dafd226c
DV		 4485 for_each_encoder_on_crtc(dev, crtc, encoder)
4486 if (encoder->pre_pll_enable)
4487 encoder->pre_pll_enable(encoder);
4488
5b5896e4
DV		 4489 I915_WRITE(DPLL(pipe), dpll);
4490
4491 /* Wait for the clocks to stabilize. */
4492 POSTING_READ(DPLL(pipe));
4493 udelay(150);
4494
eb1cbe48
DV		 4495 /* The pixel multiplier can only be updated once the
4496 * DPLL is enabled and the clocks are stable.
4497 *
4498 * So write it again.
4499 */
4500 I915_WRITE(DPLL(pipe), dpll);
4501}
4502
b0e77b9c
PZ		 4503static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4504 struct drm_display_mode *mode,
4505 struct drm_display_mode *adjusted_mode)
4506{
4507 struct drm_device *dev = intel_crtc->base.dev;
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4510 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4511 uint32_t vsyncshift;
4512
4513 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4514 /* the chip adds 2 halflines automatically */
4515 adjusted_mode->crtc_vtotal -= 1;
4516 adjusted_mode->crtc_vblank_end -= 1;
4517 vsyncshift = adjusted_mode->crtc_hsync_start
4518 - adjusted_mode->crtc_htotal / 2;
4519 } else {
4520 vsyncshift = 0;
4521 }
4522
4523 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4524 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4525
fe2b8f9d 4526 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4527 (adjusted_mode->crtc_hdisplay - 1) |
4528 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4529 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4530 (adjusted_mode->crtc_hblank_start - 1) |
4531 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4532 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4533 (adjusted_mode->crtc_hsync_start - 1) |
4534 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4535
fe2b8f9d 4536 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4537 (adjusted_mode->crtc_vdisplay - 1) |
4538 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4539 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4540 (adjusted_mode->crtc_vblank_start - 1) |
4541 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4542 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4543 (adjusted_mode->crtc_vsync_start - 1) |
4544 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4545
b5e508d4
PZ		 4546 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4547 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4548 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4549 * bits. */
4550 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4551 (pipe == PIPE_B || pipe == PIPE_C))
4552 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4553
b0e77b9c
PZ		 4554 /* pipesrc controls the size that is scaled from, which should
4555 * always be the user's requested size.
4556 */
4557 I915_WRITE(PIPESRC(pipe),
4558 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4559}
4560
f564048e
EA		 4561static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4562 struct drm_display_mode *mode,
4563 struct drm_display_mode *adjusted_mode,
4564 int x, int y,
94352cf9 4565 struct drm_framebuffer *fb)
79e53945
JB		 4566{
4567 struct drm_device *dev = crtc->dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4570 int pipe = intel_crtc->pipe;
80824003 4571 int plane = intel_crtc->plane;
c751ce4f 4572 int refclk, num_connectors = 0;
652c393a 4573 intel_clock_t clock, reduced_clock;
b0e77b9c 4574 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4575 bool ok, has_reduced_clock = false, is_sdvo = false;
4576 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4577 struct intel_encoder *encoder;
d4906093 4578 const intel_limit_t *limit;
5c3b82e2 4579 int ret;
79e53945 4580
6c2b7c12 4581 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4582 switch (encoder->type) {
79e53945
JB		 4583 case INTEL_OUTPUT_LVDS:
4584 is_lvds = true;
4585 break;
4586 case INTEL_OUTPUT_SDVO:
7d57382e 4587 case INTEL_OUTPUT_HDMI:
79e53945 4588 is_sdvo = true;
5eddb70b 4589 if (encoder->needs_tv_clock)
e2f0ba97 4590 is_tv = true;
79e53945 4591 break;
79e53945
JB		 4592 case INTEL_OUTPUT_TVOUT:
4593 is_tv = true;
4594 break;
a4fc5ed6
KP		 4595 case INTEL_OUTPUT_DISPLAYPORT:
4596 is_dp = true;
4597 break;
79e53945 4598 }
43565a06 4599
c751ce4f 4600 num_connectors++;
79e53945
JB		 4601 }
4602
c65d77d8 4603 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4604
d4906093
ML		 4605 /*
4606 * Returns a set of divisors for the desired target clock with the given
4607 * refclk, or FALSE. The returned values represent the clock equation:
4608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4609 */
1b894b59 4610 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4611 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4612 &clock);
79e53945
JB		 4613 if (!ok) {
4614 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4615 return -EINVAL;
79e53945
JB		 4616 }
4617
cda4b7d3 4618 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4619 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4620
ddc9003c 4621 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4622 /*
4623 * Ensure we match the reduced clock's P to the target clock.
4624 * If the clocks don't match, we can't switch the display clock
4625 * by using the FP0/FP1. In such case we will disable the LVDS
4626 * downclock feature.
4627 */
ddc9003c 4628 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4629 dev_priv->lvds_downclock,
4630 refclk,
cec2f356 4631 &clock,
5eddb70b 4632 &reduced_clock);
7026d4ac
ZW		 4633 }
4634
c65d77d8
JB		 4635 if (is_sdvo && is_tv)
4636 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4637
eb1cbe48 4638 if (IS_GEN2(dev))
2a8f64ca
VP		 4639 i8xx_update_pll(crtc, adjusted_mode, &clock,
4640 has_reduced_clock ? &reduced_clock : NULL,
4641 num_connectors);
a0c4da24 4642 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4643 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4644 has_reduced_clock ? &reduced_clock : NULL,
4645 num_connectors);
79e53945 4646 else
eb1cbe48
DV		 4647 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4648 has_reduced_clock ? &reduced_clock : NULL,
4649 num_connectors);
79e53945
JB		 4650
4651 /* setup pipeconf */
5eddb70b 4652 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4653
4654 /* Set up the display plane register */
4655 dspcntr = DISPPLANE_GAMMA_ENABLE;
4656
929c77fb
EA		 4657 if (pipe == 0)
4658 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4659 else
4660 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4661
a6c45cf0 4662 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4663 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4664 * core speed.
4665 *
4666 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4667 * pipe == 0 check?
4668 */
e70236a8
JB		 4669 if (mode->clock >
4670 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4671 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4672 else
5eddb70b 4673 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4674 }
4675
3b5c78a3
AJ		 4676 /* default to 8bpc */
4677 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4678 if (is_dp) {
0c96c65b 4679 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4680 pipeconf |= PIPECONF_BPP_6 |
4681 PIPECONF_DITHER_EN |
4682 PIPECONF_DITHER_TYPE_SP;
4683 }
4684 }
4685
19c03924
GB		 4686 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4687 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4688 pipeconf |= PIPECONF_BPP_6 |
4689 PIPECONF_ENABLE |
4690 I965_PIPECONF_ACTIVE;
4691 }
4692 }
4693
28c97730 4694 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4695 drm_mode_debug_printmodeline(mode);
4696
a7516a05
JB		 4697 if (HAS_PIPE_CXSR(dev)) {
4698 if (intel_crtc->lowfreq_avail) {
28c97730 4699 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4700 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4701 } else {
28c97730 4702 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4703 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4704 }
4705 }
4706
617cf884 4707 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4708 if (!IS_GEN2(dev) &&
b0e77b9c 4709 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4710 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4711 else
617cf884 4712 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4713
b0e77b9c 4714 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4715
4716 /* pipesrc and dspsize control the size that is scaled from,
4717 * which should always be the user's requested size.
79e53945 4718 */
929c77fb
EA		 4719 I915_WRITE(DSPSIZE(plane),
4720 ((mode->vdisplay - 1) << 16) |
4721 (mode->hdisplay - 1));
4722 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4723
f564048e
EA		 4724 I915_WRITE(PIPECONF(pipe), pipeconf);
4725 POSTING_READ(PIPECONF(pipe));
929c77fb 4726 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4727
4728 intel_wait_for_vblank(dev, pipe);
4729
f564048e
EA		 4730 I915_WRITE(DSPCNTR(plane), dspcntr);
4731 POSTING_READ(DSPCNTR(plane));
4732
94352cf9 4733 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4734
4735 intel_update_watermarks(dev);
4736
f564048e
EA		 4737 return ret;
4738}
4739
9fb526db
KP		 4740/*
4741 * Initialize reference clocks when the driver loads
4742 */
4743void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4744{
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4747 struct intel_encoder *encoder;
13d83a67
JB		 4748 u32 temp;
4749 bool has_lvds = false;
199e5d79
KP		 4750 bool has_cpu_edp = false;
4751 bool has_pch_edp = false;
4752 bool has_panel = false;
99eb6a01
KP		 4753 bool has_ck505 = false;
4754 bool can_ssc = false;
13d83a67
JB		 4755
4756 /* We need to take the global config into account */
199e5d79
KP		 4757 list_for_each_entry(encoder, &mode_config->encoder_list,
4758 base.head) {
4759 switch (encoder->type) {
4760 case INTEL_OUTPUT_LVDS:
4761 has_panel = true;
4762 has_lvds = true;
4763 break;
4764 case INTEL_OUTPUT_EDP:
4765 has_panel = true;
4766 if (intel_encoder_is_pch_edp(&encoder->base))
4767 has_pch_edp = true;
4768 else
4769 has_cpu_edp = true;
4770 break;
13d83a67
JB		 4771 }
4772 }
4773
99eb6a01
KP		 4774 if (HAS_PCH_IBX(dev)) {
4775 has_ck505 = dev_priv->display_clock_mode;
4776 can_ssc = has_ck505;
4777 } else {
4778 has_ck505 = false;
4779 can_ssc = true;
4780 }
4781
4782 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4783 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4784 has_ck505);
13d83a67
JB		 4785
4786 /* Ironlake: try to setup display ref clock before DPLL
4787 * enabling. This is only under driver's control after
4788 * PCH B stepping, previous chipset stepping should be
4789 * ignoring this setting.
4790 */
4791 temp = I915_READ(PCH_DREF_CONTROL);
4792 /* Always enable nonspread source */
4793 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4794
99eb6a01
KP		 4795 if (has_ck505)
4796 temp |= DREF_NONSPREAD_CK505_ENABLE;
4797 else
4798 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4799
199e5d79
KP		 4800 if (has_panel) {
4801 temp &= ~DREF_SSC_SOURCE_MASK;
4802 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4803
199e5d79 4804 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4805 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4806 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4807 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4808 } else
4809 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4810
4811 /* Get SSC going before enabling the outputs */
4812 I915_WRITE(PCH_DREF_CONTROL, temp);
4813 POSTING_READ(PCH_DREF_CONTROL);
4814 udelay(200);
4815
13d83a67
JB		 4816 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4817
4818 /* Enable CPU source on CPU attached eDP */
199e5d79 4819 if (has_cpu_edp) {
99eb6a01 4820 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4821 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4822 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4823 }
13d83a67
JB		 4824 else
4825 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4826 } else
4827 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4828
4829 I915_WRITE(PCH_DREF_CONTROL, temp);
4830 POSTING_READ(PCH_DREF_CONTROL);
4831 udelay(200);
4832 } else {
4833 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4834
4835 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4836
4837 /* Turn off CPU output */
4838 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4839
4840 I915_WRITE(PCH_DREF_CONTROL, temp);
4841 POSTING_READ(PCH_DREF_CONTROL);
4842 udelay(200);
4843
4844 /* Turn off the SSC source */
4845 temp &= ~DREF_SSC_SOURCE_MASK;
4846 temp |= DREF_SSC_SOURCE_DISABLE;
4847
4848 /* Turn off SSC1 */
4849 temp &= ~ DREF_SSC1_ENABLE;
4850
13d83a67
JB		 4851 I915_WRITE(PCH_DREF_CONTROL, temp);
4852 POSTING_READ(PCH_DREF_CONTROL);
4853 udelay(200);
4854 }
4855}
4856
d9d444cb
JB		 4857static int ironlake_get_refclk(struct drm_crtc *crtc)
4858{
4859 struct drm_device *dev = crtc->dev;
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 struct intel_encoder *encoder;
d9d444cb
JB		 4862 struct intel_encoder *edp_encoder = NULL;
4863 int num_connectors = 0;
4864 bool is_lvds = false;
4865
6c2b7c12 4866 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4867 switch (encoder->type) {
4868 case INTEL_OUTPUT_LVDS:
4869 is_lvds = true;
4870 break;
4871 case INTEL_OUTPUT_EDP:
4872 edp_encoder = encoder;
4873 break;
4874 }
4875 num_connectors++;
4876 }
4877
4878 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4879 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4880 dev_priv->lvds_ssc_freq);
4881 return dev_priv->lvds_ssc_freq * 1000;
4882 }
4883
4884 return 120000;
4885}
4886
c8203565 4887static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 4888 struct drm_display_mode *adjusted_mode,
c8203565 4889 bool dither)
79e53945 4890{
c8203565 4891 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 4892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893 int pipe = intel_crtc->pipe;
c8203565
PZ		 4894 uint32_t val;
4895
4896 val = I915_READ(PIPECONF(pipe));
4897
4898 val &= ~PIPE_BPC_MASK;
4899 switch (intel_crtc->bpp) {
4900 case 18:
4901 val |= PIPE_6BPC;
4902 break;
4903 case 24:
4904 val |= PIPE_8BPC;
4905 break;
4906 case 30:
4907 val |= PIPE_10BPC;
4908 break;
4909 case 36:
4910 val |= PIPE_12BPC;
4911 break;
4912 default:
cc769b62
PZ		 4913 /* Case prevented by intel_choose_pipe_bpp_dither. */
4914 BUG();
c8203565
PZ		 4915 }
4916
4917 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4918 if (dither)
4919 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4920
4921 val &= ~PIPECONF_INTERLACE_MASK;
4922 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4923 val |= PIPECONF_INTERLACED_ILK;
4924 else
4925 val |= PIPECONF_PROGRESSIVE;
4926
4927 I915_WRITE(PIPECONF(pipe), val);
4928 POSTING_READ(PIPECONF(pipe));
4929}
4930
ee2b0b38
PZ		 4931static void haswell_set_pipeconf(struct drm_crtc *crtc,
4932 struct drm_display_mode *adjusted_mode,
4933 bool dither)
4934{
4935 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4937 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4938 uint32_t val;
4939
702e7a56 4940 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4941
4942 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4943 if (dither)
4944 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4945
4946 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4947 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4948 val |= PIPECONF_INTERLACED_ILK;
4949 else
4950 val |= PIPECONF_PROGRESSIVE;
4951
702e7a56
PZ		 4952 I915_WRITE(PIPECONF(cpu_transcoder), val);
4953 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4954}
4955
6591c6e4
PZ		 4956static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4957 struct drm_display_mode *adjusted_mode,
4958 intel_clock_t *clock,
4959 bool *has_reduced_clock,
4960 intel_clock_t *reduced_clock)
4961{
4962 struct drm_device *dev = crtc->dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 struct intel_encoder *intel_encoder;
4965 int refclk;
d4906093 4966 const intel_limit_t *limit;
6591c6e4 4967 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 4968
6591c6e4
PZ		 4969 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4970 switch (intel_encoder->type) {
79e53945
JB		 4971 case INTEL_OUTPUT_LVDS:
4972 is_lvds = true;
4973 break;
4974 case INTEL_OUTPUT_SDVO:
7d57382e 4975 case INTEL_OUTPUT_HDMI:
79e53945 4976 is_sdvo = true;
6591c6e4 4977 if (intel_encoder->needs_tv_clock)
e2f0ba97 4978 is_tv = true;
79e53945 4979 break;
79e53945
JB		 4980 case INTEL_OUTPUT_TVOUT:
4981 is_tv = true;
4982 break;
79e53945
JB		 4983 }
4984 }
4985
d9d444cb 4986 refclk = ironlake_get_refclk(crtc);
79e53945 4987
d4906093
ML		 4988 /*
4989 * Returns a set of divisors for the desired target clock with the given
4990 * refclk, or FALSE. The returned values represent the clock equation:
4991 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4992 */
1b894b59 4993 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 4994 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4995 clock);
4996 if (!ret)
4997 return false;
cda4b7d3 4998
ddc9003c 4999 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5000 /*
5001 * Ensure we match the reduced clock's P to the target clock.
5002 * If the clocks don't match, we can't switch the display clock
5003 * by using the FP0/FP1. In such case we will disable the LVDS
5004 * downclock feature.
5005 */
6591c6e4
PZ		 5006 *has_reduced_clock = limit->find_pll(limit, crtc,
5007 dev_priv->lvds_downclock,
5008 refclk,
5009 clock,
5010 reduced_clock);
652c393a 5011 }
61e9653f
DV		 5012
5013 if (is_sdvo && is_tv)
6591c6e4
PZ		 5014 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5015
5016 return true;
5017}
5018
01a415fd
DV		 5019static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5020{
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 uint32_t temp;
5023
5024 temp = I915_READ(SOUTH_CHICKEN1);
5025 if (temp & FDI_BC_BIFURCATION_SELECT)
5026 return;
5027
5028 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5029 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5030
5031 temp |= FDI_BC_BIFURCATION_SELECT;
5032 DRM_DEBUG_KMS("enabling fdi C rx\n");
5033 I915_WRITE(SOUTH_CHICKEN1, temp);
5034 POSTING_READ(SOUTH_CHICKEN1);
5035}
5036
5037static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5038{
5039 struct drm_device *dev = intel_crtc->base.dev;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 struct intel_crtc *pipe_B_crtc =
5042 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5043
5044 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5045 intel_crtc->pipe, intel_crtc->fdi_lanes);
5046 if (intel_crtc->fdi_lanes > 4) {
5047 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5048 intel_crtc->pipe, intel_crtc->fdi_lanes);
5049 /* Clamp lanes to avoid programming the hw with bogus values. */
5050 intel_crtc->fdi_lanes = 4;
5051
5052 return false;
5053 }
5054
5055 if (dev_priv->num_pipe == 2)
5056 return true;
5057
5058 switch (intel_crtc->pipe) {
5059 case PIPE_A:
5060 return true;
5061 case PIPE_B:
5062 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5063 intel_crtc->fdi_lanes > 2) {
5064 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5065 intel_crtc->pipe, intel_crtc->fdi_lanes);
5066 /* Clamp lanes to avoid programming the hw with bogus values. */
5067 intel_crtc->fdi_lanes = 2;
5068
5069 return false;
5070 }
5071
5072 if (intel_crtc->fdi_lanes > 2)
5073 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5074 else
5075 cpt_enable_fdi_bc_bifurcation(dev);
5076
5077 return true;
5078 case PIPE_C:
5079 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5080 if (intel_crtc->fdi_lanes > 2) {
5081 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5082 intel_crtc->pipe, intel_crtc->fdi_lanes);
5083 /* Clamp lanes to avoid programming the hw with bogus values. */
5084 intel_crtc->fdi_lanes = 2;
5085
5086 return false;
5087 }
5088 } else {
5089 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5090 return false;
5091 }
5092
5093 cpt_enable_fdi_bc_bifurcation(dev);
5094
5095 return true;
5096 default:
5097 BUG();
5098 }
5099}
5100
f48d8f23
PZ		 5101static void ironlake_set_m_n(struct drm_crtc *crtc,
5102 struct drm_display_mode *mode,
5103 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5104{
5105 struct drm_device *dev = crtc->dev;
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5108 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5109 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5110 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5111 int target_clock, pixel_multiplier, lane, link_bw;
5112 bool is_dp = false, is_cpu_edp = false;
79e53945 5113
f48d8f23
PZ		 5114 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5115 switch (intel_encoder->type) {
a4fc5ed6
KP		 5116 case INTEL_OUTPUT_DISPLAYPORT:
5117 is_dp = true;
5118 break;
32f9d658 5119 case INTEL_OUTPUT_EDP:
e3aef172 5120 is_dp = true;
f48d8f23 5121 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5122 is_cpu_edp = true;
f48d8f23 5123 edp_encoder = intel_encoder;
32f9d658 5124 break;
79e53945 5125 }
79e53945 5126 }
61e9653f 5127
2c07245f 5128 /* FDI link */
8febb297
EA		 5129 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5130 lane = 0;
5131 /* CPU eDP doesn't require FDI link, so just set DP M/N
5132 according to current link config */
e3aef172 5133 if (is_cpu_edp) {
e3aef172 5134 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5135 } else {
8febb297
EA		 5136 /* FDI is a binary signal running at ~2.7GHz, encoding
5137 * each output octet as 10 bits. The actual frequency
5138 * is stored as a divider into a 100MHz clock, and the
5139 * mode pixel clock is stored in units of 1KHz.
5140 * Hence the bw of each lane in terms of the mode signal
5141 * is:
5142 */
5143 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5144 }
58a27471 5145
94bf2ced
DV		 5146 /* [e]DP over FDI requires target mode clock instead of link clock. */
5147 if (edp_encoder)
5148 target_clock = intel_edp_target_clock(edp_encoder, mode);
5149 else if (is_dp)
5150 target_clock = mode->clock;
5151 else
5152 target_clock = adjusted_mode->clock;
5153
8febb297
EA		 5154 if (!lane) {
5155 /*
5156 * Account for spread spectrum to avoid
5157 * oversubscribing the link. Max center spread
5158 * is 2.5%; use 5% for safety's sake.
5159 */
5a354204 5160 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5161 lane = bps / (link_bw * 8) + 1;
5eb08b69 5162 }
2c07245f 5163
8febb297
EA		 5164 intel_crtc->fdi_lanes = lane;
5165
5166 if (pixel_multiplier > 1)
5167 link_bw *= pixel_multiplier;
e69d0bc1 5168 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5169
afe2fcf5
PZ		 5170 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5171 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5172 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5173 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5174}
5175
de13a2e3
PZ		 5176static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5177 struct drm_display_mode *adjusted_mode,
5178 intel_clock_t *clock, u32 fp)
79e53945 5179{
de13a2e3 5180 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5181 struct drm_device *dev = crtc->dev;
5182 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5183 struct intel_encoder *intel_encoder;
5184 uint32_t dpll;
5185 int factor, pixel_multiplier, num_connectors = 0;
5186 bool is_lvds = false, is_sdvo = false, is_tv = false;
5187 bool is_dp = false, is_cpu_edp = false;
79e53945 5188
de13a2e3
PZ		 5189 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5190 switch (intel_encoder->type) {
79e53945
JB		 5191 case INTEL_OUTPUT_LVDS:
5192 is_lvds = true;
5193 break;
5194 case INTEL_OUTPUT_SDVO:
7d57382e 5195 case INTEL_OUTPUT_HDMI:
79e53945 5196 is_sdvo = true;
de13a2e3 5197 if (intel_encoder->needs_tv_clock)
e2f0ba97 5198 is_tv = true;
79e53945 5199 break;
79e53945
JB		 5200 case INTEL_OUTPUT_TVOUT:
5201 is_tv = true;
5202 break;
a4fc5ed6
KP		 5203 case INTEL_OUTPUT_DISPLAYPORT:
5204 is_dp = true;
5205 break;
32f9d658 5206 case INTEL_OUTPUT_EDP:
e3aef172 5207 is_dp = true;
de13a2e3 5208 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5209 is_cpu_edp = true;
32f9d658 5210 break;
79e53945 5211 }
43565a06 5212
c751ce4f 5213 num_connectors++;
79e53945 5214 }
79e53945 5215
c1858123 5216 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5217 factor = 21;
5218 if (is_lvds) {
5219 if ((intel_panel_use_ssc(dev_priv) &&
5220 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5221 intel_is_dual_link_lvds(dev))
8febb297
EA		 5222 factor = 25;
5223 } else if (is_sdvo && is_tv)
5224 factor = 20;
c1858123 5225
de13a2e3 5226 if (clock->m < factor * clock->n)
8febb297 5227 fp |= FP_CB_TUNE;
2c07245f 5228
5eddb70b 5229 dpll = 0;
2c07245f 5230
a07d6787
EA		 5231 if (is_lvds)
5232 dpll |= DPLLB_MODE_LVDS;
5233 else
5234 dpll |= DPLLB_MODE_DAC_SERIAL;
5235 if (is_sdvo) {
de13a2e3 5236 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5237 if (pixel_multiplier > 1) {
5238 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5239 }
a07d6787
EA		 5240 dpll |= DPLL_DVO_HIGH_SPEED;
5241 }
e3aef172 5242 if (is_dp && !is_cpu_edp)
a07d6787 5243 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5244
a07d6787 5245 /* compute bitmask from p1 value */
de13a2e3 5246 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5247 /* also FPA1 */
de13a2e3 5248 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5249
de13a2e3 5250 switch (clock->p2) {
a07d6787
EA		 5251 case 5:
5252 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5253 break;
5254 case 7:
5255 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5256 break;
5257 case 10:
5258 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5259 break;
5260 case 14:
5261 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5262 break;
79e53945
JB		 5263 }
5264
43565a06
KH		 5265 if (is_sdvo && is_tv)
5266 dpll |= PLL_REF_INPUT_TVCLKINBC;
5267 else if (is_tv)
79e53945 5268 /* XXX: just matching BIOS for now */
43565a06 5269 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5270 dpll |= 3;
a7615030 5271 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5272 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5273 else
5274 dpll |= PLL_REF_INPUT_DREFCLK;
5275
de13a2e3
PZ		 5276 return dpll;
5277}
5278
5279static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5280 struct drm_display_mode *mode,
5281 struct drm_display_mode *adjusted_mode,
5282 int x, int y,
5283 struct drm_framebuffer *fb)
5284{
5285 struct drm_device *dev = crtc->dev;
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288 int pipe = intel_crtc->pipe;
5289 int plane = intel_crtc->plane;
5290 int num_connectors = 0;
5291 intel_clock_t clock, reduced_clock;
5292 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5293 bool ok, has_reduced_clock = false;
5294 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5295 struct intel_encoder *encoder;
de13a2e3 5296 int ret;
01a415fd 5297 bool dither, fdi_config_ok;
de13a2e3
PZ		 5298
5299 for_each_encoder_on_crtc(dev, crtc, encoder) {
5300 switch (encoder->type) {
5301 case INTEL_OUTPUT_LVDS:
5302 is_lvds = true;
5303 break;
de13a2e3
PZ		 5304 case INTEL_OUTPUT_DISPLAYPORT:
5305 is_dp = true;
5306 break;
5307 case INTEL_OUTPUT_EDP:
5308 is_dp = true;
e2f12b07 5309 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5310 is_cpu_edp = true;
5311 break;
5312 }
5313
5314 num_connectors++;
a07d6787 5315 }
79e53945 5316
5dc5298b
PZ		 5317 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5318 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5319
de13a2e3
PZ		 5320 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5321 &has_reduced_clock, &reduced_clock);
5322 if (!ok) {
5323 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5324 return -EINVAL;
79e53945
JB		 5325 }
5326
de13a2e3
PZ		 5327 /* Ensure that the cursor is valid for the new mode before changing... */
5328 intel_crtc_update_cursor(crtc, true);
5329
5330 /* determine panel color depth */
c8241969
JN		 5331 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5332 adjusted_mode);
de13a2e3
PZ		 5333 if (is_lvds && dev_priv->lvds_dither)
5334 dither = true;
5335
5336 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5337 if (has_reduced_clock)
5338 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5339 reduced_clock.m2;
5340
5341 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5342
f7cb34d4 5343 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5344 drm_mode_debug_printmodeline(mode);
5345
5dc5298b
PZ		 5346 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5347 if (!is_cpu_edp) {
ee7b9f93 5348 struct intel_pch_pll *pll;
4b645f14 5349
ee7b9f93
JB		 5350 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5351 if (pll == NULL) {
5352 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5353 pipe);
4b645f14
JB		 5354 return -EINVAL;
5355 }
ee7b9f93
JB		 5356 } else
5357 intel_put_pch_pll(intel_crtc);
79e53945 5358
2f0c2ad1 5359 if (is_dp && !is_cpu_edp)
a4fc5ed6 5360 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5361
dafd226c
DV		 5362 for_each_encoder_on_crtc(dev, crtc, encoder)
5363 if (encoder->pre_pll_enable)
5364 encoder->pre_pll_enable(encoder);
5365
ee7b9f93
JB		 5366 if (intel_crtc->pch_pll) {
5367 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5368
32f9d658 5369 /* Wait for the clocks to stabilize. */
ee7b9f93 5370 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5371 udelay(150);
5372
8febb297
EA		 5373 /* The pixel multiplier can only be updated once the
5374 * DPLL is enabled and the clocks are stable.
5375 *
5376 * So write it again.
5377 */
ee7b9f93 5378 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5379 }
79e53945 5380
5eddb70b 5381 intel_crtc->lowfreq_avail = false;
ee7b9f93 5382 if (intel_crtc->pch_pll) {
4b645f14 5383 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5384 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5385 intel_crtc->lowfreq_avail = true;
4b645f14 5386 } else {
ee7b9f93 5387 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5388 }
5389 }
5390
b0e77b9c 5391 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5392
01a415fd
DV		 5393 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5394 * ironlake_check_fdi_lanes. */
f48d8f23 5395 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5396
01a415fd 5397 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5398
c8203565 5399 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5400
9d0498a2 5401 intel_wait_for_vblank(dev, pipe);
79e53945 5402
a1f9e77e
PZ		 5403 /* Set up the display plane register */
5404 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5405 POSTING_READ(DSPCNTR(plane));
79e53945 5406
94352cf9 5407 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5408
5409 intel_update_watermarks(dev);
5410
1f8eeabf
ED		 5411 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5412
01a415fd 5413 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5414}
5415
09b4ddf9
PZ		 5416static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5417 struct drm_display_mode *mode,
5418 struct drm_display_mode *adjusted_mode,
5419 int x, int y,
5420 struct drm_framebuffer *fb)
5421{
5422 struct drm_device *dev = crtc->dev;
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5425 int pipe = intel_crtc->pipe;
5426 int plane = intel_crtc->plane;
5427 int num_connectors = 0;
ed7ef439 5428 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5429 struct intel_encoder *encoder;
09b4ddf9
PZ		 5430 int ret;
5431 bool dither;
5432
5433 for_each_encoder_on_crtc(dev, crtc, encoder) {
5434 switch (encoder->type) {
09b4ddf9
PZ		 5435 case INTEL_OUTPUT_DISPLAYPORT:
5436 is_dp = true;
5437 break;
5438 case INTEL_OUTPUT_EDP:
5439 is_dp = true;
5440 if (!intel_encoder_is_pch_edp(&encoder->base))
5441 is_cpu_edp = true;
5442 break;
5443 }
5444
5445 num_connectors++;
5446 }
5447
a5c961d1
PZ		 5448 if (is_cpu_edp)
5449 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5450 else
5451 intel_crtc->cpu_transcoder = pipe;
5452
5dc5298b
PZ		 5453 /* We are not sure yet this won't happen. */
5454 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5455 INTEL_PCH_TYPE(dev));
5456
5457 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5458 num_connectors, pipe_name(pipe));
5459
702e7a56 5460 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5461 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5462
5463 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5464
6441ab5f
PZ		 5465 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5466 return -EINVAL;
5467
09b4ddf9
PZ		 5468 /* Ensure that the cursor is valid for the new mode before changing... */
5469 intel_crtc_update_cursor(crtc, true);
5470
5471 /* determine panel color depth */
c8241969
JN		 5472 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5473 adjusted_mode);
09b4ddf9 5474
09b4ddf9
PZ		 5475 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5476 drm_mode_debug_printmodeline(mode);
5477
ed7ef439 5478 if (is_dp && !is_cpu_edp)
09b4ddf9 5479 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5480
5481 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5482
5483 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5484
1eb8dfec
PZ		 5485 if (!is_dp || is_cpu_edp)
5486 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5487
ee2b0b38 5488 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5489
09b4ddf9
PZ		 5490 /* Set up the display plane register */
5491 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5492 POSTING_READ(DSPCNTR(plane));
5493
5494 ret = intel_pipe_set_base(crtc, x, y, fb);
5495
5496 intel_update_watermarks(dev);
5497
5498 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5499
1f803ee5 5500 return ret;
79e53945
JB		 5501}
5502
f564048e
EA		 5503static int intel_crtc_mode_set(struct drm_crtc *crtc,
5504 struct drm_display_mode *mode,
5505 struct drm_display_mode *adjusted_mode,
5506 int x, int y,
94352cf9 5507 struct drm_framebuffer *fb)
f564048e
EA		 5508{
5509 struct drm_device *dev = crtc->dev;
5510 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5511 struct drm_encoder_helper_funcs *encoder_funcs;
5512 struct intel_encoder *encoder;
0b701d27
EA		 5513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5514 int pipe = intel_crtc->pipe;
f564048e
EA		 5515 int ret;
5516
0b701d27 5517 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5518
f564048e 5519 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5520 x, y, fb);
79e53945 5521 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5522
9256aa19
DV		 5523 if (ret != 0)
5524 return ret;
5525
5526 for_each_encoder_on_crtc(dev, crtc, encoder) {
5527 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5528 encoder->base.base.id,
5529 drm_get_encoder_name(&encoder->base),
5530 mode->base.id, mode->name);
5531 encoder_funcs = encoder->base.helper_private;
5532 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5533 }
5534
5535 return 0;
79e53945
JB		 5536}
5537
3a9627f4
WF		 5538static bool intel_eld_uptodate(struct drm_connector *connector,
5539 int reg_eldv, uint32_t bits_eldv,
5540 int reg_elda, uint32_t bits_elda,
5541 int reg_edid)
5542{
5543 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5544 uint8_t *eld = connector->eld;
5545 uint32_t i;
5546
5547 i = I915_READ(reg_eldv);
5548 i &= bits_eldv;
5549
5550 if (!eld[0])
5551 return !i;
5552
5553 if (!i)
5554 return false;
5555
5556 i = I915_READ(reg_elda);
5557 i &= ~bits_elda;
5558 I915_WRITE(reg_elda, i);
5559
5560 for (i = 0; i < eld[2]; i++)
5561 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5562 return false;
5563
5564 return true;
5565}
5566
e0dac65e
WF		 5567static void g4x_write_eld(struct drm_connector *connector,
5568 struct drm_crtc *crtc)
5569{
5570 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5571 uint8_t *eld = connector->eld;
5572 uint32_t eldv;
5573 uint32_t len;
5574 uint32_t i;
5575
5576 i = I915_READ(G4X_AUD_VID_DID);
5577
5578 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5579 eldv = G4X_ELDV_DEVCL_DEVBLC;
5580 else
5581 eldv = G4X_ELDV_DEVCTG;
5582
3a9627f4
WF		 5583 if (intel_eld_uptodate(connector,
5584 G4X_AUD_CNTL_ST, eldv,
5585 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5586 G4X_HDMIW_HDMIEDID))
5587 return;
5588
e0dac65e
WF		 5589 i = I915_READ(G4X_AUD_CNTL_ST);
5590 i &= ~(eldv | G4X_ELD_ADDR);
5591 len = (i >> 9) & 0x1f; /* ELD buffer size */
5592 I915_WRITE(G4X_AUD_CNTL_ST, i);
5593
5594 if (!eld[0])
5595 return;
5596
5597 len = min_t(uint8_t, eld[2], len);
5598 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5599 for (i = 0; i < len; i++)
5600 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5601
5602 i = I915_READ(G4X_AUD_CNTL_ST);
5603 i |= eldv;
5604 I915_WRITE(G4X_AUD_CNTL_ST, i);
5605}
5606
83358c85
WX		 5607static void haswell_write_eld(struct drm_connector *connector,
5608 struct drm_crtc *crtc)
5609{
5610 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5611 uint8_t *eld = connector->eld;
5612 struct drm_device *dev = crtc->dev;
5613 uint32_t eldv;
5614 uint32_t i;
5615 int len;
5616 int pipe = to_intel_crtc(crtc)->pipe;
5617 int tmp;
5618
5619 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5620 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5621 int aud_config = HSW_AUD_CFG(pipe);
5622 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5623
5624
5625 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5626
5627 /* Audio output enable */
5628 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5629 tmp = I915_READ(aud_cntrl_st2);
5630 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5631 I915_WRITE(aud_cntrl_st2, tmp);
5632
5633 /* Wait for 1 vertical blank */
5634 intel_wait_for_vblank(dev, pipe);
5635
5636 /* Set ELD valid state */
5637 tmp = I915_READ(aud_cntrl_st2);
5638 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5639 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5640 I915_WRITE(aud_cntrl_st2, tmp);
5641 tmp = I915_READ(aud_cntrl_st2);
5642 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5643
5644 /* Enable HDMI mode */
5645 tmp = I915_READ(aud_config);
5646 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5647 /* clear N_programing_enable and N_value_index */
5648 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5649 I915_WRITE(aud_config, tmp);
5650
5651 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5652
5653 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5654
5655 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5656 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5657 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5658 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5659 } else
5660 I915_WRITE(aud_config, 0);
5661
5662 if (intel_eld_uptodate(connector,
5663 aud_cntrl_st2, eldv,
5664 aud_cntl_st, IBX_ELD_ADDRESS,
5665 hdmiw_hdmiedid))
5666 return;
5667
5668 i = I915_READ(aud_cntrl_st2);
5669 i &= ~eldv;
5670 I915_WRITE(aud_cntrl_st2, i);
5671
5672 if (!eld[0])
5673 return;
5674
5675 i = I915_READ(aud_cntl_st);
5676 i &= ~IBX_ELD_ADDRESS;
5677 I915_WRITE(aud_cntl_st, i);
5678 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5679 DRM_DEBUG_DRIVER("port num:%d\n", i);
5680
5681 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5682 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5683 for (i = 0; i < len; i++)
5684 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5685
5686 i = I915_READ(aud_cntrl_st2);
5687 i |= eldv;
5688 I915_WRITE(aud_cntrl_st2, i);
5689
5690}
5691
e0dac65e
WF		 5692static void ironlake_write_eld(struct drm_connector *connector,
5693 struct drm_crtc *crtc)
5694{
5695 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5696 uint8_t *eld = connector->eld;
5697 uint32_t eldv;
5698 uint32_t i;
5699 int len;
5700 int hdmiw_hdmiedid;
b6daa025 5701 int aud_config;
e0dac65e
WF		 5702 int aud_cntl_st;
5703 int aud_cntrl_st2;
9b138a83 5704 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5705
b3f33cbf 5706 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5707 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5708 aud_config = IBX_AUD_CFG(pipe);
5709 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5710 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5711 } else {
9b138a83
WX		 5712 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5713 aud_config = CPT_AUD_CFG(pipe);
5714 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5715 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5716 }
5717
9b138a83 5718 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5719
5720 i = I915_READ(aud_cntl_st);
9b138a83 5721 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5722 if (!i) {
5723 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5724 /* operate blindly on all ports */
1202b4c6
WF		 5725 eldv = IBX_ELD_VALIDB;
5726 eldv |= IBX_ELD_VALIDB << 4;
5727 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5728 } else {
5729 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5730 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5731 }
5732
3a9627f4
WF		 5733 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5734 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5735 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5736 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5737 } else
5738 I915_WRITE(aud_config, 0);
e0dac65e 5739
3a9627f4
WF		 5740 if (intel_eld_uptodate(connector,
5741 aud_cntrl_st2, eldv,
5742 aud_cntl_st, IBX_ELD_ADDRESS,
5743 hdmiw_hdmiedid))
5744 return;
5745
e0dac65e
WF		 5746 i = I915_READ(aud_cntrl_st2);
5747 i &= ~eldv;
5748 I915_WRITE(aud_cntrl_st2, i);
5749
5750 if (!eld[0])
5751 return;
5752
e0dac65e 5753 i = I915_READ(aud_cntl_st);
1202b4c6 5754 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5755 I915_WRITE(aud_cntl_st, i);
5756
5757 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5758 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5759 for (i = 0; i < len; i++)
5760 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5761
5762 i = I915_READ(aud_cntrl_st2);
5763 i |= eldv;
5764 I915_WRITE(aud_cntrl_st2, i);
5765}
5766
5767void intel_write_eld(struct drm_encoder *encoder,
5768 struct drm_display_mode *mode)
5769{
5770 struct drm_crtc *crtc = encoder->crtc;
5771 struct drm_connector *connector;
5772 struct drm_device *dev = encoder->dev;
5773 struct drm_i915_private *dev_priv = dev->dev_private;
5774
5775 connector = drm_select_eld(encoder, mode);
5776 if (!connector)
5777 return;
5778
5779 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5780 connector->base.id,
5781 drm_get_connector_name(connector),
5782 connector->encoder->base.id,
5783 drm_get_encoder_name(connector->encoder));
5784
5785 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5786
5787 if (dev_priv->display.write_eld)
5788 dev_priv->display.write_eld(connector, crtc);
5789}
5790
79e53945
JB		 5791/** Loads the palette/gamma unit for the CRTC with the prepared values */
5792void intel_crtc_load_lut(struct drm_crtc *crtc)
5793{
5794 struct drm_device *dev = crtc->dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5797 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5798 int i;
5799
5800 /* The clocks have to be on to load the palette. */
aed3f09d 5801 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5802 return;
5803
f2b115e6 5804 /* use legacy palette for Ironlake */
bad720ff 5805 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5806 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5807
79e53945
JB		 5808 for (i = 0; i < 256; i++) {
5809 I915_WRITE(palreg + 4 * i,
5810 (intel_crtc->lut_r[i] << 16) |
5811 (intel_crtc->lut_g[i] << 8) |
5812 intel_crtc->lut_b[i]);
5813 }
5814}
5815
560b85bb
CW		 5816static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5817{
5818 struct drm_device *dev = crtc->dev;
5819 struct drm_i915_private *dev_priv = dev->dev_private;
5820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5821 bool visible = base != 0;
5822 u32 cntl;
5823
5824 if (intel_crtc->cursor_visible == visible)
5825 return;
5826
9db4a9c7 5827 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5828 if (visible) {
5829 /* On these chipsets we can only modify the base whilst
5830 * the cursor is disabled.
5831 */
9db4a9c7 5832 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5833
5834 cntl &= ~(CURSOR_FORMAT_MASK);
5835 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5836 cntl |= CURSOR_ENABLE |
5837 CURSOR_GAMMA_ENABLE |
5838 CURSOR_FORMAT_ARGB;
5839 } else
5840 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5841 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5842
5843 intel_crtc->cursor_visible = visible;
5844}
5845
5846static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5847{
5848 struct drm_device *dev = crtc->dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5851 int pipe = intel_crtc->pipe;
5852 bool visible = base != 0;
5853
5854 if (intel_crtc->cursor_visible != visible) {
548f245b 5855 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5856 if (base) {
5857 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5858 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5859 cntl |= pipe << 28; /* Connect to correct pipe */
5860 } else {
5861 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5862 cntl |= CURSOR_MODE_DISABLE;
5863 }
9db4a9c7 5864 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5865
5866 intel_crtc->cursor_visible = visible;
5867 }
5868 /* and commit changes on next vblank */
9db4a9c7 5869 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5870}
5871
65a21cd6
JB		 5872static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5873{
5874 struct drm_device *dev = crtc->dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5877 int pipe = intel_crtc->pipe;
5878 bool visible = base != 0;
5879
5880 if (intel_crtc->cursor_visible != visible) {
5881 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5882 if (base) {
5883 cntl &= ~CURSOR_MODE;
5884 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5885 } else {
5886 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5887 cntl |= CURSOR_MODE_DISABLE;
5888 }
5889 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5890
5891 intel_crtc->cursor_visible = visible;
5892 }
5893 /* and commit changes on next vblank */
5894 I915_WRITE(CURBASE_IVB(pipe), base);
5895}
5896
cda4b7d3 5897/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5898static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5899 bool on)
cda4b7d3
CW		 5900{
5901 struct drm_device *dev = crtc->dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5904 int pipe = intel_crtc->pipe;
5905 int x = intel_crtc->cursor_x;
5906 int y = intel_crtc->cursor_y;
560b85bb 5907 u32 base, pos;
cda4b7d3
CW		 5908 bool visible;
5909
5910 pos = 0;
5911
6b383a7f 5912 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5913 base = intel_crtc->cursor_addr;
5914 if (x > (int) crtc->fb->width)
5915 base = 0;
5916
5917 if (y > (int) crtc->fb->height)
5918 base = 0;
5919 } else
5920 base = 0;
5921
5922 if (x < 0) {
5923 if (x + intel_crtc->cursor_width < 0)
5924 base = 0;
5925
5926 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5927 x = -x;
5928 }
5929 pos |= x << CURSOR_X_SHIFT;
5930
5931 if (y < 0) {
5932 if (y + intel_crtc->cursor_height < 0)
5933 base = 0;
5934
5935 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5936 y = -y;
5937 }
5938 pos |= y << CURSOR_Y_SHIFT;
5939
5940 visible = base != 0;
560b85bb 5941 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5942 return;
5943
0cd83aa9 5944 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5945 I915_WRITE(CURPOS_IVB(pipe), pos);
5946 ivb_update_cursor(crtc, base);
5947 } else {
5948 I915_WRITE(CURPOS(pipe), pos);
5949 if (IS_845G(dev) || IS_I865G(dev))
5950 i845_update_cursor(crtc, base);
5951 else
5952 i9xx_update_cursor(crtc, base);
5953 }
cda4b7d3
CW		 5954}
5955
79e53945 5956static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5957 struct drm_file *file,
79e53945
JB		 5958 uint32_t handle,
5959 uint32_t width, uint32_t height)
5960{
5961 struct drm_device *dev = crtc->dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5964 struct drm_i915_gem_object *obj;
cda4b7d3 5965 uint32_t addr;
3f8bc370 5966 int ret;
79e53945 5967
79e53945
JB		 5968 /* if we want to turn off the cursor ignore width and height */
5969 if (!handle) {
28c97730 5970 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5971 addr = 0;
05394f39 5972 obj = NULL;
5004417d 5973 mutex_lock(&dev->struct_mutex);
3f8bc370 5974 goto finish;
79e53945
JB		 5975 }
5976
5977 /* Currently we only support 64x64 cursors */
5978 if (width != 64 || height != 64) {
5979 DRM_ERROR("we currently only support 64x64 cursors\n");
5980 return -EINVAL;
5981 }
5982
05394f39 5983 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5984 if (&obj->base == NULL)
79e53945
JB		 5985 return -ENOENT;
5986
05394f39 5987 if (obj->base.size < width * height * 4) {
79e53945 5988 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5989 ret = -ENOMEM;
5990 goto fail;
79e53945
JB		 5991 }
5992
71acb5eb 5993 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5994 mutex_lock(&dev->struct_mutex);
b295d1b6 5995 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5996 if (obj->tiling_mode) {
5997 DRM_ERROR("cursor cannot be tiled\n");
5998 ret = -EINVAL;
5999 goto fail_locked;
6000 }
6001
2da3b9b9 6002 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6003 if (ret) {
6004 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6005 goto fail_locked;
e7b526bb
CW		 6006 }
6007
d9e86c0e
CW		 6008 ret = i915_gem_object_put_fence(obj);
6009 if (ret) {
2da3b9b9 6010 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6011 goto fail_unpin;
6012 }
6013
05394f39 6014 addr = obj->gtt_offset;
71acb5eb 6015 } else {
6eeefaf3 6016 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6017 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6018 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6019 align);
71acb5eb
DA		 6020 if (ret) {
6021 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6022 goto fail_locked;
71acb5eb 6023 }
05394f39 6024 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6025 }
6026
a6c45cf0 6027 if (IS_GEN2(dev))
14b60391
JB		 6028 I915_WRITE(CURSIZE, (height << 12) | width);
6029
3f8bc370 6030 finish:
3f8bc370 6031 if (intel_crtc->cursor_bo) {
b295d1b6 6032 if (dev_priv->info->cursor_needs_physical) {
05394f39 6033 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6034 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6035 } else
6036 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6037 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6038 }
80824003 6039
7f9872e0 6040 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6041
6042 intel_crtc->cursor_addr = addr;
05394f39 6043 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6044 intel_crtc->cursor_width = width;
6045 intel_crtc->cursor_height = height;
6046
6b383a7f 6047 intel_crtc_update_cursor(crtc, true);
3f8bc370 6048
79e53945 6049 return 0;
e7b526bb 6050fail_unpin:
05394f39 6051 i915_gem_object_unpin(obj);
7f9872e0 6052fail_locked:
34b8686e 6053 mutex_unlock(&dev->struct_mutex);
bc9025bd 6054fail:
05394f39 6055 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6056 return ret;
79e53945
JB		 6057}
6058
6059static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6060{
79e53945 6061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6062
cda4b7d3
CW		 6063 intel_crtc->cursor_x = x;
6064 intel_crtc->cursor_y = y;
652c393a 6065
6b383a7f 6066 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6067
6068 return 0;
6069}
6070
6071/** Sets the color ramps on behalf of RandR */
6072void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6073 u16 blue, int regno)
6074{
6075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076
6077 intel_crtc->lut_r[regno] = red >> 8;
6078 intel_crtc->lut_g[regno] = green >> 8;
6079 intel_crtc->lut_b[regno] = blue >> 8;
6080}
6081
b8c00ac5
DA		 6082void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6083 u16 *blue, int regno)
6084{
6085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086
6087 *red = intel_crtc->lut_r[regno] << 8;
6088 *green = intel_crtc->lut_g[regno] << 8;
6089 *blue = intel_crtc->lut_b[regno] << 8;
6090}
6091
79e53945 6092static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6093 u16 *blue, uint32_t start, uint32_t size)
79e53945 6094{
7203425a 6095 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6097
7203425a 6098 for (i = start; i < end; i++) {
79e53945
JB		 6099 intel_crtc->lut_r[i] = red[i] >> 8;
6100 intel_crtc->lut_g[i] = green[i] >> 8;
6101 intel_crtc->lut_b[i] = blue[i] >> 8;
6102 }
6103
6104 intel_crtc_load_lut(crtc);
6105}
6106
6107/**
6108 * Get a pipe with a simple mode set on it for doing load-based monitor
6109 * detection.
6110 *
6111 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6112 * its requirements. The pipe will be connected to no other encoders.
79e53945 6113 *
c751ce4f 6114 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6115 * configured for it. In the future, it could choose to temporarily disable
6116 * some outputs to free up a pipe for its use.
6117 *
6118 * \return crtc, or NULL if no pipes are available.
6119 */
6120
6121/* VESA 640x480x72Hz mode to set on the pipe */
6122static struct drm_display_mode load_detect_mode = {
6123 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6124 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6125};
6126
d2dff872
CW		 6127static struct drm_framebuffer *
6128intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6129 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6130 struct drm_i915_gem_object *obj)
6131{
6132 struct intel_framebuffer *intel_fb;
6133 int ret;
6134
6135 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6136 if (!intel_fb) {
6137 drm_gem_object_unreference_unlocked(&obj->base);
6138 return ERR_PTR(-ENOMEM);
6139 }
6140
6141 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6142 if (ret) {
6143 drm_gem_object_unreference_unlocked(&obj->base);
6144 kfree(intel_fb);
6145 return ERR_PTR(ret);
6146 }
6147
6148 return &intel_fb->base;
6149}
6150
6151static u32
6152intel_framebuffer_pitch_for_width(int width, int bpp)
6153{
6154 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6155 return ALIGN(pitch, 64);
6156}
6157
6158static u32
6159intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6160{
6161 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6162 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6163}
6164
6165static struct drm_framebuffer *
6166intel_framebuffer_create_for_mode(struct drm_device *dev,
6167 struct drm_display_mode *mode,
6168 int depth, int bpp)
6169{
6170 struct drm_i915_gem_object *obj;
0fed39bd 6171 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6172
6173 obj = i915_gem_alloc_object(dev,
6174 intel_framebuffer_size_for_mode(mode, bpp));
6175 if (obj == NULL)
6176 return ERR_PTR(-ENOMEM);
6177
6178 mode_cmd.width = mode->hdisplay;
6179 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6180 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6181 bpp);
5ca0c34a 6182 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6183
6184 return intel_framebuffer_create(dev, &mode_cmd, obj);
6185}
6186
6187static struct drm_framebuffer *
6188mode_fits_in_fbdev(struct drm_device *dev,
6189 struct drm_display_mode *mode)
6190{
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct drm_i915_gem_object *obj;
6193 struct drm_framebuffer *fb;
6194
6195 if (dev_priv->fbdev == NULL)
6196 return NULL;
6197
6198 obj = dev_priv->fbdev->ifb.obj;
6199 if (obj == NULL)
6200 return NULL;
6201
6202 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6203 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6204 fb->bits_per_pixel))
d2dff872
CW		 6205 return NULL;
6206
01f2c773 6207 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6208 return NULL;
6209
6210 return fb;
6211}
6212
d2434ab7 6213bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6214 struct drm_display_mode *mode,
8261b191 6215 struct intel_load_detect_pipe *old)
79e53945
JB		 6216{
6217 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6218 struct intel_encoder *intel_encoder =
6219 intel_attached_encoder(connector);
79e53945 6220 struct drm_crtc *possible_crtc;
4ef69c7a 6221 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6222 struct drm_crtc *crtc = NULL;
6223 struct drm_device *dev = encoder->dev;
94352cf9 6224 struct drm_framebuffer *fb;
79e53945
JB		 6225 int i = -1;
6226
d2dff872
CW		 6227 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6228 connector->base.id, drm_get_connector_name(connector),
6229 encoder->base.id, drm_get_encoder_name(encoder));
6230
79e53945
JB		 6231 /*
6232 * Algorithm gets a little messy:
7a5e4805 6233 *
79e53945
JB		 6234 * - if the connector already has an assigned crtc, use it (but make
6235 * sure it's on first)
7a5e4805 6236 *
79e53945
JB		 6237 * - try to find the first unused crtc that can drive this connector,
6238 * and use that if we find one
79e53945
JB		 6239 */
6240
6241 /* See if we already have a CRTC for this connector */
6242 if (encoder->crtc) {
6243 crtc = encoder->crtc;
8261b191 6244
24218aac 6245 old->dpms_mode = connector->dpms;
8261b191
CW		 6246 old->load_detect_temp = false;
6247
6248 /* Make sure the crtc and connector are running */
24218aac
DV		 6249 if (connector->dpms != DRM_MODE_DPMS_ON)
6250 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6251
7173188d 6252 return true;
79e53945
JB		 6253 }
6254
6255 /* Find an unused one (if possible) */
6256 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6257 i++;
6258 if (!(encoder->possible_crtcs & (1 << i)))
6259 continue;
6260 if (!possible_crtc->enabled) {
6261 crtc = possible_crtc;
6262 break;
6263 }
79e53945
JB		 6264 }
6265
6266 /*
6267 * If we didn't find an unused CRTC, don't use any.
6268 */
6269 if (!crtc) {
7173188d
CW		 6270 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6271 return false;
79e53945
JB		 6272 }
6273
fc303101
DV		 6274 intel_encoder->new_crtc = to_intel_crtc(crtc);
6275 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6276
6277 intel_crtc = to_intel_crtc(crtc);
24218aac 6278 old->dpms_mode = connector->dpms;
8261b191 6279 old->load_detect_temp = true;
d2dff872 6280 old->release_fb = NULL;
79e53945 6281
6492711d
CW		 6282 if (!mode)
6283 mode = &load_detect_mode;
79e53945 6284
d2dff872
CW		 6285 /* We need a framebuffer large enough to accommodate all accesses
6286 * that the plane may generate whilst we perform load detection.
6287 * We can not rely on the fbcon either being present (we get called
6288 * during its initialisation to detect all boot displays, or it may
6289 * not even exist) or that it is large enough to satisfy the
6290 * requested mode.
6291 */
94352cf9
DV		 6292 fb = mode_fits_in_fbdev(dev, mode);
6293 if (fb == NULL) {
d2dff872 6294 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6295 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6296 old->release_fb = fb;
d2dff872
CW		 6297 } else
6298 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6299 if (IS_ERR(fb)) {
d2dff872 6300 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6301 return false;
79e53945 6302 }
79e53945 6303
94352cf9 6304 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6305 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6306 if (old->release_fb)
6307 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6308 return false;
79e53945 6309 }
7173188d 6310
79e53945 6311 /* let the connector get through one full cycle before testing */
9d0498a2 6312 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6313 return true;
79e53945
JB		 6314}
6315
d2434ab7 6316void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6317 struct intel_load_detect_pipe *old)
79e53945 6318{
d2434ab7
DV		 6319 struct intel_encoder *intel_encoder =
6320 intel_attached_encoder(connector);
4ef69c7a 6321 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6322
d2dff872
CW		 6323 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6324 connector->base.id, drm_get_connector_name(connector),
6325 encoder->base.id, drm_get_encoder_name(encoder));
6326
8261b191 6327 if (old->load_detect_temp) {
fc303101
DV		 6328 struct drm_crtc *crtc = encoder->crtc;
6329
6330 to_intel_connector(connector)->new_encoder = NULL;
6331 intel_encoder->new_crtc = NULL;
6332 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6333
6334 if (old->release_fb)
6335 old->release_fb->funcs->destroy(old->release_fb);
6336
0622a53c 6337 return;
79e53945
JB		 6338 }
6339
c751ce4f 6340 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6341 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6342 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6343}
6344
6345/* Returns the clock of the currently programmed mode of the given pipe. */
6346static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6347{
6348 struct drm_i915_private *dev_priv = dev->dev_private;
6349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6350 int pipe = intel_crtc->pipe;
548f245b 6351 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6352 u32 fp;
6353 intel_clock_t clock;
6354
6355 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6356 fp = I915_READ(FP0(pipe));
79e53945 6357 else
39adb7a5 6358 fp = I915_READ(FP1(pipe));
79e53945
JB		 6359
6360 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6361 if (IS_PINEVIEW(dev)) {
6362 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6363 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6364 } else {
6365 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6366 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6367 }
6368
a6c45cf0 6369 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6370 if (IS_PINEVIEW(dev))
6371 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6372 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6373 else
6374 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6375 DPLL_FPA01_P1_POST_DIV_SHIFT);
6376
6377 switch (dpll & DPLL_MODE_MASK) {
6378 case DPLLB_MODE_DAC_SERIAL:
6379 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6380 5 : 10;
6381 break;
6382 case DPLLB_MODE_LVDS:
6383 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6384 7 : 14;
6385 break;
6386 default:
28c97730 6387 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6388 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6389 return 0;
6390 }
6391
6392 /* XXX: Handle the 100Mhz refclk */
2177832f 6393 intel_clock(dev, 96000, &clock);
79e53945
JB		 6394 } else {
6395 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6396
6397 if (is_lvds) {
6398 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6399 DPLL_FPA01_P1_POST_DIV_SHIFT);
6400 clock.p2 = 14;
6401
6402 if ((dpll & PLL_REF_INPUT_MASK) ==
6403 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6404 /* XXX: might not be 66MHz */
2177832f 6405 intel_clock(dev, 66000, &clock);
79e53945 6406 } else
2177832f 6407 intel_clock(dev, 48000, &clock);
79e53945
JB		 6408 } else {
6409 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6410 clock.p1 = 2;
6411 else {
6412 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6413 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6414 }
6415 if (dpll & PLL_P2_DIVIDE_BY_4)
6416 clock.p2 = 4;
6417 else
6418 clock.p2 = 2;
6419
2177832f 6420 intel_clock(dev, 48000, &clock);
79e53945
JB		 6421 }
6422 }
6423
6424 /* XXX: It would be nice to validate the clocks, but we can't reuse
6425 * i830PllIsValid() because it relies on the xf86_config connector
6426 * configuration being accurate, which it isn't necessarily.
6427 */
6428
6429 return clock.dot;
6430}
6431
6432/** Returns the currently programmed mode of the given pipe. */
6433struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6434 struct drm_crtc *crtc)
6435{
548f245b 6436 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6438 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6439 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6440 int htot = I915_READ(HTOTAL(cpu_transcoder));
6441 int hsync = I915_READ(HSYNC(cpu_transcoder));
6442 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6443 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6444
6445 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6446 if (!mode)
6447 return NULL;
6448
6449 mode->clock = intel_crtc_clock_get(dev, crtc);
6450 mode->hdisplay = (htot & 0xffff) + 1;
6451 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6452 mode->hsync_start = (hsync & 0xffff) + 1;
6453 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6454 mode->vdisplay = (vtot & 0xffff) + 1;
6455 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6456 mode->vsync_start = (vsync & 0xffff) + 1;
6457 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6458
6459 drm_mode_set_name(mode);
79e53945
JB		 6460
6461 return mode;
6462}
6463
3dec0095 6464static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6465{
6466 struct drm_device *dev = crtc->dev;
6467 drm_i915_private_t *dev_priv = dev->dev_private;
6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6470 int dpll_reg = DPLL(pipe);
6471 int dpll;
652c393a 6472
bad720ff 6473 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6474 return;
6475
6476 if (!dev_priv->lvds_downclock_avail)
6477 return;
6478
dbdc6479 6479 dpll = I915_READ(dpll_reg);
652c393a 6480 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6481 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6482
8ac5a6d5 6483 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6484
6485 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6486 I915_WRITE(dpll_reg, dpll);
9d0498a2 6487 intel_wait_for_vblank(dev, pipe);
dbdc6479 6488
652c393a
JB		 6489 dpll = I915_READ(dpll_reg);
6490 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6491 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6492 }
652c393a
JB		 6493}
6494
6495static void intel_decrease_pllclock(struct drm_crtc *crtc)
6496{
6497 struct drm_device *dev = crtc->dev;
6498 drm_i915_private_t *dev_priv = dev->dev_private;
6499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6500
bad720ff 6501 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6502 return;
6503
6504 if (!dev_priv->lvds_downclock_avail)
6505 return;
6506
6507 /*
6508 * Since this is called by a timer, we should never get here in
6509 * the manual case.
6510 */
6511 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6512 int pipe = intel_crtc->pipe;
6513 int dpll_reg = DPLL(pipe);
6514 int dpll;
f6e5b160 6515
44d98a61 6516 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6517
8ac5a6d5 6518 assert_panel_unlocked(dev_priv, pipe);
652c393a 6519
dc257cf1 6520 dpll = I915_READ(dpll_reg);
652c393a
JB		 6521 dpll |= DISPLAY_RATE_SELECT_FPA1;
6522 I915_WRITE(dpll_reg, dpll);
9d0498a2 6523 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6524 dpll = I915_READ(dpll_reg);
6525 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6526 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6527 }
6528
6529}
6530
f047e395
CW		 6531void intel_mark_busy(struct drm_device *dev)
6532{
f047e395
CW		 6533 i915_update_gfx_val(dev->dev_private);
6534}
6535
6536void intel_mark_idle(struct drm_device *dev)
652c393a 6537{
f047e395
CW		 6538}
6539
6540void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6541{
6542 struct drm_device *dev = obj->base.dev;
652c393a 6543 struct drm_crtc *crtc;
652c393a
JB		 6544
6545 if (!i915_powersave)
6546 return;
6547
652c393a 6548 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6549 if (!crtc->fb)
6550 continue;
6551
f047e395
CW		 6552 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6553 intel_increase_pllclock(crtc);
652c393a 6554 }
652c393a
JB		 6555}
6556
f047e395 6557void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6558{
f047e395
CW		 6559 struct drm_device *dev = obj->base.dev;
6560 struct drm_crtc *crtc;
652c393a 6561
f047e395 6562 if (!i915_powersave)
acb87dfb
CW		 6563 return;
6564
652c393a
JB		 6565 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6566 if (!crtc->fb)
6567 continue;
6568
f047e395
CW		 6569 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6570 intel_decrease_pllclock(crtc);
652c393a
JB		 6571 }
6572}
6573
79e53945
JB		 6574static void intel_crtc_destroy(struct drm_crtc *crtc)
6575{
6576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6577 struct drm_device *dev = crtc->dev;
6578 struct intel_unpin_work *work;
6579 unsigned long flags;
6580
6581 spin_lock_irqsave(&dev->event_lock, flags);
6582 work = intel_crtc->unpin_work;
6583 intel_crtc->unpin_work = NULL;
6584 spin_unlock_irqrestore(&dev->event_lock, flags);
6585
6586 if (work) {
6587 cancel_work_sync(&work->work);
6588 kfree(work);
6589 }
79e53945
JB		 6590
6591 drm_crtc_cleanup(crtc);
67e77c5a 6592
79e53945
JB		 6593 kfree(intel_crtc);
6594}
6595
6b95a207
KH		 6596static void intel_unpin_work_fn(struct work_struct *__work)
6597{
6598 struct intel_unpin_work *work =
6599 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6600 struct drm_device *dev = work->crtc->dev;
6b95a207 6601
b4a98e57 6602 mutex_lock(&dev->struct_mutex);
1690e1eb 6603 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6604 drm_gem_object_unreference(&work->pending_flip_obj->base);
6605 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6606
b4a98e57
CW		 6607 intel_update_fbc(dev);
6608 mutex_unlock(&dev->struct_mutex);
6609
6610 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6611 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6612
6b95a207
KH		 6613 kfree(work);
6614}
6615
1afe3e9d 6616static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6617 struct drm_crtc *crtc)
6b95a207
KH		 6618{
6619 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6621 struct intel_unpin_work *work;
05394f39 6622 struct drm_i915_gem_object *obj;
6b95a207
KH		 6623 unsigned long flags;
6624
6625 /* Ignore early vblank irqs */
6626 if (intel_crtc == NULL)
6627 return;
6628
6629 spin_lock_irqsave(&dev->event_lock, flags);
6630 work = intel_crtc->unpin_work;
6631 if (work == NULL || !work->pending) {
6632 spin_unlock_irqrestore(&dev->event_lock, flags);
6633 return;
6634 }
6635
6636 intel_crtc->unpin_work = NULL;
6b95a207 6637
45a066eb
RC		 6638 if (work->event)
6639 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6640
0af7e4df
MK		 6641 drm_vblank_put(dev, intel_crtc->pipe);
6642
6b95a207
KH		 6643 spin_unlock_irqrestore(&dev->event_lock, flags);
6644
05394f39 6645 obj = work->old_fb_obj;
d9e86c0e 6646
5bb61643 6647 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6648
6649 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6650
6651 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6652}
6653
1afe3e9d
JB		 6654void intel_finish_page_flip(struct drm_device *dev, int pipe)
6655{
6656 drm_i915_private_t *dev_priv = dev->dev_private;
6657 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6658
49b14a5c 6659 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6660}
6661
6662void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6663{
6664 drm_i915_private_t *dev_priv = dev->dev_private;
6665 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6666
49b14a5c 6667 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6668}
6669
6b95a207
KH		 6670void intel_prepare_page_flip(struct drm_device *dev, int plane)
6671{
6672 drm_i915_private_t *dev_priv = dev->dev_private;
6673 struct intel_crtc *intel_crtc =
6674 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6675 unsigned long flags;
6676
6677 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6678 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6679 if ((++intel_crtc->unpin_work->pending) > 1)
6680 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6681 } else {
6682 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6683 }
6b95a207
KH		 6684 spin_unlock_irqrestore(&dev->event_lock, flags);
6685}
6686
8c9f3aaf
JB		 6687static int intel_gen2_queue_flip(struct drm_device *dev,
6688 struct drm_crtc *crtc,
6689 struct drm_framebuffer *fb,
6690 struct drm_i915_gem_object *obj)
6691{
6692 struct drm_i915_private *dev_priv = dev->dev_private;
6693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6694 u32 flip_mask;
6d90c952 6695 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6696 int ret;
6697
6d90c952 6698 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6699 if (ret)
83d4092b 6700 goto err;
8c9f3aaf 6701
6d90c952 6702 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6703 if (ret)
83d4092b 6704 goto err_unpin;
8c9f3aaf
JB		 6705
6706 /* Can't queue multiple flips, so wait for the previous
6707 * one to finish before executing the next.
6708 */
6709 if (intel_crtc->plane)
6710 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6711 else
6712 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6713 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6714 intel_ring_emit(ring, MI_NOOP);
6715 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6716 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6717 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6718 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6719 intel_ring_emit(ring, 0); /* aux display base address, unused */
6720 intel_ring_advance(ring);
83d4092b
CW		 6721 return 0;
6722
6723err_unpin:
6724 intel_unpin_fb_obj(obj);
6725err:
8c9f3aaf
JB		 6726 return ret;
6727}
6728
6729static int intel_gen3_queue_flip(struct drm_device *dev,
6730 struct drm_crtc *crtc,
6731 struct drm_framebuffer *fb,
6732 struct drm_i915_gem_object *obj)
6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6736 u32 flip_mask;
6d90c952 6737 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6738 int ret;
6739
6d90c952 6740 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6741 if (ret)
83d4092b 6742 goto err;
8c9f3aaf 6743
6d90c952 6744 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6745 if (ret)
83d4092b 6746 goto err_unpin;
8c9f3aaf
JB		 6747
6748 if (intel_crtc->plane)
6749 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6750 else
6751 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6752 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6753 intel_ring_emit(ring, MI_NOOP);
6754 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6755 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6756 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6757 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6758 intel_ring_emit(ring, MI_NOOP);
6759
6760 intel_ring_advance(ring);
83d4092b
CW		 6761 return 0;
6762
6763err_unpin:
6764 intel_unpin_fb_obj(obj);
6765err:
8c9f3aaf
JB		 6766 return ret;
6767}
6768
6769static int intel_gen4_queue_flip(struct drm_device *dev,
6770 struct drm_crtc *crtc,
6771 struct drm_framebuffer *fb,
6772 struct drm_i915_gem_object *obj)
6773{
6774 struct drm_i915_private *dev_priv = dev->dev_private;
6775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6776 uint32_t pf, pipesrc;
6d90c952 6777 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6778 int ret;
6779
6d90c952 6780 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6781 if (ret)
83d4092b 6782 goto err;
8c9f3aaf 6783
6d90c952 6784 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6785 if (ret)
83d4092b 6786 goto err_unpin;
8c9f3aaf
JB		 6787
6788 /* i965+ uses the linear or tiled offsets from the
6789 * Display Registers (which do not change across a page-flip)
6790 * so we need only reprogram the base address.
6791 */
6d90c952
DV		 6792 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6793 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6794 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6795 intel_ring_emit(ring,
6796 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6797 obj->tiling_mode);
8c9f3aaf
JB		 6798
6799 /* XXX Enabling the panel-fitter across page-flip is so far
6800 * untested on non-native modes, so ignore it for now.
6801 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6802 */
6803 pf = 0;
6804 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6805 intel_ring_emit(ring, pf | pipesrc);
6806 intel_ring_advance(ring);
83d4092b
CW		 6807 return 0;
6808
6809err_unpin:
6810 intel_unpin_fb_obj(obj);
6811err:
8c9f3aaf
JB		 6812 return ret;
6813}
6814
6815static int intel_gen6_queue_flip(struct drm_device *dev,
6816 struct drm_crtc *crtc,
6817 struct drm_framebuffer *fb,
6818 struct drm_i915_gem_object *obj)
6819{
6820 struct drm_i915_private *dev_priv = dev->dev_private;
6821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6822 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6823 uint32_t pf, pipesrc;
6824 int ret;
6825
6d90c952 6826 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6827 if (ret)
83d4092b 6828 goto err;
8c9f3aaf 6829
6d90c952 6830 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6831 if (ret)
83d4092b 6832 goto err_unpin;
8c9f3aaf 6833
6d90c952
DV		 6834 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6835 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6836 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6837 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6838
dc257cf1
DV		 6839 /* Contrary to the suggestions in the documentation,
6840 * "Enable Panel Fitter" does not seem to be required when page
6841 * flipping with a non-native mode, and worse causes a normal
6842 * modeset to fail.
6843 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6844 */
6845 pf = 0;
8c9f3aaf 6846 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6847 intel_ring_emit(ring, pf | pipesrc);
6848 intel_ring_advance(ring);
83d4092b
CW		 6849 return 0;
6850
6851err_unpin:
6852 intel_unpin_fb_obj(obj);
6853err:
8c9f3aaf
JB		 6854 return ret;
6855}
6856
7c9017e5
JB		 6857/*
6858 * On gen7 we currently use the blit ring because (in early silicon at least)
6859 * the render ring doesn't give us interrpts for page flip completion, which
6860 * means clients will hang after the first flip is queued. Fortunately the
6861 * blit ring generates interrupts properly, so use it instead.
6862 */
6863static int intel_gen7_queue_flip(struct drm_device *dev,
6864 struct drm_crtc *crtc,
6865 struct drm_framebuffer *fb,
6866 struct drm_i915_gem_object *obj)
6867{
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6871 uint32_t plane_bit = 0;
7c9017e5
JB		 6872 int ret;
6873
6874 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6875 if (ret)
83d4092b 6876 goto err;
7c9017e5 6877
cb05d8de
DV		 6878 switch(intel_crtc->plane) {
6879 case PLANE_A:
6880 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6881 break;
6882 case PLANE_B:
6883 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6884 break;
6885 case PLANE_C:
6886 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6887 break;
6888 default:
6889 WARN_ONCE(1, "unknown plane in flip command\n");
6890 ret = -ENODEV;
ab3951eb 6891 goto err_unpin;
cb05d8de
DV		 6892 }
6893
7c9017e5
JB		 6894 ret = intel_ring_begin(ring, 4);
6895 if (ret)
83d4092b 6896 goto err_unpin;
7c9017e5 6897
cb05d8de 6898 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6899 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6900 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6901 intel_ring_emit(ring, (MI_NOOP));
6902 intel_ring_advance(ring);
83d4092b
CW		 6903 return 0;
6904
6905err_unpin:
6906 intel_unpin_fb_obj(obj);
6907err:
7c9017e5
JB		 6908 return ret;
6909}
6910
8c9f3aaf
JB		 6911static int intel_default_queue_flip(struct drm_device *dev,
6912 struct drm_crtc *crtc,
6913 struct drm_framebuffer *fb,
6914 struct drm_i915_gem_object *obj)
6915{
6916 return -ENODEV;
6917}
6918
6b95a207
KH		 6919static int intel_crtc_page_flip(struct drm_crtc *crtc,
6920 struct drm_framebuffer *fb,
6921 struct drm_pending_vblank_event *event)
6922{
6923 struct drm_device *dev = crtc->dev;
6924 struct drm_i915_private *dev_priv = dev->dev_private;
6925 struct intel_framebuffer *intel_fb;
05394f39 6926 struct drm_i915_gem_object *obj;
6b95a207
KH		 6927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6928 struct intel_unpin_work *work;
8c9f3aaf 6929 unsigned long flags;
52e68630 6930 int ret;
6b95a207 6931
e6a595d2
VS		 6932 /* Can't change pixel format via MI display flips. */
6933 if (fb->pixel_format != crtc->fb->pixel_format)
6934 return -EINVAL;
6935
6936 /*
6937 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6938 * Note that pitch changes could also affect these register.
6939 */
6940 if (INTEL_INFO(dev)->gen > 3 &&
6941 (fb->offsets[0] != crtc->fb->offsets[0] ||
6942 fb->pitches[0] != crtc->fb->pitches[0]))
6943 return -EINVAL;
6944
6b95a207
KH		 6945 work = kzalloc(sizeof *work, GFP_KERNEL);
6946 if (work == NULL)
6947 return -ENOMEM;
6948
6b95a207 6949 work->event = event;
b4a98e57 6950 work->crtc = crtc;
6b95a207 6951 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6952 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6953 INIT_WORK(&work->work, intel_unpin_work_fn);
6954
7317c75e
JB		 6955 ret = drm_vblank_get(dev, intel_crtc->pipe);
6956 if (ret)
6957 goto free_work;
6958
6b95a207
KH		 6959 /* We borrow the event spin lock for protecting unpin_work */
6960 spin_lock_irqsave(&dev->event_lock, flags);
6961 if (intel_crtc->unpin_work) {
6962 spin_unlock_irqrestore(&dev->event_lock, flags);
6963 kfree(work);
7317c75e 6964 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6965
6966 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6967 return -EBUSY;
6968 }
6969 intel_crtc->unpin_work = work;
6970 spin_unlock_irqrestore(&dev->event_lock, flags);
6971
6972 intel_fb = to_intel_framebuffer(fb);
6973 obj = intel_fb->obj;
6974
b4a98e57
CW		 6975 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
6976 flush_workqueue(dev_priv->wq);
6977
79158103
CW		 6978 ret = i915_mutex_lock_interruptible(dev);
6979 if (ret)
6980 goto cleanup;
6b95a207 6981
75dfca80 6982 /* Reference the objects for the scheduled work. */
05394f39
CW		 6983 drm_gem_object_reference(&work->old_fb_obj->base);
6984 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6985
6986 crtc->fb = fb;
96b099fd 6987
e1f99ce6 6988 work->pending_flip_obj = obj;
e1f99ce6 6989
4e5359cd
SF		 6990 work->enable_stall_check = true;
6991
b4a98e57 6992 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 6993
8c9f3aaf
JB		 6994 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6995 if (ret)
6996 goto cleanup_pending;
6b95a207 6997
7782de3b 6998 intel_disable_fbc(dev);
f047e395 6999 intel_mark_fb_busy(obj);
6b95a207
KH		 7000 mutex_unlock(&dev->struct_mutex);
7001
e5510fac
JB		 7002 trace_i915_flip_request(intel_crtc->plane, obj);
7003
6b95a207 7004 return 0;
96b099fd 7005
8c9f3aaf 7006cleanup_pending:
b4a98e57 7007 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7008 drm_gem_object_unreference(&work->old_fb_obj->base);
7009 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7010 mutex_unlock(&dev->struct_mutex);
7011
79158103 7012cleanup:
96b099fd
CW		 7013 spin_lock_irqsave(&dev->event_lock, flags);
7014 intel_crtc->unpin_work = NULL;
7015 spin_unlock_irqrestore(&dev->event_lock, flags);
7016
7317c75e
JB		 7017 drm_vblank_put(dev, intel_crtc->pipe);
7018free_work:
96b099fd
CW		 7019 kfree(work);
7020
7021 return ret;
6b95a207
KH		 7022}
7023
f6e5b160 7024static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7025 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7026 .load_lut = intel_crtc_load_lut,
976f8a20 7027 .disable = intel_crtc_noop,
f6e5b160
CW		 7028};
7029
6ed0f796 7030bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7031{
6ed0f796
DV		 7032 struct intel_encoder *other_encoder;
7033 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7034
6ed0f796
DV		 7035 if (WARN_ON(!crtc))
7036 return false;
7037
7038 list_for_each_entry(other_encoder,
7039 &crtc->dev->mode_config.encoder_list,
7040 base.head) {
7041
7042 if (&other_encoder->new_crtc->base != crtc ||
7043 encoder == other_encoder)
7044 continue;
7045 else
7046 return true;
f47166d2
CW		 7047 }
7048
6ed0f796
DV		 7049 return false;
7050}
47f1c6c9 7051
50f56119
DV		 7052static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7053 struct drm_crtc *crtc)
7054{
7055 struct drm_device *dev;
7056 struct drm_crtc *tmp;
7057 int crtc_mask = 1;
47f1c6c9 7058
50f56119 7059 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7060
50f56119 7061 dev = crtc->dev;
47f1c6c9 7062
50f56119
DV		 7063 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7064 if (tmp == crtc)
7065 break;
7066 crtc_mask <<= 1;
7067 }
47f1c6c9 7068
50f56119
DV		 7069 if (encoder->possible_crtcs & crtc_mask)
7070 return true;
7071 return false;
47f1c6c9 7072}
79e53945 7073
9a935856
DV		 7074/**
7075 * intel_modeset_update_staged_output_state
7076 *
7077 * Updates the staged output configuration state, e.g. after we've read out the
7078 * current hw state.
7079 */
7080static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7081{
9a935856
DV		 7082 struct intel_encoder *encoder;
7083 struct intel_connector *connector;
f6e5b160 7084
9a935856
DV		 7085 list_for_each_entry(connector, &dev->mode_config.connector_list,
7086 base.head) {
7087 connector->new_encoder =
7088 to_intel_encoder(connector->base.encoder);
7089 }
f6e5b160 7090
9a935856
DV		 7091 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7092 base.head) {
7093 encoder->new_crtc =
7094 to_intel_crtc(encoder->base.crtc);
7095 }
f6e5b160
CW		 7096}
7097
9a935856
DV		 7098/**
7099 * intel_modeset_commit_output_state
7100 *
7101 * This function copies the stage display pipe configuration to the real one.
7102 */
7103static void intel_modeset_commit_output_state(struct drm_device *dev)
7104{
7105 struct intel_encoder *encoder;
7106 struct intel_connector *connector;
f6e5b160 7107
9a935856
DV		 7108 list_for_each_entry(connector, &dev->mode_config.connector_list,
7109 base.head) {
7110 connector->base.encoder = &connector->new_encoder->base;
7111 }
f6e5b160 7112
9a935856
DV		 7113 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7114 base.head) {
7115 encoder->base.crtc = &encoder->new_crtc->base;
7116 }
7117}
7118
7758a113
DV		 7119static struct drm_display_mode *
7120intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7121 struct drm_display_mode *mode)
ee7b9f93 7122{
7758a113
DV		 7123 struct drm_device *dev = crtc->dev;
7124 struct drm_display_mode *adjusted_mode;
7125 struct drm_encoder_helper_funcs *encoder_funcs;
7126 struct intel_encoder *encoder;
ee7b9f93 7127
7758a113
DV		 7128 adjusted_mode = drm_mode_duplicate(dev, mode);
7129 if (!adjusted_mode)
7130 return ERR_PTR(-ENOMEM);
7131
7132 /* Pass our mode to the connectors and the CRTC to give them a chance to
7133 * adjust it according to limitations or connector properties, and also
7134 * a chance to reject the mode entirely.
47f1c6c9 7135 */
7758a113
DV		 7136 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7137 base.head) {
47f1c6c9 7138
7758a113
DV		 7139 if (&encoder->new_crtc->base != crtc)
7140 continue;
7141 encoder_funcs = encoder->base.helper_private;
7142 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7143 adjusted_mode))) {
7144 DRM_DEBUG_KMS("Encoder fixup failed\n");
7145 goto fail;
7146 }
ee7b9f93 7147 }
47f1c6c9 7148
7758a113
DV		 7149 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7150 DRM_DEBUG_KMS("CRTC fixup failed\n");
7151 goto fail;
ee7b9f93 7152 }
7758a113 7153 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7154
7758a113
DV		 7155 return adjusted_mode;
7156fail:
7157 drm_mode_destroy(dev, adjusted_mode);
7158 return ERR_PTR(-EINVAL);
ee7b9f93 7159}
47f1c6c9 7160
e2e1ed41
DV		 7161/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7162 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7163static void
7164intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7165 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7166{
7167 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7168 struct drm_device *dev = crtc->dev;
7169 struct intel_encoder *encoder;
7170 struct intel_connector *connector;
7171 struct drm_crtc *tmp_crtc;
79e53945 7172
e2e1ed41 7173 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7174
e2e1ed41
DV		 7175 /* Check which crtcs have changed outputs connected to them, these need
7176 * to be part of the prepare_pipes mask. We don't (yet) support global
7177 * modeset across multiple crtcs, so modeset_pipes will only have one
7178 * bit set at most. */
7179 list_for_each_entry(connector, &dev->mode_config.connector_list,
7180 base.head) {
7181 if (connector->base.encoder == &connector->new_encoder->base)
7182 continue;
79e53945 7183
e2e1ed41
DV		 7184 if (connector->base.encoder) {
7185 tmp_crtc = connector->base.encoder->crtc;
7186
7187 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7188 }
7189
7190 if (connector->new_encoder)
7191 *prepare_pipes |=
7192 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7193 }
7194
e2e1ed41
DV		 7195 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7196 base.head) {
7197 if (encoder->base.crtc == &encoder->new_crtc->base)
7198 continue;
7199
7200 if (encoder->base.crtc) {
7201 tmp_crtc = encoder->base.crtc;
7202
7203 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7204 }
7205
7206 if (encoder->new_crtc)
7207 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7208 }
7209
e2e1ed41
DV		 7210 /* Check for any pipes that will be fully disabled ... */
7211 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7212 base.head) {
7213 bool used = false;
22fd0fab 7214
e2e1ed41
DV		 7215 /* Don't try to disable disabled crtcs. */
7216 if (!intel_crtc->base.enabled)
7217 continue;
7e7d76c3 7218
e2e1ed41
DV		 7219 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7220 base.head) {
7221 if (encoder->new_crtc == intel_crtc)
7222 used = true;
7223 }
7224
7225 if (!used)
7226 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7227 }
7228
e2e1ed41
DV		 7229
7230 /* set_mode is also used to update properties on life display pipes. */
7231 intel_crtc = to_intel_crtc(crtc);
7232 if (crtc->enabled)
7233 *prepare_pipes |= 1 << intel_crtc->pipe;
7234
7235 /* We only support modeset on one single crtc, hence we need to do that
7236 * only for the passed in crtc iff we change anything else than just
7237 * disable crtcs.
7238 *
7239 * This is actually not true, to be fully compatible with the old crtc
7240 * helper we automatically disable _any_ output (i.e. doesn't need to be
7241 * connected to the crtc we're modesetting on) if it's disconnected.
7242 * Which is a rather nutty api (since changed the output configuration
7243 * without userspace's explicit request can lead to confusion), but
7244 * alas. Hence we currently need to modeset on all pipes we prepare. */
7245 if (*prepare_pipes)
7246 *modeset_pipes = *prepare_pipes;
7247
7248 /* ... and mask these out. */
7249 *modeset_pipes &= ~(*disable_pipes);
7250 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7251}
79e53945 7252
ea9d758d 7253static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7254{
ea9d758d 7255 struct drm_encoder *encoder;
f6e5b160 7256 struct drm_device *dev = crtc->dev;
f6e5b160 7257
ea9d758d
DV		 7258 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7259 if (encoder->crtc == crtc)
7260 return true;
7261
7262 return false;
7263}
7264
7265static void
7266intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7267{
7268 struct intel_encoder *intel_encoder;
7269 struct intel_crtc *intel_crtc;
7270 struct drm_connector *connector;
7271
7272 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7273 base.head) {
7274 if (!intel_encoder->base.crtc)
7275 continue;
7276
7277 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7278
7279 if (prepare_pipes & (1 << intel_crtc->pipe))
7280 intel_encoder->connectors_active = false;
7281 }
7282
7283 intel_modeset_commit_output_state(dev);
7284
7285 /* Update computed state. */
7286 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7287 base.head) {
7288 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7289 }
7290
7291 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7292 if (!connector->encoder || !connector->encoder->crtc)
7293 continue;
7294
7295 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7296
7297 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7298 struct drm_property *dpms_property =
7299 dev->mode_config.dpms_property;
7300
ea9d758d 7301 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7302 drm_object_property_set_value(&connector->base,
68d34720
DV		 7303 dpms_property,
7304 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7305
7306 intel_encoder = to_intel_encoder(connector->encoder);
7307 intel_encoder->connectors_active = true;
7308 }
7309 }
7310
7311}
7312
25c5b266
DV		 7313#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7314 list_for_each_entry((intel_crtc), \
7315 &(dev)->mode_config.crtc_list, \
7316 base.head) \
7317 if (mask & (1 <<(intel_crtc)->pipe)) \
7318
b980514c 7319void
8af6cf88
DV		 7320intel_modeset_check_state(struct drm_device *dev)
7321{
7322 struct intel_crtc *crtc;
7323 struct intel_encoder *encoder;
7324 struct intel_connector *connector;
7325
7326 list_for_each_entry(connector, &dev->mode_config.connector_list,
7327 base.head) {
7328 /* This also checks the encoder/connector hw state with the
7329 * ->get_hw_state callbacks. */
7330 intel_connector_check_state(connector);
7331
7332 WARN(&connector->new_encoder->base != connector->base.encoder,
7333 "connector's staged encoder doesn't match current encoder\n");
7334 }
7335
7336 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7337 base.head) {
7338 bool enabled = false;
7339 bool active = false;
7340 enum pipe pipe, tracked_pipe;
7341
7342 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7343 encoder->base.base.id,
7344 drm_get_encoder_name(&encoder->base));
7345
7346 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7347 "encoder's stage crtc doesn't match current crtc\n");
7348 WARN(encoder->connectors_active && !encoder->base.crtc,
7349 "encoder's active_connectors set, but no crtc\n");
7350
7351 list_for_each_entry(connector, &dev->mode_config.connector_list,
7352 base.head) {
7353 if (connector->base.encoder != &encoder->base)
7354 continue;
7355 enabled = true;
7356 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7357 active = true;
7358 }
7359 WARN(!!encoder->base.crtc != enabled,
7360 "encoder's enabled state mismatch "
7361 "(expected %i, found %i)\n",
7362 !!encoder->base.crtc, enabled);
7363 WARN(active && !encoder->base.crtc,
7364 "active encoder with no crtc\n");
7365
7366 WARN(encoder->connectors_active != active,
7367 "encoder's computed active state doesn't match tracked active state "
7368 "(expected %i, found %i)\n", active, encoder->connectors_active);
7369
7370 active = encoder->get_hw_state(encoder, &pipe);
7371 WARN(active != encoder->connectors_active,
7372 "encoder's hw state doesn't match sw tracking "
7373 "(expected %i, found %i)\n",
7374 encoder->connectors_active, active);
7375
7376 if (!encoder->base.crtc)
7377 continue;
7378
7379 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7380 WARN(active && pipe != tracked_pipe,
7381 "active encoder's pipe doesn't match"
7382 "(expected %i, found %i)\n",
7383 tracked_pipe, pipe);
7384
7385 }
7386
7387 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7388 base.head) {
7389 bool enabled = false;
7390 bool active = false;
7391
7392 DRM_DEBUG_KMS("[CRTC:%d]\n",
7393 crtc->base.base.id);
7394
7395 WARN(crtc->active && !crtc->base.enabled,
7396 "active crtc, but not enabled in sw tracking\n");
7397
7398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7399 base.head) {
7400 if (encoder->base.crtc != &crtc->base)
7401 continue;
7402 enabled = true;
7403 if (encoder->connectors_active)
7404 active = true;
7405 }
7406 WARN(active != crtc->active,
7407 "crtc's computed active state doesn't match tracked active state "
7408 "(expected %i, found %i)\n", active, crtc->active);
7409 WARN(enabled != crtc->base.enabled,
7410 "crtc's computed enabled state doesn't match tracked enabled state "
7411 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7412
7413 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7414 }
7415}
7416
a6778b3c
DV		 7417bool intel_set_mode(struct drm_crtc *crtc,
7418 struct drm_display_mode *mode,
94352cf9 7419 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7420{
7421 struct drm_device *dev = crtc->dev;
dbf2b54e 7422 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7423 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7424 struct intel_crtc *intel_crtc;
7425 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7426 bool ret = true;
7427
3ac18232
TG		 7428 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7429 if (!saved_mode) {
7430 DRM_ERROR("i915: Could not allocate saved display mode.\n");
7431 return false;
7432 }
7433 saved_hwmode = saved_mode + 1;
7434
e2e1ed41 7435 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7436 &prepare_pipes, &disable_pipes);
7437
7438 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7439 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7440
976f8a20
DV		 7441 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7442 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7443
3ac18232
TG		 7444 *saved_hwmode = crtc->hwmode;
7445 *saved_mode = crtc->mode;
a6778b3c 7446
25c5b266
DV		 7447 /* Hack: Because we don't (yet) support global modeset on multiple
7448 * crtcs, we don't keep track of the new mode for more than one crtc.
7449 * Hence simply check whether any bit is set in modeset_pipes in all the
7450 * pieces of code that are not yet converted to deal with mutliple crtcs
7451 * changing their mode at the same time. */
7452 adjusted_mode = NULL;
7453 if (modeset_pipes) {
7454 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7455 if (IS_ERR(adjusted_mode)) {
3ac18232
TG		 7456 ret = false;
7457 goto out;
25c5b266 7458 }
25c5b266 7459 }
a6778b3c 7460
ea9d758d
DV		 7461 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7462 if (intel_crtc->base.enabled)
7463 dev_priv->display.crtc_disable(&intel_crtc->base);
7464 }
a6778b3c 7465
6c4c86f5
DV		 7466 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7467 * to set it here already despite that we pass it down the callchain.
f6e5b160 7468 */
6c4c86f5 7469 if (modeset_pipes)
25c5b266 7470 crtc->mode = *mode;
7758a113 7471
ea9d758d
DV		 7472 /* Only after disabling all output pipelines that will be changed can we
7473 * update the the output configuration. */
7474 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7475
47fab737
DV		 7476 if (dev_priv->display.modeset_global_resources)
7477 dev_priv->display.modeset_global_resources(dev);
7478
a6778b3c
DV		 7479 /* Set up the DPLL and any encoders state that needs to adjust or depend
7480 * on the DPLL.
f6e5b160 7481 */
25c5b266
DV		 7482 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7483 ret = !intel_crtc_mode_set(&intel_crtc->base,
7484 mode, adjusted_mode,
7485 x, y, fb);
7486 if (!ret)
7487 goto done;
a6778b3c
DV		 7488 }
7489
7490 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7491 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7492 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7493
25c5b266
DV		 7494 if (modeset_pipes) {
7495 /* Store real post-adjustment hardware mode. */
7496 crtc->hwmode = *adjusted_mode;
a6778b3c 7497
25c5b266
DV		 7498 /* Calculate and store various constants which
7499 * are later needed by vblank and swap-completion
7500 * timestamping. They are derived from true hwmode.
7501 */
7502 drm_calc_timestamping_constants(crtc);
7503 }
a6778b3c
DV		 7504
7505 /* FIXME: add subpixel order */
7506done:
7507 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7508 if (!ret && crtc->enabled) {
3ac18232
TG		 7509 crtc->hwmode = *saved_hwmode;
7510 crtc->mode = *saved_mode;
8af6cf88
DV		 7511 } else {
7512 intel_modeset_check_state(dev);
a6778b3c
DV		 7513 }
7514
3ac18232
TG		 7515out:
7516 kfree(saved_mode);
a6778b3c 7517 return ret;
f6e5b160
CW		 7518}
7519
25c5b266
DV		 7520#undef for_each_intel_crtc_masked
7521
d9e55608
DV		 7522static void intel_set_config_free(struct intel_set_config *config)
7523{
7524 if (!config)
7525 return;
7526
1aa4b628
DV		 7527 kfree(config->save_connector_encoders);
7528 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7529 kfree(config);
7530}
7531
85f9eb71
DV		 7532static int intel_set_config_save_state(struct drm_device *dev,
7533 struct intel_set_config *config)
7534{
85f9eb71
DV		 7535 struct drm_encoder *encoder;
7536 struct drm_connector *connector;
7537 int count;
7538
1aa4b628
DV		 7539 config->save_encoder_crtcs =
7540 kcalloc(dev->mode_config.num_encoder,
7541 sizeof(struct drm_crtc *), GFP_KERNEL);
7542 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7543 return -ENOMEM;
7544
1aa4b628
DV		 7545 config->save_connector_encoders =
7546 kcalloc(dev->mode_config.num_connector,
7547 sizeof(struct drm_encoder *), GFP_KERNEL);
7548 if (!config->save_connector_encoders)
85f9eb71
DV		 7549 return -ENOMEM;
7550
7551 /* Copy data. Note that driver private data is not affected.
7552 * Should anything bad happen only the expected state is
7553 * restored, not the drivers personal bookkeeping.
7554 */
85f9eb71
DV		 7555 count = 0;
7556 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7557 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7558 }
7559
7560 count = 0;
7561 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7562 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7563 }
7564
7565 return 0;
7566}
7567
7568static void intel_set_config_restore_state(struct drm_device *dev,
7569 struct intel_set_config *config)
7570{
9a935856
DV		 7571 struct intel_encoder *encoder;
7572 struct intel_connector *connector;
85f9eb71
DV		 7573 int count;
7574
85f9eb71 7575 count = 0;
9a935856
DV		 7576 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7577 encoder->new_crtc =
7578 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7579 }
7580
7581 count = 0;
9a935856
DV		 7582 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7583 connector->new_encoder =
7584 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7585 }
7586}
7587
5e2b584e
DV		 7588static void
7589intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7590 struct intel_set_config *config)
7591{
7592
7593 /* We should be able to check here if the fb has the same properties
7594 * and then just flip_or_move it */
7595 if (set->crtc->fb != set->fb) {
7596 /* If we have no fb then treat it as a full mode set */
7597 if (set->crtc->fb == NULL) {
7598 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7599 config->mode_changed = true;
7600 } else if (set->fb == NULL) {
7601 config->mode_changed = true;
7602 } else if (set->fb->depth != set->crtc->fb->depth) {
7603 config->mode_changed = true;
7604 } else if (set->fb->bits_per_pixel !=
7605 set->crtc->fb->bits_per_pixel) {
7606 config->mode_changed = true;
7607 } else
7608 config->fb_changed = true;
7609 }
7610
835c5873 7611 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7612 config->fb_changed = true;
7613
7614 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7615 DRM_DEBUG_KMS("modes are different, full mode set\n");
7616 drm_mode_debug_printmodeline(&set->crtc->mode);
7617 drm_mode_debug_printmodeline(set->mode);
7618 config->mode_changed = true;
7619 }
7620}
7621
2e431051 7622static int
9a935856
DV		 7623intel_modeset_stage_output_state(struct drm_device *dev,
7624 struct drm_mode_set *set,
7625 struct intel_set_config *config)
50f56119 7626{
85f9eb71 7627 struct drm_crtc *new_crtc;
9a935856
DV		 7628 struct intel_connector *connector;
7629 struct intel_encoder *encoder;
2e431051 7630 int count, ro;
50f56119 7631
9a935856
DV		 7632 /* The upper layers ensure that we either disabl a crtc or have a list
7633 * of connectors. For paranoia, double-check this. */
7634 WARN_ON(!set->fb && (set->num_connectors != 0));
7635 WARN_ON(set->fb && (set->num_connectors == 0));
7636
50f56119 7637 count = 0;
9a935856
DV		 7638 list_for_each_entry(connector, &dev->mode_config.connector_list,
7639 base.head) {
7640 /* Otherwise traverse passed in connector list and get encoders
7641 * for them. */
50f56119 7642 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7643 if (set->connectors[ro] == &connector->base) {
7644 connector->new_encoder = connector->encoder;
50f56119
DV		 7645 break;
7646 }
7647 }
7648
9a935856
DV		 7649 /* If we disable the crtc, disable all its connectors. Also, if
7650 * the connector is on the changing crtc but not on the new
7651 * connector list, disable it. */
7652 if ((!set->fb || ro == set->num_connectors) &&
7653 connector->base.encoder &&
7654 connector->base.encoder->crtc == set->crtc) {
7655 connector->new_encoder = NULL;
7656
7657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7658 connector->base.base.id,
7659 drm_get_connector_name(&connector->base));
7660 }
7661
7662
7663 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7664 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7665 config->mode_changed = true;
50f56119 7666 }
9a935856
DV		 7667
7668 /* Disable all disconnected encoders. */
7669 if (connector->base.status == connector_status_disconnected)
7670 connector->new_encoder = NULL;
50f56119 7671 }
9a935856 7672 /* connector->new_encoder is now updated for all connectors. */
50f56119 7673
9a935856 7674 /* Update crtc of enabled connectors. */
50f56119 7675 count = 0;
9a935856
DV		 7676 list_for_each_entry(connector, &dev->mode_config.connector_list,
7677 base.head) {
7678 if (!connector->new_encoder)
50f56119
DV		 7679 continue;
7680
9a935856 7681 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7682
7683 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7684 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7685 new_crtc = set->crtc;
7686 }
7687
7688 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7689 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7690 new_crtc)) {
5e2b584e 7691 return -EINVAL;
50f56119 7692 }
9a935856
DV		 7693 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7694
7695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7696 connector->base.base.id,
7697 drm_get_connector_name(&connector->base),
7698 new_crtc->base.id);
7699 }
7700
7701 /* Check for any encoders that needs to be disabled. */
7702 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7703 base.head) {
7704 list_for_each_entry(connector,
7705 &dev->mode_config.connector_list,
7706 base.head) {
7707 if (connector->new_encoder == encoder) {
7708 WARN_ON(!connector->new_encoder->new_crtc);
7709
7710 goto next_encoder;
7711 }
7712 }
7713 encoder->new_crtc = NULL;
7714next_encoder:
7715 /* Only now check for crtc changes so we don't miss encoders
7716 * that will be disabled. */
7717 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7718 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7719 config->mode_changed = true;
50f56119
DV		 7720 }
7721 }
9a935856 7722 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7723
2e431051
DV		 7724 return 0;
7725}
7726
7727static int intel_crtc_set_config(struct drm_mode_set *set)
7728{
7729 struct drm_device *dev;
2e431051
DV		 7730 struct drm_mode_set save_set;
7731 struct intel_set_config *config;
7732 int ret;
2e431051 7733
8d3e375e
DV		 7734 BUG_ON(!set);
7735 BUG_ON(!set->crtc);
7736 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7737
7738 if (!set->mode)
7739 set->fb = NULL;
7740
431e50f7
DV		 7741 /* The fb helper likes to play gross jokes with ->mode_set_config.
7742 * Unfortunately the crtc helper doesn't do much at all for this case,
7743 * so we have to cope with this madness until the fb helper is fixed up. */
7744 if (set->fb && set->num_connectors == 0)
7745 return 0;
7746
2e431051
DV		 7747 if (set->fb) {
7748 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7749 set->crtc->base.id, set->fb->base.id,
7750 (int)set->num_connectors, set->x, set->y);
7751 } else {
7752 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7753 }
7754
7755 dev = set->crtc->dev;
7756
7757 ret = -ENOMEM;
7758 config = kzalloc(sizeof(*config), GFP_KERNEL);
7759 if (!config)
7760 goto out_config;
7761
7762 ret = intel_set_config_save_state(dev, config);
7763 if (ret)
7764 goto out_config;
7765
7766 save_set.crtc = set->crtc;
7767 save_set.mode = &set->crtc->mode;
7768 save_set.x = set->crtc->x;
7769 save_set.y = set->crtc->y;
7770 save_set.fb = set->crtc->fb;
7771
7772 /* Compute whether we need a full modeset, only an fb base update or no
7773 * change at all. In the future we might also check whether only the
7774 * mode changed, e.g. for LVDS where we only change the panel fitter in
7775 * such cases. */
7776 intel_set_config_compute_mode_changes(set, config);
7777
9a935856 7778 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7779 if (ret)
7780 goto fail;
7781
5e2b584e 7782 if (config->mode_changed) {
87f1faa6 7783 if (set->mode) {
50f56119
DV		 7784 DRM_DEBUG_KMS("attempting to set mode from"
7785 " userspace\n");
7786 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7787 }
7788
7789 if (!intel_set_mode(set->crtc, set->mode,
7790 set->x, set->y, set->fb)) {
7791 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7792 set->crtc->base.id);
7793 ret = -EINVAL;
7794 goto fail;
7795 }
5e2b584e 7796 } else if (config->fb_changed) {
4f660f49 7797 ret = intel_pipe_set_base(set->crtc,
94352cf9 7798 set->x, set->y, set->fb);
50f56119
DV		 7799 }
7800
d9e55608
DV		 7801 intel_set_config_free(config);
7802
50f56119
DV		 7803 return 0;
7804
7805fail:
85f9eb71 7806 intel_set_config_restore_state(dev, config);
50f56119
DV		 7807
7808 /* Try to restore the config */
5e2b584e 7809 if (config->mode_changed &&
a6778b3c
DV		 7810 !intel_set_mode(save_set.crtc, save_set.mode,
7811 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7812 DRM_ERROR("failed to restore config after modeset failure\n");
7813
d9e55608
DV		 7814out_config:
7815 intel_set_config_free(config);
50f56119
DV		 7816 return ret;
7817}
f6e5b160
CW		 7818
7819static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7820 .cursor_set = intel_crtc_cursor_set,
7821 .cursor_move = intel_crtc_cursor_move,
7822 .gamma_set = intel_crtc_gamma_set,
50f56119 7823 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7824 .destroy = intel_crtc_destroy,
7825 .page_flip = intel_crtc_page_flip,
7826};
7827
79f689aa
PZ		 7828static void intel_cpu_pll_init(struct drm_device *dev)
7829{
affa9354 7830 if (HAS_DDI(dev))
79f689aa
PZ		 7831 intel_ddi_pll_init(dev);
7832}
7833
ee7b9f93
JB		 7834static void intel_pch_pll_init(struct drm_device *dev)
7835{
7836 drm_i915_private_t *dev_priv = dev->dev_private;
7837 int i;
7838
7839 if (dev_priv->num_pch_pll == 0) {
7840 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7841 return;
7842 }
7843
7844 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7845 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7846 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7847 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7848 }
7849}
7850
b358d0a6 7851static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7852{
22fd0fab 7853 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7854 struct intel_crtc *intel_crtc;
7855 int i;
7856
7857 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7858 if (intel_crtc == NULL)
7859 return;
7860
7861 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7862
7863 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7864 for (i = 0; i < 256; i++) {
7865 intel_crtc->lut_r[i] = i;
7866 intel_crtc->lut_g[i] = i;
7867 intel_crtc->lut_b[i] = i;
7868 }
7869
80824003
JB		 7870 /* Swap pipes & planes for FBC on pre-965 */
7871 intel_crtc->pipe = pipe;
7872 intel_crtc->plane = pipe;
a5c961d1 7873 intel_crtc->cpu_transcoder = pipe;
e2e767ab 7874 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7875 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7876 intel_crtc->plane = !pipe;
80824003
JB		 7877 }
7878
22fd0fab
JB		 7879 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7880 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7881 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7882 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7883
5a354204 7884 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7885
79e53945 7886 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7887}
7888
08d7b3d1 7889int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7890 struct drm_file *file)
08d7b3d1 7891{
08d7b3d1 7892 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7893 struct drm_mode_object *drmmode_obj;
7894 struct intel_crtc *crtc;
08d7b3d1 7895
1cff8f6b
DV		 7896 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7897 return -ENODEV;
08d7b3d1 7898
c05422d5
DV		 7899 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7900 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7901
c05422d5 7902 if (!drmmode_obj) {
08d7b3d1
CW		 7903 DRM_ERROR("no such CRTC id\n");
7904 return -EINVAL;
7905 }
7906
c05422d5
DV		 7907 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7908 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7909
c05422d5 7910 return 0;
08d7b3d1
CW		 7911}
7912
66a9278e 7913static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7914{
66a9278e
DV		 7915 struct drm_device *dev = encoder->base.dev;
7916 struct intel_encoder *source_encoder;
79e53945 7917 int index_mask = 0;
79e53945
JB		 7918 int entry = 0;
7919
66a9278e
DV		 7920 list_for_each_entry(source_encoder,
7921 &dev->mode_config.encoder_list, base.head) {
7922
7923 if (encoder == source_encoder)
79e53945 7924 index_mask |= (1 << entry);
66a9278e
DV		 7925
7926 /* Intel hw has only one MUX where enocoders could be cloned. */
7927 if (encoder->cloneable && source_encoder->cloneable)
7928 index_mask |= (1 << entry);
7929
79e53945
JB		 7930 entry++;
7931 }
4ef69c7a 7932
79e53945
JB		 7933 return index_mask;
7934}
7935
4d302442
CW		 7936static bool has_edp_a(struct drm_device *dev)
7937{
7938 struct drm_i915_private *dev_priv = dev->dev_private;
7939
7940 if (!IS_MOBILE(dev))
7941 return false;
7942
7943 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7944 return false;
7945
7946 if (IS_GEN5(dev) &&
7947 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7948 return false;
7949
7950 return true;
7951}
7952
79e53945
JB		 7953static void intel_setup_outputs(struct drm_device *dev)
7954{
725e30ad 7955 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7956 struct intel_encoder *encoder;
cb0953d7 7957 bool dpd_is_edp = false;
f3cfcba6 7958 bool has_lvds;
79e53945 7959
f3cfcba6 7960 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7961 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7962 /* disable the panel fitter on everything but LVDS */
7963 I915_WRITE(PFIT_CONTROL, 0);
7964 }
79e53945 7965
affa9354 7966 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 7967 intel_crt_init(dev);
cb0953d7 7968
affa9354 7969 if (HAS_DDI(dev)) {
0e72a5b5
ED		 7970 int found;
7971
7972 /* Haswell uses DDI functions to detect digital outputs */
7973 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7974 /* DDI A only supports eDP */
7975 if (found)
7976 intel_ddi_init(dev, PORT_A);
7977
7978 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7979 * register */
7980 found = I915_READ(SFUSE_STRAP);
7981
7982 if (found & SFUSE_STRAP_DDIB_DETECTED)
7983 intel_ddi_init(dev, PORT_B);
7984 if (found & SFUSE_STRAP_DDIC_DETECTED)
7985 intel_ddi_init(dev, PORT_C);
7986 if (found & SFUSE_STRAP_DDID_DETECTED)
7987 intel_ddi_init(dev, PORT_D);
7988 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7989 int found;
270b3042
DV		 7990 dpd_is_edp = intel_dpd_is_edp(dev);
7991
7992 if (has_edp_a(dev))
7993 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 7994
30ad48b7 7995 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7996 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7997 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7998 if (!found)
08d644ad 7999 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8000 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8001 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8002 }
8003
8004 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8005 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8006
b708a1d5 8007 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8008 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8009
5eb08b69 8010 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8011 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8012
270b3042 8013 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8014 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8015 } else if (IS_VALLEYVIEW(dev)) {
8016 int found;
8017
19c03924
GB		 8018 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8019 if (I915_READ(DP_C) & DP_DETECTED)
8020 intel_dp_init(dev, DP_C, PORT_C);
8021
4a87d65d
JB		 8022 if (I915_READ(SDVOB) & PORT_DETECTED) {
8023 /* SDVOB multiplex with HDMIB */
8024 found = intel_sdvo_init(dev, SDVOB, true);
8025 if (!found)
08d644ad 8026 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8027 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8028 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8029 }
8030
8031 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8032 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8033
103a196f 8034 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8035 bool found = false;
7d57382e 8036
725e30ad 8037 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8038 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8039 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8040 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8041 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8042 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8043 }
27185ae1 8044
b01f2c3a
JB		 8045 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8046 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8047 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8048 }
725e30ad 8049 }
13520b05
KH		 8050
8051 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8052
b01f2c3a
JB		 8053 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8054 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8055 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8056 }
27185ae1
ML		 8057
8058 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8059
b01f2c3a
JB		 8060 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8061 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8062 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8063 }
8064 if (SUPPORTS_INTEGRATED_DP(dev)) {
8065 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8066 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8067 }
725e30ad 8068 }
27185ae1 8069
b01f2c3a
JB		 8070 if (SUPPORTS_INTEGRATED_DP(dev) &&
8071 (I915_READ(DP_D) & DP_DETECTED)) {
8072 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8073 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8074 }
bad720ff 8075 } else if (IS_GEN2(dev))
79e53945
JB		 8076 intel_dvo_init(dev);
8077
103a196f 8078 if (SUPPORTS_TV(dev))
79e53945
JB		 8079 intel_tv_init(dev);
8080
4ef69c7a
CW		 8081 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8082 encoder->base.possible_crtcs = encoder->crtc_mask;
8083 encoder->base.possible_clones =
66a9278e 8084 intel_encoder_clones(encoder);
79e53945 8085 }
47356eb6 8086
40579abe 8087 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8088 ironlake_init_pch_refclk(dev);
270b3042
DV		 8089
8090 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8091}
8092
8093static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8094{
8095 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8096
8097 drm_framebuffer_cleanup(fb);
05394f39 8098 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8099
8100 kfree(intel_fb);
8101}
8102
8103static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8104 struct drm_file *file,
79e53945
JB		 8105 unsigned int *handle)
8106{
8107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8108 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8109
05394f39 8110 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8111}
8112
8113static const struct drm_framebuffer_funcs intel_fb_funcs = {
8114 .destroy = intel_user_framebuffer_destroy,
8115 .create_handle = intel_user_framebuffer_create_handle,
8116};
8117
38651674
DA		 8118int intel_framebuffer_init(struct drm_device *dev,
8119 struct intel_framebuffer *intel_fb,
308e5bcb 8120 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8121 struct drm_i915_gem_object *obj)
79e53945 8122{
79e53945
JB		 8123 int ret;
8124
05394f39 8125 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8126 return -EINVAL;
8127
308e5bcb 8128 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8129 return -EINVAL;
8130
5d7bd705
VS		 8131 /* FIXME <= Gen4 stride limits are bit unclear */
8132 if (mode_cmd->pitches[0] > 32768)
8133 return -EINVAL;
8134
8135 if (obj->tiling_mode != I915_TILING_NONE &&
8136 mode_cmd->pitches[0] != obj->stride)
8137 return -EINVAL;
8138
57779d06 8139 /* Reject formats not supported by any plane early. */
308e5bcb 8140 switch (mode_cmd->pixel_format) {
57779d06 8141 case DRM_FORMAT_C8:
04b3924d
VS		 8142 case DRM_FORMAT_RGB565:
8143 case DRM_FORMAT_XRGB8888:
8144 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8145 break;
8146 case DRM_FORMAT_XRGB1555:
8147 case DRM_FORMAT_ARGB1555:
8148 if (INTEL_INFO(dev)->gen > 3)
8149 return -EINVAL;
8150 break;
8151 case DRM_FORMAT_XBGR8888:
8152 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8153 case DRM_FORMAT_XRGB2101010:
8154 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8155 case DRM_FORMAT_XBGR2101010:
8156 case DRM_FORMAT_ABGR2101010:
8157 if (INTEL_INFO(dev)->gen < 4)
8158 return -EINVAL;
b5626747 8159 break;
04b3924d
VS		 8160 case DRM_FORMAT_YUYV:
8161 case DRM_FORMAT_UYVY:
8162 case DRM_FORMAT_YVYU:
8163 case DRM_FORMAT_VYUY:
57779d06
VS		 8164 if (INTEL_INFO(dev)->gen < 6)
8165 return -EINVAL;
57cd6508
CW		 8166 break;
8167 default:
57779d06 8168 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8169 return -EINVAL;
8170 }
8171
90f9a336
VS		 8172 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8173 if (mode_cmd->offsets[0] != 0)
8174 return -EINVAL;
8175
79e53945
JB		 8176 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8177 if (ret) {
8178 DRM_ERROR("framebuffer init failed %d\n", ret);
8179 return ret;
8180 }
8181
8182 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8183 intel_fb->obj = obj;
79e53945
JB		 8184 return 0;
8185}
8186
79e53945
JB		 8187static struct drm_framebuffer *
8188intel_user_framebuffer_create(struct drm_device *dev,
8189 struct drm_file *filp,
308e5bcb 8190 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8191{
05394f39 8192 struct drm_i915_gem_object *obj;
79e53945 8193
308e5bcb
JB		 8194 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8195 mode_cmd->handles[0]));
c8725226 8196 if (&obj->base == NULL)
cce13ff7 8197 return ERR_PTR(-ENOENT);
79e53945 8198
d2dff872 8199 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8200}
8201
79e53945 8202static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8203 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8204 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8205};
8206
e70236a8
JB		 8207/* Set up chip specific display functions */
8208static void intel_init_display(struct drm_device *dev)
8209{
8210 struct drm_i915_private *dev_priv = dev->dev_private;
8211
8212 /* We always want a DPMS function */
affa9354 8213 if (HAS_DDI(dev)) {
09b4ddf9 8214 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8215 dev_priv->display.crtc_enable = haswell_crtc_enable;
8216 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8217 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8218 dev_priv->display.update_plane = ironlake_update_plane;
8219 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8220 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8221 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8222 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8223 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8224 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8225 } else {
f564048e 8226 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8227 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8228 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8229 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8230 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8231 }
e70236a8 8232
e70236a8 8233 /* Returns the core display clock speed */
25eb05fc
JB		 8234 if (IS_VALLEYVIEW(dev))
8235 dev_priv->display.get_display_clock_speed =
8236 valleyview_get_display_clock_speed;
8237 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8238 dev_priv->display.get_display_clock_speed =
8239 i945_get_display_clock_speed;
8240 else if (IS_I915G(dev))
8241 dev_priv->display.get_display_clock_speed =
8242 i915_get_display_clock_speed;
f2b115e6 8243 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8244 dev_priv->display.get_display_clock_speed =
8245 i9xx_misc_get_display_clock_speed;
8246 else if (IS_I915GM(dev))
8247 dev_priv->display.get_display_clock_speed =
8248 i915gm_get_display_clock_speed;
8249 else if (IS_I865G(dev))
8250 dev_priv->display.get_display_clock_speed =
8251 i865_get_display_clock_speed;
f0f8a9ce 8252 else if (IS_I85X(dev))
e70236a8
JB		 8253 dev_priv->display.get_display_clock_speed =
8254 i855_get_display_clock_speed;
8255 else /* 852, 830 */
8256 dev_priv->display.get_display_clock_speed =
8257 i830_get_display_clock_speed;
8258
7f8a8569 8259 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8260 if (IS_GEN5(dev)) {
674cf967 8261 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8262 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8263 } else if (IS_GEN6(dev)) {
674cf967 8264 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8265 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8266 } else if (IS_IVYBRIDGE(dev)) {
8267 /* FIXME: detect B0+ stepping and use auto training */
8268 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8269 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8270 dev_priv->display.modeset_global_resources =
8271 ivb_modeset_global_resources;
c82e4d26
ED		 8272 } else if (IS_HASWELL(dev)) {
8273 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8274 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8275 } else
8276 dev_priv->display.update_wm = NULL;
6067aaea 8277 } else if (IS_G4X(dev)) {
e0dac65e 8278 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8279 }
8c9f3aaf
JB		 8280
8281 /* Default just returns -ENODEV to indicate unsupported */
8282 dev_priv->display.queue_flip = intel_default_queue_flip;
8283
8284 switch (INTEL_INFO(dev)->gen) {
8285 case 2:
8286 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8287 break;
8288
8289 case 3:
8290 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8291 break;
8292
8293 case 4:
8294 case 5:
8295 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8296 break;
8297
8298 case 6:
8299 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8300 break;
7c9017e5
JB		 8301 case 7:
8302 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8303 break;
8c9f3aaf 8304 }
e70236a8
JB		 8305}
8306
b690e96c
JB		 8307/*
8308 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8309 * resume, or other times. This quirk makes sure that's the case for
8310 * affected systems.
8311 */
0206e353 8312static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8313{
8314 struct drm_i915_private *dev_priv = dev->dev_private;
8315
8316 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8317 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8318}
8319
435793df
KP		 8320/*
8321 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8322 */
8323static void quirk_ssc_force_disable(struct drm_device *dev)
8324{
8325 struct drm_i915_private *dev_priv = dev->dev_private;
8326 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8327 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8328}
8329
4dca20ef 8330/*
5a15ab5b
CE		 8331 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8332 * brightness value
4dca20ef
CE		 8333 */
8334static void quirk_invert_brightness(struct drm_device *dev)
8335{
8336 struct drm_i915_private *dev_priv = dev->dev_private;
8337 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8338 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8339}
8340
b690e96c
JB		 8341struct intel_quirk {
8342 int device;
8343 int subsystem_vendor;
8344 int subsystem_device;
8345 void (*hook)(struct drm_device *dev);
8346};
8347
5f85f176
EE		 8348/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8349struct intel_dmi_quirk {
8350 void (*hook)(struct drm_device *dev);
8351 const struct dmi_system_id (*dmi_id_list)[];
8352};
8353
8354static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8355{
8356 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8357 return 1;
8358}
8359
8360static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8361 {
8362 .dmi_id_list = &(const struct dmi_system_id[]) {
8363 {
8364 .callback = intel_dmi_reverse_brightness,
8365 .ident = "NCR Corporation",
8366 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8367 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8368 },
8369 },
8370 { } /* terminating entry */
8371 },
8372 .hook = quirk_invert_brightness,
8373 },
8374};
8375
c43b5634 8376static struct intel_quirk intel_quirks[] = {
b690e96c 8377 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8378 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8379
b690e96c
JB		 8380 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8381 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8382
b690e96c
JB		 8383 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8384 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8385
ccd0d36e 8386 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8387 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8388 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8389
8390 /* Lenovo U160 cannot use SSC on LVDS */
8391 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8392
8393 /* Sony Vaio Y cannot use SSC on LVDS */
8394 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8395
8396 /* Acer Aspire 5734Z must invert backlight brightness */
8397 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8398};
8399
8400static void intel_init_quirks(struct drm_device *dev)
8401{
8402 struct pci_dev *d = dev->pdev;
8403 int i;
8404
8405 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8406 struct intel_quirk *q = &intel_quirks[i];
8407
8408 if (d->device == q->device &&
8409 (d->subsystem_vendor == q->subsystem_vendor ||
8410 q->subsystem_vendor == PCI_ANY_ID) &&
8411 (d->subsystem_device == q->subsystem_device ||
8412 q->subsystem_device == PCI_ANY_ID))
8413 q->hook(dev);
8414 }
5f85f176
EE		 8415 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8416 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8417 intel_dmi_quirks[i].hook(dev);
8418 }
b690e96c
JB		 8419}
8420
9cce37f4
JB		 8421/* Disable the VGA plane that we never use */
8422static void i915_disable_vga(struct drm_device *dev)
8423{
8424 struct drm_i915_private *dev_priv = dev->dev_private;
8425 u8 sr1;
8426 u32 vga_reg;
8427
8428 if (HAS_PCH_SPLIT(dev))
8429 vga_reg = CPU_VGACNTRL;
8430 else
8431 vga_reg = VGACNTRL;
8432
8433 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8434 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8435 sr1 = inb(VGA_SR_DATA);
8436 outb(sr1 | 1<<5, VGA_SR_DATA);
8437 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8438 udelay(300);
8439
8440 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8441 POSTING_READ(vga_reg);
8442}
8443
f817586c
DV		 8444void intel_modeset_init_hw(struct drm_device *dev)
8445{
0232e927
ED		 8446 /* We attempt to init the necessary power wells early in the initialization
8447 * time, so the subsystems that expect power to be enabled can work.
8448 */
8449 intel_init_power_wells(dev);
8450
a8f78b58
ED		 8451 intel_prepare_ddi(dev);
8452
f817586c
DV		 8453 intel_init_clock_gating(dev);
8454
79f5b2c7 8455 mutex_lock(&dev->struct_mutex);
8090c6b9 8456 intel_enable_gt_powersave(dev);
79f5b2c7 8457 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8458}
8459
79e53945
JB		 8460void intel_modeset_init(struct drm_device *dev)
8461{
652c393a 8462 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8463 int i, ret;
79e53945
JB		 8464
8465 drm_mode_config_init(dev);
8466
8467 dev->mode_config.min_width = 0;
8468 dev->mode_config.min_height = 0;
8469
019d96cb
DA		 8470 dev->mode_config.preferred_depth = 24;
8471 dev->mode_config.prefer_shadow = 1;
8472
e6ecefaa 8473 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8474
b690e96c
JB		 8475 intel_init_quirks(dev);
8476
1fa61106
ED		 8477 intel_init_pm(dev);
8478
e70236a8
JB		 8479 intel_init_display(dev);
8480
a6c45cf0
CW		 8481 if (IS_GEN2(dev)) {
8482 dev->mode_config.max_width = 2048;
8483 dev->mode_config.max_height = 2048;
8484 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8485 dev->mode_config.max_width = 4096;
8486 dev->mode_config.max_height = 4096;
79e53945 8487 } else {
a6c45cf0
CW		 8488 dev->mode_config.max_width = 8192;
8489 dev->mode_config.max_height = 8192;
79e53945 8490 }
dd2757f8 8491 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8492
28c97730 8493 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8494 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8495
a3524f1b 8496 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8497 intel_crtc_init(dev, i);
00c2064b
JB		 8498 ret = intel_plane_init(dev, i);
8499 if (ret)
8500 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8501 }
8502
79f689aa 8503 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8504 intel_pch_pll_init(dev);
8505
9cce37f4
JB		 8506 /* Just disable it once at startup */
8507 i915_disable_vga(dev);
79e53945 8508 intel_setup_outputs(dev);
11be49eb
CW		 8509
8510 /* Just in case the BIOS is doing something questionable. */
8511 intel_disable_fbc(dev);
2c7111db
CW		 8512}
8513
24929352
DV		 8514static void
8515intel_connector_break_all_links(struct intel_connector *connector)
8516{
8517 connector->base.dpms = DRM_MODE_DPMS_OFF;
8518 connector->base.encoder = NULL;
8519 connector->encoder->connectors_active = false;
8520 connector->encoder->base.crtc = NULL;
8521}
8522
7fad798e
DV		 8523static void intel_enable_pipe_a(struct drm_device *dev)
8524{
8525 struct intel_connector *connector;
8526 struct drm_connector *crt = NULL;
8527 struct intel_load_detect_pipe load_detect_temp;
8528
8529 /* We can't just switch on the pipe A, we need to set things up with a
8530 * proper mode and output configuration. As a gross hack, enable pipe A
8531 * by enabling the load detect pipe once. */
8532 list_for_each_entry(connector,
8533 &dev->mode_config.connector_list,
8534 base.head) {
8535 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8536 crt = &connector->base;
8537 break;
8538 }
8539 }
8540
8541 if (!crt)
8542 return;
8543
8544 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8545 intel_release_load_detect_pipe(crt, &load_detect_temp);
8546
652c393a 8547
7fad798e
DV		 8548}
8549
fa555837
DV		 8550static bool
8551intel_check_plane_mapping(struct intel_crtc *crtc)
8552{
8553 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8554 u32 reg, val;
8555
8556 if (dev_priv->num_pipe == 1)
8557 return true;
8558
8559 reg = DSPCNTR(!crtc->plane);
8560 val = I915_READ(reg);
8561
8562 if ((val & DISPLAY_PLANE_ENABLE) &&
8563 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8564 return false;
8565
8566 return true;
8567}
8568
24929352
DV		 8569static void intel_sanitize_crtc(struct intel_crtc *crtc)
8570{
8571 struct drm_device *dev = crtc->base.dev;
8572 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8573 u32 reg;
24929352 8574
24929352 8575 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8576 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8577 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8578
8579 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8580 * disable the crtc (and hence change the state) if it is wrong. Note
8581 * that gen4+ has a fixed plane -> pipe mapping. */
8582 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8583 struct intel_connector *connector;
8584 bool plane;
8585
24929352
DV		 8586 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8587 crtc->base.base.id);
8588
8589 /* Pipe has the wrong plane attached and the plane is active.
8590 * Temporarily change the plane mapping and disable everything
8591 * ... */
8592 plane = crtc->plane;
8593 crtc->plane = !plane;
8594 dev_priv->display.crtc_disable(&crtc->base);
8595 crtc->plane = plane;
8596
8597 /* ... and break all links. */
8598 list_for_each_entry(connector, &dev->mode_config.connector_list,
8599 base.head) {
8600 if (connector->encoder->base.crtc != &crtc->base)
8601 continue;
8602
8603 intel_connector_break_all_links(connector);
8604 }
8605
8606 WARN_ON(crtc->active);
8607 crtc->base.enabled = false;
8608 }
24929352 8609
7fad798e
DV		 8610 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8611 crtc->pipe == PIPE_A && !crtc->active) {
8612 /* BIOS forgot to enable pipe A, this mostly happens after
8613 * resume. Force-enable the pipe to fix this, the update_dpms
8614 * call below we restore the pipe to the right state, but leave
8615 * the required bits on. */
8616 intel_enable_pipe_a(dev);
8617 }
8618
24929352
DV		 8619 /* Adjust the state of the output pipe according to whether we
8620 * have active connectors/encoders. */
8621 intel_crtc_update_dpms(&crtc->base);
8622
8623 if (crtc->active != crtc->base.enabled) {
8624 struct intel_encoder *encoder;
8625
8626 /* This can happen either due to bugs in the get_hw_state
8627 * functions or because the pipe is force-enabled due to the
8628 * pipe A quirk. */
8629 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8630 crtc->base.base.id,
8631 crtc->base.enabled ? "enabled" : "disabled",
8632 crtc->active ? "enabled" : "disabled");
8633
8634 crtc->base.enabled = crtc->active;
8635
8636 /* Because we only establish the connector -> encoder ->
8637 * crtc links if something is active, this means the
8638 * crtc is now deactivated. Break the links. connector
8639 * -> encoder links are only establish when things are
8640 * actually up, hence no need to break them. */
8641 WARN_ON(crtc->active);
8642
8643 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8644 WARN_ON(encoder->connectors_active);
8645 encoder->base.crtc = NULL;
8646 }
8647 }
8648}
8649
8650static void intel_sanitize_encoder(struct intel_encoder *encoder)
8651{
8652 struct intel_connector *connector;
8653 struct drm_device *dev = encoder->base.dev;
8654
8655 /* We need to check both for a crtc link (meaning that the
8656 * encoder is active and trying to read from a pipe) and the
8657 * pipe itself being active. */
8658 bool has_active_crtc = encoder->base.crtc &&
8659 to_intel_crtc(encoder->base.crtc)->active;
8660
8661 if (encoder->connectors_active && !has_active_crtc) {
8662 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8663 encoder->base.base.id,
8664 drm_get_encoder_name(&encoder->base));
8665
8666 /* Connector is active, but has no active pipe. This is
8667 * fallout from our resume register restoring. Disable
8668 * the encoder manually again. */
8669 if (encoder->base.crtc) {
8670 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8671 encoder->base.base.id,
8672 drm_get_encoder_name(&encoder->base));
8673 encoder->disable(encoder);
8674 }
8675
8676 /* Inconsistent output/port/pipe state happens presumably due to
8677 * a bug in one of the get_hw_state functions. Or someplace else
8678 * in our code, like the register restore mess on resume. Clamp
8679 * things to off as a safer default. */
8680 list_for_each_entry(connector,
8681 &dev->mode_config.connector_list,
8682 base.head) {
8683 if (connector->encoder != encoder)
8684 continue;
8685
8686 intel_connector_break_all_links(connector);
8687 }
8688 }
8689 /* Enabled encoders without active connectors will be fixed in
8690 * the crtc fixup. */
8691}
8692
8693/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8694 * and i915 state tracking structures. */
45e2b5f6
DV		 8695void intel_modeset_setup_hw_state(struct drm_device *dev,
8696 bool force_restore)
24929352
DV		 8697{
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 enum pipe pipe;
8700 u32 tmp;
8701 struct intel_crtc *crtc;
8702 struct intel_encoder *encoder;
8703 struct intel_connector *connector;
8704
affa9354 8705 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8706 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8707
8708 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8709 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8710 case TRANS_DDI_EDP_INPUT_A_ON:
8711 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8712 pipe = PIPE_A;
8713 break;
8714 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8715 pipe = PIPE_B;
8716 break;
8717 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8718 pipe = PIPE_C;
8719 break;
8720 }
8721
8722 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8723 crtc->cpu_transcoder = TRANSCODER_EDP;
8724
8725 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8726 pipe_name(pipe));
8727 }
8728 }
8729
24929352
DV		 8730 for_each_pipe(pipe) {
8731 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8732
702e7a56 8733 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8734 if (tmp & PIPECONF_ENABLE)
8735 crtc->active = true;
8736 else
8737 crtc->active = false;
8738
8739 crtc->base.enabled = crtc->active;
8740
8741 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8742 crtc->base.base.id,
8743 crtc->active ? "enabled" : "disabled");
8744 }
8745
affa9354 8746 if (HAS_DDI(dev))
6441ab5f
PZ		 8747 intel_ddi_setup_hw_pll_state(dev);
8748
24929352
DV		 8749 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8750 base.head) {
8751 pipe = 0;
8752
8753 if (encoder->get_hw_state(encoder, &pipe)) {
8754 encoder->base.crtc =
8755 dev_priv->pipe_to_crtc_mapping[pipe];
8756 } else {
8757 encoder->base.crtc = NULL;
8758 }
8759
8760 encoder->connectors_active = false;
8761 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8762 encoder->base.base.id,
8763 drm_get_encoder_name(&encoder->base),
8764 encoder->base.crtc ? "enabled" : "disabled",
8765 pipe);
8766 }
8767
8768 list_for_each_entry(connector, &dev->mode_config.connector_list,
8769 base.head) {
8770 if (connector->get_hw_state(connector)) {
8771 connector->base.dpms = DRM_MODE_DPMS_ON;
8772 connector->encoder->connectors_active = true;
8773 connector->base.encoder = &connector->encoder->base;
8774 } else {
8775 connector->base.dpms = DRM_MODE_DPMS_OFF;
8776 connector->base.encoder = NULL;
8777 }
8778 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8779 connector->base.base.id,
8780 drm_get_connector_name(&connector->base),
8781 connector->base.encoder ? "enabled" : "disabled");
8782 }
8783
8784 /* HW state is read out, now we need to sanitize this mess. */
8785 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8786 base.head) {
8787 intel_sanitize_encoder(encoder);
8788 }
8789
8790 for_each_pipe(pipe) {
8791 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8792 intel_sanitize_crtc(crtc);
8793 }
9a935856 8794
45e2b5f6
DV		 8795 if (force_restore) {
8796 for_each_pipe(pipe) {
8797 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8798 intel_set_mode(&crtc->base, &crtc->base.mode,
8799 crtc->base.x, crtc->base.y, crtc->base.fb);
8800 }
8801 } else {
8802 intel_modeset_update_staged_output_state(dev);
8803 }
8af6cf88
DV		 8804
8805 intel_modeset_check_state(dev);
2e938892
DV		 8806
8807 drm_mode_config_reset(dev);
2c7111db
CW		 8808}
8809
8810void intel_modeset_gem_init(struct drm_device *dev)
8811{
1833b134 8812 intel_modeset_init_hw(dev);
02e792fb
DV		 8813
8814 intel_setup_overlay(dev);
24929352 8815
45e2b5f6 8816 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 8817}
8818
8819void intel_modeset_cleanup(struct drm_device *dev)
8820{
652c393a
JB		 8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822 struct drm_crtc *crtc;
8823 struct intel_crtc *intel_crtc;
8824
f87ea761 8825 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8826 mutex_lock(&dev->struct_mutex);
8827
723bfd70
JB		 8828 intel_unregister_dsm_handler();
8829
8830
652c393a
JB		 8831 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8832 /* Skip inactive CRTCs */
8833 if (!crtc->fb)
8834 continue;
8835
8836 intel_crtc = to_intel_crtc(crtc);
3dec0095 8837 intel_increase_pllclock(crtc);
652c393a
JB		 8838 }
8839
973d04f9 8840 intel_disable_fbc(dev);
e70236a8 8841
8090c6b9 8842 intel_disable_gt_powersave(dev);
0cdab21f 8843
930ebb46
DV		 8844 ironlake_teardown_rc6(dev);
8845
57f350b6
JB		 8846 if (IS_VALLEYVIEW(dev))
8847 vlv_init_dpio(dev);
8848
69341a5e
KH		 8849 mutex_unlock(&dev->struct_mutex);
8850
6c0d9350
DV		 8851 /* Disable the irq before mode object teardown, for the irq might
8852 * enqueue unpin/hotplug work. */
8853 drm_irq_uninstall(dev);
8854 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8855 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8856
1630fe75
CW		 8857 /* flush any delayed tasks or pending work */
8858 flush_scheduled_work();
8859
79e53945
JB		 8860 drm_mode_config_cleanup(dev);
8861}
8862
f1c79df3
ZW		 8863/*
8864 * Return which encoder is currently attached for connector.
8865 */
df0e9248 8866struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8867{
df0e9248
CW		 8868 return &intel_attached_encoder(connector)->base;
8869}
f1c79df3 8870
df0e9248
CW		 8871void intel_connector_attach_encoder(struct intel_connector *connector,
8872 struct intel_encoder *encoder)
8873{
8874 connector->encoder = encoder;
8875 drm_mode_connector_attach_encoder(&connector->base,
8876 &encoder->base);
79e53945 8877}
28d52043
DA		 8878
8879/*
8880 * set vga decode state - true == enable VGA decode
8881 */
8882int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8883{
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 u16 gmch_ctrl;
8886
8887 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8888 if (state)
8889 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8890 else
8891 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8892 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8893 return 0;
8894}
c4a1d9e4
CW		 8895
8896#ifdef CONFIG_DEBUG_FS
8897#include <linux/seq_file.h>
8898
8899struct intel_display_error_state {
8900 struct intel_cursor_error_state {
8901 u32 control;
8902 u32 position;
8903 u32 base;
8904 u32 size;
52331309 8905 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8906
8907 struct intel_pipe_error_state {
8908 u32 conf;
8909 u32 source;
8910
8911 u32 htotal;
8912 u32 hblank;
8913 u32 hsync;
8914 u32 vtotal;
8915 u32 vblank;
8916 u32 vsync;
52331309 8917 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8918
8919 struct intel_plane_error_state {
8920 u32 control;
8921 u32 stride;
8922 u32 size;
8923 u32 pos;
8924 u32 addr;
8925 u32 surface;
8926 u32 tile_offset;
52331309 8927 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8928};
8929
8930struct intel_display_error_state *
8931intel_display_capture_error_state(struct drm_device *dev)
8932{
0206e353 8933 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 8934 struct intel_display_error_state *error;
702e7a56 8935 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 8936 int i;
8937
8938 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8939 if (error == NULL)
8940 return NULL;
8941
52331309 8942 for_each_pipe(i) {
702e7a56
PZ		 8943 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8944
c4a1d9e4
CW		 8945 error->cursor[i].control = I915_READ(CURCNTR(i));
8946 error->cursor[i].position = I915_READ(CURPOS(i));
8947 error->cursor[i].base = I915_READ(CURBASE(i));
8948
8949 error->plane[i].control = I915_READ(DSPCNTR(i));
8950 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8951 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8952 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8953 error->plane[i].addr = I915_READ(DSPADDR(i));
8954 if (INTEL_INFO(dev)->gen >= 4) {
8955 error->plane[i].surface = I915_READ(DSPSURF(i));
8956 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8957 }
8958
702e7a56 8959 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 8960 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 8961 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8962 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8963 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8964 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8965 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8966 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 8967 }
8968
8969 return error;
8970}
8971
8972void
8973intel_display_print_error_state(struct seq_file *m,
8974 struct drm_device *dev,
8975 struct intel_display_error_state *error)
8976{
52331309 8977 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8978 int i;
8979
52331309
DL		 8980 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8981 for_each_pipe(i) {
c4a1d9e4
CW		 8982 seq_printf(m, "Pipe [%d]:\n", i);
8983 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8984 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8985 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8986 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8987 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8988 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8989 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8990 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8991
8992 seq_printf(m, "Plane [%d]:\n", i);
8993 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8994 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8995 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8996 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8997 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8998 if (INTEL_INFO(dev)->gen >= 4) {
8999 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9000 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9001 }
9002
9003 seq_printf(m, "Cursor [%d]:\n", i);
9004 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9005 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9006 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9007 }
9008}
9009#endif
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