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drm/i915: remove comment about IVB link training from intel_pm.c
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
15d199ea
PZ		 1230 if (!intel_using_power_well(dev_priv->dev) &&
1231 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
a0c4da24 1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
a416edef
ED		 1528/* SBI access */
1529static void
988d6ee8
PZ		 1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
a416edef 1532{
988d6ee8 1533 u32 tmp;
a416edef 1534
09153000 1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1540 return;
a416edef
ED		 1541 }
1542
988d6ee8
PZ		 1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1551
39fb50f6 1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1555 return;
a416edef 1556 }
a416edef
ED		 1557}
1558
1559static u32
988d6ee8
PZ		 1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
a416edef 1562{
39fb50f6 1563 u32 value = 0;
09153000 1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1569 return 0;
a416edef
ED		 1570 }
1571
988d6ee8
PZ		 1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1579
39fb50f6 1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1583 return 0;
a416edef
ED		 1584 }
1585
09153000 1586 return I915_READ(SBI_DATA);
a416edef
ED		 1587}
1588
92f2584a 1589/**
b6b4e185 1590 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
b6b4e185 1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1598{
ee7b9f93 1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1600 struct intel_pch_pll *pll;
92f2584a
JB		 1601 int reg;
1602 u32 val;
1603
48da64a8 1604 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1605 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
ee7b9f93
JB		 1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
92f2584a
JB		 1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
ee7b9f93 1620 if (pll->active++ && pll->on) {
92b27b08 1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
92f2584a
JB		 1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
ee7b9f93
JB		 1633
1634 pll->on = true;
92f2584a
JB		 1635}
1636
ee7b9f93 1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1638{
ee7b9f93
JB		 1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1641 int reg;
ee7b9f93 1642 u32 val;
4c609cb8 1643
92f2584a
JB		 1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1646 if (pll == NULL)
1647 return;
92f2584a 1648
48da64a8
CW		 1649 if (WARN_ON(pll->refcount == 0))
1650 return;
7a419866 1651
ee7b9f93
JB		 1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
7a419866 1655
48da64a8 1656 if (WARN_ON(pll->active == 0)) {
92b27b08 1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1658 return;
1659 }
1660
ee7b9f93 1661 if (--pll->active) {
92b27b08 1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1663 return;
ee7b9f93
JB		 1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1670
ee7b9f93 1671 reg = pll->pll_reg;
92f2584a
JB		 1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
ee7b9f93
JB		 1677
1678 pll->on = false;
92f2584a
JB		 1679}
1680
b8a4f404
PZ		 1681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
040484af 1683{
23670b32 1684 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1686 uint32_t reg, val, pipeconf_val;
040484af
JB		 1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
040484af
JB		 1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
23670b32
DV		 1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
59c859d6 1707 }
23670b32 1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
5f7f726d 1711 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
dfd07d72
DV		 1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1720 }
5f7f726d
PZ		 1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
040484af
JB		 1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
8fb033d7 1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1738 enum transcoder cpu_transcoder)
040484af 1739{
8fb033d7 1740 u32 val, pipeconf_val;
8fb033d7
PZ		 1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
8fb033d7 1745 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1748
223a6fdf
PZ		 1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
25f3ef11 1754 val = TRANS_ENABLE;
937bb610 1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1756
9a76b1c6
PZ		 1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
a35f2679 1759 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
25f3ef11 1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1766}
1767
b8a4f404
PZ		 1768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
040484af 1770{
23670b32
DV		 1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
040484af
JB		 1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
291906f1
JB		 1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
040484af
JB		 1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
040484af
JB		 1796}
1797
ab4d966c 1798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1799{
8fb033d7
PZ		 1800 u32 val;
1801
8a52fd9f 1802 val = I915_READ(_TRANSACONF);
8fb033d7 1803 val &= ~TRANS_ENABLE;
8a52fd9f 1804 I915_WRITE(_TRANSACONF, val);
8fb033d7 1805 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1812 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1a240d4d 1834 enum pipe pch_transcoder;
b24e7179
JB		 1835 int reg;
1836 u32 val;
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
8bb6e959
DV		 2005 /* Despite that we check this in framebuffer_init userspace can
2006 * screw us over and change the tiling after the fact. Only
2007 * pinned buffers can't change their tiling. */
2008 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2009 return -EINVAL;
2010 default:
2011 BUG();
2012 }
2013
693db184
CW		 2014 /* Note that the w/a also requires 64 PTE of padding following the
2015 * bo. We currently fill all unused PTE with the shadow page and so
2016 * we should always have valid PTE following the scanout preventing
2017 * the VT-d warning.
2018 */
2019 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2020 alignment = 256 * 1024;
2021
ce453d81 2022 dev_priv->mm.interruptible = false;
2da3b9b9 2023 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2024 if (ret)
ce453d81 2025 goto err_interruptible;
6b95a207
KH		 2026
2027 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028 * fence, whereas 965+ only requires a fence if using
2029 * framebuffer compression. For simplicity, we always install
2030 * a fence as the cost is not that onerous.
2031 */
06d98131 2032 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2033 if (ret)
2034 goto err_unpin;
1690e1eb 2035
9a5a53b3 2036 i915_gem_object_pin_fence(obj);
6b95a207 2037
ce453d81 2038 dev_priv->mm.interruptible = true;
6b95a207 2039 return 0;
48b956c5
CW		 2040
2041err_unpin:
2042 i915_gem_object_unpin(obj);
ce453d81
CW		 2043err_interruptible:
2044 dev_priv->mm.interruptible = true;
48b956c5 2045 return ret;
6b95a207
KH		 2046}
2047
1690e1eb
CW		 2048void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2049{
2050 i915_gem_object_unpin_fence(obj);
2051 i915_gem_object_unpin(obj);
2052}
2053
c2c75131
DV		 2054/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055 * is assumed to be a power-of-two. */
bc752862
CW		 2056unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2057 unsigned int tiling_mode,
2058 unsigned int cpp,
2059 unsigned int pitch)
c2c75131 2060{
bc752862
CW		 2061 if (tiling_mode != I915_TILING_NONE) {
2062 unsigned int tile_rows, tiles;
c2c75131 2063
bc752862
CW		 2064 tile_rows = *y / 8;
2065 *y %= 8;
c2c75131 2066
bc752862
CW		 2067 tiles = *x / (512/cpp);
2068 *x %= 512/cpp;
2069
2070 return tile_rows * pitch * 8 + tiles * 4096;
2071 } else {
2072 unsigned int offset;
2073
2074 offset = *y * pitch + *x * cpp;
2075 *y = 0;
2076 *x = (offset & 4095) / cpp;
2077 return offset & -4096;
2078 }
c2c75131
DV		 2079}
2080
17638cd6
JB		 2081static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2082 int x, int y)
81255565
JB		 2083{
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 struct intel_framebuffer *intel_fb;
05394f39 2088 struct drm_i915_gem_object *obj;
81255565 2089 int plane = intel_crtc->plane;
e506a0c6 2090 unsigned long linear_offset;
81255565 2091 u32 dspcntr;
5eddb70b 2092 u32 reg;
81255565
JB		 2093
2094 switch (plane) {
2095 case 0:
2096 case 1:
2097 break;
2098 default:
2099 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100 return -EINVAL;
2101 }
2102
2103 intel_fb = to_intel_framebuffer(fb);
2104 obj = intel_fb->obj;
81255565 2105
5eddb70b
CW		 2106 reg = DSPCNTR(plane);
2107 dspcntr = I915_READ(reg);
81255565
JB		 2108 /* Mask out pixel format bits in case we change it */
2109 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2110 switch (fb->pixel_format) {
2111 case DRM_FORMAT_C8:
81255565
JB		 2112 dspcntr |= DISPPLANE_8BPP;
2113 break;
57779d06
VS		 2114 case DRM_FORMAT_XRGB1555:
2115 case DRM_FORMAT_ARGB1555:
2116 dspcntr |= DISPPLANE_BGRX555;
81255565 2117 break;
57779d06
VS		 2118 case DRM_FORMAT_RGB565:
2119 dspcntr |= DISPPLANE_BGRX565;
2120 break;
2121 case DRM_FORMAT_XRGB8888:
2122 case DRM_FORMAT_ARGB8888:
2123 dspcntr |= DISPPLANE_BGRX888;
2124 break;
2125 case DRM_FORMAT_XBGR8888:
2126 case DRM_FORMAT_ABGR8888:
2127 dspcntr |= DISPPLANE_RGBX888;
2128 break;
2129 case DRM_FORMAT_XRGB2101010:
2130 case DRM_FORMAT_ARGB2101010:
2131 dspcntr |= DISPPLANE_BGRX101010;
2132 break;
2133 case DRM_FORMAT_XBGR2101010:
2134 case DRM_FORMAT_ABGR2101010:
2135 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2136 break;
2137 default:
baba133a 2138 BUG();
81255565 2139 }
57779d06 2140
a6c45cf0 2141 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2142 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2143 dspcntr |= DISPPLANE_TILED;
2144 else
2145 dspcntr &= ~DISPPLANE_TILED;
2146 }
2147
5eddb70b 2148 I915_WRITE(reg, dspcntr);
81255565 2149
e506a0c6 2150 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2151
c2c75131
DV		 2152 if (INTEL_INFO(dev)->gen >= 4) {
2153 intel_crtc->dspaddr_offset =
bc752862
CW		 2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155 fb->bits_per_pixel / 8,
2156 fb->pitches[0]);
c2c75131
DV		 2157 linear_offset -= intel_crtc->dspaddr_offset;
2158 } else {
e506a0c6 2159 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2160 }
e506a0c6
DV		 2161
2162 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2164 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2165 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2166 I915_MODIFY_DISPBASE(DSPSURF(plane),
2167 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2168 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2169 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2170 } else
e506a0c6 2171 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2172 POSTING_READ(reg);
81255565 2173
17638cd6
JB		 2174 return 0;
2175}
2176
2177static int ironlake_update_plane(struct drm_crtc *crtc,
2178 struct drm_framebuffer *fb, int x, int y)
2179{
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 struct intel_framebuffer *intel_fb;
2184 struct drm_i915_gem_object *obj;
2185 int plane = intel_crtc->plane;
e506a0c6 2186 unsigned long linear_offset;
17638cd6
JB		 2187 u32 dspcntr;
2188 u32 reg;
2189
2190 switch (plane) {
2191 case 0:
2192 case 1:
27f8227b 2193 case 2:
17638cd6
JB		 2194 break;
2195 default:
2196 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2197 return -EINVAL;
2198 }
2199
2200 intel_fb = to_intel_framebuffer(fb);
2201 obj = intel_fb->obj;
2202
2203 reg = DSPCNTR(plane);
2204 dspcntr = I915_READ(reg);
2205 /* Mask out pixel format bits in case we change it */
2206 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2207 switch (fb->pixel_format) {
2208 case DRM_FORMAT_C8:
17638cd6
JB		 2209 dspcntr |= DISPPLANE_8BPP;
2210 break;
57779d06
VS		 2211 case DRM_FORMAT_RGB565:
2212 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2213 break;
57779d06
VS		 2214 case DRM_FORMAT_XRGB8888:
2215 case DRM_FORMAT_ARGB8888:
2216 dspcntr |= DISPPLANE_BGRX888;
2217 break;
2218 case DRM_FORMAT_XBGR8888:
2219 case DRM_FORMAT_ABGR8888:
2220 dspcntr |= DISPPLANE_RGBX888;
2221 break;
2222 case DRM_FORMAT_XRGB2101010:
2223 case DRM_FORMAT_ARGB2101010:
2224 dspcntr |= DISPPLANE_BGRX101010;
2225 break;
2226 case DRM_FORMAT_XBGR2101010:
2227 case DRM_FORMAT_ABGR2101010:
2228 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2229 break;
2230 default:
baba133a 2231 BUG();
17638cd6
JB		 2232 }
2233
2234 if (obj->tiling_mode != I915_TILING_NONE)
2235 dspcntr |= DISPPLANE_TILED;
2236 else
2237 dspcntr &= ~DISPPLANE_TILED;
2238
2239 /* must disable */
2240 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2241
2242 I915_WRITE(reg, dspcntr);
2243
e506a0c6 2244 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2245 intel_crtc->dspaddr_offset =
bc752862
CW		 2246 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2247 fb->bits_per_pixel / 8,
2248 fb->pitches[0]);
c2c75131 2249 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2250
e506a0c6
DV		 2251 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2253 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2254 I915_MODIFY_DISPBASE(DSPSURF(plane),
2255 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2256 if (IS_HASWELL(dev)) {
2257 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2258 } else {
2259 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2260 I915_WRITE(DSPLINOFF(plane), linear_offset);
2261 }
17638cd6
JB		 2262 POSTING_READ(reg);
2263
2264 return 0;
2265}
2266
2267/* Assume fb object is pinned & idle & fenced and just update base pointers */
2268static int
2269intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2270 int x, int y, enum mode_set_atomic state)
2271{
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2274
6b8e6ed0
CW		 2275 if (dev_priv->display.disable_fbc)
2276 dev_priv->display.disable_fbc(dev);
3dec0095 2277 intel_increase_pllclock(crtc);
81255565 2278
6b8e6ed0 2279 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2280}
2281
96a02917
VS		 2282void intel_display_handle_reset(struct drm_device *dev)
2283{
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct drm_crtc *crtc;
2286
2287 /*
2288 * Flips in the rings have been nuked by the reset,
2289 * so complete all pending flips so that user space
2290 * will get its events and not get stuck.
2291 *
2292 * Also update the base address of all primary
2293 * planes to the the last fb to make sure we're
2294 * showing the correct fb after a reset.
2295 *
2296 * Need to make two loops over the crtcs so that we
2297 * don't try to grab a crtc mutex before the
2298 * pending_flip_queue really got woken up.
2299 */
2300
2301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303 enum plane plane = intel_crtc->plane;
2304
2305 intel_prepare_page_flip(dev, plane);
2306 intel_finish_page_flip_plane(dev, plane);
2307 }
2308
2309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312 mutex_lock(&crtc->mutex);
2313 if (intel_crtc->active)
2314 dev_priv->display.update_plane(crtc, crtc->fb,
2315 crtc->x, crtc->y);
2316 mutex_unlock(&crtc->mutex);
2317 }
2318}
2319
14667a4b
CW		 2320static int
2321intel_finish_fb(struct drm_framebuffer *old_fb)
2322{
2323 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2324 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2325 bool was_interruptible = dev_priv->mm.interruptible;
2326 int ret;
2327
14667a4b
CW		 2328 /* Big Hammer, we also need to ensure that any pending
2329 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330 * current scanout is retired before unpinning the old
2331 * framebuffer.
2332 *
2333 * This should only fail upon a hung GPU, in which case we
2334 * can safely continue.
2335 */
2336 dev_priv->mm.interruptible = false;
2337 ret = i915_gem_object_finish_gpu(obj);
2338 dev_priv->mm.interruptible = was_interruptible;
2339
2340 return ret;
2341}
2342
198598d0
VS		 2343static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2344{
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_master_private *master_priv;
2347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2348
2349 if (!dev->primary->master)
2350 return;
2351
2352 master_priv = dev->primary->master->driver_priv;
2353 if (!master_priv->sarea_priv)
2354 return;
2355
2356 switch (intel_crtc->pipe) {
2357 case 0:
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 break;
2361 case 1:
2362 master_priv->sarea_priv->pipeB_x = x;
2363 master_priv->sarea_priv->pipeB_y = y;
2364 break;
2365 default:
2366 break;
2367 }
2368}
2369
5c3b82e2 2370static int
3c4fdcfb 2371intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2372 struct drm_framebuffer *fb)
79e53945
JB		 2373{
2374 struct drm_device *dev = crtc->dev;
6b8e6ed0 2375 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2377 struct drm_framebuffer *old_fb;
5c3b82e2 2378 int ret;
79e53945
JB		 2379
2380 /* no fb bound */
94352cf9 2381 if (!fb) {
a5071c2f 2382 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2383 return 0;
2384 }
2385
7eb552ae 2386 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2387 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2388 intel_crtc->plane,
7eb552ae 2389 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2390 return -EINVAL;
79e53945
JB		 2391 }
2392
5c3b82e2 2393 mutex_lock(&dev->struct_mutex);
265db958 2394 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2395 to_intel_framebuffer(fb)->obj,
919926ae 2396 NULL);
5c3b82e2
CW		 2397 if (ret != 0) {
2398 mutex_unlock(&dev->struct_mutex);
a5071c2f 2399 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2400 return ret;
2401 }
79e53945 2402
94352cf9 2403 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2404 if (ret) {
94352cf9 2405 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2406 mutex_unlock(&dev->struct_mutex);
a5071c2f 2407 DRM_ERROR("failed to update base address\n");
4e6cfefc 2408 return ret;
79e53945 2409 }
3c4fdcfb 2410
94352cf9
DV		 2411 old_fb = crtc->fb;
2412 crtc->fb = fb;
6c4c86f5
DV		 2413 crtc->x = x;
2414 crtc->y = y;
94352cf9 2415
b7f1de28
CW		 2416 if (old_fb) {
2417 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2419 }
652c393a 2420
6b8e6ed0 2421 intel_update_fbc(dev);
5c3b82e2 2422 mutex_unlock(&dev->struct_mutex);
79e53945 2423
198598d0 2424 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2425
2426 return 0;
79e53945
JB		 2427}
2428
5e84e1a4
ZW		 2429static void intel_fdi_normal_train(struct drm_crtc *crtc)
2430{
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434 int pipe = intel_crtc->pipe;
2435 u32 reg, temp;
2436
2437 /* enable normal train */
2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
61e499bf 2440 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2441 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2442 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2443 } else {
2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2446 }
5e84e1a4
ZW		 2447 I915_WRITE(reg, temp);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 if (HAS_PCH_CPT(dev)) {
2452 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2453 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2454 } else {
2455 temp &= ~FDI_LINK_TRAIN_NONE;
2456 temp |= FDI_LINK_TRAIN_NONE;
2457 }
2458 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2459
2460 /* wait one idle pattern time */
2461 POSTING_READ(reg);
2462 udelay(1000);
357555c0
JB		 2463
2464 /* IVB wants error correction enabled */
2465 if (IS_IVYBRIDGE(dev))
2466 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2467 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2468}
2469
01a415fd
DV		 2470static void ivb_modeset_global_resources(struct drm_device *dev)
2471{
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *pipe_B_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2475 struct intel_crtc *pipe_C_crtc =
2476 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477 uint32_t temp;
2478
2479 /* When everything is off disable fdi C so that we could enable fdi B
2480 * with all lanes. XXX: This misses the case where a pipe is not using
2481 * any pch resources and so doesn't need any fdi lanes. */
2482 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485
2486 temp = I915_READ(SOUTH_CHICKEN1);
2487 temp &= ~FDI_BC_BIFURCATION_SELECT;
2488 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489 I915_WRITE(SOUTH_CHICKEN1, temp);
2490 }
2491}
2492
8db9d77b
ZW		 2493/* The FDI link training functions for ILK/Ibexpeak. */
2494static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2495{
2496 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 int pipe = intel_crtc->pipe;
0fc932b8 2500 int plane = intel_crtc->plane;
5eddb70b 2501 u32 reg, temp, tries;
8db9d77b 2502
0fc932b8
JB		 2503 /* FDI needs bits from pipe & plane first */
2504 assert_pipe_enabled(dev_priv, pipe);
2505 assert_plane_enabled(dev_priv, plane);
2506
e1a44743
AJ		 2507 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 for train result */
5eddb70b
CW		 2509 reg = FDI_RX_IMR(pipe);
2510 temp = I915_READ(reg);
e1a44743
AJ		 2511 temp &= ~FDI_RX_SYMBOL_LOCK;
2512 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2513 I915_WRITE(reg, temp);
2514 I915_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2524 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2525
5eddb70b
CW		 2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 temp &= ~FDI_LINK_TRAIN_NONE;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(150);
2534
5b2adf89 2535 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2538 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2539
5eddb70b 2540 reg = FDI_RX_IIR(pipe);
e1a44743 2541 for (tries = 0; tries < 5; tries++) {
5eddb70b 2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545 if ((temp & FDI_RX_BIT_LOCK)) {
2546 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2548 break;
2549 }
8db9d77b 2550 }
e1a44743 2551 if (tries == 5)
5eddb70b 2552 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2553
2554 /* Train 2 */
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2559 I915_WRITE(reg, temp);
8db9d77b 2560
5eddb70b
CW		 2561 reg = FDI_RX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2565 I915_WRITE(reg, temp);
8db9d77b 2566
5eddb70b
CW		 2567 POSTING_READ(reg);
2568 udelay(150);
8db9d77b 2569
5eddb70b 2570 reg = FDI_RX_IIR(pipe);
e1a44743 2571 for (tries = 0; tries < 5; tries++) {
5eddb70b 2572 temp = I915_READ(reg);
8db9d77b
ZW		 2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
8db9d77b 2580 }
e1a44743 2581 if (tries == 5)
5eddb70b 2582 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2583
2584 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2585
8db9d77b
ZW		 2586}
2587
0206e353 2588static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2589 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2590 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2591 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2592 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2593};
2594
2595/* The FDI link training functions for SNB/Cougarpoint. */
2596static void gen6_fdi_link_train(struct drm_crtc *crtc)
2597{
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
fa37d39e 2602 u32 reg, temp, i, retry;
8db9d77b 2603
e1a44743
AJ		 2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605 for train result */
5eddb70b
CW		 2606 reg = FDI_RX_IMR(pipe);
2607 temp = I915_READ(reg);
e1a44743
AJ		 2608 temp &= ~FDI_RX_SYMBOL_LOCK;
2609 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
e1a44743
AJ		 2613 udelay(150);
2614
8db9d77b 2615 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
77ffb597
AJ		 2618 temp &= ~(7 << 19);
2619 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2620 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623 /* SNB-B */
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2625 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2626
d74cf324
DV		 2627 I915_WRITE(FDI_RX_MISC(pipe),
2628 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2629
5eddb70b
CW		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
8db9d77b
ZW		 2632 if (HAS_PCH_CPT(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 } else {
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_1;
2638 }
5eddb70b
CW		 2639 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2640
2641 POSTING_READ(reg);
8db9d77b
ZW		 2642 udelay(150);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
8db9d77b
ZW		 2652 udelay(500);
2653
fa37d39e
SP		 2654 for (retry = 0; retry < 5; retry++) {
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_BIT_LOCK) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661 break;
2662 }
2663 udelay(50);
8db9d77b 2664 }
fa37d39e
SP		 2665 if (retry < 5)
2666 break;
8db9d77b
ZW		 2667 }
2668 if (i == 4)
5eddb70b 2669 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2670
2671 /* Train 2 */
5eddb70b
CW		 2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
8db9d77b
ZW		 2674 temp &= ~FDI_LINK_TRAIN_NONE;
2675 temp |= FDI_LINK_TRAIN_PATTERN_2;
2676 if (IS_GEN6(dev)) {
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 /* SNB-B */
2679 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2680 }
5eddb70b 2681 I915_WRITE(reg, temp);
8db9d77b 2682
5eddb70b
CW		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
8db9d77b
ZW		 2685 if (HAS_PCH_CPT(dev)) {
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688 } else {
2689 temp &= ~FDI_LINK_TRAIN_NONE;
2690 temp |= FDI_LINK_TRAIN_PATTERN_2;
2691 }
5eddb70b
CW		 2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
8db9d77b
ZW		 2695 udelay(150);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
8db9d77b
ZW		 2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
8db9d77b
ZW		 2705 udelay(500);
2706
fa37d39e
SP		 2707 for (retry = 0; retry < 5; retry++) {
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711 if (temp & FDI_RX_SYMBOL_LOCK) {
2712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2714 break;
2715 }
2716 udelay(50);
8db9d77b 2717 }
fa37d39e
SP		 2718 if (retry < 5)
2719 break;
8db9d77b
ZW		 2720 }
2721 if (i == 4)
5eddb70b 2722 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2723
2724 DRM_DEBUG_KMS("FDI train done.\n");
2725}
2726
357555c0
JB		 2727/* Manual link training for Ivy Bridge A0 parts */
2728static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2729{
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp, i;
2735
2736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2737 for train result */
2738 reg = FDI_RX_IMR(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_RX_SYMBOL_LOCK;
2741 temp &= ~FDI_RX_BIT_LOCK;
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
01a415fd
DV		 2747 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748 I915_READ(FDI_RX_IIR(pipe)));
2749
357555c0
JB		 2750 /* enable CPU FDI TX and PCH FDI RX */
2751 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 temp &= ~(7 << 19);
2754 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2755 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2759 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2760 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2761
d74cf324
DV		 2762 I915_WRITE(FDI_RX_MISC(pipe),
2763 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2764
357555c0
JB		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_AUTO;
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2770 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2771 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(150);
2775
0206e353 2776 for (i = 0; i < 4; i++) {
357555c0
JB		 2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780 temp |= snb_b_fdi_train_param[i];
2781 I915_WRITE(reg, temp);
2782
2783 POSTING_READ(reg);
2784 udelay(500);
2785
2786 reg = FDI_RX_IIR(pipe);
2787 temp = I915_READ(reg);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789
2790 if (temp & FDI_RX_BIT_LOCK ||
2791 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2792 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2793 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2794 break;
2795 }
2796 }
2797 if (i == 4)
2798 DRM_ERROR("FDI train 1 fail!\n");
2799
2800 /* Train 2 */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2805 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2806 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(150);
2817
0206e353 2818 for (i = 0; i < 4; i++) {
357555c0
JB		 2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2822 temp |= snb_b_fdi_train_param[i];
2823 I915_WRITE(reg, temp);
2824
2825 POSTING_READ(reg);
2826 udelay(500);
2827
2828 reg = FDI_RX_IIR(pipe);
2829 temp = I915_READ(reg);
2830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2831
2832 if (temp & FDI_RX_SYMBOL_LOCK) {
2833 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2834 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2835 break;
2836 }
2837 }
2838 if (i == 4)
2839 DRM_ERROR("FDI train 2 fail!\n");
2840
2841 DRM_DEBUG_KMS("FDI train done.\n");
2842}
2843
88cefb6c 2844static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2845{
88cefb6c 2846 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2847 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2848 int pipe = intel_crtc->pipe;
5eddb70b 2849 u32 reg, temp;
79e53945 2850
c64e311e 2851
c98e9dcf 2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2856 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2858 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859
2860 POSTING_READ(reg);
c98e9dcf
JB		 2861 udelay(200);
2862
2863 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp | FDI_PCDCLK);
2866
2867 POSTING_READ(reg);
c98e9dcf
JB		 2868 udelay(200);
2869
20749730
PZ		 2870 /* Enable CPU FDI TX PLL, always on for Ironlake */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2874 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2875
20749730
PZ		 2876 POSTING_READ(reg);
2877 udelay(100);
6be4a607 2878 }
0e23b99d
JB		 2879}
2880
88cefb6c
DV		 2881static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2882{
2883 struct drm_device *dev = intel_crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 int pipe = intel_crtc->pipe;
2886 u32 reg, temp;
2887
2888 /* Switch from PCDclk to Rawclk */
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893 /* Disable CPU FDI TX PLL */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900
2901 reg = FDI_RX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905 /* Wait for the clocks to turn off. */
2906 POSTING_READ(reg);
2907 udelay(100);
2908}
2909
0fc932b8
JB		 2910static void ironlake_fdi_disable(struct drm_crtc *crtc)
2911{
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2915 int pipe = intel_crtc->pipe;
2916 u32 reg, temp;
2917
2918 /* disable CPU FDI tx and PCH FDI rx */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2922 POSTING_READ(reg);
2923
2924 reg = FDI_RX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~(0x7 << 16);
dfd07d72 2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2928 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2929
2930 POSTING_READ(reg);
2931 udelay(100);
2932
2933 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2934 if (HAS_PCH_IBX(dev)) {
2935 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2936 }
0fc932b8
JB		 2937
2938 /* still set train pattern 1 */
2939 reg = FDI_TX_CTL(pipe);
2940 temp = I915_READ(reg);
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 I915_WRITE(reg, temp);
2944
2945 reg = FDI_RX_CTL(pipe);
2946 temp = I915_READ(reg);
2947 if (HAS_PCH_CPT(dev)) {
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950 } else {
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 }
2954 /* BPC in FDI rx is consistent with that in PIPECONF */
2955 temp &= ~(0x07 << 16);
dfd07d72 2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(100);
2961}
2962
5bb61643
CW		 2963static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2964{
2965 struct drm_device *dev = crtc->dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2968 unsigned long flags;
2969 bool pending;
2970
10d83730
VS		 2971 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2973 return false;
2974
2975 spin_lock_irqsave(&dev->event_lock, flags);
2976 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977 spin_unlock_irqrestore(&dev->event_lock, flags);
2978
2979 return pending;
2980}
2981
e6c3a2a6
CW		 2982static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2983{
0f91128d 2984 struct drm_device *dev = crtc->dev;
5bb61643 2985 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2986
2987 if (crtc->fb == NULL)
2988 return;
2989
2c10d571
DV		 2990 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2991
5bb61643
CW		 2992 wait_event(dev_priv->pending_flip_queue,
2993 !intel_crtc_has_pending_flip(crtc));
2994
0f91128d
CW		 2995 mutex_lock(&dev->struct_mutex);
2996 intel_finish_fb(crtc->fb);
2997 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2998}
2999
e615efe4
ED		 3000/* Program iCLKIP clock to the desired frequency */
3001static void lpt_program_iclkip(struct drm_crtc *crtc)
3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 u32 temp;
3007
09153000
DV		 3008 mutex_lock(&dev_priv->dpio_lock);
3009
e615efe4
ED		 3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3012 */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3017 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018 SBI_SSCCTL_DISABLE,
3019 SBI_ICLK);
e615efe4
ED		 3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc->mode.clock == 20000) {
3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053 crtc->mode.clock,
3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
988d6ee8 3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3067 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3068
3069 /* Program SSCAUXDIV */
988d6ee8 3070 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3071 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Enable modulator and associated divider */
988d6ee8 3076 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3077 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3078 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3079
3080 /* Wait for initialization time */
3081 udelay(24);
3082
3083 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3084
3085 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3086}
3087
f67a559d
JB		 3088/*
3089 * Enable PCH resources required for PCH ports:
3090 * - PCH PLLs
3091 * - FDI training & RX/TX
3092 * - update transcoder timings
3093 * - DP transcoding bits
3094 * - transcoder
3095 */
3096static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3097{
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
ee7b9f93 3102 u32 reg, temp;
2c07245f 3103
e7e164db
CW		 3104 assert_transcoder_disabled(dev_priv, pipe);
3105
cd986abb
DV		 3106 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */
3108 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3109 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3110
c98e9dcf 3111 /* For PCH output, training FDI link */
674cf967 3112 dev_priv->display.fdi_link_train(crtc);
2c07245f 3113
572deb37
DV		 3114 /* XXX: pch pll's can be enabled any time before we enable the PCH
3115 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it.
3117 *
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119 * unconditionally resets the pll - we need that to have the right LVDS
3120 * enable sequence. */
b6b4e185 3121 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3122
303b81e0 3123 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3124 u32 sel;
4b645f14 3125
c98e9dcf 3126 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3127 switch (pipe) {
3128 default:
3129 case 0:
3130 temp |= TRANSA_DPLL_ENABLE;
3131 sel = TRANSA_DPLLB_SEL;
3132 break;
3133 case 1:
3134 temp |= TRANSB_DPLL_ENABLE;
3135 sel = TRANSB_DPLLB_SEL;
3136 break;
3137 case 2:
3138 temp |= TRANSC_DPLL_ENABLE;
3139 sel = TRANSC_DPLLB_SEL;
3140 break;
d64311ab 3141 }
ee7b9f93
JB		 3142 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143 temp |= sel;
3144 else
3145 temp &= ~sel;
c98e9dcf 3146 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3147 }
5eddb70b 3148
d9b6cb56
JB		 3149 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3151 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3152 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3154
5eddb70b
CW		 3155 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3159
303b81e0 3160 intel_fdi_normal_train(crtc);
5e84e1a4 3161
c98e9dcf
JB		 3162 /* For PCH DP, enable TRANS_DP_CTL */
3163 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3164 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3165 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3167 reg = TRANS_DP_CTL(pipe);
3168 temp = I915_READ(reg);
3169 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3170 TRANS_DP_SYNC_MASK |
3171 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3172 temp |= (TRANS_DP_OUTPUT_ENABLE |
3173 TRANS_DP_ENH_FRAMING);
9325c9f0 3174 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3175
3176 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3177 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3178 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3179 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3180
3181 switch (intel_trans_dp_port_sel(crtc)) {
3182 case PCH_DP_B:
5eddb70b 3183 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3184 break;
3185 case PCH_DP_C:
5eddb70b 3186 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3187 break;
3188 case PCH_DP_D:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3190 break;
3191 default:
e95d41e1 3192 BUG();
32f9d658 3193 }
2c07245f 3194
5eddb70b 3195 I915_WRITE(reg, temp);
6be4a607 3196 }
b52eb4dc 3197
b8a4f404 3198 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3199}
3200
1507e5bd
PZ		 3201static void lpt_pch_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3206 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3207
daed2dbb 3208 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3209
8c52b5e8 3210 lpt_program_iclkip(crtc);
1507e5bd 3211
0540e488 3212 /* Set transcoder timing. */
daed2dbb
PZ		 3213 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3214 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3216
daed2dbb
PZ		 3217 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3221
937bb610 3222 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3223}
3224
ee7b9f93
JB		 3225static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3226{
3227 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3228
3229 if (pll == NULL)
3230 return;
3231
3232 if (pll->refcount == 0) {
3233 WARN(1, "bad PCH PLL refcount\n");
3234 return;
3235 }
3236
3237 --pll->refcount;
3238 intel_crtc->pch_pll = NULL;
3239}
3240
3241static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3242{
3243 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3244 struct intel_pch_pll *pll;
3245 int i;
3246
3247 pll = intel_crtc->pch_pll;
3248 if (pll) {
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250 intel_crtc->base.base.id, pll->pll_reg);
3251 goto prepare;
3252 }
3253
98b6bd99
DV		 3254 if (HAS_PCH_IBX(dev_priv->dev)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i = intel_crtc->pipe;
3257 pll = &dev_priv->pch_plls[i];
3258
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260 intel_crtc->base.base.id, pll->pll_reg);
3261
3262 goto found;
3263 }
3264
ee7b9f93
JB		 3265 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3266 pll = &dev_priv->pch_plls[i];
3267
3268 /* Only want to check enabled timings first */
3269 if (pll->refcount == 0)
3270 continue;
3271
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3273 fp == I915_READ(pll->fp0_reg)) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275 intel_crtc->base.base.id,
3276 pll->pll_reg, pll->refcount, pll->active);
3277
3278 goto found;
3279 }
3280 }
3281
3282 /* Ok no matching timings, maybe there's a free one? */
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3285 if (pll->refcount == 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287 intel_crtc->base.base.id, pll->pll_reg);
3288 goto found;
3289 }
3290 }
3291
3292 return NULL;
3293
3294found:
3295 intel_crtc->pch_pll = pll;
3296 pll->refcount++;
3297 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3298prepare: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3300
e04c7350
CW		 3301 /* Wait for the clocks to stabilize before rewriting the regs */
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3303 POSTING_READ(pll->pll_reg);
3304 udelay(150);
e04c7350
CW		 3305
3306 I915_WRITE(pll->fp0_reg, fp);
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3308 pll->on = false;
3309 return pll;
3310}
3311
d4270e57
JB		 3312void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3313{
3314 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3315 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3316 u32 temp;
3317
3318 temp = I915_READ(dslreg);
3319 udelay(500);
3320 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3321 if (wait_for(I915_READ(dslreg) != temp, 5))
3322 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3323 }
3324}
3325
f67a559d
JB		 3326static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3331 struct intel_encoder *encoder;
f67a559d
JB		 3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
3334 u32 temp;
f67a559d 3335
08a48469
DV		 3336 WARN_ON(!crtc->enabled);
3337
f67a559d
JB		 3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
3342 intel_update_watermarks(dev);
3343
3344 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3345 temp = I915_READ(PCH_LVDS);
3346 if ((temp & LVDS_PORT_EN) == 0)
3347 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3348 }
3349
f67a559d 3350
5bfe2ac0 3351 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3352 /* Note: FDI PLL enabling _must_ be done before we enable the
3353 * cpu pipes, hence this is separate from all the other fdi/pch
3354 * enabling. */
88cefb6c 3355 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3356 } else {
3357 assert_fdi_tx_disabled(dev_priv, pipe);
3358 assert_fdi_rx_disabled(dev_priv, pipe);
3359 }
f67a559d 3360
bf49ec8c
DV		 3361 for_each_encoder_on_crtc(dev, crtc, encoder)
3362 if (encoder->pre_enable)
3363 encoder->pre_enable(encoder);
f67a559d
JB		 3364
3365 /* Enable panel fitting for LVDS */
3366 if (dev_priv->pch_pf_size &&
547dc041
JN		 3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3369 /* Force use of hard-coded filter coefficients
3370 * as some pre-programmed values are broken,
3371 * e.g. x201.
3372 */
13888d78
PZ		 3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3375 PF_PIPE_SEL_IVB(pipe));
3376 else
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3378 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3379 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3380 }
3381
9c54c0dd
JB		 3382 /*
3383 * On ILK+ LUT must be loaded before the pipe is running but with
3384 * clocks enabled
3385 */
3386 intel_crtc_load_lut(crtc);
3387
5bfe2ac0
DV		 3388 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3390 intel_enable_plane(dev_priv, plane, pipe);
3391
5bfe2ac0 3392 if (intel_crtc->config.has_pch_encoder)
f67a559d 3393 ironlake_pch_enable(crtc);
c98e9dcf 3394
d1ebd816 3395 mutex_lock(&dev->struct_mutex);
bed4a673 3396 intel_update_fbc(dev);
d1ebd816
BW		 3397 mutex_unlock(&dev->struct_mutex);
3398
6b383a7f 3399 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3400
fa5c73b1
DV		 3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 encoder->enable(encoder);
61b77ddd
DV		 3403
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3406
3407 /*
3408 * There seems to be a race in PCH platform hw (at least on some
3409 * outputs) where an enabled pipe still completes any pageflip right
3410 * away (as if the pipe is off) instead of waiting for vblank. As soon
3411 * as the first vblank happend, everything works as expected. Hence just
3412 * wait for one vblank before returning to avoid strange things
3413 * happening.
3414 */
3415 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3416}
3417
4f771f10
PZ		 3418static void haswell_crtc_enable(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 struct intel_encoder *encoder;
3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
4f771f10
PZ		 3426
3427 WARN_ON(!crtc->enabled);
3428
3429 if (intel_crtc->active)
3430 return;
3431
3432 intel_crtc->active = true;
3433 intel_update_watermarks(dev);
3434
5bfe2ac0 3435 if (intel_crtc->config.has_pch_encoder)
04945641 3436 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3437
3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 if (encoder->pre_enable)
3440 encoder->pre_enable(encoder);
3441
1f544388 3442 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3443
1f544388 3444 /* Enable panel fitting for eDP */
547dc041
JN		 3445 if (dev_priv->pch_pf_size &&
3446 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3447 /* Force use of hard-coded filter coefficients
3448 * as some pre-programmed values are broken,
3449 * e.g. x201.
3450 */
54075a7d
PZ		 3451 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3452 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3453 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3454 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3455 }
3456
3457 /*
3458 * On ILK+ LUT must be loaded before the pipe is running but with
3459 * clocks enabled
3460 */
3461 intel_crtc_load_lut(crtc);
3462
1f544388 3463 intel_ddi_set_pipe_settings(crtc);
8228c251 3464 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3465
5bfe2ac0
DV		 3466 intel_enable_pipe(dev_priv, pipe,
3467 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3468 intel_enable_plane(dev_priv, plane, pipe);
3469
5bfe2ac0 3470 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3471 lpt_pch_enable(crtc);
4f771f10
PZ		 3472
3473 mutex_lock(&dev->struct_mutex);
3474 intel_update_fbc(dev);
3475 mutex_unlock(&dev->struct_mutex);
3476
3477 intel_crtc_update_cursor(crtc, true);
3478
3479 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 encoder->enable(encoder);
3481
4f771f10
PZ		 3482 /*
3483 * There seems to be a race in PCH platform hw (at least on some
3484 * outputs) where an enabled pipe still completes any pageflip right
3485 * away (as if the pipe is off) instead of waiting for vblank. As soon
3486 * as the first vblank happend, everything works as expected. Hence just
3487 * wait for one vblank before returning to avoid strange things
3488 * happening.
3489 */
3490 intel_wait_for_vblank(dev, intel_crtc->pipe);
3491}
3492
6be4a607
JB		 3493static void ironlake_crtc_disable(struct drm_crtc *crtc)
3494{
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3498 struct intel_encoder *encoder;
6be4a607
JB		 3499 int pipe = intel_crtc->pipe;
3500 int plane = intel_crtc->plane;
5eddb70b 3501 u32 reg, temp;
b52eb4dc 3502
ef9c3aee 3503
f7abfe8b
CW		 3504 if (!intel_crtc->active)
3505 return;
3506
ea9d758d
DV		 3507 for_each_encoder_on_crtc(dev, crtc, encoder)
3508 encoder->disable(encoder);
3509
e6c3a2a6 3510 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3511 drm_vblank_off(dev, pipe);
6b383a7f 3512 intel_crtc_update_cursor(crtc, false);
5eddb70b 3513
b24e7179 3514 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3515
973d04f9
CW		 3516 if (dev_priv->cfb_plane == plane)
3517 intel_disable_fbc(dev);
2c07245f 3518
b24e7179 3519 intel_disable_pipe(dev_priv, pipe);
32f9d658 3520
6be4a607 3521 /* Disable PF */
9db4a9c7
JB		 3522 I915_WRITE(PF_CTL(pipe), 0);
3523 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3524
bf49ec8c
DV		 3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
2c07245f 3528
0fc932b8 3529 ironlake_fdi_disable(crtc);
249c0e64 3530
b8a4f404 3531 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3532
6be4a607
JB		 3533 if (HAS_PCH_CPT(dev)) {
3534 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3535 reg = TRANS_DP_CTL(pipe);
3536 temp = I915_READ(reg);
3537 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3538 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3539 I915_WRITE(reg, temp);
6be4a607
JB		 3540
3541 /* disable DPLL_SEL */
3542 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3543 switch (pipe) {
3544 case 0:
d64311ab 3545 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3546 break;
3547 case 1:
6be4a607 3548 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3549 break;
3550 case 2:
4b645f14 3551 /* C shares PLL A or B */
d64311ab 3552 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3553 break;
3554 default:
3555 BUG(); /* wtf */
3556 }
6be4a607 3557 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3558 }
e3421a18 3559
6be4a607 3560 /* disable PCH DPLL */
ee7b9f93 3561 intel_disable_pch_pll(intel_crtc);
8db9d77b 3562
88cefb6c 3563 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3564
f7abfe8b 3565 intel_crtc->active = false;
6b383a7f 3566 intel_update_watermarks(dev);
d1ebd816
BW		 3567
3568 mutex_lock(&dev->struct_mutex);
6b383a7f 3569 intel_update_fbc(dev);
d1ebd816 3570 mutex_unlock(&dev->struct_mutex);
6be4a607 3571}
1b3c7a47 3572
4f771f10 3573static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3574{
4f771f10
PZ		 3575 struct drm_device *dev = crtc->dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3578 struct intel_encoder *encoder;
3579 int pipe = intel_crtc->pipe;
3580 int plane = intel_crtc->plane;
ad80a810 3581 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee7b9f93 3582
4f771f10
PZ		 3583 if (!intel_crtc->active)
3584 return;
3585
3586 for_each_encoder_on_crtc(dev, crtc, encoder)
3587 encoder->disable(encoder);
3588
3589 intel_crtc_wait_for_pending_flips(crtc);
3590 drm_vblank_off(dev, pipe);
3591 intel_crtc_update_cursor(crtc, false);
3592
3593 intel_disable_plane(dev_priv, plane, pipe);
3594
3595 if (dev_priv->cfb_plane == plane)
3596 intel_disable_fbc(dev);
3597
3598 intel_disable_pipe(dev_priv, pipe);
3599
ad80a810 3600 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3601
f7708f78
PZ		 3602 /* XXX: Once we have proper panel fitter state tracking implemented with
3603 * hardware state read/check support we should switch to only disable
3604 * the panel fitter when we know it's used. */
3605 if (intel_using_power_well(dev)) {
3606 I915_WRITE(PF_CTL(pipe), 0);
3607 I915_WRITE(PF_WIN_SZ(pipe), 0);
3608 }
4f771f10 3609
1f544388 3610 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3611
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 if (encoder->post_disable)
3614 encoder->post_disable(encoder);
3615
88adfff1 3616 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3617 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3618 intel_ddi_fdi_disable(crtc);
83616634 3619 }
4f771f10
PZ		 3620
3621 intel_crtc->active = false;
3622 intel_update_watermarks(dev);
3623
3624 mutex_lock(&dev->struct_mutex);
3625 intel_update_fbc(dev);
3626 mutex_unlock(&dev->struct_mutex);
3627}
3628
ee7b9f93
JB		 3629static void ironlake_crtc_off(struct drm_crtc *crtc)
3630{
3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632 intel_put_pch_pll(intel_crtc);
3633}
3634
6441ab5f
PZ		 3635static void haswell_crtc_off(struct drm_crtc *crtc)
3636{
a5c961d1
PZ		 3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638
3639 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640 * start using it. */
1a240d4d 3641 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3642
6441ab5f
PZ		 3643 intel_ddi_put_crtc_pll(crtc);
3644}
3645
02e792fb
DV		 3646static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3647{
02e792fb 3648 if (!enable && intel_crtc->overlay) {
23f09ce3 3649 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3650 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3651
23f09ce3 3652 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3653 dev_priv->mm.interruptible = false;
3654 (void) intel_overlay_switch_off(intel_crtc->overlay);
3655 dev_priv->mm.interruptible = true;
23f09ce3 3656 mutex_unlock(&dev->struct_mutex);
02e792fb 3657 }
02e792fb 3658
5dcdbcb0
CW		 3659 /* Let userspace switch the overlay on again. In most cases userspace
3660 * has to recompute where to put it anyway.
3661 */
02e792fb
DV		 3662}
3663
61bc95c1
EE		 3664/**
3665 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3666 * cursor plane briefly if not already running after enabling the display
3667 * plane.
3668 * This workaround avoids occasional blank screens when self refresh is
3669 * enabled.
3670 */
3671static void
3672g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3673{
3674 u32 cntl = I915_READ(CURCNTR(pipe));
3675
3676 if ((cntl & CURSOR_MODE) == 0) {
3677 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3678
3679 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3680 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3681 intel_wait_for_vblank(dev_priv->dev, pipe);
3682 I915_WRITE(CURCNTR(pipe), cntl);
3683 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3685 }
3686}
3687
0b8765c6 3688static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3689{
3690 struct drm_device *dev = crtc->dev;
79e53945
JB		 3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3693 struct intel_encoder *encoder;
79e53945 3694 int pipe = intel_crtc->pipe;
80824003 3695 int plane = intel_crtc->plane;
79e53945 3696
08a48469
DV		 3697 WARN_ON(!crtc->enabled);
3698
f7abfe8b
CW		 3699 if (intel_crtc->active)
3700 return;
3701
3702 intel_crtc->active = true;
6b383a7f
CW		 3703 intel_update_watermarks(dev);
3704
63d7bbe9 3705 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_enable)
3709 encoder->pre_enable(encoder);
3710
040484af 3711 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3712 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3713 if (IS_G4X(dev))
3714 g4x_fixup_plane(dev_priv, pipe);
79e53945 3715
0b8765c6 3716 intel_crtc_load_lut(crtc);
bed4a673 3717 intel_update_fbc(dev);
79e53945 3718
0b8765c6
JB		 3719 /* Give the overlay scaler a chance to enable if it's on this pipe */
3720 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3721 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3722
fa5c73b1
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder);
0b8765c6 3725}
79e53945 3726
87476d63
DV		 3727static void i9xx_pfit_disable(struct intel_crtc *crtc)
3728{
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum pipe pipe;
3732 uint32_t pctl = I915_READ(PFIT_CONTROL);
3733
3734 assert_pipe_disabled(dev_priv, crtc->pipe);
3735
3736 if (INTEL_INFO(dev)->gen >= 4)
3737 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3738 else
3739 pipe = PIPE_B;
3740
3741 if (pipe == crtc->pipe) {
3742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3743 I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745}
3746
0b8765c6
JB		 3747static void i9xx_crtc_disable(struct drm_crtc *crtc)
3748{
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3752 struct intel_encoder *encoder;
0b8765c6
JB		 3753 int pipe = intel_crtc->pipe;
3754 int plane = intel_crtc->plane;
ef9c3aee 3755
f7abfe8b
CW		 3756 if (!intel_crtc->active)
3757 return;
3758
ea9d758d
DV		 3759 for_each_encoder_on_crtc(dev, crtc, encoder)
3760 encoder->disable(encoder);
3761
0b8765c6 3762 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3763 intel_crtc_wait_for_pending_flips(crtc);
3764 drm_vblank_off(dev, pipe);
0b8765c6 3765 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3766 intel_crtc_update_cursor(crtc, false);
0b8765c6 3767
973d04f9
CW		 3768 if (dev_priv->cfb_plane == plane)
3769 intel_disable_fbc(dev);
79e53945 3770
b24e7179 3771 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3772 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3773
87476d63 3774 i9xx_pfit_disable(intel_crtc);
24a1f16d 3775
63d7bbe9 3776 intel_disable_pll(dev_priv, pipe);
0b8765c6 3777
f7abfe8b 3778 intel_crtc->active = false;
6b383a7f
CW		 3779 intel_update_fbc(dev);
3780 intel_update_watermarks(dev);
0b8765c6
JB		 3781}
3782
ee7b9f93
JB		 3783static void i9xx_crtc_off(struct drm_crtc *crtc)
3784{
3785}
3786
976f8a20
DV		 3787static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3788 bool enabled)
2c07245f
ZW		 3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_master_private *master_priv;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
79e53945
JB		 3794
3795 if (!dev->primary->master)
3796 return;
3797
3798 master_priv = dev->primary->master->driver_priv;
3799 if (!master_priv->sarea_priv)
3800 return;
3801
79e53945
JB		 3802 switch (pipe) {
3803 case 0:
3804 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3805 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3806 break;
3807 case 1:
3808 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3809 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3810 break;
3811 default:
9db4a9c7 3812 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3813 break;
3814 }
79e53945
JB		 3815}
3816
976f8a20
DV		 3817/**
3818 * Sets the power management mode of the pipe and plane.
3819 */
3820void intel_crtc_update_dpms(struct drm_crtc *crtc)
3821{
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 struct intel_encoder *intel_encoder;
3825 bool enable = false;
3826
3827 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3828 enable |= intel_encoder->connectors_active;
3829
3830 if (enable)
3831 dev_priv->display.crtc_enable(crtc);
3832 else
3833 dev_priv->display.crtc_disable(crtc);
3834
3835 intel_crtc_update_sarea(crtc, enable);
3836}
3837
cdd59983
CW		 3838static void intel_crtc_disable(struct drm_crtc *crtc)
3839{
cdd59983 3840 struct drm_device *dev = crtc->dev;
976f8a20 3841 struct drm_connector *connector;
ee7b9f93 3842 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3844
976f8a20
DV		 3845 /* crtc should still be enabled when we disable it. */
3846 WARN_ON(!crtc->enabled);
3847
7b9f35a6 3848 intel_crtc->eld_vld = false;
976f8a20
DV		 3849 dev_priv->display.crtc_disable(crtc);
3850 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3851 dev_priv->display.off(crtc);
3852
931872fc
CW		 3853 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3854 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3855
3856 if (crtc->fb) {
3857 mutex_lock(&dev->struct_mutex);
1690e1eb 3858 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3859 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3860 crtc->fb = NULL;
3861 }
3862
3863 /* Update computed state. */
3864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3865 if (!connector->encoder || !connector->encoder->crtc)
3866 continue;
3867
3868 if (connector->encoder->crtc != crtc)
3869 continue;
3870
3871 connector->dpms = DRM_MODE_DPMS_OFF;
3872 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3873 }
3874}
3875
a261b246 3876void intel_modeset_disable(struct drm_device *dev)
79e53945 3877{
a261b246
DV		 3878 struct drm_crtc *crtc;
3879
3880 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3881 if (crtc->enabled)
3882 intel_crtc_disable(crtc);
3883 }
79e53945
JB		 3884}
3885
ea5b213a 3886void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3887{
4ef69c7a 3888 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3889
ea5b213a
CW		 3890 drm_encoder_cleanup(encoder);
3891 kfree(intel_encoder);
7e7d76c3
JB		 3892}
3893
5ab432ef
DV		 3894/* Simple dpms helper for encodres with just one connector, no cloning and only
3895 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3896 * state of the entire output pipe. */
3897void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3898{
5ab432ef
DV		 3899 if (mode == DRM_MODE_DPMS_ON) {
3900 encoder->connectors_active = true;
3901
b2cabb0e 3902 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3903 } else {
3904 encoder->connectors_active = false;
3905
b2cabb0e 3906 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3907 }
79e53945
JB		 3908}
3909
0a91ca29
DV		 3910/* Cross check the actual hw state with our own modeset state tracking (and it's
3911 * internal consistency). */
b980514c 3912static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3913{
0a91ca29
DV		 3914 if (connector->get_hw_state(connector)) {
3915 struct intel_encoder *encoder = connector->encoder;
3916 struct drm_crtc *crtc;
3917 bool encoder_enabled;
3918 enum pipe pipe;
3919
3920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3921 connector->base.base.id,
3922 drm_get_connector_name(&connector->base));
3923
3924 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3925 "wrong connector dpms state\n");
3926 WARN(connector->base.encoder != &encoder->base,
3927 "active connector not linked to encoder\n");
3928 WARN(!encoder->connectors_active,
3929 "encoder->connectors_active not set\n");
3930
3931 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3932 WARN(!encoder_enabled, "encoder not enabled\n");
3933 if (WARN_ON(!encoder->base.crtc))
3934 return;
3935
3936 crtc = encoder->base.crtc;
3937
3938 WARN(!crtc->enabled, "crtc not enabled\n");
3939 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3940 WARN(pipe != to_intel_crtc(crtc)->pipe,
3941 "encoder active on the wrong pipe\n");
3942 }
79e53945
JB		 3943}
3944
5ab432ef
DV		 3945/* Even simpler default implementation, if there's really no special case to
3946 * consider. */
3947void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3948{
5ab432ef 3949 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3950
5ab432ef
DV		 3951 /* All the simple cases only support two dpms states. */
3952 if (mode != DRM_MODE_DPMS_ON)
3953 mode = DRM_MODE_DPMS_OFF;
d4270e57 3954
5ab432ef
DV		 3955 if (mode == connector->dpms)
3956 return;
3957
3958 connector->dpms = mode;
3959
3960 /* Only need to change hw state when actually enabled */
3961 if (encoder->base.crtc)
3962 intel_encoder_dpms(encoder, mode);
3963 else
8af6cf88 3964 WARN_ON(encoder->connectors_active != false);
0a91ca29 3965
b980514c 3966 intel_modeset_check_state(connector->dev);
79e53945
JB		 3967}
3968
f0947c37
DV		 3969/* Simple connector->get_hw_state implementation for encoders that support only
3970 * one connector and no cloning and hence the encoder state determines the state
3971 * of the connector. */
3972bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3973{
24929352 3974 enum pipe pipe = 0;
f0947c37 3975 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3976
f0947c37 3977 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3978}
3979
b8cecdf5
DV		 3980static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3981 struct intel_crtc_config *pipe_config)
79e53945 3982{
2c07245f 3983 struct drm_device *dev = crtc->dev;
b8cecdf5 3984 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3985
bad720ff 3986 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3987 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3988 if (pipe_config->requested_mode.clock * 3
3989 > IRONLAKE_FDI_FREQ * 4)
2377b741 3990 return false;
2c07245f 3991 }
89749350 3992
f9bef081
DV		 3993 /* All interlaced capable intel hw wants timings in frames. Note though
3994 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3995 * timings, so we need to be careful not to clobber these.*/
7ae89233 3996 if (!pipe_config->timings_set)
f9bef081 3997 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3998
44f46b42
CW		 3999 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4000 * with a hsync front porch of 0.
4001 */
4002 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4003 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4004 return false;
4005
5d2d38dd
DV		 4006 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
4007 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4008 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
4009 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4010 * for lvds. */
4011 pipe_config->pipe_bpp = 8*3;
4012 }
4013
79e53945
JB		 4014 return true;
4015}
4016
25eb05fc
JB		 4017static int valleyview_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 400000; /* FIXME */
4020}
4021
e70236a8
JB		 4022static int i945_get_display_clock_speed(struct drm_device *dev)
4023{
4024 return 400000;
4025}
79e53945 4026
e70236a8 4027static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4028{
e70236a8
JB		 4029 return 333000;
4030}
79e53945 4031
e70236a8
JB		 4032static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4033{
4034 return 200000;
4035}
79e53945 4036
e70236a8
JB		 4037static int i915gm_get_display_clock_speed(struct drm_device *dev)
4038{
4039 u16 gcfgc = 0;
79e53945 4040
e70236a8
JB		 4041 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4042
4043 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4044 return 133000;
4045 else {
4046 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4047 case GC_DISPLAY_CLOCK_333_MHZ:
4048 return 333000;
4049 default:
4050 case GC_DISPLAY_CLOCK_190_200_MHZ:
4051 return 190000;
79e53945 4052 }
e70236a8
JB		 4053 }
4054}
4055
4056static int i865_get_display_clock_speed(struct drm_device *dev)
4057{
4058 return 266000;
4059}
4060
4061static int i855_get_display_clock_speed(struct drm_device *dev)
4062{
4063 u16 hpllcc = 0;
4064 /* Assume that the hardware is in the high speed state. This
4065 * should be the default.
4066 */
4067 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4068 case GC_CLOCK_133_200:
4069 case GC_CLOCK_100_200:
4070 return 200000;
4071 case GC_CLOCK_166_250:
4072 return 250000;
4073 case GC_CLOCK_100_133:
79e53945 4074 return 133000;
e70236a8 4075 }
79e53945 4076
e70236a8
JB		 4077 /* Shouldn't happen */
4078 return 0;
4079}
79e53945 4080
e70236a8
JB		 4081static int i830_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 133000;
79e53945
JB		 4084}
4085
2c07245f 4086static void
e69d0bc1 4087intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4088{
4089 while (*num > 0xffffff || *den > 0xffffff) {
4090 *num >>= 1;
4091 *den >>= 1;
4092 }
4093}
4094
e69d0bc1
DV		 4095void
4096intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4097 int pixel_clock, int link_clock,
4098 struct intel_link_m_n *m_n)
2c07245f 4099{
e69d0bc1 4100 m_n->tu = 64;
22ed1113
CW		 4101 m_n->gmch_m = bits_per_pixel * pixel_clock;
4102 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4103 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4104 m_n->link_m = pixel_clock;
4105 m_n->link_n = link_clock;
e69d0bc1 4106 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4107}
4108
a7615030
CW		 4109static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4110{
72bbe58c
KP		 4111 if (i915_panel_use_ssc >= 0)
4112 return i915_panel_use_ssc != 0;
4113 return dev_priv->lvds_use_ssc
435793df 4114 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4115}
4116
a0c4da24
JB		 4117static int vlv_get_refclk(struct drm_crtc *crtc)
4118{
4119 struct drm_device *dev = crtc->dev;
4120 struct drm_i915_private *dev_priv = dev->dev_private;
4121 int refclk = 27000; /* for DP & HDMI */
4122
4123 return 100000; /* only one validated so far */
4124
4125 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4126 refclk = 96000;
4127 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4128 if (intel_panel_use_ssc(dev_priv))
4129 refclk = 100000;
4130 else
4131 refclk = 96000;
4132 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4133 refclk = 100000;
4134 }
4135
4136 return refclk;
4137}
4138
c65d77d8
JB		 4139static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4140{
4141 struct drm_device *dev = crtc->dev;
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143 int refclk;
4144
a0c4da24
JB		 4145 if (IS_VALLEYVIEW(dev)) {
4146 refclk = vlv_get_refclk(crtc);
4147 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4148 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4149 refclk = dev_priv->lvds_ssc_freq * 1000;
4150 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4151 refclk / 1000);
4152 } else if (!IS_GEN2(dev)) {
4153 refclk = 96000;
4154 } else {
4155 refclk = 48000;
4156 }
4157
4158 return refclk;
4159}
4160
f47709a9 4161static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4162{
f47709a9
DV		 4163 unsigned dotclock = crtc->config.adjusted_mode.clock;
4164 struct dpll *clock = &crtc->config.dpll;
4165
c65d77d8
JB		 4166 /* SDVO TV has fixed PLL values depend on its clock range,
4167 this mirrors vbios setting. */
f47709a9 4168 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4169 clock->p1 = 2;
4170 clock->p2 = 10;
4171 clock->n = 3;
4172 clock->m1 = 16;
4173 clock->m2 = 8;
f47709a9 4174 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4175 clock->p1 = 1;
4176 clock->p2 = 10;
4177 clock->n = 6;
4178 clock->m1 = 12;
4179 clock->m2 = 8;
4180 }
f47709a9
DV		 4181
4182 crtc->config.clock_set = true;
c65d77d8
JB		 4183}
4184
f47709a9 4185static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4186 intel_clock_t *reduced_clock)
4187{
f47709a9 4188 struct drm_device *dev = crtc->base.dev;
a7516a05 4189 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4190 int pipe = crtc->pipe;
a7516a05 4191 u32 fp, fp2 = 0;
f47709a9 4192 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4193
4194 if (IS_PINEVIEW(dev)) {
4195 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4196 if (reduced_clock)
4197 fp2 = (1 << reduced_clock->n) << 16 |
4198 reduced_clock->m1 << 8 | reduced_clock->m2;
4199 } else {
4200 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4201 if (reduced_clock)
4202 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4203 reduced_clock->m2;
4204 }
4205
4206 I915_WRITE(FP0(pipe), fp);
4207
f47709a9
DV		 4208 crtc->lowfreq_avail = false;
4209 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4210 reduced_clock && i915_powersave) {
4211 I915_WRITE(FP1(pipe), fp2);
f47709a9 4212 crtc->lowfreq_avail = true;
a7516a05
JB		 4213 } else {
4214 I915_WRITE(FP1(pipe), fp);
4215 }
4216}
4217
03afc4a2
DV		 4218static void intel_dp_set_m_n(struct intel_crtc *crtc)
4219{
4220 if (crtc->config.has_pch_encoder)
4221 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4222 else
4223 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4224}
4225
f47709a9 4226static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4227{
f47709a9 4228 struct drm_device *dev = crtc->base.dev;
a0c4da24 4229 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4230 int pipe = crtc->pipe;
a0c4da24
JB		 4231 u32 dpll, mdiv, pdiv;
4232 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4233 bool is_sdvo;
4234 u32 temp;
a0c4da24 4235
09153000
DV		 4236 mutex_lock(&dev_priv->dpio_lock);
4237
f47709a9
DV		 4238 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4239 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4240
2a8f64ca
VP		 4241 dpll = DPLL_VGA_MODE_DIS;
4242 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4243 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4244 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4245
4246 I915_WRITE(DPLL(pipe), dpll);
4247 POSTING_READ(DPLL(pipe));
a0c4da24 4248
f47709a9
DV		 4249 bestn = crtc->config.dpll.n;
4250 bestm1 = crtc->config.dpll.m1;
4251 bestm2 = crtc->config.dpll.m2;
4252 bestp1 = crtc->config.dpll.p1;
4253 bestp2 = crtc->config.dpll.p2;
a0c4da24 4254
2a8f64ca
VP		 4255 /*
4256 * In Valleyview PLL and program lane counter registers are exposed
4257 * through DPIO interface
4258 */
a0c4da24
JB		 4259 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4260 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4261 mdiv |= ((bestn << DPIO_N_SHIFT));
4262 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4263 mdiv |= (1 << DPIO_K_SHIFT);
4264 mdiv |= DPIO_ENABLE_CALIBRATION;
4265 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4266
4267 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4268
2a8f64ca 4269 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4270 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4271 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4272 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4273 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4274
2a8f64ca 4275 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4276
4277 dpll |= DPLL_VCO_ENABLE;
4278 I915_WRITE(DPLL(pipe), dpll);
4279 POSTING_READ(DPLL(pipe));
4280 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4281 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4282
2a8f64ca
VP		 4283 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4284
f47709a9
DV		 4285 if (crtc->config.has_dp_encoder)
4286 intel_dp_set_m_n(crtc);
2a8f64ca
VP		 4287
4288 I915_WRITE(DPLL(pipe), dpll);
4289
4290 /* Wait for the clocks to stabilize. */
4291 POSTING_READ(DPLL(pipe));
4292 udelay(150);
a0c4da24 4293
2a8f64ca
VP		 4294 temp = 0;
4295 if (is_sdvo) {
6cc5f341 4296 temp = 0;
f47709a9
DV		 4297 if (crtc->config.pixel_multiplier > 1) {
4298 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4299 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4300 }
a0c4da24 4301 }
2a8f64ca
VP		 4302 I915_WRITE(DPLL_MD(pipe), temp);
4303 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4304
2a8f64ca 4305 /* Now program lane control registers */
f47709a9
DV		 4306 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4307 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
2a8f64ca
VP		 4308 temp = 0x1000C4;
4309 if(pipe == 1)
4310 temp |= (1 << 21);
4311 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4312 }
f47709a9
DV		 4313
4314 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
2a8f64ca
VP		 4315 temp = 0x1000C4;
4316 if(pipe == 1)
4317 temp |= (1 << 21);
4318 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4319 }
09153000
DV		 4320
4321 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4322}
4323
f47709a9
DV		 4324static void i9xx_update_pll(struct intel_crtc *crtc,
4325 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4326 int num_connectors)
4327{
f47709a9 4328 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4329 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4330 struct intel_encoder *encoder;
f47709a9 4331 int pipe = crtc->pipe;
eb1cbe48
DV		 4332 u32 dpll;
4333 bool is_sdvo;
f47709a9 4334 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4335
f47709a9 4336 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4337
f47709a9
DV		 4338 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4339 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4340
4341 dpll = DPLL_VGA_MODE_DIS;
4342
f47709a9 4343 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4344 dpll |= DPLLB_MODE_LVDS;
4345 else
4346 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4347
eb1cbe48 4348 if (is_sdvo) {
f47709a9 4349 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4350 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4351 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4352 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4353 }
4354 dpll |= DPLL_DVO_HIGH_SPEED;
4355 }
f47709a9 4356 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4357 dpll |= DPLL_DVO_HIGH_SPEED;
4358
4359 /* compute bitmask from p1 value */
4360 if (IS_PINEVIEW(dev))
4361 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4362 else {
4363 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4364 if (IS_G4X(dev) && reduced_clock)
4365 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4366 }
4367 switch (clock->p2) {
4368 case 5:
4369 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4370 break;
4371 case 7:
4372 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4373 break;
4374 case 10:
4375 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4376 break;
4377 case 14:
4378 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4379 break;
4380 }
4381 if (INTEL_INFO(dev)->gen >= 4)
4382 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4383
f47709a9 4384 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4385 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4386 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4387 /* XXX: just matching BIOS for now */
4388 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4389 dpll |= 3;
f47709a9 4390 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4391 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4392 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4393 else
4394 dpll |= PLL_REF_INPUT_DREFCLK;
4395
4396 dpll |= DPLL_VCO_ENABLE;
4397 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4398 POSTING_READ(DPLL(pipe));
4399 udelay(150);
4400
f47709a9 4401 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4402 if (encoder->pre_pll_enable)
4403 encoder->pre_pll_enable(encoder);
eb1cbe48 4404
f47709a9
DV		 4405 if (crtc->config.has_dp_encoder)
4406 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4407
4408 I915_WRITE(DPLL(pipe), dpll);
4409
4410 /* Wait for the clocks to stabilize. */
4411 POSTING_READ(DPLL(pipe));
4412 udelay(150);
4413
4414 if (INTEL_INFO(dev)->gen >= 4) {
4415 u32 temp = 0;
4416 if (is_sdvo) {
6cc5f341 4417 temp = 0;
f47709a9
DV		 4418 if (crtc->config.pixel_multiplier > 1) {
4419 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4420 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4421 }
eb1cbe48
DV		 4422 }
4423 I915_WRITE(DPLL_MD(pipe), temp);
4424 } else {
4425 /* The pixel multiplier can only be updated once the
4426 * DPLL is enabled and the clocks are stable.
4427 *
4428 * So write it again.
4429 */
4430 I915_WRITE(DPLL(pipe), dpll);
4431 }
4432}
4433
f47709a9 4434static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4435 struct drm_display_mode *adjusted_mode,
f47709a9 4436 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4437 int num_connectors)
4438{
f47709a9 4439 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4440 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4441 struct intel_encoder *encoder;
f47709a9 4442 int pipe = crtc->pipe;
eb1cbe48 4443 u32 dpll;
f47709a9 4444 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4445
f47709a9 4446 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4447
eb1cbe48
DV		 4448 dpll = DPLL_VGA_MODE_DIS;
4449
f47709a9 4450 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4451 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4452 } else {
4453 if (clock->p1 == 2)
4454 dpll |= PLL_P1_DIVIDE_BY_TWO;
4455 else
4456 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4457 if (clock->p2 == 4)
4458 dpll |= PLL_P2_DIVIDE_BY_4;
4459 }
4460
f47709a9 4461 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4462 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4463 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4464 else
4465 dpll |= PLL_REF_INPUT_DREFCLK;
4466
4467 dpll |= DPLL_VCO_ENABLE;
4468 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4469 POSTING_READ(DPLL(pipe));
4470 udelay(150);
4471
f47709a9 4472 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4473 if (encoder->pre_pll_enable)
4474 encoder->pre_pll_enable(encoder);
eb1cbe48 4475
5b5896e4
DV		 4476 I915_WRITE(DPLL(pipe), dpll);
4477
4478 /* Wait for the clocks to stabilize. */
4479 POSTING_READ(DPLL(pipe));
4480 udelay(150);
4481
eb1cbe48
DV		 4482 /* The pixel multiplier can only be updated once the
4483 * DPLL is enabled and the clocks are stable.
4484 *
4485 * So write it again.
4486 */
4487 I915_WRITE(DPLL(pipe), dpll);
4488}
4489
b0e77b9c
PZ		 4490static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4491 struct drm_display_mode *mode,
4492 struct drm_display_mode *adjusted_mode)
4493{
4494 struct drm_device *dev = intel_crtc->base.dev;
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4496 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4497 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4498 uint32_t vsyncshift;
4499
4500 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4501 /* the chip adds 2 halflines automatically */
4502 adjusted_mode->crtc_vtotal -= 1;
4503 adjusted_mode->crtc_vblank_end -= 1;
4504 vsyncshift = adjusted_mode->crtc_hsync_start
4505 - adjusted_mode->crtc_htotal / 2;
4506 } else {
4507 vsyncshift = 0;
4508 }
4509
4510 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4511 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4512
fe2b8f9d 4513 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4514 (adjusted_mode->crtc_hdisplay - 1) |
4515 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4516 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4517 (adjusted_mode->crtc_hblank_start - 1) |
4518 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4519 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4520 (adjusted_mode->crtc_hsync_start - 1) |
4521 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4522
fe2b8f9d 4523 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4524 (adjusted_mode->crtc_vdisplay - 1) |
4525 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4526 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4527 (adjusted_mode->crtc_vblank_start - 1) |
4528 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4529 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4530 (adjusted_mode->crtc_vsync_start - 1) |
4531 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4532
b5e508d4
PZ		 4533 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4534 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4535 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4536 * bits. */
4537 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4538 (pipe == PIPE_B || pipe == PIPE_C))
4539 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4540
b0e77b9c
PZ		 4541 /* pipesrc controls the size that is scaled from, which should
4542 * always be the user's requested size.
4543 */
4544 I915_WRITE(PIPESRC(pipe),
4545 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4546}
4547
84b046f3
DV		 4548static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4549{
4550 struct drm_device *dev = intel_crtc->base.dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 uint32_t pipeconf;
4553
4554 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4555
4556 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4557 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4558 * core speed.
4559 *
4560 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4561 * pipe == 0 check?
4562 */
4563 if (intel_crtc->config.requested_mode.clock >
4564 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4565 pipeconf |= PIPECONF_DOUBLE_WIDE;
4566 else
4567 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4568 }
4569
4570 /* default to 8bpc */
4571 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4572 if (intel_crtc->config.has_dp_encoder) {
4573 if (intel_crtc->config.dither) {
4574 pipeconf |= PIPECONF_6BPC |
4575 PIPECONF_DITHER_EN |
4576 PIPECONF_DITHER_TYPE_SP;
4577 }
4578 }
4579
4580 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4581 INTEL_OUTPUT_EDP)) {
4582 if (intel_crtc->config.dither) {
4583 pipeconf |= PIPECONF_6BPC |
4584 PIPECONF_ENABLE |
4585 I965_PIPECONF_ACTIVE;
4586 }
4587 }
4588
4589 if (HAS_PIPE_CXSR(dev)) {
4590 if (intel_crtc->lowfreq_avail) {
4591 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4592 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4593 } else {
4594 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4595 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4596 }
4597 }
4598
4599 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4600 if (!IS_GEN2(dev) &&
4601 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4602 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4603 else
4604 pipeconf |= PIPECONF_PROGRESSIVE;
4605
9c8e09b7
VS		 4606 if (IS_VALLEYVIEW(dev)) {
4607 if (intel_crtc->config.limited_color_range)
4608 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4609 else
4610 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4611 }
4612
84b046f3
DV		 4613 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4614 POSTING_READ(PIPECONF(intel_crtc->pipe));
4615}
4616
f564048e 4617static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4618 int x, int y,
94352cf9 4619 struct drm_framebuffer *fb)
79e53945
JB		 4620{
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4624 struct drm_display_mode *adjusted_mode =
4625 &intel_crtc->config.adjusted_mode;
4626 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4627 int pipe = intel_crtc->pipe;
80824003 4628 int plane = intel_crtc->plane;
c751ce4f 4629 int refclk, num_connectors = 0;
652c393a 4630 intel_clock_t clock, reduced_clock;
84b046f3 4631 u32 dspcntr;
eb1cbe48 4632 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4633 bool is_lvds = false, is_tv = false;
5eddb70b 4634 struct intel_encoder *encoder;
d4906093 4635 const intel_limit_t *limit;
5c3b82e2 4636 int ret;
79e53945 4637
6c2b7c12 4638 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4639 switch (encoder->type) {
79e53945
JB		 4640 case INTEL_OUTPUT_LVDS:
4641 is_lvds = true;
4642 break;
4643 case INTEL_OUTPUT_SDVO:
7d57382e 4644 case INTEL_OUTPUT_HDMI:
79e53945 4645 is_sdvo = true;
5eddb70b 4646 if (encoder->needs_tv_clock)
e2f0ba97 4647 is_tv = true;
79e53945 4648 break;
79e53945
JB		 4649 case INTEL_OUTPUT_TVOUT:
4650 is_tv = true;
4651 break;
79e53945 4652 }
43565a06 4653
c751ce4f 4654 num_connectors++;
79e53945
JB		 4655 }
4656
c65d77d8 4657 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4658
d4906093
ML		 4659 /*
4660 * Returns a set of divisors for the desired target clock with the given
4661 * refclk, or FALSE. The returned values represent the clock equation:
4662 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4663 */
1b894b59 4664 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4665 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4666 &clock);
79e53945
JB		 4667 if (!ok) {
4668 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4669 return -EINVAL;
79e53945
JB		 4670 }
4671
cda4b7d3 4672 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4673 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4674
ddc9003c 4675 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4676 /*
4677 * Ensure we match the reduced clock's P to the target clock.
4678 * If the clocks don't match, we can't switch the display clock
4679 * by using the FP0/FP1. In such case we will disable the LVDS
4680 * downclock feature.
4681 */
ddc9003c 4682 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4683 dev_priv->lvds_downclock,
4684 refclk,
cec2f356 4685 &clock,
5eddb70b 4686 &reduced_clock);
7026d4ac 4687 }
f47709a9
DV		 4688 /* Compat-code for transition, will disappear. */
4689 if (!intel_crtc->config.clock_set) {
4690 intel_crtc->config.dpll.n = clock.n;
4691 intel_crtc->config.dpll.m1 = clock.m1;
4692 intel_crtc->config.dpll.m2 = clock.m2;
4693 intel_crtc->config.dpll.p1 = clock.p1;
4694 intel_crtc->config.dpll.p2 = clock.p2;
4695 }
7026d4ac 4696
c65d77d8 4697 if (is_sdvo && is_tv)
f47709a9 4698 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4699
eb1cbe48 4700 if (IS_GEN2(dev))
f47709a9 4701 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4702 has_reduced_clock ? &reduced_clock : NULL,
4703 num_connectors);
a0c4da24 4704 else if (IS_VALLEYVIEW(dev))
f47709a9 4705 vlv_update_pll(intel_crtc);
79e53945 4706 else
f47709a9 4707 i9xx_update_pll(intel_crtc,
eb1cbe48
DV		 4708 has_reduced_clock ? &reduced_clock : NULL,
4709 num_connectors);
79e53945 4710
79e53945
JB		 4711 /* Set up the display plane register */
4712 dspcntr = DISPPLANE_GAMMA_ENABLE;
4713
da6ecc5d
JB		 4714 if (!IS_VALLEYVIEW(dev)) {
4715 if (pipe == 0)
4716 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4717 else
4718 dspcntr |= DISPPLANE_SEL_PIPE_B;
4719 }
79e53945 4720
28c97730 4721 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4722 drm_mode_debug_printmodeline(mode);
4723
b0e77b9c 4724 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4725
4726 /* pipesrc and dspsize control the size that is scaled from,
4727 * which should always be the user's requested size.
79e53945 4728 */
929c77fb
EA		 4729 I915_WRITE(DSPSIZE(plane),
4730 ((mode->vdisplay - 1) << 16) |
4731 (mode->hdisplay - 1));
4732 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4733
84b046f3
DV		 4734 i9xx_set_pipeconf(intel_crtc);
4735
929c77fb 4736 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4737
4738 intel_wait_for_vblank(dev, pipe);
4739
f564048e
EA		 4740 I915_WRITE(DSPCNTR(plane), dspcntr);
4741 POSTING_READ(DSPCNTR(plane));
4742
94352cf9 4743 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4744
4745 intel_update_watermarks(dev);
4746
f564048e
EA		 4747 return ret;
4748}
4749
0e8ffe1b
DV		 4750static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4751 struct intel_crtc_config *pipe_config)
4752{
4753 struct drm_device *dev = crtc->base.dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755 uint32_t tmp;
4756
4757 tmp = I915_READ(PIPECONF(crtc->pipe));
4758 if (!(tmp & PIPECONF_ENABLE))
4759 return false;
4760
4761 return true;
4762}
4763
dde86e2d 4764static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4765{
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4768 struct intel_encoder *encoder;
74cfd7ac 4769 u32 val, final;
13d83a67 4770 bool has_lvds = false;
199e5d79
KP		 4771 bool has_cpu_edp = false;
4772 bool has_pch_edp = false;
4773 bool has_panel = false;
99eb6a01
KP		 4774 bool has_ck505 = false;
4775 bool can_ssc = false;
13d83a67
JB		 4776
4777 /* We need to take the global config into account */
199e5d79
KP		 4778 list_for_each_entry(encoder, &mode_config->encoder_list,
4779 base.head) {
4780 switch (encoder->type) {
4781 case INTEL_OUTPUT_LVDS:
4782 has_panel = true;
4783 has_lvds = true;
4784 break;
4785 case INTEL_OUTPUT_EDP:
4786 has_panel = true;
4787 if (intel_encoder_is_pch_edp(&encoder->base))
4788 has_pch_edp = true;
4789 else
4790 has_cpu_edp = true;
4791 break;
13d83a67
JB		 4792 }
4793 }
4794
99eb6a01
KP		 4795 if (HAS_PCH_IBX(dev)) {
4796 has_ck505 = dev_priv->display_clock_mode;
4797 can_ssc = has_ck505;
4798 } else {
4799 has_ck505 = false;
4800 can_ssc = true;
4801 }
4802
4803 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4804 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4805 has_ck505);
13d83a67
JB		 4806
4807 /* Ironlake: try to setup display ref clock before DPLL
4808 * enabling. This is only under driver's control after
4809 * PCH B stepping, previous chipset stepping should be
4810 * ignoring this setting.
4811 */
74cfd7ac
CW		 4812 val = I915_READ(PCH_DREF_CONTROL);
4813
4814 /* As we must carefully and slowly disable/enable each source in turn,
4815 * compute the final state we want first and check if we need to
4816 * make any changes at all.
4817 */
4818 final = val;
4819 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4820 if (has_ck505)
4821 final |= DREF_NONSPREAD_CK505_ENABLE;
4822 else
4823 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4824
4825 final &= ~DREF_SSC_SOURCE_MASK;
4826 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4827 final &= ~DREF_SSC1_ENABLE;
4828
4829 if (has_panel) {
4830 final |= DREF_SSC_SOURCE_ENABLE;
4831
4832 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4833 final |= DREF_SSC1_ENABLE;
4834
4835 if (has_cpu_edp) {
4836 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4837 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4838 else
4839 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4840 } else
4841 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4842 } else {
4843 final |= DREF_SSC_SOURCE_DISABLE;
4844 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4845 }
4846
4847 if (final == val)
4848 return;
4849
13d83a67 4850 /* Always enable nonspread source */
74cfd7ac 4851 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4852
99eb6a01 4853 if (has_ck505)
74cfd7ac 4854 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4855 else
74cfd7ac 4856 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4857
199e5d79 4858 if (has_panel) {
74cfd7ac
CW		 4859 val &= ~DREF_SSC_SOURCE_MASK;
4860 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4861
199e5d79 4862 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4863 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4864 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4865 val |= DREF_SSC1_ENABLE;
e77166b5 4866 } else
74cfd7ac 4867 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4868
4869 /* Get SSC going before enabling the outputs */
74cfd7ac 4870 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4871 POSTING_READ(PCH_DREF_CONTROL);
4872 udelay(200);
4873
74cfd7ac 4874 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4875
4876 /* Enable CPU source on CPU attached eDP */
199e5d79 4877 if (has_cpu_edp) {
99eb6a01 4878 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4879 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4880 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4881 }
13d83a67 4882 else
74cfd7ac 4883 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4884 } else
74cfd7ac 4885 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4886
74cfd7ac 4887 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4888 POSTING_READ(PCH_DREF_CONTROL);
4889 udelay(200);
4890 } else {
4891 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4892
74cfd7ac 4893 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4894
4895 /* Turn off CPU output */
74cfd7ac 4896 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4897
74cfd7ac 4898 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4899 POSTING_READ(PCH_DREF_CONTROL);
4900 udelay(200);
4901
4902 /* Turn off the SSC source */
74cfd7ac
CW		 4903 val &= ~DREF_SSC_SOURCE_MASK;
4904 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4905
4906 /* Turn off SSC1 */
74cfd7ac 4907 val &= ~DREF_SSC1_ENABLE;
199e5d79 4908
74cfd7ac 4909 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4910 POSTING_READ(PCH_DREF_CONTROL);
4911 udelay(200);
4912 }
74cfd7ac
CW		 4913
4914 BUG_ON(val != final);
13d83a67
JB		 4915}
4916
dde86e2d
PZ		 4917/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4918static void lpt_init_pch_refclk(struct drm_device *dev)
4919{
4920 struct drm_i915_private *dev_priv = dev->dev_private;
4921 struct drm_mode_config *mode_config = &dev->mode_config;
4922 struct intel_encoder *encoder;
4923 bool has_vga = false;
4924 bool is_sdv = false;
4925 u32 tmp;
4926
4927 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4928 switch (encoder->type) {
4929 case INTEL_OUTPUT_ANALOG:
4930 has_vga = true;
4931 break;
4932 }
4933 }
4934
4935 if (!has_vga)
4936 return;
4937
c00db246
DV		 4938 mutex_lock(&dev_priv->dpio_lock);
4939
dde86e2d
PZ		 4940 /* XXX: Rip out SDV support once Haswell ships for real. */
4941 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4942 is_sdv = true;
4943
4944 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4945 tmp &= ~SBI_SSCCTL_DISABLE;
4946 tmp |= SBI_SSCCTL_PATHALT;
4947 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4948
4949 udelay(24);
4950
4951 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4952 tmp &= ~SBI_SSCCTL_PATHALT;
4953 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4954
4955 if (!is_sdv) {
4956 tmp = I915_READ(SOUTH_CHICKEN2);
4957 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4958 I915_WRITE(SOUTH_CHICKEN2, tmp);
4959
4960 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4961 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4962 DRM_ERROR("FDI mPHY reset assert timeout\n");
4963
4964 tmp = I915_READ(SOUTH_CHICKEN2);
4965 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4966 I915_WRITE(SOUTH_CHICKEN2, tmp);
4967
4968 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4969 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4970 100))
4971 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4972 }
4973
4974 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4975 tmp &= ~(0xFF << 24);
4976 tmp |= (0x12 << 24);
4977 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4978
dde86e2d
PZ		 4979 if (is_sdv) {
4980 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4981 tmp |= 0x7FFF;
4982 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4983 }
4984
4985 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4986 tmp |= (1 << 11);
4987 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4988
4989 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4990 tmp |= (1 << 11);
4991 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4992
4993 if (is_sdv) {
4994 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4995 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4996 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4997
4998 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4999 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5000 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5003 tmp |= (0x3F << 8);
5004 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5005
5006 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5007 tmp |= (0x3F << 8);
5008 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5009 }
5010
5011 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5012 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5013 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5014
5015 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5016 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5017 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5018
5019 if (!is_sdv) {
5020 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5021 tmp &= ~(7 << 13);
5022 tmp |= (5 << 13);
5023 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5024
5025 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5026 tmp &= ~(7 << 13);
5027 tmp |= (5 << 13);
5028 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5029 }
5030
5031 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5032 tmp &= ~0xFF;
5033 tmp |= 0x1C;
5034 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5035
5036 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5037 tmp &= ~0xFF;
5038 tmp |= 0x1C;
5039 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5040
5041 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5042 tmp &= ~(0xFF << 16);
5043 tmp |= (0x1C << 16);
5044 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5045
5046 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5047 tmp &= ~(0xFF << 16);
5048 tmp |= (0x1C << 16);
5049 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5050
5051 if (!is_sdv) {
5052 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5053 tmp |= (1 << 27);
5054 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5055
5056 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5057 tmp |= (1 << 27);
5058 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5059
5060 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5061 tmp &= ~(0xF << 28);
5062 tmp |= (4 << 28);
5063 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5064
5065 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5066 tmp &= ~(0xF << 28);
5067 tmp |= (4 << 28);
5068 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5069 }
5070
5071 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5072 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5073 tmp |= SBI_DBUFF0_ENABLE;
5074 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5075
5076 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5077}
5078
5079/*
5080 * Initialize reference clocks when the driver loads
5081 */
5082void intel_init_pch_refclk(struct drm_device *dev)
5083{
5084 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5085 ironlake_init_pch_refclk(dev);
5086 else if (HAS_PCH_LPT(dev))
5087 lpt_init_pch_refclk(dev);
5088}
5089
d9d444cb
JB		 5090static int ironlake_get_refclk(struct drm_crtc *crtc)
5091{
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_encoder *encoder;
d9d444cb
JB		 5095 struct intel_encoder *edp_encoder = NULL;
5096 int num_connectors = 0;
5097 bool is_lvds = false;
5098
6c2b7c12 5099 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5100 switch (encoder->type) {
5101 case INTEL_OUTPUT_LVDS:
5102 is_lvds = true;
5103 break;
5104 case INTEL_OUTPUT_EDP:
5105 edp_encoder = encoder;
5106 break;
5107 }
5108 num_connectors++;
5109 }
5110
5111 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5112 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5113 dev_priv->lvds_ssc_freq);
5114 return dev_priv->lvds_ssc_freq * 1000;
5115 }
5116
5117 return 120000;
5118}
5119
c8203565 5120static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5121 struct drm_display_mode *adjusted_mode,
c8203565 5122 bool dither)
79e53945 5123{
c8203565 5124 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5126 int pipe = intel_crtc->pipe;
c8203565
PZ		 5127 uint32_t val;
5128
5129 val = I915_READ(PIPECONF(pipe));
5130
dfd07d72 5131 val &= ~PIPECONF_BPC_MASK;
965e0c48 5132 switch (intel_crtc->config.pipe_bpp) {
c8203565 5133 case 18:
dfd07d72 5134 val |= PIPECONF_6BPC;
c8203565
PZ		 5135 break;
5136 case 24:
dfd07d72 5137 val |= PIPECONF_8BPC;
c8203565
PZ		 5138 break;
5139 case 30:
dfd07d72 5140 val |= PIPECONF_10BPC;
c8203565
PZ		 5141 break;
5142 case 36:
dfd07d72 5143 val |= PIPECONF_12BPC;
c8203565
PZ		 5144 break;
5145 default:
cc769b62
PZ		 5146 /* Case prevented by intel_choose_pipe_bpp_dither. */
5147 BUG();
c8203565
PZ		 5148 }
5149
5150 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5151 if (dither)
5152 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5153
5154 val &= ~PIPECONF_INTERLACE_MASK;
5155 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5156 val |= PIPECONF_INTERLACED_ILK;
5157 else
5158 val |= PIPECONF_PROGRESSIVE;
5159
50f3b016 5160 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5161 val |= PIPECONF_COLOR_RANGE_SELECT;
5162 else
5163 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5164
c8203565
PZ		 5165 I915_WRITE(PIPECONF(pipe), val);
5166 POSTING_READ(PIPECONF(pipe));
5167}
5168
86d3efce
VS		 5169/*
5170 * Set up the pipe CSC unit.
5171 *
5172 * Currently only full range RGB to limited range RGB conversion
5173 * is supported, but eventually this should handle various
5174 * RGB<->YCbCr scenarios as well.
5175 */
50f3b016 5176static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5177{
5178 struct drm_device *dev = crtc->dev;
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5181 int pipe = intel_crtc->pipe;
5182 uint16_t coeff = 0x7800; /* 1.0 */
5183
5184 /*
5185 * TODO: Check what kind of values actually come out of the pipe
5186 * with these coeff/postoff values and adjust to get the best
5187 * accuracy. Perhaps we even need to take the bpc value into
5188 * consideration.
5189 */
5190
50f3b016 5191 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5192 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5193
5194 /*
5195 * GY/GU and RY/RU should be the other way around according
5196 * to BSpec, but reality doesn't agree. Just set them up in
5197 * a way that results in the correct picture.
5198 */
5199 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5200 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5201
5202 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5203 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5204
5205 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5206 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5207
5208 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5209 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5210 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5211
5212 if (INTEL_INFO(dev)->gen > 6) {
5213 uint16_t postoff = 0;
5214
50f3b016 5215 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5216 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5217
5218 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5219 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5220 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5221
5222 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5223 } else {
5224 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5225
50f3b016 5226 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5227 mode |= CSC_BLACK_SCREEN_OFFSET;
5228
5229 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5230 }
5231}
5232
ee2b0b38
PZ		 5233static void haswell_set_pipeconf(struct drm_crtc *crtc,
5234 struct drm_display_mode *adjusted_mode,
5235 bool dither)
5236{
5237 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5239 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5240 uint32_t val;
5241
702e7a56 5242 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5243
5244 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5245 if (dither)
5246 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5247
5248 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5249 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5250 val |= PIPECONF_INTERLACED_ILK;
5251 else
5252 val |= PIPECONF_PROGRESSIVE;
5253
702e7a56
PZ		 5254 I915_WRITE(PIPECONF(cpu_transcoder), val);
5255 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5256}
5257
6591c6e4
PZ		 5258static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5259 struct drm_display_mode *adjusted_mode,
5260 intel_clock_t *clock,
5261 bool *has_reduced_clock,
5262 intel_clock_t *reduced_clock)
5263{
5264 struct drm_device *dev = crtc->dev;
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266 struct intel_encoder *intel_encoder;
5267 int refclk;
d4906093 5268 const intel_limit_t *limit;
6591c6e4 5269 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5270
6591c6e4
PZ		 5271 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5272 switch (intel_encoder->type) {
79e53945
JB		 5273 case INTEL_OUTPUT_LVDS:
5274 is_lvds = true;
5275 break;
5276 case INTEL_OUTPUT_SDVO:
7d57382e 5277 case INTEL_OUTPUT_HDMI:
79e53945 5278 is_sdvo = true;
6591c6e4 5279 if (intel_encoder->needs_tv_clock)
e2f0ba97 5280 is_tv = true;
79e53945 5281 break;
79e53945
JB		 5282 case INTEL_OUTPUT_TVOUT:
5283 is_tv = true;
5284 break;
79e53945
JB		 5285 }
5286 }
5287
d9d444cb 5288 refclk = ironlake_get_refclk(crtc);
79e53945 5289
d4906093
ML		 5290 /*
5291 * Returns a set of divisors for the desired target clock with the given
5292 * refclk, or FALSE. The returned values represent the clock equation:
5293 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5294 */
1b894b59 5295 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5296 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5297 clock);
5298 if (!ret)
5299 return false;
cda4b7d3 5300
ddc9003c 5301 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5302 /*
5303 * Ensure we match the reduced clock's P to the target clock.
5304 * If the clocks don't match, we can't switch the display clock
5305 * by using the FP0/FP1. In such case we will disable the LVDS
5306 * downclock feature.
5307 */
6591c6e4
PZ		 5308 *has_reduced_clock = limit->find_pll(limit, crtc,
5309 dev_priv->lvds_downclock,
5310 refclk,
5311 clock,
5312 reduced_clock);
652c393a 5313 }
61e9653f
DV		 5314
5315 if (is_sdvo && is_tv)
f47709a9 5316 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5317
5318 return true;
5319}
5320
01a415fd
DV		 5321static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5322{
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324 uint32_t temp;
5325
5326 temp = I915_READ(SOUTH_CHICKEN1);
5327 if (temp & FDI_BC_BIFURCATION_SELECT)
5328 return;
5329
5330 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5331 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5332
5333 temp |= FDI_BC_BIFURCATION_SELECT;
5334 DRM_DEBUG_KMS("enabling fdi C rx\n");
5335 I915_WRITE(SOUTH_CHICKEN1, temp);
5336 POSTING_READ(SOUTH_CHICKEN1);
5337}
5338
5339static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5340{
5341 struct drm_device *dev = intel_crtc->base.dev;
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 struct intel_crtc *pipe_B_crtc =
5344 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5345
5346 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5347 intel_crtc->pipe, intel_crtc->fdi_lanes);
5348 if (intel_crtc->fdi_lanes > 4) {
5349 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5350 intel_crtc->pipe, intel_crtc->fdi_lanes);
5351 /* Clamp lanes to avoid programming the hw with bogus values. */
5352 intel_crtc->fdi_lanes = 4;
5353
5354 return false;
5355 }
5356
7eb552ae 5357 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5358 return true;
5359
5360 switch (intel_crtc->pipe) {
5361 case PIPE_A:
5362 return true;
5363 case PIPE_B:
5364 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5365 intel_crtc->fdi_lanes > 2) {
5366 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5367 intel_crtc->pipe, intel_crtc->fdi_lanes);
5368 /* Clamp lanes to avoid programming the hw with bogus values. */
5369 intel_crtc->fdi_lanes = 2;
5370
5371 return false;
5372 }
5373
5374 if (intel_crtc->fdi_lanes > 2)
5375 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5376 else
5377 cpt_enable_fdi_bc_bifurcation(dev);
5378
5379 return true;
5380 case PIPE_C:
5381 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5382 if (intel_crtc->fdi_lanes > 2) {
5383 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5384 intel_crtc->pipe, intel_crtc->fdi_lanes);
5385 /* Clamp lanes to avoid programming the hw with bogus values. */
5386 intel_crtc->fdi_lanes = 2;
5387
5388 return false;
5389 }
5390 } else {
5391 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5392 return false;
5393 }
5394
5395 cpt_enable_fdi_bc_bifurcation(dev);
5396
5397 return true;
5398 default:
5399 BUG();
5400 }
5401}
5402
d4b1931c
PZ		 5403int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5404{
5405 /*
5406 * Account for spread spectrum to avoid
5407 * oversubscribing the link. Max center spread
5408 * is 2.5%; use 5% for safety's sake.
5409 */
5410 u32 bps = target_clock * bpp * 21 / 20;
5411 return bps / (link_bw * 8) + 1;
5412}
5413
6cf86a5e
DV		 5414void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5415 struct intel_link_m_n *m_n)
79e53945 5416{
6cf86a5e
DV		 5417 struct drm_device *dev = crtc->base.dev;
5418 struct drm_i915_private *dev_priv = dev->dev_private;
5419 int pipe = crtc->pipe;
5420
5421 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5422 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5423 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5424 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5425}
5426
5427void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5428 struct intel_link_m_n *m_n)
5429{
5430 struct drm_device *dev = crtc->base.dev;
79e53945 5431 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e
DV		 5432 int pipe = crtc->pipe;
5433 enum transcoder transcoder = crtc->cpu_transcoder;
5434
5435 if (INTEL_INFO(dev)->gen >= 5) {
5436 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5437 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5438 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5439 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5440 } else {
5441 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5442 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5443 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5444 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5445 }
5446}
5447
5448static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5449{
5450 struct drm_device *dev = crtc->dev;
79e53945 5451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5452 struct drm_display_mode *adjusted_mode =
5453 &intel_crtc->config.adjusted_mode;
e69d0bc1 5454 struct intel_link_m_n m_n = {0};
6cc5f341 5455 int target_clock, lane, link_bw;
61e9653f 5456
6cf86a5e
DV		 5457 /* FDI is a binary signal running at ~2.7GHz, encoding
5458 * each output octet as 10 bits. The actual frequency
5459 * is stored as a divider into a 100MHz clock, and the
5460 * mode pixel clock is stored in units of 1KHz.
5461 * Hence the bw of each lane in terms of the mode signal
5462 * is:
5463 */
5464 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5465
df92b1e6
DV		 5466 if (intel_crtc->config.pixel_target_clock)
5467 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5468 else
5469 target_clock = adjusted_mode->clock;
5470
6cf86a5e
DV		 5471 lane = ironlake_get_lanes_required(target_clock, link_bw,
5472 intel_crtc->config.pipe_bpp);
2c07245f 5473
8febb297
EA		 5474 intel_crtc->fdi_lanes = lane;
5475
6cc5f341
DV		 5476 if (intel_crtc->config.pixel_multiplier > 1)
5477 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5478 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5479 link_bw, &m_n);
8febb297 5480
6cf86a5e 5481 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5482}
5483
de13a2e3 5484static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9a7c7890
DV		 5485 intel_clock_t *clock, u32 *fp,
5486 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5487{
de13a2e3 5488 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5489 struct drm_device *dev = crtc->dev;
5490 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5491 struct intel_encoder *intel_encoder;
5492 uint32_t dpll;
6cc5f341 5493 int factor, num_connectors = 0;
de13a2e3 5494 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5495
de13a2e3
PZ		 5496 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5497 switch (intel_encoder->type) {
79e53945
JB		 5498 case INTEL_OUTPUT_LVDS:
5499 is_lvds = true;
5500 break;
5501 case INTEL_OUTPUT_SDVO:
7d57382e 5502 case INTEL_OUTPUT_HDMI:
79e53945 5503 is_sdvo = true;
de13a2e3 5504 if (intel_encoder->needs_tv_clock)
e2f0ba97 5505 is_tv = true;
79e53945 5506 break;
79e53945
JB		 5507 case INTEL_OUTPUT_TVOUT:
5508 is_tv = true;
5509 break;
79e53945 5510 }
43565a06 5511
c751ce4f 5512 num_connectors++;
79e53945 5513 }
79e53945 5514
c1858123 5515 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5516 factor = 21;
5517 if (is_lvds) {
5518 if ((intel_panel_use_ssc(dev_priv) &&
5519 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5520 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5521 factor = 25;
5522 } else if (is_sdvo && is_tv)
5523 factor = 20;
c1858123 5524
de13a2e3 5525 if (clock->m < factor * clock->n)
7d0ac5b7 5526 *fp |= FP_CB_TUNE;
2c07245f 5527
9a7c7890
DV		 5528 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5529 *fp2 |= FP_CB_TUNE;
5530
5eddb70b 5531 dpll = 0;
2c07245f 5532
a07d6787
EA		 5533 if (is_lvds)
5534 dpll |= DPLLB_MODE_LVDS;
5535 else
5536 dpll |= DPLLB_MODE_DAC_SERIAL;
5537 if (is_sdvo) {
6cc5f341
DV		 5538 if (intel_crtc->config.pixel_multiplier > 1) {
5539 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5540 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5541 }
a07d6787
EA		 5542 dpll |= DPLL_DVO_HIGH_SPEED;
5543 }
8b47047b
DV		 5544 if (intel_crtc->config.has_dp_encoder &&
5545 intel_crtc->config.has_pch_encoder)
a07d6787 5546 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5547
a07d6787 5548 /* compute bitmask from p1 value */
de13a2e3 5549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5550 /* also FPA1 */
de13a2e3 5551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5552
de13a2e3 5553 switch (clock->p2) {
a07d6787
EA		 5554 case 5:
5555 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5556 break;
5557 case 7:
5558 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5559 break;
5560 case 10:
5561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5562 break;
5563 case 14:
5564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5565 break;
79e53945
JB		 5566 }
5567
43565a06
KH		 5568 if (is_sdvo && is_tv)
5569 dpll |= PLL_REF_INPUT_TVCLKINBC;
5570 else if (is_tv)
79e53945 5571 /* XXX: just matching BIOS for now */
43565a06 5572 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5573 dpll |= 3;
a7615030 5574 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5576 else
5577 dpll |= PLL_REF_INPUT_DREFCLK;
5578
de13a2e3
PZ		 5579 return dpll;
5580}
5581
5582static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5583 int x, int y,
5584 struct drm_framebuffer *fb)
5585{
5586 struct drm_device *dev = crtc->dev;
5587 struct drm_i915_private *dev_priv = dev->dev_private;
5588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5589 struct drm_display_mode *adjusted_mode =
5590 &intel_crtc->config.adjusted_mode;
5591 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5592 int pipe = intel_crtc->pipe;
5593 int plane = intel_crtc->plane;
5594 int num_connectors = 0;
5595 intel_clock_t clock, reduced_clock;
5596 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5597 bool ok, has_reduced_clock = false;
8b47047b 5598 bool is_lvds = false;
de13a2e3 5599 struct intel_encoder *encoder;
de13a2e3 5600 int ret;
01a415fd 5601 bool dither, fdi_config_ok;
de13a2e3
PZ		 5602
5603 for_each_encoder_on_crtc(dev, crtc, encoder) {
5604 switch (encoder->type) {
5605 case INTEL_OUTPUT_LVDS:
5606 is_lvds = true;
5607 break;
de13a2e3
PZ		 5608 }
5609
5610 num_connectors++;
a07d6787 5611 }
79e53945 5612
5dc5298b
PZ		 5613 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5614 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5615
6cf86a5e
DV		 5616 intel_crtc->cpu_transcoder = pipe;
5617
de13a2e3
PZ		 5618 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5619 &has_reduced_clock, &reduced_clock);
5620 if (!ok) {
5621 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5622 return -EINVAL;
79e53945 5623 }
f47709a9
DV		 5624 /* Compat-code for transition, will disappear. */
5625 if (!intel_crtc->config.clock_set) {
5626 intel_crtc->config.dpll.n = clock.n;
5627 intel_crtc->config.dpll.m1 = clock.m1;
5628 intel_crtc->config.dpll.m2 = clock.m2;
5629 intel_crtc->config.dpll.p1 = clock.p1;
5630 intel_crtc->config.dpll.p2 = clock.p2;
5631 }
79e53945 5632
de13a2e3
PZ		 5633 /* Ensure that the cursor is valid for the new mode before changing... */
5634 intel_crtc_update_cursor(crtc, true);
5635
5636 /* determine panel color depth */
4e53c2e0 5637 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5638 if (is_lvds && dev_priv->lvds_dither)
5639 dither = true;
5640
5641 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5642 if (has_reduced_clock)
5643 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5644 reduced_clock.m2;
5645
9a7c7890
DV		 5646 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5647 has_reduced_clock ? &fp2 : NULL);
79e53945 5648
f7cb34d4 5649 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5650 drm_mode_debug_printmodeline(mode);
5651
5dc5298b 5652 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5653 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5654 struct intel_pch_pll *pll;
4b645f14 5655
ee7b9f93
JB		 5656 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5657 if (pll == NULL) {
5658 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5659 pipe);
4b645f14
JB		 5660 return -EINVAL;
5661 }
ee7b9f93
JB		 5662 } else
5663 intel_put_pch_pll(intel_crtc);
79e53945 5664
03afc4a2
DV		 5665 if (intel_crtc->config.has_dp_encoder)
5666 intel_dp_set_m_n(intel_crtc);
79e53945 5667
dafd226c
DV		 5668 for_each_encoder_on_crtc(dev, crtc, encoder)
5669 if (encoder->pre_pll_enable)
5670 encoder->pre_pll_enable(encoder);
79e53945 5671
ee7b9f93
JB		 5672 if (intel_crtc->pch_pll) {
5673 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5674
32f9d658 5675 /* Wait for the clocks to stabilize. */
ee7b9f93 5676 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5677 udelay(150);
5678
8febb297
EA		 5679 /* The pixel multiplier can only be updated once the
5680 * DPLL is enabled and the clocks are stable.
5681 *
5682 * So write it again.
5683 */
ee7b9f93 5684 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5685 }
79e53945 5686
5eddb70b 5687 intel_crtc->lowfreq_avail = false;
ee7b9f93 5688 if (intel_crtc->pch_pll) {
4b645f14 5689 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5690 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5691 intel_crtc->lowfreq_avail = true;
4b645f14 5692 } else {
ee7b9f93 5693 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5694 }
5695 }
5696
b0e77b9c 5697 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5698
01a415fd
DV		 5699 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5700 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5701 intel_crtc->fdi_lanes = 0;
5702 if (intel_crtc->config.has_pch_encoder)
5703 ironlake_fdi_set_m_n(crtc);
2c07245f 5704
01a415fd 5705 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5706
c8203565 5707 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5708
9d0498a2 5709 intel_wait_for_vblank(dev, pipe);
79e53945 5710
a1f9e77e
PZ		 5711 /* Set up the display plane register */
5712 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5713 POSTING_READ(DSPCNTR(plane));
79e53945 5714
94352cf9 5715 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5716
5717 intel_update_watermarks(dev);
5718
1f8eeabf
ED		 5719 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5720
01a415fd 5721 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5722}
5723
0e8ffe1b
DV		 5724static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5725 struct intel_crtc_config *pipe_config)
5726{
5727 struct drm_device *dev = crtc->base.dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 uint32_t tmp;
5730
5731 tmp = I915_READ(PIPECONF(crtc->pipe));
5732 if (!(tmp & PIPECONF_ENABLE))
5733 return false;
5734
88adfff1
DV		 5735 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5736 pipe_config->has_pch_encoder = true;
5737
0e8ffe1b
DV		 5738 return true;
5739}
5740
d6dd9eb1
DV		 5741static void haswell_modeset_global_resources(struct drm_device *dev)
5742{
5743 struct drm_i915_private *dev_priv = dev->dev_private;
5744 bool enable = false;
5745 struct intel_crtc *crtc;
5746 struct intel_encoder *encoder;
5747
5748 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5749 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5750 enable = true;
5751 /* XXX: Should check for edp transcoder here, but thanks to init
5752 * sequence that's not yet available. Just in case desktop eDP
5753 * on PORT D is possible on haswell, too. */
5754 }
5755
5756 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5757 base.head) {
5758 if (encoder->type != INTEL_OUTPUT_EDP &&
5759 encoder->connectors_active)
5760 enable = true;
5761 }
5762
5763 /* Even the eDP panel fitter is outside the always-on well. */
5764 if (dev_priv->pch_pf_size)
5765 enable = true;
5766
5767 intel_set_power_well(dev, enable);
5768}
5769
09b4ddf9 5770static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5771 int x, int y,
5772 struct drm_framebuffer *fb)
5773{
5774 struct drm_device *dev = crtc->dev;
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5777 struct drm_display_mode *adjusted_mode =
5778 &intel_crtc->config.adjusted_mode;
5779 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5780 int pipe = intel_crtc->pipe;
5781 int plane = intel_crtc->plane;
5782 int num_connectors = 0;
8b47047b 5783 bool is_cpu_edp = false;
09b4ddf9 5784 struct intel_encoder *encoder;
09b4ddf9
PZ		 5785 int ret;
5786 bool dither;
5787
5788 for_each_encoder_on_crtc(dev, crtc, encoder) {
5789 switch (encoder->type) {
09b4ddf9 5790 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5791 if (!intel_encoder_is_pch_edp(&encoder->base))
5792 is_cpu_edp = true;
5793 break;
5794 }
5795
5796 num_connectors++;
5797 }
5798
bba2181c
DV		 5799 if (is_cpu_edp)
5800 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5801 else
5802 intel_crtc->cpu_transcoder = pipe;
5803
5dc5298b
PZ		 5804 /* We are not sure yet this won't happen. */
5805 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5806 INTEL_PCH_TYPE(dev));
5807
5808 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5809 num_connectors, pipe_name(pipe));
5810
702e7a56 5811 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5812 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5813
5814 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5815
6441ab5f
PZ		 5816 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5817 return -EINVAL;
5818
09b4ddf9
PZ		 5819 /* Ensure that the cursor is valid for the new mode before changing... */
5820 intel_crtc_update_cursor(crtc, true);
5821
5822 /* determine panel color depth */
4e53c2e0 5823 dither = intel_crtc->config.dither;
09b4ddf9 5824
09b4ddf9
PZ		 5825 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5826 drm_mode_debug_printmodeline(mode);
5827
03afc4a2
DV		 5828 if (intel_crtc->config.has_dp_encoder)
5829 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5830
5831 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5832
5833 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5834
6cf86a5e
DV		 5835 if (intel_crtc->config.has_pch_encoder)
5836 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5837
ee2b0b38 5838 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5839
50f3b016 5840 intel_set_pipe_csc(crtc);
86d3efce 5841
09b4ddf9 5842 /* Set up the display plane register */
86d3efce 5843 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5844 POSTING_READ(DSPCNTR(plane));
5845
5846 ret = intel_pipe_set_base(crtc, x, y, fb);
5847
5848 intel_update_watermarks(dev);
5849
5850 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5851
1f803ee5 5852 return ret;
79e53945
JB		 5853}
5854
0e8ffe1b
DV		 5855static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5856 struct intel_crtc_config *pipe_config)
5857{
5858 struct drm_device *dev = crtc->base.dev;
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 uint32_t tmp;
5861
5862 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
5863 if (!(tmp & PIPECONF_ENABLE))
5864 return false;
5865
88adfff1
DV		 5866 /*
5867 * aswell has only FDI/PCH transcoder A. It is which is connected to
5868 * DDI E. So just check whether this pipe is wired to DDI E and whether
5869 * the PCH transcoder is on.
5870 */
5871 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5872 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5873 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5874 pipe_config->has_pch_encoder = true;
5875
5876
0e8ffe1b
DV		 5877 return true;
5878}
5879
f564048e 5880static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5881 int x, int y,
94352cf9 5882 struct drm_framebuffer *fb)
f564048e
EA		 5883{
5884 struct drm_device *dev = crtc->dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5886 struct drm_encoder_helper_funcs *encoder_funcs;
5887 struct intel_encoder *encoder;
0b701d27 5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5889 struct drm_display_mode *adjusted_mode =
5890 &intel_crtc->config.adjusted_mode;
5891 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5892 int pipe = intel_crtc->pipe;
f564048e
EA		 5893 int ret;
5894
0b701d27 5895 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5896
b8cecdf5
DV		 5897 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5898
79e53945 5899 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5900
9256aa19
DV		 5901 if (ret != 0)
5902 return ret;
5903
5904 for_each_encoder_on_crtc(dev, crtc, encoder) {
5905 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5906 encoder->base.base.id,
5907 drm_get_encoder_name(&encoder->base),
5908 mode->base.id, mode->name);
6cc5f341
DV		 5909 if (encoder->mode_set) {
5910 encoder->mode_set(encoder);
5911 } else {
5912 encoder_funcs = encoder->base.helper_private;
5913 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5914 }
9256aa19
DV		 5915 }
5916
5917 return 0;
79e53945
JB		 5918}
5919
3a9627f4
WF		 5920static bool intel_eld_uptodate(struct drm_connector *connector,
5921 int reg_eldv, uint32_t bits_eldv,
5922 int reg_elda, uint32_t bits_elda,
5923 int reg_edid)
5924{
5925 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5926 uint8_t *eld = connector->eld;
5927 uint32_t i;
5928
5929 i = I915_READ(reg_eldv);
5930 i &= bits_eldv;
5931
5932 if (!eld[0])
5933 return !i;
5934
5935 if (!i)
5936 return false;
5937
5938 i = I915_READ(reg_elda);
5939 i &= ~bits_elda;
5940 I915_WRITE(reg_elda, i);
5941
5942 for (i = 0; i < eld[2]; i++)
5943 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5944 return false;
5945
5946 return true;
5947}
5948
e0dac65e
WF		 5949static void g4x_write_eld(struct drm_connector *connector,
5950 struct drm_crtc *crtc)
5951{
5952 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5953 uint8_t *eld = connector->eld;
5954 uint32_t eldv;
5955 uint32_t len;
5956 uint32_t i;
5957
5958 i = I915_READ(G4X_AUD_VID_DID);
5959
5960 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5961 eldv = G4X_ELDV_DEVCL_DEVBLC;
5962 else
5963 eldv = G4X_ELDV_DEVCTG;
5964
3a9627f4
WF		 5965 if (intel_eld_uptodate(connector,
5966 G4X_AUD_CNTL_ST, eldv,
5967 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5968 G4X_HDMIW_HDMIEDID))
5969 return;
5970
e0dac65e
WF		 5971 i = I915_READ(G4X_AUD_CNTL_ST);
5972 i &= ~(eldv | G4X_ELD_ADDR);
5973 len = (i >> 9) & 0x1f; /* ELD buffer size */
5974 I915_WRITE(G4X_AUD_CNTL_ST, i);
5975
5976 if (!eld[0])
5977 return;
5978
5979 len = min_t(uint8_t, eld[2], len);
5980 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5981 for (i = 0; i < len; i++)
5982 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5983
5984 i = I915_READ(G4X_AUD_CNTL_ST);
5985 i |= eldv;
5986 I915_WRITE(G4X_AUD_CNTL_ST, i);
5987}
5988
83358c85
WX		 5989static void haswell_write_eld(struct drm_connector *connector,
5990 struct drm_crtc *crtc)
5991{
5992 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5993 uint8_t *eld = connector->eld;
5994 struct drm_device *dev = crtc->dev;
7b9f35a6 5995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5996 uint32_t eldv;
5997 uint32_t i;
5998 int len;
5999 int pipe = to_intel_crtc(crtc)->pipe;
6000 int tmp;
6001
6002 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6003 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6004 int aud_config = HSW_AUD_CFG(pipe);
6005 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6006
6007
6008 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6009
6010 /* Audio output enable */
6011 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6012 tmp = I915_READ(aud_cntrl_st2);
6013 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6014 I915_WRITE(aud_cntrl_st2, tmp);
6015
6016 /* Wait for 1 vertical blank */
6017 intel_wait_for_vblank(dev, pipe);
6018
6019 /* Set ELD valid state */
6020 tmp = I915_READ(aud_cntrl_st2);
6021 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6022 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6023 I915_WRITE(aud_cntrl_st2, tmp);
6024 tmp = I915_READ(aud_cntrl_st2);
6025 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6026
6027 /* Enable HDMI mode */
6028 tmp = I915_READ(aud_config);
6029 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6030 /* clear N_programing_enable and N_value_index */
6031 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6032 I915_WRITE(aud_config, tmp);
6033
6034 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6035
6036 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6037 intel_crtc->eld_vld = true;
83358c85
WX		 6038
6039 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6040 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6041 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6042 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6043 } else
6044 I915_WRITE(aud_config, 0);
6045
6046 if (intel_eld_uptodate(connector,
6047 aud_cntrl_st2, eldv,
6048 aud_cntl_st, IBX_ELD_ADDRESS,
6049 hdmiw_hdmiedid))
6050 return;
6051
6052 i = I915_READ(aud_cntrl_st2);
6053 i &= ~eldv;
6054 I915_WRITE(aud_cntrl_st2, i);
6055
6056 if (!eld[0])
6057 return;
6058
6059 i = I915_READ(aud_cntl_st);
6060 i &= ~IBX_ELD_ADDRESS;
6061 I915_WRITE(aud_cntl_st, i);
6062 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6063 DRM_DEBUG_DRIVER("port num:%d\n", i);
6064
6065 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6066 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6067 for (i = 0; i < len; i++)
6068 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6069
6070 i = I915_READ(aud_cntrl_st2);
6071 i |= eldv;
6072 I915_WRITE(aud_cntrl_st2, i);
6073
6074}
6075
e0dac65e
WF		 6076static void ironlake_write_eld(struct drm_connector *connector,
6077 struct drm_crtc *crtc)
6078{
6079 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6080 uint8_t *eld = connector->eld;
6081 uint32_t eldv;
6082 uint32_t i;
6083 int len;
6084 int hdmiw_hdmiedid;
b6daa025 6085 int aud_config;
e0dac65e
WF		 6086 int aud_cntl_st;
6087 int aud_cntrl_st2;
9b138a83 6088 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6089
b3f33cbf 6090 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6091 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6092 aud_config = IBX_AUD_CFG(pipe);
6093 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6094 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6095 } else {
9b138a83
WX		 6096 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6097 aud_config = CPT_AUD_CFG(pipe);
6098 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6099 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6100 }
6101
9b138a83 6102 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6103
6104 i = I915_READ(aud_cntl_st);
9b138a83 6105 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6106 if (!i) {
6107 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6108 /* operate blindly on all ports */
1202b4c6
WF		 6109 eldv = IBX_ELD_VALIDB;
6110 eldv |= IBX_ELD_VALIDB << 4;
6111 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6112 } else {
6113 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6114 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6115 }
6116
3a9627f4
WF		 6117 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6118 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6119 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6120 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6121 } else
6122 I915_WRITE(aud_config, 0);
e0dac65e 6123
3a9627f4
WF		 6124 if (intel_eld_uptodate(connector,
6125 aud_cntrl_st2, eldv,
6126 aud_cntl_st, IBX_ELD_ADDRESS,
6127 hdmiw_hdmiedid))
6128 return;
6129
e0dac65e
WF		 6130 i = I915_READ(aud_cntrl_st2);
6131 i &= ~eldv;
6132 I915_WRITE(aud_cntrl_st2, i);
6133
6134 if (!eld[0])
6135 return;
6136
e0dac65e 6137 i = I915_READ(aud_cntl_st);
1202b4c6 6138 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6139 I915_WRITE(aud_cntl_st, i);
6140
6141 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6142 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6143 for (i = 0; i < len; i++)
6144 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6145
6146 i = I915_READ(aud_cntrl_st2);
6147 i |= eldv;
6148 I915_WRITE(aud_cntrl_st2, i);
6149}
6150
6151void intel_write_eld(struct drm_encoder *encoder,
6152 struct drm_display_mode *mode)
6153{
6154 struct drm_crtc *crtc = encoder->crtc;
6155 struct drm_connector *connector;
6156 struct drm_device *dev = encoder->dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158
6159 connector = drm_select_eld(encoder, mode);
6160 if (!connector)
6161 return;
6162
6163 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6164 connector->base.id,
6165 drm_get_connector_name(connector),
6166 connector->encoder->base.id,
6167 drm_get_encoder_name(connector->encoder));
6168
6169 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6170
6171 if (dev_priv->display.write_eld)
6172 dev_priv->display.write_eld(connector, crtc);
6173}
6174
79e53945
JB		 6175/** Loads the palette/gamma unit for the CRTC with the prepared values */
6176void intel_crtc_load_lut(struct drm_crtc *crtc)
6177{
6178 struct drm_device *dev = crtc->dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6181 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6182 int i;
6183
6184 /* The clocks have to be on to load the palette. */
aed3f09d 6185 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6186 return;
6187
f2b115e6 6188 /* use legacy palette for Ironlake */
bad720ff 6189 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6190 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6191
79e53945
JB		 6192 for (i = 0; i < 256; i++) {
6193 I915_WRITE(palreg + 4 * i,
6194 (intel_crtc->lut_r[i] << 16) |
6195 (intel_crtc->lut_g[i] << 8) |
6196 intel_crtc->lut_b[i]);
6197 }
6198}
6199
560b85bb
CW		 6200static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6201{
6202 struct drm_device *dev = crtc->dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205 bool visible = base != 0;
6206 u32 cntl;
6207
6208 if (intel_crtc->cursor_visible == visible)
6209 return;
6210
9db4a9c7 6211 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6212 if (visible) {
6213 /* On these chipsets we can only modify the base whilst
6214 * the cursor is disabled.
6215 */
9db4a9c7 6216 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6217
6218 cntl &= ~(CURSOR_FORMAT_MASK);
6219 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6220 cntl |= CURSOR_ENABLE |
6221 CURSOR_GAMMA_ENABLE |
6222 CURSOR_FORMAT_ARGB;
6223 } else
6224 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6225 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6226
6227 intel_crtc->cursor_visible = visible;
6228}
6229
6230static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6231{
6232 struct drm_device *dev = crtc->dev;
6233 struct drm_i915_private *dev_priv = dev->dev_private;
6234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6235 int pipe = intel_crtc->pipe;
6236 bool visible = base != 0;
6237
6238 if (intel_crtc->cursor_visible != visible) {
548f245b 6239 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6240 if (base) {
6241 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6242 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6243 cntl |= pipe << 28; /* Connect to correct pipe */
6244 } else {
6245 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6246 cntl |= CURSOR_MODE_DISABLE;
6247 }
9db4a9c7 6248 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6249
6250 intel_crtc->cursor_visible = visible;
6251 }
6252 /* and commit changes on next vblank */
9db4a9c7 6253 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6254}
6255
65a21cd6
JB		 6256static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6257{
6258 struct drm_device *dev = crtc->dev;
6259 struct drm_i915_private *dev_priv = dev->dev_private;
6260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6261 int pipe = intel_crtc->pipe;
6262 bool visible = base != 0;
6263
6264 if (intel_crtc->cursor_visible != visible) {
6265 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6266 if (base) {
6267 cntl &= ~CURSOR_MODE;
6268 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6269 } else {
6270 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6271 cntl |= CURSOR_MODE_DISABLE;
6272 }
86d3efce
VS		 6273 if (IS_HASWELL(dev))
6274 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6275 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6276
6277 intel_crtc->cursor_visible = visible;
6278 }
6279 /* and commit changes on next vblank */
6280 I915_WRITE(CURBASE_IVB(pipe), base);
6281}
6282
cda4b7d3 6283/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6284static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6285 bool on)
cda4b7d3
CW		 6286{
6287 struct drm_device *dev = crtc->dev;
6288 struct drm_i915_private *dev_priv = dev->dev_private;
6289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290 int pipe = intel_crtc->pipe;
6291 int x = intel_crtc->cursor_x;
6292 int y = intel_crtc->cursor_y;
560b85bb 6293 u32 base, pos;
cda4b7d3
CW		 6294 bool visible;
6295
6296 pos = 0;
6297
6b383a7f 6298 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6299 base = intel_crtc->cursor_addr;
6300 if (x > (int) crtc->fb->width)
6301 base = 0;
6302
6303 if (y > (int) crtc->fb->height)
6304 base = 0;
6305 } else
6306 base = 0;
6307
6308 if (x < 0) {
6309 if (x + intel_crtc->cursor_width < 0)
6310 base = 0;
6311
6312 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6313 x = -x;
6314 }
6315 pos |= x << CURSOR_X_SHIFT;
6316
6317 if (y < 0) {
6318 if (y + intel_crtc->cursor_height < 0)
6319 base = 0;
6320
6321 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6322 y = -y;
6323 }
6324 pos |= y << CURSOR_Y_SHIFT;
6325
6326 visible = base != 0;
560b85bb 6327 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6328 return;
6329
0cd83aa9 6330 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6331 I915_WRITE(CURPOS_IVB(pipe), pos);
6332 ivb_update_cursor(crtc, base);
6333 } else {
6334 I915_WRITE(CURPOS(pipe), pos);
6335 if (IS_845G(dev) || IS_I865G(dev))
6336 i845_update_cursor(crtc, base);
6337 else
6338 i9xx_update_cursor(crtc, base);
6339 }
cda4b7d3
CW		 6340}
6341
79e53945 6342static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6343 struct drm_file *file,
79e53945
JB		 6344 uint32_t handle,
6345 uint32_t width, uint32_t height)
6346{
6347 struct drm_device *dev = crtc->dev;
6348 struct drm_i915_private *dev_priv = dev->dev_private;
6349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6350 struct drm_i915_gem_object *obj;
cda4b7d3 6351 uint32_t addr;
3f8bc370 6352 int ret;
79e53945 6353
79e53945
JB		 6354 /* if we want to turn off the cursor ignore width and height */
6355 if (!handle) {
28c97730 6356 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6357 addr = 0;
05394f39 6358 obj = NULL;
5004417d 6359 mutex_lock(&dev->struct_mutex);
3f8bc370 6360 goto finish;
79e53945
JB		 6361 }
6362
6363 /* Currently we only support 64x64 cursors */
6364 if (width != 64 || height != 64) {
6365 DRM_ERROR("we currently only support 64x64 cursors\n");
6366 return -EINVAL;
6367 }
6368
05394f39 6369 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6370 if (&obj->base == NULL)
79e53945
JB		 6371 return -ENOENT;
6372
05394f39 6373 if (obj->base.size < width * height * 4) {
79e53945 6374 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6375 ret = -ENOMEM;
6376 goto fail;
79e53945
JB		 6377 }
6378
71acb5eb 6379 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6380 mutex_lock(&dev->struct_mutex);
b295d1b6 6381 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6382 unsigned alignment;
6383
d9e86c0e
CW		 6384 if (obj->tiling_mode) {
6385 DRM_ERROR("cursor cannot be tiled\n");
6386 ret = -EINVAL;
6387 goto fail_locked;
6388 }
6389
693db184
CW		 6390 /* Note that the w/a also requires 2 PTE of padding following
6391 * the bo. We currently fill all unused PTE with the shadow
6392 * page and so we should always have valid PTE following the
6393 * cursor preventing the VT-d warning.
6394 */
6395 alignment = 0;
6396 if (need_vtd_wa(dev))
6397 alignment = 64*1024;
6398
6399 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6400 if (ret) {
6401 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6402 goto fail_locked;
e7b526bb
CW		 6403 }
6404
d9e86c0e
CW		 6405 ret = i915_gem_object_put_fence(obj);
6406 if (ret) {
2da3b9b9 6407 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6408 goto fail_unpin;
6409 }
6410
05394f39 6411 addr = obj->gtt_offset;
71acb5eb 6412 } else {
6eeefaf3 6413 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6414 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6415 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6416 align);
71acb5eb
DA		 6417 if (ret) {
6418 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6419 goto fail_locked;
71acb5eb 6420 }
05394f39 6421 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6422 }
6423
a6c45cf0 6424 if (IS_GEN2(dev))
14b60391
JB		 6425 I915_WRITE(CURSIZE, (height << 12) | width);
6426
3f8bc370 6427 finish:
3f8bc370 6428 if (intel_crtc->cursor_bo) {
b295d1b6 6429 if (dev_priv->info->cursor_needs_physical) {
05394f39 6430 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6431 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6432 } else
6433 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6434 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6435 }
80824003 6436
7f9872e0 6437 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6438
6439 intel_crtc->cursor_addr = addr;
05394f39 6440 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6441 intel_crtc->cursor_width = width;
6442 intel_crtc->cursor_height = height;
6443
6b383a7f 6444 intel_crtc_update_cursor(crtc, true);
3f8bc370 6445
79e53945 6446 return 0;
e7b526bb 6447fail_unpin:
05394f39 6448 i915_gem_object_unpin(obj);
7f9872e0 6449fail_locked:
34b8686e 6450 mutex_unlock(&dev->struct_mutex);
bc9025bd 6451fail:
05394f39 6452 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6453 return ret;
79e53945
JB		 6454}
6455
6456static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6457{
79e53945 6458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6459
cda4b7d3
CW		 6460 intel_crtc->cursor_x = x;
6461 intel_crtc->cursor_y = y;
652c393a 6462
6b383a7f 6463 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6464
6465 return 0;
6466}
6467
6468/** Sets the color ramps on behalf of RandR */
6469void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6470 u16 blue, int regno)
6471{
6472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473
6474 intel_crtc->lut_r[regno] = red >> 8;
6475 intel_crtc->lut_g[regno] = green >> 8;
6476 intel_crtc->lut_b[regno] = blue >> 8;
6477}
6478
b8c00ac5
DA		 6479void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6480 u16 *blue, int regno)
6481{
6482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6483
6484 *red = intel_crtc->lut_r[regno] << 8;
6485 *green = intel_crtc->lut_g[regno] << 8;
6486 *blue = intel_crtc->lut_b[regno] << 8;
6487}
6488
79e53945 6489static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6490 u16 *blue, uint32_t start, uint32_t size)
79e53945 6491{
7203425a 6492 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6494
7203425a 6495 for (i = start; i < end; i++) {
79e53945
JB		 6496 intel_crtc->lut_r[i] = red[i] >> 8;
6497 intel_crtc->lut_g[i] = green[i] >> 8;
6498 intel_crtc->lut_b[i] = blue[i] >> 8;
6499 }
6500
6501 intel_crtc_load_lut(crtc);
6502}
6503
79e53945
JB		 6504/* VESA 640x480x72Hz mode to set on the pipe */
6505static struct drm_display_mode load_detect_mode = {
6506 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6507 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6508};
6509
d2dff872
CW		 6510static struct drm_framebuffer *
6511intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6512 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6513 struct drm_i915_gem_object *obj)
6514{
6515 struct intel_framebuffer *intel_fb;
6516 int ret;
6517
6518 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6519 if (!intel_fb) {
6520 drm_gem_object_unreference_unlocked(&obj->base);
6521 return ERR_PTR(-ENOMEM);
6522 }
6523
6524 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6525 if (ret) {
6526 drm_gem_object_unreference_unlocked(&obj->base);
6527 kfree(intel_fb);
6528 return ERR_PTR(ret);
6529 }
6530
6531 return &intel_fb->base;
6532}
6533
6534static u32
6535intel_framebuffer_pitch_for_width(int width, int bpp)
6536{
6537 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6538 return ALIGN(pitch, 64);
6539}
6540
6541static u32
6542intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6543{
6544 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6545 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6546}
6547
6548static struct drm_framebuffer *
6549intel_framebuffer_create_for_mode(struct drm_device *dev,
6550 struct drm_display_mode *mode,
6551 int depth, int bpp)
6552{
6553 struct drm_i915_gem_object *obj;
0fed39bd 6554 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6555
6556 obj = i915_gem_alloc_object(dev,
6557 intel_framebuffer_size_for_mode(mode, bpp));
6558 if (obj == NULL)
6559 return ERR_PTR(-ENOMEM);
6560
6561 mode_cmd.width = mode->hdisplay;
6562 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6563 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6564 bpp);
5ca0c34a 6565 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6566
6567 return intel_framebuffer_create(dev, &mode_cmd, obj);
6568}
6569
6570static struct drm_framebuffer *
6571mode_fits_in_fbdev(struct drm_device *dev,
6572 struct drm_display_mode *mode)
6573{
6574 struct drm_i915_private *dev_priv = dev->dev_private;
6575 struct drm_i915_gem_object *obj;
6576 struct drm_framebuffer *fb;
6577
6578 if (dev_priv->fbdev == NULL)
6579 return NULL;
6580
6581 obj = dev_priv->fbdev->ifb.obj;
6582 if (obj == NULL)
6583 return NULL;
6584
6585 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6586 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6587 fb->bits_per_pixel))
d2dff872
CW		 6588 return NULL;
6589
01f2c773 6590 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6591 return NULL;
6592
6593 return fb;
6594}
6595
d2434ab7 6596bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6597 struct drm_display_mode *mode,
8261b191 6598 struct intel_load_detect_pipe *old)
79e53945
JB		 6599{
6600 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6601 struct intel_encoder *intel_encoder =
6602 intel_attached_encoder(connector);
79e53945 6603 struct drm_crtc *possible_crtc;
4ef69c7a 6604 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6605 struct drm_crtc *crtc = NULL;
6606 struct drm_device *dev = encoder->dev;
94352cf9 6607 struct drm_framebuffer *fb;
79e53945
JB		 6608 int i = -1;
6609
d2dff872
CW		 6610 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6611 connector->base.id, drm_get_connector_name(connector),
6612 encoder->base.id, drm_get_encoder_name(encoder));
6613
79e53945
JB		 6614 /*
6615 * Algorithm gets a little messy:
7a5e4805 6616 *
79e53945
JB		 6617 * - if the connector already has an assigned crtc, use it (but make
6618 * sure it's on first)
7a5e4805 6619 *
79e53945
JB		 6620 * - try to find the first unused crtc that can drive this connector,
6621 * and use that if we find one
79e53945
JB		 6622 */
6623
6624 /* See if we already have a CRTC for this connector */
6625 if (encoder->crtc) {
6626 crtc = encoder->crtc;
8261b191 6627
7b24056b
DV		 6628 mutex_lock(&crtc->mutex);
6629
24218aac 6630 old->dpms_mode = connector->dpms;
8261b191
CW		 6631 old->load_detect_temp = false;
6632
6633 /* Make sure the crtc and connector are running */
24218aac
DV		 6634 if (connector->dpms != DRM_MODE_DPMS_ON)
6635 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6636
7173188d 6637 return true;
79e53945
JB		 6638 }
6639
6640 /* Find an unused one (if possible) */
6641 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6642 i++;
6643 if (!(encoder->possible_crtcs & (1 << i)))
6644 continue;
6645 if (!possible_crtc->enabled) {
6646 crtc = possible_crtc;
6647 break;
6648 }
79e53945
JB		 6649 }
6650
6651 /*
6652 * If we didn't find an unused CRTC, don't use any.
6653 */
6654 if (!crtc) {
7173188d
CW		 6655 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6656 return false;
79e53945
JB		 6657 }
6658
7b24056b 6659 mutex_lock(&crtc->mutex);
fc303101
DV		 6660 intel_encoder->new_crtc = to_intel_crtc(crtc);
6661 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6662
6663 intel_crtc = to_intel_crtc(crtc);
24218aac 6664 old->dpms_mode = connector->dpms;
8261b191 6665 old->load_detect_temp = true;
d2dff872 6666 old->release_fb = NULL;
79e53945 6667
6492711d
CW		 6668 if (!mode)
6669 mode = &load_detect_mode;
79e53945 6670
d2dff872
CW		 6671 /* We need a framebuffer large enough to accommodate all accesses
6672 * that the plane may generate whilst we perform load detection.
6673 * We can not rely on the fbcon either being present (we get called
6674 * during its initialisation to detect all boot displays, or it may
6675 * not even exist) or that it is large enough to satisfy the
6676 * requested mode.
6677 */
94352cf9
DV		 6678 fb = mode_fits_in_fbdev(dev, mode);
6679 if (fb == NULL) {
d2dff872 6680 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6681 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6682 old->release_fb = fb;
d2dff872
CW		 6683 } else
6684 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6685 if (IS_ERR(fb)) {
d2dff872 6686 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6687 mutex_unlock(&crtc->mutex);
0e8b3d3e 6688 return false;
79e53945 6689 }
79e53945 6690
c0c36b94 6691 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6692 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6693 if (old->release_fb)
6694 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6695 mutex_unlock(&crtc->mutex);
0e8b3d3e 6696 return false;
79e53945 6697 }
7173188d 6698
79e53945 6699 /* let the connector get through one full cycle before testing */
9d0498a2 6700 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6701 return true;
79e53945
JB		 6702}
6703
d2434ab7 6704void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6705 struct intel_load_detect_pipe *old)
79e53945 6706{
d2434ab7
DV		 6707 struct intel_encoder *intel_encoder =
6708 intel_attached_encoder(connector);
4ef69c7a 6709 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6710 struct drm_crtc *crtc = encoder->crtc;
79e53945 6711
d2dff872
CW		 6712 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6713 connector->base.id, drm_get_connector_name(connector),
6714 encoder->base.id, drm_get_encoder_name(encoder));
6715
8261b191 6716 if (old->load_detect_temp) {
fc303101
DV		 6717 to_intel_connector(connector)->new_encoder = NULL;
6718 intel_encoder->new_crtc = NULL;
6719 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6720
36206361
DV		 6721 if (old->release_fb) {
6722 drm_framebuffer_unregister_private(old->release_fb);
6723 drm_framebuffer_unreference(old->release_fb);
6724 }
d2dff872 6725
67c96400 6726 mutex_unlock(&crtc->mutex);
0622a53c 6727 return;
79e53945
JB		 6728 }
6729
c751ce4f 6730 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6731 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6732 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6733
6734 mutex_unlock(&crtc->mutex);
79e53945
JB		 6735}
6736
6737/* Returns the clock of the currently programmed mode of the given pipe. */
6738static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6739{
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6742 int pipe = intel_crtc->pipe;
548f245b 6743 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6744 u32 fp;
6745 intel_clock_t clock;
6746
6747 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6748 fp = I915_READ(FP0(pipe));
79e53945 6749 else
39adb7a5 6750 fp = I915_READ(FP1(pipe));
79e53945
JB		 6751
6752 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6753 if (IS_PINEVIEW(dev)) {
6754 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6755 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6756 } else {
6757 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6758 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6759 }
6760
a6c45cf0 6761 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6762 if (IS_PINEVIEW(dev))
6763 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6764 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6765 else
6766 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6767 DPLL_FPA01_P1_POST_DIV_SHIFT);
6768
6769 switch (dpll & DPLL_MODE_MASK) {
6770 case DPLLB_MODE_DAC_SERIAL:
6771 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6772 5 : 10;
6773 break;
6774 case DPLLB_MODE_LVDS:
6775 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6776 7 : 14;
6777 break;
6778 default:
28c97730 6779 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6780 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6781 return 0;
6782 }
6783
6784 /* XXX: Handle the 100Mhz refclk */
2177832f 6785 intel_clock(dev, 96000, &clock);
79e53945
JB		 6786 } else {
6787 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6788
6789 if (is_lvds) {
6790 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6791 DPLL_FPA01_P1_POST_DIV_SHIFT);
6792 clock.p2 = 14;
6793
6794 if ((dpll & PLL_REF_INPUT_MASK) ==
6795 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6796 /* XXX: might not be 66MHz */
2177832f 6797 intel_clock(dev, 66000, &clock);
79e53945 6798 } else
2177832f 6799 intel_clock(dev, 48000, &clock);
79e53945
JB		 6800 } else {
6801 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6802 clock.p1 = 2;
6803 else {
6804 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6805 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6806 }
6807 if (dpll & PLL_P2_DIVIDE_BY_4)
6808 clock.p2 = 4;
6809 else
6810 clock.p2 = 2;
6811
2177832f 6812 intel_clock(dev, 48000, &clock);
79e53945
JB		 6813 }
6814 }
6815
6816 /* XXX: It would be nice to validate the clocks, but we can't reuse
6817 * i830PllIsValid() because it relies on the xf86_config connector
6818 * configuration being accurate, which it isn't necessarily.
6819 */
6820
6821 return clock.dot;
6822}
6823
6824/** Returns the currently programmed mode of the given pipe. */
6825struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6826 struct drm_crtc *crtc)
6827{
548f245b 6828 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6830 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6831 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6832 int htot = I915_READ(HTOTAL(cpu_transcoder));
6833 int hsync = I915_READ(HSYNC(cpu_transcoder));
6834 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6835 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6836
6837 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6838 if (!mode)
6839 return NULL;
6840
6841 mode->clock = intel_crtc_clock_get(dev, crtc);
6842 mode->hdisplay = (htot & 0xffff) + 1;
6843 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6844 mode->hsync_start = (hsync & 0xffff) + 1;
6845 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6846 mode->vdisplay = (vtot & 0xffff) + 1;
6847 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6848 mode->vsync_start = (vsync & 0xffff) + 1;
6849 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6850
6851 drm_mode_set_name(mode);
79e53945
JB		 6852
6853 return mode;
6854}
6855
3dec0095 6856static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6857{
6858 struct drm_device *dev = crtc->dev;
6859 drm_i915_private_t *dev_priv = dev->dev_private;
6860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6861 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6862 int dpll_reg = DPLL(pipe);
6863 int dpll;
652c393a 6864
bad720ff 6865 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6866 return;
6867
6868 if (!dev_priv->lvds_downclock_avail)
6869 return;
6870
dbdc6479 6871 dpll = I915_READ(dpll_reg);
652c393a 6872 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6873 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6874
8ac5a6d5 6875 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6876
6877 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6878 I915_WRITE(dpll_reg, dpll);
9d0498a2 6879 intel_wait_for_vblank(dev, pipe);
dbdc6479 6880
652c393a
JB		 6881 dpll = I915_READ(dpll_reg);
6882 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6883 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6884 }
652c393a
JB		 6885}
6886
6887static void intel_decrease_pllclock(struct drm_crtc *crtc)
6888{
6889 struct drm_device *dev = crtc->dev;
6890 drm_i915_private_t *dev_priv = dev->dev_private;
6891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6892
bad720ff 6893 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6894 return;
6895
6896 if (!dev_priv->lvds_downclock_avail)
6897 return;
6898
6899 /*
6900 * Since this is called by a timer, we should never get here in
6901 * the manual case.
6902 */
6903 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6904 int pipe = intel_crtc->pipe;
6905 int dpll_reg = DPLL(pipe);
6906 int dpll;
f6e5b160 6907
44d98a61 6908 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6909
8ac5a6d5 6910 assert_panel_unlocked(dev_priv, pipe);
652c393a 6911
dc257cf1 6912 dpll = I915_READ(dpll_reg);
652c393a
JB		 6913 dpll |= DISPLAY_RATE_SELECT_FPA1;
6914 I915_WRITE(dpll_reg, dpll);
9d0498a2 6915 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6916 dpll = I915_READ(dpll_reg);
6917 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6918 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6919 }
6920
6921}
6922
f047e395
CW		 6923void intel_mark_busy(struct drm_device *dev)
6924{
f047e395
CW		 6925 i915_update_gfx_val(dev->dev_private);
6926}
6927
6928void intel_mark_idle(struct drm_device *dev)
652c393a 6929{
652c393a 6930 struct drm_crtc *crtc;
652c393a
JB		 6931
6932 if (!i915_powersave)
6933 return;
6934
652c393a 6935 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6936 if (!crtc->fb)
6937 continue;
6938
725a5b54 6939 intel_decrease_pllclock(crtc);
652c393a 6940 }
652c393a
JB		 6941}
6942
725a5b54 6943void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6944{
f047e395
CW		 6945 struct drm_device *dev = obj->base.dev;
6946 struct drm_crtc *crtc;
652c393a 6947
f047e395 6948 if (!i915_powersave)
acb87dfb
CW		 6949 return;
6950
652c393a
JB		 6951 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6952 if (!crtc->fb)
6953 continue;
6954
f047e395 6955 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6956 intel_increase_pllclock(crtc);
652c393a
JB		 6957 }
6958}
6959
79e53945
JB		 6960static void intel_crtc_destroy(struct drm_crtc *crtc)
6961{
6962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6963 struct drm_device *dev = crtc->dev;
6964 struct intel_unpin_work *work;
6965 unsigned long flags;
6966
6967 spin_lock_irqsave(&dev->event_lock, flags);
6968 work = intel_crtc->unpin_work;
6969 intel_crtc->unpin_work = NULL;
6970 spin_unlock_irqrestore(&dev->event_lock, flags);
6971
6972 if (work) {
6973 cancel_work_sync(&work->work);
6974 kfree(work);
6975 }
79e53945
JB		 6976
6977 drm_crtc_cleanup(crtc);
67e77c5a 6978
79e53945
JB		 6979 kfree(intel_crtc);
6980}
6981
6b95a207
KH		 6982static void intel_unpin_work_fn(struct work_struct *__work)
6983{
6984 struct intel_unpin_work *work =
6985 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6986 struct drm_device *dev = work->crtc->dev;
6b95a207 6987
b4a98e57 6988 mutex_lock(&dev->struct_mutex);
1690e1eb 6989 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6990 drm_gem_object_unreference(&work->pending_flip_obj->base);
6991 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6992
b4a98e57
CW		 6993 intel_update_fbc(dev);
6994 mutex_unlock(&dev->struct_mutex);
6995
6996 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6997 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6998
6b95a207
KH		 6999 kfree(work);
7000}
7001
1afe3e9d 7002static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7003 struct drm_crtc *crtc)
6b95a207
KH		 7004{
7005 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007 struct intel_unpin_work *work;
6b95a207
KH		 7008 unsigned long flags;
7009
7010 /* Ignore early vblank irqs */
7011 if (intel_crtc == NULL)
7012 return;
7013
7014 spin_lock_irqsave(&dev->event_lock, flags);
7015 work = intel_crtc->unpin_work;
e7d841ca
CW		 7016
7017 /* Ensure we don't miss a work->pending update ... */
7018 smp_rmb();
7019
7020 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7021 spin_unlock_irqrestore(&dev->event_lock, flags);
7022 return;
7023 }
7024
e7d841ca
CW		 7025 /* and that the unpin work is consistent wrt ->pending. */
7026 smp_rmb();
7027
6b95a207 7028 intel_crtc->unpin_work = NULL;
6b95a207 7029
45a066eb
RC		 7030 if (work->event)
7031 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7032
0af7e4df
MK		 7033 drm_vblank_put(dev, intel_crtc->pipe);
7034
6b95a207
KH		 7035 spin_unlock_irqrestore(&dev->event_lock, flags);
7036
2c10d571 7037 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7038
7039 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7040
7041 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7042}
7043
1afe3e9d
JB		 7044void intel_finish_page_flip(struct drm_device *dev, int pipe)
7045{
7046 drm_i915_private_t *dev_priv = dev->dev_private;
7047 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7048
49b14a5c 7049 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7050}
7051
7052void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7053{
7054 drm_i915_private_t *dev_priv = dev->dev_private;
7055 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7056
49b14a5c 7057 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7058}
7059
6b95a207
KH		 7060void intel_prepare_page_flip(struct drm_device *dev, int plane)
7061{
7062 drm_i915_private_t *dev_priv = dev->dev_private;
7063 struct intel_crtc *intel_crtc =
7064 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7065 unsigned long flags;
7066
e7d841ca
CW		 7067 /* NB: An MMIO update of the plane base pointer will also
7068 * generate a page-flip completion irq, i.e. every modeset
7069 * is also accompanied by a spurious intel_prepare_page_flip().
7070 */
6b95a207 7071 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7072 if (intel_crtc->unpin_work)
7073 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7074 spin_unlock_irqrestore(&dev->event_lock, flags);
7075}
7076
e7d841ca
CW		 7077inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7078{
7079 /* Ensure that the work item is consistent when activating it ... */
7080 smp_wmb();
7081 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7082 /* and that it is marked active as soon as the irq could fire. */
7083 smp_wmb();
7084}
7085
8c9f3aaf
JB		 7086static int intel_gen2_queue_flip(struct drm_device *dev,
7087 struct drm_crtc *crtc,
7088 struct drm_framebuffer *fb,
7089 struct drm_i915_gem_object *obj)
7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7093 u32 flip_mask;
6d90c952 7094 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7095 int ret;
7096
6d90c952 7097 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7098 if (ret)
83d4092b 7099 goto err;
8c9f3aaf 7100
6d90c952 7101 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7102 if (ret)
83d4092b 7103 goto err_unpin;
8c9f3aaf
JB		 7104
7105 /* Can't queue multiple flips, so wait for the previous
7106 * one to finish before executing the next.
7107 */
7108 if (intel_crtc->plane)
7109 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7110 else
7111 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7112 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7113 intel_ring_emit(ring, MI_NOOP);
7114 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7115 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7116 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7117 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7118 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7119
7120 intel_mark_page_flip_active(intel_crtc);
6d90c952 7121 intel_ring_advance(ring);
83d4092b
CW		 7122 return 0;
7123
7124err_unpin:
7125 intel_unpin_fb_obj(obj);
7126err:
8c9f3aaf
JB		 7127 return ret;
7128}
7129
7130static int intel_gen3_queue_flip(struct drm_device *dev,
7131 struct drm_crtc *crtc,
7132 struct drm_framebuffer *fb,
7133 struct drm_i915_gem_object *obj)
7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7137 u32 flip_mask;
6d90c952 7138 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7139 int ret;
7140
6d90c952 7141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7142 if (ret)
83d4092b 7143 goto err;
8c9f3aaf 7144
6d90c952 7145 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7146 if (ret)
83d4092b 7147 goto err_unpin;
8c9f3aaf
JB		 7148
7149 if (intel_crtc->plane)
7150 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7151 else
7152 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7153 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7154 intel_ring_emit(ring, MI_NOOP);
7155 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7156 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7157 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7158 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7159 intel_ring_emit(ring, MI_NOOP);
7160
e7d841ca 7161 intel_mark_page_flip_active(intel_crtc);
6d90c952 7162 intel_ring_advance(ring);
83d4092b
CW		 7163 return 0;
7164
7165err_unpin:
7166 intel_unpin_fb_obj(obj);
7167err:
8c9f3aaf
JB		 7168 return ret;
7169}
7170
7171static int intel_gen4_queue_flip(struct drm_device *dev,
7172 struct drm_crtc *crtc,
7173 struct drm_framebuffer *fb,
7174 struct drm_i915_gem_object *obj)
7175{
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178 uint32_t pf, pipesrc;
6d90c952 7179 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7180 int ret;
7181
6d90c952 7182 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7183 if (ret)
83d4092b 7184 goto err;
8c9f3aaf 7185
6d90c952 7186 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7187 if (ret)
83d4092b 7188 goto err_unpin;
8c9f3aaf
JB		 7189
7190 /* i965+ uses the linear or tiled offsets from the
7191 * Display Registers (which do not change across a page-flip)
7192 * so we need only reprogram the base address.
7193 */
6d90c952
DV		 7194 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7195 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7196 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7197 intel_ring_emit(ring,
7198 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7199 obj->tiling_mode);
8c9f3aaf
JB		 7200
7201 /* XXX Enabling the panel-fitter across page-flip is so far
7202 * untested on non-native modes, so ignore it for now.
7203 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7204 */
7205 pf = 0;
7206 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7207 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7208
7209 intel_mark_page_flip_active(intel_crtc);
6d90c952 7210 intel_ring_advance(ring);
83d4092b
CW		 7211 return 0;
7212
7213err_unpin:
7214 intel_unpin_fb_obj(obj);
7215err:
8c9f3aaf
JB		 7216 return ret;
7217}
7218
7219static int intel_gen6_queue_flip(struct drm_device *dev,
7220 struct drm_crtc *crtc,
7221 struct drm_framebuffer *fb,
7222 struct drm_i915_gem_object *obj)
7223{
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7226 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7227 uint32_t pf, pipesrc;
7228 int ret;
7229
6d90c952 7230 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7231 if (ret)
83d4092b 7232 goto err;
8c9f3aaf 7233
6d90c952 7234 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7235 if (ret)
83d4092b 7236 goto err_unpin;
8c9f3aaf 7237
6d90c952
DV		 7238 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7239 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7240 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7241 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7242
dc257cf1
DV		 7243 /* Contrary to the suggestions in the documentation,
7244 * "Enable Panel Fitter" does not seem to be required when page
7245 * flipping with a non-native mode, and worse causes a normal
7246 * modeset to fail.
7247 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7248 */
7249 pf = 0;
8c9f3aaf 7250 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7251 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7252
7253 intel_mark_page_flip_active(intel_crtc);
6d90c952 7254 intel_ring_advance(ring);
83d4092b
CW		 7255 return 0;
7256
7257err_unpin:
7258 intel_unpin_fb_obj(obj);
7259err:
8c9f3aaf
JB		 7260 return ret;
7261}
7262
7c9017e5
JB		 7263/*
7264 * On gen7 we currently use the blit ring because (in early silicon at least)
7265 * the render ring doesn't give us interrpts for page flip completion, which
7266 * means clients will hang after the first flip is queued. Fortunately the
7267 * blit ring generates interrupts properly, so use it instead.
7268 */
7269static int intel_gen7_queue_flip(struct drm_device *dev,
7270 struct drm_crtc *crtc,
7271 struct drm_framebuffer *fb,
7272 struct drm_i915_gem_object *obj)
7273{
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7276 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7277 uint32_t plane_bit = 0;
7c9017e5
JB		 7278 int ret;
7279
7280 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7281 if (ret)
83d4092b 7282 goto err;
7c9017e5 7283
cb05d8de
DV		 7284 switch(intel_crtc->plane) {
7285 case PLANE_A:
7286 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7287 break;
7288 case PLANE_B:
7289 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7290 break;
7291 case PLANE_C:
7292 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7293 break;
7294 default:
7295 WARN_ONCE(1, "unknown plane in flip command\n");
7296 ret = -ENODEV;
ab3951eb 7297 goto err_unpin;
cb05d8de
DV		 7298 }
7299
7c9017e5
JB		 7300 ret = intel_ring_begin(ring, 4);
7301 if (ret)
83d4092b 7302 goto err_unpin;
7c9017e5 7303
cb05d8de 7304 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7305 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7306 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7307 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7308
7309 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7310 intel_ring_advance(ring);
83d4092b
CW		 7311 return 0;
7312
7313err_unpin:
7314 intel_unpin_fb_obj(obj);
7315err:
7c9017e5
JB		 7316 return ret;
7317}
7318
8c9f3aaf
JB		 7319static int intel_default_queue_flip(struct drm_device *dev,
7320 struct drm_crtc *crtc,
7321 struct drm_framebuffer *fb,
7322 struct drm_i915_gem_object *obj)
7323{
7324 return -ENODEV;
7325}
7326
6b95a207
KH		 7327static int intel_crtc_page_flip(struct drm_crtc *crtc,
7328 struct drm_framebuffer *fb,
7329 struct drm_pending_vblank_event *event)
7330{
7331 struct drm_device *dev = crtc->dev;
7332 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7333 struct drm_framebuffer *old_fb = crtc->fb;
7334 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7336 struct intel_unpin_work *work;
8c9f3aaf 7337 unsigned long flags;
52e68630 7338 int ret;
6b95a207 7339
e6a595d2
VS		 7340 /* Can't change pixel format via MI display flips. */
7341 if (fb->pixel_format != crtc->fb->pixel_format)
7342 return -EINVAL;
7343
7344 /*
7345 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7346 * Note that pitch changes could also affect these register.
7347 */
7348 if (INTEL_INFO(dev)->gen > 3 &&
7349 (fb->offsets[0] != crtc->fb->offsets[0] ||
7350 fb->pitches[0] != crtc->fb->pitches[0]))
7351 return -EINVAL;
7352
6b95a207
KH		 7353 work = kzalloc(sizeof *work, GFP_KERNEL);
7354 if (work == NULL)
7355 return -ENOMEM;
7356
6b95a207 7357 work->event = event;
b4a98e57 7358 work->crtc = crtc;
4a35f83b 7359 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7360 INIT_WORK(&work->work, intel_unpin_work_fn);
7361
7317c75e
JB		 7362 ret = drm_vblank_get(dev, intel_crtc->pipe);
7363 if (ret)
7364 goto free_work;
7365
6b95a207
KH		 7366 /* We borrow the event spin lock for protecting unpin_work */
7367 spin_lock_irqsave(&dev->event_lock, flags);
7368 if (intel_crtc->unpin_work) {
7369 spin_unlock_irqrestore(&dev->event_lock, flags);
7370 kfree(work);
7317c75e 7371 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7372
7373 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7374 return -EBUSY;
7375 }
7376 intel_crtc->unpin_work = work;
7377 spin_unlock_irqrestore(&dev->event_lock, flags);
7378
b4a98e57
CW		 7379 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7380 flush_workqueue(dev_priv->wq);
7381
79158103
CW		 7382 ret = i915_mutex_lock_interruptible(dev);
7383 if (ret)
7384 goto cleanup;
6b95a207 7385
75dfca80 7386 /* Reference the objects for the scheduled work. */
05394f39
CW		 7387 drm_gem_object_reference(&work->old_fb_obj->base);
7388 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7389
7390 crtc->fb = fb;
96b099fd 7391
e1f99ce6 7392 work->pending_flip_obj = obj;
e1f99ce6 7393
4e5359cd
SF		 7394 work->enable_stall_check = true;
7395
b4a98e57 7396 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7397 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7398
8c9f3aaf
JB		 7399 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7400 if (ret)
7401 goto cleanup_pending;
6b95a207 7402
7782de3b 7403 intel_disable_fbc(dev);
f047e395 7404 intel_mark_fb_busy(obj);
6b95a207
KH		 7405 mutex_unlock(&dev->struct_mutex);
7406
e5510fac
JB		 7407 trace_i915_flip_request(intel_crtc->plane, obj);
7408
6b95a207 7409 return 0;
96b099fd 7410
8c9f3aaf 7411cleanup_pending:
b4a98e57 7412 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7413 crtc->fb = old_fb;
05394f39
CW		 7414 drm_gem_object_unreference(&work->old_fb_obj->base);
7415 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7416 mutex_unlock(&dev->struct_mutex);
7417
79158103 7418cleanup:
96b099fd
CW		 7419 spin_lock_irqsave(&dev->event_lock, flags);
7420 intel_crtc->unpin_work = NULL;
7421 spin_unlock_irqrestore(&dev->event_lock, flags);
7422
7317c75e
JB		 7423 drm_vblank_put(dev, intel_crtc->pipe);
7424free_work:
96b099fd
CW		 7425 kfree(work);
7426
7427 return ret;
6b95a207
KH		 7428}
7429
f6e5b160 7430static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7431 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7432 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7433};
7434
6ed0f796 7435bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7436{
6ed0f796
DV		 7437 struct intel_encoder *other_encoder;
7438 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7439
6ed0f796
DV		 7440 if (WARN_ON(!crtc))
7441 return false;
7442
7443 list_for_each_entry(other_encoder,
7444 &crtc->dev->mode_config.encoder_list,
7445 base.head) {
7446
7447 if (&other_encoder->new_crtc->base != crtc ||
7448 encoder == other_encoder)
7449 continue;
7450 else
7451 return true;
f47166d2
CW		 7452 }
7453
6ed0f796
DV		 7454 return false;
7455}
47f1c6c9 7456
50f56119
DV		 7457static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7458 struct drm_crtc *crtc)
7459{
7460 struct drm_device *dev;
7461 struct drm_crtc *tmp;
7462 int crtc_mask = 1;
47f1c6c9 7463
50f56119 7464 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7465
50f56119 7466 dev = crtc->dev;
47f1c6c9 7467
50f56119
DV		 7468 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7469 if (tmp == crtc)
7470 break;
7471 crtc_mask <<= 1;
7472 }
47f1c6c9 7473
50f56119
DV		 7474 if (encoder->possible_crtcs & crtc_mask)
7475 return true;
7476 return false;
47f1c6c9 7477}
79e53945 7478
9a935856
DV		 7479/**
7480 * intel_modeset_update_staged_output_state
7481 *
7482 * Updates the staged output configuration state, e.g. after we've read out the
7483 * current hw state.
7484 */
7485static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7486{
9a935856
DV		 7487 struct intel_encoder *encoder;
7488 struct intel_connector *connector;
f6e5b160 7489
9a935856
DV		 7490 list_for_each_entry(connector, &dev->mode_config.connector_list,
7491 base.head) {
7492 connector->new_encoder =
7493 to_intel_encoder(connector->base.encoder);
7494 }
f6e5b160 7495
9a935856
DV		 7496 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7497 base.head) {
7498 encoder->new_crtc =
7499 to_intel_crtc(encoder->base.crtc);
7500 }
f6e5b160
CW		 7501}
7502
9a935856
DV		 7503/**
7504 * intel_modeset_commit_output_state
7505 *
7506 * This function copies the stage display pipe configuration to the real one.
7507 */
7508static void intel_modeset_commit_output_state(struct drm_device *dev)
7509{
7510 struct intel_encoder *encoder;
7511 struct intel_connector *connector;
f6e5b160 7512
9a935856
DV		 7513 list_for_each_entry(connector, &dev->mode_config.connector_list,
7514 base.head) {
7515 connector->base.encoder = &connector->new_encoder->base;
7516 }
f6e5b160 7517
9a935856
DV		 7518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7519 base.head) {
7520 encoder->base.crtc = &encoder->new_crtc->base;
7521 }
7522}
7523
4e53c2e0
DV		 7524static int
7525pipe_config_set_bpp(struct drm_crtc *crtc,
7526 struct drm_framebuffer *fb,
7527 struct intel_crtc_config *pipe_config)
7528{
7529 struct drm_device *dev = crtc->dev;
7530 struct drm_connector *connector;
7531 int bpp;
7532
d42264b1
DV		 7533 switch (fb->pixel_format) {
7534 case DRM_FORMAT_C8:
4e53c2e0
DV		 7535 bpp = 8*3; /* since we go through a colormap */
7536 break;
d42264b1
DV		 7537 case DRM_FORMAT_XRGB1555:
7538 case DRM_FORMAT_ARGB1555:
7539 /* checked in intel_framebuffer_init already */
7540 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7541 return -EINVAL;
7542 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7543 bpp = 6*3; /* min is 18bpp */
7544 break;
d42264b1
DV		 7545 case DRM_FORMAT_XBGR8888:
7546 case DRM_FORMAT_ABGR8888:
7547 /* checked in intel_framebuffer_init already */
7548 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7549 return -EINVAL;
7550 case DRM_FORMAT_XRGB8888:
7551 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7552 bpp = 8*3;
7553 break;
d42264b1
DV		 7554 case DRM_FORMAT_XRGB2101010:
7555 case DRM_FORMAT_ARGB2101010:
7556 case DRM_FORMAT_XBGR2101010:
7557 case DRM_FORMAT_ABGR2101010:
7558 /* checked in intel_framebuffer_init already */
7559 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7560 return -EINVAL;
4e53c2e0
DV		 7561 bpp = 10*3;
7562 break;
baba133a 7563 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7564 default:
7565 DRM_DEBUG_KMS("unsupported depth\n");
7566 return -EINVAL;
7567 }
7568
4e53c2e0
DV		 7569 pipe_config->pipe_bpp = bpp;
7570
7571 /* Clamp display bpp to EDID value */
7572 list_for_each_entry(connector, &dev->mode_config.connector_list,
7573 head) {
7574 if (connector->encoder && connector->encoder->crtc != crtc)
7575 continue;
7576
7577 /* Don't use an invalid EDID bpc value */
7578 if (connector->display_info.bpc &&
7579 connector->display_info.bpc * 3 < bpp) {
7580 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7581 bpp, connector->display_info.bpc*3);
7582 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7583 }
7584 }
7585
7586 return bpp;
7587}
7588
b8cecdf5
DV		 7589static struct intel_crtc_config *
7590intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7591 struct drm_framebuffer *fb,
b8cecdf5 7592 struct drm_display_mode *mode)
ee7b9f93 7593{
7758a113 7594 struct drm_device *dev = crtc->dev;
7758a113
DV		 7595 struct drm_encoder_helper_funcs *encoder_funcs;
7596 struct intel_encoder *encoder;
b8cecdf5 7597 struct intel_crtc_config *pipe_config;
4e53c2e0 7598 int plane_bpp;
ee7b9f93 7599
b8cecdf5
DV		 7600 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7601 if (!pipe_config)
7758a113
DV		 7602 return ERR_PTR(-ENOMEM);
7603
b8cecdf5
DV		 7604 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7605 drm_mode_copy(&pipe_config->requested_mode, mode);
7606
4e53c2e0
DV		 7607 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7608 if (plane_bpp < 0)
7609 goto fail;
7610
7758a113
DV		 7611 /* Pass our mode to the connectors and the CRTC to give them a chance to
7612 * adjust it according to limitations or connector properties, and also
7613 * a chance to reject the mode entirely.
47f1c6c9 7614 */
7758a113
DV		 7615 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7616 base.head) {
47f1c6c9 7617
7758a113
DV		 7618 if (&encoder->new_crtc->base != crtc)
7619 continue;
7ae89233
DV		 7620
7621 if (encoder->compute_config) {
7622 if (!(encoder->compute_config(encoder, pipe_config))) {
7623 DRM_DEBUG_KMS("Encoder config failure\n");
7624 goto fail;
7625 }
7626
7627 continue;
7628 }
7629
7758a113 7630 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7631 if (!(encoder_funcs->mode_fixup(&encoder->base,
7632 &pipe_config->requested_mode,
7633 &pipe_config->adjusted_mode))) {
7758a113
DV		 7634 DRM_DEBUG_KMS("Encoder fixup failed\n");
7635 goto fail;
7636 }
ee7b9f93 7637 }
47f1c6c9 7638
b8cecdf5 7639 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7640 DRM_DEBUG_KMS("CRTC fixup failed\n");
7641 goto fail;
ee7b9f93 7642 }
7758a113 7643 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7644
4e53c2e0
DV		 7645 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7646 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7647 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7648
b8cecdf5 7649 return pipe_config;
7758a113 7650fail:
b8cecdf5 7651 kfree(pipe_config);
7758a113 7652 return ERR_PTR(-EINVAL);
ee7b9f93 7653}
47f1c6c9 7654
e2e1ed41
DV		 7655/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7656 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7657static void
7658intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7659 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7660{
7661 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7662 struct drm_device *dev = crtc->dev;
7663 struct intel_encoder *encoder;
7664 struct intel_connector *connector;
7665 struct drm_crtc *tmp_crtc;
79e53945 7666
e2e1ed41 7667 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7668
e2e1ed41
DV		 7669 /* Check which crtcs have changed outputs connected to them, these need
7670 * to be part of the prepare_pipes mask. We don't (yet) support global
7671 * modeset across multiple crtcs, so modeset_pipes will only have one
7672 * bit set at most. */
7673 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674 base.head) {
7675 if (connector->base.encoder == &connector->new_encoder->base)
7676 continue;
79e53945 7677
e2e1ed41
DV		 7678 if (connector->base.encoder) {
7679 tmp_crtc = connector->base.encoder->crtc;
7680
7681 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7682 }
7683
7684 if (connector->new_encoder)
7685 *prepare_pipes |=
7686 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7687 }
7688
e2e1ed41
DV		 7689 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7690 base.head) {
7691 if (encoder->base.crtc == &encoder->new_crtc->base)
7692 continue;
7693
7694 if (encoder->base.crtc) {
7695 tmp_crtc = encoder->base.crtc;
7696
7697 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7698 }
7699
7700 if (encoder->new_crtc)
7701 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7702 }
7703
e2e1ed41
DV		 7704 /* Check for any pipes that will be fully disabled ... */
7705 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7706 base.head) {
7707 bool used = false;
22fd0fab 7708
e2e1ed41
DV		 7709 /* Don't try to disable disabled crtcs. */
7710 if (!intel_crtc->base.enabled)
7711 continue;
7e7d76c3 7712
e2e1ed41
DV		 7713 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7714 base.head) {
7715 if (encoder->new_crtc == intel_crtc)
7716 used = true;
7717 }
7718
7719 if (!used)
7720 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7721 }
7722
e2e1ed41
DV		 7723
7724 /* set_mode is also used to update properties on life display pipes. */
7725 intel_crtc = to_intel_crtc(crtc);
7726 if (crtc->enabled)
7727 *prepare_pipes |= 1 << intel_crtc->pipe;
7728
b6c5164d
DV		 7729 /*
7730 * For simplicity do a full modeset on any pipe where the output routing
7731 * changed. We could be more clever, but that would require us to be
7732 * more careful with calling the relevant encoder->mode_set functions.
7733 */
e2e1ed41
DV		 7734 if (*prepare_pipes)
7735 *modeset_pipes = *prepare_pipes;
7736
7737 /* ... and mask these out. */
7738 *modeset_pipes &= ~(*disable_pipes);
7739 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7740
7741 /*
7742 * HACK: We don't (yet) fully support global modesets. intel_set_config
7743 * obies this rule, but the modeset restore mode of
7744 * intel_modeset_setup_hw_state does not.
7745 */
7746 *modeset_pipes &= 1 << intel_crtc->pipe;
7747 *prepare_pipes &= 1 << intel_crtc->pipe;
47f1c6c9 7748}
79e53945 7749
ea9d758d 7750static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7751{
ea9d758d 7752 struct drm_encoder *encoder;
f6e5b160 7753 struct drm_device *dev = crtc->dev;
f6e5b160 7754
ea9d758d
DV		 7755 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7756 if (encoder->crtc == crtc)
7757 return true;
7758
7759 return false;
7760}
7761
7762static void
7763intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7764{
7765 struct intel_encoder *intel_encoder;
7766 struct intel_crtc *intel_crtc;
7767 struct drm_connector *connector;
7768
7769 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7770 base.head) {
7771 if (!intel_encoder->base.crtc)
7772 continue;
7773
7774 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7775
7776 if (prepare_pipes & (1 << intel_crtc->pipe))
7777 intel_encoder->connectors_active = false;
7778 }
7779
7780 intel_modeset_commit_output_state(dev);
7781
7782 /* Update computed state. */
7783 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7784 base.head) {
7785 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7786 }
7787
7788 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7789 if (!connector->encoder || !connector->encoder->crtc)
7790 continue;
7791
7792 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7793
7794 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7795 struct drm_property *dpms_property =
7796 dev->mode_config.dpms_property;
7797
ea9d758d 7798 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7799 drm_object_property_set_value(&connector->base,
68d34720
DV		 7800 dpms_property,
7801 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7802
7803 intel_encoder = to_intel_encoder(connector->encoder);
7804 intel_encoder->connectors_active = true;
7805 }
7806 }
7807
7808}
7809
25c5b266
DV		 7810#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7811 list_for_each_entry((intel_crtc), \
7812 &(dev)->mode_config.crtc_list, \
7813 base.head) \
7814 if (mask & (1 <<(intel_crtc)->pipe)) \
7815
0e8ffe1b
DV		 7816static bool
7817intel_pipe_config_compare(struct intel_crtc_config *current_config,
7818 struct intel_crtc_config *pipe_config)
7819{
88adfff1
DV		 7820 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7821 DRM_ERROR("mismatch in has_pch_encoder "
7822 "(expected %i, found %i)\n",
7823 current_config->has_pch_encoder,
7824 pipe_config->has_pch_encoder);
7825 return false;
7826 }
7827
0e8ffe1b
DV		 7828 return true;
7829}
7830
b980514c 7831void
8af6cf88
DV		 7832intel_modeset_check_state(struct drm_device *dev)
7833{
0e8ffe1b 7834 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7835 struct intel_crtc *crtc;
7836 struct intel_encoder *encoder;
7837 struct intel_connector *connector;
0e8ffe1b 7838 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7839
7840 list_for_each_entry(connector, &dev->mode_config.connector_list,
7841 base.head) {
7842 /* This also checks the encoder/connector hw state with the
7843 * ->get_hw_state callbacks. */
7844 intel_connector_check_state(connector);
7845
7846 WARN(&connector->new_encoder->base != connector->base.encoder,
7847 "connector's staged encoder doesn't match current encoder\n");
7848 }
7849
7850 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7851 base.head) {
7852 bool enabled = false;
7853 bool active = false;
7854 enum pipe pipe, tracked_pipe;
7855
7856 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7857 encoder->base.base.id,
7858 drm_get_encoder_name(&encoder->base));
7859
7860 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7861 "encoder's stage crtc doesn't match current crtc\n");
7862 WARN(encoder->connectors_active && !encoder->base.crtc,
7863 "encoder's active_connectors set, but no crtc\n");
7864
7865 list_for_each_entry(connector, &dev->mode_config.connector_list,
7866 base.head) {
7867 if (connector->base.encoder != &encoder->base)
7868 continue;
7869 enabled = true;
7870 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7871 active = true;
7872 }
7873 WARN(!!encoder->base.crtc != enabled,
7874 "encoder's enabled state mismatch "
7875 "(expected %i, found %i)\n",
7876 !!encoder->base.crtc, enabled);
7877 WARN(active && !encoder->base.crtc,
7878 "active encoder with no crtc\n");
7879
7880 WARN(encoder->connectors_active != active,
7881 "encoder's computed active state doesn't match tracked active state "
7882 "(expected %i, found %i)\n", active, encoder->connectors_active);
7883
7884 active = encoder->get_hw_state(encoder, &pipe);
7885 WARN(active != encoder->connectors_active,
7886 "encoder's hw state doesn't match sw tracking "
7887 "(expected %i, found %i)\n",
7888 encoder->connectors_active, active);
7889
7890 if (!encoder->base.crtc)
7891 continue;
7892
7893 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7894 WARN(active && pipe != tracked_pipe,
7895 "active encoder's pipe doesn't match"
7896 "(expected %i, found %i)\n",
7897 tracked_pipe, pipe);
7898
7899 }
7900
7901 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7902 base.head) {
7903 bool enabled = false;
7904 bool active = false;
7905
7906 DRM_DEBUG_KMS("[CRTC:%d]\n",
7907 crtc->base.base.id);
7908
7909 WARN(crtc->active && !crtc->base.enabled,
7910 "active crtc, but not enabled in sw tracking\n");
7911
7912 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7913 base.head) {
7914 if (encoder->base.crtc != &crtc->base)
7915 continue;
7916 enabled = true;
7917 if (encoder->connectors_active)
7918 active = true;
7919 }
7920 WARN(active != crtc->active,
7921 "crtc's computed active state doesn't match tracked active state "
7922 "(expected %i, found %i)\n", active, crtc->active);
7923 WARN(enabled != crtc->base.enabled,
7924 "crtc's computed enabled state doesn't match tracked enabled state "
7925 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7926
88adfff1 7927 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7928 active = dev_priv->display.get_pipe_config(crtc,
7929 &pipe_config);
7930 WARN(crtc->active != active,
7931 "crtc active state doesn't match with hw state "
7932 "(expected %i, found %i)\n", crtc->active, active);
7933
7934 WARN(active &&
7935 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7936 "pipe state doesn't match!\n");
8af6cf88
DV		 7937 }
7938}
7939
f30da187
DV		 7940static int __intel_set_mode(struct drm_crtc *crtc,
7941 struct drm_display_mode *mode,
7942 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7943{
7944 struct drm_device *dev = crtc->dev;
dbf2b54e 7945 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7946 struct drm_display_mode *saved_mode, *saved_hwmode;
7947 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7948 struct intel_crtc *intel_crtc;
7949 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7950 int ret = 0;
a6778b3c 7951
3ac18232 7952 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7953 if (!saved_mode)
7954 return -ENOMEM;
3ac18232 7955 saved_hwmode = saved_mode + 1;
a6778b3c 7956
e2e1ed41 7957 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7958 &prepare_pipes, &disable_pipes);
7959
3ac18232
TG		 7960 *saved_hwmode = crtc->hwmode;
7961 *saved_mode = crtc->mode;
a6778b3c 7962
25c5b266
DV		 7963 /* Hack: Because we don't (yet) support global modeset on multiple
7964 * crtcs, we don't keep track of the new mode for more than one crtc.
7965 * Hence simply check whether any bit is set in modeset_pipes in all the
7966 * pieces of code that are not yet converted to deal with mutliple crtcs
7967 * changing their mode at the same time. */
25c5b266 7968 if (modeset_pipes) {
4e53c2e0 7969 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7970 if (IS_ERR(pipe_config)) {
7971 ret = PTR_ERR(pipe_config);
7972 pipe_config = NULL;
7973
3ac18232 7974 goto out;
25c5b266 7975 }
25c5b266 7976 }
a6778b3c 7977
460da916
DV		 7978 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7979 modeset_pipes, prepare_pipes, disable_pipes);
7980
7981 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7982 intel_crtc_disable(&intel_crtc->base);
7983
ea9d758d
DV		 7984 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7985 if (intel_crtc->base.enabled)
7986 dev_priv->display.crtc_disable(&intel_crtc->base);
7987 }
a6778b3c 7988
6c4c86f5
DV		 7989 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7990 * to set it here already despite that we pass it down the callchain.
f6e5b160 7991 */
b8cecdf5 7992 if (modeset_pipes) {
25c5b266 7993 crtc->mode = *mode;
b8cecdf5
DV		 7994 /* mode_set/enable/disable functions rely on a correct pipe
7995 * config. */
7996 to_intel_crtc(crtc)->config = *pipe_config;
7997 }
7758a113 7998
ea9d758d
DV		 7999 /* Only after disabling all output pipelines that will be changed can we
8000 * update the the output configuration. */
8001 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8002
47fab737
DV		 8003 if (dev_priv->display.modeset_global_resources)
8004 dev_priv->display.modeset_global_resources(dev);
8005
a6778b3c
DV		 8006 /* Set up the DPLL and any encoders state that needs to adjust or depend
8007 * on the DPLL.
f6e5b160 8008 */
25c5b266 8009 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8010 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8011 x, y, fb);
8012 if (ret)
8013 goto done;
a6778b3c
DV		 8014 }
8015
8016 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8017 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8018 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8019
25c5b266
DV		 8020 if (modeset_pipes) {
8021 /* Store real post-adjustment hardware mode. */
b8cecdf5 8022 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8023
25c5b266
DV		 8024 /* Calculate and store various constants which
8025 * are later needed by vblank and swap-completion
8026 * timestamping. They are derived from true hwmode.
8027 */
8028 drm_calc_timestamping_constants(crtc);
8029 }
a6778b3c
DV		 8030
8031 /* FIXME: add subpixel order */
8032done:
c0c36b94 8033 if (ret && crtc->enabled) {
3ac18232
TG		 8034 crtc->hwmode = *saved_hwmode;
8035 crtc->mode = *saved_mode;
a6778b3c
DV		 8036 }
8037
3ac18232 8038out:
b8cecdf5 8039 kfree(pipe_config);
3ac18232 8040 kfree(saved_mode);
a6778b3c 8041 return ret;
f6e5b160
CW		 8042}
8043
f30da187
DV		 8044int intel_set_mode(struct drm_crtc *crtc,
8045 struct drm_display_mode *mode,
8046 int x, int y, struct drm_framebuffer *fb)
8047{
8048 int ret;
8049
8050 ret = __intel_set_mode(crtc, mode, x, y, fb);
8051
8052 if (ret == 0)
8053 intel_modeset_check_state(crtc->dev);
8054
8055 return ret;
8056}
8057
c0c36b94
CW		 8058void intel_crtc_restore_mode(struct drm_crtc *crtc)
8059{
8060 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8061}
8062
25c5b266
DV		 8063#undef for_each_intel_crtc_masked
8064
d9e55608
DV		 8065static void intel_set_config_free(struct intel_set_config *config)
8066{
8067 if (!config)
8068 return;
8069
1aa4b628
DV		 8070 kfree(config->save_connector_encoders);
8071 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8072 kfree(config);
8073}
8074
85f9eb71
DV		 8075static int intel_set_config_save_state(struct drm_device *dev,
8076 struct intel_set_config *config)
8077{
85f9eb71
DV		 8078 struct drm_encoder *encoder;
8079 struct drm_connector *connector;
8080 int count;
8081
1aa4b628
DV		 8082 config->save_encoder_crtcs =
8083 kcalloc(dev->mode_config.num_encoder,
8084 sizeof(struct drm_crtc *), GFP_KERNEL);
8085 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8086 return -ENOMEM;
8087
1aa4b628
DV		 8088 config->save_connector_encoders =
8089 kcalloc(dev->mode_config.num_connector,
8090 sizeof(struct drm_encoder *), GFP_KERNEL);
8091 if (!config->save_connector_encoders)
85f9eb71
DV		 8092 return -ENOMEM;
8093
8094 /* Copy data. Note that driver private data is not affected.
8095 * Should anything bad happen only the expected state is
8096 * restored, not the drivers personal bookkeeping.
8097 */
85f9eb71
DV		 8098 count = 0;
8099 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8100 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8101 }
8102
8103 count = 0;
8104 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8105 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8106 }
8107
8108 return 0;
8109}
8110
8111static void intel_set_config_restore_state(struct drm_device *dev,
8112 struct intel_set_config *config)
8113{
9a935856
DV		 8114 struct intel_encoder *encoder;
8115 struct intel_connector *connector;
85f9eb71
DV		 8116 int count;
8117
85f9eb71 8118 count = 0;
9a935856
DV		 8119 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8120 encoder->new_crtc =
8121 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8122 }
8123
8124 count = 0;
9a935856
DV		 8125 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8126 connector->new_encoder =
8127 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8128 }
8129}
8130
5e2b584e
DV		 8131static void
8132intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8133 struct intel_set_config *config)
8134{
8135
8136 /* We should be able to check here if the fb has the same properties
8137 * and then just flip_or_move it */
8138 if (set->crtc->fb != set->fb) {
8139 /* If we have no fb then treat it as a full mode set */
8140 if (set->crtc->fb == NULL) {
8141 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8142 config->mode_changed = true;
8143 } else if (set->fb == NULL) {
8144 config->mode_changed = true;
72f4901e
DV		 8145 } else if (set->fb->pixel_format !=
8146 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8147 config->mode_changed = true;
8148 } else
8149 config->fb_changed = true;
8150 }
8151
835c5873 8152 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8153 config->fb_changed = true;
8154
8155 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8156 DRM_DEBUG_KMS("modes are different, full mode set\n");
8157 drm_mode_debug_printmodeline(&set->crtc->mode);
8158 drm_mode_debug_printmodeline(set->mode);
8159 config->mode_changed = true;
8160 }
8161}
8162
2e431051 8163static int
9a935856
DV		 8164intel_modeset_stage_output_state(struct drm_device *dev,
8165 struct drm_mode_set *set,
8166 struct intel_set_config *config)
50f56119 8167{
85f9eb71 8168 struct drm_crtc *new_crtc;
9a935856
DV		 8169 struct intel_connector *connector;
8170 struct intel_encoder *encoder;
2e431051 8171 int count, ro;
50f56119 8172
9abdda74 8173 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8174 * of connectors. For paranoia, double-check this. */
8175 WARN_ON(!set->fb && (set->num_connectors != 0));
8176 WARN_ON(set->fb && (set->num_connectors == 0));
8177
50f56119 8178 count = 0;
9a935856
DV		 8179 list_for_each_entry(connector, &dev->mode_config.connector_list,
8180 base.head) {
8181 /* Otherwise traverse passed in connector list and get encoders
8182 * for them. */
50f56119 8183 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8184 if (set->connectors[ro] == &connector->base) {
8185 connector->new_encoder = connector->encoder;
50f56119
DV		 8186 break;
8187 }
8188 }
8189
9a935856
DV		 8190 /* If we disable the crtc, disable all its connectors. Also, if
8191 * the connector is on the changing crtc but not on the new
8192 * connector list, disable it. */
8193 if ((!set->fb || ro == set->num_connectors) &&
8194 connector->base.encoder &&
8195 connector->base.encoder->crtc == set->crtc) {
8196 connector->new_encoder = NULL;
8197
8198 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8199 connector->base.base.id,
8200 drm_get_connector_name(&connector->base));
8201 }
8202
8203
8204 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8205 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8206 config->mode_changed = true;
50f56119
DV		 8207 }
8208 }
9a935856 8209 /* connector->new_encoder is now updated for all connectors. */
50f56119 8210
9a935856 8211 /* Update crtc of enabled connectors. */
50f56119 8212 count = 0;
9a935856
DV		 8213 list_for_each_entry(connector, &dev->mode_config.connector_list,
8214 base.head) {
8215 if (!connector->new_encoder)
50f56119
DV		 8216 continue;
8217
9a935856 8218 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8219
8220 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8221 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8222 new_crtc = set->crtc;
8223 }
8224
8225 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8226 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8227 new_crtc)) {
5e2b584e 8228 return -EINVAL;
50f56119 8229 }
9a935856
DV		 8230 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8231
8232 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8233 connector->base.base.id,
8234 drm_get_connector_name(&connector->base),
8235 new_crtc->base.id);
8236 }
8237
8238 /* Check for any encoders that needs to be disabled. */
8239 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8240 base.head) {
8241 list_for_each_entry(connector,
8242 &dev->mode_config.connector_list,
8243 base.head) {
8244 if (connector->new_encoder == encoder) {
8245 WARN_ON(!connector->new_encoder->new_crtc);
8246
8247 goto next_encoder;
8248 }
8249 }
8250 encoder->new_crtc = NULL;
8251next_encoder:
8252 /* Only now check for crtc changes so we don't miss encoders
8253 * that will be disabled. */
8254 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8255 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8256 config->mode_changed = true;
50f56119
DV		 8257 }
8258 }
9a935856 8259 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8260
2e431051
DV		 8261 return 0;
8262}
8263
8264static int intel_crtc_set_config(struct drm_mode_set *set)
8265{
8266 struct drm_device *dev;
2e431051
DV		 8267 struct drm_mode_set save_set;
8268 struct intel_set_config *config;
8269 int ret;
2e431051 8270
8d3e375e
DV		 8271 BUG_ON(!set);
8272 BUG_ON(!set->crtc);
8273 BUG_ON(!set->crtc->helper_private);
2e431051 8274
7e53f3a4
DV		 8275 /* Enforce sane interface api - has been abused by the fb helper. */
8276 BUG_ON(!set->mode && set->fb);
8277 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8278
2e431051
DV		 8279 if (set->fb) {
8280 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8281 set->crtc->base.id, set->fb->base.id,
8282 (int)set->num_connectors, set->x, set->y);
8283 } else {
8284 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8285 }
8286
8287 dev = set->crtc->dev;
8288
8289 ret = -ENOMEM;
8290 config = kzalloc(sizeof(*config), GFP_KERNEL);
8291 if (!config)
8292 goto out_config;
8293
8294 ret = intel_set_config_save_state(dev, config);
8295 if (ret)
8296 goto out_config;
8297
8298 save_set.crtc = set->crtc;
8299 save_set.mode = &set->crtc->mode;
8300 save_set.x = set->crtc->x;
8301 save_set.y = set->crtc->y;
8302 save_set.fb = set->crtc->fb;
8303
8304 /* Compute whether we need a full modeset, only an fb base update or no
8305 * change at all. In the future we might also check whether only the
8306 * mode changed, e.g. for LVDS where we only change the panel fitter in
8307 * such cases. */
8308 intel_set_config_compute_mode_changes(set, config);
8309
9a935856 8310 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8311 if (ret)
8312 goto fail;
8313
5e2b584e 8314 if (config->mode_changed) {
87f1faa6 8315 if (set->mode) {
50f56119
DV		 8316 DRM_DEBUG_KMS("attempting to set mode from"
8317 " userspace\n");
8318 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8319 }
8320
c0c36b94
CW		 8321 ret = intel_set_mode(set->crtc, set->mode,
8322 set->x, set->y, set->fb);
8323 if (ret) {
8324 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8325 set->crtc->base.id, ret);
87f1faa6
DV		 8326 goto fail;
8327 }
5e2b584e 8328 } else if (config->fb_changed) {
4878cae2
VS		 8329 intel_crtc_wait_for_pending_flips(set->crtc);
8330
4f660f49 8331 ret = intel_pipe_set_base(set->crtc,
94352cf9 8332 set->x, set->y, set->fb);
50f56119
DV		 8333 }
8334
d9e55608
DV		 8335 intel_set_config_free(config);
8336
50f56119
DV		 8337 return 0;
8338
8339fail:
85f9eb71 8340 intel_set_config_restore_state(dev, config);
50f56119
DV		 8341
8342 /* Try to restore the config */
5e2b584e 8343 if (config->mode_changed &&
c0c36b94
CW		 8344 intel_set_mode(save_set.crtc, save_set.mode,
8345 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8346 DRM_ERROR("failed to restore config after modeset failure\n");
8347
d9e55608
DV		 8348out_config:
8349 intel_set_config_free(config);
50f56119
DV		 8350 return ret;
8351}
f6e5b160
CW		 8352
8353static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8354 .cursor_set = intel_crtc_cursor_set,
8355 .cursor_move = intel_crtc_cursor_move,
8356 .gamma_set = intel_crtc_gamma_set,
50f56119 8357 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8358 .destroy = intel_crtc_destroy,
8359 .page_flip = intel_crtc_page_flip,
8360};
8361
79f689aa
PZ		 8362static void intel_cpu_pll_init(struct drm_device *dev)
8363{
affa9354 8364 if (HAS_DDI(dev))
79f689aa
PZ		 8365 intel_ddi_pll_init(dev);
8366}
8367
ee7b9f93
JB		 8368static void intel_pch_pll_init(struct drm_device *dev)
8369{
8370 drm_i915_private_t *dev_priv = dev->dev_private;
8371 int i;
8372
8373 if (dev_priv->num_pch_pll == 0) {
8374 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8375 return;
8376 }
8377
8378 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8379 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8380 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8381 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8382 }
8383}
8384
b358d0a6 8385static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8386{
22fd0fab 8387 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8388 struct intel_crtc *intel_crtc;
8389 int i;
8390
8391 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8392 if (intel_crtc == NULL)
8393 return;
8394
8395 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8396
8397 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8398 for (i = 0; i < 256; i++) {
8399 intel_crtc->lut_r[i] = i;
8400 intel_crtc->lut_g[i] = i;
8401 intel_crtc->lut_b[i] = i;
8402 }
8403
80824003
JB		 8404 /* Swap pipes & planes for FBC on pre-965 */
8405 intel_crtc->pipe = pipe;
8406 intel_crtc->plane = pipe;
a5c961d1 8407 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8408 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8409 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8410 intel_crtc->plane = !pipe;
80824003
JB		 8411 }
8412
22fd0fab
JB		 8413 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8414 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8415 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8416 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8417
79e53945 8418 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8419}
8420
08d7b3d1 8421int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8422 struct drm_file *file)
08d7b3d1 8423{
08d7b3d1 8424 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8425 struct drm_mode_object *drmmode_obj;
8426 struct intel_crtc *crtc;
08d7b3d1 8427
1cff8f6b
DV		 8428 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8429 return -ENODEV;
08d7b3d1 8430
c05422d5
DV		 8431 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8432 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8433
c05422d5 8434 if (!drmmode_obj) {
08d7b3d1
CW		 8435 DRM_ERROR("no such CRTC id\n");
8436 return -EINVAL;
8437 }
8438
c05422d5
DV		 8439 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8440 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8441
c05422d5 8442 return 0;
08d7b3d1
CW		 8443}
8444
66a9278e 8445static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8446{
66a9278e
DV		 8447 struct drm_device *dev = encoder->base.dev;
8448 struct intel_encoder *source_encoder;
79e53945 8449 int index_mask = 0;
79e53945
JB		 8450 int entry = 0;
8451
66a9278e
DV		 8452 list_for_each_entry(source_encoder,
8453 &dev->mode_config.encoder_list, base.head) {
8454
8455 if (encoder == source_encoder)
79e53945 8456 index_mask |= (1 << entry);
66a9278e
DV		 8457
8458 /* Intel hw has only one MUX where enocoders could be cloned. */
8459 if (encoder->cloneable && source_encoder->cloneable)
8460 index_mask |= (1 << entry);
8461
79e53945
JB		 8462 entry++;
8463 }
4ef69c7a 8464
79e53945
JB		 8465 return index_mask;
8466}
8467
4d302442
CW		 8468static bool has_edp_a(struct drm_device *dev)
8469{
8470 struct drm_i915_private *dev_priv = dev->dev_private;
8471
8472 if (!IS_MOBILE(dev))
8473 return false;
8474
8475 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8476 return false;
8477
8478 if (IS_GEN5(dev) &&
8479 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8480 return false;
8481
8482 return true;
8483}
8484
79e53945
JB		 8485static void intel_setup_outputs(struct drm_device *dev)
8486{
725e30ad 8487 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8488 struct intel_encoder *encoder;
cb0953d7 8489 bool dpd_is_edp = false;
f3cfcba6 8490 bool has_lvds;
79e53945 8491
f3cfcba6 8492 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8493 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8494 /* disable the panel fitter on everything but LVDS */
8495 I915_WRITE(PFIT_CONTROL, 0);
8496 }
79e53945 8497
affa9354 8498 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8499 intel_crt_init(dev);
cb0953d7 8500
affa9354 8501 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8502 int found;
8503
8504 /* Haswell uses DDI functions to detect digital outputs */
8505 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8506 /* DDI A only supports eDP */
8507 if (found)
8508 intel_ddi_init(dev, PORT_A);
8509
8510 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8511 * register */
8512 found = I915_READ(SFUSE_STRAP);
8513
8514 if (found & SFUSE_STRAP_DDIB_DETECTED)
8515 intel_ddi_init(dev, PORT_B);
8516 if (found & SFUSE_STRAP_DDIC_DETECTED)
8517 intel_ddi_init(dev, PORT_C);
8518 if (found & SFUSE_STRAP_DDID_DETECTED)
8519 intel_ddi_init(dev, PORT_D);
8520 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8521 int found;
270b3042
DV		 8522 dpd_is_edp = intel_dpd_is_edp(dev);
8523
8524 if (has_edp_a(dev))
8525 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8526
dc0fa718 8527 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8528 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8529 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8530 if (!found)
e2debe91 8531 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8532 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8533 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8534 }
8535
dc0fa718 8536 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8537 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8538
dc0fa718 8539 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8540 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8541
5eb08b69 8542 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8543 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8544
270b3042 8545 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8546 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8547 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8548 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8549 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8550 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8551
dc0fa718 8552 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8553 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8554 PORT_B);
67cfc203
VS		 8555 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8556 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8557 }
103a196f 8558 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8559 bool found = false;
7d57382e 8560
e2debe91 8561 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8562 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8563 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8564 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8565 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8566 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8567 }
27185ae1 8568
b01f2c3a
JB		 8569 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8570 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8571 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8572 }
725e30ad 8573 }
13520b05
KH		 8574
8575 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8576
e2debe91 8577 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8578 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8579 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8580 }
27185ae1 8581
e2debe91 8582 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8583
b01f2c3a
JB		 8584 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8585 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8586 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8587 }
8588 if (SUPPORTS_INTEGRATED_DP(dev)) {
8589 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8590 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8591 }
725e30ad 8592 }
27185ae1 8593
b01f2c3a
JB		 8594 if (SUPPORTS_INTEGRATED_DP(dev) &&
8595 (I915_READ(DP_D) & DP_DETECTED)) {
8596 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8597 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8598 }
bad720ff 8599 } else if (IS_GEN2(dev))
79e53945
JB		 8600 intel_dvo_init(dev);
8601
103a196f 8602 if (SUPPORTS_TV(dev))
79e53945
JB		 8603 intel_tv_init(dev);
8604
4ef69c7a
CW		 8605 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8606 encoder->base.possible_crtcs = encoder->crtc_mask;
8607 encoder->base.possible_clones =
66a9278e 8608 intel_encoder_clones(encoder);
79e53945 8609 }
47356eb6 8610
dde86e2d 8611 intel_init_pch_refclk(dev);
270b3042
DV		 8612
8613 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8614}
8615
8616static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8617{
8618 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8619
8620 drm_framebuffer_cleanup(fb);
05394f39 8621 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8622
8623 kfree(intel_fb);
8624}
8625
8626static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8627 struct drm_file *file,
79e53945
JB		 8628 unsigned int *handle)
8629{
8630 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8631 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8632
05394f39 8633 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8634}
8635
8636static const struct drm_framebuffer_funcs intel_fb_funcs = {
8637 .destroy = intel_user_framebuffer_destroy,
8638 .create_handle = intel_user_framebuffer_create_handle,
8639};
8640
38651674
DA		 8641int intel_framebuffer_init(struct drm_device *dev,
8642 struct intel_framebuffer *intel_fb,
308e5bcb 8643 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8644 struct drm_i915_gem_object *obj)
79e53945 8645{
79e53945
JB		 8646 int ret;
8647
c16ed4be
CW		 8648 if (obj->tiling_mode == I915_TILING_Y) {
8649 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8650 return -EINVAL;
c16ed4be 8651 }
57cd6508 8652
c16ed4be
CW		 8653 if (mode_cmd->pitches[0] & 63) {
8654 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8655 mode_cmd->pitches[0]);
57cd6508 8656 return -EINVAL;
c16ed4be 8657 }
57cd6508 8658
5d7bd705 8659 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8660 if (mode_cmd->pitches[0] > 32768) {
8661 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8662 mode_cmd->pitches[0]);
5d7bd705 8663 return -EINVAL;
c16ed4be 8664 }
5d7bd705
VS		 8665
8666 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8667 mode_cmd->pitches[0] != obj->stride) {
8668 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8669 mode_cmd->pitches[0], obj->stride);
5d7bd705 8670 return -EINVAL;
c16ed4be 8671 }
5d7bd705 8672
57779d06 8673 /* Reject formats not supported by any plane early. */
308e5bcb 8674 switch (mode_cmd->pixel_format) {
57779d06 8675 case DRM_FORMAT_C8:
04b3924d
VS		 8676 case DRM_FORMAT_RGB565:
8677 case DRM_FORMAT_XRGB8888:
8678 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8679 break;
8680 case DRM_FORMAT_XRGB1555:
8681 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8682 if (INTEL_INFO(dev)->gen > 3) {
8683 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8684 return -EINVAL;
c16ed4be 8685 }
57779d06
VS		 8686 break;
8687 case DRM_FORMAT_XBGR8888:
8688 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8689 case DRM_FORMAT_XRGB2101010:
8690 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8691 case DRM_FORMAT_XBGR2101010:
8692 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8693 if (INTEL_INFO(dev)->gen < 4) {
8694 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8695 return -EINVAL;
c16ed4be 8696 }
b5626747 8697 break;
04b3924d
VS		 8698 case DRM_FORMAT_YUYV:
8699 case DRM_FORMAT_UYVY:
8700 case DRM_FORMAT_YVYU:
8701 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8702 if (INTEL_INFO(dev)->gen < 5) {
8703 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8704 return -EINVAL;
c16ed4be 8705 }
57cd6508
CW		 8706 break;
8707 default:
c16ed4be 8708 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8709 return -EINVAL;
8710 }
8711
90f9a336
VS		 8712 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8713 if (mode_cmd->offsets[0] != 0)
8714 return -EINVAL;
8715
c7d73f6a
DV		 8716 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8717 intel_fb->obj = obj;
8718
79e53945
JB		 8719 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8720 if (ret) {
8721 DRM_ERROR("framebuffer init failed %d\n", ret);
8722 return ret;
8723 }
8724
79e53945
JB		 8725 return 0;
8726}
8727
79e53945
JB		 8728static struct drm_framebuffer *
8729intel_user_framebuffer_create(struct drm_device *dev,
8730 struct drm_file *filp,
308e5bcb 8731 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8732{
05394f39 8733 struct drm_i915_gem_object *obj;
79e53945 8734
308e5bcb
JB		 8735 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8736 mode_cmd->handles[0]));
c8725226 8737 if (&obj->base == NULL)
cce13ff7 8738 return ERR_PTR(-ENOENT);
79e53945 8739
d2dff872 8740 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8741}
8742
79e53945 8743static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8744 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8745 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8746};
8747
e70236a8
JB		 8748/* Set up chip specific display functions */
8749static void intel_init_display(struct drm_device *dev)
8750{
8751 struct drm_i915_private *dev_priv = dev->dev_private;
8752
affa9354 8753 if (HAS_DDI(dev)) {
0e8ffe1b 8754 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8755 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8756 dev_priv->display.crtc_enable = haswell_crtc_enable;
8757 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8758 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8759 dev_priv->display.update_plane = ironlake_update_plane;
8760 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8761 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8762 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8763 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8764 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8765 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8766 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8767 } else {
0e8ffe1b 8768 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8769 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8770 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8771 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8772 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8773 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8774 }
e70236a8 8775
e70236a8 8776 /* Returns the core display clock speed */
25eb05fc
JB		 8777 if (IS_VALLEYVIEW(dev))
8778 dev_priv->display.get_display_clock_speed =
8779 valleyview_get_display_clock_speed;
8780 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8781 dev_priv->display.get_display_clock_speed =
8782 i945_get_display_clock_speed;
8783 else if (IS_I915G(dev))
8784 dev_priv->display.get_display_clock_speed =
8785 i915_get_display_clock_speed;
f2b115e6 8786 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8787 dev_priv->display.get_display_clock_speed =
8788 i9xx_misc_get_display_clock_speed;
8789 else if (IS_I915GM(dev))
8790 dev_priv->display.get_display_clock_speed =
8791 i915gm_get_display_clock_speed;
8792 else if (IS_I865G(dev))
8793 dev_priv->display.get_display_clock_speed =
8794 i865_get_display_clock_speed;
f0f8a9ce 8795 else if (IS_I85X(dev))
e70236a8
JB		 8796 dev_priv->display.get_display_clock_speed =
8797 i855_get_display_clock_speed;
8798 else /* 852, 830 */
8799 dev_priv->display.get_display_clock_speed =
8800 i830_get_display_clock_speed;
8801
7f8a8569 8802 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8803 if (IS_GEN5(dev)) {
674cf967 8804 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8805 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8806 } else if (IS_GEN6(dev)) {
674cf967 8807 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8808 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8809 } else if (IS_IVYBRIDGE(dev)) {
8810 /* FIXME: detect B0+ stepping and use auto training */
8811 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8812 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8813 dev_priv->display.modeset_global_resources =
8814 ivb_modeset_global_resources;
c82e4d26
ED		 8815 } else if (IS_HASWELL(dev)) {
8816 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8817 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8818 dev_priv->display.modeset_global_resources =
8819 haswell_modeset_global_resources;
a0e63c22 8820 }
6067aaea 8821 } else if (IS_G4X(dev)) {
e0dac65e 8822 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8823 }
8c9f3aaf
JB		 8824
8825 /* Default just returns -ENODEV to indicate unsupported */
8826 dev_priv->display.queue_flip = intel_default_queue_flip;
8827
8828 switch (INTEL_INFO(dev)->gen) {
8829 case 2:
8830 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8831 break;
8832
8833 case 3:
8834 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8835 break;
8836
8837 case 4:
8838 case 5:
8839 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8840 break;
8841
8842 case 6:
8843 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8844 break;
7c9017e5
JB		 8845 case 7:
8846 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8847 break;
8c9f3aaf 8848 }
e70236a8
JB		 8849}
8850
b690e96c
JB		 8851/*
8852 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8853 * resume, or other times. This quirk makes sure that's the case for
8854 * affected systems.
8855 */
0206e353 8856static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8857{
8858 struct drm_i915_private *dev_priv = dev->dev_private;
8859
8860 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8861 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8862}
8863
435793df
KP		 8864/*
8865 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8866 */
8867static void quirk_ssc_force_disable(struct drm_device *dev)
8868{
8869 struct drm_i915_private *dev_priv = dev->dev_private;
8870 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8871 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8872}
8873
4dca20ef 8874/*
5a15ab5b
CE		 8875 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8876 * brightness value
4dca20ef
CE		 8877 */
8878static void quirk_invert_brightness(struct drm_device *dev)
8879{
8880 struct drm_i915_private *dev_priv = dev->dev_private;
8881 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8882 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8883}
8884
b690e96c
JB		 8885struct intel_quirk {
8886 int device;
8887 int subsystem_vendor;
8888 int subsystem_device;
8889 void (*hook)(struct drm_device *dev);
8890};
8891
5f85f176
EE		 8892/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8893struct intel_dmi_quirk {
8894 void (*hook)(struct drm_device *dev);
8895 const struct dmi_system_id (*dmi_id_list)[];
8896};
8897
8898static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8899{
8900 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8901 return 1;
8902}
8903
8904static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8905 {
8906 .dmi_id_list = &(const struct dmi_system_id[]) {
8907 {
8908 .callback = intel_dmi_reverse_brightness,
8909 .ident = "NCR Corporation",
8910 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8911 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8912 },
8913 },
8914 { } /* terminating entry */
8915 },
8916 .hook = quirk_invert_brightness,
8917 },
8918};
8919
c43b5634 8920static struct intel_quirk intel_quirks[] = {
b690e96c 8921 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8922 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8923
b690e96c
JB		 8924 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8925 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8926
b690e96c
JB		 8927 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8928 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8929
ccd0d36e 8930 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8931 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8932 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8933
8934 /* Lenovo U160 cannot use SSC on LVDS */
8935 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8936
8937 /* Sony Vaio Y cannot use SSC on LVDS */
8938 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8939
8940 /* Acer Aspire 5734Z must invert backlight brightness */
8941 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8942
8943 /* Acer/eMachines G725 */
8944 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8945
8946 /* Acer/eMachines e725 */
8947 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8948
8949 /* Acer/Packard Bell NCL20 */
8950 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8951
8952 /* Acer Aspire 4736Z */
8953 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8954};
8955
8956static void intel_init_quirks(struct drm_device *dev)
8957{
8958 struct pci_dev *d = dev->pdev;
8959 int i;
8960
8961 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8962 struct intel_quirk *q = &intel_quirks[i];
8963
8964 if (d->device == q->device &&
8965 (d->subsystem_vendor == q->subsystem_vendor ||
8966 q->subsystem_vendor == PCI_ANY_ID) &&
8967 (d->subsystem_device == q->subsystem_device ||
8968 q->subsystem_device == PCI_ANY_ID))
8969 q->hook(dev);
8970 }
5f85f176
EE		 8971 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8972 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8973 intel_dmi_quirks[i].hook(dev);
8974 }
b690e96c
JB		 8975}
8976
9cce37f4
JB		 8977/* Disable the VGA plane that we never use */
8978static void i915_disable_vga(struct drm_device *dev)
8979{
8980 struct drm_i915_private *dev_priv = dev->dev_private;
8981 u8 sr1;
766aa1c4 8982 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8983
8984 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8985 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8986 sr1 = inb(VGA_SR_DATA);
8987 outb(sr1 | 1<<5, VGA_SR_DATA);
8988 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8989 udelay(300);
8990
8991 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8992 POSTING_READ(vga_reg);
8993}
8994
f817586c
DV		 8995void intel_modeset_init_hw(struct drm_device *dev)
8996{
fa42e23c 8997 intel_init_power_well(dev);
0232e927 8998
a8f78b58
ED		 8999 intel_prepare_ddi(dev);
9000
f817586c
DV		 9001 intel_init_clock_gating(dev);
9002
79f5b2c7 9003 mutex_lock(&dev->struct_mutex);
8090c6b9 9004 intel_enable_gt_powersave(dev);
79f5b2c7 9005 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9006}
9007
79e53945
JB		 9008void intel_modeset_init(struct drm_device *dev)
9009{
652c393a 9010 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9011 int i, j, ret;
79e53945
JB		 9012
9013 drm_mode_config_init(dev);
9014
9015 dev->mode_config.min_width = 0;
9016 dev->mode_config.min_height = 0;
9017
019d96cb
DA		 9018 dev->mode_config.preferred_depth = 24;
9019 dev->mode_config.prefer_shadow = 1;
9020
e6ecefaa 9021 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9022
b690e96c
JB		 9023 intel_init_quirks(dev);
9024
1fa61106
ED		 9025 intel_init_pm(dev);
9026
e3c74757
BW		 9027 if (INTEL_INFO(dev)->num_pipes == 0)
9028 return;
9029
e70236a8
JB		 9030 intel_init_display(dev);
9031
a6c45cf0
CW		 9032 if (IS_GEN2(dev)) {
9033 dev->mode_config.max_width = 2048;
9034 dev->mode_config.max_height = 2048;
9035 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9036 dev->mode_config.max_width = 4096;
9037 dev->mode_config.max_height = 4096;
79e53945 9038 } else {
a6c45cf0
CW		 9039 dev->mode_config.max_width = 8192;
9040 dev->mode_config.max_height = 8192;
79e53945 9041 }
5d4545ae 9042 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9043
28c97730 9044 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9045 INTEL_INFO(dev)->num_pipes,
9046 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9047
7eb552ae 9048 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9049 intel_crtc_init(dev, i);
7f1f3851
JB		 9050 for (j = 0; j < dev_priv->num_plane; j++) {
9051 ret = intel_plane_init(dev, i, j);
9052 if (ret)
9053 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9054 i, j, ret);
9055 }
79e53945
JB		 9056 }
9057
79f689aa 9058 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9059 intel_pch_pll_init(dev);
9060
9cce37f4
JB		 9061 /* Just disable it once at startup */
9062 i915_disable_vga(dev);
79e53945 9063 intel_setup_outputs(dev);
11be49eb
CW		 9064
9065 /* Just in case the BIOS is doing something questionable. */
9066 intel_disable_fbc(dev);
2c7111db
CW		 9067}
9068
24929352
DV		 9069static void
9070intel_connector_break_all_links(struct intel_connector *connector)
9071{
9072 connector->base.dpms = DRM_MODE_DPMS_OFF;
9073 connector->base.encoder = NULL;
9074 connector->encoder->connectors_active = false;
9075 connector->encoder->base.crtc = NULL;
9076}
9077
7fad798e
DV		 9078static void intel_enable_pipe_a(struct drm_device *dev)
9079{
9080 struct intel_connector *connector;
9081 struct drm_connector *crt = NULL;
9082 struct intel_load_detect_pipe load_detect_temp;
9083
9084 /* We can't just switch on the pipe A, we need to set things up with a
9085 * proper mode and output configuration. As a gross hack, enable pipe A
9086 * by enabling the load detect pipe once. */
9087 list_for_each_entry(connector,
9088 &dev->mode_config.connector_list,
9089 base.head) {
9090 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9091 crt = &connector->base;
9092 break;
9093 }
9094 }
9095
9096 if (!crt)
9097 return;
9098
9099 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9100 intel_release_load_detect_pipe(crt, &load_detect_temp);
9101
652c393a 9102
7fad798e
DV		 9103}
9104
fa555837
DV		 9105static bool
9106intel_check_plane_mapping(struct intel_crtc *crtc)
9107{
7eb552ae
BW		 9108 struct drm_device *dev = crtc->base.dev;
9109 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9110 u32 reg, val;
9111
7eb552ae 9112 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9113 return true;
9114
9115 reg = DSPCNTR(!crtc->plane);
9116 val = I915_READ(reg);
9117
9118 if ((val & DISPLAY_PLANE_ENABLE) &&
9119 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9120 return false;
9121
9122 return true;
9123}
9124
24929352
DV		 9125static void intel_sanitize_crtc(struct intel_crtc *crtc)
9126{
9127 struct drm_device *dev = crtc->base.dev;
9128 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9129 u32 reg;
24929352 9130
24929352 9131 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9132 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9133 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9134
9135 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9136 * disable the crtc (and hence change the state) if it is wrong. Note
9137 * that gen4+ has a fixed plane -> pipe mapping. */
9138 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9139 struct intel_connector *connector;
9140 bool plane;
9141
24929352
DV		 9142 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9143 crtc->base.base.id);
9144
9145 /* Pipe has the wrong plane attached and the plane is active.
9146 * Temporarily change the plane mapping and disable everything
9147 * ... */
9148 plane = crtc->plane;
9149 crtc->plane = !plane;
9150 dev_priv->display.crtc_disable(&crtc->base);
9151 crtc->plane = plane;
9152
9153 /* ... and break all links. */
9154 list_for_each_entry(connector, &dev->mode_config.connector_list,
9155 base.head) {
9156 if (connector->encoder->base.crtc != &crtc->base)
9157 continue;
9158
9159 intel_connector_break_all_links(connector);
9160 }
9161
9162 WARN_ON(crtc->active);
9163 crtc->base.enabled = false;
9164 }
24929352 9165
7fad798e
DV		 9166 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9167 crtc->pipe == PIPE_A && !crtc->active) {
9168 /* BIOS forgot to enable pipe A, this mostly happens after
9169 * resume. Force-enable the pipe to fix this, the update_dpms
9170 * call below we restore the pipe to the right state, but leave
9171 * the required bits on. */
9172 intel_enable_pipe_a(dev);
9173 }
9174
24929352
DV		 9175 /* Adjust the state of the output pipe according to whether we
9176 * have active connectors/encoders. */
9177 intel_crtc_update_dpms(&crtc->base);
9178
9179 if (crtc->active != crtc->base.enabled) {
9180 struct intel_encoder *encoder;
9181
9182 /* This can happen either due to bugs in the get_hw_state
9183 * functions or because the pipe is force-enabled due to the
9184 * pipe A quirk. */
9185 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9186 crtc->base.base.id,
9187 crtc->base.enabled ? "enabled" : "disabled",
9188 crtc->active ? "enabled" : "disabled");
9189
9190 crtc->base.enabled = crtc->active;
9191
9192 /* Because we only establish the connector -> encoder ->
9193 * crtc links if something is active, this means the
9194 * crtc is now deactivated. Break the links. connector
9195 * -> encoder links are only establish when things are
9196 * actually up, hence no need to break them. */
9197 WARN_ON(crtc->active);
9198
9199 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9200 WARN_ON(encoder->connectors_active);
9201 encoder->base.crtc = NULL;
9202 }
9203 }
9204}
9205
9206static void intel_sanitize_encoder(struct intel_encoder *encoder)
9207{
9208 struct intel_connector *connector;
9209 struct drm_device *dev = encoder->base.dev;
9210
9211 /* We need to check both for a crtc link (meaning that the
9212 * encoder is active and trying to read from a pipe) and the
9213 * pipe itself being active. */
9214 bool has_active_crtc = encoder->base.crtc &&
9215 to_intel_crtc(encoder->base.crtc)->active;
9216
9217 if (encoder->connectors_active && !has_active_crtc) {
9218 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9219 encoder->base.base.id,
9220 drm_get_encoder_name(&encoder->base));
9221
9222 /* Connector is active, but has no active pipe. This is
9223 * fallout from our resume register restoring. Disable
9224 * the encoder manually again. */
9225 if (encoder->base.crtc) {
9226 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9227 encoder->base.base.id,
9228 drm_get_encoder_name(&encoder->base));
9229 encoder->disable(encoder);
9230 }
9231
9232 /* Inconsistent output/port/pipe state happens presumably due to
9233 * a bug in one of the get_hw_state functions. Or someplace else
9234 * in our code, like the register restore mess on resume. Clamp
9235 * things to off as a safer default. */
9236 list_for_each_entry(connector,
9237 &dev->mode_config.connector_list,
9238 base.head) {
9239 if (connector->encoder != encoder)
9240 continue;
9241
9242 intel_connector_break_all_links(connector);
9243 }
9244 }
9245 /* Enabled encoders without active connectors will be fixed in
9246 * the crtc fixup. */
9247}
9248
44cec740 9249void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9250{
9251 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9252 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9253
9254 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9255 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9256 i915_disable_vga(dev);
0fde901f
KM		 9257 }
9258}
9259
24929352
DV		 9260/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9261 * and i915 state tracking structures. */
45e2b5f6
DV		 9262void intel_modeset_setup_hw_state(struct drm_device *dev,
9263 bool force_restore)
24929352
DV		 9264{
9265 struct drm_i915_private *dev_priv = dev->dev_private;
9266 enum pipe pipe;
9267 u32 tmp;
b5644d05 9268 struct drm_plane *plane;
24929352
DV		 9269 struct intel_crtc *crtc;
9270 struct intel_encoder *encoder;
9271 struct intel_connector *connector;
9272
affa9354 9273 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9274 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9275
9276 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9277 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9278 case TRANS_DDI_EDP_INPUT_A_ON:
9279 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9280 pipe = PIPE_A;
9281 break;
9282 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9283 pipe = PIPE_B;
9284 break;
9285 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9286 pipe = PIPE_C;
9287 break;
aaa148ec
DL		 9288 default:
9289 /* A bogus value has been programmed, disable
9290 * the transcoder */
9291 WARN(1, "Bogus eDP source %08x\n", tmp);
9292 intel_ddi_disable_transcoder_func(dev_priv,
9293 TRANSCODER_EDP);
9294 goto setup_pipes;
e28d54cb
PZ		 9295 }
9296
9297 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9298 crtc->cpu_transcoder = TRANSCODER_EDP;
9299
9300 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9301 pipe_name(pipe));
9302 }
9303 }
9304
aaa148ec 9305setup_pipes:
0e8ffe1b
DV		 9306 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9307 base.head) {
88adfff1 9308 memset(&crtc->config, 0, sizeof(crtc->config));
0e8ffe1b
DV		 9309 crtc->active = dev_priv->display.get_pipe_config(crtc,
9310 &crtc->config);
24929352
DV		 9311
9312 crtc->base.enabled = crtc->active;
9313
9314 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9315 crtc->base.base.id,
9316 crtc->active ? "enabled" : "disabled");
9317 }
9318
affa9354 9319 if (HAS_DDI(dev))
6441ab5f
PZ		 9320 intel_ddi_setup_hw_pll_state(dev);
9321
24929352
DV		 9322 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9323 base.head) {
9324 pipe = 0;
9325
9326 if (encoder->get_hw_state(encoder, &pipe)) {
9327 encoder->base.crtc =
9328 dev_priv->pipe_to_crtc_mapping[pipe];
9329 } else {
9330 encoder->base.crtc = NULL;
9331 }
9332
9333 encoder->connectors_active = false;
9334 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9335 encoder->base.base.id,
9336 drm_get_encoder_name(&encoder->base),
9337 encoder->base.crtc ? "enabled" : "disabled",
9338 pipe);
9339 }
9340
9341 list_for_each_entry(connector, &dev->mode_config.connector_list,
9342 base.head) {
9343 if (connector->get_hw_state(connector)) {
9344 connector->base.dpms = DRM_MODE_DPMS_ON;
9345 connector->encoder->connectors_active = true;
9346 connector->base.encoder = &connector->encoder->base;
9347 } else {
9348 connector->base.dpms = DRM_MODE_DPMS_OFF;
9349 connector->base.encoder = NULL;
9350 }
9351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9352 connector->base.base.id,
9353 drm_get_connector_name(&connector->base),
9354 connector->base.encoder ? "enabled" : "disabled");
9355 }
9356
9357 /* HW state is read out, now we need to sanitize this mess. */
9358 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9359 base.head) {
9360 intel_sanitize_encoder(encoder);
9361 }
9362
9363 for_each_pipe(pipe) {
9364 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9365 intel_sanitize_crtc(crtc);
9366 }
9a935856 9367
45e2b5f6 9368 if (force_restore) {
f30da187
DV		 9369 /*
9370 * We need to use raw interfaces for restoring state to avoid
9371 * checking (bogus) intermediate states.
9372 */
45e2b5f6 9373 for_each_pipe(pipe) {
b5644d05
JB		 9374 struct drm_crtc *crtc =
9375 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9376
9377 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9378 crtc->fb);
45e2b5f6 9379 }
b5644d05
JB		 9380 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9381 intel_plane_restore(plane);
0fde901f
KM		 9382
9383 i915_redisable_vga(dev);
45e2b5f6
DV		 9384 } else {
9385 intel_modeset_update_staged_output_state(dev);
9386 }
8af6cf88
DV		 9387
9388 intel_modeset_check_state(dev);
2e938892
DV		 9389
9390 drm_mode_config_reset(dev);
2c7111db
CW		 9391}
9392
9393void intel_modeset_gem_init(struct drm_device *dev)
9394{
1833b134 9395 intel_modeset_init_hw(dev);
02e792fb
DV		 9396
9397 intel_setup_overlay(dev);
24929352 9398
45e2b5f6 9399 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9400}
9401
9402void intel_modeset_cleanup(struct drm_device *dev)
9403{
652c393a
JB		 9404 struct drm_i915_private *dev_priv = dev->dev_private;
9405 struct drm_crtc *crtc;
9406 struct intel_crtc *intel_crtc;
9407
f87ea761 9408 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9409 mutex_lock(&dev->struct_mutex);
9410
723bfd70
JB		 9411 intel_unregister_dsm_handler();
9412
9413
652c393a
JB		 9414 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9415 /* Skip inactive CRTCs */
9416 if (!crtc->fb)
9417 continue;
9418
9419 intel_crtc = to_intel_crtc(crtc);
3dec0095 9420 intel_increase_pllclock(crtc);
652c393a
JB		 9421 }
9422
973d04f9 9423 intel_disable_fbc(dev);
e70236a8 9424
8090c6b9 9425 intel_disable_gt_powersave(dev);
0cdab21f 9426
930ebb46
DV		 9427 ironlake_teardown_rc6(dev);
9428
57f350b6
JB		 9429 if (IS_VALLEYVIEW(dev))
9430 vlv_init_dpio(dev);
9431
69341a5e
KH		 9432 mutex_unlock(&dev->struct_mutex);
9433
6c0d9350
DV		 9434 /* Disable the irq before mode object teardown, for the irq might
9435 * enqueue unpin/hotplug work. */
9436 drm_irq_uninstall(dev);
9437 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9438 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9439
1630fe75
CW		 9440 /* flush any delayed tasks or pending work */
9441 flush_scheduled_work();
9442
dc652f90
JN		 9443 /* destroy backlight, if any, before the connectors */
9444 intel_panel_destroy_backlight(dev);
9445
79e53945 9446 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9447
9448 intel_cleanup_overlay(dev);
79e53945
JB		 9449}
9450
f1c79df3
ZW		 9451/*
9452 * Return which encoder is currently attached for connector.
9453 */
df0e9248 9454struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9455{
df0e9248
CW		 9456 return &intel_attached_encoder(connector)->base;
9457}
f1c79df3 9458
df0e9248
CW		 9459void intel_connector_attach_encoder(struct intel_connector *connector,
9460 struct intel_encoder *encoder)
9461{
9462 connector->encoder = encoder;
9463 drm_mode_connector_attach_encoder(&connector->base,
9464 &encoder->base);
79e53945 9465}
28d52043
DA		 9466
9467/*
9468 * set vga decode state - true == enable VGA decode
9469 */
9470int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9471{
9472 struct drm_i915_private *dev_priv = dev->dev_private;
9473 u16 gmch_ctrl;
9474
9475 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9476 if (state)
9477 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9478 else
9479 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9480 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9481 return 0;
9482}
c4a1d9e4
CW		 9483
9484#ifdef CONFIG_DEBUG_FS
9485#include <linux/seq_file.h>
9486
9487struct intel_display_error_state {
9488 struct intel_cursor_error_state {
9489 u32 control;
9490 u32 position;
9491 u32 base;
9492 u32 size;
52331309 9493 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9494
9495 struct intel_pipe_error_state {
9496 u32 conf;
9497 u32 source;
9498
9499 u32 htotal;
9500 u32 hblank;
9501 u32 hsync;
9502 u32 vtotal;
9503 u32 vblank;
9504 u32 vsync;
52331309 9505 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9506
9507 struct intel_plane_error_state {
9508 u32 control;
9509 u32 stride;
9510 u32 size;
9511 u32 pos;
9512 u32 addr;
9513 u32 surface;
9514 u32 tile_offset;
52331309 9515 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9516};
9517
9518struct intel_display_error_state *
9519intel_display_capture_error_state(struct drm_device *dev)
9520{
0206e353 9521 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9522 struct intel_display_error_state *error;
702e7a56 9523 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9524 int i;
9525
9526 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9527 if (error == NULL)
9528 return NULL;
9529
52331309 9530 for_each_pipe(i) {
702e7a56
PZ		 9531 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9532
a18c4c3d
PZ		 9533 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9534 error->cursor[i].control = I915_READ(CURCNTR(i));
9535 error->cursor[i].position = I915_READ(CURPOS(i));
9536 error->cursor[i].base = I915_READ(CURBASE(i));
9537 } else {
9538 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9539 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9540 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9541 }
c4a1d9e4
CW		 9542
9543 error->plane[i].control = I915_READ(DSPCNTR(i));
9544 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9545 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9546 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9547 error->plane[i].pos = I915_READ(DSPPOS(i));
9548 }
ca291363
PZ		 9549 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9550 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9551 if (INTEL_INFO(dev)->gen >= 4) {
9552 error->plane[i].surface = I915_READ(DSPSURF(i));
9553 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9554 }
9555
702e7a56 9556 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9557 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9558 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9559 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9560 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9561 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9562 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9563 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9564 }
9565
9566 return error;
9567}
9568
9569void
9570intel_display_print_error_state(struct seq_file *m,
9571 struct drm_device *dev,
9572 struct intel_display_error_state *error)
9573{
9574 int i;
9575
7eb552ae 9576 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9577 for_each_pipe(i) {
c4a1d9e4
CW		 9578 seq_printf(m, "Pipe [%d]:\n", i);
9579 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9580 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9581 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9582 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9583 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9584 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9585 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9586 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9587
9588 seq_printf(m, "Plane [%d]:\n", i);
9589 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9590 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9591 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9592 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9593 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9594 }
4b71a570 9595 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9596 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9597 if (INTEL_INFO(dev)->gen >= 4) {
9598 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9599 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9600 }
9601
9602 seq_printf(m, "Cursor [%d]:\n", i);
9603 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9604 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9605 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9606 }
9607}
9608#endif
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