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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 AJ |
92 | .dot = { .min = 25000, .max = 350000 }, |
93 | .vco = { .min = 930000, .max = 1400000 }, | |
94 | .n = { .min = 3, .max = 16 }, | |
95 | .m = { .min = 96, .max = 140 }, | |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
106 | .vco = { .min = 930000, .max = 1400000 }, | |
107 | .n = { .min = 3, .max = 16 }, | |
108 | .m = { .min = 96, .max = 140 }, | |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 AJ |
118 | .dot = { .min = 25000, .max = 350000 }, |
119 | .vco = { .min = 930000, .max = 1400000 }, | |
120 | .n = { .min = 3, .max = 16 }, | |
121 | .m = { .min = 96, .max = 140 }, | |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
fb03ac01 VS |
332 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
333 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
334 | } |
335 | ||
e0638cdf PZ |
336 | /** |
337 | * Returns whether any output on the specified pipe is of the specified type | |
338 | */ | |
339 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
340 | { | |
341 | struct drm_device *dev = crtc->dev; | |
342 | struct intel_encoder *encoder; | |
343 | ||
344 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
345 | if (encoder->type == type) | |
346 | return true; | |
347 | ||
348 | return false; | |
349 | } | |
350 | ||
1b894b59 CW |
351 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
352 | int refclk) | |
2c07245f | 353 | { |
b91ad0ec | 354 | struct drm_device *dev = crtc->dev; |
2c07245f | 355 | const intel_limit_t *limit; |
b91ad0ec ZW |
356 | |
357 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 358 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 359 | if (refclk == 100000) |
b91ad0ec ZW |
360 | limit = &intel_limits_ironlake_dual_lvds_100m; |
361 | else | |
362 | limit = &intel_limits_ironlake_dual_lvds; | |
363 | } else { | |
1b894b59 | 364 | if (refclk == 100000) |
b91ad0ec ZW |
365 | limit = &intel_limits_ironlake_single_lvds_100m; |
366 | else | |
367 | limit = &intel_limits_ironlake_single_lvds; | |
368 | } | |
c6bb3538 | 369 | } else |
b91ad0ec | 370 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
371 | |
372 | return limit; | |
373 | } | |
374 | ||
044c7c41 ML |
375 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
376 | { | |
377 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
378 | const intel_limit_t *limit; |
379 | ||
380 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 381 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 382 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 383 | else |
e4b36699 | 384 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
385 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
386 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 387 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 388 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 389 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 390 | } else /* The option is for other outputs */ |
e4b36699 | 391 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
392 | |
393 | return limit; | |
394 | } | |
395 | ||
1b894b59 | 396 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
397 | { |
398 | struct drm_device *dev = crtc->dev; | |
399 | const intel_limit_t *limit; | |
400 | ||
bad720ff | 401 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 402 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 403 | else if (IS_G4X(dev)) { |
044c7c41 | 404 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 405 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 406 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 407 | limit = &intel_limits_pineview_lvds; |
2177832f | 408 | else |
f2b115e6 | 409 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 410 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 411 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
412 | } else if (!IS_GEN2(dev)) { |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
414 | limit = &intel_limits_i9xx_lvds; | |
415 | else | |
416 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
417 | } else { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 419 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 421 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
422 | else |
423 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
424 | } |
425 | return limit; | |
426 | } | |
427 | ||
f2b115e6 AJ |
428 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
429 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 430 | { |
2177832f SL |
431 | clock->m = clock->m2 + 2; |
432 | clock->p = clock->p1 * clock->p2; | |
fb03ac01 VS |
433 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
434 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
435 | } |
436 | ||
7429e9d4 DV |
437 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
438 | { | |
439 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
440 | } | |
441 | ||
ac58c3f0 | 442 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 443 | { |
7429e9d4 | 444 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 445 | clock->p = clock->p1 * clock->p2; |
fb03ac01 VS |
446 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
447 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
448 | } |
449 | ||
7c04d1d9 | 450 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
451 | /** |
452 | * Returns whether the given set of divisors are valid for a given refclk with | |
453 | * the given connectors. | |
454 | */ | |
455 | ||
1b894b59 CW |
456 | static bool intel_PLL_is_valid(struct drm_device *dev, |
457 | const intel_limit_t *limit, | |
458 | const intel_clock_t *clock) | |
79e53945 | 459 | { |
f01b7962 VS |
460 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
461 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 462 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 463 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 464 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 465 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 466 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 467 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
468 | |
469 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
470 | if (clock->m1 <= clock->m2) | |
471 | INTELPllInvalid("m1 <= m2\n"); | |
472 | ||
473 | if (!IS_VALLEYVIEW(dev)) { | |
474 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
475 | INTELPllInvalid("p out of range\n"); | |
476 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
477 | INTELPllInvalid("m out of range\n"); | |
478 | } | |
479 | ||
79e53945 | 480 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 481 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
482 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
483 | * connector, etc., rather than just a single range. | |
484 | */ | |
485 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 486 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
487 | |
488 | return true; | |
489 | } | |
490 | ||
d4906093 | 491 | static bool |
ee9300bb | 492 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
493 | int target, int refclk, intel_clock_t *match_clock, |
494 | intel_clock_t *best_clock) | |
79e53945 JB |
495 | { |
496 | struct drm_device *dev = crtc->dev; | |
79e53945 | 497 | intel_clock_t clock; |
79e53945 JB |
498 | int err = target; |
499 | ||
a210b028 | 500 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 501 | /* |
a210b028 DV |
502 | * For LVDS just rely on its current settings for dual-channel. |
503 | * We haven't figured out how to reliably set up different | |
504 | * single/dual channel state, if we even can. | |
79e53945 | 505 | */ |
1974cad0 | 506 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
507 | clock.p2 = limit->p2.p2_fast; |
508 | else | |
509 | clock.p2 = limit->p2.p2_slow; | |
510 | } else { | |
511 | if (target < limit->p2.dot_limit) | |
512 | clock.p2 = limit->p2.p2_slow; | |
513 | else | |
514 | clock.p2 = limit->p2.p2_fast; | |
515 | } | |
516 | ||
0206e353 | 517 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 518 | |
42158660 ZY |
519 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
520 | clock.m1++) { | |
521 | for (clock.m2 = limit->m2.min; | |
522 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 523 | if (clock.m2 >= clock.m1) |
42158660 ZY |
524 | break; |
525 | for (clock.n = limit->n.min; | |
526 | clock.n <= limit->n.max; clock.n++) { | |
527 | for (clock.p1 = limit->p1.min; | |
528 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
529 | int this_err; |
530 | ||
ac58c3f0 DV |
531 | i9xx_clock(refclk, &clock); |
532 | if (!intel_PLL_is_valid(dev, limit, | |
533 | &clock)) | |
534 | continue; | |
535 | if (match_clock && | |
536 | clock.p != match_clock->p) | |
537 | continue; | |
538 | ||
539 | this_err = abs(clock.dot - target); | |
540 | if (this_err < err) { | |
541 | *best_clock = clock; | |
542 | err = this_err; | |
543 | } | |
544 | } | |
545 | } | |
546 | } | |
547 | } | |
548 | ||
549 | return (err != target); | |
550 | } | |
551 | ||
552 | static bool | |
ee9300bb DV |
553 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
554 | int target, int refclk, intel_clock_t *match_clock, | |
555 | intel_clock_t *best_clock) | |
79e53945 JB |
556 | { |
557 | struct drm_device *dev = crtc->dev; | |
79e53945 | 558 | intel_clock_t clock; |
79e53945 JB |
559 | int err = target; |
560 | ||
a210b028 | 561 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 562 | /* |
a210b028 DV |
563 | * For LVDS just rely on its current settings for dual-channel. |
564 | * We haven't figured out how to reliably set up different | |
565 | * single/dual channel state, if we even can. | |
79e53945 | 566 | */ |
1974cad0 | 567 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
568 | clock.p2 = limit->p2.p2_fast; |
569 | else | |
570 | clock.p2 = limit->p2.p2_slow; | |
571 | } else { | |
572 | if (target < limit->p2.dot_limit) | |
573 | clock.p2 = limit->p2.p2_slow; | |
574 | else | |
575 | clock.p2 = limit->p2.p2_fast; | |
576 | } | |
577 | ||
0206e353 | 578 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 579 | |
42158660 ZY |
580 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
581 | clock.m1++) { | |
582 | for (clock.m2 = limit->m2.min; | |
583 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
584 | for (clock.n = limit->n.min; |
585 | clock.n <= limit->n.max; clock.n++) { | |
586 | for (clock.p1 = limit->p1.min; | |
587 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
588 | int this_err; |
589 | ||
ac58c3f0 | 590 | pineview_clock(refclk, &clock); |
1b894b59 CW |
591 | if (!intel_PLL_is_valid(dev, limit, |
592 | &clock)) | |
79e53945 | 593 | continue; |
cec2f356 SP |
594 | if (match_clock && |
595 | clock.p != match_clock->p) | |
596 | continue; | |
79e53945 JB |
597 | |
598 | this_err = abs(clock.dot - target); | |
599 | if (this_err < err) { | |
600 | *best_clock = clock; | |
601 | err = this_err; | |
602 | } | |
603 | } | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | return (err != target); | |
609 | } | |
610 | ||
d4906093 | 611 | static bool |
ee9300bb DV |
612 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
613 | int target, int refclk, intel_clock_t *match_clock, | |
614 | intel_clock_t *best_clock) | |
d4906093 ML |
615 | { |
616 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
617 | intel_clock_t clock; |
618 | int max_n; | |
619 | bool found; | |
6ba770dc AJ |
620 | /* approximately equals target * 0.00585 */ |
621 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
622 | found = false; |
623 | ||
624 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 625 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
626 | clock.p2 = limit->p2.p2_fast; |
627 | else | |
628 | clock.p2 = limit->p2.p2_slow; | |
629 | } else { | |
630 | if (target < limit->p2.dot_limit) | |
631 | clock.p2 = limit->p2.p2_slow; | |
632 | else | |
633 | clock.p2 = limit->p2.p2_fast; | |
634 | } | |
635 | ||
636 | memset(best_clock, 0, sizeof(*best_clock)); | |
637 | max_n = limit->n.max; | |
f77f13e2 | 638 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 639 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 640 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
641 | for (clock.m1 = limit->m1.max; |
642 | clock.m1 >= limit->m1.min; clock.m1--) { | |
643 | for (clock.m2 = limit->m2.max; | |
644 | clock.m2 >= limit->m2.min; clock.m2--) { | |
645 | for (clock.p1 = limit->p1.max; | |
646 | clock.p1 >= limit->p1.min; clock.p1--) { | |
647 | int this_err; | |
648 | ||
ac58c3f0 | 649 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
650 | if (!intel_PLL_is_valid(dev, limit, |
651 | &clock)) | |
d4906093 | 652 | continue; |
1b894b59 CW |
653 | |
654 | this_err = abs(clock.dot - target); | |
d4906093 ML |
655 | if (this_err < err_most) { |
656 | *best_clock = clock; | |
657 | err_most = this_err; | |
658 | max_n = clock.n; | |
659 | found = true; | |
660 | } | |
661 | } | |
662 | } | |
663 | } | |
664 | } | |
2c07245f ZW |
665 | return found; |
666 | } | |
667 | ||
a0c4da24 | 668 | static bool |
ee9300bb DV |
669 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
670 | int target, int refclk, intel_clock_t *match_clock, | |
671 | intel_clock_t *best_clock) | |
a0c4da24 | 672 | { |
f01b7962 | 673 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 674 | intel_clock_t clock; |
69e4f900 | 675 | unsigned int bestppm = 1000000; |
27e639bf VS |
676 | /* min update 19.2 MHz */ |
677 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 678 | bool found = false; |
a0c4da24 | 679 | |
6b4bf1c4 VS |
680 | target *= 5; /* fast clock */ |
681 | ||
682 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
683 | |
684 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 685 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 686 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 687 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 688 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 689 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 690 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 691 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
692 | unsigned int ppm, diff; |
693 | ||
6b4bf1c4 VS |
694 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
695 | refclk * clock.m1); | |
696 | ||
697 | vlv_clock(refclk, &clock); | |
43b0ac53 | 698 | |
f01b7962 VS |
699 | if (!intel_PLL_is_valid(dev, limit, |
700 | &clock)) | |
43b0ac53 VS |
701 | continue; |
702 | ||
6b4bf1c4 VS |
703 | diff = abs(clock.dot - target); |
704 | ppm = div_u64(1000000ULL * diff, target); | |
705 | ||
706 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 707 | bestppm = 0; |
6b4bf1c4 | 708 | *best_clock = clock; |
49e497ef | 709 | found = true; |
43b0ac53 | 710 | } |
6b4bf1c4 | 711 | |
c686122c | 712 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 713 | bestppm = ppm; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
a0c4da24 JB |
716 | } |
717 | } | |
718 | } | |
719 | } | |
720 | } | |
a0c4da24 | 721 | |
49e497ef | 722 | return found; |
a0c4da24 | 723 | } |
a4fc5ed6 | 724 | |
20ddf665 VS |
725 | bool intel_crtc_active(struct drm_crtc *crtc) |
726 | { | |
727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
728 | ||
729 | /* Be paranoid as we can arrive here with only partial | |
730 | * state retrieved from the hardware during setup. | |
731 | * | |
241bfc38 | 732 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
733 | * as Haswell has gained clock readout/fastboot support. |
734 | * | |
735 | * We can ditch the crtc->fb check as soon as we can | |
736 | * properly reconstruct framebuffers. | |
737 | */ | |
738 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 739 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
740 | } |
741 | ||
a5c961d1 PZ |
742 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
743 | enum pipe pipe) | |
744 | { | |
745 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
747 | ||
3b117c8f | 748 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
749 | } |
750 | ||
57e22f4a | 751 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
752 | { |
753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 754 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
755 | |
756 | frame = I915_READ(frame_reg); | |
757 | ||
758 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
759 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
760 | } | |
761 | ||
9d0498a2 JB |
762 | /** |
763 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
764 | * @dev: drm device | |
765 | * @pipe: pipe to wait for | |
766 | * | |
767 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
768 | * mode setting code. | |
769 | */ | |
770 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 771 | { |
9d0498a2 | 772 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 773 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 774 | |
57e22f4a VS |
775 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
776 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
777 | return; |
778 | } | |
779 | ||
300387c0 CW |
780 | /* Clear existing vblank status. Note this will clear any other |
781 | * sticky status fields as well. | |
782 | * | |
783 | * This races with i915_driver_irq_handler() with the result | |
784 | * that either function could miss a vblank event. Here it is not | |
785 | * fatal, as we will either wait upon the next vblank interrupt or | |
786 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
787 | * called during modeset at which time the GPU should be idle and | |
788 | * should *not* be performing page flips and thus not waiting on | |
789 | * vblanks... | |
790 | * Currently, the result of us stealing a vblank from the irq | |
791 | * handler is that a single frame will be skipped during swapbuffers. | |
792 | */ | |
793 | I915_WRITE(pipestat_reg, | |
794 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
795 | ||
9d0498a2 | 796 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
797 | if (wait_for(I915_READ(pipestat_reg) & |
798 | PIPE_VBLANK_INTERRUPT_STATUS, | |
799 | 50)) | |
9d0498a2 JB |
800 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
801 | } | |
802 | ||
fbf49ea2 VS |
803 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
804 | { | |
805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
806 | u32 reg = PIPEDSL(pipe); | |
807 | u32 line1, line2; | |
808 | u32 line_mask; | |
809 | ||
810 | if (IS_GEN2(dev)) | |
811 | line_mask = DSL_LINEMASK_GEN2; | |
812 | else | |
813 | line_mask = DSL_LINEMASK_GEN3; | |
814 | ||
815 | line1 = I915_READ(reg) & line_mask; | |
816 | mdelay(5); | |
817 | line2 = I915_READ(reg) & line_mask; | |
818 | ||
819 | return line1 == line2; | |
820 | } | |
821 | ||
ab7ad7f6 KP |
822 | /* |
823 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
824 | * @dev: drm device |
825 | * @pipe: pipe to wait for | |
826 | * | |
827 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
828 | * spinning on the vblank interrupt status bit, since we won't actually | |
829 | * see an interrupt when the pipe is disabled. | |
830 | * | |
ab7ad7f6 KP |
831 | * On Gen4 and above: |
832 | * wait for the pipe register state bit to turn off | |
833 | * | |
834 | * Otherwise: | |
835 | * wait for the display line value to settle (it usually | |
836 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 837 | * |
9d0498a2 | 838 | */ |
58e10eb9 | 839 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
840 | { |
841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
842 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
843 | pipe); | |
ab7ad7f6 KP |
844 | |
845 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 846 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
847 | |
848 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
849 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
850 | 100)) | |
284637d9 | 851 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 852 | } else { |
ab7ad7f6 | 853 | /* Wait for the display line to settle */ |
fbf49ea2 | 854 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 855 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 856 | } |
79e53945 JB |
857 | } |
858 | ||
b0ea7d37 DL |
859 | /* |
860 | * ibx_digital_port_connected - is the specified port connected? | |
861 | * @dev_priv: i915 private structure | |
862 | * @port: the port to test | |
863 | * | |
864 | * Returns true if @port is connected, false otherwise. | |
865 | */ | |
866 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
867 | struct intel_digital_port *port) | |
868 | { | |
869 | u32 bit; | |
870 | ||
c36346e3 DL |
871 | if (HAS_PCH_IBX(dev_priv->dev)) { |
872 | switch(port->port) { | |
873 | case PORT_B: | |
874 | bit = SDE_PORTB_HOTPLUG; | |
875 | break; | |
876 | case PORT_C: | |
877 | bit = SDE_PORTC_HOTPLUG; | |
878 | break; | |
879 | case PORT_D: | |
880 | bit = SDE_PORTD_HOTPLUG; | |
881 | break; | |
882 | default: | |
883 | return true; | |
884 | } | |
885 | } else { | |
886 | switch(port->port) { | |
887 | case PORT_B: | |
888 | bit = SDE_PORTB_HOTPLUG_CPT; | |
889 | break; | |
890 | case PORT_C: | |
891 | bit = SDE_PORTC_HOTPLUG_CPT; | |
892 | break; | |
893 | case PORT_D: | |
894 | bit = SDE_PORTD_HOTPLUG_CPT; | |
895 | break; | |
896 | default: | |
897 | return true; | |
898 | } | |
b0ea7d37 DL |
899 | } |
900 | ||
901 | return I915_READ(SDEISR) & bit; | |
902 | } | |
903 | ||
b24e7179 JB |
904 | static const char *state_string(bool enabled) |
905 | { | |
906 | return enabled ? "on" : "off"; | |
907 | } | |
908 | ||
909 | /* Only for pre-ILK configs */ | |
55607e8a DV |
910 | void assert_pll(struct drm_i915_private *dev_priv, |
911 | enum pipe pipe, bool state) | |
b24e7179 JB |
912 | { |
913 | int reg; | |
914 | u32 val; | |
915 | bool cur_state; | |
916 | ||
917 | reg = DPLL(pipe); | |
918 | val = I915_READ(reg); | |
919 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
920 | WARN(cur_state != state, | |
921 | "PLL state assertion failure (expected %s, current %s)\n", | |
922 | state_string(state), state_string(cur_state)); | |
923 | } | |
b24e7179 | 924 | |
23538ef1 JN |
925 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
926 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
927 | { | |
928 | u32 val; | |
929 | bool cur_state; | |
930 | ||
931 | mutex_lock(&dev_priv->dpio_lock); | |
932 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
933 | mutex_unlock(&dev_priv->dpio_lock); | |
934 | ||
935 | cur_state = val & DSI_PLL_VCO_EN; | |
936 | WARN(cur_state != state, | |
937 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
938 | state_string(state), state_string(cur_state)); | |
939 | } | |
940 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
941 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
942 | ||
55607e8a | 943 | struct intel_shared_dpll * |
e2b78267 DV |
944 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
945 | { | |
946 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
947 | ||
a43f6e0f | 948 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
949 | return NULL; |
950 | ||
a43f6e0f | 951 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
952 | } |
953 | ||
040484af | 954 | /* For ILK+ */ |
55607e8a DV |
955 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
956 | struct intel_shared_dpll *pll, | |
957 | bool state) | |
040484af | 958 | { |
040484af | 959 | bool cur_state; |
5358901f | 960 | struct intel_dpll_hw_state hw_state; |
040484af | 961 | |
9d82aa17 ED |
962 | if (HAS_PCH_LPT(dev_priv->dev)) { |
963 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
964 | return; | |
965 | } | |
966 | ||
92b27b08 | 967 | if (WARN (!pll, |
46edb027 | 968 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 969 | return; |
ee7b9f93 | 970 | |
5358901f | 971 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 972 | WARN(cur_state != state, |
5358901f DV |
973 | "%s assertion failure (expected %s, current %s)\n", |
974 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 975 | } |
040484af JB |
976 | |
977 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
978 | enum pipe pipe, bool state) | |
979 | { | |
980 | int reg; | |
981 | u32 val; | |
982 | bool cur_state; | |
ad80a810 PZ |
983 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
984 | pipe); | |
040484af | 985 | |
affa9354 PZ |
986 | if (HAS_DDI(dev_priv->dev)) { |
987 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 988 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 989 | val = I915_READ(reg); |
ad80a810 | 990 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
991 | } else { |
992 | reg = FDI_TX_CTL(pipe); | |
993 | val = I915_READ(reg); | |
994 | cur_state = !!(val & FDI_TX_ENABLE); | |
995 | } | |
040484af JB |
996 | WARN(cur_state != state, |
997 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
998 | state_string(state), state_string(cur_state)); | |
999 | } | |
1000 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1001 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1002 | ||
1003 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1004 | enum pipe pipe, bool state) | |
1005 | { | |
1006 | int reg; | |
1007 | u32 val; | |
1008 | bool cur_state; | |
1009 | ||
d63fa0dc PZ |
1010 | reg = FDI_RX_CTL(pipe); |
1011 | val = I915_READ(reg); | |
1012 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1013 | WARN(cur_state != state, |
1014 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1015 | state_string(state), state_string(cur_state)); | |
1016 | } | |
1017 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1018 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1019 | ||
1020 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1021 | enum pipe pipe) | |
1022 | { | |
1023 | int reg; | |
1024 | u32 val; | |
1025 | ||
1026 | /* ILK FDI PLL is always enabled */ | |
1027 | if (dev_priv->info->gen == 5) | |
1028 | return; | |
1029 | ||
bf507ef7 | 1030 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1031 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1032 | return; |
1033 | ||
040484af JB |
1034 | reg = FDI_TX_CTL(pipe); |
1035 | val = I915_READ(reg); | |
1036 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1037 | } | |
1038 | ||
55607e8a DV |
1039 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1040 | enum pipe pipe, bool state) | |
040484af JB |
1041 | { |
1042 | int reg; | |
1043 | u32 val; | |
55607e8a | 1044 | bool cur_state; |
040484af JB |
1045 | |
1046 | reg = FDI_RX_CTL(pipe); | |
1047 | val = I915_READ(reg); | |
55607e8a DV |
1048 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1049 | WARN(cur_state != state, | |
1050 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1051 | state_string(state), state_string(cur_state)); | |
040484af JB |
1052 | } |
1053 | ||
ea0760cf JB |
1054 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1055 | enum pipe pipe) | |
1056 | { | |
1057 | int pp_reg, lvds_reg; | |
1058 | u32 val; | |
1059 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1060 | bool locked = true; |
ea0760cf JB |
1061 | |
1062 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1063 | pp_reg = PCH_PP_CONTROL; | |
1064 | lvds_reg = PCH_LVDS; | |
1065 | } else { | |
1066 | pp_reg = PP_CONTROL; | |
1067 | lvds_reg = LVDS; | |
1068 | } | |
1069 | ||
1070 | val = I915_READ(pp_reg); | |
1071 | if (!(val & PANEL_POWER_ON) || | |
1072 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1073 | locked = false; | |
1074 | ||
1075 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1076 | panel_pipe = PIPE_B; | |
1077 | ||
1078 | WARN(panel_pipe == pipe && locked, | |
1079 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1080 | pipe_name(pipe)); |
ea0760cf JB |
1081 | } |
1082 | ||
93ce0ba6 JN |
1083 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1084 | enum pipe pipe, bool state) | |
1085 | { | |
1086 | struct drm_device *dev = dev_priv->dev; | |
1087 | bool cur_state; | |
1088 | ||
1089 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1090 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1091 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1092 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1093 | else | |
1094 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1095 | ||
1096 | WARN(cur_state != state, | |
1097 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1098 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1099 | } | |
1100 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1101 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1102 | ||
b840d907 JB |
1103 | void assert_pipe(struct drm_i915_private *dev_priv, |
1104 | enum pipe pipe, bool state) | |
b24e7179 JB |
1105 | { |
1106 | int reg; | |
1107 | u32 val; | |
63d7bbe9 | 1108 | bool cur_state; |
702e7a56 PZ |
1109 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1110 | pipe); | |
b24e7179 | 1111 | |
8e636784 DV |
1112 | /* if we need the pipe A quirk it must be always on */ |
1113 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1114 | state = true; | |
1115 | ||
b97186f0 PZ |
1116 | if (!intel_display_power_enabled(dev_priv->dev, |
1117 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1118 | cur_state = false; |
1119 | } else { | |
1120 | reg = PIPECONF(cpu_transcoder); | |
1121 | val = I915_READ(reg); | |
1122 | cur_state = !!(val & PIPECONF_ENABLE); | |
1123 | } | |
1124 | ||
63d7bbe9 JB |
1125 | WARN(cur_state != state, |
1126 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1127 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1128 | } |
1129 | ||
931872fc CW |
1130 | static void assert_plane(struct drm_i915_private *dev_priv, |
1131 | enum plane plane, bool state) | |
b24e7179 JB |
1132 | { |
1133 | int reg; | |
1134 | u32 val; | |
931872fc | 1135 | bool cur_state; |
b24e7179 JB |
1136 | |
1137 | reg = DSPCNTR(plane); | |
1138 | val = I915_READ(reg); | |
931872fc CW |
1139 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1140 | WARN(cur_state != state, | |
1141 | "plane %c assertion failure (expected %s, current %s)\n", | |
1142 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1143 | } |
1144 | ||
931872fc CW |
1145 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1146 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1147 | ||
b24e7179 JB |
1148 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1149 | enum pipe pipe) | |
1150 | { | |
653e1026 | 1151 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1152 | int reg, i; |
1153 | u32 val; | |
1154 | int cur_pipe; | |
1155 | ||
653e1026 VS |
1156 | /* Primary planes are fixed to pipes on gen4+ */ |
1157 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1158 | reg = DSPCNTR(pipe); |
1159 | val = I915_READ(reg); | |
1160 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1161 | "plane %c assertion failure, should be disabled but not\n", | |
1162 | plane_name(pipe)); | |
19ec1358 | 1163 | return; |
28c05794 | 1164 | } |
19ec1358 | 1165 | |
b24e7179 | 1166 | /* Need to check both planes against the pipe */ |
08e2a7de | 1167 | for_each_pipe(i) { |
b24e7179 JB |
1168 | reg = DSPCNTR(i); |
1169 | val = I915_READ(reg); | |
1170 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1171 | DISPPLANE_SEL_PIPE_SHIFT; | |
1172 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1173 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1174 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1175 | } |
1176 | } | |
1177 | ||
19332d7a JB |
1178 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1179 | enum pipe pipe) | |
1180 | { | |
20674eef | 1181 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1182 | int reg, i; |
1183 | u32 val; | |
1184 | ||
20674eef VS |
1185 | if (IS_VALLEYVIEW(dev)) { |
1186 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1187 | reg = SPCNTR(pipe, i); | |
1188 | val = I915_READ(reg); | |
1189 | WARN((val & SP_ENABLE), | |
1190 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1191 | sprite_name(pipe, i), pipe_name(pipe)); | |
1192 | } | |
1193 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1194 | reg = SPRCTL(pipe); | |
19332d7a | 1195 | val = I915_READ(reg); |
20674eef | 1196 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1197 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1198 | plane_name(pipe), pipe_name(pipe)); |
1199 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1200 | reg = DVSCNTR(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & DVS_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1204 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1205 | } |
1206 | } | |
1207 | ||
92f2584a JB |
1208 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1209 | { | |
1210 | u32 val; | |
1211 | bool enabled; | |
1212 | ||
9d82aa17 ED |
1213 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1214 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1215 | return; | |
1216 | } | |
1217 | ||
92f2584a JB |
1218 | val = I915_READ(PCH_DREF_CONTROL); |
1219 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1220 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1221 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1222 | } | |
1223 | ||
ab9412ba DV |
1224 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1225 | enum pipe pipe) | |
92f2584a JB |
1226 | { |
1227 | int reg; | |
1228 | u32 val; | |
1229 | bool enabled; | |
1230 | ||
ab9412ba | 1231 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1232 | val = I915_READ(reg); |
1233 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1234 | WARN(enabled, |
1235 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1236 | pipe_name(pipe)); | |
92f2584a JB |
1237 | } |
1238 | ||
4e634389 KP |
1239 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1240 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1241 | { |
1242 | if ((val & DP_PORT_EN) == 0) | |
1243 | return false; | |
1244 | ||
1245 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1246 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1247 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1248 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1249 | return false; | |
1250 | } else { | |
1251 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1252 | return false; | |
1253 | } | |
1254 | return true; | |
1255 | } | |
1256 | ||
1519b995 KP |
1257 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1258 | enum pipe pipe, u32 val) | |
1259 | { | |
dc0fa718 | 1260 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1261 | return false; |
1262 | ||
1263 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1264 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1265 | return false; |
1266 | } else { | |
dc0fa718 | 1267 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1268 | return false; |
1269 | } | |
1270 | return true; | |
1271 | } | |
1272 | ||
1273 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1274 | enum pipe pipe, u32 val) | |
1275 | { | |
1276 | if ((val & LVDS_PORT_EN) == 0) | |
1277 | return false; | |
1278 | ||
1279 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1280 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1281 | return false; | |
1282 | } else { | |
1283 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1284 | return false; | |
1285 | } | |
1286 | return true; | |
1287 | } | |
1288 | ||
1289 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1290 | enum pipe pipe, u32 val) | |
1291 | { | |
1292 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1293 | return false; | |
1294 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1295 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1296 | return false; | |
1297 | } else { | |
1298 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1299 | return false; | |
1300 | } | |
1301 | return true; | |
1302 | } | |
1303 | ||
291906f1 | 1304 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1305 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1306 | { |
47a05eca | 1307 | u32 val = I915_READ(reg); |
4e634389 | 1308 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1309 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1310 | reg, pipe_name(pipe)); |
de9a35ab | 1311 | |
75c5da27 DV |
1312 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1313 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1314 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1315 | } |
1316 | ||
1317 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1318 | enum pipe pipe, int reg) | |
1319 | { | |
47a05eca | 1320 | u32 val = I915_READ(reg); |
b70ad586 | 1321 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1322 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1323 | reg, pipe_name(pipe)); |
de9a35ab | 1324 | |
dc0fa718 | 1325 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1326 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1327 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1328 | } |
1329 | ||
1330 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1331 | enum pipe pipe) | |
1332 | { | |
1333 | int reg; | |
1334 | u32 val; | |
291906f1 | 1335 | |
f0575e92 KP |
1336 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1337 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1338 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1339 | |
1340 | reg = PCH_ADPA; | |
1341 | val = I915_READ(reg); | |
b70ad586 | 1342 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1343 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1344 | pipe_name(pipe)); |
291906f1 JB |
1345 | |
1346 | reg = PCH_LVDS; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 | 1351 | |
e2debe91 PZ |
1352 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1353 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1354 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1355 | } |
1356 | ||
40e9cf64 JB |
1357 | static void intel_init_dpio(struct drm_device *dev) |
1358 | { | |
1359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1360 | ||
1361 | if (!IS_VALLEYVIEW(dev)) | |
1362 | return; | |
1363 | ||
e4607fcf | 1364 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
40e9cf64 JB |
1365 | /* |
1366 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1367 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1368 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1369 | * b. The other bits such as sfr settings / modesel may all be set | |
1370 | * to 0. | |
1371 | * | |
1372 | * This should only be done on init and resume from S3 with both | |
1373 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1374 | */ | |
1375 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1376 | } | |
1377 | ||
426115cf | 1378 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1379 | { |
426115cf DV |
1380 | struct drm_device *dev = crtc->base.dev; |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1382 | int reg = DPLL(crtc->pipe); | |
1383 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1384 | |
426115cf | 1385 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1386 | |
1387 | /* No really, not for ILK+ */ | |
1388 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1389 | ||
1390 | /* PLL is protected by panel, make sure we can write it */ | |
1391 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1392 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1393 | |
426115cf DV |
1394 | I915_WRITE(reg, dpll); |
1395 | POSTING_READ(reg); | |
1396 | udelay(150); | |
1397 | ||
1398 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1399 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1400 | ||
1401 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1402 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1403 | |
1404 | /* We do this three times for luck */ | |
426115cf | 1405 | I915_WRITE(reg, dpll); |
87442f73 DV |
1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ | |
426115cf | 1408 | I915_WRITE(reg, dpll); |
87442f73 DV |
1409 | POSTING_READ(reg); |
1410 | udelay(150); /* wait for warmup */ | |
426115cf | 1411 | I915_WRITE(reg, dpll); |
87442f73 DV |
1412 | POSTING_READ(reg); |
1413 | udelay(150); /* wait for warmup */ | |
1414 | } | |
1415 | ||
66e3d5c0 | 1416 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1417 | { |
66e3d5c0 DV |
1418 | struct drm_device *dev = crtc->base.dev; |
1419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1420 | int reg = DPLL(crtc->pipe); | |
1421 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1422 | |
66e3d5c0 | 1423 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1424 | |
63d7bbe9 | 1425 | /* No really, not for ILK+ */ |
87442f73 | 1426 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1427 | |
1428 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1429 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1430 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1431 | |
66e3d5c0 DV |
1432 | I915_WRITE(reg, dpll); |
1433 | ||
1434 | /* Wait for the clocks to stabilize. */ | |
1435 | POSTING_READ(reg); | |
1436 | udelay(150); | |
1437 | ||
1438 | if (INTEL_INFO(dev)->gen >= 4) { | |
1439 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1440 | crtc->config.dpll_hw_state.dpll_md); | |
1441 | } else { | |
1442 | /* The pixel multiplier can only be updated once the | |
1443 | * DPLL is enabled and the clocks are stable. | |
1444 | * | |
1445 | * So write it again. | |
1446 | */ | |
1447 | I915_WRITE(reg, dpll); | |
1448 | } | |
63d7bbe9 JB |
1449 | |
1450 | /* We do this three times for luck */ | |
66e3d5c0 | 1451 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1452 | POSTING_READ(reg); |
1453 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1454 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1455 | POSTING_READ(reg); |
1456 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1457 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1458 | POSTING_READ(reg); |
1459 | udelay(150); /* wait for warmup */ | |
1460 | } | |
1461 | ||
1462 | /** | |
50b44a44 | 1463 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1464 | * @dev_priv: i915 private structure |
1465 | * @pipe: pipe PLL to disable | |
1466 | * | |
1467 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1468 | * | |
1469 | * Note! This is for pre-ILK only. | |
1470 | */ | |
50b44a44 | 1471 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1472 | { |
63d7bbe9 JB |
1473 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1474 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1475 | return; | |
1476 | ||
1477 | /* Make sure the pipe isn't still relying on us */ | |
1478 | assert_pipe_disabled(dev_priv, pipe); | |
1479 | ||
50b44a44 DV |
1480 | I915_WRITE(DPLL(pipe), 0); |
1481 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1482 | } |
1483 | ||
f6071166 JB |
1484 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1485 | { | |
1486 | u32 val = 0; | |
1487 | ||
1488 | /* Make sure the pipe isn't still relying on us */ | |
1489 | assert_pipe_disabled(dev_priv, pipe); | |
1490 | ||
1491 | /* Leave integrated clock source enabled */ | |
1492 | if (pipe == PIPE_B) | |
1493 | val = DPLL_INTEGRATED_CRI_CLK_VLV; | |
1494 | I915_WRITE(DPLL(pipe), val); | |
1495 | POSTING_READ(DPLL(pipe)); | |
1496 | } | |
1497 | ||
e4607fcf CML |
1498 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1499 | struct intel_digital_port *dport) | |
89b667f8 JB |
1500 | { |
1501 | u32 port_mask; | |
1502 | ||
e4607fcf CML |
1503 | switch (dport->port) { |
1504 | case PORT_B: | |
89b667f8 | 1505 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1506 | break; |
1507 | case PORT_C: | |
89b667f8 | 1508 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1509 | break; |
1510 | default: | |
1511 | BUG(); | |
1512 | } | |
89b667f8 JB |
1513 | |
1514 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1515 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
e4607fcf | 1516 | 'B' + dport->port, I915_READ(DPLL(0))); |
89b667f8 JB |
1517 | } |
1518 | ||
92f2584a | 1519 | /** |
e72f9fbf | 1520 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1521 | * @dev_priv: i915 private structure |
1522 | * @pipe: pipe PLL to enable | |
1523 | * | |
1524 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1525 | * drives the transcoder clock. | |
1526 | */ | |
e2b78267 | 1527 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1528 | { |
e2b78267 DV |
1529 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1530 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1531 | |
48da64a8 | 1532 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1533 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1534 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1535 | return; |
1536 | ||
1537 | if (WARN_ON(pll->refcount == 0)) | |
1538 | return; | |
ee7b9f93 | 1539 | |
46edb027 DV |
1540 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1541 | pll->name, pll->active, pll->on, | |
e2b78267 | 1542 | crtc->base.base.id); |
92f2584a | 1543 | |
cdbd2316 DV |
1544 | if (pll->active++) { |
1545 | WARN_ON(!pll->on); | |
e9d6944e | 1546 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1547 | return; |
1548 | } | |
f4a091c7 | 1549 | WARN_ON(pll->on); |
ee7b9f93 | 1550 | |
46edb027 | 1551 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1552 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1553 | pll->on = true; |
92f2584a JB |
1554 | } |
1555 | ||
e2b78267 | 1556 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1557 | { |
e2b78267 DV |
1558 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1559 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1560 | |
92f2584a JB |
1561 | /* PCH only available on ILK+ */ |
1562 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1563 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1564 | return; |
92f2584a | 1565 | |
48da64a8 CW |
1566 | if (WARN_ON(pll->refcount == 0)) |
1567 | return; | |
7a419866 | 1568 | |
46edb027 DV |
1569 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1570 | pll->name, pll->active, pll->on, | |
e2b78267 | 1571 | crtc->base.base.id); |
7a419866 | 1572 | |
48da64a8 | 1573 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1574 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1575 | return; |
1576 | } | |
1577 | ||
e9d6944e | 1578 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1579 | WARN_ON(!pll->on); |
cdbd2316 | 1580 | if (--pll->active) |
7a419866 | 1581 | return; |
ee7b9f93 | 1582 | |
46edb027 | 1583 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1584 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1585 | pll->on = false; |
92f2584a JB |
1586 | } |
1587 | ||
b8a4f404 PZ |
1588 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1589 | enum pipe pipe) | |
040484af | 1590 | { |
23670b32 | 1591 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1592 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1593 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1594 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1595 | |
1596 | /* PCH only available on ILK+ */ | |
1597 | BUG_ON(dev_priv->info->gen < 5); | |
1598 | ||
1599 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1600 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1601 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1602 | |
1603 | /* FDI must be feeding us bits for PCH ports */ | |
1604 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1605 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1606 | ||
23670b32 DV |
1607 | if (HAS_PCH_CPT(dev)) { |
1608 | /* Workaround: Set the timing override bit before enabling the | |
1609 | * pch transcoder. */ | |
1610 | reg = TRANS_CHICKEN2(pipe); | |
1611 | val = I915_READ(reg); | |
1612 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1613 | I915_WRITE(reg, val); | |
59c859d6 | 1614 | } |
23670b32 | 1615 | |
ab9412ba | 1616 | reg = PCH_TRANSCONF(pipe); |
040484af | 1617 | val = I915_READ(reg); |
5f7f726d | 1618 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1619 | |
1620 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1621 | /* | |
1622 | * make the BPC in transcoder be consistent with | |
1623 | * that in pipeconf reg. | |
1624 | */ | |
dfd07d72 DV |
1625 | val &= ~PIPECONF_BPC_MASK; |
1626 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1627 | } |
5f7f726d PZ |
1628 | |
1629 | val &= ~TRANS_INTERLACE_MASK; | |
1630 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1631 | if (HAS_PCH_IBX(dev_priv->dev) && |
1632 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1633 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1634 | else | |
1635 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1636 | else |
1637 | val |= TRANS_PROGRESSIVE; | |
1638 | ||
040484af JB |
1639 | I915_WRITE(reg, val | TRANS_ENABLE); |
1640 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1641 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1642 | } |
1643 | ||
8fb033d7 | 1644 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1645 | enum transcoder cpu_transcoder) |
040484af | 1646 | { |
8fb033d7 | 1647 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1648 | |
1649 | /* PCH only available on ILK+ */ | |
1650 | BUG_ON(dev_priv->info->gen < 5); | |
1651 | ||
8fb033d7 | 1652 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1653 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1654 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1655 | |
223a6fdf PZ |
1656 | /* Workaround: set timing override bit. */ |
1657 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1658 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1659 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1660 | ||
25f3ef11 | 1661 | val = TRANS_ENABLE; |
937bb610 | 1662 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1663 | |
9a76b1c6 PZ |
1664 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1665 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1666 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1667 | else |
1668 | val |= TRANS_PROGRESSIVE; | |
1669 | ||
ab9412ba DV |
1670 | I915_WRITE(LPT_TRANSCONF, val); |
1671 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1672 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1673 | } |
1674 | ||
b8a4f404 PZ |
1675 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1676 | enum pipe pipe) | |
040484af | 1677 | { |
23670b32 DV |
1678 | struct drm_device *dev = dev_priv->dev; |
1679 | uint32_t reg, val; | |
040484af JB |
1680 | |
1681 | /* FDI relies on the transcoder */ | |
1682 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1683 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1684 | ||
291906f1 JB |
1685 | /* Ports must be off as well */ |
1686 | assert_pch_ports_disabled(dev_priv, pipe); | |
1687 | ||
ab9412ba | 1688 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1689 | val = I915_READ(reg); |
1690 | val &= ~TRANS_ENABLE; | |
1691 | I915_WRITE(reg, val); | |
1692 | /* wait for PCH transcoder off, transcoder state */ | |
1693 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1694 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1695 | |
1696 | if (!HAS_PCH_IBX(dev)) { | |
1697 | /* Workaround: Clear the timing override chicken bit again. */ | |
1698 | reg = TRANS_CHICKEN2(pipe); | |
1699 | val = I915_READ(reg); | |
1700 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1701 | I915_WRITE(reg, val); | |
1702 | } | |
040484af JB |
1703 | } |
1704 | ||
ab4d966c | 1705 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1706 | { |
8fb033d7 PZ |
1707 | u32 val; |
1708 | ||
ab9412ba | 1709 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1710 | val &= ~TRANS_ENABLE; |
ab9412ba | 1711 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1712 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1713 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1714 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1715 | |
1716 | /* Workaround: clear timing override bit. */ | |
1717 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1718 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1719 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1720 | } |
1721 | ||
b24e7179 | 1722 | /** |
309cfea8 | 1723 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1724 | * @dev_priv: i915 private structure |
1725 | * @pipe: pipe to enable | |
040484af | 1726 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1727 | * |
1728 | * Enable @pipe, making sure that various hardware specific requirements | |
1729 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1730 | * | |
1731 | * @pipe should be %PIPE_A or %PIPE_B. | |
1732 | * | |
1733 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1734 | * returning. | |
1735 | */ | |
040484af | 1736 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1737 | bool pch_port, bool dsi) |
b24e7179 | 1738 | { |
702e7a56 PZ |
1739 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1740 | pipe); | |
1a240d4d | 1741 | enum pipe pch_transcoder; |
b24e7179 JB |
1742 | int reg; |
1743 | u32 val; | |
1744 | ||
58c6eaa2 | 1745 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1746 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1747 | assert_sprites_disabled(dev_priv, pipe); |
1748 | ||
681e5811 | 1749 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1750 | pch_transcoder = TRANSCODER_A; |
1751 | else | |
1752 | pch_transcoder = pipe; | |
1753 | ||
b24e7179 JB |
1754 | /* |
1755 | * A pipe without a PLL won't actually be able to drive bits from | |
1756 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1757 | * need the check. | |
1758 | */ | |
1759 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1760 | if (dsi) |
1761 | assert_dsi_pll_enabled(dev_priv); | |
1762 | else | |
1763 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1764 | else { |
1765 | if (pch_port) { | |
1766 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1767 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1768 | assert_fdi_tx_pll_enabled(dev_priv, |
1769 | (enum pipe) cpu_transcoder); | |
040484af JB |
1770 | } |
1771 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1772 | } | |
b24e7179 | 1773 | |
702e7a56 | 1774 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1775 | val = I915_READ(reg); |
00d70b15 CW |
1776 | if (val & PIPECONF_ENABLE) |
1777 | return; | |
1778 | ||
1779 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1780 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1781 | } | |
1782 | ||
1783 | /** | |
309cfea8 | 1784 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1785 | * @dev_priv: i915 private structure |
1786 | * @pipe: pipe to disable | |
1787 | * | |
1788 | * Disable @pipe, making sure that various hardware specific requirements | |
1789 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1790 | * | |
1791 | * @pipe should be %PIPE_A or %PIPE_B. | |
1792 | * | |
1793 | * Will wait until the pipe has shut down before returning. | |
1794 | */ | |
1795 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1796 | enum pipe pipe) | |
1797 | { | |
702e7a56 PZ |
1798 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1799 | pipe); | |
b24e7179 JB |
1800 | int reg; |
1801 | u32 val; | |
1802 | ||
1803 | /* | |
1804 | * Make sure planes won't keep trying to pump pixels to us, | |
1805 | * or we might hang the display. | |
1806 | */ | |
1807 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1808 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1809 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1810 | |
1811 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1812 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1813 | return; | |
1814 | ||
702e7a56 | 1815 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1816 | val = I915_READ(reg); |
00d70b15 CW |
1817 | if ((val & PIPECONF_ENABLE) == 0) |
1818 | return; | |
1819 | ||
1820 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1821 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1822 | } | |
1823 | ||
d74362c9 KP |
1824 | /* |
1825 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1826 | * trigger in order to latch. The display address reg provides this. | |
1827 | */ | |
1dba99f4 VS |
1828 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1829 | enum plane plane) | |
d74362c9 | 1830 | { |
1dba99f4 VS |
1831 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1832 | ||
1833 | I915_WRITE(reg, I915_READ(reg)); | |
1834 | POSTING_READ(reg); | |
d74362c9 KP |
1835 | } |
1836 | ||
b24e7179 | 1837 | /** |
d1de00ef | 1838 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1839 | * @dev_priv: i915 private structure |
1840 | * @plane: plane to enable | |
1841 | * @pipe: pipe being fed | |
1842 | * | |
1843 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1844 | */ | |
d1de00ef VS |
1845 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1846 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1847 | { |
939c2fe8 VS |
1848 | struct intel_crtc *intel_crtc = |
1849 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1850 | int reg; |
1851 | u32 val; | |
1852 | ||
1853 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1854 | assert_pipe_enabled(dev_priv, pipe); | |
1855 | ||
4c445e0e | 1856 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1857 | |
4c445e0e | 1858 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1859 | |
b24e7179 JB |
1860 | reg = DSPCNTR(plane); |
1861 | val = I915_READ(reg); | |
00d70b15 CW |
1862 | if (val & DISPLAY_PLANE_ENABLE) |
1863 | return; | |
1864 | ||
1865 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1866 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1867 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1868 | } | |
1869 | ||
b24e7179 | 1870 | /** |
d1de00ef | 1871 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1872 | * @dev_priv: i915 private structure |
1873 | * @plane: plane to disable | |
1874 | * @pipe: pipe consuming the data | |
1875 | * | |
1876 | * Disable @plane; should be an independent operation. | |
1877 | */ | |
d1de00ef VS |
1878 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1879 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1880 | { |
939c2fe8 VS |
1881 | struct intel_crtc *intel_crtc = |
1882 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1883 | int reg; |
1884 | u32 val; | |
1885 | ||
4c445e0e | 1886 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1887 | |
4c445e0e | 1888 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1889 | |
b24e7179 JB |
1890 | reg = DSPCNTR(plane); |
1891 | val = I915_READ(reg); | |
00d70b15 CW |
1892 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1893 | return; | |
1894 | ||
1895 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1896 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1897 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1898 | } | |
1899 | ||
693db184 CW |
1900 | static bool need_vtd_wa(struct drm_device *dev) |
1901 | { | |
1902 | #ifdef CONFIG_INTEL_IOMMU | |
1903 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1904 | return true; | |
1905 | #endif | |
1906 | return false; | |
1907 | } | |
1908 | ||
127bd2ac | 1909 | int |
48b956c5 | 1910 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1911 | struct drm_i915_gem_object *obj, |
919926ae | 1912 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1913 | { |
ce453d81 | 1914 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1915 | u32 alignment; |
1916 | int ret; | |
1917 | ||
05394f39 | 1918 | switch (obj->tiling_mode) { |
6b95a207 | 1919 | case I915_TILING_NONE: |
534843da CW |
1920 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1921 | alignment = 128 * 1024; | |
a6c45cf0 | 1922 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1923 | alignment = 4 * 1024; |
1924 | else | |
1925 | alignment = 64 * 1024; | |
6b95a207 KH |
1926 | break; |
1927 | case I915_TILING_X: | |
1928 | /* pin() will align the object as required by fence */ | |
1929 | alignment = 0; | |
1930 | break; | |
1931 | case I915_TILING_Y: | |
80075d49 | 1932 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1933 | return -EINVAL; |
1934 | default: | |
1935 | BUG(); | |
1936 | } | |
1937 | ||
693db184 CW |
1938 | /* Note that the w/a also requires 64 PTE of padding following the |
1939 | * bo. We currently fill all unused PTE with the shadow page and so | |
1940 | * we should always have valid PTE following the scanout preventing | |
1941 | * the VT-d warning. | |
1942 | */ | |
1943 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1944 | alignment = 256 * 1024; | |
1945 | ||
ce453d81 | 1946 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1947 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1948 | if (ret) |
ce453d81 | 1949 | goto err_interruptible; |
6b95a207 KH |
1950 | |
1951 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1952 | * fence, whereas 965+ only requires a fence if using | |
1953 | * framebuffer compression. For simplicity, we always install | |
1954 | * a fence as the cost is not that onerous. | |
1955 | */ | |
06d98131 | 1956 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1957 | if (ret) |
1958 | goto err_unpin; | |
1690e1eb | 1959 | |
9a5a53b3 | 1960 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1961 | |
ce453d81 | 1962 | dev_priv->mm.interruptible = true; |
6b95a207 | 1963 | return 0; |
48b956c5 CW |
1964 | |
1965 | err_unpin: | |
cc98b413 | 1966 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1967 | err_interruptible: |
1968 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1969 | return ret; |
6b95a207 KH |
1970 | } |
1971 | ||
1690e1eb CW |
1972 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1973 | { | |
1974 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1975 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1976 | } |
1977 | ||
c2c75131 DV |
1978 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1979 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1980 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1981 | unsigned int tiling_mode, | |
1982 | unsigned int cpp, | |
1983 | unsigned int pitch) | |
c2c75131 | 1984 | { |
bc752862 CW |
1985 | if (tiling_mode != I915_TILING_NONE) { |
1986 | unsigned int tile_rows, tiles; | |
c2c75131 | 1987 | |
bc752862 CW |
1988 | tile_rows = *y / 8; |
1989 | *y %= 8; | |
c2c75131 | 1990 | |
bc752862 CW |
1991 | tiles = *x / (512/cpp); |
1992 | *x %= 512/cpp; | |
1993 | ||
1994 | return tile_rows * pitch * 8 + tiles * 4096; | |
1995 | } else { | |
1996 | unsigned int offset; | |
1997 | ||
1998 | offset = *y * pitch + *x * cpp; | |
1999 | *y = 0; | |
2000 | *x = (offset & 4095) / cpp; | |
2001 | return offset & -4096; | |
2002 | } | |
c2c75131 DV |
2003 | } |
2004 | ||
17638cd6 JB |
2005 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2006 | int x, int y) | |
81255565 JB |
2007 | { |
2008 | struct drm_device *dev = crtc->dev; | |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2011 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2012 | struct drm_i915_gem_object *obj; |
81255565 | 2013 | int plane = intel_crtc->plane; |
e506a0c6 | 2014 | unsigned long linear_offset; |
81255565 | 2015 | u32 dspcntr; |
5eddb70b | 2016 | u32 reg; |
81255565 JB |
2017 | |
2018 | switch (plane) { | |
2019 | case 0: | |
2020 | case 1: | |
2021 | break; | |
2022 | default: | |
84f44ce7 | 2023 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2024 | return -EINVAL; |
2025 | } | |
2026 | ||
2027 | intel_fb = to_intel_framebuffer(fb); | |
2028 | obj = intel_fb->obj; | |
81255565 | 2029 | |
5eddb70b CW |
2030 | reg = DSPCNTR(plane); |
2031 | dspcntr = I915_READ(reg); | |
81255565 JB |
2032 | /* Mask out pixel format bits in case we change it */ |
2033 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2034 | switch (fb->pixel_format) { |
2035 | case DRM_FORMAT_C8: | |
81255565 JB |
2036 | dspcntr |= DISPPLANE_8BPP; |
2037 | break; | |
57779d06 VS |
2038 | case DRM_FORMAT_XRGB1555: |
2039 | case DRM_FORMAT_ARGB1555: | |
2040 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2041 | break; |
57779d06 VS |
2042 | case DRM_FORMAT_RGB565: |
2043 | dspcntr |= DISPPLANE_BGRX565; | |
2044 | break; | |
2045 | case DRM_FORMAT_XRGB8888: | |
2046 | case DRM_FORMAT_ARGB8888: | |
2047 | dspcntr |= DISPPLANE_BGRX888; | |
2048 | break; | |
2049 | case DRM_FORMAT_XBGR8888: | |
2050 | case DRM_FORMAT_ABGR8888: | |
2051 | dspcntr |= DISPPLANE_RGBX888; | |
2052 | break; | |
2053 | case DRM_FORMAT_XRGB2101010: | |
2054 | case DRM_FORMAT_ARGB2101010: | |
2055 | dspcntr |= DISPPLANE_BGRX101010; | |
2056 | break; | |
2057 | case DRM_FORMAT_XBGR2101010: | |
2058 | case DRM_FORMAT_ABGR2101010: | |
2059 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2060 | break; |
2061 | default: | |
baba133a | 2062 | BUG(); |
81255565 | 2063 | } |
57779d06 | 2064 | |
a6c45cf0 | 2065 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2066 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2067 | dspcntr |= DISPPLANE_TILED; |
2068 | else | |
2069 | dspcntr &= ~DISPPLANE_TILED; | |
2070 | } | |
2071 | ||
de1aa629 VS |
2072 | if (IS_G4X(dev)) |
2073 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2074 | ||
5eddb70b | 2075 | I915_WRITE(reg, dspcntr); |
81255565 | 2076 | |
e506a0c6 | 2077 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2078 | |
c2c75131 DV |
2079 | if (INTEL_INFO(dev)->gen >= 4) { |
2080 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2081 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2082 | fb->bits_per_pixel / 8, | |
2083 | fb->pitches[0]); | |
c2c75131 DV |
2084 | linear_offset -= intel_crtc->dspaddr_offset; |
2085 | } else { | |
e506a0c6 | 2086 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2087 | } |
e506a0c6 | 2088 | |
f343c5f6 BW |
2089 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2090 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2091 | fb->pitches[0]); | |
01f2c773 | 2092 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2093 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2094 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2095 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2096 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2097 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2098 | } else |
f343c5f6 | 2099 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2100 | POSTING_READ(reg); |
81255565 | 2101 | |
17638cd6 JB |
2102 | return 0; |
2103 | } | |
2104 | ||
2105 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2106 | struct drm_framebuffer *fb, int x, int y) | |
2107 | { | |
2108 | struct drm_device *dev = crtc->dev; | |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2111 | struct intel_framebuffer *intel_fb; | |
2112 | struct drm_i915_gem_object *obj; | |
2113 | int plane = intel_crtc->plane; | |
e506a0c6 | 2114 | unsigned long linear_offset; |
17638cd6 JB |
2115 | u32 dspcntr; |
2116 | u32 reg; | |
2117 | ||
2118 | switch (plane) { | |
2119 | case 0: | |
2120 | case 1: | |
27f8227b | 2121 | case 2: |
17638cd6 JB |
2122 | break; |
2123 | default: | |
84f44ce7 | 2124 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2125 | return -EINVAL; |
2126 | } | |
2127 | ||
2128 | intel_fb = to_intel_framebuffer(fb); | |
2129 | obj = intel_fb->obj; | |
2130 | ||
2131 | reg = DSPCNTR(plane); | |
2132 | dspcntr = I915_READ(reg); | |
2133 | /* Mask out pixel format bits in case we change it */ | |
2134 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2135 | switch (fb->pixel_format) { |
2136 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2137 | dspcntr |= DISPPLANE_8BPP; |
2138 | break; | |
57779d06 VS |
2139 | case DRM_FORMAT_RGB565: |
2140 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2141 | break; |
57779d06 VS |
2142 | case DRM_FORMAT_XRGB8888: |
2143 | case DRM_FORMAT_ARGB8888: | |
2144 | dspcntr |= DISPPLANE_BGRX888; | |
2145 | break; | |
2146 | case DRM_FORMAT_XBGR8888: | |
2147 | case DRM_FORMAT_ABGR8888: | |
2148 | dspcntr |= DISPPLANE_RGBX888; | |
2149 | break; | |
2150 | case DRM_FORMAT_XRGB2101010: | |
2151 | case DRM_FORMAT_ARGB2101010: | |
2152 | dspcntr |= DISPPLANE_BGRX101010; | |
2153 | break; | |
2154 | case DRM_FORMAT_XBGR2101010: | |
2155 | case DRM_FORMAT_ABGR2101010: | |
2156 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2157 | break; |
2158 | default: | |
baba133a | 2159 | BUG(); |
17638cd6 JB |
2160 | } |
2161 | ||
2162 | if (obj->tiling_mode != I915_TILING_NONE) | |
2163 | dspcntr |= DISPPLANE_TILED; | |
2164 | else | |
2165 | dspcntr &= ~DISPPLANE_TILED; | |
2166 | ||
b42c6009 | 2167 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2168 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2169 | else | |
2170 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2171 | |
2172 | I915_WRITE(reg, dspcntr); | |
2173 | ||
e506a0c6 | 2174 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2175 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2176 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2177 | fb->bits_per_pixel / 8, | |
2178 | fb->pitches[0]); | |
c2c75131 | 2179 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2180 | |
f343c5f6 BW |
2181 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2182 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2183 | fb->pitches[0]); | |
01f2c773 | 2184 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2185 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2186 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
b3dc685e | 2187 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2188 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2189 | } else { | |
2190 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2191 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2192 | } | |
17638cd6 JB |
2193 | POSTING_READ(reg); |
2194 | ||
2195 | return 0; | |
2196 | } | |
2197 | ||
2198 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2199 | static int | |
2200 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2201 | int x, int y, enum mode_set_atomic state) | |
2202 | { | |
2203 | struct drm_device *dev = crtc->dev; | |
2204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2205 | |
6b8e6ed0 CW |
2206 | if (dev_priv->display.disable_fbc) |
2207 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2208 | intel_increase_pllclock(crtc); |
81255565 | 2209 | |
6b8e6ed0 | 2210 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2211 | } |
2212 | ||
96a02917 VS |
2213 | void intel_display_handle_reset(struct drm_device *dev) |
2214 | { | |
2215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2216 | struct drm_crtc *crtc; | |
2217 | ||
2218 | /* | |
2219 | * Flips in the rings have been nuked by the reset, | |
2220 | * so complete all pending flips so that user space | |
2221 | * will get its events and not get stuck. | |
2222 | * | |
2223 | * Also update the base address of all primary | |
2224 | * planes to the the last fb to make sure we're | |
2225 | * showing the correct fb after a reset. | |
2226 | * | |
2227 | * Need to make two loops over the crtcs so that we | |
2228 | * don't try to grab a crtc mutex before the | |
2229 | * pending_flip_queue really got woken up. | |
2230 | */ | |
2231 | ||
2232 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2234 | enum plane plane = intel_crtc->plane; | |
2235 | ||
2236 | intel_prepare_page_flip(dev, plane); | |
2237 | intel_finish_page_flip_plane(dev, plane); | |
2238 | } | |
2239 | ||
2240 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2242 | ||
2243 | mutex_lock(&crtc->mutex); | |
2244 | if (intel_crtc->active) | |
2245 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2246 | crtc->x, crtc->y); | |
2247 | mutex_unlock(&crtc->mutex); | |
2248 | } | |
2249 | } | |
2250 | ||
14667a4b CW |
2251 | static int |
2252 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2253 | { | |
2254 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2255 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2256 | bool was_interruptible = dev_priv->mm.interruptible; | |
2257 | int ret; | |
2258 | ||
14667a4b CW |
2259 | /* Big Hammer, we also need to ensure that any pending |
2260 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2261 | * current scanout is retired before unpinning the old | |
2262 | * framebuffer. | |
2263 | * | |
2264 | * This should only fail upon a hung GPU, in which case we | |
2265 | * can safely continue. | |
2266 | */ | |
2267 | dev_priv->mm.interruptible = false; | |
2268 | ret = i915_gem_object_finish_gpu(obj); | |
2269 | dev_priv->mm.interruptible = was_interruptible; | |
2270 | ||
2271 | return ret; | |
2272 | } | |
2273 | ||
198598d0 VS |
2274 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2275 | { | |
2276 | struct drm_device *dev = crtc->dev; | |
2277 | struct drm_i915_master_private *master_priv; | |
2278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2279 | ||
2280 | if (!dev->primary->master) | |
2281 | return; | |
2282 | ||
2283 | master_priv = dev->primary->master->driver_priv; | |
2284 | if (!master_priv->sarea_priv) | |
2285 | return; | |
2286 | ||
2287 | switch (intel_crtc->pipe) { | |
2288 | case 0: | |
2289 | master_priv->sarea_priv->pipeA_x = x; | |
2290 | master_priv->sarea_priv->pipeA_y = y; | |
2291 | break; | |
2292 | case 1: | |
2293 | master_priv->sarea_priv->pipeB_x = x; | |
2294 | master_priv->sarea_priv->pipeB_y = y; | |
2295 | break; | |
2296 | default: | |
2297 | break; | |
2298 | } | |
2299 | } | |
2300 | ||
5c3b82e2 | 2301 | static int |
3c4fdcfb | 2302 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2303 | struct drm_framebuffer *fb) |
79e53945 JB |
2304 | { |
2305 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2306 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2307 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2308 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2309 | int ret; |
79e53945 JB |
2310 | |
2311 | /* no fb bound */ | |
94352cf9 | 2312 | if (!fb) { |
a5071c2f | 2313 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2314 | return 0; |
2315 | } | |
2316 | ||
7eb552ae | 2317 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2318 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2319 | plane_name(intel_crtc->plane), | |
2320 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2321 | return -EINVAL; |
79e53945 JB |
2322 | } |
2323 | ||
5c3b82e2 | 2324 | mutex_lock(&dev->struct_mutex); |
265db958 | 2325 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2326 | to_intel_framebuffer(fb)->obj, |
919926ae | 2327 | NULL); |
5c3b82e2 CW |
2328 | if (ret != 0) { |
2329 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2330 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2331 | return ret; |
2332 | } | |
79e53945 | 2333 | |
bb2043de DL |
2334 | /* |
2335 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2336 | * that in compute_mode_changes we check the native mode (not the pfit | |
2337 | * mode) to see if we can flip rather than do a full mode set. In the | |
2338 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2339 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2340 | * sized surface. | |
2341 | * | |
2342 | * To fix this properly, we need to hoist the checks up into | |
2343 | * compute_mode_changes (or above), check the actual pfit state and | |
2344 | * whether the platform allows pfit disable with pipe active, and only | |
2345 | * then update the pipesrc and pfit state, even on the flip path. | |
2346 | */ | |
4d6a3e63 | 2347 | if (i915_fastboot) { |
d7bf63f2 DL |
2348 | const struct drm_display_mode *adjusted_mode = |
2349 | &intel_crtc->config.adjusted_mode; | |
2350 | ||
4d6a3e63 | 2351 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2352 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2353 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2354 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2355 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2356 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2357 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2358 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2359 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2360 | } | |
2361 | } | |
2362 | ||
94352cf9 | 2363 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2364 | if (ret) { |
94352cf9 | 2365 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2366 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2367 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2368 | return ret; |
79e53945 | 2369 | } |
3c4fdcfb | 2370 | |
94352cf9 DV |
2371 | old_fb = crtc->fb; |
2372 | crtc->fb = fb; | |
6c4c86f5 DV |
2373 | crtc->x = x; |
2374 | crtc->y = y; | |
94352cf9 | 2375 | |
b7f1de28 | 2376 | if (old_fb) { |
d7697eea DV |
2377 | if (intel_crtc->active && old_fb != fb) |
2378 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2379 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2380 | } |
652c393a | 2381 | |
6b8e6ed0 | 2382 | intel_update_fbc(dev); |
4906557e | 2383 | intel_edp_psr_update(dev); |
5c3b82e2 | 2384 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2385 | |
198598d0 | 2386 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2387 | |
2388 | return 0; | |
79e53945 JB |
2389 | } |
2390 | ||
5e84e1a4 ZW |
2391 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2392 | { | |
2393 | struct drm_device *dev = crtc->dev; | |
2394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2396 | int pipe = intel_crtc->pipe; | |
2397 | u32 reg, temp; | |
2398 | ||
2399 | /* enable normal train */ | |
2400 | reg = FDI_TX_CTL(pipe); | |
2401 | temp = I915_READ(reg); | |
61e499bf | 2402 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2403 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2404 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2405 | } else { |
2406 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2407 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2408 | } |
5e84e1a4 ZW |
2409 | I915_WRITE(reg, temp); |
2410 | ||
2411 | reg = FDI_RX_CTL(pipe); | |
2412 | temp = I915_READ(reg); | |
2413 | if (HAS_PCH_CPT(dev)) { | |
2414 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2415 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2416 | } else { | |
2417 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2418 | temp |= FDI_LINK_TRAIN_NONE; | |
2419 | } | |
2420 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2421 | ||
2422 | /* wait one idle pattern time */ | |
2423 | POSTING_READ(reg); | |
2424 | udelay(1000); | |
357555c0 JB |
2425 | |
2426 | /* IVB wants error correction enabled */ | |
2427 | if (IS_IVYBRIDGE(dev)) | |
2428 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2429 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2430 | } |
2431 | ||
1fbc0d78 | 2432 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2433 | { |
1fbc0d78 DV |
2434 | return crtc->base.enabled && crtc->active && |
2435 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2436 | } |
2437 | ||
01a415fd DV |
2438 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2439 | { | |
2440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2441 | struct intel_crtc *pipe_B_crtc = | |
2442 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2443 | struct intel_crtc *pipe_C_crtc = | |
2444 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2445 | uint32_t temp; | |
2446 | ||
1e833f40 DV |
2447 | /* |
2448 | * When everything is off disable fdi C so that we could enable fdi B | |
2449 | * with all lanes. Note that we don't care about enabled pipes without | |
2450 | * an enabled pch encoder. | |
2451 | */ | |
2452 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2453 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2454 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2455 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2456 | ||
2457 | temp = I915_READ(SOUTH_CHICKEN1); | |
2458 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2459 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2460 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2461 | } | |
2462 | } | |
2463 | ||
8db9d77b ZW |
2464 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2465 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2466 | { | |
2467 | struct drm_device *dev = crtc->dev; | |
2468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2470 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2471 | int plane = intel_crtc->plane; |
5eddb70b | 2472 | u32 reg, temp, tries; |
8db9d77b | 2473 | |
0fc932b8 JB |
2474 | /* FDI needs bits from pipe & plane first */ |
2475 | assert_pipe_enabled(dev_priv, pipe); | |
2476 | assert_plane_enabled(dev_priv, plane); | |
2477 | ||
e1a44743 AJ |
2478 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2479 | for train result */ | |
5eddb70b CW |
2480 | reg = FDI_RX_IMR(pipe); |
2481 | temp = I915_READ(reg); | |
e1a44743 AJ |
2482 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2483 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2484 | I915_WRITE(reg, temp); |
2485 | I915_READ(reg); | |
e1a44743 AJ |
2486 | udelay(150); |
2487 | ||
8db9d77b | 2488 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2489 | reg = FDI_TX_CTL(pipe); |
2490 | temp = I915_READ(reg); | |
627eb5a3 DV |
2491 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2492 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2493 | temp &= ~FDI_LINK_TRAIN_NONE; |
2494 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2495 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2496 | |
5eddb70b CW |
2497 | reg = FDI_RX_CTL(pipe); |
2498 | temp = I915_READ(reg); | |
8db9d77b ZW |
2499 | temp &= ~FDI_LINK_TRAIN_NONE; |
2500 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2501 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2502 | ||
2503 | POSTING_READ(reg); | |
8db9d77b ZW |
2504 | udelay(150); |
2505 | ||
5b2adf89 | 2506 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2507 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2508 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2509 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2510 | |
5eddb70b | 2511 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2512 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2513 | temp = I915_READ(reg); |
8db9d77b ZW |
2514 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2515 | ||
2516 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2517 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2518 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2519 | break; |
2520 | } | |
8db9d77b | 2521 | } |
e1a44743 | 2522 | if (tries == 5) |
5eddb70b | 2523 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2524 | |
2525 | /* Train 2 */ | |
5eddb70b CW |
2526 | reg = FDI_TX_CTL(pipe); |
2527 | temp = I915_READ(reg); | |
8db9d77b ZW |
2528 | temp &= ~FDI_LINK_TRAIN_NONE; |
2529 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2530 | I915_WRITE(reg, temp); |
8db9d77b | 2531 | |
5eddb70b CW |
2532 | reg = FDI_RX_CTL(pipe); |
2533 | temp = I915_READ(reg); | |
8db9d77b ZW |
2534 | temp &= ~FDI_LINK_TRAIN_NONE; |
2535 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2536 | I915_WRITE(reg, temp); |
8db9d77b | 2537 | |
5eddb70b CW |
2538 | POSTING_READ(reg); |
2539 | udelay(150); | |
8db9d77b | 2540 | |
5eddb70b | 2541 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2542 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2543 | temp = I915_READ(reg); |
8db9d77b ZW |
2544 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2545 | ||
2546 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2547 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2548 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2549 | break; | |
2550 | } | |
8db9d77b | 2551 | } |
e1a44743 | 2552 | if (tries == 5) |
5eddb70b | 2553 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2554 | |
2555 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2556 | |
8db9d77b ZW |
2557 | } |
2558 | ||
0206e353 | 2559 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2560 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2561 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2562 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2563 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2564 | }; | |
2565 | ||
2566 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2567 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2568 | { | |
2569 | struct drm_device *dev = crtc->dev; | |
2570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2572 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2573 | u32 reg, temp, i, retry; |
8db9d77b | 2574 | |
e1a44743 AJ |
2575 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2576 | for train result */ | |
5eddb70b CW |
2577 | reg = FDI_RX_IMR(pipe); |
2578 | temp = I915_READ(reg); | |
e1a44743 AJ |
2579 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2580 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2581 | I915_WRITE(reg, temp); |
2582 | ||
2583 | POSTING_READ(reg); | |
e1a44743 AJ |
2584 | udelay(150); |
2585 | ||
8db9d77b | 2586 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2587 | reg = FDI_TX_CTL(pipe); |
2588 | temp = I915_READ(reg); | |
627eb5a3 DV |
2589 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2590 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2591 | temp &= ~FDI_LINK_TRAIN_NONE; |
2592 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2593 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2594 | /* SNB-B */ | |
2595 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2596 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2597 | |
d74cf324 DV |
2598 | I915_WRITE(FDI_RX_MISC(pipe), |
2599 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2600 | ||
5eddb70b CW |
2601 | reg = FDI_RX_CTL(pipe); |
2602 | temp = I915_READ(reg); | |
8db9d77b ZW |
2603 | if (HAS_PCH_CPT(dev)) { |
2604 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2605 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2606 | } else { | |
2607 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2608 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2609 | } | |
5eddb70b CW |
2610 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2611 | ||
2612 | POSTING_READ(reg); | |
8db9d77b ZW |
2613 | udelay(150); |
2614 | ||
0206e353 | 2615 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2616 | reg = FDI_TX_CTL(pipe); |
2617 | temp = I915_READ(reg); | |
8db9d77b ZW |
2618 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2619 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2620 | I915_WRITE(reg, temp); |
2621 | ||
2622 | POSTING_READ(reg); | |
8db9d77b ZW |
2623 | udelay(500); |
2624 | ||
fa37d39e SP |
2625 | for (retry = 0; retry < 5; retry++) { |
2626 | reg = FDI_RX_IIR(pipe); | |
2627 | temp = I915_READ(reg); | |
2628 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2629 | if (temp & FDI_RX_BIT_LOCK) { | |
2630 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2631 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2632 | break; | |
2633 | } | |
2634 | udelay(50); | |
8db9d77b | 2635 | } |
fa37d39e SP |
2636 | if (retry < 5) |
2637 | break; | |
8db9d77b ZW |
2638 | } |
2639 | if (i == 4) | |
5eddb70b | 2640 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2641 | |
2642 | /* Train 2 */ | |
5eddb70b CW |
2643 | reg = FDI_TX_CTL(pipe); |
2644 | temp = I915_READ(reg); | |
8db9d77b ZW |
2645 | temp &= ~FDI_LINK_TRAIN_NONE; |
2646 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2647 | if (IS_GEN6(dev)) { | |
2648 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2649 | /* SNB-B */ | |
2650 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2651 | } | |
5eddb70b | 2652 | I915_WRITE(reg, temp); |
8db9d77b | 2653 | |
5eddb70b CW |
2654 | reg = FDI_RX_CTL(pipe); |
2655 | temp = I915_READ(reg); | |
8db9d77b ZW |
2656 | if (HAS_PCH_CPT(dev)) { |
2657 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2658 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2659 | } else { | |
2660 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2661 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2662 | } | |
5eddb70b CW |
2663 | I915_WRITE(reg, temp); |
2664 | ||
2665 | POSTING_READ(reg); | |
8db9d77b ZW |
2666 | udelay(150); |
2667 | ||
0206e353 | 2668 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2669 | reg = FDI_TX_CTL(pipe); |
2670 | temp = I915_READ(reg); | |
8db9d77b ZW |
2671 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2672 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2673 | I915_WRITE(reg, temp); |
2674 | ||
2675 | POSTING_READ(reg); | |
8db9d77b ZW |
2676 | udelay(500); |
2677 | ||
fa37d39e SP |
2678 | for (retry = 0; retry < 5; retry++) { |
2679 | reg = FDI_RX_IIR(pipe); | |
2680 | temp = I915_READ(reg); | |
2681 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2682 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2683 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2684 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2685 | break; | |
2686 | } | |
2687 | udelay(50); | |
8db9d77b | 2688 | } |
fa37d39e SP |
2689 | if (retry < 5) |
2690 | break; | |
8db9d77b ZW |
2691 | } |
2692 | if (i == 4) | |
5eddb70b | 2693 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2694 | |
2695 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2696 | } | |
2697 | ||
357555c0 JB |
2698 | /* Manual link training for Ivy Bridge A0 parts */ |
2699 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2700 | { | |
2701 | struct drm_device *dev = crtc->dev; | |
2702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2704 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2705 | u32 reg, temp, i, j; |
357555c0 JB |
2706 | |
2707 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2708 | for train result */ | |
2709 | reg = FDI_RX_IMR(pipe); | |
2710 | temp = I915_READ(reg); | |
2711 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2712 | temp &= ~FDI_RX_BIT_LOCK; | |
2713 | I915_WRITE(reg, temp); | |
2714 | ||
2715 | POSTING_READ(reg); | |
2716 | udelay(150); | |
2717 | ||
01a415fd DV |
2718 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2719 | I915_READ(FDI_RX_IIR(pipe))); | |
2720 | ||
139ccd3f JB |
2721 | /* Try each vswing and preemphasis setting twice before moving on */ |
2722 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2723 | /* disable first in case we need to retry */ | |
2724 | reg = FDI_TX_CTL(pipe); | |
2725 | temp = I915_READ(reg); | |
2726 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2727 | temp &= ~FDI_TX_ENABLE; | |
2728 | I915_WRITE(reg, temp); | |
357555c0 | 2729 | |
139ccd3f JB |
2730 | reg = FDI_RX_CTL(pipe); |
2731 | temp = I915_READ(reg); | |
2732 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2733 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2734 | temp &= ~FDI_RX_ENABLE; | |
2735 | I915_WRITE(reg, temp); | |
357555c0 | 2736 | |
139ccd3f | 2737 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2738 | reg = FDI_TX_CTL(pipe); |
2739 | temp = I915_READ(reg); | |
139ccd3f JB |
2740 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2741 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2742 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2743 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2744 | temp |= snb_b_fdi_train_param[j/2]; |
2745 | temp |= FDI_COMPOSITE_SYNC; | |
2746 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2747 | |
139ccd3f JB |
2748 | I915_WRITE(FDI_RX_MISC(pipe), |
2749 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2750 | |
139ccd3f | 2751 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2752 | temp = I915_READ(reg); |
139ccd3f JB |
2753 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2754 | temp |= FDI_COMPOSITE_SYNC; | |
2755 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2756 | |
139ccd3f JB |
2757 | POSTING_READ(reg); |
2758 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2759 | |
139ccd3f JB |
2760 | for (i = 0; i < 4; i++) { |
2761 | reg = FDI_RX_IIR(pipe); | |
2762 | temp = I915_READ(reg); | |
2763 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2764 | |
139ccd3f JB |
2765 | if (temp & FDI_RX_BIT_LOCK || |
2766 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2767 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2768 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2769 | i); | |
2770 | break; | |
2771 | } | |
2772 | udelay(1); /* should be 0.5us */ | |
2773 | } | |
2774 | if (i == 4) { | |
2775 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2776 | continue; | |
2777 | } | |
357555c0 | 2778 | |
139ccd3f | 2779 | /* Train 2 */ |
357555c0 JB |
2780 | reg = FDI_TX_CTL(pipe); |
2781 | temp = I915_READ(reg); | |
139ccd3f JB |
2782 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2783 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2784 | I915_WRITE(reg, temp); | |
2785 | ||
2786 | reg = FDI_RX_CTL(pipe); | |
2787 | temp = I915_READ(reg); | |
2788 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2789 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2790 | I915_WRITE(reg, temp); |
2791 | ||
2792 | POSTING_READ(reg); | |
139ccd3f | 2793 | udelay(2); /* should be 1.5us */ |
357555c0 | 2794 | |
139ccd3f JB |
2795 | for (i = 0; i < 4; i++) { |
2796 | reg = FDI_RX_IIR(pipe); | |
2797 | temp = I915_READ(reg); | |
2798 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2799 | |
139ccd3f JB |
2800 | if (temp & FDI_RX_SYMBOL_LOCK || |
2801 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2802 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2803 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2804 | i); | |
2805 | goto train_done; | |
2806 | } | |
2807 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2808 | } |
139ccd3f JB |
2809 | if (i == 4) |
2810 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2811 | } |
357555c0 | 2812 | |
139ccd3f | 2813 | train_done: |
357555c0 JB |
2814 | DRM_DEBUG_KMS("FDI train done.\n"); |
2815 | } | |
2816 | ||
88cefb6c | 2817 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2818 | { |
88cefb6c | 2819 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2820 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2821 | int pipe = intel_crtc->pipe; |
5eddb70b | 2822 | u32 reg, temp; |
79e53945 | 2823 | |
c64e311e | 2824 | |
c98e9dcf | 2825 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2826 | reg = FDI_RX_CTL(pipe); |
2827 | temp = I915_READ(reg); | |
627eb5a3 DV |
2828 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2829 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2830 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2831 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2832 | ||
2833 | POSTING_READ(reg); | |
c98e9dcf JB |
2834 | udelay(200); |
2835 | ||
2836 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2837 | temp = I915_READ(reg); |
2838 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2839 | ||
2840 | POSTING_READ(reg); | |
c98e9dcf JB |
2841 | udelay(200); |
2842 | ||
20749730 PZ |
2843 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2844 | reg = FDI_TX_CTL(pipe); | |
2845 | temp = I915_READ(reg); | |
2846 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2847 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2848 | |
20749730 PZ |
2849 | POSTING_READ(reg); |
2850 | udelay(100); | |
6be4a607 | 2851 | } |
0e23b99d JB |
2852 | } |
2853 | ||
88cefb6c DV |
2854 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2855 | { | |
2856 | struct drm_device *dev = intel_crtc->base.dev; | |
2857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2858 | int pipe = intel_crtc->pipe; | |
2859 | u32 reg, temp; | |
2860 | ||
2861 | /* Switch from PCDclk to Rawclk */ | |
2862 | reg = FDI_RX_CTL(pipe); | |
2863 | temp = I915_READ(reg); | |
2864 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2865 | ||
2866 | /* Disable CPU FDI TX PLL */ | |
2867 | reg = FDI_TX_CTL(pipe); | |
2868 | temp = I915_READ(reg); | |
2869 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2870 | ||
2871 | POSTING_READ(reg); | |
2872 | udelay(100); | |
2873 | ||
2874 | reg = FDI_RX_CTL(pipe); | |
2875 | temp = I915_READ(reg); | |
2876 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2877 | ||
2878 | /* Wait for the clocks to turn off. */ | |
2879 | POSTING_READ(reg); | |
2880 | udelay(100); | |
2881 | } | |
2882 | ||
0fc932b8 JB |
2883 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2884 | { | |
2885 | struct drm_device *dev = crtc->dev; | |
2886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2888 | int pipe = intel_crtc->pipe; | |
2889 | u32 reg, temp; | |
2890 | ||
2891 | /* disable CPU FDI tx and PCH FDI rx */ | |
2892 | reg = FDI_TX_CTL(pipe); | |
2893 | temp = I915_READ(reg); | |
2894 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2895 | POSTING_READ(reg); | |
2896 | ||
2897 | reg = FDI_RX_CTL(pipe); | |
2898 | temp = I915_READ(reg); | |
2899 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2900 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2901 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2902 | ||
2903 | POSTING_READ(reg); | |
2904 | udelay(100); | |
2905 | ||
2906 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2907 | if (HAS_PCH_IBX(dev)) { |
2908 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2909 | } |
0fc932b8 JB |
2910 | |
2911 | /* still set train pattern 1 */ | |
2912 | reg = FDI_TX_CTL(pipe); | |
2913 | temp = I915_READ(reg); | |
2914 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2915 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2916 | I915_WRITE(reg, temp); | |
2917 | ||
2918 | reg = FDI_RX_CTL(pipe); | |
2919 | temp = I915_READ(reg); | |
2920 | if (HAS_PCH_CPT(dev)) { | |
2921 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2922 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2923 | } else { | |
2924 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2925 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2926 | } | |
2927 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2928 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2929 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2930 | I915_WRITE(reg, temp); |
2931 | ||
2932 | POSTING_READ(reg); | |
2933 | udelay(100); | |
2934 | } | |
2935 | ||
5bb61643 CW |
2936 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2937 | { | |
2938 | struct drm_device *dev = crtc->dev; | |
2939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2941 | unsigned long flags; |
2942 | bool pending; | |
2943 | ||
10d83730 VS |
2944 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2945 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2946 | return false; |
2947 | ||
2948 | spin_lock_irqsave(&dev->event_lock, flags); | |
2949 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2950 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2951 | ||
2952 | return pending; | |
2953 | } | |
2954 | ||
e6c3a2a6 CW |
2955 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2956 | { | |
0f91128d | 2957 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2958 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2959 | |
2960 | if (crtc->fb == NULL) | |
2961 | return; | |
2962 | ||
2c10d571 DV |
2963 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2964 | ||
5bb61643 CW |
2965 | wait_event(dev_priv->pending_flip_queue, |
2966 | !intel_crtc_has_pending_flip(crtc)); | |
2967 | ||
0f91128d CW |
2968 | mutex_lock(&dev->struct_mutex); |
2969 | intel_finish_fb(crtc->fb); | |
2970 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2971 | } |
2972 | ||
e615efe4 ED |
2973 | /* Program iCLKIP clock to the desired frequency */ |
2974 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2975 | { | |
2976 | struct drm_device *dev = crtc->dev; | |
2977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 2978 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
2979 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2980 | u32 temp; | |
2981 | ||
09153000 DV |
2982 | mutex_lock(&dev_priv->dpio_lock); |
2983 | ||
e615efe4 ED |
2984 | /* It is necessary to ungate the pixclk gate prior to programming |
2985 | * the divisors, and gate it back when it is done. | |
2986 | */ | |
2987 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2988 | ||
2989 | /* Disable SSCCTL */ | |
2990 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2991 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2992 | SBI_SSCCTL_DISABLE, | |
2993 | SBI_ICLK); | |
e615efe4 ED |
2994 | |
2995 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 2996 | if (clock == 20000) { |
e615efe4 ED |
2997 | auxdiv = 1; |
2998 | divsel = 0x41; | |
2999 | phaseinc = 0x20; | |
3000 | } else { | |
3001 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3002 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3003 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3004 | * convert the virtual clock precision to KHz here for higher |
3005 | * precision. | |
3006 | */ | |
3007 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3008 | u32 iclk_pi_range = 64; | |
3009 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3010 | ||
12d7ceed | 3011 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3012 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3013 | pi_value = desired_divisor % iclk_pi_range; | |
3014 | ||
3015 | auxdiv = 0; | |
3016 | divsel = msb_divisor_value - 2; | |
3017 | phaseinc = pi_value; | |
3018 | } | |
3019 | ||
3020 | /* This should not happen with any sane values */ | |
3021 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3022 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3023 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3024 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3025 | ||
3026 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3027 | clock, |
e615efe4 ED |
3028 | auxdiv, |
3029 | divsel, | |
3030 | phasedir, | |
3031 | phaseinc); | |
3032 | ||
3033 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3034 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3035 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3036 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3037 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3038 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3039 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3040 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3041 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3042 | |
3043 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3044 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3045 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3046 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3047 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3048 | |
3049 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3050 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3051 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3052 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3053 | |
3054 | /* Wait for initialization time */ | |
3055 | udelay(24); | |
3056 | ||
3057 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3058 | |
3059 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3060 | } |
3061 | ||
275f01b2 DV |
3062 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3063 | enum pipe pch_transcoder) | |
3064 | { | |
3065 | struct drm_device *dev = crtc->base.dev; | |
3066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3067 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3068 | ||
3069 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3070 | I915_READ(HTOTAL(cpu_transcoder))); | |
3071 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3072 | I915_READ(HBLANK(cpu_transcoder))); | |
3073 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3074 | I915_READ(HSYNC(cpu_transcoder))); | |
3075 | ||
3076 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3077 | I915_READ(VTOTAL(cpu_transcoder))); | |
3078 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3079 | I915_READ(VBLANK(cpu_transcoder))); | |
3080 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3081 | I915_READ(VSYNC(cpu_transcoder))); | |
3082 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3083 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3084 | } | |
3085 | ||
1fbc0d78 DV |
3086 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3087 | { | |
3088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3089 | uint32_t temp; | |
3090 | ||
3091 | temp = I915_READ(SOUTH_CHICKEN1); | |
3092 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3093 | return; | |
3094 | ||
3095 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3096 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3097 | ||
3098 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3099 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3100 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3101 | POSTING_READ(SOUTH_CHICKEN1); | |
3102 | } | |
3103 | ||
3104 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3105 | { | |
3106 | struct drm_device *dev = intel_crtc->base.dev; | |
3107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3108 | ||
3109 | switch (intel_crtc->pipe) { | |
3110 | case PIPE_A: | |
3111 | break; | |
3112 | case PIPE_B: | |
3113 | if (intel_crtc->config.fdi_lanes > 2) | |
3114 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3115 | else | |
3116 | cpt_enable_fdi_bc_bifurcation(dev); | |
3117 | ||
3118 | break; | |
3119 | case PIPE_C: | |
3120 | cpt_enable_fdi_bc_bifurcation(dev); | |
3121 | ||
3122 | break; | |
3123 | default: | |
3124 | BUG(); | |
3125 | } | |
3126 | } | |
3127 | ||
f67a559d JB |
3128 | /* |
3129 | * Enable PCH resources required for PCH ports: | |
3130 | * - PCH PLLs | |
3131 | * - FDI training & RX/TX | |
3132 | * - update transcoder timings | |
3133 | * - DP transcoding bits | |
3134 | * - transcoder | |
3135 | */ | |
3136 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3137 | { |
3138 | struct drm_device *dev = crtc->dev; | |
3139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3141 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3142 | u32 reg, temp; |
2c07245f | 3143 | |
ab9412ba | 3144 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3145 | |
1fbc0d78 DV |
3146 | if (IS_IVYBRIDGE(dev)) |
3147 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3148 | ||
cd986abb DV |
3149 | /* Write the TU size bits before fdi link training, so that error |
3150 | * detection works. */ | |
3151 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3152 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3153 | ||
c98e9dcf | 3154 | /* For PCH output, training FDI link */ |
674cf967 | 3155 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3156 | |
3ad8a208 DV |
3157 | /* We need to program the right clock selection before writing the pixel |
3158 | * mutliplier into the DPLL. */ | |
303b81e0 | 3159 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3160 | u32 sel; |
4b645f14 | 3161 | |
c98e9dcf | 3162 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3163 | temp |= TRANS_DPLL_ENABLE(pipe); |
3164 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3165 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3166 | temp |= sel; |
3167 | else | |
3168 | temp &= ~sel; | |
c98e9dcf | 3169 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3170 | } |
5eddb70b | 3171 | |
3ad8a208 DV |
3172 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3173 | * transcoder, and we actually should do this to not upset any PCH | |
3174 | * transcoder that already use the clock when we share it. | |
3175 | * | |
3176 | * Note that enable_shared_dpll tries to do the right thing, but | |
3177 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3178 | * the right LVDS enable sequence. */ | |
3179 | ironlake_enable_shared_dpll(intel_crtc); | |
3180 | ||
d9b6cb56 JB |
3181 | /* set transcoder timing, panel must allow it */ |
3182 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3183 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3184 | |
303b81e0 | 3185 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3186 | |
c98e9dcf JB |
3187 | /* For PCH DP, enable TRANS_DP_CTL */ |
3188 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3189 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3190 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3191 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3192 | reg = TRANS_DP_CTL(pipe); |
3193 | temp = I915_READ(reg); | |
3194 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3195 | TRANS_DP_SYNC_MASK | |
3196 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3197 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3198 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3199 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3200 | |
3201 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3202 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3203 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3204 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3205 | |
3206 | switch (intel_trans_dp_port_sel(crtc)) { | |
3207 | case PCH_DP_B: | |
5eddb70b | 3208 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3209 | break; |
3210 | case PCH_DP_C: | |
5eddb70b | 3211 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3212 | break; |
3213 | case PCH_DP_D: | |
5eddb70b | 3214 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3215 | break; |
3216 | default: | |
e95d41e1 | 3217 | BUG(); |
32f9d658 | 3218 | } |
2c07245f | 3219 | |
5eddb70b | 3220 | I915_WRITE(reg, temp); |
6be4a607 | 3221 | } |
b52eb4dc | 3222 | |
b8a4f404 | 3223 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3224 | } |
3225 | ||
1507e5bd PZ |
3226 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3227 | { | |
3228 | struct drm_device *dev = crtc->dev; | |
3229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3231 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3232 | |
ab9412ba | 3233 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3234 | |
8c52b5e8 | 3235 | lpt_program_iclkip(crtc); |
1507e5bd | 3236 | |
0540e488 | 3237 | /* Set transcoder timing. */ |
275f01b2 | 3238 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3239 | |
937bb610 | 3240 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3241 | } |
3242 | ||
e2b78267 | 3243 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3244 | { |
e2b78267 | 3245 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3246 | |
3247 | if (pll == NULL) | |
3248 | return; | |
3249 | ||
3250 | if (pll->refcount == 0) { | |
46edb027 | 3251 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3252 | return; |
3253 | } | |
3254 | ||
f4a091c7 DV |
3255 | if (--pll->refcount == 0) { |
3256 | WARN_ON(pll->on); | |
3257 | WARN_ON(pll->active); | |
3258 | } | |
3259 | ||
a43f6e0f | 3260 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3261 | } |
3262 | ||
b89a1d39 | 3263 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3264 | { |
e2b78267 DV |
3265 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3266 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3267 | enum intel_dpll_id i; | |
ee7b9f93 | 3268 | |
ee7b9f93 | 3269 | if (pll) { |
46edb027 DV |
3270 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3271 | crtc->base.base.id, pll->name); | |
e2b78267 | 3272 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3273 | } |
3274 | ||
98b6bd99 DV |
3275 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3276 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3277 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3278 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3279 | |
46edb027 DV |
3280 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3281 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3282 | |
3283 | goto found; | |
3284 | } | |
3285 | ||
e72f9fbf DV |
3286 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3287 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3288 | |
3289 | /* Only want to check enabled timings first */ | |
3290 | if (pll->refcount == 0) | |
3291 | continue; | |
3292 | ||
b89a1d39 DV |
3293 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3294 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3295 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3296 | crtc->base.base.id, |
46edb027 | 3297 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3298 | |
3299 | goto found; | |
3300 | } | |
3301 | } | |
3302 | ||
3303 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3304 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3305 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3306 | if (pll->refcount == 0) { |
46edb027 DV |
3307 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3308 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3309 | goto found; |
3310 | } | |
3311 | } | |
3312 | ||
3313 | return NULL; | |
3314 | ||
3315 | found: | |
a43f6e0f | 3316 | crtc->config.shared_dpll = i; |
46edb027 DV |
3317 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3318 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3319 | |
cdbd2316 | 3320 | if (pll->active == 0) { |
66e985c0 DV |
3321 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3322 | sizeof(pll->hw_state)); | |
3323 | ||
46edb027 | 3324 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3325 | WARN_ON(pll->on); |
e9d6944e | 3326 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3327 | |
15bdd4cf | 3328 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3329 | } |
3330 | pll->refcount++; | |
e04c7350 | 3331 | |
ee7b9f93 JB |
3332 | return pll; |
3333 | } | |
3334 | ||
a1520318 | 3335 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3336 | { |
3337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3338 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3339 | u32 temp; |
3340 | ||
3341 | temp = I915_READ(dslreg); | |
3342 | udelay(500); | |
3343 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3344 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3345 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3346 | } |
3347 | } | |
3348 | ||
b074cec8 JB |
3349 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3350 | { | |
3351 | struct drm_device *dev = crtc->base.dev; | |
3352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3353 | int pipe = crtc->pipe; | |
3354 | ||
fd4daa9c | 3355 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3356 | /* Force use of hard-coded filter coefficients |
3357 | * as some pre-programmed values are broken, | |
3358 | * e.g. x201. | |
3359 | */ | |
3360 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3361 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3362 | PF_PIPE_SEL_IVB(pipe)); | |
3363 | else | |
3364 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3365 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3366 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3367 | } |
3368 | } | |
3369 | ||
bb53d4ae VS |
3370 | static void intel_enable_planes(struct drm_crtc *crtc) |
3371 | { | |
3372 | struct drm_device *dev = crtc->dev; | |
3373 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3374 | struct intel_plane *intel_plane; | |
3375 | ||
3376 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3377 | if (intel_plane->pipe == pipe) | |
3378 | intel_plane_restore(&intel_plane->base); | |
3379 | } | |
3380 | ||
3381 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3382 | { | |
3383 | struct drm_device *dev = crtc->dev; | |
3384 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3385 | struct intel_plane *intel_plane; | |
3386 | ||
3387 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3388 | if (intel_plane->pipe == pipe) | |
3389 | intel_plane_disable(&intel_plane->base); | |
3390 | } | |
3391 | ||
20bc8673 | 3392 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3393 | { |
3394 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3395 | ||
3396 | if (!crtc->config.ips_enabled) | |
3397 | return; | |
3398 | ||
3399 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3400 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3401 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3402 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3403 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3404 | if (IS_BROADWELL(crtc->base.dev)) { |
3405 | mutex_lock(&dev_priv->rps.hw_lock); | |
3406 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3407 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3408 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3409 | * value in IPS_CTL bit 31 after enabling IPS through the | |
3410 | * mailbox." Therefore we need to defer waiting on the state | |
3411 | * change. | |
3412 | * TODO: need to fix this for state checker | |
3413 | */ | |
3414 | } else { | |
3415 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3416 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3417 | * is essentially intel_wait_for_vblank. If we don't have this | |
3418 | * and don't wait for vblanks until the end of crtc_enable, then | |
3419 | * the HW state readout code will complain that the expected | |
3420 | * IPS_CTL value is not the one we read. */ | |
3421 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3422 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3423 | } | |
d77e4531 PZ |
3424 | } |
3425 | ||
20bc8673 | 3426 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3427 | { |
3428 | struct drm_device *dev = crtc->base.dev; | |
3429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3430 | ||
3431 | if (!crtc->config.ips_enabled) | |
3432 | return; | |
3433 | ||
3434 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3435 | if (IS_BROADWELL(crtc->base.dev)) { |
3436 | mutex_lock(&dev_priv->rps.hw_lock); | |
3437 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3438 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3439 | } else | |
3440 | I915_WRITE(IPS_CTL, 0); | |
d77e4531 PZ |
3441 | POSTING_READ(IPS_CTL); |
3442 | ||
3443 | /* We need to wait for a vblank before we can disable the plane. */ | |
3444 | intel_wait_for_vblank(dev, crtc->pipe); | |
3445 | } | |
3446 | ||
3447 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3448 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3449 | { | |
3450 | struct drm_device *dev = crtc->dev; | |
3451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3452 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3453 | enum pipe pipe = intel_crtc->pipe; | |
3454 | int palreg = PALETTE(pipe); | |
3455 | int i; | |
3456 | bool reenable_ips = false; | |
3457 | ||
3458 | /* The clocks have to be on to load the palette. */ | |
3459 | if (!crtc->enabled || !intel_crtc->active) | |
3460 | return; | |
3461 | ||
3462 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3463 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3464 | assert_dsi_pll_enabled(dev_priv); | |
3465 | else | |
3466 | assert_pll_enabled(dev_priv, pipe); | |
3467 | } | |
3468 | ||
3469 | /* use legacy palette for Ironlake */ | |
3470 | if (HAS_PCH_SPLIT(dev)) | |
3471 | palreg = LGC_PALETTE(pipe); | |
3472 | ||
3473 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3474 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3475 | */ | |
3476 | if (intel_crtc->config.ips_enabled && | |
3477 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
3478 | GAMMA_MODE_MODE_SPLIT)) { | |
3479 | hsw_disable_ips(intel_crtc); | |
3480 | reenable_ips = true; | |
3481 | } | |
3482 | ||
3483 | for (i = 0; i < 256; i++) { | |
3484 | I915_WRITE(palreg + 4 * i, | |
3485 | (intel_crtc->lut_r[i] << 16) | | |
3486 | (intel_crtc->lut_g[i] << 8) | | |
3487 | intel_crtc->lut_b[i]); | |
3488 | } | |
3489 | ||
3490 | if (reenable_ips) | |
3491 | hsw_enable_ips(intel_crtc); | |
3492 | } | |
3493 | ||
f67a559d JB |
3494 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3495 | { | |
3496 | struct drm_device *dev = crtc->dev; | |
3497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3499 | struct intel_encoder *encoder; |
f67a559d JB |
3500 | int pipe = intel_crtc->pipe; |
3501 | int plane = intel_crtc->plane; | |
f67a559d | 3502 | |
08a48469 DV |
3503 | WARN_ON(!crtc->enabled); |
3504 | ||
f67a559d JB |
3505 | if (intel_crtc->active) |
3506 | return; | |
3507 | ||
3508 | intel_crtc->active = true; | |
8664281b PZ |
3509 | |
3510 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3511 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3512 | ||
f6736a1a | 3513 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3514 | if (encoder->pre_enable) |
3515 | encoder->pre_enable(encoder); | |
f67a559d | 3516 | |
5bfe2ac0 | 3517 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3518 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3519 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3520 | * enabling. */ | |
88cefb6c | 3521 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3522 | } else { |
3523 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3524 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3525 | } | |
f67a559d | 3526 | |
b074cec8 | 3527 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3528 | |
9c54c0dd JB |
3529 | /* |
3530 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3531 | * clocks enabled | |
3532 | */ | |
3533 | intel_crtc_load_lut(crtc); | |
3534 | ||
f37fcc2a | 3535 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3536 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3537 | intel_crtc->config.has_pch_encoder, false); |
d1de00ef | 3538 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3539 | intel_enable_planes(crtc); |
5c38d48c | 3540 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3541 | |
5bfe2ac0 | 3542 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3543 | ironlake_pch_enable(crtc); |
c98e9dcf | 3544 | |
d1ebd816 | 3545 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3546 | intel_update_fbc(dev); |
d1ebd816 BW |
3547 | mutex_unlock(&dev->struct_mutex); |
3548 | ||
fa5c73b1 DV |
3549 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3550 | encoder->enable(encoder); | |
61b77ddd DV |
3551 | |
3552 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3553 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3554 | |
3555 | /* | |
3556 | * There seems to be a race in PCH platform hw (at least on some | |
3557 | * outputs) where an enabled pipe still completes any pageflip right | |
3558 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3559 | * as the first vblank happend, everything works as expected. Hence just | |
3560 | * wait for one vblank before returning to avoid strange things | |
3561 | * happening. | |
3562 | */ | |
3563 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3564 | } |
3565 | ||
42db64ef PZ |
3566 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3567 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3568 | { | |
f5adf94e | 3569 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3570 | } |
3571 | ||
dda9a66a VS |
3572 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3573 | { | |
3574 | struct drm_device *dev = crtc->dev; | |
3575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3577 | int pipe = intel_crtc->pipe; | |
3578 | int plane = intel_crtc->plane; | |
3579 | ||
d1de00ef | 3580 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3581 | intel_enable_planes(crtc); |
3582 | intel_crtc_update_cursor(crtc, true); | |
3583 | ||
3584 | hsw_enable_ips(intel_crtc); | |
3585 | ||
3586 | mutex_lock(&dev->struct_mutex); | |
3587 | intel_update_fbc(dev); | |
3588 | mutex_unlock(&dev->struct_mutex); | |
3589 | } | |
3590 | ||
3591 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3592 | { | |
3593 | struct drm_device *dev = crtc->dev; | |
3594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3596 | int pipe = intel_crtc->pipe; | |
3597 | int plane = intel_crtc->plane; | |
3598 | ||
3599 | intel_crtc_wait_for_pending_flips(crtc); | |
3600 | drm_vblank_off(dev, pipe); | |
3601 | ||
3602 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3603 | if (dev_priv->fbc.plane == plane) | |
3604 | intel_disable_fbc(dev); | |
3605 | ||
3606 | hsw_disable_ips(intel_crtc); | |
3607 | ||
3608 | intel_crtc_update_cursor(crtc, false); | |
3609 | intel_disable_planes(crtc); | |
d1de00ef | 3610 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3611 | } |
3612 | ||
e4916946 PZ |
3613 | /* |
3614 | * This implements the workaround described in the "notes" section of the mode | |
3615 | * set sequence documentation. When going from no pipes or single pipe to | |
3616 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3617 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3618 | */ | |
3619 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3620 | { | |
3621 | struct drm_device *dev = crtc->base.dev; | |
3622 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3623 | ||
3624 | /* We want to get the other_active_crtc only if there's only 1 other | |
3625 | * active crtc. */ | |
3626 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3627 | if (!crtc_it->active || crtc_it == crtc) | |
3628 | continue; | |
3629 | ||
3630 | if (other_active_crtc) | |
3631 | return; | |
3632 | ||
3633 | other_active_crtc = crtc_it; | |
3634 | } | |
3635 | if (!other_active_crtc) | |
3636 | return; | |
3637 | ||
3638 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3639 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3640 | } | |
3641 | ||
4f771f10 PZ |
3642 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3643 | { | |
3644 | struct drm_device *dev = crtc->dev; | |
3645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3647 | struct intel_encoder *encoder; | |
3648 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3649 | |
3650 | WARN_ON(!crtc->enabled); | |
3651 | ||
3652 | if (intel_crtc->active) | |
3653 | return; | |
3654 | ||
3655 | intel_crtc->active = true; | |
8664281b PZ |
3656 | |
3657 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3658 | if (intel_crtc->config.has_pch_encoder) | |
3659 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3660 | ||
5bfe2ac0 | 3661 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3662 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3663 | |
3664 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3665 | if (encoder->pre_enable) | |
3666 | encoder->pre_enable(encoder); | |
3667 | ||
1f544388 | 3668 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3669 | |
b074cec8 | 3670 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3671 | |
3672 | /* | |
3673 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3674 | * clocks enabled | |
3675 | */ | |
3676 | intel_crtc_load_lut(crtc); | |
3677 | ||
1f544388 | 3678 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3679 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3680 | |
f37fcc2a | 3681 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3682 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3683 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3684 | |
5bfe2ac0 | 3685 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3686 | lpt_pch_enable(crtc); |
4f771f10 | 3687 | |
8807e55b | 3688 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3689 | encoder->enable(encoder); |
8807e55b JN |
3690 | intel_opregion_notify_encoder(encoder, true); |
3691 | } | |
4f771f10 | 3692 | |
e4916946 PZ |
3693 | /* If we change the relative order between pipe/planes enabling, we need |
3694 | * to change the workaround. */ | |
3695 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3696 | haswell_crtc_enable_planes(crtc); |
3697 | ||
4f771f10 PZ |
3698 | /* |
3699 | * There seems to be a race in PCH platform hw (at least on some | |
3700 | * outputs) where an enabled pipe still completes any pageflip right | |
3701 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3702 | * as the first vblank happend, everything works as expected. Hence just | |
3703 | * wait for one vblank before returning to avoid strange things | |
3704 | * happening. | |
3705 | */ | |
3706 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3707 | } | |
3708 | ||
3f8dce3a DV |
3709 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3710 | { | |
3711 | struct drm_device *dev = crtc->base.dev; | |
3712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3713 | int pipe = crtc->pipe; | |
3714 | ||
3715 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3716 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3717 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3718 | I915_WRITE(PF_CTL(pipe), 0); |
3719 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3720 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3721 | } | |
3722 | } | |
3723 | ||
6be4a607 JB |
3724 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3725 | { | |
3726 | struct drm_device *dev = crtc->dev; | |
3727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3729 | struct intel_encoder *encoder; |
6be4a607 JB |
3730 | int pipe = intel_crtc->pipe; |
3731 | int plane = intel_crtc->plane; | |
5eddb70b | 3732 | u32 reg, temp; |
b52eb4dc | 3733 | |
ef9c3aee | 3734 | |
f7abfe8b CW |
3735 | if (!intel_crtc->active) |
3736 | return; | |
3737 | ||
ea9d758d DV |
3738 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3739 | encoder->disable(encoder); | |
3740 | ||
e6c3a2a6 | 3741 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3742 | drm_vblank_off(dev, pipe); |
913d8d11 | 3743 | |
5c3fe8b0 | 3744 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3745 | intel_disable_fbc(dev); |
2c07245f | 3746 | |
0d5b8c61 | 3747 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3748 | intel_disable_planes(crtc); |
d1de00ef | 3749 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3750 | |
d925c59a DV |
3751 | if (intel_crtc->config.has_pch_encoder) |
3752 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3753 | ||
b24e7179 | 3754 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3755 | |
3f8dce3a | 3756 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3757 | |
bf49ec8c DV |
3758 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3759 | if (encoder->post_disable) | |
3760 | encoder->post_disable(encoder); | |
2c07245f | 3761 | |
d925c59a DV |
3762 | if (intel_crtc->config.has_pch_encoder) { |
3763 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3764 | |
d925c59a DV |
3765 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3766 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3767 | |
d925c59a DV |
3768 | if (HAS_PCH_CPT(dev)) { |
3769 | /* disable TRANS_DP_CTL */ | |
3770 | reg = TRANS_DP_CTL(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3773 | TRANS_DP_PORT_SEL_MASK); | |
3774 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3775 | I915_WRITE(reg, temp); | |
3776 | ||
3777 | /* disable DPLL_SEL */ | |
3778 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3779 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3780 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3781 | } |
e3421a18 | 3782 | |
d925c59a | 3783 | /* disable PCH DPLL */ |
e72f9fbf | 3784 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3785 | |
d925c59a DV |
3786 | ironlake_fdi_pll_disable(intel_crtc); |
3787 | } | |
6b383a7f | 3788 | |
f7abfe8b | 3789 | intel_crtc->active = false; |
46ba614c | 3790 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3791 | |
3792 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3793 | intel_update_fbc(dev); |
d1ebd816 | 3794 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3795 | } |
1b3c7a47 | 3796 | |
4f771f10 | 3797 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3798 | { |
4f771f10 PZ |
3799 | struct drm_device *dev = crtc->dev; |
3800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3801 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3802 | struct intel_encoder *encoder; |
3803 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3804 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3805 | |
4f771f10 PZ |
3806 | if (!intel_crtc->active) |
3807 | return; | |
3808 | ||
dda9a66a VS |
3809 | haswell_crtc_disable_planes(crtc); |
3810 | ||
8807e55b JN |
3811 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3812 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3813 | encoder->disable(encoder); |
8807e55b | 3814 | } |
4f771f10 | 3815 | |
8664281b PZ |
3816 | if (intel_crtc->config.has_pch_encoder) |
3817 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3818 | intel_disable_pipe(dev_priv, pipe); |
3819 | ||
ad80a810 | 3820 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3821 | |
3f8dce3a | 3822 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3823 | |
1f544388 | 3824 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3825 | |
3826 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3827 | if (encoder->post_disable) | |
3828 | encoder->post_disable(encoder); | |
3829 | ||
88adfff1 | 3830 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3831 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3832 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3833 | intel_ddi_fdi_disable(crtc); |
83616634 | 3834 | } |
4f771f10 PZ |
3835 | |
3836 | intel_crtc->active = false; | |
46ba614c | 3837 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3838 | |
3839 | mutex_lock(&dev->struct_mutex); | |
3840 | intel_update_fbc(dev); | |
3841 | mutex_unlock(&dev->struct_mutex); | |
3842 | } | |
3843 | ||
ee7b9f93 JB |
3844 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3845 | { | |
3846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3847 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3848 | } |
3849 | ||
6441ab5f PZ |
3850 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3851 | { | |
3852 | intel_ddi_put_crtc_pll(crtc); | |
3853 | } | |
3854 | ||
02e792fb DV |
3855 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3856 | { | |
02e792fb | 3857 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3858 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3859 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3860 | |
23f09ce3 | 3861 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3862 | dev_priv->mm.interruptible = false; |
3863 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3864 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3865 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3866 | } |
02e792fb | 3867 | |
5dcdbcb0 CW |
3868 | /* Let userspace switch the overlay on again. In most cases userspace |
3869 | * has to recompute where to put it anyway. | |
3870 | */ | |
02e792fb DV |
3871 | } |
3872 | ||
61bc95c1 EE |
3873 | /** |
3874 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3875 | * cursor plane briefly if not already running after enabling the display | |
3876 | * plane. | |
3877 | * This workaround avoids occasional blank screens when self refresh is | |
3878 | * enabled. | |
3879 | */ | |
3880 | static void | |
3881 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3882 | { | |
3883 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3884 | ||
3885 | if ((cntl & CURSOR_MODE) == 0) { | |
3886 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3887 | ||
3888 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3889 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3890 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3891 | I915_WRITE(CURCNTR(pipe), cntl); | |
3892 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3893 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3894 | } | |
3895 | } | |
3896 | ||
2dd24552 JB |
3897 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3898 | { | |
3899 | struct drm_device *dev = crtc->base.dev; | |
3900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3901 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3902 | ||
328d8e82 | 3903 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3904 | return; |
3905 | ||
2dd24552 | 3906 | /* |
c0b03411 DV |
3907 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3908 | * according to register description and PRM. | |
2dd24552 | 3909 | */ |
c0b03411 DV |
3910 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3911 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3912 | |
b074cec8 JB |
3913 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3914 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3915 | |
3916 | /* Border color in case we don't scale up to the full screen. Black by | |
3917 | * default, change to something else for debugging. */ | |
3918 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3919 | } |
3920 | ||
586f49dc | 3921 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3922 | { |
586f49dc | 3923 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3924 | |
586f49dc JB |
3925 | /* Obtain SKU information */ |
3926 | mutex_lock(&dev_priv->dpio_lock); | |
3927 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3928 | CCK_FUSE_HPLL_FREQ_MASK; | |
3929 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3930 | |
586f49dc | 3931 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3932 | } |
3933 | ||
3934 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
3935 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
3936 | { | |
3937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3938 | u32 val, cmd; | |
3939 | ||
3940 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
3941 | cmd = 2; | |
3942 | else if (cdclk == 266) | |
3943 | cmd = 1; | |
3944 | else | |
3945 | cmd = 0; | |
3946 | ||
3947 | mutex_lock(&dev_priv->rps.hw_lock); | |
3948 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
3949 | val &= ~DSPFREQGUAR_MASK; | |
3950 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
3951 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
3952 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
3953 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
3954 | 50)) { | |
3955 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
3956 | } | |
3957 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3958 | ||
3959 | if (cdclk == 400) { | |
3960 | u32 divider, vco; | |
3961 | ||
3962 | vco = valleyview_get_vco(dev_priv); | |
3963 | divider = ((vco << 1) / cdclk) - 1; | |
3964 | ||
3965 | mutex_lock(&dev_priv->dpio_lock); | |
3966 | /* adjust cdclk divider */ | |
3967 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
3968 | val &= ~0xf; | |
3969 | val |= divider; | |
3970 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
3971 | mutex_unlock(&dev_priv->dpio_lock); | |
3972 | } | |
3973 | ||
3974 | mutex_lock(&dev_priv->dpio_lock); | |
3975 | /* adjust self-refresh exit latency value */ | |
3976 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
3977 | val &= ~0x7f; | |
3978 | ||
3979 | /* | |
3980 | * For high bandwidth configs, we set a higher latency in the bunit | |
3981 | * so that the core display fetch happens in time to avoid underruns. | |
3982 | */ | |
3983 | if (cdclk == 400) | |
3984 | val |= 4500 / 250; /* 4.5 usec */ | |
3985 | else | |
3986 | val |= 3000 / 250; /* 3.0 usec */ | |
3987 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
3988 | mutex_unlock(&dev_priv->dpio_lock); | |
3989 | ||
3990 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
3991 | intel_i2c_reset(dev); | |
3992 | } | |
3993 | ||
3994 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
3995 | { | |
3996 | int cur_cdclk, vco; | |
3997 | int divider; | |
3998 | ||
3999 | vco = valleyview_get_vco(dev_priv); | |
4000 | ||
4001 | mutex_lock(&dev_priv->dpio_lock); | |
4002 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4003 | mutex_unlock(&dev_priv->dpio_lock); | |
4004 | ||
4005 | divider &= 0xf; | |
4006 | ||
4007 | cur_cdclk = (vco << 1) / (divider + 1); | |
4008 | ||
4009 | return cur_cdclk; | |
4010 | } | |
4011 | ||
4012 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4013 | int max_pixclk) | |
4014 | { | |
4015 | int cur_cdclk; | |
4016 | ||
4017 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4018 | ||
4019 | /* | |
4020 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4021 | * 200MHz | |
4022 | * 267MHz | |
4023 | * 320MHz | |
4024 | * 400MHz | |
4025 | * So we check to see whether we're above 90% of the lower bin and | |
4026 | * adjust if needed. | |
4027 | */ | |
4028 | if (max_pixclk > 288000) { | |
4029 | return 400; | |
4030 | } else if (max_pixclk > 240000) { | |
4031 | return 320; | |
4032 | } else | |
4033 | return 266; | |
4034 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4035 | } | |
4036 | ||
4037 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, | |
4038 | unsigned modeset_pipes, | |
4039 | struct intel_crtc_config *pipe_config) | |
4040 | { | |
4041 | struct drm_device *dev = dev_priv->dev; | |
4042 | struct intel_crtc *intel_crtc; | |
4043 | int max_pixclk = 0; | |
4044 | ||
4045 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4046 | base.head) { | |
4047 | if (modeset_pipes & (1 << intel_crtc->pipe)) | |
4048 | max_pixclk = max(max_pixclk, | |
4049 | pipe_config->adjusted_mode.crtc_clock); | |
4050 | else if (intel_crtc->base.enabled) | |
4051 | max_pixclk = max(max_pixclk, | |
4052 | intel_crtc->config.adjusted_mode.crtc_clock); | |
4053 | } | |
4054 | ||
4055 | return max_pixclk; | |
4056 | } | |
4057 | ||
4058 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
4059 | unsigned *prepare_pipes, | |
4060 | unsigned modeset_pipes, | |
4061 | struct intel_crtc_config *pipe_config) | |
4062 | { | |
4063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4064 | struct intel_crtc *intel_crtc; | |
4065 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, | |
4066 | pipe_config); | |
4067 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4068 | ||
4069 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4070 | return; | |
4071 | ||
4072 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4073 | base.head) | |
4074 | if (intel_crtc->base.enabled) | |
4075 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4076 | } | |
4077 | ||
4078 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4079 | { | |
4080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4081 | int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL); | |
4082 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4083 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4084 | ||
4085 | if (req_cdclk != cur_cdclk) | |
4086 | valleyview_set_cdclk(dev, req_cdclk); | |
4087 | } | |
4088 | ||
89b667f8 JB |
4089 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4090 | { | |
4091 | struct drm_device *dev = crtc->dev; | |
4092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4094 | struct intel_encoder *encoder; | |
4095 | int pipe = intel_crtc->pipe; | |
4096 | int plane = intel_crtc->plane; | |
23538ef1 | 4097 | bool is_dsi; |
89b667f8 JB |
4098 | |
4099 | WARN_ON(!crtc->enabled); | |
4100 | ||
4101 | if (intel_crtc->active) | |
4102 | return; | |
4103 | ||
4104 | intel_crtc->active = true; | |
89b667f8 | 4105 | |
89b667f8 JB |
4106 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4107 | if (encoder->pre_pll_enable) | |
4108 | encoder->pre_pll_enable(encoder); | |
4109 | ||
23538ef1 JN |
4110 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4111 | ||
e9fd1c02 JN |
4112 | if (!is_dsi) |
4113 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4114 | |
4115 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4116 | if (encoder->pre_enable) | |
4117 | encoder->pre_enable(encoder); | |
4118 | ||
2dd24552 JB |
4119 | i9xx_pfit_enable(intel_crtc); |
4120 | ||
63cbb074 VS |
4121 | intel_crtc_load_lut(crtc); |
4122 | ||
f37fcc2a | 4123 | intel_update_watermarks(crtc); |
23538ef1 | 4124 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
d1de00ef | 4125 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4126 | intel_enable_planes(crtc); |
5c38d48c | 4127 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4128 | |
89b667f8 | 4129 | intel_update_fbc(dev); |
5004945f JN |
4130 | |
4131 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4132 | encoder->enable(encoder); | |
89b667f8 JB |
4133 | } |
4134 | ||
0b8765c6 | 4135 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4136 | { |
4137 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4138 | struct drm_i915_private *dev_priv = dev->dev_private; |
4139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4140 | struct intel_encoder *encoder; |
79e53945 | 4141 | int pipe = intel_crtc->pipe; |
80824003 | 4142 | int plane = intel_crtc->plane; |
79e53945 | 4143 | |
08a48469 DV |
4144 | WARN_ON(!crtc->enabled); |
4145 | ||
f7abfe8b CW |
4146 | if (intel_crtc->active) |
4147 | return; | |
4148 | ||
4149 | intel_crtc->active = true; | |
6b383a7f | 4150 | |
9d6d9f19 MK |
4151 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4152 | if (encoder->pre_enable) | |
4153 | encoder->pre_enable(encoder); | |
4154 | ||
f6736a1a DV |
4155 | i9xx_enable_pll(intel_crtc); |
4156 | ||
2dd24552 JB |
4157 | i9xx_pfit_enable(intel_crtc); |
4158 | ||
63cbb074 VS |
4159 | intel_crtc_load_lut(crtc); |
4160 | ||
f37fcc2a | 4161 | intel_update_watermarks(crtc); |
23538ef1 | 4162 | intel_enable_pipe(dev_priv, pipe, false, false); |
d1de00ef | 4163 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4164 | intel_enable_planes(crtc); |
22e407d7 | 4165 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4166 | if (IS_G4X(dev)) |
4167 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4168 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4169 | |
0b8765c6 JB |
4170 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4171 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4172 | |
f440eb13 | 4173 | intel_update_fbc(dev); |
ef9c3aee | 4174 | |
fa5c73b1 DV |
4175 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4176 | encoder->enable(encoder); | |
0b8765c6 | 4177 | } |
79e53945 | 4178 | |
87476d63 DV |
4179 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4180 | { | |
4181 | struct drm_device *dev = crtc->base.dev; | |
4182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4183 | |
328d8e82 DV |
4184 | if (!crtc->config.gmch_pfit.control) |
4185 | return; | |
87476d63 | 4186 | |
328d8e82 | 4187 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4188 | |
328d8e82 DV |
4189 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4190 | I915_READ(PFIT_CONTROL)); | |
4191 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4192 | } |
4193 | ||
0b8765c6 JB |
4194 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4195 | { | |
4196 | struct drm_device *dev = crtc->dev; | |
4197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4199 | struct intel_encoder *encoder; |
0b8765c6 JB |
4200 | int pipe = intel_crtc->pipe; |
4201 | int plane = intel_crtc->plane; | |
ef9c3aee | 4202 | |
f7abfe8b CW |
4203 | if (!intel_crtc->active) |
4204 | return; | |
4205 | ||
ea9d758d DV |
4206 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4207 | encoder->disable(encoder); | |
4208 | ||
0b8765c6 | 4209 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4210 | intel_crtc_wait_for_pending_flips(crtc); |
4211 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4212 | |
5c3fe8b0 | 4213 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4214 | intel_disable_fbc(dev); |
79e53945 | 4215 | |
0d5b8c61 VS |
4216 | intel_crtc_dpms_overlay(intel_crtc, false); |
4217 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4218 | intel_disable_planes(crtc); |
d1de00ef | 4219 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4220 | |
b24e7179 | 4221 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4222 | |
87476d63 | 4223 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4224 | |
89b667f8 JB |
4225 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4226 | if (encoder->post_disable) | |
4227 | encoder->post_disable(encoder); | |
4228 | ||
f6071166 JB |
4229 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4230 | vlv_disable_pll(dev_priv, pipe); | |
4231 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4232 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4233 | |
f7abfe8b | 4234 | intel_crtc->active = false; |
46ba614c | 4235 | intel_update_watermarks(crtc); |
f37fcc2a | 4236 | |
6b383a7f | 4237 | intel_update_fbc(dev); |
0b8765c6 JB |
4238 | } |
4239 | ||
ee7b9f93 JB |
4240 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4241 | { | |
4242 | } | |
4243 | ||
976f8a20 DV |
4244 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4245 | bool enabled) | |
2c07245f ZW |
4246 | { |
4247 | struct drm_device *dev = crtc->dev; | |
4248 | struct drm_i915_master_private *master_priv; | |
4249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4250 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4251 | |
4252 | if (!dev->primary->master) | |
4253 | return; | |
4254 | ||
4255 | master_priv = dev->primary->master->driver_priv; | |
4256 | if (!master_priv->sarea_priv) | |
4257 | return; | |
4258 | ||
79e53945 JB |
4259 | switch (pipe) { |
4260 | case 0: | |
4261 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4262 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4263 | break; | |
4264 | case 1: | |
4265 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4266 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4267 | break; | |
4268 | default: | |
9db4a9c7 | 4269 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4270 | break; |
4271 | } | |
79e53945 JB |
4272 | } |
4273 | ||
976f8a20 DV |
4274 | /** |
4275 | * Sets the power management mode of the pipe and plane. | |
4276 | */ | |
4277 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4278 | { | |
4279 | struct drm_device *dev = crtc->dev; | |
4280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4281 | struct intel_encoder *intel_encoder; | |
4282 | bool enable = false; | |
4283 | ||
4284 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4285 | enable |= intel_encoder->connectors_active; | |
4286 | ||
4287 | if (enable) | |
4288 | dev_priv->display.crtc_enable(crtc); | |
4289 | else | |
4290 | dev_priv->display.crtc_disable(crtc); | |
4291 | ||
4292 | intel_crtc_update_sarea(crtc, enable); | |
4293 | } | |
4294 | ||
cdd59983 CW |
4295 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4296 | { | |
cdd59983 | 4297 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4298 | struct drm_connector *connector; |
ee7b9f93 | 4299 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4300 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4301 | |
976f8a20 DV |
4302 | /* crtc should still be enabled when we disable it. */ |
4303 | WARN_ON(!crtc->enabled); | |
4304 | ||
4305 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4306 | intel_crtc->eld_vld = false; |
976f8a20 | 4307 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4308 | dev_priv->display.off(crtc); |
4309 | ||
931872fc | 4310 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4311 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4312 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4313 | |
4314 | if (crtc->fb) { | |
4315 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4316 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4317 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4318 | crtc->fb = NULL; |
4319 | } | |
4320 | ||
4321 | /* Update computed state. */ | |
4322 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4323 | if (!connector->encoder || !connector->encoder->crtc) | |
4324 | continue; | |
4325 | ||
4326 | if (connector->encoder->crtc != crtc) | |
4327 | continue; | |
4328 | ||
4329 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4330 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4331 | } |
4332 | } | |
4333 | ||
ea5b213a | 4334 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4335 | { |
4ef69c7a | 4336 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4337 | |
ea5b213a CW |
4338 | drm_encoder_cleanup(encoder); |
4339 | kfree(intel_encoder); | |
7e7d76c3 JB |
4340 | } |
4341 | ||
9237329d | 4342 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4343 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4344 | * state of the entire output pipe. */ | |
9237329d | 4345 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4346 | { |
5ab432ef DV |
4347 | if (mode == DRM_MODE_DPMS_ON) { |
4348 | encoder->connectors_active = true; | |
4349 | ||
b2cabb0e | 4350 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4351 | } else { |
4352 | encoder->connectors_active = false; | |
4353 | ||
b2cabb0e | 4354 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4355 | } |
79e53945 JB |
4356 | } |
4357 | ||
0a91ca29 DV |
4358 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4359 | * internal consistency). */ | |
b980514c | 4360 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4361 | { |
0a91ca29 DV |
4362 | if (connector->get_hw_state(connector)) { |
4363 | struct intel_encoder *encoder = connector->encoder; | |
4364 | struct drm_crtc *crtc; | |
4365 | bool encoder_enabled; | |
4366 | enum pipe pipe; | |
4367 | ||
4368 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4369 | connector->base.base.id, | |
4370 | drm_get_connector_name(&connector->base)); | |
4371 | ||
4372 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4373 | "wrong connector dpms state\n"); | |
4374 | WARN(connector->base.encoder != &encoder->base, | |
4375 | "active connector not linked to encoder\n"); | |
4376 | WARN(!encoder->connectors_active, | |
4377 | "encoder->connectors_active not set\n"); | |
4378 | ||
4379 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4380 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4381 | if (WARN_ON(!encoder->base.crtc)) | |
4382 | return; | |
4383 | ||
4384 | crtc = encoder->base.crtc; | |
4385 | ||
4386 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4387 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4388 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4389 | "encoder active on the wrong pipe\n"); | |
4390 | } | |
79e53945 JB |
4391 | } |
4392 | ||
5ab432ef DV |
4393 | /* Even simpler default implementation, if there's really no special case to |
4394 | * consider. */ | |
4395 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4396 | { |
5ab432ef DV |
4397 | /* All the simple cases only support two dpms states. */ |
4398 | if (mode != DRM_MODE_DPMS_ON) | |
4399 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4400 | |
5ab432ef DV |
4401 | if (mode == connector->dpms) |
4402 | return; | |
4403 | ||
4404 | connector->dpms = mode; | |
4405 | ||
4406 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4407 | if (connector->encoder) |
4408 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4409 | |
b980514c | 4410 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4411 | } |
4412 | ||
f0947c37 DV |
4413 | /* Simple connector->get_hw_state implementation for encoders that support only |
4414 | * one connector and no cloning and hence the encoder state determines the state | |
4415 | * of the connector. */ | |
4416 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4417 | { |
24929352 | 4418 | enum pipe pipe = 0; |
f0947c37 | 4419 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4420 | |
f0947c37 | 4421 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4422 | } |
4423 | ||
1857e1da DV |
4424 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4425 | struct intel_crtc_config *pipe_config) | |
4426 | { | |
4427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4428 | struct intel_crtc *pipe_B_crtc = | |
4429 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4430 | ||
4431 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4432 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4433 | if (pipe_config->fdi_lanes > 4) { | |
4434 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4435 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4436 | return false; | |
4437 | } | |
4438 | ||
bafb6553 | 4439 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4440 | if (pipe_config->fdi_lanes > 2) { |
4441 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4442 | pipe_config->fdi_lanes); | |
4443 | return false; | |
4444 | } else { | |
4445 | return true; | |
4446 | } | |
4447 | } | |
4448 | ||
4449 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4450 | return true; | |
4451 | ||
4452 | /* Ivybridge 3 pipe is really complicated */ | |
4453 | switch (pipe) { | |
4454 | case PIPE_A: | |
4455 | return true; | |
4456 | case PIPE_B: | |
4457 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4458 | pipe_config->fdi_lanes > 2) { | |
4459 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4460 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4461 | return false; | |
4462 | } | |
4463 | return true; | |
4464 | case PIPE_C: | |
1e833f40 | 4465 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4466 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4467 | if (pipe_config->fdi_lanes > 2) { | |
4468 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4469 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4470 | return false; | |
4471 | } | |
4472 | } else { | |
4473 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4474 | return false; | |
4475 | } | |
4476 | return true; | |
4477 | default: | |
4478 | BUG(); | |
4479 | } | |
4480 | } | |
4481 | ||
e29c22c0 DV |
4482 | #define RETRY 1 |
4483 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4484 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4485 | { |
1857e1da | 4486 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4487 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4488 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4489 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4490 | |
e29c22c0 | 4491 | retry: |
877d48d5 DV |
4492 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4493 | * each output octet as 10 bits. The actual frequency | |
4494 | * is stored as a divider into a 100MHz clock, and the | |
4495 | * mode pixel clock is stored in units of 1KHz. | |
4496 | * Hence the bw of each lane in terms of the mode signal | |
4497 | * is: | |
4498 | */ | |
4499 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4500 | ||
241bfc38 | 4501 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4502 | |
2bd89a07 | 4503 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4504 | pipe_config->pipe_bpp); |
4505 | ||
4506 | pipe_config->fdi_lanes = lane; | |
4507 | ||
2bd89a07 | 4508 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4509 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4510 | |
e29c22c0 DV |
4511 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4512 | intel_crtc->pipe, pipe_config); | |
4513 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4514 | pipe_config->pipe_bpp -= 2*3; | |
4515 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4516 | pipe_config->pipe_bpp); | |
4517 | needs_recompute = true; | |
4518 | pipe_config->bw_constrained = true; | |
4519 | ||
4520 | goto retry; | |
4521 | } | |
4522 | ||
4523 | if (needs_recompute) | |
4524 | return RETRY; | |
4525 | ||
4526 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4527 | } |
4528 | ||
42db64ef PZ |
4529 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4530 | struct intel_crtc_config *pipe_config) | |
4531 | { | |
3c4ca58c PZ |
4532 | pipe_config->ips_enabled = i915_enable_ips && |
4533 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4534 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4535 | } |
4536 | ||
a43f6e0f | 4537 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4538 | struct intel_crtc_config *pipe_config) |
79e53945 | 4539 | { |
a43f6e0f | 4540 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4541 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4542 | |
ad3a4479 | 4543 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4544 | if (INTEL_INFO(dev)->gen < 4) { |
4545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4546 | int clock_limit = | |
4547 | dev_priv->display.get_display_clock_speed(dev); | |
4548 | ||
4549 | /* | |
4550 | * Enable pixel doubling when the dot clock | |
4551 | * is > 90% of the (display) core speed. | |
4552 | * | |
b397c96b VS |
4553 | * GDG double wide on either pipe, |
4554 | * otherwise pipe A only. | |
cf532bb2 | 4555 | */ |
b397c96b | 4556 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4557 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4558 | clock_limit *= 2; |
cf532bb2 | 4559 | pipe_config->double_wide = true; |
ad3a4479 VS |
4560 | } |
4561 | ||
241bfc38 | 4562 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4563 | return -EINVAL; |
2c07245f | 4564 | } |
89749350 | 4565 | |
1d1d0e27 VS |
4566 | /* |
4567 | * Pipe horizontal size must be even in: | |
4568 | * - DVO ganged mode | |
4569 | * - LVDS dual channel mode | |
4570 | * - Double wide pipe | |
4571 | */ | |
4572 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4573 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4574 | pipe_config->pipe_src_w &= ~1; | |
4575 | ||
8693a824 DL |
4576 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4577 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4578 | */ |
4579 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4580 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4581 | return -EINVAL; |
44f46b42 | 4582 | |
bd080ee5 | 4583 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4584 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4585 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4586 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4587 | * for lvds. */ | |
4588 | pipe_config->pipe_bpp = 8*3; | |
4589 | } | |
4590 | ||
f5adf94e | 4591 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4592 | hsw_compute_ips_config(crtc, pipe_config); |
4593 | ||
4594 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4595 | * clock survives for now. */ | |
4596 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4597 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4598 | |
877d48d5 | 4599 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4600 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4601 | |
e29c22c0 | 4602 | return 0; |
79e53945 JB |
4603 | } |
4604 | ||
25eb05fc JB |
4605 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4606 | { | |
4607 | return 400000; /* FIXME */ | |
4608 | } | |
4609 | ||
e70236a8 JB |
4610 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4611 | { | |
4612 | return 400000; | |
4613 | } | |
79e53945 | 4614 | |
e70236a8 | 4615 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4616 | { |
e70236a8 JB |
4617 | return 333000; |
4618 | } | |
79e53945 | 4619 | |
e70236a8 JB |
4620 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4621 | { | |
4622 | return 200000; | |
4623 | } | |
79e53945 | 4624 | |
257a7ffc DV |
4625 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4626 | { | |
4627 | u16 gcfgc = 0; | |
4628 | ||
4629 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4630 | ||
4631 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4632 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4633 | return 267000; | |
4634 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4635 | return 333000; | |
4636 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4637 | return 444000; | |
4638 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4639 | return 200000; | |
4640 | default: | |
4641 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4642 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4643 | return 133000; | |
4644 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4645 | return 167000; | |
4646 | } | |
4647 | } | |
4648 | ||
e70236a8 JB |
4649 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4650 | { | |
4651 | u16 gcfgc = 0; | |
79e53945 | 4652 | |
e70236a8 JB |
4653 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4654 | ||
4655 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4656 | return 133000; | |
4657 | else { | |
4658 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4659 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4660 | return 333000; | |
4661 | default: | |
4662 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4663 | return 190000; | |
79e53945 | 4664 | } |
e70236a8 JB |
4665 | } |
4666 | } | |
4667 | ||
4668 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4669 | { | |
4670 | return 266000; | |
4671 | } | |
4672 | ||
4673 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4674 | { | |
4675 | u16 hpllcc = 0; | |
4676 | /* Assume that the hardware is in the high speed state. This | |
4677 | * should be the default. | |
4678 | */ | |
4679 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4680 | case GC_CLOCK_133_200: | |
4681 | case GC_CLOCK_100_200: | |
4682 | return 200000; | |
4683 | case GC_CLOCK_166_250: | |
4684 | return 250000; | |
4685 | case GC_CLOCK_100_133: | |
79e53945 | 4686 | return 133000; |
e70236a8 | 4687 | } |
79e53945 | 4688 | |
e70236a8 JB |
4689 | /* Shouldn't happen */ |
4690 | return 0; | |
4691 | } | |
79e53945 | 4692 | |
e70236a8 JB |
4693 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4694 | { | |
4695 | return 133000; | |
79e53945 JB |
4696 | } |
4697 | ||
2c07245f | 4698 | static void |
a65851af | 4699 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4700 | { |
a65851af VS |
4701 | while (*num > DATA_LINK_M_N_MASK || |
4702 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4703 | *num >>= 1; |
4704 | *den >>= 1; | |
4705 | } | |
4706 | } | |
4707 | ||
a65851af VS |
4708 | static void compute_m_n(unsigned int m, unsigned int n, |
4709 | uint32_t *ret_m, uint32_t *ret_n) | |
4710 | { | |
4711 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4712 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4713 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4714 | } | |
4715 | ||
e69d0bc1 DV |
4716 | void |
4717 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4718 | int pixel_clock, int link_clock, | |
4719 | struct intel_link_m_n *m_n) | |
2c07245f | 4720 | { |
e69d0bc1 | 4721 | m_n->tu = 64; |
a65851af VS |
4722 | |
4723 | compute_m_n(bits_per_pixel * pixel_clock, | |
4724 | link_clock * nlanes * 8, | |
4725 | &m_n->gmch_m, &m_n->gmch_n); | |
4726 | ||
4727 | compute_m_n(pixel_clock, link_clock, | |
4728 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4729 | } |
4730 | ||
a7615030 CW |
4731 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4732 | { | |
72bbe58c KP |
4733 | if (i915_panel_use_ssc >= 0) |
4734 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4735 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4736 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4737 | } |
4738 | ||
c65d77d8 JB |
4739 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4740 | { | |
4741 | struct drm_device *dev = crtc->dev; | |
4742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4743 | int refclk; | |
4744 | ||
a0c4da24 | 4745 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4746 | refclk = 100000; |
a0c4da24 | 4747 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4748 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4749 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4750 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4751 | refclk / 1000); | |
4752 | } else if (!IS_GEN2(dev)) { | |
4753 | refclk = 96000; | |
4754 | } else { | |
4755 | refclk = 48000; | |
4756 | } | |
4757 | ||
4758 | return refclk; | |
4759 | } | |
4760 | ||
7429e9d4 | 4761 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4762 | { |
7df00d7a | 4763 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4764 | } |
f47709a9 | 4765 | |
7429e9d4 DV |
4766 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4767 | { | |
4768 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4769 | } |
4770 | ||
f47709a9 | 4771 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4772 | intel_clock_t *reduced_clock) |
4773 | { | |
f47709a9 | 4774 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4775 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4776 | int pipe = crtc->pipe; |
a7516a05 JB |
4777 | u32 fp, fp2 = 0; |
4778 | ||
4779 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4780 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4781 | if (reduced_clock) |
7429e9d4 | 4782 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4783 | } else { |
7429e9d4 | 4784 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4785 | if (reduced_clock) |
7429e9d4 | 4786 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4787 | } |
4788 | ||
4789 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4790 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4791 | |
f47709a9 DV |
4792 | crtc->lowfreq_avail = false; |
4793 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4794 | reduced_clock && i915_powersave) { |
4795 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4796 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4797 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4798 | } else { |
4799 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4800 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4801 | } |
4802 | } | |
4803 | ||
5e69f97f CML |
4804 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4805 | pipe) | |
89b667f8 JB |
4806 | { |
4807 | u32 reg_val; | |
4808 | ||
4809 | /* | |
4810 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4811 | * and set it to a reasonable value instead. | |
4812 | */ | |
ab3c759a | 4813 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4814 | reg_val &= 0xffffff00; |
4815 | reg_val |= 0x00000030; | |
ab3c759a | 4816 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4817 | |
ab3c759a | 4818 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4819 | reg_val &= 0x8cffffff; |
4820 | reg_val = 0x8c000000; | |
ab3c759a | 4821 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4822 | |
ab3c759a | 4823 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4824 | reg_val &= 0xffffff00; |
ab3c759a | 4825 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4826 | |
ab3c759a | 4827 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4828 | reg_val &= 0x00ffffff; |
4829 | reg_val |= 0xb0000000; | |
ab3c759a | 4830 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4831 | } |
4832 | ||
b551842d DV |
4833 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4834 | struct intel_link_m_n *m_n) | |
4835 | { | |
4836 | struct drm_device *dev = crtc->base.dev; | |
4837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4838 | int pipe = crtc->pipe; | |
4839 | ||
e3b95f1e DV |
4840 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4841 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4842 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4843 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4844 | } |
4845 | ||
4846 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4847 | struct intel_link_m_n *m_n) | |
4848 | { | |
4849 | struct drm_device *dev = crtc->base.dev; | |
4850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4851 | int pipe = crtc->pipe; | |
4852 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4853 | ||
4854 | if (INTEL_INFO(dev)->gen >= 5) { | |
4855 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4856 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4857 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4858 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4859 | } else { | |
e3b95f1e DV |
4860 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4861 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4862 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4863 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4864 | } |
4865 | } | |
4866 | ||
03afc4a2 DV |
4867 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4868 | { | |
4869 | if (crtc->config.has_pch_encoder) | |
4870 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4871 | else | |
4872 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4873 | } | |
4874 | ||
f47709a9 | 4875 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4876 | { |
f47709a9 | 4877 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4878 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4879 | int pipe = crtc->pipe; |
89b667f8 | 4880 | u32 dpll, mdiv; |
a0c4da24 | 4881 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4882 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4883 | |
09153000 DV |
4884 | mutex_lock(&dev_priv->dpio_lock); |
4885 | ||
f47709a9 DV |
4886 | bestn = crtc->config.dpll.n; |
4887 | bestm1 = crtc->config.dpll.m1; | |
4888 | bestm2 = crtc->config.dpll.m2; | |
4889 | bestp1 = crtc->config.dpll.p1; | |
4890 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4891 | |
89b667f8 JB |
4892 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4893 | ||
4894 | /* PLL B needs special handling */ | |
4895 | if (pipe) | |
5e69f97f | 4896 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4897 | |
4898 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4899 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4900 | |
4901 | /* Disable target IRef on PLL */ | |
ab3c759a | 4902 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4903 | reg_val &= 0x00ffffff; |
ab3c759a | 4904 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4905 | |
4906 | /* Disable fast lock */ | |
ab3c759a | 4907 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4908 | |
4909 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4910 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4911 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4912 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4913 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4914 | |
4915 | /* | |
4916 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4917 | * but we don't support that). | |
4918 | * Note: don't use the DAC post divider as it seems unstable. | |
4919 | */ | |
4920 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4921 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4922 | |
a0c4da24 | 4923 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4924 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4925 | |
89b667f8 | 4926 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4927 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4928 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4929 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4930 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4931 | 0x009f0003); |
89b667f8 | 4932 | else |
ab3c759a | 4933 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4934 | 0x00d0000f); |
4935 | ||
4936 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4937 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4938 | /* Use SSC source */ | |
4939 | if (!pipe) | |
ab3c759a | 4940 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4941 | 0x0df40000); |
4942 | else | |
ab3c759a | 4943 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4944 | 0x0df70000); |
4945 | } else { /* HDMI or VGA */ | |
4946 | /* Use bend source */ | |
4947 | if (!pipe) | |
ab3c759a | 4948 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4949 | 0x0df70000); |
4950 | else | |
ab3c759a | 4951 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4952 | 0x0df40000); |
4953 | } | |
a0c4da24 | 4954 | |
ab3c759a | 4955 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
4956 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4957 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4958 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4959 | coreclk |= 0x01000000; | |
ab3c759a | 4960 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 4961 | |
ab3c759a | 4962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 4963 | |
89b667f8 JB |
4964 | /* Enable DPIO clock input */ |
4965 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4966 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
4967 | /* We should never disable this, set it here for state tracking */ |
4968 | if (pipe == PIPE_B) | |
89b667f8 | 4969 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 4970 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
4971 | crtc->config.dpll_hw_state.dpll = dpll; |
4972 | ||
ef1b460d DV |
4973 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4974 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4975 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4976 | ||
89b667f8 JB |
4977 | if (crtc->config.has_dp_encoder) |
4978 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4979 | |
4980 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4981 | } |
4982 | ||
f47709a9 DV |
4983 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4984 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4985 | int num_connectors) |
4986 | { | |
f47709a9 | 4987 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4988 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
4989 | u32 dpll; |
4990 | bool is_sdvo; | |
f47709a9 | 4991 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4992 | |
f47709a9 | 4993 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4994 | |
f47709a9 DV |
4995 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4996 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4997 | |
4998 | dpll = DPLL_VGA_MODE_DIS; | |
4999 | ||
f47709a9 | 5000 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5001 | dpll |= DPLLB_MODE_LVDS; |
5002 | else | |
5003 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5004 | |
ef1b460d | 5005 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5006 | dpll |= (crtc->config.pixel_multiplier - 1) |
5007 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5008 | } |
198a037f DV |
5009 | |
5010 | if (is_sdvo) | |
4a33e48d | 5011 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5012 | |
f47709a9 | 5013 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5014 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5015 | |
5016 | /* compute bitmask from p1 value */ | |
5017 | if (IS_PINEVIEW(dev)) | |
5018 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5019 | else { | |
5020 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5021 | if (IS_G4X(dev) && reduced_clock) | |
5022 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5023 | } | |
5024 | switch (clock->p2) { | |
5025 | case 5: | |
5026 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5027 | break; | |
5028 | case 7: | |
5029 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5030 | break; | |
5031 | case 10: | |
5032 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5033 | break; | |
5034 | case 14: | |
5035 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5036 | break; | |
5037 | } | |
5038 | if (INTEL_INFO(dev)->gen >= 4) | |
5039 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5040 | ||
09ede541 | 5041 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5042 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5043 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5044 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5045 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5046 | else | |
5047 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5048 | ||
5049 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5050 | crtc->config.dpll_hw_state.dpll = dpll; |
5051 | ||
eb1cbe48 | 5052 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5053 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5054 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5055 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5056 | } |
66e3d5c0 DV |
5057 | |
5058 | if (crtc->config.has_dp_encoder) | |
5059 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5060 | } |
5061 | ||
f47709a9 | 5062 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5063 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5064 | int num_connectors) |
5065 | { | |
f47709a9 | 5066 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5067 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5068 | u32 dpll; |
f47709a9 | 5069 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5070 | |
f47709a9 | 5071 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5072 | |
eb1cbe48 DV |
5073 | dpll = DPLL_VGA_MODE_DIS; |
5074 | ||
f47709a9 | 5075 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5076 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5077 | } else { | |
5078 | if (clock->p1 == 2) | |
5079 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5080 | else | |
5081 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5082 | if (clock->p2 == 4) | |
5083 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5084 | } | |
5085 | ||
4a33e48d DV |
5086 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5087 | dpll |= DPLL_DVO_2X_MODE; | |
5088 | ||
f47709a9 | 5089 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5090 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5091 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5092 | else | |
5093 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5094 | ||
5095 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5096 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5097 | } |
5098 | ||
8a654f3b | 5099 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5100 | { |
5101 | struct drm_device *dev = intel_crtc->base.dev; | |
5102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5103 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5104 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5105 | struct drm_display_mode *adjusted_mode = |
5106 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5107 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5108 | ||
5109 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5110 | * the hw state checker will get angry at the mismatch. */ | |
5111 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5112 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5113 | |
5114 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5115 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5116 | crtc_vtotal -= 1; |
5117 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5118 | vsyncshift = adjusted_mode->crtc_hsync_start |
5119 | - adjusted_mode->crtc_htotal / 2; | |
5120 | } else { | |
5121 | vsyncshift = 0; | |
5122 | } | |
5123 | ||
5124 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5125 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5126 | |
fe2b8f9d | 5127 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5128 | (adjusted_mode->crtc_hdisplay - 1) | |
5129 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5130 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5131 | (adjusted_mode->crtc_hblank_start - 1) | |
5132 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5133 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5134 | (adjusted_mode->crtc_hsync_start - 1) | |
5135 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5136 | ||
fe2b8f9d | 5137 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5138 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5139 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5140 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5141 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5142 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5143 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5144 | (adjusted_mode->crtc_vsync_start - 1) | |
5145 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5146 | ||
b5e508d4 PZ |
5147 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5148 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5149 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5150 | * bits. */ | |
5151 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5152 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5153 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5154 | ||
b0e77b9c PZ |
5155 | /* pipesrc controls the size that is scaled from, which should |
5156 | * always be the user's requested size. | |
5157 | */ | |
5158 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5159 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5160 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5161 | } |
5162 | ||
1bd1bd80 DV |
5163 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5164 | struct intel_crtc_config *pipe_config) | |
5165 | { | |
5166 | struct drm_device *dev = crtc->base.dev; | |
5167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5168 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5169 | uint32_t tmp; | |
5170 | ||
5171 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5172 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5173 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5174 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5175 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5176 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5177 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5178 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5179 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5180 | ||
5181 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5182 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5183 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5184 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5185 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5186 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5187 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5188 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5189 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5190 | ||
5191 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5192 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5193 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5194 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5195 | } | |
5196 | ||
5197 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5198 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5199 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5200 | ||
5201 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5202 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5203 | } |
5204 | ||
babea61d JB |
5205 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5206 | struct intel_crtc_config *pipe_config) | |
5207 | { | |
5208 | struct drm_crtc *crtc = &intel_crtc->base; | |
5209 | ||
5210 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5211 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5212 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5213 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5214 | ||
5215 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5216 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5217 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5218 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5219 | ||
5220 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5221 | ||
241bfc38 | 5222 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5223 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5224 | } | |
5225 | ||
84b046f3 DV |
5226 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5227 | { | |
5228 | struct drm_device *dev = intel_crtc->base.dev; | |
5229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5230 | uint32_t pipeconf; | |
5231 | ||
9f11a9e4 | 5232 | pipeconf = 0; |
84b046f3 | 5233 | |
67c72a12 DV |
5234 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5235 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5236 | pipeconf |= PIPECONF_ENABLE; | |
5237 | ||
cf532bb2 VS |
5238 | if (intel_crtc->config.double_wide) |
5239 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5240 | |
ff9ce46e DV |
5241 | /* only g4x and later have fancy bpc/dither controls */ |
5242 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5243 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5244 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5245 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5246 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5247 | |
ff9ce46e DV |
5248 | switch (intel_crtc->config.pipe_bpp) { |
5249 | case 18: | |
5250 | pipeconf |= PIPECONF_6BPC; | |
5251 | break; | |
5252 | case 24: | |
5253 | pipeconf |= PIPECONF_8BPC; | |
5254 | break; | |
5255 | case 30: | |
5256 | pipeconf |= PIPECONF_10BPC; | |
5257 | break; | |
5258 | default: | |
5259 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5260 | BUG(); | |
84b046f3 DV |
5261 | } |
5262 | } | |
5263 | ||
5264 | if (HAS_PIPE_CXSR(dev)) { | |
5265 | if (intel_crtc->lowfreq_avail) { | |
5266 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5267 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5268 | } else { | |
5269 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5270 | } |
5271 | } | |
5272 | ||
84b046f3 DV |
5273 | if (!IS_GEN2(dev) && |
5274 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5275 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5276 | else | |
5277 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5278 | ||
9f11a9e4 DV |
5279 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5280 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5281 | |
84b046f3 DV |
5282 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5283 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5284 | } | |
5285 | ||
f564048e | 5286 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5287 | int x, int y, |
94352cf9 | 5288 | struct drm_framebuffer *fb) |
79e53945 JB |
5289 | { |
5290 | struct drm_device *dev = crtc->dev; | |
5291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5293 | int pipe = intel_crtc->pipe; | |
80824003 | 5294 | int plane = intel_crtc->plane; |
c751ce4f | 5295 | int refclk, num_connectors = 0; |
652c393a | 5296 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5297 | u32 dspcntr; |
a16af721 | 5298 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5299 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5300 | struct intel_encoder *encoder; |
d4906093 | 5301 | const intel_limit_t *limit; |
5c3b82e2 | 5302 | int ret; |
79e53945 | 5303 | |
6c2b7c12 | 5304 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5305 | switch (encoder->type) { |
79e53945 JB |
5306 | case INTEL_OUTPUT_LVDS: |
5307 | is_lvds = true; | |
5308 | break; | |
e9fd1c02 JN |
5309 | case INTEL_OUTPUT_DSI: |
5310 | is_dsi = true; | |
5311 | break; | |
79e53945 | 5312 | } |
43565a06 | 5313 | |
c751ce4f | 5314 | num_connectors++; |
79e53945 JB |
5315 | } |
5316 | ||
f2335330 JN |
5317 | if (is_dsi) |
5318 | goto skip_dpll; | |
5319 | ||
5320 | if (!intel_crtc->config.clock_set) { | |
5321 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5322 | |
e9fd1c02 JN |
5323 | /* |
5324 | * Returns a set of divisors for the desired target clock with | |
5325 | * the given refclk, or FALSE. The returned values represent | |
5326 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5327 | * 2) / p1 / p2. | |
5328 | */ | |
5329 | limit = intel_limit(crtc, refclk); | |
5330 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5331 | intel_crtc->config.port_clock, | |
5332 | refclk, NULL, &clock); | |
f2335330 | 5333 | if (!ok) { |
e9fd1c02 JN |
5334 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5335 | return -EINVAL; | |
5336 | } | |
79e53945 | 5337 | |
f2335330 JN |
5338 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5339 | /* | |
5340 | * Ensure we match the reduced clock's P to the target | |
5341 | * clock. If the clocks don't match, we can't switch | |
5342 | * the display clock by using the FP0/FP1. In such case | |
5343 | * we will disable the LVDS downclock feature. | |
5344 | */ | |
5345 | has_reduced_clock = | |
5346 | dev_priv->display.find_dpll(limit, crtc, | |
5347 | dev_priv->lvds_downclock, | |
5348 | refclk, &clock, | |
5349 | &reduced_clock); | |
5350 | } | |
5351 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5352 | intel_crtc->config.dpll.n = clock.n; |
5353 | intel_crtc->config.dpll.m1 = clock.m1; | |
5354 | intel_crtc->config.dpll.m2 = clock.m2; | |
5355 | intel_crtc->config.dpll.p1 = clock.p1; | |
5356 | intel_crtc->config.dpll.p2 = clock.p2; | |
5357 | } | |
7026d4ac | 5358 | |
e9fd1c02 | 5359 | if (IS_GEN2(dev)) { |
8a654f3b | 5360 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5361 | has_reduced_clock ? &reduced_clock : NULL, |
5362 | num_connectors); | |
e9fd1c02 | 5363 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5364 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5365 | } else { |
f47709a9 | 5366 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5367 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5368 | num_connectors); |
e9fd1c02 | 5369 | } |
79e53945 | 5370 | |
f2335330 | 5371 | skip_dpll: |
79e53945 JB |
5372 | /* Set up the display plane register */ |
5373 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5374 | ||
da6ecc5d JB |
5375 | if (!IS_VALLEYVIEW(dev)) { |
5376 | if (pipe == 0) | |
5377 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5378 | else | |
5379 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5380 | } | |
79e53945 | 5381 | |
8a654f3b | 5382 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5383 | |
5384 | /* pipesrc and dspsize control the size that is scaled from, | |
5385 | * which should always be the user's requested size. | |
79e53945 | 5386 | */ |
929c77fb | 5387 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5388 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5389 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5390 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5391 | |
84b046f3 DV |
5392 | i9xx_set_pipeconf(intel_crtc); |
5393 | ||
f564048e EA |
5394 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5395 | POSTING_READ(DSPCNTR(plane)); | |
5396 | ||
94352cf9 | 5397 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5398 | |
f564048e EA |
5399 | return ret; |
5400 | } | |
5401 | ||
2fa2fe9a DV |
5402 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5403 | struct intel_crtc_config *pipe_config) | |
5404 | { | |
5405 | struct drm_device *dev = crtc->base.dev; | |
5406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5407 | uint32_t tmp; | |
5408 | ||
5409 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
5410 | if (!(tmp & PFIT_ENABLE)) |
5411 | return; | |
2fa2fe9a | 5412 | |
06922821 | 5413 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5414 | if (INTEL_INFO(dev)->gen < 4) { |
5415 | if (crtc->pipe != PIPE_B) | |
5416 | return; | |
2fa2fe9a DV |
5417 | } else { |
5418 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5419 | return; | |
5420 | } | |
5421 | ||
06922821 | 5422 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5423 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5424 | if (INTEL_INFO(dev)->gen < 5) | |
5425 | pipe_config->gmch_pfit.lvds_border_bits = | |
5426 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5427 | } | |
5428 | ||
acbec814 JB |
5429 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5430 | struct intel_crtc_config *pipe_config) | |
5431 | { | |
5432 | struct drm_device *dev = crtc->base.dev; | |
5433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5434 | int pipe = pipe_config->cpu_transcoder; | |
5435 | intel_clock_t clock; | |
5436 | u32 mdiv; | |
662c6ecb | 5437 | int refclk = 100000; |
acbec814 JB |
5438 | |
5439 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5440 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5441 | mutex_unlock(&dev_priv->dpio_lock); |
5442 | ||
5443 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5444 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5445 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5446 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5447 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5448 | ||
f646628b | 5449 | vlv_clock(refclk, &clock); |
acbec814 | 5450 | |
f646628b VS |
5451 | /* clock.dot is the fast clock */ |
5452 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5453 | } |
5454 | ||
0e8ffe1b DV |
5455 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5456 | struct intel_crtc_config *pipe_config) | |
5457 | { | |
5458 | struct drm_device *dev = crtc->base.dev; | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5460 | uint32_t tmp; | |
5461 | ||
e143a21c | 5462 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5463 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5464 | |
0e8ffe1b DV |
5465 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5466 | if (!(tmp & PIPECONF_ENABLE)) | |
5467 | return false; | |
5468 | ||
42571aef VS |
5469 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5470 | switch (tmp & PIPECONF_BPC_MASK) { | |
5471 | case PIPECONF_6BPC: | |
5472 | pipe_config->pipe_bpp = 18; | |
5473 | break; | |
5474 | case PIPECONF_8BPC: | |
5475 | pipe_config->pipe_bpp = 24; | |
5476 | break; | |
5477 | case PIPECONF_10BPC: | |
5478 | pipe_config->pipe_bpp = 30; | |
5479 | break; | |
5480 | default: | |
5481 | break; | |
5482 | } | |
5483 | } | |
5484 | ||
282740f7 VS |
5485 | if (INTEL_INFO(dev)->gen < 4) |
5486 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5487 | ||
1bd1bd80 DV |
5488 | intel_get_pipe_timings(crtc, pipe_config); |
5489 | ||
2fa2fe9a DV |
5490 | i9xx_get_pfit_config(crtc, pipe_config); |
5491 | ||
6c49f241 DV |
5492 | if (INTEL_INFO(dev)->gen >= 4) { |
5493 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5494 | pipe_config->pixel_multiplier = | |
5495 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5496 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5497 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5498 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5499 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5500 | pipe_config->pixel_multiplier = | |
5501 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5502 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5503 | } else { | |
5504 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5505 | * port and will be fixed up in the encoder->get_config | |
5506 | * function. */ | |
5507 | pipe_config->pixel_multiplier = 1; | |
5508 | } | |
8bcc2795 DV |
5509 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5510 | if (!IS_VALLEYVIEW(dev)) { | |
5511 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5512 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5513 | } else { |
5514 | /* Mask out read-only status bits. */ | |
5515 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5516 | DPLL_PORTC_READY_MASK | | |
5517 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5518 | } |
6c49f241 | 5519 | |
acbec814 JB |
5520 | if (IS_VALLEYVIEW(dev)) |
5521 | vlv_crtc_clock_get(crtc, pipe_config); | |
5522 | else | |
5523 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5524 | |
0e8ffe1b DV |
5525 | return true; |
5526 | } | |
5527 | ||
dde86e2d | 5528 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5529 | { |
5530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5531 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5532 | struct intel_encoder *encoder; |
74cfd7ac | 5533 | u32 val, final; |
13d83a67 | 5534 | bool has_lvds = false; |
199e5d79 | 5535 | bool has_cpu_edp = false; |
199e5d79 | 5536 | bool has_panel = false; |
99eb6a01 KP |
5537 | bool has_ck505 = false; |
5538 | bool can_ssc = false; | |
13d83a67 JB |
5539 | |
5540 | /* We need to take the global config into account */ | |
199e5d79 KP |
5541 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5542 | base.head) { | |
5543 | switch (encoder->type) { | |
5544 | case INTEL_OUTPUT_LVDS: | |
5545 | has_panel = true; | |
5546 | has_lvds = true; | |
5547 | break; | |
5548 | case INTEL_OUTPUT_EDP: | |
5549 | has_panel = true; | |
2de6905f | 5550 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5551 | has_cpu_edp = true; |
5552 | break; | |
13d83a67 JB |
5553 | } |
5554 | } | |
5555 | ||
99eb6a01 | 5556 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5557 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5558 | can_ssc = has_ck505; |
5559 | } else { | |
5560 | has_ck505 = false; | |
5561 | can_ssc = true; | |
5562 | } | |
5563 | ||
2de6905f ID |
5564 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5565 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5566 | |
5567 | /* Ironlake: try to setup display ref clock before DPLL | |
5568 | * enabling. This is only under driver's control after | |
5569 | * PCH B stepping, previous chipset stepping should be | |
5570 | * ignoring this setting. | |
5571 | */ | |
74cfd7ac CW |
5572 | val = I915_READ(PCH_DREF_CONTROL); |
5573 | ||
5574 | /* As we must carefully and slowly disable/enable each source in turn, | |
5575 | * compute the final state we want first and check if we need to | |
5576 | * make any changes at all. | |
5577 | */ | |
5578 | final = val; | |
5579 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5580 | if (has_ck505) | |
5581 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5582 | else | |
5583 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5584 | ||
5585 | final &= ~DREF_SSC_SOURCE_MASK; | |
5586 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5587 | final &= ~DREF_SSC1_ENABLE; | |
5588 | ||
5589 | if (has_panel) { | |
5590 | final |= DREF_SSC_SOURCE_ENABLE; | |
5591 | ||
5592 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5593 | final |= DREF_SSC1_ENABLE; | |
5594 | ||
5595 | if (has_cpu_edp) { | |
5596 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5597 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5598 | else | |
5599 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5600 | } else | |
5601 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5602 | } else { | |
5603 | final |= DREF_SSC_SOURCE_DISABLE; | |
5604 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5605 | } | |
5606 | ||
5607 | if (final == val) | |
5608 | return; | |
5609 | ||
13d83a67 | 5610 | /* Always enable nonspread source */ |
74cfd7ac | 5611 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5612 | |
99eb6a01 | 5613 | if (has_ck505) |
74cfd7ac | 5614 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5615 | else |
74cfd7ac | 5616 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5617 | |
199e5d79 | 5618 | if (has_panel) { |
74cfd7ac CW |
5619 | val &= ~DREF_SSC_SOURCE_MASK; |
5620 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5621 | |
199e5d79 | 5622 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5623 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5624 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5625 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5626 | } else |
74cfd7ac | 5627 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5628 | |
5629 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5630 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5631 | POSTING_READ(PCH_DREF_CONTROL); |
5632 | udelay(200); | |
5633 | ||
74cfd7ac | 5634 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5635 | |
5636 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5637 | if (has_cpu_edp) { |
99eb6a01 | 5638 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5639 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5640 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5641 | } |
13d83a67 | 5642 | else |
74cfd7ac | 5643 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5644 | } else |
74cfd7ac | 5645 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5646 | |
74cfd7ac | 5647 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5648 | POSTING_READ(PCH_DREF_CONTROL); |
5649 | udelay(200); | |
5650 | } else { | |
5651 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5652 | ||
74cfd7ac | 5653 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5654 | |
5655 | /* Turn off CPU output */ | |
74cfd7ac | 5656 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5657 | |
74cfd7ac | 5658 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5659 | POSTING_READ(PCH_DREF_CONTROL); |
5660 | udelay(200); | |
5661 | ||
5662 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5663 | val &= ~DREF_SSC_SOURCE_MASK; |
5664 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5665 | |
5666 | /* Turn off SSC1 */ | |
74cfd7ac | 5667 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5668 | |
74cfd7ac | 5669 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5670 | POSTING_READ(PCH_DREF_CONTROL); |
5671 | udelay(200); | |
5672 | } | |
74cfd7ac CW |
5673 | |
5674 | BUG_ON(val != final); | |
13d83a67 JB |
5675 | } |
5676 | ||
f31f2d55 | 5677 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5678 | { |
f31f2d55 | 5679 | uint32_t tmp; |
dde86e2d | 5680 | |
0ff066a9 PZ |
5681 | tmp = I915_READ(SOUTH_CHICKEN2); |
5682 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5683 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5684 | |
0ff066a9 PZ |
5685 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5686 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5687 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5688 | |
0ff066a9 PZ |
5689 | tmp = I915_READ(SOUTH_CHICKEN2); |
5690 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5691 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5692 | |
0ff066a9 PZ |
5693 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5694 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5695 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5696 | } |
5697 | ||
5698 | /* WaMPhyProgramming:hsw */ | |
5699 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5700 | { | |
5701 | uint32_t tmp; | |
dde86e2d PZ |
5702 | |
5703 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5704 | tmp &= ~(0xFF << 24); | |
5705 | tmp |= (0x12 << 24); | |
5706 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5707 | ||
dde86e2d PZ |
5708 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5709 | tmp |= (1 << 11); | |
5710 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5711 | ||
5712 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5713 | tmp |= (1 << 11); | |
5714 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5715 | ||
dde86e2d PZ |
5716 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5717 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5718 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5719 | ||
5720 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5721 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5722 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5723 | ||
0ff066a9 PZ |
5724 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5725 | tmp &= ~(7 << 13); | |
5726 | tmp |= (5 << 13); | |
5727 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5728 | |
0ff066a9 PZ |
5729 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5730 | tmp &= ~(7 << 13); | |
5731 | tmp |= (5 << 13); | |
5732 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5733 | |
5734 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5735 | tmp &= ~0xFF; | |
5736 | tmp |= 0x1C; | |
5737 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5738 | ||
5739 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5740 | tmp &= ~0xFF; | |
5741 | tmp |= 0x1C; | |
5742 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5743 | ||
5744 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5745 | tmp &= ~(0xFF << 16); | |
5746 | tmp |= (0x1C << 16); | |
5747 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5748 | ||
5749 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5750 | tmp &= ~(0xFF << 16); | |
5751 | tmp |= (0x1C << 16); | |
5752 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5753 | ||
0ff066a9 PZ |
5754 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5755 | tmp |= (1 << 27); | |
5756 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5757 | |
0ff066a9 PZ |
5758 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5759 | tmp |= (1 << 27); | |
5760 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5761 | |
0ff066a9 PZ |
5762 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5763 | tmp &= ~(0xF << 28); | |
5764 | tmp |= (4 << 28); | |
5765 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5766 | |
0ff066a9 PZ |
5767 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5768 | tmp &= ~(0xF << 28); | |
5769 | tmp |= (4 << 28); | |
5770 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5771 | } |
5772 | ||
2fa86a1f PZ |
5773 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5774 | * Programming" based on the parameters passed: | |
5775 | * - Sequence to enable CLKOUT_DP | |
5776 | * - Sequence to enable CLKOUT_DP without spread | |
5777 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5778 | */ | |
5779 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5780 | bool with_fdi) | |
f31f2d55 PZ |
5781 | { |
5782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5783 | uint32_t reg, tmp; |
5784 | ||
5785 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5786 | with_spread = true; | |
5787 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5788 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5789 | with_fdi = false; | |
f31f2d55 PZ |
5790 | |
5791 | mutex_lock(&dev_priv->dpio_lock); | |
5792 | ||
5793 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5794 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5795 | tmp |= SBI_SSCCTL_PATHALT; | |
5796 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5797 | ||
5798 | udelay(24); | |
5799 | ||
2fa86a1f PZ |
5800 | if (with_spread) { |
5801 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5802 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5803 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5804 | |
2fa86a1f PZ |
5805 | if (with_fdi) { |
5806 | lpt_reset_fdi_mphy(dev_priv); | |
5807 | lpt_program_fdi_mphy(dev_priv); | |
5808 | } | |
5809 | } | |
dde86e2d | 5810 | |
2fa86a1f PZ |
5811 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5812 | SBI_GEN0 : SBI_DBUFF0; | |
5813 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5814 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5815 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5816 | |
5817 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5818 | } |
5819 | ||
47701c3b PZ |
5820 | /* Sequence to disable CLKOUT_DP */ |
5821 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5822 | { | |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5824 | uint32_t reg, tmp; | |
5825 | ||
5826 | mutex_lock(&dev_priv->dpio_lock); | |
5827 | ||
5828 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5829 | SBI_GEN0 : SBI_DBUFF0; | |
5830 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5831 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5832 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5833 | ||
5834 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5835 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5836 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5837 | tmp |= SBI_SSCCTL_PATHALT; | |
5838 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5839 | udelay(32); | |
5840 | } | |
5841 | tmp |= SBI_SSCCTL_DISABLE; | |
5842 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5843 | } | |
5844 | ||
5845 | mutex_unlock(&dev_priv->dpio_lock); | |
5846 | } | |
5847 | ||
bf8fa3d3 PZ |
5848 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5849 | { | |
5850 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5851 | struct intel_encoder *encoder; | |
5852 | bool has_vga = false; | |
5853 | ||
5854 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5855 | switch (encoder->type) { | |
5856 | case INTEL_OUTPUT_ANALOG: | |
5857 | has_vga = true; | |
5858 | break; | |
5859 | } | |
5860 | } | |
5861 | ||
47701c3b PZ |
5862 | if (has_vga) |
5863 | lpt_enable_clkout_dp(dev, true, true); | |
5864 | else | |
5865 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5866 | } |
5867 | ||
dde86e2d PZ |
5868 | /* |
5869 | * Initialize reference clocks when the driver loads | |
5870 | */ | |
5871 | void intel_init_pch_refclk(struct drm_device *dev) | |
5872 | { | |
5873 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5874 | ironlake_init_pch_refclk(dev); | |
5875 | else if (HAS_PCH_LPT(dev)) | |
5876 | lpt_init_pch_refclk(dev); | |
5877 | } | |
5878 | ||
d9d444cb JB |
5879 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5880 | { | |
5881 | struct drm_device *dev = crtc->dev; | |
5882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5883 | struct intel_encoder *encoder; | |
d9d444cb JB |
5884 | int num_connectors = 0; |
5885 | bool is_lvds = false; | |
5886 | ||
6c2b7c12 | 5887 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5888 | switch (encoder->type) { |
5889 | case INTEL_OUTPUT_LVDS: | |
5890 | is_lvds = true; | |
5891 | break; | |
d9d444cb JB |
5892 | } |
5893 | num_connectors++; | |
5894 | } | |
5895 | ||
5896 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5897 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5898 | dev_priv->vbt.lvds_ssc_freq); |
5899 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5900 | } |
5901 | ||
5902 | return 120000; | |
5903 | } | |
5904 | ||
6ff93609 | 5905 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5906 | { |
c8203565 | 5907 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5909 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5910 | uint32_t val; |
5911 | ||
78114071 | 5912 | val = 0; |
c8203565 | 5913 | |
965e0c48 | 5914 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5915 | case 18: |
dfd07d72 | 5916 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5917 | break; |
5918 | case 24: | |
dfd07d72 | 5919 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5920 | break; |
5921 | case 30: | |
dfd07d72 | 5922 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5923 | break; |
5924 | case 36: | |
dfd07d72 | 5925 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5926 | break; |
5927 | default: | |
cc769b62 PZ |
5928 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5929 | BUG(); | |
c8203565 PZ |
5930 | } |
5931 | ||
d8b32247 | 5932 | if (intel_crtc->config.dither) |
c8203565 PZ |
5933 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5934 | ||
6ff93609 | 5935 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5936 | val |= PIPECONF_INTERLACED_ILK; |
5937 | else | |
5938 | val |= PIPECONF_PROGRESSIVE; | |
5939 | ||
50f3b016 | 5940 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5941 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5942 | |
c8203565 PZ |
5943 | I915_WRITE(PIPECONF(pipe), val); |
5944 | POSTING_READ(PIPECONF(pipe)); | |
5945 | } | |
5946 | ||
86d3efce VS |
5947 | /* |
5948 | * Set up the pipe CSC unit. | |
5949 | * | |
5950 | * Currently only full range RGB to limited range RGB conversion | |
5951 | * is supported, but eventually this should handle various | |
5952 | * RGB<->YCbCr scenarios as well. | |
5953 | */ | |
50f3b016 | 5954 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5955 | { |
5956 | struct drm_device *dev = crtc->dev; | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5959 | int pipe = intel_crtc->pipe; | |
5960 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5961 | ||
5962 | /* | |
5963 | * TODO: Check what kind of values actually come out of the pipe | |
5964 | * with these coeff/postoff values and adjust to get the best | |
5965 | * accuracy. Perhaps we even need to take the bpc value into | |
5966 | * consideration. | |
5967 | */ | |
5968 | ||
50f3b016 | 5969 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5970 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5971 | ||
5972 | /* | |
5973 | * GY/GU and RY/RU should be the other way around according | |
5974 | * to BSpec, but reality doesn't agree. Just set them up in | |
5975 | * a way that results in the correct picture. | |
5976 | */ | |
5977 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5978 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5979 | ||
5980 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5981 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5982 | ||
5983 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5984 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5985 | ||
5986 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5987 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5988 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5989 | ||
5990 | if (INTEL_INFO(dev)->gen > 6) { | |
5991 | uint16_t postoff = 0; | |
5992 | ||
50f3b016 | 5993 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5994 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5995 | ||
5996 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5997 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5998 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5999 | ||
6000 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6001 | } else { | |
6002 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6003 | ||
50f3b016 | 6004 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6005 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6006 | ||
6007 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6008 | } | |
6009 | } | |
6010 | ||
6ff93609 | 6011 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6012 | { |
756f85cf PZ |
6013 | struct drm_device *dev = crtc->dev; |
6014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6015 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6016 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6017 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6018 | uint32_t val; |
6019 | ||
3eff4faa | 6020 | val = 0; |
ee2b0b38 | 6021 | |
756f85cf | 6022 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6023 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6024 | ||
6ff93609 | 6025 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6026 | val |= PIPECONF_INTERLACED_ILK; |
6027 | else | |
6028 | val |= PIPECONF_PROGRESSIVE; | |
6029 | ||
702e7a56 PZ |
6030 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6031 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6032 | |
6033 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6034 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6035 | |
6036 | if (IS_BROADWELL(dev)) { | |
6037 | val = 0; | |
6038 | ||
6039 | switch (intel_crtc->config.pipe_bpp) { | |
6040 | case 18: | |
6041 | val |= PIPEMISC_DITHER_6_BPC; | |
6042 | break; | |
6043 | case 24: | |
6044 | val |= PIPEMISC_DITHER_8_BPC; | |
6045 | break; | |
6046 | case 30: | |
6047 | val |= PIPEMISC_DITHER_10_BPC; | |
6048 | break; | |
6049 | case 36: | |
6050 | val |= PIPEMISC_DITHER_12_BPC; | |
6051 | break; | |
6052 | default: | |
6053 | /* Case prevented by pipe_config_set_bpp. */ | |
6054 | BUG(); | |
6055 | } | |
6056 | ||
6057 | if (intel_crtc->config.dither) | |
6058 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6059 | ||
6060 | I915_WRITE(PIPEMISC(pipe), val); | |
6061 | } | |
ee2b0b38 PZ |
6062 | } |
6063 | ||
6591c6e4 | 6064 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6065 | intel_clock_t *clock, |
6066 | bool *has_reduced_clock, | |
6067 | intel_clock_t *reduced_clock) | |
6068 | { | |
6069 | struct drm_device *dev = crtc->dev; | |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6071 | struct intel_encoder *intel_encoder; | |
6072 | int refclk; | |
d4906093 | 6073 | const intel_limit_t *limit; |
a16af721 | 6074 | bool ret, is_lvds = false; |
79e53945 | 6075 | |
6591c6e4 PZ |
6076 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6077 | switch (intel_encoder->type) { | |
79e53945 JB |
6078 | case INTEL_OUTPUT_LVDS: |
6079 | is_lvds = true; | |
6080 | break; | |
79e53945 JB |
6081 | } |
6082 | } | |
6083 | ||
d9d444cb | 6084 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6085 | |
d4906093 ML |
6086 | /* |
6087 | * Returns a set of divisors for the desired target clock with the given | |
6088 | * refclk, or FALSE. The returned values represent the clock equation: | |
6089 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6090 | */ | |
1b894b59 | 6091 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6092 | ret = dev_priv->display.find_dpll(limit, crtc, |
6093 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6094 | refclk, NULL, clock); |
6591c6e4 PZ |
6095 | if (!ret) |
6096 | return false; | |
cda4b7d3 | 6097 | |
ddc9003c | 6098 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6099 | /* |
6100 | * Ensure we match the reduced clock's P to the target clock. | |
6101 | * If the clocks don't match, we can't switch the display clock | |
6102 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6103 | * downclock feature. | |
6104 | */ | |
ee9300bb DV |
6105 | *has_reduced_clock = |
6106 | dev_priv->display.find_dpll(limit, crtc, | |
6107 | dev_priv->lvds_downclock, | |
6108 | refclk, clock, | |
6109 | reduced_clock); | |
652c393a | 6110 | } |
61e9653f | 6111 | |
6591c6e4 PZ |
6112 | return true; |
6113 | } | |
6114 | ||
d4b1931c PZ |
6115 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6116 | { | |
6117 | /* | |
6118 | * Account for spread spectrum to avoid | |
6119 | * oversubscribing the link. Max center spread | |
6120 | * is 2.5%; use 5% for safety's sake. | |
6121 | */ | |
6122 | u32 bps = target_clock * bpp * 21 / 20; | |
6123 | return bps / (link_bw * 8) + 1; | |
6124 | } | |
6125 | ||
7429e9d4 | 6126 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6127 | { |
7429e9d4 | 6128 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6129 | } |
6130 | ||
de13a2e3 | 6131 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6132 | u32 *fp, |
9a7c7890 | 6133 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6134 | { |
de13a2e3 | 6135 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6136 | struct drm_device *dev = crtc->dev; |
6137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6138 | struct intel_encoder *intel_encoder; |
6139 | uint32_t dpll; | |
6cc5f341 | 6140 | int factor, num_connectors = 0; |
09ede541 | 6141 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6142 | |
de13a2e3 PZ |
6143 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6144 | switch (intel_encoder->type) { | |
79e53945 JB |
6145 | case INTEL_OUTPUT_LVDS: |
6146 | is_lvds = true; | |
6147 | break; | |
6148 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6149 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6150 | is_sdvo = true; |
79e53945 | 6151 | break; |
79e53945 | 6152 | } |
43565a06 | 6153 | |
c751ce4f | 6154 | num_connectors++; |
79e53945 | 6155 | } |
79e53945 | 6156 | |
c1858123 | 6157 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6158 | factor = 21; |
6159 | if (is_lvds) { | |
6160 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 6161 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 6162 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6163 | factor = 25; |
09ede541 | 6164 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6165 | factor = 20; |
c1858123 | 6166 | |
7429e9d4 | 6167 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6168 | *fp |= FP_CB_TUNE; |
2c07245f | 6169 | |
9a7c7890 DV |
6170 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6171 | *fp2 |= FP_CB_TUNE; | |
6172 | ||
5eddb70b | 6173 | dpll = 0; |
2c07245f | 6174 | |
a07d6787 EA |
6175 | if (is_lvds) |
6176 | dpll |= DPLLB_MODE_LVDS; | |
6177 | else | |
6178 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6179 | |
ef1b460d DV |
6180 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6181 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6182 | |
6183 | if (is_sdvo) | |
4a33e48d | 6184 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6185 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6186 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6187 | |
a07d6787 | 6188 | /* compute bitmask from p1 value */ |
7429e9d4 | 6189 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6190 | /* also FPA1 */ |
7429e9d4 | 6191 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6192 | |
7429e9d4 | 6193 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6194 | case 5: |
6195 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6196 | break; | |
6197 | case 7: | |
6198 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6199 | break; | |
6200 | case 10: | |
6201 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6202 | break; | |
6203 | case 14: | |
6204 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6205 | break; | |
79e53945 JB |
6206 | } |
6207 | ||
b4c09f3b | 6208 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6209 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6210 | else |
6211 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6212 | ||
959e16d6 | 6213 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6214 | } |
6215 | ||
6216 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6217 | int x, int y, |
6218 | struct drm_framebuffer *fb) | |
6219 | { | |
6220 | struct drm_device *dev = crtc->dev; | |
6221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6223 | int pipe = intel_crtc->pipe; | |
6224 | int plane = intel_crtc->plane; | |
6225 | int num_connectors = 0; | |
6226 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6227 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6228 | bool ok, has_reduced_clock = false; |
8b47047b | 6229 | bool is_lvds = false; |
de13a2e3 | 6230 | struct intel_encoder *encoder; |
e2b78267 | 6231 | struct intel_shared_dpll *pll; |
de13a2e3 | 6232 | int ret; |
de13a2e3 PZ |
6233 | |
6234 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6235 | switch (encoder->type) { | |
6236 | case INTEL_OUTPUT_LVDS: | |
6237 | is_lvds = true; | |
6238 | break; | |
de13a2e3 PZ |
6239 | } |
6240 | ||
6241 | num_connectors++; | |
a07d6787 | 6242 | } |
79e53945 | 6243 | |
5dc5298b PZ |
6244 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6245 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6246 | |
ff9a6750 | 6247 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6248 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6249 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6250 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6251 | return -EINVAL; | |
79e53945 | 6252 | } |
f47709a9 DV |
6253 | /* Compat-code for transition, will disappear. */ |
6254 | if (!intel_crtc->config.clock_set) { | |
6255 | intel_crtc->config.dpll.n = clock.n; | |
6256 | intel_crtc->config.dpll.m1 = clock.m1; | |
6257 | intel_crtc->config.dpll.m2 = clock.m2; | |
6258 | intel_crtc->config.dpll.p1 = clock.p1; | |
6259 | intel_crtc->config.dpll.p2 = clock.p2; | |
6260 | } | |
79e53945 | 6261 | |
5dc5298b | 6262 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6263 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6264 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6265 | if (has_reduced_clock) |
7429e9d4 | 6266 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6267 | |
7429e9d4 | 6268 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6269 | &fp, &reduced_clock, |
6270 | has_reduced_clock ? &fp2 : NULL); | |
6271 | ||
959e16d6 | 6272 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6273 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6274 | if (has_reduced_clock) | |
6275 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6276 | else | |
6277 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6278 | ||
b89a1d39 | 6279 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6280 | if (pll == NULL) { |
84f44ce7 VS |
6281 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6282 | pipe_name(pipe)); | |
4b645f14 JB |
6283 | return -EINVAL; |
6284 | } | |
ee7b9f93 | 6285 | } else |
e72f9fbf | 6286 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6287 | |
03afc4a2 DV |
6288 | if (intel_crtc->config.has_dp_encoder) |
6289 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6290 | |
bcd644e0 DV |
6291 | if (is_lvds && has_reduced_clock && i915_powersave) |
6292 | intel_crtc->lowfreq_avail = true; | |
6293 | else | |
6294 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6295 | |
8a654f3b | 6296 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6297 | |
ca3a0ff8 | 6298 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6299 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6300 | &intel_crtc->config.fdi_m_n); | |
6301 | } | |
2c07245f | 6302 | |
6ff93609 | 6303 | ironlake_set_pipeconf(crtc); |
79e53945 | 6304 | |
a1f9e77e PZ |
6305 | /* Set up the display plane register */ |
6306 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6307 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6308 | |
94352cf9 | 6309 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6310 | |
1857e1da | 6311 | return ret; |
79e53945 JB |
6312 | } |
6313 | ||
eb14cb74 VS |
6314 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6315 | struct intel_link_m_n *m_n) | |
6316 | { | |
6317 | struct drm_device *dev = crtc->base.dev; | |
6318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6319 | enum pipe pipe = crtc->pipe; | |
6320 | ||
6321 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6322 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6323 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6324 | & ~TU_SIZE_MASK; | |
6325 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6326 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6327 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6328 | } | |
6329 | ||
6330 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6331 | enum transcoder transcoder, | |
6332 | struct intel_link_m_n *m_n) | |
72419203 DV |
6333 | { |
6334 | struct drm_device *dev = crtc->base.dev; | |
6335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6336 | enum pipe pipe = crtc->pipe; |
72419203 | 6337 | |
eb14cb74 VS |
6338 | if (INTEL_INFO(dev)->gen >= 5) { |
6339 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6340 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6341 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6342 | & ~TU_SIZE_MASK; | |
6343 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6344 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6345 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6346 | } else { | |
6347 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6348 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6349 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6350 | & ~TU_SIZE_MASK; | |
6351 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6352 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6353 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6354 | } | |
6355 | } | |
6356 | ||
6357 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6358 | struct intel_crtc_config *pipe_config) | |
6359 | { | |
6360 | if (crtc->config.has_pch_encoder) | |
6361 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6362 | else | |
6363 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6364 | &pipe_config->dp_m_n); | |
6365 | } | |
72419203 | 6366 | |
eb14cb74 VS |
6367 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6368 | struct intel_crtc_config *pipe_config) | |
6369 | { | |
6370 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6371 | &pipe_config->fdi_m_n); | |
72419203 DV |
6372 | } |
6373 | ||
2fa2fe9a DV |
6374 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6375 | struct intel_crtc_config *pipe_config) | |
6376 | { | |
6377 | struct drm_device *dev = crtc->base.dev; | |
6378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6379 | uint32_t tmp; | |
6380 | ||
6381 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6382 | ||
6383 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6384 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6385 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6386 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6387 | |
6388 | /* We currently do not free assignements of panel fitters on | |
6389 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6390 | * differentiates them) so just WARN about this case for now. */ | |
6391 | if (IS_GEN7(dev)) { | |
6392 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6393 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6394 | } | |
2fa2fe9a | 6395 | } |
79e53945 JB |
6396 | } |
6397 | ||
0e8ffe1b DV |
6398 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6399 | struct intel_crtc_config *pipe_config) | |
6400 | { | |
6401 | struct drm_device *dev = crtc->base.dev; | |
6402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6403 | uint32_t tmp; | |
6404 | ||
e143a21c | 6405 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6406 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6407 | |
0e8ffe1b DV |
6408 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6409 | if (!(tmp & PIPECONF_ENABLE)) | |
6410 | return false; | |
6411 | ||
42571aef VS |
6412 | switch (tmp & PIPECONF_BPC_MASK) { |
6413 | case PIPECONF_6BPC: | |
6414 | pipe_config->pipe_bpp = 18; | |
6415 | break; | |
6416 | case PIPECONF_8BPC: | |
6417 | pipe_config->pipe_bpp = 24; | |
6418 | break; | |
6419 | case PIPECONF_10BPC: | |
6420 | pipe_config->pipe_bpp = 30; | |
6421 | break; | |
6422 | case PIPECONF_12BPC: | |
6423 | pipe_config->pipe_bpp = 36; | |
6424 | break; | |
6425 | default: | |
6426 | break; | |
6427 | } | |
6428 | ||
ab9412ba | 6429 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6430 | struct intel_shared_dpll *pll; |
6431 | ||
88adfff1 DV |
6432 | pipe_config->has_pch_encoder = true; |
6433 | ||
627eb5a3 DV |
6434 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6435 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6436 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6437 | |
6438 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6439 | |
c0d43d62 | 6440 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6441 | pipe_config->shared_dpll = |
6442 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6443 | } else { |
6444 | tmp = I915_READ(PCH_DPLL_SEL); | |
6445 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6446 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6447 | else | |
6448 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6449 | } | |
66e985c0 DV |
6450 | |
6451 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6452 | ||
6453 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6454 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6455 | |
6456 | tmp = pipe_config->dpll_hw_state.dpll; | |
6457 | pipe_config->pixel_multiplier = | |
6458 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6459 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6460 | |
6461 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6462 | } else { |
6463 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6464 | } |
6465 | ||
1bd1bd80 DV |
6466 | intel_get_pipe_timings(crtc, pipe_config); |
6467 | ||
2fa2fe9a DV |
6468 | ironlake_get_pfit_config(crtc, pipe_config); |
6469 | ||
0e8ffe1b DV |
6470 | return true; |
6471 | } | |
6472 | ||
be256dc7 PZ |
6473 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6474 | { | |
6475 | struct drm_device *dev = dev_priv->dev; | |
6476 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6477 | struct intel_crtc *crtc; | |
6478 | unsigned long irqflags; | |
bd633a7c | 6479 | uint32_t val; |
be256dc7 PZ |
6480 | |
6481 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6482 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | |
6483 | pipe_name(crtc->pipe)); | |
6484 | ||
6485 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6486 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6487 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6488 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6489 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6490 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6491 | "CPU PWM1 enabled\n"); | |
6492 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6493 | "CPU PWM2 enabled\n"); | |
6494 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6495 | "PCH PWM1 enabled\n"); | |
6496 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6497 | "Utility pin enabled\n"); | |
6498 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6499 | ||
6500 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6501 | val = I915_READ(DEIMR); | |
6502 | WARN((val & ~DE_PCH_EVENT_IVB) != val, | |
6503 | "Unexpected DEIMR bits enabled: 0x%x\n", val); | |
6504 | val = I915_READ(SDEIMR); | |
bd633a7c | 6505 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6506 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6507 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6508 | } | |
6509 | ||
6510 | /* | |
6511 | * This function implements pieces of two sequences from BSpec: | |
6512 | * - Sequence for display software to disable LCPLL | |
6513 | * - Sequence for display software to allow package C8+ | |
6514 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6515 | * register. Callers should take care of disabling all the display engine | |
6516 | * functions, doing the mode unset, fixing interrupts, etc. | |
6517 | */ | |
6ff58d53 PZ |
6518 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6519 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6520 | { |
6521 | uint32_t val; | |
6522 | ||
6523 | assert_can_disable_lcpll(dev_priv); | |
6524 | ||
6525 | val = I915_READ(LCPLL_CTL); | |
6526 | ||
6527 | if (switch_to_fclk) { | |
6528 | val |= LCPLL_CD_SOURCE_FCLK; | |
6529 | I915_WRITE(LCPLL_CTL, val); | |
6530 | ||
6531 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6532 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6533 | DRM_ERROR("Switching to FCLK failed\n"); | |
6534 | ||
6535 | val = I915_READ(LCPLL_CTL); | |
6536 | } | |
6537 | ||
6538 | val |= LCPLL_PLL_DISABLE; | |
6539 | I915_WRITE(LCPLL_CTL, val); | |
6540 | POSTING_READ(LCPLL_CTL); | |
6541 | ||
6542 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6543 | DRM_ERROR("LCPLL still locked\n"); | |
6544 | ||
6545 | val = I915_READ(D_COMP); | |
6546 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6547 | mutex_lock(&dev_priv->rps.hw_lock); |
6548 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6549 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6550 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6551 | POSTING_READ(D_COMP); |
6552 | ndelay(100); | |
6553 | ||
6554 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6555 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6556 | ||
6557 | if (allow_power_down) { | |
6558 | val = I915_READ(LCPLL_CTL); | |
6559 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6560 | I915_WRITE(LCPLL_CTL, val); | |
6561 | POSTING_READ(LCPLL_CTL); | |
6562 | } | |
6563 | } | |
6564 | ||
6565 | /* | |
6566 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6567 | * source. | |
6568 | */ | |
6ff58d53 | 6569 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6570 | { |
6571 | uint32_t val; | |
6572 | ||
6573 | val = I915_READ(LCPLL_CTL); | |
6574 | ||
6575 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6576 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6577 | return; | |
6578 | ||
215733fa PZ |
6579 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6580 | * we'll hang the machine! */ | |
6581 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
6582 | ||
be256dc7 PZ |
6583 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6584 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6585 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6586 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6587 | } |
6588 | ||
6589 | val = I915_READ(D_COMP); | |
6590 | val |= D_COMP_COMP_FORCE; | |
6591 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6592 | mutex_lock(&dev_priv->rps.hw_lock); |
6593 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6594 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6595 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6596 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6597 | |
6598 | val = I915_READ(LCPLL_CTL); | |
6599 | val &= ~LCPLL_PLL_DISABLE; | |
6600 | I915_WRITE(LCPLL_CTL, val); | |
6601 | ||
6602 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6603 | DRM_ERROR("LCPLL not locked yet\n"); | |
6604 | ||
6605 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6606 | val = I915_READ(LCPLL_CTL); | |
6607 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6608 | I915_WRITE(LCPLL_CTL, val); | |
6609 | ||
6610 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6611 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6612 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6613 | } | |
215733fa PZ |
6614 | |
6615 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
be256dc7 PZ |
6616 | } |
6617 | ||
c67a470b PZ |
6618 | void hsw_enable_pc8_work(struct work_struct *__work) |
6619 | { | |
6620 | struct drm_i915_private *dev_priv = | |
6621 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6622 | pc8.enable_work); | |
6623 | struct drm_device *dev = dev_priv->dev; | |
6624 | uint32_t val; | |
6625 | ||
6626 | if (dev_priv->pc8.enabled) | |
6627 | return; | |
6628 | ||
6629 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6630 | ||
6631 | dev_priv->pc8.enabled = true; | |
6632 | ||
6633 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6634 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6635 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6636 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6637 | } | |
6638 | ||
6639 | lpt_disable_clkout_dp(dev); | |
6640 | hsw_pc8_disable_interrupts(dev); | |
6641 | hsw_disable_lcpll(dev_priv, true, true); | |
6642 | } | |
6643 | ||
6644 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6645 | { | |
6646 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6647 | WARN(dev_priv->pc8.disable_count < 1, | |
6648 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6649 | ||
6650 | dev_priv->pc8.disable_count--; | |
6651 | if (dev_priv->pc8.disable_count != 0) | |
6652 | return; | |
6653 | ||
6654 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6655 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6656 | } |
6657 | ||
6658 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6659 | { | |
6660 | struct drm_device *dev = dev_priv->dev; | |
6661 | uint32_t val; | |
6662 | ||
6663 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6664 | WARN(dev_priv->pc8.disable_count < 0, | |
6665 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6666 | ||
6667 | dev_priv->pc8.disable_count++; | |
6668 | if (dev_priv->pc8.disable_count != 1) | |
6669 | return; | |
6670 | ||
6671 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); | |
6672 | if (!dev_priv->pc8.enabled) | |
6673 | return; | |
6674 | ||
6675 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6676 | ||
6677 | hsw_restore_lcpll(dev_priv); | |
6678 | hsw_pc8_restore_interrupts(dev); | |
6679 | lpt_init_pch_refclk(dev); | |
6680 | ||
6681 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6682 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6683 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6684 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6685 | } | |
6686 | ||
6687 | intel_prepare_ddi(dev); | |
6688 | i915_gem_init_swizzling(dev); | |
6689 | mutex_lock(&dev_priv->rps.hw_lock); | |
6690 | gen6_update_ring_freq(dev); | |
6691 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6692 | dev_priv->pc8.enabled = false; | |
6693 | } | |
6694 | ||
6695 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6696 | { | |
6697 | mutex_lock(&dev_priv->pc8.lock); | |
6698 | __hsw_enable_package_c8(dev_priv); | |
6699 | mutex_unlock(&dev_priv->pc8.lock); | |
6700 | } | |
6701 | ||
6702 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6703 | { | |
6704 | mutex_lock(&dev_priv->pc8.lock); | |
6705 | __hsw_disable_package_c8(dev_priv); | |
6706 | mutex_unlock(&dev_priv->pc8.lock); | |
6707 | } | |
6708 | ||
6709 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6710 | { | |
6711 | struct drm_device *dev = dev_priv->dev; | |
6712 | struct intel_crtc *crtc; | |
6713 | uint32_t val; | |
6714 | ||
6715 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6716 | if (crtc->base.enabled) | |
6717 | return false; | |
6718 | ||
6719 | /* This case is still possible since we have the i915.disable_power_well | |
6720 | * parameter and also the KVMr or something else might be requesting the | |
6721 | * power well. */ | |
6722 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6723 | if (val != 0) { | |
6724 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6725 | return false; | |
6726 | } | |
6727 | ||
6728 | return true; | |
6729 | } | |
6730 | ||
6731 | /* Since we're called from modeset_global_resources there's no way to | |
6732 | * symmetrically increase and decrease the refcount, so we use | |
6733 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6734 | * or not. | |
6735 | */ | |
6736 | static void hsw_update_package_c8(struct drm_device *dev) | |
6737 | { | |
6738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6739 | bool allow; | |
6740 | ||
6741 | if (!i915_enable_pc8) | |
6742 | return; | |
6743 | ||
6744 | mutex_lock(&dev_priv->pc8.lock); | |
6745 | ||
6746 | allow = hsw_can_enable_package_c8(dev_priv); | |
6747 | ||
6748 | if (allow == dev_priv->pc8.requirements_met) | |
6749 | goto done; | |
6750 | ||
6751 | dev_priv->pc8.requirements_met = allow; | |
6752 | ||
6753 | if (allow) | |
6754 | __hsw_enable_package_c8(dev_priv); | |
6755 | else | |
6756 | __hsw_disable_package_c8(dev_priv); | |
6757 | ||
6758 | done: | |
6759 | mutex_unlock(&dev_priv->pc8.lock); | |
6760 | } | |
6761 | ||
6762 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6763 | { | |
3458122e | 6764 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6765 | if (!dev_priv->pc8.gpu_idle) { |
6766 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6767 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6768 | } |
3458122e | 6769 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6770 | } |
6771 | ||
6772 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6773 | { | |
3458122e | 6774 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6775 | if (dev_priv->pc8.gpu_idle) { |
6776 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6777 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6778 | } |
3458122e | 6779 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6780 | } |
6781 | ||
6efdf354 ID |
6782 | #define for_each_power_domain(domain, mask) \ |
6783 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6784 | if ((1 << (domain)) & (mask)) | |
6785 | ||
6786 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6787 | enum pipe pipe, bool pfit_enabled) | |
6788 | { | |
6789 | unsigned long mask; | |
6790 | enum transcoder transcoder; | |
6791 | ||
6792 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6793 | ||
6794 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6795 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6796 | if (pfit_enabled) | |
6797 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6798 | ||
6799 | return mask; | |
6800 | } | |
6801 | ||
baa70707 ID |
6802 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6803 | { | |
6804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6805 | ||
6806 | if (dev_priv->power_domains.init_power_on == enable) | |
6807 | return; | |
6808 | ||
6809 | if (enable) | |
6810 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6811 | else | |
6812 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6813 | ||
6814 | dev_priv->power_domains.init_power_on = enable; | |
6815 | } | |
6816 | ||
4f074129 | 6817 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6818 | { |
6efdf354 | 6819 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6820 | struct intel_crtc *crtc; |
d6dd9eb1 | 6821 | |
6efdf354 ID |
6822 | /* |
6823 | * First get all needed power domains, then put all unneeded, to avoid | |
6824 | * any unnecessary toggling of the power wells. | |
6825 | */ | |
d6dd9eb1 | 6826 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6827 | enum intel_display_power_domain domain; |
6828 | ||
e7a639c4 DV |
6829 | if (!crtc->base.enabled) |
6830 | continue; | |
d6dd9eb1 | 6831 | |
6efdf354 ID |
6832 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6833 | crtc->pipe, | |
6834 | crtc->config.pch_pfit.enabled); | |
6835 | ||
6836 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6837 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6838 | } |
6839 | ||
6efdf354 ID |
6840 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6841 | enum intel_display_power_domain domain; | |
6842 | ||
6843 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6844 | intel_display_power_put(dev, domain); | |
6845 | ||
6846 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6847 | } | |
baa70707 ID |
6848 | |
6849 | intel_display_set_init_power(dev, false); | |
4f074129 | 6850 | } |
c67a470b | 6851 | |
4f074129 ID |
6852 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6853 | { | |
6854 | modeset_update_power_wells(dev); | |
c67a470b | 6855 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6856 | } |
6857 | ||
09b4ddf9 | 6858 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6859 | int x, int y, |
6860 | struct drm_framebuffer *fb) | |
6861 | { | |
6862 | struct drm_device *dev = crtc->dev; | |
6863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6864 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6865 | int plane = intel_crtc->plane; |
09b4ddf9 | 6866 | int ret; |
09b4ddf9 | 6867 | |
ff9a6750 | 6868 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6869 | return -EINVAL; |
6870 | ||
03afc4a2 DV |
6871 | if (intel_crtc->config.has_dp_encoder) |
6872 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6873 | |
6874 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6875 | |
8a654f3b | 6876 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6877 | |
ca3a0ff8 | 6878 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6879 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6880 | &intel_crtc->config.fdi_m_n); | |
6881 | } | |
09b4ddf9 | 6882 | |
6ff93609 | 6883 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6884 | |
50f3b016 | 6885 | intel_set_pipe_csc(crtc); |
86d3efce | 6886 | |
09b4ddf9 | 6887 | /* Set up the display plane register */ |
86d3efce | 6888 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6889 | POSTING_READ(DSPCNTR(plane)); |
6890 | ||
6891 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6892 | ||
1f803ee5 | 6893 | return ret; |
79e53945 JB |
6894 | } |
6895 | ||
0e8ffe1b DV |
6896 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6897 | struct intel_crtc_config *pipe_config) | |
6898 | { | |
6899 | struct drm_device *dev = crtc->base.dev; | |
6900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6901 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6902 | uint32_t tmp; |
6903 | ||
e143a21c | 6904 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6905 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6906 | ||
eccb140b DV |
6907 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6908 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6909 | enum pipe trans_edp_pipe; | |
6910 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6911 | default: | |
6912 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6913 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6914 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6915 | trans_edp_pipe = PIPE_A; | |
6916 | break; | |
6917 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6918 | trans_edp_pipe = PIPE_B; | |
6919 | break; | |
6920 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6921 | trans_edp_pipe = PIPE_C; | |
6922 | break; | |
6923 | } | |
6924 | ||
6925 | if (trans_edp_pipe == crtc->pipe) | |
6926 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6927 | } | |
6928 | ||
b97186f0 | 6929 | if (!intel_display_power_enabled(dev, |
eccb140b | 6930 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6931 | return false; |
6932 | ||
eccb140b | 6933 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6934 | if (!(tmp & PIPECONF_ENABLE)) |
6935 | return false; | |
6936 | ||
88adfff1 | 6937 | /* |
f196e6be | 6938 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6939 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6940 | * the PCH transcoder is on. | |
6941 | */ | |
eccb140b | 6942 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6943 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6944 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6945 | pipe_config->has_pch_encoder = true; |
6946 | ||
627eb5a3 DV |
6947 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6948 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6949 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6950 | |
6951 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6952 | } |
6953 | ||
1bd1bd80 DV |
6954 | intel_get_pipe_timings(crtc, pipe_config); |
6955 | ||
2fa2fe9a DV |
6956 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6957 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6958 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6959 | |
42db64ef PZ |
6960 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6961 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
6962 | ||
6c49f241 DV |
6963 | pipe_config->pixel_multiplier = 1; |
6964 | ||
0e8ffe1b DV |
6965 | return true; |
6966 | } | |
6967 | ||
f564048e | 6968 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6969 | int x, int y, |
94352cf9 | 6970 | struct drm_framebuffer *fb) |
f564048e EA |
6971 | { |
6972 | struct drm_device *dev = crtc->dev; | |
6973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 6974 | struct intel_encoder *encoder; |
0b701d27 | 6975 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 6976 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 6977 | int pipe = intel_crtc->pipe; |
f564048e EA |
6978 | int ret; |
6979 | ||
0b701d27 | 6980 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6981 | |
b8cecdf5 DV |
6982 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6983 | ||
79e53945 | 6984 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6985 | |
9256aa19 DV |
6986 | if (ret != 0) |
6987 | return ret; | |
6988 | ||
6989 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6990 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6991 | encoder->base.base.id, | |
6992 | drm_get_encoder_name(&encoder->base), | |
6993 | mode->base.id, mode->name); | |
36f2d1f1 | 6994 | encoder->mode_set(encoder); |
9256aa19 DV |
6995 | } |
6996 | ||
6997 | return 0; | |
79e53945 JB |
6998 | } |
6999 | ||
1a91510d JN |
7000 | static struct { |
7001 | int clock; | |
7002 | u32 config; | |
7003 | } hdmi_audio_clock[] = { | |
7004 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7005 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7006 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7007 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7008 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7009 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7010 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7011 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7012 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7013 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7014 | }; | |
7015 | ||
7016 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7017 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7018 | { | |
7019 | int i; | |
7020 | ||
7021 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7022 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7023 | break; | |
7024 | } | |
7025 | ||
7026 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7027 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7028 | i = 1; | |
7029 | } | |
7030 | ||
7031 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7032 | hdmi_audio_clock[i].clock, | |
7033 | hdmi_audio_clock[i].config); | |
7034 | ||
7035 | return hdmi_audio_clock[i].config; | |
7036 | } | |
7037 | ||
3a9627f4 WF |
7038 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7039 | int reg_eldv, uint32_t bits_eldv, | |
7040 | int reg_elda, uint32_t bits_elda, | |
7041 | int reg_edid) | |
7042 | { | |
7043 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7044 | uint8_t *eld = connector->eld; | |
7045 | uint32_t i; | |
7046 | ||
7047 | i = I915_READ(reg_eldv); | |
7048 | i &= bits_eldv; | |
7049 | ||
7050 | if (!eld[0]) | |
7051 | return !i; | |
7052 | ||
7053 | if (!i) | |
7054 | return false; | |
7055 | ||
7056 | i = I915_READ(reg_elda); | |
7057 | i &= ~bits_elda; | |
7058 | I915_WRITE(reg_elda, i); | |
7059 | ||
7060 | for (i = 0; i < eld[2]; i++) | |
7061 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7062 | return false; | |
7063 | ||
7064 | return true; | |
7065 | } | |
7066 | ||
e0dac65e | 7067 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7068 | struct drm_crtc *crtc, |
7069 | struct drm_display_mode *mode) | |
e0dac65e WF |
7070 | { |
7071 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7072 | uint8_t *eld = connector->eld; | |
7073 | uint32_t eldv; | |
7074 | uint32_t len; | |
7075 | uint32_t i; | |
7076 | ||
7077 | i = I915_READ(G4X_AUD_VID_DID); | |
7078 | ||
7079 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7080 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7081 | else | |
7082 | eldv = G4X_ELDV_DEVCTG; | |
7083 | ||
3a9627f4 WF |
7084 | if (intel_eld_uptodate(connector, |
7085 | G4X_AUD_CNTL_ST, eldv, | |
7086 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7087 | G4X_HDMIW_HDMIEDID)) | |
7088 | return; | |
7089 | ||
e0dac65e WF |
7090 | i = I915_READ(G4X_AUD_CNTL_ST); |
7091 | i &= ~(eldv | G4X_ELD_ADDR); | |
7092 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7093 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7094 | ||
7095 | if (!eld[0]) | |
7096 | return; | |
7097 | ||
7098 | len = min_t(uint8_t, eld[2], len); | |
7099 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7100 | for (i = 0; i < len; i++) | |
7101 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7102 | ||
7103 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7104 | i |= eldv; | |
7105 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7106 | } | |
7107 | ||
83358c85 | 7108 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7109 | struct drm_crtc *crtc, |
7110 | struct drm_display_mode *mode) | |
83358c85 WX |
7111 | { |
7112 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7113 | uint8_t *eld = connector->eld; | |
7114 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7116 | uint32_t eldv; |
7117 | uint32_t i; | |
7118 | int len; | |
7119 | int pipe = to_intel_crtc(crtc)->pipe; | |
7120 | int tmp; | |
7121 | ||
7122 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7123 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7124 | int aud_config = HSW_AUD_CFG(pipe); | |
7125 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7126 | ||
7127 | ||
7128 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7129 | ||
7130 | /* Audio output enable */ | |
7131 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7132 | tmp = I915_READ(aud_cntrl_st2); | |
7133 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7134 | I915_WRITE(aud_cntrl_st2, tmp); | |
7135 | ||
7136 | /* Wait for 1 vertical blank */ | |
7137 | intel_wait_for_vblank(dev, pipe); | |
7138 | ||
7139 | /* Set ELD valid state */ | |
7140 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7141 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7142 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7143 | I915_WRITE(aud_cntrl_st2, tmp); | |
7144 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7145 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7146 | |
7147 | /* Enable HDMI mode */ | |
7148 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7149 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7150 | /* clear N_programing_enable and N_value_index */ |
7151 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7152 | I915_WRITE(aud_config, tmp); | |
7153 | ||
7154 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7155 | ||
7156 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7157 | intel_crtc->eld_vld = true; |
83358c85 WX |
7158 | |
7159 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7160 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7161 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7162 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7163 | } else { |
7164 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7165 | } | |
83358c85 WX |
7166 | |
7167 | if (intel_eld_uptodate(connector, | |
7168 | aud_cntrl_st2, eldv, | |
7169 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7170 | hdmiw_hdmiedid)) | |
7171 | return; | |
7172 | ||
7173 | i = I915_READ(aud_cntrl_st2); | |
7174 | i &= ~eldv; | |
7175 | I915_WRITE(aud_cntrl_st2, i); | |
7176 | ||
7177 | if (!eld[0]) | |
7178 | return; | |
7179 | ||
7180 | i = I915_READ(aud_cntl_st); | |
7181 | i &= ~IBX_ELD_ADDRESS; | |
7182 | I915_WRITE(aud_cntl_st, i); | |
7183 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7184 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7185 | ||
7186 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7187 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7188 | for (i = 0; i < len; i++) | |
7189 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7190 | ||
7191 | i = I915_READ(aud_cntrl_st2); | |
7192 | i |= eldv; | |
7193 | I915_WRITE(aud_cntrl_st2, i); | |
7194 | ||
7195 | } | |
7196 | ||
e0dac65e | 7197 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7198 | struct drm_crtc *crtc, |
7199 | struct drm_display_mode *mode) | |
e0dac65e WF |
7200 | { |
7201 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7202 | uint8_t *eld = connector->eld; | |
7203 | uint32_t eldv; | |
7204 | uint32_t i; | |
7205 | int len; | |
7206 | int hdmiw_hdmiedid; | |
b6daa025 | 7207 | int aud_config; |
e0dac65e WF |
7208 | int aud_cntl_st; |
7209 | int aud_cntrl_st2; | |
9b138a83 | 7210 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7211 | |
b3f33cbf | 7212 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7213 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7214 | aud_config = IBX_AUD_CFG(pipe); | |
7215 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7216 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7217 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7218 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7219 | aud_config = VLV_AUD_CFG(pipe); | |
7220 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7221 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7222 | } else { |
9b138a83 WX |
7223 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7224 | aud_config = CPT_AUD_CFG(pipe); | |
7225 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7226 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7227 | } |
7228 | ||
9b138a83 | 7229 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7230 | |
9ca2fe73 ML |
7231 | if (IS_VALLEYVIEW(connector->dev)) { |
7232 | struct intel_encoder *intel_encoder; | |
7233 | struct intel_digital_port *intel_dig_port; | |
7234 | ||
7235 | intel_encoder = intel_attached_encoder(connector); | |
7236 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7237 | i = intel_dig_port->port; | |
7238 | } else { | |
7239 | i = I915_READ(aud_cntl_st); | |
7240 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7241 | /* DIP_Port_Select, 0x1 = PortB */ | |
7242 | } | |
7243 | ||
e0dac65e WF |
7244 | if (!i) { |
7245 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7246 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7247 | eldv = IBX_ELD_VALIDB; |
7248 | eldv |= IBX_ELD_VALIDB << 4; | |
7249 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7250 | } else { |
2582a850 | 7251 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7252 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7253 | } |
7254 | ||
3a9627f4 WF |
7255 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7256 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7257 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7258 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7259 | } else { |
7260 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7261 | } | |
e0dac65e | 7262 | |
3a9627f4 WF |
7263 | if (intel_eld_uptodate(connector, |
7264 | aud_cntrl_st2, eldv, | |
7265 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7266 | hdmiw_hdmiedid)) | |
7267 | return; | |
7268 | ||
e0dac65e WF |
7269 | i = I915_READ(aud_cntrl_st2); |
7270 | i &= ~eldv; | |
7271 | I915_WRITE(aud_cntrl_st2, i); | |
7272 | ||
7273 | if (!eld[0]) | |
7274 | return; | |
7275 | ||
e0dac65e | 7276 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7277 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7278 | I915_WRITE(aud_cntl_st, i); |
7279 | ||
7280 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7281 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7282 | for (i = 0; i < len; i++) | |
7283 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7284 | ||
7285 | i = I915_READ(aud_cntrl_st2); | |
7286 | i |= eldv; | |
7287 | I915_WRITE(aud_cntrl_st2, i); | |
7288 | } | |
7289 | ||
7290 | void intel_write_eld(struct drm_encoder *encoder, | |
7291 | struct drm_display_mode *mode) | |
7292 | { | |
7293 | struct drm_crtc *crtc = encoder->crtc; | |
7294 | struct drm_connector *connector; | |
7295 | struct drm_device *dev = encoder->dev; | |
7296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7297 | ||
7298 | connector = drm_select_eld(encoder, mode); | |
7299 | if (!connector) | |
7300 | return; | |
7301 | ||
7302 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7303 | connector->base.id, | |
7304 | drm_get_connector_name(connector), | |
7305 | connector->encoder->base.id, | |
7306 | drm_get_encoder_name(connector->encoder)); | |
7307 | ||
7308 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7309 | ||
7310 | if (dev_priv->display.write_eld) | |
34427052 | 7311 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7312 | } |
7313 | ||
560b85bb CW |
7314 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7315 | { | |
7316 | struct drm_device *dev = crtc->dev; | |
7317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7319 | bool visible = base != 0; | |
7320 | u32 cntl; | |
7321 | ||
7322 | if (intel_crtc->cursor_visible == visible) | |
7323 | return; | |
7324 | ||
9db4a9c7 | 7325 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7326 | if (visible) { |
7327 | /* On these chipsets we can only modify the base whilst | |
7328 | * the cursor is disabled. | |
7329 | */ | |
9db4a9c7 | 7330 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7331 | |
7332 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7333 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7334 | cntl |= CURSOR_ENABLE | | |
7335 | CURSOR_GAMMA_ENABLE | | |
7336 | CURSOR_FORMAT_ARGB; | |
7337 | } else | |
7338 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7339 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7340 | |
7341 | intel_crtc->cursor_visible = visible; | |
7342 | } | |
7343 | ||
7344 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7345 | { | |
7346 | struct drm_device *dev = crtc->dev; | |
7347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7349 | int pipe = intel_crtc->pipe; | |
7350 | bool visible = base != 0; | |
7351 | ||
7352 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7353 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7354 | if (base) { |
7355 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7356 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7357 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7358 | } else { | |
7359 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7360 | cntl |= CURSOR_MODE_DISABLE; | |
7361 | } | |
9db4a9c7 | 7362 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7363 | |
7364 | intel_crtc->cursor_visible = visible; | |
7365 | } | |
7366 | /* and commit changes on next vblank */ | |
9db4a9c7 | 7367 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
7368 | } |
7369 | ||
65a21cd6 JB |
7370 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7371 | { | |
7372 | struct drm_device *dev = crtc->dev; | |
7373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7375 | int pipe = intel_crtc->pipe; | |
7376 | bool visible = base != 0; | |
7377 | ||
7378 | if (intel_crtc->cursor_visible != visible) { | |
7379 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7380 | if (base) { | |
7381 | cntl &= ~CURSOR_MODE; | |
7382 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7383 | } else { | |
7384 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7385 | cntl |= CURSOR_MODE_DISABLE; | |
7386 | } | |
6bbfa1c5 | 7387 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7388 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7389 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7390 | } | |
65a21cd6 JB |
7391 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7392 | ||
7393 | intel_crtc->cursor_visible = visible; | |
7394 | } | |
7395 | /* and commit changes on next vblank */ | |
7396 | I915_WRITE(CURBASE_IVB(pipe), base); | |
7397 | } | |
7398 | ||
cda4b7d3 | 7399 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7400 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7401 | bool on) | |
cda4b7d3 CW |
7402 | { |
7403 | struct drm_device *dev = crtc->dev; | |
7404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7406 | int pipe = intel_crtc->pipe; | |
7407 | int x = intel_crtc->cursor_x; | |
7408 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7409 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7410 | bool visible; |
7411 | ||
d6e4db15 | 7412 | if (on) |
cda4b7d3 | 7413 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7414 | |
d6e4db15 VS |
7415 | if (x >= intel_crtc->config.pipe_src_w) |
7416 | base = 0; | |
7417 | ||
7418 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7419 | base = 0; |
7420 | ||
7421 | if (x < 0) { | |
efc9064e | 7422 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7423 | base = 0; |
7424 | ||
7425 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7426 | x = -x; | |
7427 | } | |
7428 | pos |= x << CURSOR_X_SHIFT; | |
7429 | ||
7430 | if (y < 0) { | |
efc9064e | 7431 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7432 | base = 0; |
7433 | ||
7434 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7435 | y = -y; | |
7436 | } | |
7437 | pos |= y << CURSOR_Y_SHIFT; | |
7438 | ||
7439 | visible = base != 0; | |
560b85bb | 7440 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7441 | return; |
7442 | ||
b3dc685e | 7443 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7444 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7445 | ivb_update_cursor(crtc, base); | |
7446 | } else { | |
7447 | I915_WRITE(CURPOS(pipe), pos); | |
7448 | if (IS_845G(dev) || IS_I865G(dev)) | |
7449 | i845_update_cursor(crtc, base); | |
7450 | else | |
7451 | i9xx_update_cursor(crtc, base); | |
7452 | } | |
cda4b7d3 CW |
7453 | } |
7454 | ||
79e53945 | 7455 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7456 | struct drm_file *file, |
79e53945 JB |
7457 | uint32_t handle, |
7458 | uint32_t width, uint32_t height) | |
7459 | { | |
7460 | struct drm_device *dev = crtc->dev; | |
7461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7463 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7464 | uint32_t addr; |
3f8bc370 | 7465 | int ret; |
79e53945 | 7466 | |
79e53945 JB |
7467 | /* if we want to turn off the cursor ignore width and height */ |
7468 | if (!handle) { | |
28c97730 | 7469 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7470 | addr = 0; |
05394f39 | 7471 | obj = NULL; |
5004417d | 7472 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7473 | goto finish; |
79e53945 JB |
7474 | } |
7475 | ||
7476 | /* Currently we only support 64x64 cursors */ | |
7477 | if (width != 64 || height != 64) { | |
7478 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7479 | return -EINVAL; | |
7480 | } | |
7481 | ||
05394f39 | 7482 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7483 | if (&obj->base == NULL) |
79e53945 JB |
7484 | return -ENOENT; |
7485 | ||
05394f39 | 7486 | if (obj->base.size < width * height * 4) { |
79e53945 | 7487 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7488 | ret = -ENOMEM; |
7489 | goto fail; | |
79e53945 JB |
7490 | } |
7491 | ||
71acb5eb | 7492 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7493 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 7494 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
7495 | unsigned alignment; |
7496 | ||
d9e86c0e CW |
7497 | if (obj->tiling_mode) { |
7498 | DRM_ERROR("cursor cannot be tiled\n"); | |
7499 | ret = -EINVAL; | |
7500 | goto fail_locked; | |
7501 | } | |
7502 | ||
693db184 CW |
7503 | /* Note that the w/a also requires 2 PTE of padding following |
7504 | * the bo. We currently fill all unused PTE with the shadow | |
7505 | * page and so we should always have valid PTE following the | |
7506 | * cursor preventing the VT-d warning. | |
7507 | */ | |
7508 | alignment = 0; | |
7509 | if (need_vtd_wa(dev)) | |
7510 | alignment = 64*1024; | |
7511 | ||
7512 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7513 | if (ret) { |
7514 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7515 | goto fail_locked; |
e7b526bb CW |
7516 | } |
7517 | ||
d9e86c0e CW |
7518 | ret = i915_gem_object_put_fence(obj); |
7519 | if (ret) { | |
2da3b9b9 | 7520 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7521 | goto fail_unpin; |
7522 | } | |
7523 | ||
f343c5f6 | 7524 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7525 | } else { |
6eeefaf3 | 7526 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7527 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7528 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7529 | align); | |
71acb5eb DA |
7530 | if (ret) { |
7531 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7532 | goto fail_locked; |
71acb5eb | 7533 | } |
05394f39 | 7534 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7535 | } |
7536 | ||
a6c45cf0 | 7537 | if (IS_GEN2(dev)) |
14b60391 JB |
7538 | I915_WRITE(CURSIZE, (height << 12) | width); |
7539 | ||
3f8bc370 | 7540 | finish: |
3f8bc370 | 7541 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 7542 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 7543 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7544 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7545 | } else | |
cc98b413 | 7546 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7547 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7548 | } |
80824003 | 7549 | |
7f9872e0 | 7550 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7551 | |
7552 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7553 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7554 | intel_crtc->cursor_width = width; |
7555 | intel_crtc->cursor_height = height; | |
7556 | ||
f2f5f771 VS |
7557 | if (intel_crtc->active) |
7558 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7559 | |
79e53945 | 7560 | return 0; |
e7b526bb | 7561 | fail_unpin: |
cc98b413 | 7562 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7563 | fail_locked: |
34b8686e | 7564 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7565 | fail: |
05394f39 | 7566 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7567 | return ret; |
79e53945 JB |
7568 | } |
7569 | ||
7570 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7571 | { | |
79e53945 | 7572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7573 | |
92e76c8c VS |
7574 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7575 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7576 | |
f2f5f771 VS |
7577 | if (intel_crtc->active) |
7578 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7579 | |
7580 | return 0; | |
b8c00ac5 DA |
7581 | } |
7582 | ||
79e53945 | 7583 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7584 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7585 | { |
7203425a | 7586 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7588 | |
7203425a | 7589 | for (i = start; i < end; i++) { |
79e53945 JB |
7590 | intel_crtc->lut_r[i] = red[i] >> 8; |
7591 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7592 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7593 | } | |
7594 | ||
7595 | intel_crtc_load_lut(crtc); | |
7596 | } | |
7597 | ||
79e53945 JB |
7598 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7599 | static struct drm_display_mode load_detect_mode = { | |
7600 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7601 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7602 | }; | |
7603 | ||
d2dff872 CW |
7604 | static struct drm_framebuffer * |
7605 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7606 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7607 | struct drm_i915_gem_object *obj) |
7608 | { | |
7609 | struct intel_framebuffer *intel_fb; | |
7610 | int ret; | |
7611 | ||
7612 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7613 | if (!intel_fb) { | |
7614 | drm_gem_object_unreference_unlocked(&obj->base); | |
7615 | return ERR_PTR(-ENOMEM); | |
7616 | } | |
7617 | ||
dd4916c5 DV |
7618 | ret = i915_mutex_lock_interruptible(dev); |
7619 | if (ret) | |
7620 | goto err; | |
7621 | ||
d2dff872 | 7622 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
dd4916c5 DV |
7623 | mutex_unlock(&dev->struct_mutex); |
7624 | if (ret) | |
7625 | goto err; | |
d2dff872 CW |
7626 | |
7627 | return &intel_fb->base; | |
dd4916c5 DV |
7628 | err: |
7629 | drm_gem_object_unreference_unlocked(&obj->base); | |
7630 | kfree(intel_fb); | |
7631 | ||
7632 | return ERR_PTR(ret); | |
d2dff872 CW |
7633 | } |
7634 | ||
7635 | static u32 | |
7636 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7637 | { | |
7638 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7639 | return ALIGN(pitch, 64); | |
7640 | } | |
7641 | ||
7642 | static u32 | |
7643 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7644 | { | |
7645 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7646 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7647 | } | |
7648 | ||
7649 | static struct drm_framebuffer * | |
7650 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7651 | struct drm_display_mode *mode, | |
7652 | int depth, int bpp) | |
7653 | { | |
7654 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7655 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7656 | |
7657 | obj = i915_gem_alloc_object(dev, | |
7658 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7659 | if (obj == NULL) | |
7660 | return ERR_PTR(-ENOMEM); | |
7661 | ||
7662 | mode_cmd.width = mode->hdisplay; | |
7663 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7664 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7665 | bpp); | |
5ca0c34a | 7666 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7667 | |
7668 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7669 | } | |
7670 | ||
7671 | static struct drm_framebuffer * | |
7672 | mode_fits_in_fbdev(struct drm_device *dev, | |
7673 | struct drm_display_mode *mode) | |
7674 | { | |
4520f53a | 7675 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7676 | struct drm_i915_private *dev_priv = dev->dev_private; |
7677 | struct drm_i915_gem_object *obj; | |
7678 | struct drm_framebuffer *fb; | |
7679 | ||
7680 | if (dev_priv->fbdev == NULL) | |
7681 | return NULL; | |
7682 | ||
7683 | obj = dev_priv->fbdev->ifb.obj; | |
7684 | if (obj == NULL) | |
7685 | return NULL; | |
7686 | ||
7687 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7688 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7689 | fb->bits_per_pixel)) | |
d2dff872 CW |
7690 | return NULL; |
7691 | ||
01f2c773 | 7692 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7693 | return NULL; |
7694 | ||
7695 | return fb; | |
4520f53a DV |
7696 | #else |
7697 | return NULL; | |
7698 | #endif | |
d2dff872 CW |
7699 | } |
7700 | ||
d2434ab7 | 7701 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7702 | struct drm_display_mode *mode, |
8261b191 | 7703 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7704 | { |
7705 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7706 | struct intel_encoder *intel_encoder = |
7707 | intel_attached_encoder(connector); | |
79e53945 | 7708 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7709 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7710 | struct drm_crtc *crtc = NULL; |
7711 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7712 | struct drm_framebuffer *fb; |
79e53945 JB |
7713 | int i = -1; |
7714 | ||
d2dff872 CW |
7715 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7716 | connector->base.id, drm_get_connector_name(connector), | |
7717 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7718 | ||
79e53945 JB |
7719 | /* |
7720 | * Algorithm gets a little messy: | |
7a5e4805 | 7721 | * |
79e53945 JB |
7722 | * - if the connector already has an assigned crtc, use it (but make |
7723 | * sure it's on first) | |
7a5e4805 | 7724 | * |
79e53945 JB |
7725 | * - try to find the first unused crtc that can drive this connector, |
7726 | * and use that if we find one | |
79e53945 JB |
7727 | */ |
7728 | ||
7729 | /* See if we already have a CRTC for this connector */ | |
7730 | if (encoder->crtc) { | |
7731 | crtc = encoder->crtc; | |
8261b191 | 7732 | |
7b24056b DV |
7733 | mutex_lock(&crtc->mutex); |
7734 | ||
24218aac | 7735 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7736 | old->load_detect_temp = false; |
7737 | ||
7738 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7739 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7740 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7741 | |
7173188d | 7742 | return true; |
79e53945 JB |
7743 | } |
7744 | ||
7745 | /* Find an unused one (if possible) */ | |
7746 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7747 | i++; | |
7748 | if (!(encoder->possible_crtcs & (1 << i))) | |
7749 | continue; | |
7750 | if (!possible_crtc->enabled) { | |
7751 | crtc = possible_crtc; | |
7752 | break; | |
7753 | } | |
79e53945 JB |
7754 | } |
7755 | ||
7756 | /* | |
7757 | * If we didn't find an unused CRTC, don't use any. | |
7758 | */ | |
7759 | if (!crtc) { | |
7173188d CW |
7760 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7761 | return false; | |
79e53945 JB |
7762 | } |
7763 | ||
7b24056b | 7764 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7765 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7766 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7767 | |
7768 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7769 | old->dpms_mode = connector->dpms; |
8261b191 | 7770 | old->load_detect_temp = true; |
d2dff872 | 7771 | old->release_fb = NULL; |
79e53945 | 7772 | |
6492711d CW |
7773 | if (!mode) |
7774 | mode = &load_detect_mode; | |
79e53945 | 7775 | |
d2dff872 CW |
7776 | /* We need a framebuffer large enough to accommodate all accesses |
7777 | * that the plane may generate whilst we perform load detection. | |
7778 | * We can not rely on the fbcon either being present (we get called | |
7779 | * during its initialisation to detect all boot displays, or it may | |
7780 | * not even exist) or that it is large enough to satisfy the | |
7781 | * requested mode. | |
7782 | */ | |
94352cf9 DV |
7783 | fb = mode_fits_in_fbdev(dev, mode); |
7784 | if (fb == NULL) { | |
d2dff872 | 7785 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7786 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7787 | old->release_fb = fb; | |
d2dff872 CW |
7788 | } else |
7789 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7790 | if (IS_ERR(fb)) { |
d2dff872 | 7791 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7792 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7793 | return false; |
79e53945 | 7794 | } |
79e53945 | 7795 | |
c0c36b94 | 7796 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7797 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7798 | if (old->release_fb) |
7799 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7800 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7801 | return false; |
79e53945 | 7802 | } |
7173188d | 7803 | |
79e53945 | 7804 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7805 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7806 | return true; |
79e53945 JB |
7807 | } |
7808 | ||
d2434ab7 | 7809 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7810 | struct intel_load_detect_pipe *old) |
79e53945 | 7811 | { |
d2434ab7 DV |
7812 | struct intel_encoder *intel_encoder = |
7813 | intel_attached_encoder(connector); | |
4ef69c7a | 7814 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7815 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7816 | |
d2dff872 CW |
7817 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7818 | connector->base.id, drm_get_connector_name(connector), | |
7819 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7820 | ||
8261b191 | 7821 | if (old->load_detect_temp) { |
fc303101 DV |
7822 | to_intel_connector(connector)->new_encoder = NULL; |
7823 | intel_encoder->new_crtc = NULL; | |
7824 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7825 | |
36206361 DV |
7826 | if (old->release_fb) { |
7827 | drm_framebuffer_unregister_private(old->release_fb); | |
7828 | drm_framebuffer_unreference(old->release_fb); | |
7829 | } | |
d2dff872 | 7830 | |
67c96400 | 7831 | mutex_unlock(&crtc->mutex); |
0622a53c | 7832 | return; |
79e53945 JB |
7833 | } |
7834 | ||
c751ce4f | 7835 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7836 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7837 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7838 | |
7839 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7840 | } |
7841 | ||
da4a1efa VS |
7842 | static int i9xx_pll_refclk(struct drm_device *dev, |
7843 | const struct intel_crtc_config *pipe_config) | |
7844 | { | |
7845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7846 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7847 | ||
7848 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
7849 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
7850 | else if (HAS_PCH_SPLIT(dev)) | |
7851 | return 120000; | |
7852 | else if (!IS_GEN2(dev)) | |
7853 | return 96000; | |
7854 | else | |
7855 | return 48000; | |
7856 | } | |
7857 | ||
79e53945 | 7858 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7859 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7860 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7861 | { |
f1f644dc | 7862 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7863 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7864 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7865 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7866 | u32 fp; |
7867 | intel_clock_t clock; | |
da4a1efa | 7868 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7869 | |
7870 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7871 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7872 | else |
293623f7 | 7873 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7874 | |
7875 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7876 | if (IS_PINEVIEW(dev)) { |
7877 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7878 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7879 | } else { |
7880 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7881 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7882 | } | |
7883 | ||
a6c45cf0 | 7884 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7885 | if (IS_PINEVIEW(dev)) |
7886 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7887 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7888 | else |
7889 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7890 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7891 | ||
7892 | switch (dpll & DPLL_MODE_MASK) { | |
7893 | case DPLLB_MODE_DAC_SERIAL: | |
7894 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7895 | 5 : 10; | |
7896 | break; | |
7897 | case DPLLB_MODE_LVDS: | |
7898 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7899 | 7 : 14; | |
7900 | break; | |
7901 | default: | |
28c97730 | 7902 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7903 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 7904 | return; |
79e53945 JB |
7905 | } |
7906 | ||
ac58c3f0 | 7907 | if (IS_PINEVIEW(dev)) |
da4a1efa | 7908 | pineview_clock(refclk, &clock); |
ac58c3f0 | 7909 | else |
da4a1efa | 7910 | i9xx_clock(refclk, &clock); |
79e53945 JB |
7911 | } else { |
7912 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7913 | ||
7914 | if (is_lvds) { | |
7915 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7916 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7917 | clock.p2 = 14; | |
79e53945 JB |
7918 | } else { |
7919 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7920 | clock.p1 = 2; | |
7921 | else { | |
7922 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7923 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7924 | } | |
7925 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7926 | clock.p2 = 4; | |
7927 | else | |
7928 | clock.p2 = 2; | |
79e53945 | 7929 | } |
da4a1efa VS |
7930 | |
7931 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
7932 | } |
7933 | ||
18442d08 VS |
7934 | /* |
7935 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 7936 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
7937 | * encoder's get_config() function. |
7938 | */ | |
7939 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
7940 | } |
7941 | ||
6878da05 VS |
7942 | int intel_dotclock_calculate(int link_freq, |
7943 | const struct intel_link_m_n *m_n) | |
f1f644dc | 7944 | { |
f1f644dc JB |
7945 | /* |
7946 | * The calculation for the data clock is: | |
1041a02f | 7947 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 7948 | * But we want to avoid losing precison if possible, so: |
1041a02f | 7949 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
7950 | * |
7951 | * and the link clock is simpler: | |
1041a02f | 7952 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
7953 | */ |
7954 | ||
6878da05 VS |
7955 | if (!m_n->link_n) |
7956 | return 0; | |
f1f644dc | 7957 | |
6878da05 VS |
7958 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
7959 | } | |
f1f644dc | 7960 | |
18442d08 VS |
7961 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
7962 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
7963 | { |
7964 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 7965 | |
18442d08 VS |
7966 | /* read out port_clock from the DPLL */ |
7967 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 7968 | |
f1f644dc | 7969 | /* |
18442d08 | 7970 | * This value does not include pixel_multiplier. |
241bfc38 | 7971 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
7972 | * agree once we know their relationship in the encoder's |
7973 | * get_config() function. | |
79e53945 | 7974 | */ |
241bfc38 | 7975 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
7976 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
7977 | &pipe_config->fdi_m_n); | |
79e53945 JB |
7978 | } |
7979 | ||
7980 | /** Returns the currently programmed mode of the given pipe. */ | |
7981 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7982 | struct drm_crtc *crtc) | |
7983 | { | |
548f245b | 7984 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7986 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7987 | struct drm_display_mode *mode; |
f1f644dc | 7988 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
7989 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7990 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7991 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7992 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 7993 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
7994 | |
7995 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7996 | if (!mode) | |
7997 | return NULL; | |
7998 | ||
f1f644dc JB |
7999 | /* |
8000 | * Construct a pipe_config sufficient for getting the clock info | |
8001 | * back out of crtc_clock_get. | |
8002 | * | |
8003 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8004 | * to use a real value here instead. | |
8005 | */ | |
293623f7 | 8006 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8007 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8008 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8009 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8010 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8011 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8012 | ||
773ae034 | 8013 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8014 | mode->hdisplay = (htot & 0xffff) + 1; |
8015 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8016 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8017 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8018 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8019 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8020 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8021 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8022 | ||
8023 | drm_mode_set_name(mode); | |
79e53945 JB |
8024 | |
8025 | return mode; | |
8026 | } | |
8027 | ||
3dec0095 | 8028 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8029 | { |
8030 | struct drm_device *dev = crtc->dev; | |
8031 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8033 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8034 | int dpll_reg = DPLL(pipe); |
8035 | int dpll; | |
652c393a | 8036 | |
bad720ff | 8037 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8038 | return; |
8039 | ||
8040 | if (!dev_priv->lvds_downclock_avail) | |
8041 | return; | |
8042 | ||
dbdc6479 | 8043 | dpll = I915_READ(dpll_reg); |
652c393a | 8044 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8045 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8046 | |
8ac5a6d5 | 8047 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8048 | |
8049 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8050 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8051 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8052 | |
652c393a JB |
8053 | dpll = I915_READ(dpll_reg); |
8054 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8055 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8056 | } |
652c393a JB |
8057 | } |
8058 | ||
8059 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8060 | { | |
8061 | struct drm_device *dev = crtc->dev; | |
8062 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8064 | |
bad720ff | 8065 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8066 | return; |
8067 | ||
8068 | if (!dev_priv->lvds_downclock_avail) | |
8069 | return; | |
8070 | ||
8071 | /* | |
8072 | * Since this is called by a timer, we should never get here in | |
8073 | * the manual case. | |
8074 | */ | |
8075 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8076 | int pipe = intel_crtc->pipe; |
8077 | int dpll_reg = DPLL(pipe); | |
8078 | int dpll; | |
f6e5b160 | 8079 | |
44d98a61 | 8080 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8081 | |
8ac5a6d5 | 8082 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8083 | |
dc257cf1 | 8084 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8085 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8086 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8087 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8088 | dpll = I915_READ(dpll_reg); |
8089 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8090 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8091 | } |
8092 | ||
8093 | } | |
8094 | ||
f047e395 CW |
8095 | void intel_mark_busy(struct drm_device *dev) |
8096 | { | |
c67a470b PZ |
8097 | struct drm_i915_private *dev_priv = dev->dev_private; |
8098 | ||
8099 | hsw_package_c8_gpu_busy(dev_priv); | |
8100 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8101 | } |
8102 | ||
8103 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8104 | { |
c67a470b | 8105 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8106 | struct drm_crtc *crtc; |
652c393a | 8107 | |
c67a470b PZ |
8108 | hsw_package_c8_gpu_idle(dev_priv); |
8109 | ||
652c393a JB |
8110 | if (!i915_powersave) |
8111 | return; | |
8112 | ||
652c393a | 8113 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8114 | if (!crtc->fb) |
8115 | continue; | |
8116 | ||
725a5b54 | 8117 | intel_decrease_pllclock(crtc); |
652c393a | 8118 | } |
b29c19b6 CW |
8119 | |
8120 | if (dev_priv->info->gen >= 6) | |
8121 | gen6_rps_idle(dev->dev_private); | |
652c393a JB |
8122 | } |
8123 | ||
c65355bb CW |
8124 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8125 | struct intel_ring_buffer *ring) | |
652c393a | 8126 | { |
f047e395 CW |
8127 | struct drm_device *dev = obj->base.dev; |
8128 | struct drm_crtc *crtc; | |
652c393a | 8129 | |
f047e395 | 8130 | if (!i915_powersave) |
acb87dfb CW |
8131 | return; |
8132 | ||
652c393a JB |
8133 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8134 | if (!crtc->fb) | |
8135 | continue; | |
8136 | ||
c65355bb CW |
8137 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8138 | continue; | |
8139 | ||
8140 | intel_increase_pllclock(crtc); | |
8141 | if (ring && intel_fbc_enabled(dev)) | |
8142 | ring->fbc_dirty = true; | |
652c393a JB |
8143 | } |
8144 | } | |
8145 | ||
79e53945 JB |
8146 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8147 | { | |
8148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8149 | struct drm_device *dev = crtc->dev; |
8150 | struct intel_unpin_work *work; | |
8151 | unsigned long flags; | |
8152 | ||
8153 | spin_lock_irqsave(&dev->event_lock, flags); | |
8154 | work = intel_crtc->unpin_work; | |
8155 | intel_crtc->unpin_work = NULL; | |
8156 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8157 | ||
8158 | if (work) { | |
8159 | cancel_work_sync(&work->work); | |
8160 | kfree(work); | |
8161 | } | |
79e53945 | 8162 | |
40ccc72b MK |
8163 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8164 | ||
79e53945 | 8165 | drm_crtc_cleanup(crtc); |
67e77c5a | 8166 | |
79e53945 JB |
8167 | kfree(intel_crtc); |
8168 | } | |
8169 | ||
6b95a207 KH |
8170 | static void intel_unpin_work_fn(struct work_struct *__work) |
8171 | { | |
8172 | struct intel_unpin_work *work = | |
8173 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8174 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8175 | |
b4a98e57 | 8176 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8177 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8178 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8179 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8180 | |
b4a98e57 CW |
8181 | intel_update_fbc(dev); |
8182 | mutex_unlock(&dev->struct_mutex); | |
8183 | ||
8184 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8185 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8186 | ||
6b95a207 KH |
8187 | kfree(work); |
8188 | } | |
8189 | ||
1afe3e9d | 8190 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8191 | struct drm_crtc *crtc) |
6b95a207 KH |
8192 | { |
8193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8195 | struct intel_unpin_work *work; | |
6b95a207 KH |
8196 | unsigned long flags; |
8197 | ||
8198 | /* Ignore early vblank irqs */ | |
8199 | if (intel_crtc == NULL) | |
8200 | return; | |
8201 | ||
8202 | spin_lock_irqsave(&dev->event_lock, flags); | |
8203 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8204 | |
8205 | /* Ensure we don't miss a work->pending update ... */ | |
8206 | smp_rmb(); | |
8207 | ||
8208 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8209 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8210 | return; | |
8211 | } | |
8212 | ||
e7d841ca CW |
8213 | /* and that the unpin work is consistent wrt ->pending. */ |
8214 | smp_rmb(); | |
8215 | ||
6b95a207 | 8216 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8217 | |
45a066eb RC |
8218 | if (work->event) |
8219 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8220 | |
0af7e4df MK |
8221 | drm_vblank_put(dev, intel_crtc->pipe); |
8222 | ||
6b95a207 KH |
8223 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8224 | ||
2c10d571 | 8225 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8226 | |
8227 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8228 | |
8229 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8230 | } |
8231 | ||
1afe3e9d JB |
8232 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8233 | { | |
8234 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8235 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8236 | ||
49b14a5c | 8237 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8238 | } |
8239 | ||
8240 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8241 | { | |
8242 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8243 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8244 | ||
49b14a5c | 8245 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8246 | } |
8247 | ||
6b95a207 KH |
8248 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8249 | { | |
8250 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8251 | struct intel_crtc *intel_crtc = | |
8252 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8253 | unsigned long flags; | |
8254 | ||
e7d841ca CW |
8255 | /* NB: An MMIO update of the plane base pointer will also |
8256 | * generate a page-flip completion irq, i.e. every modeset | |
8257 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8258 | */ | |
6b95a207 | 8259 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8260 | if (intel_crtc->unpin_work) |
8261 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8262 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8263 | } | |
8264 | ||
e7d841ca CW |
8265 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8266 | { | |
8267 | /* Ensure that the work item is consistent when activating it ... */ | |
8268 | smp_wmb(); | |
8269 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8270 | /* and that it is marked active as soon as the irq could fire. */ | |
8271 | smp_wmb(); | |
8272 | } | |
8273 | ||
8c9f3aaf JB |
8274 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8275 | struct drm_crtc *crtc, | |
8276 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8277 | struct drm_i915_gem_object *obj, |
8278 | uint32_t flags) | |
8c9f3aaf JB |
8279 | { |
8280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8282 | u32 flip_mask; |
6d90c952 | 8283 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8284 | int ret; |
8285 | ||
6d90c952 | 8286 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8287 | if (ret) |
83d4092b | 8288 | goto err; |
8c9f3aaf | 8289 | |
6d90c952 | 8290 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8291 | if (ret) |
83d4092b | 8292 | goto err_unpin; |
8c9f3aaf JB |
8293 | |
8294 | /* Can't queue multiple flips, so wait for the previous | |
8295 | * one to finish before executing the next. | |
8296 | */ | |
8297 | if (intel_crtc->plane) | |
8298 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8299 | else | |
8300 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8301 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8302 | intel_ring_emit(ring, MI_NOOP); | |
8303 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8304 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8305 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8306 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8307 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8308 | |
8309 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8310 | __intel_ring_advance(ring); |
83d4092b CW |
8311 | return 0; |
8312 | ||
8313 | err_unpin: | |
8314 | intel_unpin_fb_obj(obj); | |
8315 | err: | |
8c9f3aaf JB |
8316 | return ret; |
8317 | } | |
8318 | ||
8319 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8320 | struct drm_crtc *crtc, | |
8321 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8322 | struct drm_i915_gem_object *obj, |
8323 | uint32_t flags) | |
8c9f3aaf JB |
8324 | { |
8325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8327 | u32 flip_mask; |
6d90c952 | 8328 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8329 | int ret; |
8330 | ||
6d90c952 | 8331 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8332 | if (ret) |
83d4092b | 8333 | goto err; |
8c9f3aaf | 8334 | |
6d90c952 | 8335 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8336 | if (ret) |
83d4092b | 8337 | goto err_unpin; |
8c9f3aaf JB |
8338 | |
8339 | if (intel_crtc->plane) | |
8340 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8341 | else | |
8342 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8343 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8344 | intel_ring_emit(ring, MI_NOOP); | |
8345 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8346 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8347 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8348 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8349 | intel_ring_emit(ring, MI_NOOP); |
8350 | ||
e7d841ca | 8351 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8352 | __intel_ring_advance(ring); |
83d4092b CW |
8353 | return 0; |
8354 | ||
8355 | err_unpin: | |
8356 | intel_unpin_fb_obj(obj); | |
8357 | err: | |
8c9f3aaf JB |
8358 | return ret; |
8359 | } | |
8360 | ||
8361 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8362 | struct drm_crtc *crtc, | |
8363 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8364 | struct drm_i915_gem_object *obj, |
8365 | uint32_t flags) | |
8c9f3aaf JB |
8366 | { |
8367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8369 | uint32_t pf, pipesrc; | |
6d90c952 | 8370 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8371 | int ret; |
8372 | ||
6d90c952 | 8373 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8374 | if (ret) |
83d4092b | 8375 | goto err; |
8c9f3aaf | 8376 | |
6d90c952 | 8377 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8378 | if (ret) |
83d4092b | 8379 | goto err_unpin; |
8c9f3aaf JB |
8380 | |
8381 | /* i965+ uses the linear or tiled offsets from the | |
8382 | * Display Registers (which do not change across a page-flip) | |
8383 | * so we need only reprogram the base address. | |
8384 | */ | |
6d90c952 DV |
8385 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8386 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8387 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8388 | intel_ring_emit(ring, |
f343c5f6 | 8389 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8390 | obj->tiling_mode); |
8c9f3aaf JB |
8391 | |
8392 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8393 | * untested on non-native modes, so ignore it for now. | |
8394 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8395 | */ | |
8396 | pf = 0; | |
8397 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8398 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8399 | |
8400 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8401 | __intel_ring_advance(ring); |
83d4092b CW |
8402 | return 0; |
8403 | ||
8404 | err_unpin: | |
8405 | intel_unpin_fb_obj(obj); | |
8406 | err: | |
8c9f3aaf JB |
8407 | return ret; |
8408 | } | |
8409 | ||
8410 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8411 | struct drm_crtc *crtc, | |
8412 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8413 | struct drm_i915_gem_object *obj, |
8414 | uint32_t flags) | |
8c9f3aaf JB |
8415 | { |
8416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8418 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8419 | uint32_t pf, pipesrc; |
8420 | int ret; | |
8421 | ||
6d90c952 | 8422 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8423 | if (ret) |
83d4092b | 8424 | goto err; |
8c9f3aaf | 8425 | |
6d90c952 | 8426 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8427 | if (ret) |
83d4092b | 8428 | goto err_unpin; |
8c9f3aaf | 8429 | |
6d90c952 DV |
8430 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8431 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8432 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8433 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8434 | |
dc257cf1 DV |
8435 | /* Contrary to the suggestions in the documentation, |
8436 | * "Enable Panel Fitter" does not seem to be required when page | |
8437 | * flipping with a non-native mode, and worse causes a normal | |
8438 | * modeset to fail. | |
8439 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8440 | */ | |
8441 | pf = 0; | |
8c9f3aaf | 8442 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8443 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8444 | |
8445 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8446 | __intel_ring_advance(ring); |
83d4092b CW |
8447 | return 0; |
8448 | ||
8449 | err_unpin: | |
8450 | intel_unpin_fb_obj(obj); | |
8451 | err: | |
8c9f3aaf JB |
8452 | return ret; |
8453 | } | |
8454 | ||
7c9017e5 JB |
8455 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8456 | struct drm_crtc *crtc, | |
8457 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8458 | struct drm_i915_gem_object *obj, |
8459 | uint32_t flags) | |
7c9017e5 JB |
8460 | { |
8461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8463 | struct intel_ring_buffer *ring; |
cb05d8de | 8464 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8465 | int len, ret; |
8466 | ||
8467 | ring = obj->ring; | |
1c5fd085 | 8468 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8469 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8470 | |
8471 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8472 | if (ret) | |
83d4092b | 8473 | goto err; |
7c9017e5 | 8474 | |
cb05d8de DV |
8475 | switch(intel_crtc->plane) { |
8476 | case PLANE_A: | |
8477 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8478 | break; | |
8479 | case PLANE_B: | |
8480 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8481 | break; | |
8482 | case PLANE_C: | |
8483 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8484 | break; | |
8485 | default: | |
8486 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8487 | ret = -ENODEV; | |
ab3951eb | 8488 | goto err_unpin; |
cb05d8de DV |
8489 | } |
8490 | ||
ffe74d75 CW |
8491 | len = 4; |
8492 | if (ring->id == RCS) | |
8493 | len += 6; | |
8494 | ||
8495 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8496 | if (ret) |
83d4092b | 8497 | goto err_unpin; |
7c9017e5 | 8498 | |
ffe74d75 CW |
8499 | /* Unmask the flip-done completion message. Note that the bspec says that |
8500 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8501 | * more than one flip event at any time (or ensure that one flip message | |
8502 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8503 | * Experimentation says that BCS works despite DERRMR masking all | |
8504 | * flip-done completion events and that unmasking all planes at once | |
8505 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8506 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8507 | */ | |
8508 | if (ring->id == RCS) { | |
8509 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8510 | intel_ring_emit(ring, DERRMR); | |
8511 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8512 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8513 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
8514 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
8515 | intel_ring_emit(ring, DERRMR); | |
8516 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8517 | } | |
8518 | ||
cb05d8de | 8519 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8520 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8521 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8522 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8523 | |
8524 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8525 | __intel_ring_advance(ring); |
83d4092b CW |
8526 | return 0; |
8527 | ||
8528 | err_unpin: | |
8529 | intel_unpin_fb_obj(obj); | |
8530 | err: | |
7c9017e5 JB |
8531 | return ret; |
8532 | } | |
8533 | ||
8c9f3aaf JB |
8534 | static int intel_default_queue_flip(struct drm_device *dev, |
8535 | struct drm_crtc *crtc, | |
8536 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8537 | struct drm_i915_gem_object *obj, |
8538 | uint32_t flags) | |
8c9f3aaf JB |
8539 | { |
8540 | return -ENODEV; | |
8541 | } | |
8542 | ||
6b95a207 KH |
8543 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8544 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8545 | struct drm_pending_vblank_event *event, |
8546 | uint32_t page_flip_flags) | |
6b95a207 KH |
8547 | { |
8548 | struct drm_device *dev = crtc->dev; | |
8549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8550 | struct drm_framebuffer *old_fb = crtc->fb; |
8551 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8553 | struct intel_unpin_work *work; | |
8c9f3aaf | 8554 | unsigned long flags; |
52e68630 | 8555 | int ret; |
6b95a207 | 8556 | |
e6a595d2 VS |
8557 | /* Can't change pixel format via MI display flips. */ |
8558 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8559 | return -EINVAL; | |
8560 | ||
8561 | /* | |
8562 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8563 | * Note that pitch changes could also affect these register. | |
8564 | */ | |
8565 | if (INTEL_INFO(dev)->gen > 3 && | |
8566 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8567 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8568 | return -EINVAL; | |
8569 | ||
b14c5679 | 8570 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8571 | if (work == NULL) |
8572 | return -ENOMEM; | |
8573 | ||
6b95a207 | 8574 | work->event = event; |
b4a98e57 | 8575 | work->crtc = crtc; |
4a35f83b | 8576 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8577 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8578 | ||
7317c75e JB |
8579 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8580 | if (ret) | |
8581 | goto free_work; | |
8582 | ||
6b95a207 KH |
8583 | /* We borrow the event spin lock for protecting unpin_work */ |
8584 | spin_lock_irqsave(&dev->event_lock, flags); | |
8585 | if (intel_crtc->unpin_work) { | |
8586 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8587 | kfree(work); | |
7317c75e | 8588 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8589 | |
8590 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8591 | return -EBUSY; |
8592 | } | |
8593 | intel_crtc->unpin_work = work; | |
8594 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8595 | ||
b4a98e57 CW |
8596 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8597 | flush_workqueue(dev_priv->wq); | |
8598 | ||
79158103 CW |
8599 | ret = i915_mutex_lock_interruptible(dev); |
8600 | if (ret) | |
8601 | goto cleanup; | |
6b95a207 | 8602 | |
75dfca80 | 8603 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8604 | drm_gem_object_reference(&work->old_fb_obj->base); |
8605 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8606 | |
8607 | crtc->fb = fb; | |
96b099fd | 8608 | |
e1f99ce6 | 8609 | work->pending_flip_obj = obj; |
e1f99ce6 | 8610 | |
4e5359cd SF |
8611 | work->enable_stall_check = true; |
8612 | ||
b4a98e57 | 8613 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8614 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8615 | |
ed8d1975 | 8616 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8617 | if (ret) |
8618 | goto cleanup_pending; | |
6b95a207 | 8619 | |
7782de3b | 8620 | intel_disable_fbc(dev); |
c65355bb | 8621 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8622 | mutex_unlock(&dev->struct_mutex); |
8623 | ||
e5510fac JB |
8624 | trace_i915_flip_request(intel_crtc->plane, obj); |
8625 | ||
6b95a207 | 8626 | return 0; |
96b099fd | 8627 | |
8c9f3aaf | 8628 | cleanup_pending: |
b4a98e57 | 8629 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8630 | crtc->fb = old_fb; |
05394f39 CW |
8631 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8632 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8633 | mutex_unlock(&dev->struct_mutex); |
8634 | ||
79158103 | 8635 | cleanup: |
96b099fd CW |
8636 | spin_lock_irqsave(&dev->event_lock, flags); |
8637 | intel_crtc->unpin_work = NULL; | |
8638 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8639 | ||
7317c75e JB |
8640 | drm_vblank_put(dev, intel_crtc->pipe); |
8641 | free_work: | |
96b099fd CW |
8642 | kfree(work); |
8643 | ||
8644 | return ret; | |
6b95a207 KH |
8645 | } |
8646 | ||
f6e5b160 | 8647 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8648 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8649 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8650 | }; |
8651 | ||
50f56119 DV |
8652 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8653 | struct drm_crtc *crtc) | |
8654 | { | |
8655 | struct drm_device *dev; | |
8656 | struct drm_crtc *tmp; | |
8657 | int crtc_mask = 1; | |
47f1c6c9 | 8658 | |
50f56119 | 8659 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8660 | |
50f56119 | 8661 | dev = crtc->dev; |
47f1c6c9 | 8662 | |
50f56119 DV |
8663 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8664 | if (tmp == crtc) | |
8665 | break; | |
8666 | crtc_mask <<= 1; | |
8667 | } | |
47f1c6c9 | 8668 | |
50f56119 DV |
8669 | if (encoder->possible_crtcs & crtc_mask) |
8670 | return true; | |
8671 | return false; | |
47f1c6c9 | 8672 | } |
79e53945 | 8673 | |
9a935856 DV |
8674 | /** |
8675 | * intel_modeset_update_staged_output_state | |
8676 | * | |
8677 | * Updates the staged output configuration state, e.g. after we've read out the | |
8678 | * current hw state. | |
8679 | */ | |
8680 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8681 | { |
9a935856 DV |
8682 | struct intel_encoder *encoder; |
8683 | struct intel_connector *connector; | |
f6e5b160 | 8684 | |
9a935856 DV |
8685 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8686 | base.head) { | |
8687 | connector->new_encoder = | |
8688 | to_intel_encoder(connector->base.encoder); | |
8689 | } | |
f6e5b160 | 8690 | |
9a935856 DV |
8691 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8692 | base.head) { | |
8693 | encoder->new_crtc = | |
8694 | to_intel_crtc(encoder->base.crtc); | |
8695 | } | |
f6e5b160 CW |
8696 | } |
8697 | ||
9a935856 DV |
8698 | /** |
8699 | * intel_modeset_commit_output_state | |
8700 | * | |
8701 | * This function copies the stage display pipe configuration to the real one. | |
8702 | */ | |
8703 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8704 | { | |
8705 | struct intel_encoder *encoder; | |
8706 | struct intel_connector *connector; | |
f6e5b160 | 8707 | |
9a935856 DV |
8708 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8709 | base.head) { | |
8710 | connector->base.encoder = &connector->new_encoder->base; | |
8711 | } | |
f6e5b160 | 8712 | |
9a935856 DV |
8713 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8714 | base.head) { | |
8715 | encoder->base.crtc = &encoder->new_crtc->base; | |
8716 | } | |
8717 | } | |
8718 | ||
050f7aeb DV |
8719 | static void |
8720 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8721 | struct intel_crtc_config *pipe_config) | |
8722 | { | |
8723 | int bpp = pipe_config->pipe_bpp; | |
8724 | ||
8725 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8726 | connector->base.base.id, | |
8727 | drm_get_connector_name(&connector->base)); | |
8728 | ||
8729 | /* Don't use an invalid EDID bpc value */ | |
8730 | if (connector->base.display_info.bpc && | |
8731 | connector->base.display_info.bpc * 3 < bpp) { | |
8732 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8733 | bpp, connector->base.display_info.bpc*3); | |
8734 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8735 | } | |
8736 | ||
8737 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8738 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8739 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8740 | bpp); | |
8741 | pipe_config->pipe_bpp = 24; | |
8742 | } | |
8743 | } | |
8744 | ||
4e53c2e0 | 8745 | static int |
050f7aeb DV |
8746 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8747 | struct drm_framebuffer *fb, | |
8748 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8749 | { |
050f7aeb DV |
8750 | struct drm_device *dev = crtc->base.dev; |
8751 | struct intel_connector *connector; | |
4e53c2e0 DV |
8752 | int bpp; |
8753 | ||
d42264b1 DV |
8754 | switch (fb->pixel_format) { |
8755 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8756 | bpp = 8*3; /* since we go through a colormap */ |
8757 | break; | |
d42264b1 DV |
8758 | case DRM_FORMAT_XRGB1555: |
8759 | case DRM_FORMAT_ARGB1555: | |
8760 | /* checked in intel_framebuffer_init already */ | |
8761 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8762 | return -EINVAL; | |
8763 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8764 | bpp = 6*3; /* min is 18bpp */ |
8765 | break; | |
d42264b1 DV |
8766 | case DRM_FORMAT_XBGR8888: |
8767 | case DRM_FORMAT_ABGR8888: | |
8768 | /* checked in intel_framebuffer_init already */ | |
8769 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8770 | return -EINVAL; | |
8771 | case DRM_FORMAT_XRGB8888: | |
8772 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8773 | bpp = 8*3; |
8774 | break; | |
d42264b1 DV |
8775 | case DRM_FORMAT_XRGB2101010: |
8776 | case DRM_FORMAT_ARGB2101010: | |
8777 | case DRM_FORMAT_XBGR2101010: | |
8778 | case DRM_FORMAT_ABGR2101010: | |
8779 | /* checked in intel_framebuffer_init already */ | |
8780 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8781 | return -EINVAL; |
4e53c2e0 DV |
8782 | bpp = 10*3; |
8783 | break; | |
baba133a | 8784 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8785 | default: |
8786 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8787 | return -EINVAL; | |
8788 | } | |
8789 | ||
4e53c2e0 DV |
8790 | pipe_config->pipe_bpp = bpp; |
8791 | ||
8792 | /* Clamp display bpp to EDID value */ | |
8793 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8794 | base.head) { |
1b829e05 DV |
8795 | if (!connector->new_encoder || |
8796 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8797 | continue; |
8798 | ||
050f7aeb | 8799 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8800 | } |
8801 | ||
8802 | return bpp; | |
8803 | } | |
8804 | ||
644db711 DV |
8805 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8806 | { | |
8807 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8808 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8809 | mode->crtc_clock, |
644db711 DV |
8810 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8811 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8812 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8813 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8814 | } | |
8815 | ||
c0b03411 DV |
8816 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8817 | struct intel_crtc_config *pipe_config, | |
8818 | const char *context) | |
8819 | { | |
8820 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8821 | context, pipe_name(crtc->pipe)); | |
8822 | ||
8823 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8824 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8825 | pipe_config->pipe_bpp, pipe_config->dither); | |
8826 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8827 | pipe_config->has_pch_encoder, | |
8828 | pipe_config->fdi_lanes, | |
8829 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8830 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8831 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8832 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8833 | pipe_config->has_dp_encoder, | |
8834 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8835 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8836 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8837 | DRM_DEBUG_KMS("requested mode:\n"); |
8838 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8839 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8840 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8841 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8842 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8843 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8844 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8845 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8846 | pipe_config->gmch_pfit.control, | |
8847 | pipe_config->gmch_pfit.pgm_ratios, | |
8848 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8849 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8850 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8851 | pipe_config->pch_pfit.size, |
8852 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8853 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8854 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8855 | } |
8856 | ||
accfc0c5 DV |
8857 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8858 | { | |
8859 | int num_encoders = 0; | |
8860 | bool uncloneable_encoders = false; | |
8861 | struct intel_encoder *encoder; | |
8862 | ||
8863 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8864 | base.head) { | |
8865 | if (&encoder->new_crtc->base != crtc) | |
8866 | continue; | |
8867 | ||
8868 | num_encoders++; | |
8869 | if (!encoder->cloneable) | |
8870 | uncloneable_encoders = true; | |
8871 | } | |
8872 | ||
8873 | return !(num_encoders > 1 && uncloneable_encoders); | |
8874 | } | |
8875 | ||
b8cecdf5 DV |
8876 | static struct intel_crtc_config * |
8877 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8878 | struct drm_framebuffer *fb, |
b8cecdf5 | 8879 | struct drm_display_mode *mode) |
ee7b9f93 | 8880 | { |
7758a113 | 8881 | struct drm_device *dev = crtc->dev; |
7758a113 | 8882 | struct intel_encoder *encoder; |
b8cecdf5 | 8883 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8884 | int plane_bpp, ret = -EINVAL; |
8885 | bool retry = true; | |
ee7b9f93 | 8886 | |
accfc0c5 DV |
8887 | if (!check_encoder_cloning(crtc)) { |
8888 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8889 | return ERR_PTR(-EINVAL); | |
8890 | } | |
8891 | ||
b8cecdf5 DV |
8892 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8893 | if (!pipe_config) | |
7758a113 DV |
8894 | return ERR_PTR(-ENOMEM); |
8895 | ||
b8cecdf5 DV |
8896 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8897 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 8898 | |
e143a21c DV |
8899 | pipe_config->cpu_transcoder = |
8900 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8901 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8902 | |
2960bc9c ID |
8903 | /* |
8904 | * Sanitize sync polarity flags based on requested ones. If neither | |
8905 | * positive or negative polarity is requested, treat this as meaning | |
8906 | * negative polarity. | |
8907 | */ | |
8908 | if (!(pipe_config->adjusted_mode.flags & | |
8909 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8910 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8911 | ||
8912 | if (!(pipe_config->adjusted_mode.flags & | |
8913 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8914 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8915 | ||
050f7aeb DV |
8916 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8917 | * plane pixel format and any sink constraints into account. Returns the | |
8918 | * source plane bpp so that dithering can be selected on mismatches | |
8919 | * after encoders and crtc also have had their say. */ | |
8920 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8921 | fb, pipe_config); | |
4e53c2e0 DV |
8922 | if (plane_bpp < 0) |
8923 | goto fail; | |
8924 | ||
e41a56be VS |
8925 | /* |
8926 | * Determine the real pipe dimensions. Note that stereo modes can | |
8927 | * increase the actual pipe size due to the frame doubling and | |
8928 | * insertion of additional space for blanks between the frame. This | |
8929 | * is stored in the crtc timings. We use the requested mode to do this | |
8930 | * computation to clearly distinguish it from the adjusted mode, which | |
8931 | * can be changed by the connectors in the below retry loop. | |
8932 | */ | |
8933 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
8934 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
8935 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
8936 | ||
e29c22c0 | 8937 | encoder_retry: |
ef1b460d | 8938 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8939 | pipe_config->port_clock = 0; |
ef1b460d | 8940 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8941 | |
135c81b8 | 8942 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 8943 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 8944 | |
7758a113 DV |
8945 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8946 | * adjust it according to limitations or connector properties, and also | |
8947 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8948 | */ |
7758a113 DV |
8949 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8950 | base.head) { | |
47f1c6c9 | 8951 | |
7758a113 DV |
8952 | if (&encoder->new_crtc->base != crtc) |
8953 | continue; | |
7ae89233 | 8954 | |
efea6e8e DV |
8955 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8956 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
8957 | goto fail; |
8958 | } | |
ee7b9f93 | 8959 | } |
47f1c6c9 | 8960 | |
ff9a6750 DV |
8961 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8962 | * done afterwards in case the encoder adjusts the mode. */ | |
8963 | if (!pipe_config->port_clock) | |
241bfc38 DL |
8964 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
8965 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 8966 | |
a43f6e0f | 8967 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 8968 | if (ret < 0) { |
7758a113 DV |
8969 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8970 | goto fail; | |
ee7b9f93 | 8971 | } |
e29c22c0 DV |
8972 | |
8973 | if (ret == RETRY) { | |
8974 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
8975 | ret = -EINVAL; | |
8976 | goto fail; | |
8977 | } | |
8978 | ||
8979 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
8980 | retry = false; | |
8981 | goto encoder_retry; | |
8982 | } | |
8983 | ||
4e53c2e0 DV |
8984 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8985 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
8986 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
8987 | ||
b8cecdf5 | 8988 | return pipe_config; |
7758a113 | 8989 | fail: |
b8cecdf5 | 8990 | kfree(pipe_config); |
e29c22c0 | 8991 | return ERR_PTR(ret); |
ee7b9f93 | 8992 | } |
47f1c6c9 | 8993 | |
e2e1ed41 DV |
8994 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8995 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
8996 | static void | |
8997 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
8998 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
8999 | { |
9000 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9001 | struct drm_device *dev = crtc->dev; |
9002 | struct intel_encoder *encoder; | |
9003 | struct intel_connector *connector; | |
9004 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9005 | |
e2e1ed41 | 9006 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9007 | |
e2e1ed41 DV |
9008 | /* Check which crtcs have changed outputs connected to them, these need |
9009 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9010 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9011 | * bit set at most. */ | |
9012 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9013 | base.head) { | |
9014 | if (connector->base.encoder == &connector->new_encoder->base) | |
9015 | continue; | |
79e53945 | 9016 | |
e2e1ed41 DV |
9017 | if (connector->base.encoder) { |
9018 | tmp_crtc = connector->base.encoder->crtc; | |
9019 | ||
9020 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9021 | } | |
9022 | ||
9023 | if (connector->new_encoder) | |
9024 | *prepare_pipes |= | |
9025 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9026 | } |
9027 | ||
e2e1ed41 DV |
9028 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9029 | base.head) { | |
9030 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9031 | continue; | |
9032 | ||
9033 | if (encoder->base.crtc) { | |
9034 | tmp_crtc = encoder->base.crtc; | |
9035 | ||
9036 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9037 | } | |
9038 | ||
9039 | if (encoder->new_crtc) | |
9040 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9041 | } |
9042 | ||
e2e1ed41 DV |
9043 | /* Check for any pipes that will be fully disabled ... */ |
9044 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9045 | base.head) { | |
9046 | bool used = false; | |
22fd0fab | 9047 | |
e2e1ed41 DV |
9048 | /* Don't try to disable disabled crtcs. */ |
9049 | if (!intel_crtc->base.enabled) | |
9050 | continue; | |
7e7d76c3 | 9051 | |
e2e1ed41 DV |
9052 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9053 | base.head) { | |
9054 | if (encoder->new_crtc == intel_crtc) | |
9055 | used = true; | |
9056 | } | |
9057 | ||
9058 | if (!used) | |
9059 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9060 | } |
9061 | ||
e2e1ed41 DV |
9062 | |
9063 | /* set_mode is also used to update properties on life display pipes. */ | |
9064 | intel_crtc = to_intel_crtc(crtc); | |
9065 | if (crtc->enabled) | |
9066 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
9067 | ||
b6c5164d DV |
9068 | /* |
9069 | * For simplicity do a full modeset on any pipe where the output routing | |
9070 | * changed. We could be more clever, but that would require us to be | |
9071 | * more careful with calling the relevant encoder->mode_set functions. | |
9072 | */ | |
e2e1ed41 DV |
9073 | if (*prepare_pipes) |
9074 | *modeset_pipes = *prepare_pipes; | |
9075 | ||
9076 | /* ... and mask these out. */ | |
9077 | *modeset_pipes &= ~(*disable_pipes); | |
9078 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9079 | |
9080 | /* | |
9081 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9082 | * obies this rule, but the modeset restore mode of | |
9083 | * intel_modeset_setup_hw_state does not. | |
9084 | */ | |
9085 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9086 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9087 | |
9088 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9089 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9090 | } |
79e53945 | 9091 | |
ea9d758d | 9092 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9093 | { |
ea9d758d | 9094 | struct drm_encoder *encoder; |
f6e5b160 | 9095 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9096 | |
ea9d758d DV |
9097 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9098 | if (encoder->crtc == crtc) | |
9099 | return true; | |
9100 | ||
9101 | return false; | |
9102 | } | |
9103 | ||
9104 | static void | |
9105 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9106 | { | |
9107 | struct intel_encoder *intel_encoder; | |
9108 | struct intel_crtc *intel_crtc; | |
9109 | struct drm_connector *connector; | |
9110 | ||
9111 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9112 | base.head) { | |
9113 | if (!intel_encoder->base.crtc) | |
9114 | continue; | |
9115 | ||
9116 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9117 | ||
9118 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9119 | intel_encoder->connectors_active = false; | |
9120 | } | |
9121 | ||
9122 | intel_modeset_commit_output_state(dev); | |
9123 | ||
9124 | /* Update computed state. */ | |
9125 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9126 | base.head) { | |
9127 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
9128 | } | |
9129 | ||
9130 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9131 | if (!connector->encoder || !connector->encoder->crtc) | |
9132 | continue; | |
9133 | ||
9134 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9135 | ||
9136 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9137 | struct drm_property *dpms_property = |
9138 | dev->mode_config.dpms_property; | |
9139 | ||
ea9d758d | 9140 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9141 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9142 | dpms_property, |
9143 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9144 | |
9145 | intel_encoder = to_intel_encoder(connector->encoder); | |
9146 | intel_encoder->connectors_active = true; | |
9147 | } | |
9148 | } | |
9149 | ||
9150 | } | |
9151 | ||
3bd26263 | 9152 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9153 | { |
3bd26263 | 9154 | int diff; |
f1f644dc JB |
9155 | |
9156 | if (clock1 == clock2) | |
9157 | return true; | |
9158 | ||
9159 | if (!clock1 || !clock2) | |
9160 | return false; | |
9161 | ||
9162 | diff = abs(clock1 - clock2); | |
9163 | ||
9164 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9165 | return true; | |
9166 | ||
9167 | return false; | |
9168 | } | |
9169 | ||
25c5b266 DV |
9170 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9171 | list_for_each_entry((intel_crtc), \ | |
9172 | &(dev)->mode_config.crtc_list, \ | |
9173 | base.head) \ | |
0973f18f | 9174 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9175 | |
0e8ffe1b | 9176 | static bool |
2fa2fe9a DV |
9177 | intel_pipe_config_compare(struct drm_device *dev, |
9178 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9179 | struct intel_crtc_config *pipe_config) |
9180 | { | |
66e985c0 DV |
9181 | #define PIPE_CONF_CHECK_X(name) \ |
9182 | if (current_config->name != pipe_config->name) { \ | |
9183 | DRM_ERROR("mismatch in " #name " " \ | |
9184 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9185 | current_config->name, \ | |
9186 | pipe_config->name); \ | |
9187 | return false; \ | |
9188 | } | |
9189 | ||
08a24034 DV |
9190 | #define PIPE_CONF_CHECK_I(name) \ |
9191 | if (current_config->name != pipe_config->name) { \ | |
9192 | DRM_ERROR("mismatch in " #name " " \ | |
9193 | "(expected %i, found %i)\n", \ | |
9194 | current_config->name, \ | |
9195 | pipe_config->name); \ | |
9196 | return false; \ | |
88adfff1 DV |
9197 | } |
9198 | ||
1bd1bd80 DV |
9199 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9200 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9201 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9202 | "(expected %i, found %i)\n", \ |
9203 | current_config->name & (mask), \ | |
9204 | pipe_config->name & (mask)); \ | |
9205 | return false; \ | |
9206 | } | |
9207 | ||
5e550656 VS |
9208 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9209 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9210 | DRM_ERROR("mismatch in " #name " " \ | |
9211 | "(expected %i, found %i)\n", \ | |
9212 | current_config->name, \ | |
9213 | pipe_config->name); \ | |
9214 | return false; \ | |
9215 | } | |
9216 | ||
bb760063 DV |
9217 | #define PIPE_CONF_QUIRK(quirk) \ |
9218 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9219 | ||
eccb140b DV |
9220 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9221 | ||
08a24034 DV |
9222 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9223 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9224 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9225 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9226 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9227 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9228 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9229 | |
eb14cb74 VS |
9230 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9231 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9232 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9233 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9234 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9235 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9236 | ||
1bd1bd80 DV |
9237 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9238 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9239 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9240 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9241 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9242 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9243 | ||
9244 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9245 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9246 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9247 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9248 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9249 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9250 | ||
c93f54cf | 9251 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9252 | |
1bd1bd80 DV |
9253 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9254 | DRM_MODE_FLAG_INTERLACE); | |
9255 | ||
bb760063 DV |
9256 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9257 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9258 | DRM_MODE_FLAG_PHSYNC); | |
9259 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9260 | DRM_MODE_FLAG_NHSYNC); | |
9261 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9262 | DRM_MODE_FLAG_PVSYNC); | |
9263 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9264 | DRM_MODE_FLAG_NVSYNC); | |
9265 | } | |
045ac3b5 | 9266 | |
37327abd VS |
9267 | PIPE_CONF_CHECK_I(pipe_src_w); |
9268 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9269 | |
2fa2fe9a DV |
9270 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9271 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9272 | if (INTEL_INFO(dev)->gen < 4) | |
9273 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9274 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9275 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9276 | if (current_config->pch_pfit.enabled) { | |
9277 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9278 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9279 | } | |
2fa2fe9a | 9280 | |
42db64ef PZ |
9281 | PIPE_CONF_CHECK_I(ips_enabled); |
9282 | ||
282740f7 VS |
9283 | PIPE_CONF_CHECK_I(double_wide); |
9284 | ||
c0d43d62 | 9285 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9286 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9287 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9288 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9289 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9290 | |
42571aef VS |
9291 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9292 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9293 | ||
d71b8d4a | 9294 | if (!IS_HASWELL(dev)) { |
241bfc38 | 9295 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
d71b8d4a VS |
9296 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9297 | } | |
5e550656 | 9298 | |
66e985c0 | 9299 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9300 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9301 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9302 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9303 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9304 | |
0e8ffe1b DV |
9305 | return true; |
9306 | } | |
9307 | ||
91d1b4bd DV |
9308 | static void |
9309 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9310 | { |
8af6cf88 DV |
9311 | struct intel_connector *connector; |
9312 | ||
9313 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9314 | base.head) { | |
9315 | /* This also checks the encoder/connector hw state with the | |
9316 | * ->get_hw_state callbacks. */ | |
9317 | intel_connector_check_state(connector); | |
9318 | ||
9319 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9320 | "connector's staged encoder doesn't match current encoder\n"); | |
9321 | } | |
91d1b4bd DV |
9322 | } |
9323 | ||
9324 | static void | |
9325 | check_encoder_state(struct drm_device *dev) | |
9326 | { | |
9327 | struct intel_encoder *encoder; | |
9328 | struct intel_connector *connector; | |
8af6cf88 DV |
9329 | |
9330 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9331 | base.head) { | |
9332 | bool enabled = false; | |
9333 | bool active = false; | |
9334 | enum pipe pipe, tracked_pipe; | |
9335 | ||
9336 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9337 | encoder->base.base.id, | |
9338 | drm_get_encoder_name(&encoder->base)); | |
9339 | ||
9340 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9341 | "encoder's stage crtc doesn't match current crtc\n"); | |
9342 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9343 | "encoder's active_connectors set, but no crtc\n"); | |
9344 | ||
9345 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9346 | base.head) { | |
9347 | if (connector->base.encoder != &encoder->base) | |
9348 | continue; | |
9349 | enabled = true; | |
9350 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9351 | active = true; | |
9352 | } | |
9353 | WARN(!!encoder->base.crtc != enabled, | |
9354 | "encoder's enabled state mismatch " | |
9355 | "(expected %i, found %i)\n", | |
9356 | !!encoder->base.crtc, enabled); | |
9357 | WARN(active && !encoder->base.crtc, | |
9358 | "active encoder with no crtc\n"); | |
9359 | ||
9360 | WARN(encoder->connectors_active != active, | |
9361 | "encoder's computed active state doesn't match tracked active state " | |
9362 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9363 | ||
9364 | active = encoder->get_hw_state(encoder, &pipe); | |
9365 | WARN(active != encoder->connectors_active, | |
9366 | "encoder's hw state doesn't match sw tracking " | |
9367 | "(expected %i, found %i)\n", | |
9368 | encoder->connectors_active, active); | |
9369 | ||
9370 | if (!encoder->base.crtc) | |
9371 | continue; | |
9372 | ||
9373 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9374 | WARN(active && pipe != tracked_pipe, | |
9375 | "active encoder's pipe doesn't match" | |
9376 | "(expected %i, found %i)\n", | |
9377 | tracked_pipe, pipe); | |
9378 | ||
9379 | } | |
91d1b4bd DV |
9380 | } |
9381 | ||
9382 | static void | |
9383 | check_crtc_state(struct drm_device *dev) | |
9384 | { | |
9385 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9386 | struct intel_crtc *crtc; | |
9387 | struct intel_encoder *encoder; | |
9388 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9389 | |
9390 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9391 | base.head) { | |
9392 | bool enabled = false; | |
9393 | bool active = false; | |
9394 | ||
045ac3b5 JB |
9395 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9396 | ||
8af6cf88 DV |
9397 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9398 | crtc->base.base.id); | |
9399 | ||
9400 | WARN(crtc->active && !crtc->base.enabled, | |
9401 | "active crtc, but not enabled in sw tracking\n"); | |
9402 | ||
9403 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9404 | base.head) { | |
9405 | if (encoder->base.crtc != &crtc->base) | |
9406 | continue; | |
9407 | enabled = true; | |
9408 | if (encoder->connectors_active) | |
9409 | active = true; | |
9410 | } | |
6c49f241 | 9411 | |
8af6cf88 DV |
9412 | WARN(active != crtc->active, |
9413 | "crtc's computed active state doesn't match tracked active state " | |
9414 | "(expected %i, found %i)\n", active, crtc->active); | |
9415 | WARN(enabled != crtc->base.enabled, | |
9416 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9417 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9418 | ||
0e8ffe1b DV |
9419 | active = dev_priv->display.get_pipe_config(crtc, |
9420 | &pipe_config); | |
d62cf62a DV |
9421 | |
9422 | /* hw state is inconsistent with the pipe A quirk */ | |
9423 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9424 | active = crtc->active; | |
9425 | ||
6c49f241 DV |
9426 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9427 | base.head) { | |
3eaba51c | 9428 | enum pipe pipe; |
6c49f241 DV |
9429 | if (encoder->base.crtc != &crtc->base) |
9430 | continue; | |
3eaba51c VS |
9431 | if (encoder->get_config && |
9432 | encoder->get_hw_state(encoder, &pipe)) | |
6c49f241 DV |
9433 | encoder->get_config(encoder, &pipe_config); |
9434 | } | |
9435 | ||
0e8ffe1b DV |
9436 | WARN(crtc->active != active, |
9437 | "crtc active state doesn't match with hw state " | |
9438 | "(expected %i, found %i)\n", crtc->active, active); | |
9439 | ||
c0b03411 DV |
9440 | if (active && |
9441 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9442 | WARN(1, "pipe state doesn't match!\n"); | |
9443 | intel_dump_pipe_config(crtc, &pipe_config, | |
9444 | "[hw state]"); | |
9445 | intel_dump_pipe_config(crtc, &crtc->config, | |
9446 | "[sw state]"); | |
9447 | } | |
8af6cf88 DV |
9448 | } |
9449 | } | |
9450 | ||
91d1b4bd DV |
9451 | static void |
9452 | check_shared_dpll_state(struct drm_device *dev) | |
9453 | { | |
9454 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9455 | struct intel_crtc *crtc; | |
9456 | struct intel_dpll_hw_state dpll_hw_state; | |
9457 | int i; | |
5358901f DV |
9458 | |
9459 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9460 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9461 | int enabled_crtcs = 0, active_crtcs = 0; | |
9462 | bool active; | |
9463 | ||
9464 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9465 | ||
9466 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9467 | ||
9468 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9469 | ||
9470 | WARN(pll->active > pll->refcount, | |
9471 | "more active pll users than references: %i vs %i\n", | |
9472 | pll->active, pll->refcount); | |
9473 | WARN(pll->active && !pll->on, | |
9474 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9475 | WARN(pll->on && !pll->active, |
9476 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9477 | WARN(pll->on != active, |
9478 | "pll on state mismatch (expected %i, found %i)\n", | |
9479 | pll->on, active); | |
9480 | ||
9481 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9482 | base.head) { | |
9483 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9484 | enabled_crtcs++; | |
9485 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9486 | active_crtcs++; | |
9487 | } | |
9488 | WARN(pll->active != active_crtcs, | |
9489 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9490 | pll->active, active_crtcs); | |
9491 | WARN(pll->refcount != enabled_crtcs, | |
9492 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9493 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9494 | |
9495 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9496 | sizeof(dpll_hw_state)), | |
9497 | "pll hw state mismatch\n"); | |
5358901f | 9498 | } |
8af6cf88 DV |
9499 | } |
9500 | ||
91d1b4bd DV |
9501 | void |
9502 | intel_modeset_check_state(struct drm_device *dev) | |
9503 | { | |
9504 | check_connector_state(dev); | |
9505 | check_encoder_state(dev); | |
9506 | check_crtc_state(dev); | |
9507 | check_shared_dpll_state(dev); | |
9508 | } | |
9509 | ||
18442d08 VS |
9510 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9511 | int dotclock) | |
9512 | { | |
9513 | /* | |
9514 | * FDI already provided one idea for the dotclock. | |
9515 | * Yell if the encoder disagrees. | |
9516 | */ | |
241bfc38 | 9517 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9518 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9519 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9520 | } |
9521 | ||
f30da187 DV |
9522 | static int __intel_set_mode(struct drm_crtc *crtc, |
9523 | struct drm_display_mode *mode, | |
9524 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9525 | { |
9526 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9527 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
9528 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9529 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
9530 | struct intel_crtc *intel_crtc; |
9531 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9532 | int ret = 0; |
a6778b3c | 9533 | |
a1e22653 | 9534 | saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9535 | if (!saved_mode) |
9536 | return -ENOMEM; | |
3ac18232 | 9537 | saved_hwmode = saved_mode + 1; |
a6778b3c | 9538 | |
e2e1ed41 | 9539 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9540 | &prepare_pipes, &disable_pipes); |
9541 | ||
3ac18232 TG |
9542 | *saved_hwmode = crtc->hwmode; |
9543 | *saved_mode = crtc->mode; | |
a6778b3c | 9544 | |
25c5b266 DV |
9545 | /* Hack: Because we don't (yet) support global modeset on multiple |
9546 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9547 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9548 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9549 | * changing their mode at the same time. */ | |
25c5b266 | 9550 | if (modeset_pipes) { |
4e53c2e0 | 9551 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9552 | if (IS_ERR(pipe_config)) { |
9553 | ret = PTR_ERR(pipe_config); | |
9554 | pipe_config = NULL; | |
9555 | ||
3ac18232 | 9556 | goto out; |
25c5b266 | 9557 | } |
c0b03411 DV |
9558 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9559 | "[modeset]"); | |
25c5b266 | 9560 | } |
a6778b3c | 9561 | |
30a970c6 JB |
9562 | /* |
9563 | * See if the config requires any additional preparation, e.g. | |
9564 | * to adjust global state with pipes off. We need to do this | |
9565 | * here so we can get the modeset_pipe updated config for the new | |
9566 | * mode set on this crtc. For other crtcs we need to use the | |
9567 | * adjusted_mode bits in the crtc directly. | |
9568 | */ | |
c164f833 | 9569 | if (IS_VALLEYVIEW(dev)) { |
30a970c6 JB |
9570 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
9571 | modeset_pipes, pipe_config); | |
9572 | ||
c164f833 VS |
9573 | /* may have added more to prepare_pipes than we should */ |
9574 | prepare_pipes &= ~disable_pipes; | |
9575 | } | |
9576 | ||
460da916 DV |
9577 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9578 | intel_crtc_disable(&intel_crtc->base); | |
9579 | ||
ea9d758d DV |
9580 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9581 | if (intel_crtc->base.enabled) | |
9582 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9583 | } | |
a6778b3c | 9584 | |
6c4c86f5 DV |
9585 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9586 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9587 | */ |
b8cecdf5 | 9588 | if (modeset_pipes) { |
25c5b266 | 9589 | crtc->mode = *mode; |
b8cecdf5 DV |
9590 | /* mode_set/enable/disable functions rely on a correct pipe |
9591 | * config. */ | |
9592 | to_intel_crtc(crtc)->config = *pipe_config; | |
9593 | } | |
7758a113 | 9594 | |
ea9d758d DV |
9595 | /* Only after disabling all output pipelines that will be changed can we |
9596 | * update the the output configuration. */ | |
9597 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9598 | |
47fab737 DV |
9599 | if (dev_priv->display.modeset_global_resources) |
9600 | dev_priv->display.modeset_global_resources(dev); | |
9601 | ||
a6778b3c DV |
9602 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9603 | * on the DPLL. | |
f6e5b160 | 9604 | */ |
25c5b266 | 9605 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9606 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9607 | x, y, fb); |
9608 | if (ret) | |
9609 | goto done; | |
a6778b3c DV |
9610 | } |
9611 | ||
9612 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9613 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9614 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9615 | |
25c5b266 DV |
9616 | if (modeset_pipes) { |
9617 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 9618 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 9619 | |
25c5b266 DV |
9620 | /* Calculate and store various constants which |
9621 | * are later needed by vblank and swap-completion | |
9622 | * timestamping. They are derived from true hwmode. | |
9623 | */ | |
9624 | drm_calc_timestamping_constants(crtc); | |
9625 | } | |
a6778b3c DV |
9626 | |
9627 | /* FIXME: add subpixel order */ | |
9628 | done: | |
c0c36b94 | 9629 | if (ret && crtc->enabled) { |
3ac18232 TG |
9630 | crtc->hwmode = *saved_hwmode; |
9631 | crtc->mode = *saved_mode; | |
a6778b3c DV |
9632 | } |
9633 | ||
3ac18232 | 9634 | out: |
b8cecdf5 | 9635 | kfree(pipe_config); |
3ac18232 | 9636 | kfree(saved_mode); |
a6778b3c | 9637 | return ret; |
f6e5b160 CW |
9638 | } |
9639 | ||
e7457a9a DL |
9640 | static int intel_set_mode(struct drm_crtc *crtc, |
9641 | struct drm_display_mode *mode, | |
9642 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9643 | { |
9644 | int ret; | |
9645 | ||
9646 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9647 | ||
9648 | if (ret == 0) | |
9649 | intel_modeset_check_state(crtc->dev); | |
9650 | ||
9651 | return ret; | |
9652 | } | |
9653 | ||
c0c36b94 CW |
9654 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9655 | { | |
9656 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9657 | } | |
9658 | ||
25c5b266 DV |
9659 | #undef for_each_intel_crtc_masked |
9660 | ||
d9e55608 DV |
9661 | static void intel_set_config_free(struct intel_set_config *config) |
9662 | { | |
9663 | if (!config) | |
9664 | return; | |
9665 | ||
1aa4b628 DV |
9666 | kfree(config->save_connector_encoders); |
9667 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
9668 | kfree(config); |
9669 | } | |
9670 | ||
85f9eb71 DV |
9671 | static int intel_set_config_save_state(struct drm_device *dev, |
9672 | struct intel_set_config *config) | |
9673 | { | |
85f9eb71 DV |
9674 | struct drm_encoder *encoder; |
9675 | struct drm_connector *connector; | |
9676 | int count; | |
9677 | ||
1aa4b628 DV |
9678 | config->save_encoder_crtcs = |
9679 | kcalloc(dev->mode_config.num_encoder, | |
9680 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9681 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9682 | return -ENOMEM; |
9683 | ||
1aa4b628 DV |
9684 | config->save_connector_encoders = |
9685 | kcalloc(dev->mode_config.num_connector, | |
9686 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9687 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9688 | return -ENOMEM; |
9689 | ||
9690 | /* Copy data. Note that driver private data is not affected. | |
9691 | * Should anything bad happen only the expected state is | |
9692 | * restored, not the drivers personal bookkeeping. | |
9693 | */ | |
85f9eb71 DV |
9694 | count = 0; |
9695 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9696 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9697 | } |
9698 | ||
9699 | count = 0; | |
9700 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9701 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9702 | } |
9703 | ||
9704 | return 0; | |
9705 | } | |
9706 | ||
9707 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9708 | struct intel_set_config *config) | |
9709 | { | |
9a935856 DV |
9710 | struct intel_encoder *encoder; |
9711 | struct intel_connector *connector; | |
85f9eb71 DV |
9712 | int count; |
9713 | ||
85f9eb71 | 9714 | count = 0; |
9a935856 DV |
9715 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9716 | encoder->new_crtc = | |
9717 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9718 | } |
9719 | ||
9720 | count = 0; | |
9a935856 DV |
9721 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9722 | connector->new_encoder = | |
9723 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9724 | } |
9725 | } | |
9726 | ||
e3de42b6 | 9727 | static bool |
2e57f47d | 9728 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9729 | { |
9730 | int i; | |
9731 | ||
2e57f47d CW |
9732 | if (set->num_connectors == 0) |
9733 | return false; | |
9734 | ||
9735 | if (WARN_ON(set->connectors == NULL)) | |
9736 | return false; | |
9737 | ||
9738 | for (i = 0; i < set->num_connectors; i++) | |
9739 | if (set->connectors[i]->encoder && | |
9740 | set->connectors[i]->encoder->crtc == set->crtc && | |
9741 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9742 | return true; |
9743 | ||
9744 | return false; | |
9745 | } | |
9746 | ||
5e2b584e DV |
9747 | static void |
9748 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9749 | struct intel_set_config *config) | |
9750 | { | |
9751 | ||
9752 | /* We should be able to check here if the fb has the same properties | |
9753 | * and then just flip_or_move it */ | |
2e57f47d CW |
9754 | if (is_crtc_connector_off(set)) { |
9755 | config->mode_changed = true; | |
e3de42b6 | 9756 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9757 | /* If we have no fb then treat it as a full mode set */ |
9758 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9759 | struct intel_crtc *intel_crtc = |
9760 | to_intel_crtc(set->crtc); | |
9761 | ||
9762 | if (intel_crtc->active && i915_fastboot) { | |
9763 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9764 | config->fb_changed = true; | |
9765 | } else { | |
9766 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9767 | config->mode_changed = true; | |
9768 | } | |
5e2b584e DV |
9769 | } else if (set->fb == NULL) { |
9770 | config->mode_changed = true; | |
72f4901e DV |
9771 | } else if (set->fb->pixel_format != |
9772 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9773 | config->mode_changed = true; |
e3de42b6 | 9774 | } else { |
5e2b584e | 9775 | config->fb_changed = true; |
e3de42b6 | 9776 | } |
5e2b584e DV |
9777 | } |
9778 | ||
835c5873 | 9779 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9780 | config->fb_changed = true; |
9781 | ||
9782 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9783 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9784 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9785 | drm_mode_debug_printmodeline(set->mode); | |
9786 | config->mode_changed = true; | |
9787 | } | |
a1d95703 CW |
9788 | |
9789 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9790 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9791 | } |
9792 | ||
2e431051 | 9793 | static int |
9a935856 DV |
9794 | intel_modeset_stage_output_state(struct drm_device *dev, |
9795 | struct drm_mode_set *set, | |
9796 | struct intel_set_config *config) | |
50f56119 | 9797 | { |
85f9eb71 | 9798 | struct drm_crtc *new_crtc; |
9a935856 DV |
9799 | struct intel_connector *connector; |
9800 | struct intel_encoder *encoder; | |
f3f08572 | 9801 | int ro; |
50f56119 | 9802 | |
9abdda74 | 9803 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9804 | * of connectors. For paranoia, double-check this. */ |
9805 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9806 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9807 | ||
9a935856 DV |
9808 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9809 | base.head) { | |
9810 | /* Otherwise traverse passed in connector list and get encoders | |
9811 | * for them. */ | |
50f56119 | 9812 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9813 | if (set->connectors[ro] == &connector->base) { |
9814 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9815 | break; |
9816 | } | |
9817 | } | |
9818 | ||
9a935856 DV |
9819 | /* If we disable the crtc, disable all its connectors. Also, if |
9820 | * the connector is on the changing crtc but not on the new | |
9821 | * connector list, disable it. */ | |
9822 | if ((!set->fb || ro == set->num_connectors) && | |
9823 | connector->base.encoder && | |
9824 | connector->base.encoder->crtc == set->crtc) { | |
9825 | connector->new_encoder = NULL; | |
9826 | ||
9827 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9828 | connector->base.base.id, | |
9829 | drm_get_connector_name(&connector->base)); | |
9830 | } | |
9831 | ||
9832 | ||
9833 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9834 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9835 | config->mode_changed = true; |
50f56119 DV |
9836 | } |
9837 | } | |
9a935856 | 9838 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9839 | |
9a935856 | 9840 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9841 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9842 | base.head) { | |
9843 | if (!connector->new_encoder) | |
50f56119 DV |
9844 | continue; |
9845 | ||
9a935856 | 9846 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9847 | |
9848 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9849 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9850 | new_crtc = set->crtc; |
9851 | } | |
9852 | ||
9853 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9854 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9855 | new_crtc)) { | |
5e2b584e | 9856 | return -EINVAL; |
50f56119 | 9857 | } |
9a935856 DV |
9858 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9859 | ||
9860 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9861 | connector->base.base.id, | |
9862 | drm_get_connector_name(&connector->base), | |
9863 | new_crtc->base.id); | |
9864 | } | |
9865 | ||
9866 | /* Check for any encoders that needs to be disabled. */ | |
9867 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9868 | base.head) { | |
9869 | list_for_each_entry(connector, | |
9870 | &dev->mode_config.connector_list, | |
9871 | base.head) { | |
9872 | if (connector->new_encoder == encoder) { | |
9873 | WARN_ON(!connector->new_encoder->new_crtc); | |
9874 | ||
9875 | goto next_encoder; | |
9876 | } | |
9877 | } | |
9878 | encoder->new_crtc = NULL; | |
9879 | next_encoder: | |
9880 | /* Only now check for crtc changes so we don't miss encoders | |
9881 | * that will be disabled. */ | |
9882 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9883 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9884 | config->mode_changed = true; |
50f56119 DV |
9885 | } |
9886 | } | |
9a935856 | 9887 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9888 | |
2e431051 DV |
9889 | return 0; |
9890 | } | |
9891 | ||
9892 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9893 | { | |
9894 | struct drm_device *dev; | |
2e431051 DV |
9895 | struct drm_mode_set save_set; |
9896 | struct intel_set_config *config; | |
9897 | int ret; | |
2e431051 | 9898 | |
8d3e375e DV |
9899 | BUG_ON(!set); |
9900 | BUG_ON(!set->crtc); | |
9901 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9902 | |
7e53f3a4 DV |
9903 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9904 | BUG_ON(!set->mode && set->fb); | |
9905 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9906 | |
2e431051 DV |
9907 | if (set->fb) { |
9908 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9909 | set->crtc->base.id, set->fb->base.id, | |
9910 | (int)set->num_connectors, set->x, set->y); | |
9911 | } else { | |
9912 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9913 | } |
9914 | ||
9915 | dev = set->crtc->dev; | |
9916 | ||
9917 | ret = -ENOMEM; | |
9918 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9919 | if (!config) | |
9920 | goto out_config; | |
9921 | ||
9922 | ret = intel_set_config_save_state(dev, config); | |
9923 | if (ret) | |
9924 | goto out_config; | |
9925 | ||
9926 | save_set.crtc = set->crtc; | |
9927 | save_set.mode = &set->crtc->mode; | |
9928 | save_set.x = set->crtc->x; | |
9929 | save_set.y = set->crtc->y; | |
9930 | save_set.fb = set->crtc->fb; | |
9931 | ||
9932 | /* Compute whether we need a full modeset, only an fb base update or no | |
9933 | * change at all. In the future we might also check whether only the | |
9934 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9935 | * such cases. */ | |
9936 | intel_set_config_compute_mode_changes(set, config); | |
9937 | ||
9a935856 | 9938 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9939 | if (ret) |
9940 | goto fail; | |
9941 | ||
5e2b584e | 9942 | if (config->mode_changed) { |
c0c36b94 CW |
9943 | ret = intel_set_mode(set->crtc, set->mode, |
9944 | set->x, set->y, set->fb); | |
5e2b584e | 9945 | } else if (config->fb_changed) { |
4878cae2 VS |
9946 | intel_crtc_wait_for_pending_flips(set->crtc); |
9947 | ||
4f660f49 | 9948 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9949 | set->x, set->y, set->fb); |
50f56119 DV |
9950 | } |
9951 | ||
2d05eae1 | 9952 | if (ret) { |
bf67dfeb DV |
9953 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9954 | set->crtc->base.id, ret); | |
50f56119 | 9955 | fail: |
2d05eae1 | 9956 | intel_set_config_restore_state(dev, config); |
50f56119 | 9957 | |
2d05eae1 CW |
9958 | /* Try to restore the config */ |
9959 | if (config->mode_changed && | |
9960 | intel_set_mode(save_set.crtc, save_set.mode, | |
9961 | save_set.x, save_set.y, save_set.fb)) | |
9962 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
9963 | } | |
50f56119 | 9964 | |
d9e55608 DV |
9965 | out_config: |
9966 | intel_set_config_free(config); | |
50f56119 DV |
9967 | return ret; |
9968 | } | |
f6e5b160 CW |
9969 | |
9970 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
9971 | .cursor_set = intel_crtc_cursor_set, |
9972 | .cursor_move = intel_crtc_cursor_move, | |
9973 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 9974 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
9975 | .destroy = intel_crtc_destroy, |
9976 | .page_flip = intel_crtc_page_flip, | |
9977 | }; | |
9978 | ||
79f689aa PZ |
9979 | static void intel_cpu_pll_init(struct drm_device *dev) |
9980 | { | |
affa9354 | 9981 | if (HAS_DDI(dev)) |
79f689aa PZ |
9982 | intel_ddi_pll_init(dev); |
9983 | } | |
9984 | ||
5358901f DV |
9985 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9986 | struct intel_shared_dpll *pll, | |
9987 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 9988 | { |
5358901f | 9989 | uint32_t val; |
ee7b9f93 | 9990 | |
5358901f | 9991 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
9992 | hw_state->dpll = val; |
9993 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
9994 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
9995 | |
9996 | return val & DPLL_VCO_ENABLE; | |
9997 | } | |
9998 | ||
15bdd4cf DV |
9999 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10000 | struct intel_shared_dpll *pll) | |
10001 | { | |
10002 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10003 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10004 | } | |
10005 | ||
e7b903d2 DV |
10006 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10007 | struct intel_shared_dpll *pll) | |
10008 | { | |
e7b903d2 DV |
10009 | /* PCH refclock must be enabled first */ |
10010 | assert_pch_refclk_enabled(dev_priv); | |
10011 | ||
15bdd4cf DV |
10012 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10013 | ||
10014 | /* Wait for the clocks to stabilize. */ | |
10015 | POSTING_READ(PCH_DPLL(pll->id)); | |
10016 | udelay(150); | |
10017 | ||
10018 | /* The pixel multiplier can only be updated once the | |
10019 | * DPLL is enabled and the clocks are stable. | |
10020 | * | |
10021 | * So write it again. | |
10022 | */ | |
10023 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10024 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10025 | udelay(200); |
10026 | } | |
10027 | ||
10028 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10029 | struct intel_shared_dpll *pll) | |
10030 | { | |
10031 | struct drm_device *dev = dev_priv->dev; | |
10032 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10033 | |
10034 | /* Make sure no transcoder isn't still depending on us. */ | |
10035 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10036 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10037 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10038 | } |
10039 | ||
15bdd4cf DV |
10040 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10041 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10042 | udelay(200); |
10043 | } | |
10044 | ||
46edb027 DV |
10045 | static char *ibx_pch_dpll_names[] = { |
10046 | "PCH DPLL A", | |
10047 | "PCH DPLL B", | |
10048 | }; | |
10049 | ||
7c74ade1 | 10050 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10051 | { |
e7b903d2 | 10052 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10053 | int i; |
10054 | ||
7c74ade1 | 10055 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10056 | |
e72f9fbf | 10057 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10058 | dev_priv->shared_dplls[i].id = i; |
10059 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10060 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10061 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10062 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10063 | dev_priv->shared_dplls[i].get_hw_state = |
10064 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10065 | } |
10066 | } | |
10067 | ||
7c74ade1 DV |
10068 | static void intel_shared_dpll_init(struct drm_device *dev) |
10069 | { | |
e7b903d2 | 10070 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10071 | |
10072 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10073 | ibx_pch_dpll_init(dev); | |
10074 | else | |
10075 | dev_priv->num_shared_dpll = 0; | |
10076 | ||
10077 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
10078 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
10079 | dev_priv->num_shared_dpll); | |
10080 | } | |
10081 | ||
b358d0a6 | 10082 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10083 | { |
22fd0fab | 10084 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10085 | struct intel_crtc *intel_crtc; |
10086 | int i; | |
10087 | ||
955382f3 | 10088 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10089 | if (intel_crtc == NULL) |
10090 | return; | |
10091 | ||
10092 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10093 | ||
10094 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10095 | for (i = 0; i < 256; i++) { |
10096 | intel_crtc->lut_r[i] = i; | |
10097 | intel_crtc->lut_g[i] = i; | |
10098 | intel_crtc->lut_b[i] = i; | |
10099 | } | |
10100 | ||
80824003 JB |
10101 | /* Swap pipes & planes for FBC on pre-965 */ |
10102 | intel_crtc->pipe = pipe; | |
10103 | intel_crtc->plane = pipe; | |
e2e767ab | 10104 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 10105 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10106 | intel_crtc->plane = !pipe; |
80824003 JB |
10107 | } |
10108 | ||
22fd0fab JB |
10109 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10110 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10111 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10112 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10113 | ||
79e53945 | 10114 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10115 | } |
10116 | ||
752aa88a JB |
10117 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10118 | { | |
10119 | struct drm_encoder *encoder = connector->base.encoder; | |
10120 | ||
10121 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10122 | ||
10123 | if (!encoder) | |
10124 | return INVALID_PIPE; | |
10125 | ||
10126 | return to_intel_crtc(encoder->crtc)->pipe; | |
10127 | } | |
10128 | ||
08d7b3d1 | 10129 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10130 | struct drm_file *file) |
08d7b3d1 | 10131 | { |
08d7b3d1 | 10132 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10133 | struct drm_mode_object *drmmode_obj; |
10134 | struct intel_crtc *crtc; | |
08d7b3d1 | 10135 | |
1cff8f6b DV |
10136 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10137 | return -ENODEV; | |
08d7b3d1 | 10138 | |
c05422d5 DV |
10139 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10140 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10141 | |
c05422d5 | 10142 | if (!drmmode_obj) { |
08d7b3d1 | 10143 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10144 | return -ENOENT; |
08d7b3d1 CW |
10145 | } |
10146 | ||
c05422d5 DV |
10147 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10148 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10149 | |
c05422d5 | 10150 | return 0; |
08d7b3d1 CW |
10151 | } |
10152 | ||
66a9278e | 10153 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10154 | { |
66a9278e DV |
10155 | struct drm_device *dev = encoder->base.dev; |
10156 | struct intel_encoder *source_encoder; | |
79e53945 | 10157 | int index_mask = 0; |
79e53945 JB |
10158 | int entry = 0; |
10159 | ||
66a9278e DV |
10160 | list_for_each_entry(source_encoder, |
10161 | &dev->mode_config.encoder_list, base.head) { | |
10162 | ||
10163 | if (encoder == source_encoder) | |
79e53945 | 10164 | index_mask |= (1 << entry); |
66a9278e DV |
10165 | |
10166 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10167 | if (encoder->cloneable && source_encoder->cloneable) | |
10168 | index_mask |= (1 << entry); | |
10169 | ||
79e53945 JB |
10170 | entry++; |
10171 | } | |
4ef69c7a | 10172 | |
79e53945 JB |
10173 | return index_mask; |
10174 | } | |
10175 | ||
4d302442 CW |
10176 | static bool has_edp_a(struct drm_device *dev) |
10177 | { | |
10178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10179 | ||
10180 | if (!IS_MOBILE(dev)) | |
10181 | return false; | |
10182 | ||
10183 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10184 | return false; | |
10185 | ||
10186 | if (IS_GEN5(dev) && | |
10187 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
10188 | return false; | |
10189 | ||
10190 | return true; | |
10191 | } | |
10192 | ||
79e53945 JB |
10193 | static void intel_setup_outputs(struct drm_device *dev) |
10194 | { | |
725e30ad | 10195 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10196 | struct intel_encoder *encoder; |
cb0953d7 | 10197 | bool dpd_is_edp = false; |
79e53945 | 10198 | |
c9093354 | 10199 | intel_lvds_init(dev); |
79e53945 | 10200 | |
c40c0f5b | 10201 | if (!IS_ULT(dev)) |
79935fca | 10202 | intel_crt_init(dev); |
cb0953d7 | 10203 | |
affa9354 | 10204 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10205 | int found; |
10206 | ||
10207 | /* Haswell uses DDI functions to detect digital outputs */ | |
10208 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10209 | /* DDI A only supports eDP */ | |
10210 | if (found) | |
10211 | intel_ddi_init(dev, PORT_A); | |
10212 | ||
10213 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10214 | * register */ | |
10215 | found = I915_READ(SFUSE_STRAP); | |
10216 | ||
10217 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10218 | intel_ddi_init(dev, PORT_B); | |
10219 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10220 | intel_ddi_init(dev, PORT_C); | |
10221 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10222 | intel_ddi_init(dev, PORT_D); | |
10223 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10224 | int found; |
270b3042 DV |
10225 | dpd_is_edp = intel_dpd_is_edp(dev); |
10226 | ||
10227 | if (has_edp_a(dev)) | |
10228 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10229 | |
dc0fa718 | 10230 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10231 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10232 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10233 | if (!found) |
e2debe91 | 10234 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10235 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10236 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10237 | } |
10238 | ||
dc0fa718 | 10239 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10240 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10241 | |
dc0fa718 | 10242 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10243 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10244 | |
5eb08b69 | 10245 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10246 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10247 | |
270b3042 | 10248 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10249 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10250 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10251 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10252 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10253 | PORT_B); | |
10254 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10255 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10256 | } | |
10257 | ||
6f6005a5 JB |
10258 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10259 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10260 | PORT_C); | |
10261 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
10262 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
10263 | PORT_C); | |
10264 | } | |
19c03924 | 10265 | |
3cfca973 | 10266 | intel_dsi_init(dev); |
103a196f | 10267 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10268 | bool found = false; |
7d57382e | 10269 | |
e2debe91 | 10270 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10271 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10272 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10273 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10274 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10275 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10276 | } |
27185ae1 | 10277 | |
e7281eab | 10278 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10279 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10280 | } |
13520b05 KH |
10281 | |
10282 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10283 | |
e2debe91 | 10284 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10285 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10286 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10287 | } |
27185ae1 | 10288 | |
e2debe91 | 10289 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10290 | |
b01f2c3a JB |
10291 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10292 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10293 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10294 | } |
e7281eab | 10295 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10296 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10297 | } |
27185ae1 | 10298 | |
b01f2c3a | 10299 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10300 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10301 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10302 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10303 | intel_dvo_init(dev); |
10304 | ||
103a196f | 10305 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10306 | intel_tv_init(dev); |
10307 | ||
4ef69c7a CW |
10308 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10309 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10310 | encoder->base.possible_clones = | |
66a9278e | 10311 | intel_encoder_clones(encoder); |
79e53945 | 10312 | } |
47356eb6 | 10313 | |
dde86e2d | 10314 | intel_init_pch_refclk(dev); |
270b3042 DV |
10315 | |
10316 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10317 | } |
10318 | ||
ddfe1567 CW |
10319 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
10320 | { | |
10321 | drm_framebuffer_cleanup(&fb->base); | |
80075d49 | 10322 | WARN_ON(!fb->obj->framebuffer_references--); |
ddfe1567 CW |
10323 | drm_gem_object_unreference_unlocked(&fb->obj->base); |
10324 | } | |
10325 | ||
79e53945 JB |
10326 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
10327 | { | |
10328 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10329 | |
ddfe1567 | 10330 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
10331 | kfree(intel_fb); |
10332 | } | |
10333 | ||
10334 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10335 | struct drm_file *file, |
79e53945 JB |
10336 | unsigned int *handle) |
10337 | { | |
10338 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10339 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10340 | |
05394f39 | 10341 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10342 | } |
10343 | ||
10344 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10345 | .destroy = intel_user_framebuffer_destroy, | |
10346 | .create_handle = intel_user_framebuffer_create_handle, | |
10347 | }; | |
10348 | ||
38651674 DA |
10349 | int intel_framebuffer_init(struct drm_device *dev, |
10350 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10351 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10352 | struct drm_i915_gem_object *obj) |
79e53945 | 10353 | { |
53155c0a | 10354 | int aligned_height, tile_height; |
a35cdaa0 | 10355 | int pitch_limit; |
79e53945 JB |
10356 | int ret; |
10357 | ||
dd4916c5 DV |
10358 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10359 | ||
c16ed4be CW |
10360 | if (obj->tiling_mode == I915_TILING_Y) { |
10361 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10362 | return -EINVAL; |
c16ed4be | 10363 | } |
57cd6508 | 10364 | |
c16ed4be CW |
10365 | if (mode_cmd->pitches[0] & 63) { |
10366 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10367 | mode_cmd->pitches[0]); | |
57cd6508 | 10368 | return -EINVAL; |
c16ed4be | 10369 | } |
57cd6508 | 10370 | |
a35cdaa0 CW |
10371 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10372 | pitch_limit = 32*1024; | |
10373 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10374 | if (obj->tiling_mode) | |
10375 | pitch_limit = 16*1024; | |
10376 | else | |
10377 | pitch_limit = 32*1024; | |
10378 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10379 | if (obj->tiling_mode) | |
10380 | pitch_limit = 8*1024; | |
10381 | else | |
10382 | pitch_limit = 16*1024; | |
10383 | } else | |
10384 | /* XXX DSPC is limited to 4k tiled */ | |
10385 | pitch_limit = 8*1024; | |
10386 | ||
10387 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10388 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10389 | obj->tiling_mode ? "tiled" : "linear", | |
10390 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10391 | return -EINVAL; |
c16ed4be | 10392 | } |
5d7bd705 VS |
10393 | |
10394 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10395 | mode_cmd->pitches[0] != obj->stride) { |
10396 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10397 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10398 | return -EINVAL; |
c16ed4be | 10399 | } |
5d7bd705 | 10400 | |
57779d06 | 10401 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10402 | switch (mode_cmd->pixel_format) { |
57779d06 | 10403 | case DRM_FORMAT_C8: |
04b3924d VS |
10404 | case DRM_FORMAT_RGB565: |
10405 | case DRM_FORMAT_XRGB8888: | |
10406 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10407 | break; |
10408 | case DRM_FORMAT_XRGB1555: | |
10409 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10410 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10411 | DRM_DEBUG("unsupported pixel format: %s\n", |
10412 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10413 | return -EINVAL; |
c16ed4be | 10414 | } |
57779d06 VS |
10415 | break; |
10416 | case DRM_FORMAT_XBGR8888: | |
10417 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10418 | case DRM_FORMAT_XRGB2101010: |
10419 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10420 | case DRM_FORMAT_XBGR2101010: |
10421 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10422 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10423 | DRM_DEBUG("unsupported pixel format: %s\n", |
10424 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10425 | return -EINVAL; |
c16ed4be | 10426 | } |
b5626747 | 10427 | break; |
04b3924d VS |
10428 | case DRM_FORMAT_YUYV: |
10429 | case DRM_FORMAT_UYVY: | |
10430 | case DRM_FORMAT_YVYU: | |
10431 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10432 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10433 | DRM_DEBUG("unsupported pixel format: %s\n", |
10434 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10435 | return -EINVAL; |
c16ed4be | 10436 | } |
57cd6508 CW |
10437 | break; |
10438 | default: | |
4ee62c76 VS |
10439 | DRM_DEBUG("unsupported pixel format: %s\n", |
10440 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10441 | return -EINVAL; |
10442 | } | |
10443 | ||
90f9a336 VS |
10444 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10445 | if (mode_cmd->offsets[0] != 0) | |
10446 | return -EINVAL; | |
10447 | ||
53155c0a DV |
10448 | tile_height = IS_GEN2(dev) ? 16 : 8; |
10449 | aligned_height = ALIGN(mode_cmd->height, | |
10450 | obj->tiling_mode ? tile_height : 1); | |
10451 | /* FIXME drm helper for size checks (especially planar formats)? */ | |
10452 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10453 | return -EINVAL; | |
10454 | ||
c7d73f6a DV |
10455 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10456 | intel_fb->obj = obj; | |
80075d49 | 10457 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10458 | |
79e53945 JB |
10459 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10460 | if (ret) { | |
10461 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10462 | return ret; | |
10463 | } | |
10464 | ||
79e53945 JB |
10465 | return 0; |
10466 | } | |
10467 | ||
79e53945 JB |
10468 | static struct drm_framebuffer * |
10469 | intel_user_framebuffer_create(struct drm_device *dev, | |
10470 | struct drm_file *filp, | |
308e5bcb | 10471 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10472 | { |
05394f39 | 10473 | struct drm_i915_gem_object *obj; |
79e53945 | 10474 | |
308e5bcb JB |
10475 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10476 | mode_cmd->handles[0])); | |
c8725226 | 10477 | if (&obj->base == NULL) |
cce13ff7 | 10478 | return ERR_PTR(-ENOENT); |
79e53945 | 10479 | |
d2dff872 | 10480 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10481 | } |
10482 | ||
4520f53a | 10483 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10484 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10485 | { |
10486 | } | |
10487 | #endif | |
10488 | ||
79e53945 | 10489 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10490 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10491 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10492 | }; |
10493 | ||
e70236a8 JB |
10494 | /* Set up chip specific display functions */ |
10495 | static void intel_init_display(struct drm_device *dev) | |
10496 | { | |
10497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10498 | ||
ee9300bb DV |
10499 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10500 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10501 | else if (IS_VALLEYVIEW(dev)) | |
10502 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10503 | else if (IS_PINEVIEW(dev)) | |
10504 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10505 | else | |
10506 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10507 | ||
affa9354 | 10508 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10509 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10510 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10511 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10512 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10513 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10514 | dev_priv->display.update_plane = ironlake_update_plane; |
10515 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10516 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10517 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10518 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10519 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10520 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10521 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10522 | } else if (IS_VALLEYVIEW(dev)) { |
10523 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10524 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10525 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10526 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10527 | dev_priv->display.off = i9xx_crtc_off; | |
10528 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10529 | } else { |
0e8ffe1b | 10530 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10531 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10532 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10533 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10534 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10535 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10536 | } |
e70236a8 | 10537 | |
e70236a8 | 10538 | /* Returns the core display clock speed */ |
25eb05fc JB |
10539 | if (IS_VALLEYVIEW(dev)) |
10540 | dev_priv->display.get_display_clock_speed = | |
10541 | valleyview_get_display_clock_speed; | |
10542 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10543 | dev_priv->display.get_display_clock_speed = |
10544 | i945_get_display_clock_speed; | |
10545 | else if (IS_I915G(dev)) | |
10546 | dev_priv->display.get_display_clock_speed = | |
10547 | i915_get_display_clock_speed; | |
257a7ffc | 10548 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10549 | dev_priv->display.get_display_clock_speed = |
10550 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10551 | else if (IS_PINEVIEW(dev)) |
10552 | dev_priv->display.get_display_clock_speed = | |
10553 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10554 | else if (IS_I915GM(dev)) |
10555 | dev_priv->display.get_display_clock_speed = | |
10556 | i915gm_get_display_clock_speed; | |
10557 | else if (IS_I865G(dev)) | |
10558 | dev_priv->display.get_display_clock_speed = | |
10559 | i865_get_display_clock_speed; | |
f0f8a9ce | 10560 | else if (IS_I85X(dev)) |
e70236a8 JB |
10561 | dev_priv->display.get_display_clock_speed = |
10562 | i855_get_display_clock_speed; | |
10563 | else /* 852, 830 */ | |
10564 | dev_priv->display.get_display_clock_speed = | |
10565 | i830_get_display_clock_speed; | |
10566 | ||
7f8a8569 | 10567 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10568 | if (IS_GEN5(dev)) { |
674cf967 | 10569 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10570 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10571 | } else if (IS_GEN6(dev)) { |
674cf967 | 10572 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10573 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10574 | } else if (IS_IVYBRIDGE(dev)) { |
10575 | /* FIXME: detect B0+ stepping and use auto training */ | |
10576 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10577 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10578 | dev_priv->display.modeset_global_resources = |
10579 | ivb_modeset_global_resources; | |
4e0bbc31 | 10580 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10581 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10582 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10583 | dev_priv->display.modeset_global_resources = |
10584 | haswell_modeset_global_resources; | |
a0e63c22 | 10585 | } |
6067aaea | 10586 | } else if (IS_G4X(dev)) { |
e0dac65e | 10587 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10588 | } else if (IS_VALLEYVIEW(dev)) { |
10589 | dev_priv->display.modeset_global_resources = | |
10590 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10591 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10592 | } |
8c9f3aaf JB |
10593 | |
10594 | /* Default just returns -ENODEV to indicate unsupported */ | |
10595 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10596 | ||
10597 | switch (INTEL_INFO(dev)->gen) { | |
10598 | case 2: | |
10599 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10600 | break; | |
10601 | ||
10602 | case 3: | |
10603 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10604 | break; | |
10605 | ||
10606 | case 4: | |
10607 | case 5: | |
10608 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10609 | break; | |
10610 | ||
10611 | case 6: | |
10612 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10613 | break; | |
7c9017e5 | 10614 | case 7: |
4e0bbc31 | 10615 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10616 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10617 | break; | |
8c9f3aaf | 10618 | } |
7bd688cd JN |
10619 | |
10620 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10621 | } |
10622 | ||
b690e96c JB |
10623 | /* |
10624 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10625 | * resume, or other times. This quirk makes sure that's the case for | |
10626 | * affected systems. | |
10627 | */ | |
0206e353 | 10628 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10629 | { |
10630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10631 | ||
10632 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10633 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10634 | } |
10635 | ||
435793df KP |
10636 | /* |
10637 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10638 | */ | |
10639 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10640 | { | |
10641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10642 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10643 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10644 | } |
10645 | ||
4dca20ef | 10646 | /* |
5a15ab5b CE |
10647 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10648 | * brightness value | |
4dca20ef CE |
10649 | */ |
10650 | static void quirk_invert_brightness(struct drm_device *dev) | |
10651 | { | |
10652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10653 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10654 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10655 | } |
10656 | ||
b690e96c JB |
10657 | struct intel_quirk { |
10658 | int device; | |
10659 | int subsystem_vendor; | |
10660 | int subsystem_device; | |
10661 | void (*hook)(struct drm_device *dev); | |
10662 | }; | |
10663 | ||
5f85f176 EE |
10664 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10665 | struct intel_dmi_quirk { | |
10666 | void (*hook)(struct drm_device *dev); | |
10667 | const struct dmi_system_id (*dmi_id_list)[]; | |
10668 | }; | |
10669 | ||
10670 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10671 | { | |
10672 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10673 | return 1; | |
10674 | } | |
10675 | ||
10676 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10677 | { | |
10678 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10679 | { | |
10680 | .callback = intel_dmi_reverse_brightness, | |
10681 | .ident = "NCR Corporation", | |
10682 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10683 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10684 | }, | |
10685 | }, | |
10686 | { } /* terminating entry */ | |
10687 | }, | |
10688 | .hook = quirk_invert_brightness, | |
10689 | }, | |
10690 | }; | |
10691 | ||
c43b5634 | 10692 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10693 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10694 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10695 | |
b690e96c JB |
10696 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10697 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10698 | ||
b690e96c JB |
10699 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10700 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10701 | ||
a4945f95 | 10702 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10703 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10704 | |
10705 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10706 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10707 | |
10708 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10709 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10710 | |
ee1452d7 JN |
10711 | /* |
10712 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | |
10713 | * seem to use inverted backlight PWM. | |
10714 | */ | |
10715 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | |
b690e96c JB |
10716 | }; |
10717 | ||
10718 | static void intel_init_quirks(struct drm_device *dev) | |
10719 | { | |
10720 | struct pci_dev *d = dev->pdev; | |
10721 | int i; | |
10722 | ||
10723 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10724 | struct intel_quirk *q = &intel_quirks[i]; | |
10725 | ||
10726 | if (d->device == q->device && | |
10727 | (d->subsystem_vendor == q->subsystem_vendor || | |
10728 | q->subsystem_vendor == PCI_ANY_ID) && | |
10729 | (d->subsystem_device == q->subsystem_device || | |
10730 | q->subsystem_device == PCI_ANY_ID)) | |
10731 | q->hook(dev); | |
10732 | } | |
5f85f176 EE |
10733 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10734 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10735 | intel_dmi_quirks[i].hook(dev); | |
10736 | } | |
b690e96c JB |
10737 | } |
10738 | ||
9cce37f4 JB |
10739 | /* Disable the VGA plane that we never use */ |
10740 | static void i915_disable_vga(struct drm_device *dev) | |
10741 | { | |
10742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10743 | u8 sr1; | |
766aa1c4 | 10744 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10745 | |
10746 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10747 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10748 | sr1 = inb(VGA_SR_DATA); |
10749 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10750 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10751 | udelay(300); | |
10752 | ||
10753 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10754 | POSTING_READ(vga_reg); | |
10755 | } | |
10756 | ||
f817586c DV |
10757 | void intel_modeset_init_hw(struct drm_device *dev) |
10758 | { | |
f6071166 JB |
10759 | struct drm_i915_private *dev_priv = dev->dev_private; |
10760 | ||
a8f78b58 ED |
10761 | intel_prepare_ddi(dev); |
10762 | ||
f817586c DV |
10763 | intel_init_clock_gating(dev); |
10764 | ||
f6071166 JB |
10765 | /* Enable the CRI clock source so we can get at the display */ |
10766 | if (IS_VALLEYVIEW(dev)) | |
10767 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
10768 | DPLL_INTEGRATED_CRI_CLK_VLV); | |
10769 | ||
40e9cf64 JB |
10770 | intel_init_dpio(dev); |
10771 | ||
79f5b2c7 | 10772 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10773 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10774 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10775 | } |
10776 | ||
7d708ee4 ID |
10777 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10778 | { | |
10779 | intel_suspend_hw(dev); | |
10780 | } | |
10781 | ||
79e53945 JB |
10782 | void intel_modeset_init(struct drm_device *dev) |
10783 | { | |
652c393a | 10784 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10785 | int i, j, ret; |
79e53945 JB |
10786 | |
10787 | drm_mode_config_init(dev); | |
10788 | ||
10789 | dev->mode_config.min_width = 0; | |
10790 | dev->mode_config.min_height = 0; | |
10791 | ||
019d96cb DA |
10792 | dev->mode_config.preferred_depth = 24; |
10793 | dev->mode_config.prefer_shadow = 1; | |
10794 | ||
e6ecefaa | 10795 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10796 | |
b690e96c JB |
10797 | intel_init_quirks(dev); |
10798 | ||
1fa61106 ED |
10799 | intel_init_pm(dev); |
10800 | ||
e3c74757 BW |
10801 | if (INTEL_INFO(dev)->num_pipes == 0) |
10802 | return; | |
10803 | ||
e70236a8 JB |
10804 | intel_init_display(dev); |
10805 | ||
a6c45cf0 CW |
10806 | if (IS_GEN2(dev)) { |
10807 | dev->mode_config.max_width = 2048; | |
10808 | dev->mode_config.max_height = 2048; | |
10809 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10810 | dev->mode_config.max_width = 4096; |
10811 | dev->mode_config.max_height = 4096; | |
79e53945 | 10812 | } else { |
a6c45cf0 CW |
10813 | dev->mode_config.max_width = 8192; |
10814 | dev->mode_config.max_height = 8192; | |
79e53945 | 10815 | } |
5d4545ae | 10816 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10817 | |
28c97730 | 10818 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10819 | INTEL_INFO(dev)->num_pipes, |
10820 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10821 | |
08e2a7de | 10822 | for_each_pipe(i) { |
79e53945 | 10823 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10824 | for (j = 0; j < dev_priv->num_plane; j++) { |
10825 | ret = intel_plane_init(dev, i, j); | |
10826 | if (ret) | |
06da8da2 VS |
10827 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10828 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10829 | } |
79e53945 JB |
10830 | } |
10831 | ||
79f689aa | 10832 | intel_cpu_pll_init(dev); |
e72f9fbf | 10833 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10834 | |
9cce37f4 JB |
10835 | /* Just disable it once at startup */ |
10836 | i915_disable_vga(dev); | |
79e53945 | 10837 | intel_setup_outputs(dev); |
11be49eb CW |
10838 | |
10839 | /* Just in case the BIOS is doing something questionable. */ | |
10840 | intel_disable_fbc(dev); | |
2c7111db CW |
10841 | } |
10842 | ||
24929352 DV |
10843 | static void |
10844 | intel_connector_break_all_links(struct intel_connector *connector) | |
10845 | { | |
10846 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10847 | connector->base.encoder = NULL; | |
10848 | connector->encoder->connectors_active = false; | |
10849 | connector->encoder->base.crtc = NULL; | |
10850 | } | |
10851 | ||
7fad798e DV |
10852 | static void intel_enable_pipe_a(struct drm_device *dev) |
10853 | { | |
10854 | struct intel_connector *connector; | |
10855 | struct drm_connector *crt = NULL; | |
10856 | struct intel_load_detect_pipe load_detect_temp; | |
10857 | ||
10858 | /* We can't just switch on the pipe A, we need to set things up with a | |
10859 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10860 | * by enabling the load detect pipe once. */ | |
10861 | list_for_each_entry(connector, | |
10862 | &dev->mode_config.connector_list, | |
10863 | base.head) { | |
10864 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10865 | crt = &connector->base; | |
10866 | break; | |
10867 | } | |
10868 | } | |
10869 | ||
10870 | if (!crt) | |
10871 | return; | |
10872 | ||
10873 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10874 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10875 | ||
652c393a | 10876 | |
7fad798e DV |
10877 | } |
10878 | ||
fa555837 DV |
10879 | static bool |
10880 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10881 | { | |
7eb552ae BW |
10882 | struct drm_device *dev = crtc->base.dev; |
10883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10884 | u32 reg, val; |
10885 | ||
7eb552ae | 10886 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10887 | return true; |
10888 | ||
10889 | reg = DSPCNTR(!crtc->plane); | |
10890 | val = I915_READ(reg); | |
10891 | ||
10892 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10893 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10894 | return false; | |
10895 | ||
10896 | return true; | |
10897 | } | |
10898 | ||
24929352 DV |
10899 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10900 | { | |
10901 | struct drm_device *dev = crtc->base.dev; | |
10902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10903 | u32 reg; |
24929352 | 10904 | |
24929352 | 10905 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10906 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10907 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10908 | ||
10909 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10910 | * disable the crtc (and hence change the state) if it is wrong. Note |
10911 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10912 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10913 | struct intel_connector *connector; |
10914 | bool plane; | |
10915 | ||
24929352 DV |
10916 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10917 | crtc->base.base.id); | |
10918 | ||
10919 | /* Pipe has the wrong plane attached and the plane is active. | |
10920 | * Temporarily change the plane mapping and disable everything | |
10921 | * ... */ | |
10922 | plane = crtc->plane; | |
10923 | crtc->plane = !plane; | |
10924 | dev_priv->display.crtc_disable(&crtc->base); | |
10925 | crtc->plane = plane; | |
10926 | ||
10927 | /* ... and break all links. */ | |
10928 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10929 | base.head) { | |
10930 | if (connector->encoder->base.crtc != &crtc->base) | |
10931 | continue; | |
10932 | ||
10933 | intel_connector_break_all_links(connector); | |
10934 | } | |
10935 | ||
10936 | WARN_ON(crtc->active); | |
10937 | crtc->base.enabled = false; | |
10938 | } | |
24929352 | 10939 | |
7fad798e DV |
10940 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10941 | crtc->pipe == PIPE_A && !crtc->active) { | |
10942 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10943 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10944 | * call below we restore the pipe to the right state, but leave | |
10945 | * the required bits on. */ | |
10946 | intel_enable_pipe_a(dev); | |
10947 | } | |
10948 | ||
24929352 DV |
10949 | /* Adjust the state of the output pipe according to whether we |
10950 | * have active connectors/encoders. */ | |
10951 | intel_crtc_update_dpms(&crtc->base); | |
10952 | ||
10953 | if (crtc->active != crtc->base.enabled) { | |
10954 | struct intel_encoder *encoder; | |
10955 | ||
10956 | /* This can happen either due to bugs in the get_hw_state | |
10957 | * functions or because the pipe is force-enabled due to the | |
10958 | * pipe A quirk. */ | |
10959 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
10960 | crtc->base.base.id, | |
10961 | crtc->base.enabled ? "enabled" : "disabled", | |
10962 | crtc->active ? "enabled" : "disabled"); | |
10963 | ||
10964 | crtc->base.enabled = crtc->active; | |
10965 | ||
10966 | /* Because we only establish the connector -> encoder -> | |
10967 | * crtc links if something is active, this means the | |
10968 | * crtc is now deactivated. Break the links. connector | |
10969 | * -> encoder links are only establish when things are | |
10970 | * actually up, hence no need to break them. */ | |
10971 | WARN_ON(crtc->active); | |
10972 | ||
10973 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
10974 | WARN_ON(encoder->connectors_active); | |
10975 | encoder->base.crtc = NULL; | |
10976 | } | |
10977 | } | |
10978 | } | |
10979 | ||
10980 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
10981 | { | |
10982 | struct intel_connector *connector; | |
10983 | struct drm_device *dev = encoder->base.dev; | |
10984 | ||
10985 | /* We need to check both for a crtc link (meaning that the | |
10986 | * encoder is active and trying to read from a pipe) and the | |
10987 | * pipe itself being active. */ | |
10988 | bool has_active_crtc = encoder->base.crtc && | |
10989 | to_intel_crtc(encoder->base.crtc)->active; | |
10990 | ||
10991 | if (encoder->connectors_active && !has_active_crtc) { | |
10992 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
10993 | encoder->base.base.id, | |
10994 | drm_get_encoder_name(&encoder->base)); | |
10995 | ||
10996 | /* Connector is active, but has no active pipe. This is | |
10997 | * fallout from our resume register restoring. Disable | |
10998 | * the encoder manually again. */ | |
10999 | if (encoder->base.crtc) { | |
11000 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11001 | encoder->base.base.id, | |
11002 | drm_get_encoder_name(&encoder->base)); | |
11003 | encoder->disable(encoder); | |
11004 | } | |
11005 | ||
11006 | /* Inconsistent output/port/pipe state happens presumably due to | |
11007 | * a bug in one of the get_hw_state functions. Or someplace else | |
11008 | * in our code, like the register restore mess on resume. Clamp | |
11009 | * things to off as a safer default. */ | |
11010 | list_for_each_entry(connector, | |
11011 | &dev->mode_config.connector_list, | |
11012 | base.head) { | |
11013 | if (connector->encoder != encoder) | |
11014 | continue; | |
11015 | ||
11016 | intel_connector_break_all_links(connector); | |
11017 | } | |
11018 | } | |
11019 | /* Enabled encoders without active connectors will be fixed in | |
11020 | * the crtc fixup. */ | |
11021 | } | |
11022 | ||
44cec740 | 11023 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11024 | { |
11025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11026 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11027 | |
8dc8a27c PZ |
11028 | /* This function can be called both from intel_modeset_setup_hw_state or |
11029 | * at a very early point in our resume sequence, where the power well | |
11030 | * structures are not yet restored. Since this function is at a very | |
11031 | * paranoid "someone might have enabled VGA while we were not looking" | |
11032 | * level, just check if the power well is enabled instead of trying to | |
11033 | * follow the "don't touch the power well if we don't need it" policy | |
11034 | * the rest of the driver uses. */ | |
11035 | if (HAS_POWER_WELL(dev) && | |
6aedd1f5 | 11036 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11037 | return; |
11038 | ||
e1553faa | 11039 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11040 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11041 | i915_disable_vga(dev); |
0fde901f KM |
11042 | } |
11043 | } | |
11044 | ||
30e984df | 11045 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11046 | { |
11047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11048 | enum pipe pipe; | |
24929352 DV |
11049 | struct intel_crtc *crtc; |
11050 | struct intel_encoder *encoder; | |
11051 | struct intel_connector *connector; | |
5358901f | 11052 | int i; |
24929352 | 11053 | |
0e8ffe1b DV |
11054 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11055 | base.head) { | |
88adfff1 | 11056 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11057 | |
0e8ffe1b DV |
11058 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11059 | &crtc->config); | |
24929352 DV |
11060 | |
11061 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11062 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11063 | |
11064 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11065 | crtc->base.base.id, | |
11066 | crtc->active ? "enabled" : "disabled"); | |
11067 | } | |
11068 | ||
5358901f | 11069 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11070 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11071 | intel_ddi_setup_hw_pll_state(dev); |
11072 | ||
5358901f DV |
11073 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11074 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11075 | ||
11076 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11077 | pll->active = 0; | |
11078 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11079 | base.head) { | |
11080 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11081 | pll->active++; | |
11082 | } | |
11083 | pll->refcount = pll->active; | |
11084 | ||
35c95375 DV |
11085 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11086 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11087 | } |
11088 | ||
24929352 DV |
11089 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11090 | base.head) { | |
11091 | pipe = 0; | |
11092 | ||
11093 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11094 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11095 | encoder->base.crtc = &crtc->base; | |
510d5f2f | 11096 | if (encoder->get_config) |
045ac3b5 | 11097 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11098 | } else { |
11099 | encoder->base.crtc = NULL; | |
11100 | } | |
11101 | ||
11102 | encoder->connectors_active = false; | |
6f2bcceb | 11103 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11104 | encoder->base.base.id, |
11105 | drm_get_encoder_name(&encoder->base), | |
11106 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11107 | pipe_name(pipe)); |
24929352 DV |
11108 | } |
11109 | ||
11110 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11111 | base.head) { | |
11112 | if (connector->get_hw_state(connector)) { | |
11113 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11114 | connector->encoder->connectors_active = true; | |
11115 | connector->base.encoder = &connector->encoder->base; | |
11116 | } else { | |
11117 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11118 | connector->base.encoder = NULL; | |
11119 | } | |
11120 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11121 | connector->base.base.id, | |
11122 | drm_get_connector_name(&connector->base), | |
11123 | connector->base.encoder ? "enabled" : "disabled"); | |
11124 | } | |
30e984df DV |
11125 | } |
11126 | ||
11127 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11128 | * and i915 state tracking structures. */ | |
11129 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11130 | bool force_restore) | |
11131 | { | |
11132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11133 | enum pipe pipe; | |
30e984df DV |
11134 | struct intel_crtc *crtc; |
11135 | struct intel_encoder *encoder; | |
35c95375 | 11136 | int i; |
30e984df DV |
11137 | |
11138 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11139 | |
babea61d JB |
11140 | /* |
11141 | * Now that we have the config, copy it to each CRTC struct | |
11142 | * Note that this could go away if we move to using crtc_config | |
11143 | * checking everywhere. | |
11144 | */ | |
11145 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11146 | base.head) { | |
11147 | if (crtc->active && i915_fastboot) { | |
11148 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
11149 | ||
11150 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11151 | crtc->base.base.id); | |
11152 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11153 | } | |
11154 | } | |
11155 | ||
24929352 DV |
11156 | /* HW state is read out, now we need to sanitize this mess. */ |
11157 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11158 | base.head) { | |
11159 | intel_sanitize_encoder(encoder); | |
11160 | } | |
11161 | ||
11162 | for_each_pipe(pipe) { | |
11163 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11164 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11165 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11166 | } |
9a935856 | 11167 | |
35c95375 DV |
11168 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11169 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11170 | ||
11171 | if (!pll->on || pll->active) | |
11172 | continue; | |
11173 | ||
11174 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11175 | ||
11176 | pll->disable(dev_priv, pll); | |
11177 | pll->on = false; | |
11178 | } | |
11179 | ||
243e6a44 VS |
11180 | if (IS_HASWELL(dev)) |
11181 | ilk_wm_get_hw_state(dev); | |
11182 | ||
45e2b5f6 | 11183 | if (force_restore) { |
7d0bc1ea VS |
11184 | i915_redisable_vga(dev); |
11185 | ||
f30da187 DV |
11186 | /* |
11187 | * We need to use raw interfaces for restoring state to avoid | |
11188 | * checking (bogus) intermediate states. | |
11189 | */ | |
45e2b5f6 | 11190 | for_each_pipe(pipe) { |
b5644d05 JB |
11191 | struct drm_crtc *crtc = |
11192 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11193 | |
11194 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11195 | crtc->fb); | |
45e2b5f6 DV |
11196 | } |
11197 | } else { | |
11198 | intel_modeset_update_staged_output_state(dev); | |
11199 | } | |
8af6cf88 DV |
11200 | |
11201 | intel_modeset_check_state(dev); | |
2e938892 DV |
11202 | |
11203 | drm_mode_config_reset(dev); | |
2c7111db CW |
11204 | } |
11205 | ||
11206 | void intel_modeset_gem_init(struct drm_device *dev) | |
11207 | { | |
1833b134 | 11208 | intel_modeset_init_hw(dev); |
02e792fb DV |
11209 | |
11210 | intel_setup_overlay(dev); | |
24929352 | 11211 | |
45e2b5f6 | 11212 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
11213 | } |
11214 | ||
11215 | void intel_modeset_cleanup(struct drm_device *dev) | |
11216 | { | |
652c393a JB |
11217 | struct drm_i915_private *dev_priv = dev->dev_private; |
11218 | struct drm_crtc *crtc; | |
d9255d57 | 11219 | struct drm_connector *connector; |
652c393a | 11220 | |
fd0c0642 DV |
11221 | /* |
11222 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11223 | * Too much stuff here (turning of rps, connectors, ...) would | |
11224 | * experience fancy races otherwise. | |
11225 | */ | |
11226 | drm_irq_uninstall(dev); | |
11227 | cancel_work_sync(&dev_priv->hotplug_work); | |
11228 | /* | |
11229 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11230 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11231 | */ | |
f87ea761 | 11232 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11233 | |
652c393a JB |
11234 | mutex_lock(&dev->struct_mutex); |
11235 | ||
723bfd70 JB |
11236 | intel_unregister_dsm_handler(); |
11237 | ||
652c393a JB |
11238 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11239 | /* Skip inactive CRTCs */ | |
11240 | if (!crtc->fb) | |
11241 | continue; | |
11242 | ||
3dec0095 | 11243 | intel_increase_pllclock(crtc); |
652c393a JB |
11244 | } |
11245 | ||
973d04f9 | 11246 | intel_disable_fbc(dev); |
e70236a8 | 11247 | |
8090c6b9 | 11248 | intel_disable_gt_powersave(dev); |
0cdab21f | 11249 | |
930ebb46 DV |
11250 | ironlake_teardown_rc6(dev); |
11251 | ||
69341a5e KH |
11252 | mutex_unlock(&dev->struct_mutex); |
11253 | ||
1630fe75 CW |
11254 | /* flush any delayed tasks or pending work */ |
11255 | flush_scheduled_work(); | |
11256 | ||
db31af1d JN |
11257 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11258 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11259 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11260 | drm_sysfs_connector_remove(connector); |
db31af1d | 11261 | } |
d9255d57 | 11262 | |
79e53945 | 11263 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11264 | |
11265 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11266 | } |
11267 | ||
f1c79df3 ZW |
11268 | /* |
11269 | * Return which encoder is currently attached for connector. | |
11270 | */ | |
df0e9248 | 11271 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11272 | { |
df0e9248 CW |
11273 | return &intel_attached_encoder(connector)->base; |
11274 | } | |
f1c79df3 | 11275 | |
df0e9248 CW |
11276 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11277 | struct intel_encoder *encoder) | |
11278 | { | |
11279 | connector->encoder = encoder; | |
11280 | drm_mode_connector_attach_encoder(&connector->base, | |
11281 | &encoder->base); | |
79e53945 | 11282 | } |
28d52043 DA |
11283 | |
11284 | /* | |
11285 | * set vga decode state - true == enable VGA decode | |
11286 | */ | |
11287 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11288 | { | |
11289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11290 | u16 gmch_ctrl; | |
11291 | ||
11292 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
11293 | if (state) | |
11294 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11295 | else | |
11296 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
11297 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
11298 | return 0; | |
11299 | } | |
c4a1d9e4 | 11300 | |
c4a1d9e4 | 11301 | struct intel_display_error_state { |
ff57f1b0 PZ |
11302 | |
11303 | u32 power_well_driver; | |
11304 | ||
63b66e5b CW |
11305 | int num_transcoders; |
11306 | ||
c4a1d9e4 CW |
11307 | struct intel_cursor_error_state { |
11308 | u32 control; | |
11309 | u32 position; | |
11310 | u32 base; | |
11311 | u32 size; | |
52331309 | 11312 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11313 | |
11314 | struct intel_pipe_error_state { | |
c4a1d9e4 | 11315 | u32 source; |
52331309 | 11316 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11317 | |
11318 | struct intel_plane_error_state { | |
11319 | u32 control; | |
11320 | u32 stride; | |
11321 | u32 size; | |
11322 | u32 pos; | |
11323 | u32 addr; | |
11324 | u32 surface; | |
11325 | u32 tile_offset; | |
52331309 | 11326 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11327 | |
11328 | struct intel_transcoder_error_state { | |
11329 | enum transcoder cpu_transcoder; | |
11330 | ||
11331 | u32 conf; | |
11332 | ||
11333 | u32 htotal; | |
11334 | u32 hblank; | |
11335 | u32 hsync; | |
11336 | u32 vtotal; | |
11337 | u32 vblank; | |
11338 | u32 vsync; | |
11339 | } transcoder[4]; | |
c4a1d9e4 CW |
11340 | }; |
11341 | ||
11342 | struct intel_display_error_state * | |
11343 | intel_display_capture_error_state(struct drm_device *dev) | |
11344 | { | |
0206e353 | 11345 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11346 | struct intel_display_error_state *error; |
63b66e5b CW |
11347 | int transcoders[] = { |
11348 | TRANSCODER_A, | |
11349 | TRANSCODER_B, | |
11350 | TRANSCODER_C, | |
11351 | TRANSCODER_EDP, | |
11352 | }; | |
c4a1d9e4 CW |
11353 | int i; |
11354 | ||
63b66e5b CW |
11355 | if (INTEL_INFO(dev)->num_pipes == 0) |
11356 | return NULL; | |
11357 | ||
9d1cb914 | 11358 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11359 | if (error == NULL) |
11360 | return NULL; | |
11361 | ||
ff57f1b0 PZ |
11362 | if (HAS_POWER_WELL(dev)) |
11363 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
11364 | ||
52331309 | 11365 | for_each_pipe(i) { |
9d1cb914 PZ |
11366 | if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i))) |
11367 | continue; | |
11368 | ||
a18c4c3d PZ |
11369 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11370 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11371 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11372 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11373 | } else { | |
11374 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11375 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11376 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11377 | } | |
c4a1d9e4 CW |
11378 | |
11379 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11380 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11381 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11382 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11383 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11384 | } | |
ca291363 PZ |
11385 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11386 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11387 | if (INTEL_INFO(dev)->gen >= 4) { |
11388 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11389 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11390 | } | |
11391 | ||
c4a1d9e4 | 11392 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11393 | } |
11394 | ||
11395 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11396 | if (HAS_DDI(dev_priv->dev)) | |
11397 | error->num_transcoders++; /* Account for eDP. */ | |
11398 | ||
11399 | for (i = 0; i < error->num_transcoders; i++) { | |
11400 | enum transcoder cpu_transcoder = transcoders[i]; | |
11401 | ||
9d1cb914 PZ |
11402 | if (!intel_display_power_enabled(dev, |
11403 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) | |
11404 | continue; | |
11405 | ||
63b66e5b CW |
11406 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11407 | ||
11408 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11409 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11410 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11411 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11412 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11413 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11414 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11415 | } |
11416 | ||
11417 | return error; | |
11418 | } | |
11419 | ||
edc3d884 MK |
11420 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11421 | ||
c4a1d9e4 | 11422 | void |
edc3d884 | 11423 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11424 | struct drm_device *dev, |
11425 | struct intel_display_error_state *error) | |
11426 | { | |
11427 | int i; | |
11428 | ||
63b66e5b CW |
11429 | if (!error) |
11430 | return; | |
11431 | ||
edc3d884 | 11432 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
ff57f1b0 | 11433 | if (HAS_POWER_WELL(dev)) |
edc3d884 | 11434 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11435 | error->power_well_driver); |
52331309 | 11436 | for_each_pipe(i) { |
edc3d884 | 11437 | err_printf(m, "Pipe [%d]:\n", i); |
edc3d884 | 11438 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11439 | |
11440 | err_printf(m, "Plane [%d]:\n", i); | |
11441 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11442 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11443 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11444 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11445 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11446 | } |
4b71a570 | 11447 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11448 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11449 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11450 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11451 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11452 | } |
11453 | ||
edc3d884 MK |
11454 | err_printf(m, "Cursor [%d]:\n", i); |
11455 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11456 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11457 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11458 | } |
63b66e5b CW |
11459 | |
11460 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11461 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b CW |
11462 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
11463 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
11464 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11465 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11466 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11467 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11468 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11469 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11470 | } | |
c4a1d9e4 | 11471 | } |