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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
7662c8bd | 28 | #include <linux/kernel.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "intel_drv.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
a4fc5ed6 | 33 | #include "intel_dp.h" |
79e53945 JB |
34 | |
35 | #include "drm_crtc_helper.h" | |
36 | ||
37 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); | |
7662c8bd | 38 | static void intel_update_watermarks(struct drm_device *dev); |
79e53945 JB |
39 | |
40 | typedef struct { | |
41 | /* given values */ | |
42 | int n; | |
43 | int m1, m2; | |
44 | int p1, p2; | |
45 | /* derived values */ | |
46 | int dot; | |
47 | int vco; | |
48 | int m; | |
49 | int p; | |
50 | } intel_clock_t; | |
51 | ||
52 | typedef struct { | |
53 | int min, max; | |
54 | } intel_range_t; | |
55 | ||
56 | typedef struct { | |
57 | int dot_limit; | |
58 | int p2_slow, p2_fast; | |
59 | } intel_p2_t; | |
60 | ||
61 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
62 | typedef struct intel_limit intel_limit_t; |
63 | struct intel_limit { | |
79e53945 JB |
64 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
65 | intel_p2_t p2; | |
d4906093 ML |
66 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
67 | int, int, intel_clock_t *); | |
68 | }; | |
79e53945 JB |
69 | |
70 | #define I8XX_DOT_MIN 25000 | |
71 | #define I8XX_DOT_MAX 350000 | |
72 | #define I8XX_VCO_MIN 930000 | |
73 | #define I8XX_VCO_MAX 1400000 | |
74 | #define I8XX_N_MIN 3 | |
75 | #define I8XX_N_MAX 16 | |
76 | #define I8XX_M_MIN 96 | |
77 | #define I8XX_M_MAX 140 | |
78 | #define I8XX_M1_MIN 18 | |
79 | #define I8XX_M1_MAX 26 | |
80 | #define I8XX_M2_MIN 6 | |
81 | #define I8XX_M2_MAX 16 | |
82 | #define I8XX_P_MIN 4 | |
83 | #define I8XX_P_MAX 128 | |
84 | #define I8XX_P1_MIN 2 | |
85 | #define I8XX_P1_MAX 33 | |
86 | #define I8XX_P1_LVDS_MIN 1 | |
87 | #define I8XX_P1_LVDS_MAX 6 | |
88 | #define I8XX_P2_SLOW 4 | |
89 | #define I8XX_P2_FAST 2 | |
90 | #define I8XX_P2_LVDS_SLOW 14 | |
91 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ | |
92 | #define I8XX_P2_SLOW_LIMIT 165000 | |
93 | ||
94 | #define I9XX_DOT_MIN 20000 | |
95 | #define I9XX_DOT_MAX 400000 | |
96 | #define I9XX_VCO_MIN 1400000 | |
97 | #define I9XX_VCO_MAX 2800000 | |
2177832f SL |
98 | #define IGD_VCO_MIN 1700000 |
99 | #define IGD_VCO_MAX 3500000 | |
f3cade5c KH |
100 | #define I9XX_N_MIN 1 |
101 | #define I9XX_N_MAX 6 | |
2177832f SL |
102 | /* IGD's Ncounter is a ring counter */ |
103 | #define IGD_N_MIN 3 | |
104 | #define IGD_N_MAX 6 | |
79e53945 JB |
105 | #define I9XX_M_MIN 70 |
106 | #define I9XX_M_MAX 120 | |
2177832f SL |
107 | #define IGD_M_MIN 2 |
108 | #define IGD_M_MAX 256 | |
79e53945 | 109 | #define I9XX_M1_MIN 10 |
f3cade5c | 110 | #define I9XX_M1_MAX 22 |
79e53945 JB |
111 | #define I9XX_M2_MIN 5 |
112 | #define I9XX_M2_MAX 9 | |
2177832f SL |
113 | /* IGD M1 is reserved, and must be 0 */ |
114 | #define IGD_M1_MIN 0 | |
115 | #define IGD_M1_MAX 0 | |
116 | #define IGD_M2_MIN 0 | |
117 | #define IGD_M2_MAX 254 | |
79e53945 JB |
118 | #define I9XX_P_SDVO_DAC_MIN 5 |
119 | #define I9XX_P_SDVO_DAC_MAX 80 | |
120 | #define I9XX_P_LVDS_MIN 7 | |
121 | #define I9XX_P_LVDS_MAX 98 | |
2177832f SL |
122 | #define IGD_P_LVDS_MIN 7 |
123 | #define IGD_P_LVDS_MAX 112 | |
79e53945 JB |
124 | #define I9XX_P1_MIN 1 |
125 | #define I9XX_P1_MAX 8 | |
126 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
127 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
128 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
129 | #define I9XX_P2_LVDS_SLOW 14 | |
130 | #define I9XX_P2_LVDS_FAST 7 | |
131 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
132 | ||
044c7c41 ML |
133 | /*The parameter is for SDVO on G4x platform*/ |
134 | #define G4X_DOT_SDVO_MIN 25000 | |
135 | #define G4X_DOT_SDVO_MAX 270000 | |
136 | #define G4X_VCO_MIN 1750000 | |
137 | #define G4X_VCO_MAX 3500000 | |
138 | #define G4X_N_SDVO_MIN 1 | |
139 | #define G4X_N_SDVO_MAX 4 | |
140 | #define G4X_M_SDVO_MIN 104 | |
141 | #define G4X_M_SDVO_MAX 138 | |
142 | #define G4X_M1_SDVO_MIN 17 | |
143 | #define G4X_M1_SDVO_MAX 23 | |
144 | #define G4X_M2_SDVO_MIN 5 | |
145 | #define G4X_M2_SDVO_MAX 11 | |
146 | #define G4X_P_SDVO_MIN 10 | |
147 | #define G4X_P_SDVO_MAX 30 | |
148 | #define G4X_P1_SDVO_MIN 1 | |
149 | #define G4X_P1_SDVO_MAX 3 | |
150 | #define G4X_P2_SDVO_SLOW 10 | |
151 | #define G4X_P2_SDVO_FAST 10 | |
152 | #define G4X_P2_SDVO_LIMIT 270000 | |
153 | ||
154 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
155 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
156 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
157 | #define G4X_N_HDMI_DAC_MIN 1 | |
158 | #define G4X_N_HDMI_DAC_MAX 4 | |
159 | #define G4X_M_HDMI_DAC_MIN 104 | |
160 | #define G4X_M_HDMI_DAC_MAX 138 | |
161 | #define G4X_M1_HDMI_DAC_MIN 16 | |
162 | #define G4X_M1_HDMI_DAC_MAX 23 | |
163 | #define G4X_M2_HDMI_DAC_MIN 5 | |
164 | #define G4X_M2_HDMI_DAC_MAX 11 | |
165 | #define G4X_P_HDMI_DAC_MIN 5 | |
166 | #define G4X_P_HDMI_DAC_MAX 80 | |
167 | #define G4X_P1_HDMI_DAC_MIN 1 | |
168 | #define G4X_P1_HDMI_DAC_MAX 8 | |
169 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
170 | #define G4X_P2_HDMI_DAC_FAST 5 | |
171 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
172 | ||
173 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
174 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
175 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
176 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
177 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
178 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
179 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
180 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
181 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
182 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
183 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
184 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
185 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
186 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
187 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
188 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
189 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
190 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
191 | ||
192 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
193 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
194 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
195 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
196 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
197 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
198 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
199 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
200 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
201 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
202 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
203 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
204 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
205 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
206 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
207 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
208 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
209 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
210 | ||
a4fc5ed6 KP |
211 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
212 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
213 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
214 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
215 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
216 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
217 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
218 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
219 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
220 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
221 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
222 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
223 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
224 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
225 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
226 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
227 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
228 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
229 | ||
2c07245f ZW |
230 | /* IGDNG */ |
231 | /* as we calculate clock using (register_value + 2) for | |
232 | N/M1/M2, so here the range value for them is (actual_value-2). | |
233 | */ | |
234 | #define IGDNG_DOT_MIN 25000 | |
235 | #define IGDNG_DOT_MAX 350000 | |
236 | #define IGDNG_VCO_MIN 1760000 | |
237 | #define IGDNG_VCO_MAX 3510000 | |
238 | #define IGDNG_N_MIN 1 | |
239 | #define IGDNG_N_MAX 5 | |
240 | #define IGDNG_M_MIN 79 | |
241 | #define IGDNG_M_MAX 118 | |
242 | #define IGDNG_M1_MIN 12 | |
243 | #define IGDNG_M1_MAX 23 | |
244 | #define IGDNG_M2_MIN 5 | |
245 | #define IGDNG_M2_MAX 9 | |
246 | #define IGDNG_P_SDVO_DAC_MIN 5 | |
247 | #define IGDNG_P_SDVO_DAC_MAX 80 | |
248 | #define IGDNG_P_LVDS_MIN 28 | |
249 | #define IGDNG_P_LVDS_MAX 112 | |
250 | #define IGDNG_P1_MIN 1 | |
251 | #define IGDNG_P1_MAX 8 | |
252 | #define IGDNG_P2_SDVO_DAC_SLOW 10 | |
253 | #define IGDNG_P2_SDVO_DAC_FAST 5 | |
254 | #define IGDNG_P2_LVDS_SLOW 14 /* single channel */ | |
255 | #define IGDNG_P2_LVDS_FAST 7 /* double channel */ | |
256 | #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ | |
257 | ||
d4906093 ML |
258 | static bool |
259 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
260 | int target, int refclk, intel_clock_t *best_clock); | |
261 | static bool | |
262 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
263 | int target, int refclk, intel_clock_t *best_clock); | |
2c07245f ZW |
264 | static bool |
265 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
266 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 267 | |
a4fc5ed6 KP |
268 | static bool |
269 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
270 | int target, int refclk, intel_clock_t *best_clock); | |
271 | ||
e4b36699 | 272 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
273 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
274 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
275 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
276 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
277 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
278 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
279 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
280 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
281 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
282 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 283 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
284 | }; |
285 | ||
286 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
287 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
288 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
289 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
290 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
291 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
292 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
293 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
294 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
295 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
296 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 297 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
298 | }; |
299 | ||
300 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
301 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
302 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
303 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
304 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
305 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
306 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
307 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
308 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
309 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
310 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 311 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
312 | }; |
313 | ||
314 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
315 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
316 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
317 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
318 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
319 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
320 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
321 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
322 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
323 | /* The single-channel range is 25-112Mhz, and dual-channel | |
324 | * is 80-224Mhz. Prefer single channel as much as possible. | |
325 | */ | |
326 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
327 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 328 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
329 | }; |
330 | ||
044c7c41 | 331 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 332 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
333 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
334 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
335 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
336 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
337 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
338 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
339 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
340 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
341 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
342 | .p2_slow = G4X_P2_SDVO_SLOW, | |
343 | .p2_fast = G4X_P2_SDVO_FAST | |
344 | }, | |
d4906093 | 345 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
346 | }; |
347 | ||
348 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
349 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
350 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
351 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
352 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
353 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
354 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
355 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
356 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
357 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
358 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
359 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
360 | }, | |
d4906093 | 361 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
362 | }; |
363 | ||
364 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
365 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
366 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
367 | .vco = { .min = G4X_VCO_MIN, | |
368 | .max = G4X_VCO_MAX }, | |
369 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
370 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
371 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
372 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
373 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
374 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
375 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
376 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
377 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
378 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
379 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
380 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
381 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
382 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
383 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
384 | }, | |
d4906093 | 385 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
386 | }; |
387 | ||
388 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
389 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
390 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
391 | .vco = { .min = G4X_VCO_MIN, | |
392 | .max = G4X_VCO_MAX }, | |
393 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
394 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
395 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
396 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
397 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
398 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
399 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
400 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
401 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
402 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
403 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
404 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
405 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
406 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
407 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
408 | }, | |
d4906093 | 409 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
410 | }; |
411 | ||
412 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
413 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
414 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
415 | .vco = { .min = G4X_VCO_MIN, | |
416 | .max = G4X_VCO_MAX}, | |
417 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
418 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
419 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
420 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
421 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
422 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
423 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
424 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
425 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
426 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
427 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
428 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
429 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
430 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
431 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
432 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
433 | }; |
434 | ||
435 | static const intel_limit_t intel_limits_igd_sdvo = { | |
2177832f SL |
436 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
437 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
438 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
439 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
440 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
441 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
442 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
443 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
444 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
445 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 446 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
447 | }; |
448 | ||
449 | static const intel_limit_t intel_limits_igd_lvds = { | |
2177832f SL |
450 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
451 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
452 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
453 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
454 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
455 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
456 | .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, | |
457 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
458 | /* IGD only supports single-channel mode. */ | |
459 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
460 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 461 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
462 | }; |
463 | ||
464 | static const intel_limit_t intel_limits_igdng_sdvo = { | |
2c07245f ZW |
465 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
466 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
467 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
468 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
469 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
470 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
471 | .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, | |
472 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
473 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
474 | .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, | |
475 | .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, | |
476 | .find_pll = intel_igdng_find_best_PLL, | |
e4b36699 KP |
477 | }; |
478 | ||
479 | static const intel_limit_t intel_limits_igdng_lvds = { | |
2c07245f ZW |
480 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
481 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
482 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
483 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
484 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
485 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
486 | .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, | |
487 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
488 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
489 | .p2_slow = IGDNG_P2_LVDS_SLOW, | |
490 | .p2_fast = IGDNG_P2_LVDS_FAST }, | |
491 | .find_pll = intel_igdng_find_best_PLL, | |
79e53945 JB |
492 | }; |
493 | ||
2c07245f ZW |
494 | static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) |
495 | { | |
496 | const intel_limit_t *limit; | |
497 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 498 | limit = &intel_limits_igdng_lvds; |
2c07245f | 499 | else |
e4b36699 | 500 | limit = &intel_limits_igdng_sdvo; |
2c07245f ZW |
501 | |
502 | return limit; | |
503 | } | |
504 | ||
044c7c41 ML |
505 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
506 | { | |
507 | struct drm_device *dev = crtc->dev; | |
508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
509 | const intel_limit_t *limit; | |
510 | ||
511 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
512 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
513 | LVDS_CLKB_POWER_UP) | |
514 | /* LVDS with dual channel */ | |
e4b36699 | 515 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
516 | else |
517 | /* LVDS with dual channel */ | |
e4b36699 | 518 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
519 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
520 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 521 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 522 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 523 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 524 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 525 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 526 | } else /* The option is for other outputs */ |
e4b36699 | 527 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
528 | |
529 | return limit; | |
530 | } | |
531 | ||
79e53945 JB |
532 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
533 | { | |
534 | struct drm_device *dev = crtc->dev; | |
535 | const intel_limit_t *limit; | |
536 | ||
2c07245f ZW |
537 | if (IS_IGDNG(dev)) |
538 | limit = intel_igdng_limit(crtc); | |
539 | else if (IS_G4X(dev)) { | |
044c7c41 | 540 | limit = intel_g4x_limit(crtc); |
2177832f | 541 | } else if (IS_I9XX(dev) && !IS_IGD(dev)) { |
79e53945 | 542 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 543 | limit = &intel_limits_i9xx_lvds; |
79e53945 | 544 | else |
e4b36699 | 545 | limit = &intel_limits_i9xx_sdvo; |
2177832f SL |
546 | } else if (IS_IGD(dev)) { |
547 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 548 | limit = &intel_limits_igd_lvds; |
2177832f | 549 | else |
e4b36699 | 550 | limit = &intel_limits_igd_sdvo; |
79e53945 JB |
551 | } else { |
552 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 553 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 554 | else |
e4b36699 | 555 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
556 | } |
557 | return limit; | |
558 | } | |
559 | ||
2177832f SL |
560 | /* m1 is reserved as 0 in IGD, n is a ring counter */ |
561 | static void igd_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 562 | { |
2177832f SL |
563 | clock->m = clock->m2 + 2; |
564 | clock->p = clock->p1 * clock->p2; | |
565 | clock->vco = refclk * clock->m / clock->n; | |
566 | clock->dot = clock->vco / clock->p; | |
567 | } | |
568 | ||
569 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
570 | { | |
571 | if (IS_IGD(dev)) { | |
572 | igd_clock(refclk, clock); | |
573 | return; | |
574 | } | |
79e53945 JB |
575 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
576 | clock->p = clock->p1 * clock->p2; | |
577 | clock->vco = refclk * clock->m / (clock->n + 2); | |
578 | clock->dot = clock->vco / clock->p; | |
579 | } | |
580 | ||
79e53945 JB |
581 | /** |
582 | * Returns whether any output on the specified pipe is of the specified type | |
583 | */ | |
584 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) | |
585 | { | |
586 | struct drm_device *dev = crtc->dev; | |
587 | struct drm_mode_config *mode_config = &dev->mode_config; | |
588 | struct drm_connector *l_entry; | |
589 | ||
590 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | |
591 | if (l_entry->encoder && | |
592 | l_entry->encoder->crtc == crtc) { | |
593 | struct intel_output *intel_output = to_intel_output(l_entry); | |
594 | if (intel_output->type == type) | |
595 | return true; | |
596 | } | |
597 | } | |
598 | return false; | |
599 | } | |
600 | ||
7c04d1d9 | 601 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
602 | /** |
603 | * Returns whether the given set of divisors are valid for a given refclk with | |
604 | * the given connectors. | |
605 | */ | |
606 | ||
607 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
608 | { | |
609 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 610 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
611 | |
612 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
613 | INTELPllInvalid ("p1 out of range\n"); | |
614 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
615 | INTELPllInvalid ("p out of range\n"); | |
616 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
617 | INTELPllInvalid ("m2 out of range\n"); | |
618 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
619 | INTELPllInvalid ("m1 out of range\n"); | |
2177832f | 620 | if (clock->m1 <= clock->m2 && !IS_IGD(dev)) |
79e53945 JB |
621 | INTELPllInvalid ("m1 <= m2\n"); |
622 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
623 | INTELPllInvalid ("m out of range\n"); | |
624 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
625 | INTELPllInvalid ("n out of range\n"); | |
626 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
627 | INTELPllInvalid ("vco out of range\n"); | |
628 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
629 | * connector, etc., rather than just a single range. | |
630 | */ | |
631 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
632 | INTELPllInvalid ("dot out of range\n"); | |
633 | ||
634 | return true; | |
635 | } | |
636 | ||
d4906093 ML |
637 | static bool |
638 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
639 | int target, int refclk, intel_clock_t *best_clock) | |
640 | ||
79e53945 JB |
641 | { |
642 | struct drm_device *dev = crtc->dev; | |
643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
644 | intel_clock_t clock; | |
79e53945 JB |
645 | int err = target; |
646 | ||
647 | if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
648 | (I915_READ(LVDS) & LVDS_PORT_EN) != 0) { | |
649 | /* | |
650 | * For LVDS, if the panel is on, just rely on its current | |
651 | * settings for dual-channel. We haven't figured out how to | |
652 | * reliably set up different single/dual channel state, if we | |
653 | * even can. | |
654 | */ | |
655 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
656 | LVDS_CLKB_POWER_UP) | |
657 | clock.p2 = limit->p2.p2_fast; | |
658 | else | |
659 | clock.p2 = limit->p2.p2_slow; | |
660 | } else { | |
661 | if (target < limit->p2.dot_limit) | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | else | |
664 | clock.p2 = limit->p2.p2_fast; | |
665 | } | |
666 | ||
667 | memset (best_clock, 0, sizeof (*best_clock)); | |
668 | ||
669 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
2177832f SL |
670 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { |
671 | /* m1 is always 0 in IGD */ | |
672 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) | |
673 | break; | |
79e53945 JB |
674 | for (clock.n = limit->n.min; clock.n <= limit->n.max; |
675 | clock.n++) { | |
676 | for (clock.p1 = limit->p1.min; | |
677 | clock.p1 <= limit->p1.max; clock.p1++) { | |
678 | int this_err; | |
679 | ||
2177832f | 680 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
681 | |
682 | if (!intel_PLL_is_valid(crtc, &clock)) | |
683 | continue; | |
684 | ||
685 | this_err = abs(clock.dot - target); | |
686 | if (this_err < err) { | |
687 | *best_clock = clock; | |
688 | err = this_err; | |
689 | } | |
690 | } | |
691 | } | |
692 | } | |
693 | } | |
694 | ||
695 | return (err != target); | |
696 | } | |
697 | ||
d4906093 ML |
698 | static bool |
699 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
700 | int target, int refclk, intel_clock_t *best_clock) | |
701 | { | |
702 | struct drm_device *dev = crtc->dev; | |
703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
704 | intel_clock_t clock; | |
705 | int max_n; | |
706 | bool found; | |
707 | /* approximately equals target * 0.00488 */ | |
708 | int err_most = (target >> 8) + (target >> 10); | |
709 | found = false; | |
710 | ||
711 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
712 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
713 | LVDS_CLKB_POWER_UP) | |
714 | clock.p2 = limit->p2.p2_fast; | |
715 | else | |
716 | clock.p2 = limit->p2.p2_slow; | |
717 | } else { | |
718 | if (target < limit->p2.dot_limit) | |
719 | clock.p2 = limit->p2.p2_slow; | |
720 | else | |
721 | clock.p2 = limit->p2.p2_fast; | |
722 | } | |
723 | ||
724 | memset(best_clock, 0, sizeof(*best_clock)); | |
725 | max_n = limit->n.max; | |
726 | /* based on hardware requriment prefer smaller n to precision */ | |
727 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
728 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
729 | for (clock.m1 = limit->m1.max; | |
730 | clock.m1 >= limit->m1.min; clock.m1--) { | |
731 | for (clock.m2 = limit->m2.max; | |
732 | clock.m2 >= limit->m2.min; clock.m2--) { | |
733 | for (clock.p1 = limit->p1.max; | |
734 | clock.p1 >= limit->p1.min; clock.p1--) { | |
735 | int this_err; | |
736 | ||
2177832f | 737 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
738 | if (!intel_PLL_is_valid(crtc, &clock)) |
739 | continue; | |
740 | this_err = abs(clock.dot - target) ; | |
741 | if (this_err < err_most) { | |
742 | *best_clock = clock; | |
743 | err_most = this_err; | |
744 | max_n = clock.n; | |
745 | found = true; | |
746 | } | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
2c07245f ZW |
751 | return found; |
752 | } | |
753 | ||
754 | static bool | |
755 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
756 | int target, int refclk, intel_clock_t *best_clock) | |
757 | { | |
758 | struct drm_device *dev = crtc->dev; | |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
760 | intel_clock_t clock; | |
761 | int max_n; | |
762 | bool found; | |
763 | int err_most = 47; | |
764 | found = false; | |
765 | ||
766 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
767 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
768 | LVDS_CLKB_POWER_UP) | |
769 | clock.p2 = limit->p2.p2_fast; | |
770 | else | |
771 | clock.p2 = limit->p2.p2_slow; | |
772 | } else { | |
773 | if (target < limit->p2.dot_limit) | |
774 | clock.p2 = limit->p2.p2_slow; | |
775 | else | |
776 | clock.p2 = limit->p2.p2_fast; | |
777 | } | |
778 | ||
779 | memset(best_clock, 0, sizeof(*best_clock)); | |
780 | max_n = limit->n.max; | |
781 | /* based on hardware requriment prefer smaller n to precision */ | |
782 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
783 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
784 | for (clock.m1 = limit->m1.max; | |
785 | clock.m1 >= limit->m1.min; clock.m1--) { | |
786 | for (clock.m2 = limit->m2.max; | |
787 | clock.m2 >= limit->m2.min; clock.m2--) { | |
788 | for (clock.p1 = limit->p1.max; | |
789 | clock.p1 >= limit->p1.min; clock.p1--) { | |
790 | int this_err; | |
d4906093 | 791 | |
2c07245f ZW |
792 | intel_clock(dev, refclk, &clock); |
793 | if (!intel_PLL_is_valid(crtc, &clock)) | |
794 | continue; | |
795 | this_err = abs((10000 - (target*10000/clock.dot))); | |
796 | if (this_err < err_most) { | |
797 | *best_clock = clock; | |
798 | err_most = this_err; | |
799 | max_n = clock.n; | |
800 | found = true; | |
801 | /* found on first matching */ | |
802 | goto out; | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | out: | |
d4906093 ML |
809 | return found; |
810 | } | |
811 | ||
a4fc5ed6 KP |
812 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
813 | static bool | |
814 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
815 | int target, int refclk, intel_clock_t *best_clock) | |
816 | { | |
817 | intel_clock_t clock; | |
818 | if (target < 200000) { | |
819 | clock.dot = 161670; | |
820 | clock.p = 20; | |
821 | clock.p1 = 2; | |
822 | clock.p2 = 10; | |
823 | clock.n = 0x01; | |
824 | clock.m = 97; | |
825 | clock.m1 = 0x10; | |
826 | clock.m2 = 0x05; | |
827 | } else { | |
828 | clock.dot = 270000; | |
829 | clock.p = 10; | |
830 | clock.p1 = 1; | |
831 | clock.p2 = 10; | |
832 | clock.n = 0x02; | |
833 | clock.m = 108; | |
834 | clock.m1 = 0x12; | |
835 | clock.m2 = 0x06; | |
836 | } | |
837 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
838 | return true; | |
839 | } | |
840 | ||
79e53945 JB |
841 | void |
842 | intel_wait_for_vblank(struct drm_device *dev) | |
843 | { | |
844 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | |
580982d3 | 845 | mdelay(20); |
79e53945 JB |
846 | } |
847 | ||
5c3b82e2 | 848 | static int |
3c4fdcfb KH |
849 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
850 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
851 | { |
852 | struct drm_device *dev = crtc->dev; | |
853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
854 | struct drm_i915_master_private *master_priv; | |
855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
856 | struct intel_framebuffer *intel_fb; | |
857 | struct drm_i915_gem_object *obj_priv; | |
858 | struct drm_gem_object *obj; | |
859 | int pipe = intel_crtc->pipe; | |
860 | unsigned long Start, Offset; | |
861 | int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); | |
862 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); | |
863 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
f544847f | 864 | int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF); |
79e53945 | 865 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
3c4fdcfb | 866 | u32 dspcntr, alignment; |
5c3b82e2 | 867 | int ret; |
79e53945 JB |
868 | |
869 | /* no fb bound */ | |
870 | if (!crtc->fb) { | |
871 | DRM_DEBUG("No FB bound\n"); | |
5c3b82e2 CW |
872 | return 0; |
873 | } | |
874 | ||
875 | switch (pipe) { | |
876 | case 0: | |
877 | case 1: | |
878 | break; | |
879 | default: | |
880 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
881 | return -EINVAL; | |
79e53945 JB |
882 | } |
883 | ||
884 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 JB |
885 | obj = intel_fb->obj; |
886 | obj_priv = obj->driver_private; | |
887 | ||
3c4fdcfb KH |
888 | switch (obj_priv->tiling_mode) { |
889 | case I915_TILING_NONE: | |
890 | alignment = 64 * 1024; | |
891 | break; | |
892 | case I915_TILING_X: | |
2ebed176 CW |
893 | /* pin() will align the object as required by fence */ |
894 | alignment = 0; | |
3c4fdcfb KH |
895 | break; |
896 | case I915_TILING_Y: | |
897 | /* FIXME: Is this true? */ | |
898 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
5c3b82e2 | 899 | return -EINVAL; |
3c4fdcfb KH |
900 | default: |
901 | BUG(); | |
902 | } | |
903 | ||
5c3b82e2 | 904 | mutex_lock(&dev->struct_mutex); |
8c4b8c3f | 905 | ret = i915_gem_object_pin(obj, alignment); |
5c3b82e2 CW |
906 | if (ret != 0) { |
907 | mutex_unlock(&dev->struct_mutex); | |
908 | return ret; | |
909 | } | |
79e53945 | 910 | |
8c4b8c3f | 911 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
5c3b82e2 | 912 | if (ret != 0) { |
8c4b8c3f | 913 | i915_gem_object_unpin(obj); |
5c3b82e2 CW |
914 | mutex_unlock(&dev->struct_mutex); |
915 | return ret; | |
916 | } | |
79e53945 | 917 | |
8c4b8c3f CW |
918 | /* Pre-i965 needs to install a fence for tiled scan-out */ |
919 | if (!IS_I965G(dev) && | |
920 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
921 | obj_priv->tiling_mode != I915_TILING_NONE) { | |
922 | ret = i915_gem_object_get_fence_reg(obj); | |
923 | if (ret != 0) { | |
924 | i915_gem_object_unpin(obj); | |
925 | mutex_unlock(&dev->struct_mutex); | |
926 | return ret; | |
927 | } | |
928 | } | |
929 | ||
79e53945 | 930 | dspcntr = I915_READ(dspcntr_reg); |
712531bf JB |
931 | /* Mask out pixel format bits in case we change it */ |
932 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
79e53945 JB |
933 | switch (crtc->fb->bits_per_pixel) { |
934 | case 8: | |
935 | dspcntr |= DISPPLANE_8BPP; | |
936 | break; | |
937 | case 16: | |
938 | if (crtc->fb->depth == 15) | |
939 | dspcntr |= DISPPLANE_15_16BPP; | |
940 | else | |
941 | dspcntr |= DISPPLANE_16BPP; | |
942 | break; | |
943 | case 24: | |
944 | case 32: | |
945 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
946 | break; | |
947 | default: | |
948 | DRM_ERROR("Unknown color depth\n"); | |
8c4b8c3f | 949 | i915_gem_object_unpin(obj); |
5c3b82e2 CW |
950 | mutex_unlock(&dev->struct_mutex); |
951 | return -EINVAL; | |
79e53945 | 952 | } |
f544847f JB |
953 | if (IS_I965G(dev)) { |
954 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
955 | dspcntr |= DISPPLANE_TILED; | |
956 | else | |
957 | dspcntr &= ~DISPPLANE_TILED; | |
958 | } | |
959 | ||
79e53945 JB |
960 | I915_WRITE(dspcntr_reg, dspcntr); |
961 | ||
5c3b82e2 CW |
962 | Start = obj_priv->gtt_offset; |
963 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); | |
964 | ||
79e53945 | 965 | DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); |
5c3b82e2 | 966 | I915_WRITE(dspstride, crtc->fb->pitch); |
79e53945 JB |
967 | if (IS_I965G(dev)) { |
968 | I915_WRITE(dspbase, Offset); | |
969 | I915_READ(dspbase); | |
970 | I915_WRITE(dspsurf, Start); | |
971 | I915_READ(dspsurf); | |
f544847f | 972 | I915_WRITE(dsptileoff, (y << 16) | x); |
79e53945 JB |
973 | } else { |
974 | I915_WRITE(dspbase, Start + Offset); | |
975 | I915_READ(dspbase); | |
976 | } | |
977 | ||
3c4fdcfb KH |
978 | intel_wait_for_vblank(dev); |
979 | ||
980 | if (old_fb) { | |
981 | intel_fb = to_intel_framebuffer(old_fb); | |
982 | i915_gem_object_unpin(intel_fb->obj); | |
983 | } | |
5c3b82e2 | 984 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
985 | |
986 | if (!dev->primary->master) | |
5c3b82e2 | 987 | return 0; |
79e53945 JB |
988 | |
989 | master_priv = dev->primary->master->driver_priv; | |
990 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 991 | return 0; |
79e53945 | 992 | |
5c3b82e2 | 993 | if (pipe) { |
79e53945 JB |
994 | master_priv->sarea_priv->pipeB_x = x; |
995 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
996 | } else { |
997 | master_priv->sarea_priv->pipeA_x = x; | |
998 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 999 | } |
5c3b82e2 CW |
1000 | |
1001 | return 0; | |
79e53945 JB |
1002 | } |
1003 | ||
2c07245f ZW |
1004 | static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) |
1005 | { | |
1006 | struct drm_device *dev = crtc->dev; | |
1007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | int pipe = intel_crtc->pipe; | |
7662c8bd | 1010 | int plane = intel_crtc->plane; |
2c07245f ZW |
1011 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
1012 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1013 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
1014 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
1015 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
1016 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
1017 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; | |
1018 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; | |
1019 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | |
1020 | int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; | |
1021 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
1022 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
1023 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
1024 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
1025 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
1026 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
1027 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | |
1028 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | |
1029 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | |
1030 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | |
1031 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | |
1032 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | |
1033 | u32 temp; | |
1034 | int tries = 5, j; | |
79e53945 | 1035 | |
2c07245f ZW |
1036 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
1037 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
1038 | */ | |
1039 | switch (mode) { | |
1040 | case DRM_MODE_DPMS_ON: | |
1041 | case DRM_MODE_DPMS_STANDBY: | |
1042 | case DRM_MODE_DPMS_SUSPEND: | |
1043 | DRM_DEBUG("crtc %d dpms on\n", pipe); | |
1044 | /* enable PCH DPLL */ | |
1045 | temp = I915_READ(pch_dpll_reg); | |
1046 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1047 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); | |
1048 | I915_READ(pch_dpll_reg); | |
1049 | } | |
79e53945 | 1050 | |
2c07245f ZW |
1051 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
1052 | temp = I915_READ(fdi_rx_reg); | |
1053 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | | |
1054 | FDI_SEL_PCDCLK | | |
1055 | FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ | |
1056 | I915_READ(fdi_rx_reg); | |
1057 | udelay(200); | |
1058 | ||
1059 | /* Enable CPU FDI TX PLL, always on for IGDNG */ | |
1060 | temp = I915_READ(fdi_tx_reg); | |
1061 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
1062 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); | |
1063 | I915_READ(fdi_tx_reg); | |
1064 | udelay(100); | |
1065 | } | |
1066 | ||
1067 | /* Enable CPU pipe */ | |
1068 | temp = I915_READ(pipeconf_reg); | |
1069 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
1070 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1071 | I915_READ(pipeconf_reg); | |
1072 | udelay(100); | |
1073 | } | |
1074 | ||
1075 | /* configure and enable CPU plane */ | |
1076 | temp = I915_READ(dspcntr_reg); | |
1077 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1078 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1079 | /* Flush the plane changes */ | |
1080 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1081 | } | |
1082 | ||
1083 | /* enable CPU FDI TX and PCH FDI RX */ | |
1084 | temp = I915_READ(fdi_tx_reg); | |
1085 | temp |= FDI_TX_ENABLE; | |
1086 | temp |= FDI_DP_PORT_WIDTH_X4; /* default */ | |
1087 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1088 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1089 | I915_WRITE(fdi_tx_reg, temp); | |
1090 | I915_READ(fdi_tx_reg); | |
1091 | ||
1092 | temp = I915_READ(fdi_rx_reg); | |
1093 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1094 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1095 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); | |
1096 | I915_READ(fdi_rx_reg); | |
1097 | ||
1098 | udelay(150); | |
1099 | ||
1100 | /* Train FDI. */ | |
1101 | /* umask FDI RX Interrupt symbol_lock and bit_lock bit | |
1102 | for train result */ | |
1103 | temp = I915_READ(fdi_rx_imr_reg); | |
1104 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
1105 | temp &= ~FDI_RX_BIT_LOCK; | |
1106 | I915_WRITE(fdi_rx_imr_reg, temp); | |
1107 | I915_READ(fdi_rx_imr_reg); | |
1108 | udelay(150); | |
1109 | ||
1110 | temp = I915_READ(fdi_rx_iir_reg); | |
1111 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1112 | ||
1113 | if ((temp & FDI_RX_BIT_LOCK) == 0) { | |
1114 | for (j = 0; j < tries; j++) { | |
1115 | temp = I915_READ(fdi_rx_iir_reg); | |
1116 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1117 | if (temp & FDI_RX_BIT_LOCK) | |
1118 | break; | |
1119 | udelay(200); | |
1120 | } | |
1121 | if (j != tries) | |
1122 | I915_WRITE(fdi_rx_iir_reg, | |
1123 | temp | FDI_RX_BIT_LOCK); | |
1124 | else | |
1125 | DRM_DEBUG("train 1 fail\n"); | |
1126 | } else { | |
1127 | I915_WRITE(fdi_rx_iir_reg, | |
1128 | temp | FDI_RX_BIT_LOCK); | |
1129 | DRM_DEBUG("train 1 ok 2!\n"); | |
1130 | } | |
1131 | temp = I915_READ(fdi_tx_reg); | |
1132 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1133 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1134 | I915_WRITE(fdi_tx_reg, temp); | |
1135 | ||
1136 | temp = I915_READ(fdi_rx_reg); | |
1137 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1138 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1139 | I915_WRITE(fdi_rx_reg, temp); | |
1140 | ||
1141 | udelay(150); | |
1142 | ||
1143 | temp = I915_READ(fdi_rx_iir_reg); | |
1144 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1145 | ||
1146 | if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { | |
1147 | for (j = 0; j < tries; j++) { | |
1148 | temp = I915_READ(fdi_rx_iir_reg); | |
1149 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1150 | if (temp & FDI_RX_SYMBOL_LOCK) | |
1151 | break; | |
1152 | udelay(200); | |
1153 | } | |
1154 | if (j != tries) { | |
1155 | I915_WRITE(fdi_rx_iir_reg, | |
1156 | temp | FDI_RX_SYMBOL_LOCK); | |
1157 | DRM_DEBUG("train 2 ok 1!\n"); | |
1158 | } else | |
1159 | DRM_DEBUG("train 2 fail\n"); | |
1160 | } else { | |
1161 | I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK); | |
1162 | DRM_DEBUG("train 2 ok 2!\n"); | |
1163 | } | |
1164 | DRM_DEBUG("train done\n"); | |
1165 | ||
1166 | /* set transcoder timing */ | |
1167 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); | |
1168 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); | |
1169 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); | |
1170 | ||
1171 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); | |
1172 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); | |
1173 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); | |
1174 | ||
1175 | /* enable PCH transcoder */ | |
1176 | temp = I915_READ(transconf_reg); | |
1177 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); | |
1178 | I915_READ(transconf_reg); | |
1179 | ||
1180 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) | |
1181 | ; | |
1182 | ||
1183 | /* enable normal */ | |
1184 | ||
1185 | temp = I915_READ(fdi_tx_reg); | |
1186 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1187 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1188 | FDI_TX_ENHANCE_FRAME_ENABLE); | |
1189 | I915_READ(fdi_tx_reg); | |
1190 | ||
1191 | temp = I915_READ(fdi_rx_reg); | |
1192 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1193 | I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1194 | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1195 | I915_READ(fdi_rx_reg); | |
1196 | ||
1197 | /* wait one idle pattern time */ | |
1198 | udelay(100); | |
1199 | ||
1200 | intel_crtc_load_lut(crtc); | |
1201 | ||
1202 | break; | |
1203 | case DRM_MODE_DPMS_OFF: | |
1204 | DRM_DEBUG("crtc %d dpms off\n", pipe); | |
1205 | ||
1206 | /* Disable the VGA plane that we never use */ | |
1207 | I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE); | |
1208 | ||
1209 | /* Disable display plane */ | |
1210 | temp = I915_READ(dspcntr_reg); | |
1211 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1212 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1213 | /* Flush the plane changes */ | |
1214 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1215 | I915_READ(dspbase_reg); | |
1216 | } | |
1217 | ||
1218 | /* disable cpu pipe, disable after all planes disabled */ | |
1219 | temp = I915_READ(pipeconf_reg); | |
1220 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1221 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1222 | I915_READ(pipeconf_reg); | |
1223 | /* wait for cpu pipe off, pipe state */ | |
1224 | while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) | |
1225 | ; | |
1226 | } else | |
1227 | DRM_DEBUG("crtc %d is disabled\n", pipe); | |
1228 | ||
1229 | /* IGDNG-A : disable cpu panel fitter ? */ | |
1230 | temp = I915_READ(pf_ctl_reg); | |
1231 | if ((temp & PF_ENABLE) != 0) { | |
1232 | I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); | |
1233 | I915_READ(pf_ctl_reg); | |
1234 | } | |
1235 | ||
1236 | /* disable CPU FDI tx and PCH FDI rx */ | |
1237 | temp = I915_READ(fdi_tx_reg); | |
1238 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); | |
1239 | I915_READ(fdi_tx_reg); | |
1240 | ||
1241 | temp = I915_READ(fdi_rx_reg); | |
1242 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); | |
1243 | I915_READ(fdi_rx_reg); | |
1244 | ||
1245 | /* still set train pattern 1 */ | |
1246 | temp = I915_READ(fdi_tx_reg); | |
1247 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1248 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1249 | I915_WRITE(fdi_tx_reg, temp); | |
1250 | ||
1251 | temp = I915_READ(fdi_rx_reg); | |
1252 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1253 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1254 | I915_WRITE(fdi_rx_reg, temp); | |
1255 | ||
1256 | /* disable PCH transcoder */ | |
1257 | temp = I915_READ(transconf_reg); | |
1258 | if ((temp & TRANS_ENABLE) != 0) { | |
1259 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); | |
1260 | I915_READ(transconf_reg); | |
1261 | /* wait for PCH transcoder off, transcoder state */ | |
1262 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) | |
1263 | ; | |
1264 | } | |
1265 | ||
1266 | /* disable PCH DPLL */ | |
1267 | temp = I915_READ(pch_dpll_reg); | |
1268 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1269 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1270 | I915_READ(pch_dpll_reg); | |
1271 | } | |
1272 | ||
1273 | temp = I915_READ(fdi_rx_reg); | |
1274 | if ((temp & FDI_RX_PLL_ENABLE) != 0) { | |
1275 | temp &= ~FDI_SEL_PCDCLK; | |
1276 | temp &= ~FDI_RX_PLL_ENABLE; | |
1277 | I915_WRITE(fdi_rx_reg, temp); | |
1278 | I915_READ(fdi_rx_reg); | |
1279 | } | |
1280 | ||
1281 | /* Wait for the clocks to turn off. */ | |
1282 | udelay(150); | |
1283 | break; | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
79e53945 JB |
1288 | { |
1289 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1290 | struct drm_i915_private *dev_priv = dev->dev_private; |
1291 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1292 | int pipe = intel_crtc->pipe; | |
1293 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
1294 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
1295 | int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; | |
1296 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1297 | u32 temp; | |
79e53945 JB |
1298 | |
1299 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
1300 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
1301 | */ | |
1302 | switch (mode) { | |
1303 | case DRM_MODE_DPMS_ON: | |
1304 | case DRM_MODE_DPMS_STANDBY: | |
1305 | case DRM_MODE_DPMS_SUSPEND: | |
1306 | /* Enable the DPLL */ | |
1307 | temp = I915_READ(dpll_reg); | |
1308 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1309 | I915_WRITE(dpll_reg, temp); | |
1310 | I915_READ(dpll_reg); | |
1311 | /* Wait for the clocks to stabilize. */ | |
1312 | udelay(150); | |
1313 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1314 | I915_READ(dpll_reg); | |
1315 | /* Wait for the clocks to stabilize. */ | |
1316 | udelay(150); | |
1317 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1318 | I915_READ(dpll_reg); | |
1319 | /* Wait for the clocks to stabilize. */ | |
1320 | udelay(150); | |
1321 | } | |
1322 | ||
1323 | /* Enable the pipe */ | |
1324 | temp = I915_READ(pipeconf_reg); | |
1325 | if ((temp & PIPEACONF_ENABLE) == 0) | |
1326 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1327 | ||
1328 | /* Enable the plane */ | |
1329 | temp = I915_READ(dspcntr_reg); | |
1330 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1331 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1332 | /* Flush the plane changes */ | |
1333 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1334 | } | |
1335 | ||
1336 | intel_crtc_load_lut(crtc); | |
1337 | ||
1338 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
1339 | //intel_crtc_dpms_video(crtc, true); TODO | |
7662c8bd | 1340 | intel_update_watermarks(dev); |
79e53945 JB |
1341 | break; |
1342 | case DRM_MODE_DPMS_OFF: | |
7662c8bd | 1343 | intel_update_watermarks(dev); |
79e53945 JB |
1344 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
1345 | //intel_crtc_dpms_video(crtc, FALSE); TODO | |
1346 | ||
1347 | /* Disable the VGA plane that we never use */ | |
1348 | I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
1349 | ||
1350 | /* Disable display plane */ | |
1351 | temp = I915_READ(dspcntr_reg); | |
1352 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1353 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1354 | /* Flush the plane changes */ | |
1355 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1356 | I915_READ(dspbase_reg); | |
1357 | } | |
1358 | ||
1359 | if (!IS_I9XX(dev)) { | |
1360 | /* Wait for vblank for the disable to take effect */ | |
1361 | intel_wait_for_vblank(dev); | |
1362 | } | |
1363 | ||
1364 | /* Next, disable display pipes */ | |
1365 | temp = I915_READ(pipeconf_reg); | |
1366 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1367 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1368 | I915_READ(pipeconf_reg); | |
1369 | } | |
1370 | ||
1371 | /* Wait for vblank for the disable to take effect. */ | |
1372 | intel_wait_for_vblank(dev); | |
1373 | ||
1374 | temp = I915_READ(dpll_reg); | |
1375 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1376 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1377 | I915_READ(dpll_reg); | |
1378 | } | |
1379 | ||
1380 | /* Wait for the clocks to turn off. */ | |
1381 | udelay(150); | |
1382 | break; | |
1383 | } | |
2c07245f ZW |
1384 | } |
1385 | ||
1386 | /** | |
1387 | * Sets the power management mode of the pipe and plane. | |
1388 | * | |
1389 | * This code should probably grow support for turning the cursor off and back | |
1390 | * on appropriately at the same time as we're turning the pipe off/on. | |
1391 | */ | |
1392 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
1393 | { | |
1394 | struct drm_device *dev = crtc->dev; | |
1395 | struct drm_i915_master_private *master_priv; | |
1396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1397 | int pipe = intel_crtc->pipe; | |
1398 | bool enabled; | |
1399 | ||
1400 | if (IS_IGDNG(dev)) | |
1401 | igdng_crtc_dpms(crtc, mode); | |
1402 | else | |
1403 | i9xx_crtc_dpms(crtc, mode); | |
79e53945 JB |
1404 | |
1405 | if (!dev->primary->master) | |
1406 | return; | |
1407 | ||
1408 | master_priv = dev->primary->master->driver_priv; | |
1409 | if (!master_priv->sarea_priv) | |
1410 | return; | |
1411 | ||
1412 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
1413 | ||
1414 | switch (pipe) { | |
1415 | case 0: | |
1416 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
1417 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
1418 | break; | |
1419 | case 1: | |
1420 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
1421 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
1422 | break; | |
1423 | default: | |
1424 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
1425 | break; | |
1426 | } | |
1427 | ||
1428 | intel_crtc->dpms_mode = mode; | |
1429 | } | |
1430 | ||
1431 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
1432 | { | |
1433 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1434 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
1435 | } | |
1436 | ||
1437 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
1438 | { | |
1439 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1440 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1441 | } | |
1442 | ||
1443 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
1444 | { | |
1445 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1446 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
1447 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
1448 | } | |
1449 | ||
1450 | void intel_encoder_commit (struct drm_encoder *encoder) | |
1451 | { | |
1452 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1453 | /* lvds has its own version of commit see intel_lvds_commit */ | |
1454 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
1455 | } | |
1456 | ||
1457 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, | |
1458 | struct drm_display_mode *mode, | |
1459 | struct drm_display_mode *adjusted_mode) | |
1460 | { | |
2c07245f ZW |
1461 | struct drm_device *dev = crtc->dev; |
1462 | if (IS_IGDNG(dev)) { | |
1463 | /* FDI link clock is fixed at 2.7G */ | |
1464 | if (mode->clock * 3 > 27000 * 4) | |
1465 | return MODE_CLOCK_HIGH; | |
1466 | } | |
79e53945 JB |
1467 | return true; |
1468 | } | |
1469 | ||
1470 | ||
1471 | /** Returns the core display clock speed for i830 - i945 */ | |
1472 | static int intel_get_core_clock_speed(struct drm_device *dev) | |
1473 | { | |
1474 | ||
1475 | /* Core clock values taken from the published datasheets. | |
1476 | * The 830 may go up to 166 Mhz, which we should check. | |
1477 | */ | |
1478 | if (IS_I945G(dev)) | |
1479 | return 400000; | |
1480 | else if (IS_I915G(dev)) | |
1481 | return 333000; | |
2177832f | 1482 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) |
79e53945 JB |
1483 | return 200000; |
1484 | else if (IS_I915GM(dev)) { | |
1485 | u16 gcfgc = 0; | |
1486 | ||
1487 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
1488 | ||
1489 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
1490 | return 133000; | |
1491 | else { | |
1492 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
1493 | case GC_DISPLAY_CLOCK_333_MHZ: | |
1494 | return 333000; | |
1495 | default: | |
1496 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
1497 | return 190000; | |
1498 | } | |
1499 | } | |
1500 | } else if (IS_I865G(dev)) | |
1501 | return 266000; | |
1502 | else if (IS_I855(dev)) { | |
1503 | u16 hpllcc = 0; | |
1504 | /* Assume that the hardware is in the high speed state. This | |
1505 | * should be the default. | |
1506 | */ | |
1507 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
1508 | case GC_CLOCK_133_200: | |
1509 | case GC_CLOCK_100_200: | |
1510 | return 200000; | |
1511 | case GC_CLOCK_166_250: | |
1512 | return 250000; | |
1513 | case GC_CLOCK_100_133: | |
1514 | return 133000; | |
1515 | } | |
1516 | } else /* 852, 830 */ | |
1517 | return 133000; | |
1518 | ||
1519 | return 0; /* Silence gcc warning */ | |
1520 | } | |
1521 | ||
79e53945 JB |
1522 | /** |
1523 | * Return the pipe currently connected to the panel fitter, | |
1524 | * or -1 if the panel fitter is not present or not in use | |
1525 | */ | |
1526 | static int intel_panel_fitter_pipe (struct drm_device *dev) | |
1527 | { | |
1528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1529 | u32 pfit_control; | |
1530 | ||
1531 | /* i830 doesn't have a panel fitter */ | |
1532 | if (IS_I830(dev)) | |
1533 | return -1; | |
1534 | ||
1535 | pfit_control = I915_READ(PFIT_CONTROL); | |
1536 | ||
1537 | /* See if the panel fitter is in use */ | |
1538 | if ((pfit_control & PFIT_ENABLE) == 0) | |
1539 | return -1; | |
1540 | ||
1541 | /* 965 can place panel fitter on either pipe */ | |
1542 | if (IS_I965G(dev)) | |
1543 | return (pfit_control >> 29) & 0x3; | |
1544 | ||
1545 | /* older chips can only use pipe 1 */ | |
1546 | return 1; | |
1547 | } | |
1548 | ||
2c07245f ZW |
1549 | struct fdi_m_n { |
1550 | u32 tu; | |
1551 | u32 gmch_m; | |
1552 | u32 gmch_n; | |
1553 | u32 link_m; | |
1554 | u32 link_n; | |
1555 | }; | |
1556 | ||
1557 | static void | |
1558 | fdi_reduce_ratio(u32 *num, u32 *den) | |
1559 | { | |
1560 | while (*num > 0xffffff || *den > 0xffffff) { | |
1561 | *num >>= 1; | |
1562 | *den >>= 1; | |
1563 | } | |
1564 | } | |
1565 | ||
1566 | #define DATA_N 0x800000 | |
1567 | #define LINK_N 0x80000 | |
1568 | ||
1569 | static void | |
1570 | igdng_compute_m_n(int bytes_per_pixel, int nlanes, | |
1571 | int pixel_clock, int link_clock, | |
1572 | struct fdi_m_n *m_n) | |
1573 | { | |
1574 | u64 temp; | |
1575 | ||
1576 | m_n->tu = 64; /* default size */ | |
1577 | ||
1578 | temp = (u64) DATA_N * pixel_clock; | |
1579 | temp = div_u64(temp, link_clock); | |
1580 | m_n->gmch_m = (temp * bytes_per_pixel) / nlanes; | |
1581 | m_n->gmch_n = DATA_N; | |
1582 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
1583 | ||
1584 | temp = (u64) LINK_N * pixel_clock; | |
1585 | m_n->link_m = div_u64(temp, link_clock); | |
1586 | m_n->link_n = LINK_N; | |
1587 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
1588 | } | |
1589 | ||
1590 | ||
7662c8bd SL |
1591 | struct intel_watermark_params { |
1592 | unsigned long fifo_size; | |
1593 | unsigned long max_wm; | |
1594 | unsigned long default_wm; | |
1595 | unsigned long guard_size; | |
1596 | unsigned long cacheline_size; | |
1597 | }; | |
1598 | ||
1599 | /* IGD has different values for various configs */ | |
1600 | static struct intel_watermark_params igd_display_wm = { | |
1601 | IGD_DISPLAY_FIFO, | |
1602 | IGD_MAX_WM, | |
1603 | IGD_DFT_WM, | |
1604 | IGD_GUARD_WM, | |
1605 | IGD_FIFO_LINE_SIZE | |
1606 | }; | |
1607 | static struct intel_watermark_params igd_display_hplloff_wm = { | |
1608 | IGD_DISPLAY_FIFO, | |
1609 | IGD_MAX_WM, | |
1610 | IGD_DFT_HPLLOFF_WM, | |
1611 | IGD_GUARD_WM, | |
1612 | IGD_FIFO_LINE_SIZE | |
1613 | }; | |
1614 | static struct intel_watermark_params igd_cursor_wm = { | |
1615 | IGD_CURSOR_FIFO, | |
1616 | IGD_CURSOR_MAX_WM, | |
1617 | IGD_CURSOR_DFT_WM, | |
1618 | IGD_CURSOR_GUARD_WM, | |
1619 | IGD_FIFO_LINE_SIZE, | |
1620 | }; | |
1621 | static struct intel_watermark_params igd_cursor_hplloff_wm = { | |
1622 | IGD_CURSOR_FIFO, | |
1623 | IGD_CURSOR_MAX_WM, | |
1624 | IGD_CURSOR_DFT_WM, | |
1625 | IGD_CURSOR_GUARD_WM, | |
1626 | IGD_FIFO_LINE_SIZE | |
1627 | }; | |
1628 | static struct intel_watermark_params i945_wm_info = { | |
1629 | I915_FIFO_LINE_SIZE, | |
1630 | I915_MAX_WM, | |
1631 | 1, | |
1632 | 0, | |
1633 | IGD_FIFO_LINE_SIZE | |
1634 | }; | |
1635 | static struct intel_watermark_params i915_wm_info = { | |
1636 | I945_FIFO_SIZE, | |
1637 | I915_MAX_WM, | |
1638 | 1, | |
1639 | 0, | |
1640 | I915_FIFO_LINE_SIZE | |
1641 | }; | |
1642 | static struct intel_watermark_params i855_wm_info = { | |
1643 | I855GM_FIFO_SIZE, | |
1644 | I915_MAX_WM, | |
1645 | 1, | |
1646 | 0, | |
1647 | I830_FIFO_LINE_SIZE | |
1648 | }; | |
1649 | static struct intel_watermark_params i830_wm_info = { | |
1650 | I830_FIFO_SIZE, | |
1651 | I915_MAX_WM, | |
1652 | 1, | |
1653 | 0, | |
1654 | I830_FIFO_LINE_SIZE | |
1655 | }; | |
1656 | ||
1657 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
1658 | struct intel_watermark_params *wm, | |
1659 | int pixel_size, | |
1660 | unsigned long latency_ns) | |
1661 | { | |
1662 | unsigned long bytes_required, wm_size; | |
1663 | ||
1664 | bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000; | |
1665 | bytes_required /= wm->cacheline_size; | |
1666 | wm_size = wm->fifo_size - bytes_required - wm->guard_size; | |
1667 | ||
1668 | if (wm_size > wm->max_wm) | |
1669 | wm_size = wm->max_wm; | |
1670 | if (wm_size == 0) | |
1671 | wm_size = wm->default_wm; | |
1672 | return wm_size; | |
1673 | } | |
1674 | ||
1675 | struct cxsr_latency { | |
1676 | int is_desktop; | |
1677 | unsigned long fsb_freq; | |
1678 | unsigned long mem_freq; | |
1679 | unsigned long display_sr; | |
1680 | unsigned long display_hpll_disable; | |
1681 | unsigned long cursor_sr; | |
1682 | unsigned long cursor_hpll_disable; | |
1683 | }; | |
1684 | ||
1685 | static struct cxsr_latency cxsr_latency_table[] = { | |
1686 | {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
1687 | {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
1688 | {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
1689 | ||
1690 | {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
1691 | {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
1692 | {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
1693 | ||
1694 | {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
1695 | {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
1696 | {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
1697 | ||
1698 | {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
1699 | {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
1700 | {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
1701 | ||
1702 | {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
1703 | {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
1704 | {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
1705 | ||
1706 | {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
1707 | {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
1708 | {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
1709 | }; | |
1710 | ||
1711 | static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb, | |
1712 | int mem) | |
1713 | { | |
1714 | int i; | |
1715 | struct cxsr_latency *latency; | |
1716 | ||
1717 | if (fsb == 0 || mem == 0) | |
1718 | return NULL; | |
1719 | ||
1720 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
1721 | latency = &cxsr_latency_table[i]; | |
1722 | if (is_desktop == latency->is_desktop && | |
1723 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
1724 | break; | |
1725 | } | |
1726 | if (i >= ARRAY_SIZE(cxsr_latency_table)) { | |
1727 | DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); | |
1728 | return NULL; | |
1729 | } | |
1730 | return latency; | |
1731 | } | |
1732 | ||
1733 | static void igd_disable_cxsr(struct drm_device *dev) | |
1734 | { | |
1735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1736 | u32 reg; | |
1737 | ||
1738 | /* deactivate cxsr */ | |
1739 | reg = I915_READ(DSPFW3); | |
1740 | reg &= ~(IGD_SELF_REFRESH_EN); | |
1741 | I915_WRITE(DSPFW3, reg); | |
1742 | DRM_INFO("Big FIFO is disabled\n"); | |
1743 | } | |
1744 | ||
1745 | static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, | |
1746 | int pixel_size) | |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | u32 reg; | |
1750 | unsigned long wm; | |
1751 | struct cxsr_latency *latency; | |
1752 | ||
1753 | latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, | |
1754 | dev_priv->mem_freq); | |
1755 | if (!latency) { | |
1756 | DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); | |
1757 | igd_disable_cxsr(dev); | |
1758 | return; | |
1759 | } | |
1760 | ||
1761 | /* Display SR */ | |
1762 | wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, | |
1763 | latency->display_sr); | |
1764 | reg = I915_READ(DSPFW1); | |
1765 | reg &= 0x7fffff; | |
1766 | reg |= wm << 23; | |
1767 | I915_WRITE(DSPFW1, reg); | |
1768 | DRM_DEBUG("DSPFW1 register is %x\n", reg); | |
1769 | ||
1770 | /* cursor SR */ | |
1771 | wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, | |
1772 | latency->cursor_sr); | |
1773 | reg = I915_READ(DSPFW3); | |
1774 | reg &= ~(0x3f << 24); | |
1775 | reg |= (wm & 0x3f) << 24; | |
1776 | I915_WRITE(DSPFW3, reg); | |
1777 | ||
1778 | /* Display HPLL off SR */ | |
1779 | wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, | |
1780 | latency->display_hpll_disable, I915_FIFO_LINE_SIZE); | |
1781 | reg = I915_READ(DSPFW3); | |
1782 | reg &= 0xfffffe00; | |
1783 | reg |= wm & 0x1ff; | |
1784 | I915_WRITE(DSPFW3, reg); | |
1785 | ||
1786 | /* cursor HPLL off SR */ | |
1787 | wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, | |
1788 | latency->cursor_hpll_disable); | |
1789 | reg = I915_READ(DSPFW3); | |
1790 | reg &= ~(0x3f << 16); | |
1791 | reg |= (wm & 0x3f) << 16; | |
1792 | I915_WRITE(DSPFW3, reg); | |
1793 | DRM_DEBUG("DSPFW3 register is %x\n", reg); | |
1794 | ||
1795 | /* activate cxsr */ | |
1796 | reg = I915_READ(DSPFW3); | |
1797 | reg |= IGD_SELF_REFRESH_EN; | |
1798 | I915_WRITE(DSPFW3, reg); | |
1799 | ||
1800 | DRM_INFO("Big FIFO is enabled\n"); | |
1801 | ||
1802 | return; | |
1803 | } | |
1804 | ||
1805 | const static int latency_ns = 5000; /* default for non-igd platforms */ | |
1806 | ||
1807 | ||
1808 | static void i965_update_wm(struct drm_device *dev) | |
1809 | { | |
1810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1811 | ||
1812 | DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); | |
1813 | ||
1814 | /* 965 has limitations... */ | |
1815 | I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); | |
1816 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1817 | } | |
1818 | ||
1819 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
1820 | int planeb_clock, int sr_hdisplay, int pixel_size) | |
1821 | { | |
1822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1823 | uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; | |
1824 | uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK; | |
1825 | int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1; | |
1826 | uint32_t dsparb = I915_READ(DSPARB); | |
1827 | int planea_entries, planeb_entries; | |
1828 | struct intel_watermark_params *wm_params; | |
1829 | unsigned long line_time_us; | |
1830 | int sr_clock, sr_entries = 0; | |
1831 | ||
1832 | if (IS_I965GM(dev) || IS_I945GM(dev)) | |
1833 | wm_params = &i945_wm_info; | |
1834 | else if (IS_I9XX(dev)) | |
1835 | wm_params = &i915_wm_info; | |
1836 | else | |
1837 | wm_params = &i855_wm_info; | |
1838 | ||
1839 | planea_entries = intel_calculate_wm(planea_clock, wm_params, | |
1840 | pixel_size, latency_ns); | |
1841 | planeb_entries = intel_calculate_wm(planeb_clock, wm_params, | |
1842 | pixel_size, latency_ns); | |
1843 | ||
1844 | DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries, | |
1845 | planeb_entries); | |
1846 | ||
1847 | if (IS_I9XX(dev)) { | |
1848 | asize = dsparb & 0x7f; | |
1849 | bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f; | |
1850 | } else { | |
1851 | asize = dsparb & 0x1ff; | |
1852 | bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff; | |
1853 | } | |
1854 | DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize); | |
1855 | ||
1856 | /* Two extra entries for padding */ | |
1857 | awm = asize - (planea_entries + 2); | |
1858 | bwm = bsize - (planeb_entries + 2); | |
1859 | ||
1860 | /* Sanity check against potentially bad FIFO allocations */ | |
1861 | if (awm <= 0) { | |
1862 | /* pipe is on but has too few FIFO entries */ | |
1863 | if (planea_entries != 0) | |
1864 | DRM_DEBUG("plane A needs more FIFO entries\n"); | |
1865 | awm = 1; | |
1866 | } | |
1867 | if (bwm <= 0) { | |
1868 | if (planeb_entries != 0) | |
1869 | DRM_DEBUG("plane B needs more FIFO entries\n"); | |
1870 | bwm = 1; | |
1871 | } | |
1872 | ||
1873 | /* | |
1874 | * Overlay gets an aggressive default since video jitter is bad. | |
1875 | */ | |
1876 | cwm = 2; | |
1877 | ||
1878 | /* Calc sr entries for one pipe configs */ | |
1879 | if (!planea_clock || !planeb_clock) { | |
1880 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
1881 | line_time_us = (sr_hdisplay * 1000) / sr_clock; | |
1882 | sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size * | |
1883 | sr_hdisplay) / 1000; | |
1884 | sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1); | |
1885 | if (sr_entries < wm_params->fifo_size) | |
1886 | srwm = wm_params->fifo_size - sr_entries; | |
1887 | } | |
1888 | ||
1889 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1890 | awm, bwm, cwm, srwm); | |
1891 | ||
1892 | fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f); | |
1893 | fwater_hi = fwater_hi | (cwm & 0x1f); | |
1894 | ||
1895 | I915_WRITE(FW_BLC, fwater_lo); | |
1896 | I915_WRITE(FW_BLC2, fwater_hi); | |
1897 | if (IS_I9XX(dev)) | |
1898 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); | |
1899 | } | |
1900 | ||
1901 | static void i830_update_wm(struct drm_device *dev, int planea_clock, | |
1902 | int pixel_size) | |
1903 | { | |
1904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1905 | uint32_t dsparb = I915_READ(DSPARB); | |
1906 | uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; | |
1907 | unsigned int asize, awm; | |
1908 | int planea_entries; | |
1909 | ||
1910 | planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info, | |
1911 | pixel_size, latency_ns); | |
1912 | ||
1913 | asize = dsparb & 0x7f; | |
1914 | ||
1915 | awm = asize - planea_entries; | |
1916 | ||
1917 | fwater_lo = fwater_lo | awm; | |
1918 | ||
1919 | I915_WRITE(FW_BLC, fwater_lo); | |
1920 | } | |
1921 | ||
1922 | /** | |
1923 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
1924 | * | |
1925 | * Calculate watermark values for the various WM regs based on current mode | |
1926 | * and plane configuration. | |
1927 | * | |
1928 | * There are several cases to deal with here: | |
1929 | * - normal (i.e. non-self-refresh) | |
1930 | * - self-refresh (SR) mode | |
1931 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
1932 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
1933 | * lines), so need to account for TLB latency | |
1934 | * | |
1935 | * The normal calculation is: | |
1936 | * watermark = dotclock * bytes per pixel * latency | |
1937 | * where latency is platform & configuration dependent (we assume pessimal | |
1938 | * values here). | |
1939 | * | |
1940 | * The SR calculation is: | |
1941 | * watermark = (trunc(latency/line time)+1) * surface width * | |
1942 | * bytes per pixel | |
1943 | * where | |
1944 | * line time = htotal / dotclock | |
1945 | * and latency is assumed to be high, as above. | |
1946 | * | |
1947 | * The final value programmed to the register should always be rounded up, | |
1948 | * and include an extra 2 entries to account for clock crossings. | |
1949 | * | |
1950 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
1951 | * to set the non-SR watermarks to 8. | |
1952 | */ | |
1953 | static void intel_update_watermarks(struct drm_device *dev) | |
1954 | { | |
1955 | struct drm_crtc *crtc; | |
1956 | struct intel_crtc *intel_crtc; | |
1957 | int sr_hdisplay = 0; | |
1958 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
1959 | int enabled = 0, pixel_size = 0; | |
1960 | ||
1961 | if (DSPARB_HWCONTROL(dev)) | |
1962 | return; | |
1963 | ||
1964 | /* Get the clock config from both planes */ | |
1965 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1966 | intel_crtc = to_intel_crtc(crtc); | |
1967 | if (crtc->enabled) { | |
1968 | enabled++; | |
1969 | if (intel_crtc->plane == 0) { | |
1970 | DRM_DEBUG("plane A (pipe %d) clock: %d\n", | |
1971 | intel_crtc->pipe, crtc->mode.clock); | |
1972 | planea_clock = crtc->mode.clock; | |
1973 | } else { | |
1974 | DRM_DEBUG("plane B (pipe %d) clock: %d\n", | |
1975 | intel_crtc->pipe, crtc->mode.clock); | |
1976 | planeb_clock = crtc->mode.clock; | |
1977 | } | |
1978 | sr_hdisplay = crtc->mode.hdisplay; | |
1979 | sr_clock = crtc->mode.clock; | |
1980 | if (crtc->fb) | |
1981 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1982 | else | |
1983 | pixel_size = 4; /* by default */ | |
1984 | } | |
1985 | } | |
1986 | ||
1987 | if (enabled <= 0) | |
1988 | return; | |
1989 | ||
1990 | /* Single pipe configs can enable self refresh */ | |
1991 | if (enabled == 1 && IS_IGD(dev)) | |
1992 | igd_enable_cxsr(dev, sr_clock, pixel_size); | |
1993 | else if (IS_IGD(dev)) | |
1994 | igd_disable_cxsr(dev); | |
1995 | ||
1996 | if (IS_I965G(dev)) | |
1997 | i965_update_wm(dev); | |
1998 | else if (IS_I9XX(dev) || IS_MOBILE(dev)) | |
1999 | i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, | |
2000 | pixel_size); | |
2001 | else | |
2002 | i830_update_wm(dev, planea_clock, pixel_size); | |
2003 | } | |
2004 | ||
5c3b82e2 CW |
2005 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
2006 | struct drm_display_mode *mode, | |
2007 | struct drm_display_mode *adjusted_mode, | |
2008 | int x, int y, | |
2009 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2010 | { |
2011 | struct drm_device *dev = crtc->dev; | |
2012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2014 | int pipe = intel_crtc->pipe; | |
2015 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; | |
2016 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
2017 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
2018 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
2019 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
2020 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
2021 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
2022 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
2023 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
2024 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
2025 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
2026 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
2027 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
2028 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
43565a06 | 2029 | int refclk, num_outputs = 0; |
79e53945 JB |
2030 | intel_clock_t clock; |
2031 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | |
2032 | bool ok, is_sdvo = false, is_dvo = false; | |
a4fc5ed6 | 2033 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 JB |
2034 | struct drm_mode_config *mode_config = &dev->mode_config; |
2035 | struct drm_connector *connector; | |
d4906093 | 2036 | const intel_limit_t *limit; |
5c3b82e2 | 2037 | int ret; |
2c07245f ZW |
2038 | struct fdi_m_n m_n = {0}; |
2039 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; | |
2040 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; | |
2041 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; | |
2042 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; | |
2043 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; | |
2044 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
2045 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
541998a1 | 2046 | int lvds_reg = LVDS; |
2c07245f ZW |
2047 | u32 temp; |
2048 | int sdvo_pixel_multiply; | |
79e53945 JB |
2049 | |
2050 | drm_vblank_pre_modeset(dev, pipe); | |
2051 | ||
2052 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
2053 | struct intel_output *intel_output = to_intel_output(connector); | |
2054 | ||
2055 | if (!connector->encoder || connector->encoder->crtc != crtc) | |
2056 | continue; | |
2057 | ||
2058 | switch (intel_output->type) { | |
2059 | case INTEL_OUTPUT_LVDS: | |
2060 | is_lvds = true; | |
2061 | break; | |
2062 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 2063 | case INTEL_OUTPUT_HDMI: |
79e53945 | 2064 | is_sdvo = true; |
e2f0ba97 JB |
2065 | if (intel_output->needs_tv_clock) |
2066 | is_tv = true; | |
79e53945 JB |
2067 | break; |
2068 | case INTEL_OUTPUT_DVO: | |
2069 | is_dvo = true; | |
2070 | break; | |
2071 | case INTEL_OUTPUT_TVOUT: | |
2072 | is_tv = true; | |
2073 | break; | |
2074 | case INTEL_OUTPUT_ANALOG: | |
2075 | is_crt = true; | |
2076 | break; | |
a4fc5ed6 KP |
2077 | case INTEL_OUTPUT_DISPLAYPORT: |
2078 | is_dp = true; | |
2079 | break; | |
79e53945 | 2080 | } |
43565a06 KH |
2081 | |
2082 | num_outputs++; | |
79e53945 JB |
2083 | } |
2084 | ||
43565a06 KH |
2085 | if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { |
2086 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
2087 | DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); | |
2088 | } else if (IS_I9XX(dev)) { | |
79e53945 | 2089 | refclk = 96000; |
2c07245f ZW |
2090 | if (IS_IGDNG(dev)) |
2091 | refclk = 120000; /* 120Mhz refclk */ | |
79e53945 JB |
2092 | } else { |
2093 | refclk = 48000; | |
2094 | } | |
a4fc5ed6 | 2095 | |
79e53945 | 2096 | |
d4906093 ML |
2097 | /* |
2098 | * Returns a set of divisors for the desired target clock with the given | |
2099 | * refclk, or FALSE. The returned values represent the clock equation: | |
2100 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
2101 | */ | |
2102 | limit = intel_limit(crtc); | |
2103 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
2104 | if (!ok) { |
2105 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 2106 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 2107 | return -EINVAL; |
79e53945 JB |
2108 | } |
2109 | ||
7026d4ac ZW |
2110 | /* SDVO TV has fixed PLL values depend on its clock range, |
2111 | this mirrors vbios setting. */ | |
2112 | if (is_sdvo && is_tv) { | |
2113 | if (adjusted_mode->clock >= 100000 | |
2114 | && adjusted_mode->clock < 140500) { | |
2115 | clock.p1 = 2; | |
2116 | clock.p2 = 10; | |
2117 | clock.n = 3; | |
2118 | clock.m1 = 16; | |
2119 | clock.m2 = 8; | |
2120 | } else if (adjusted_mode->clock >= 140500 | |
2121 | && adjusted_mode->clock <= 200000) { | |
2122 | clock.p1 = 1; | |
2123 | clock.p2 = 10; | |
2124 | clock.n = 6; | |
2125 | clock.m1 = 12; | |
2126 | clock.m2 = 8; | |
2127 | } | |
2128 | } | |
2129 | ||
2c07245f ZW |
2130 | /* FDI link */ |
2131 | if (IS_IGDNG(dev)) | |
2132 | igdng_compute_m_n(3, 4, /* lane num 4 */ | |
2133 | adjusted_mode->clock, | |
2134 | 270000, /* lane clock */ | |
2135 | &m_n); | |
2136 | ||
2177832f SL |
2137 | if (IS_IGD(dev)) |
2138 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | |
2139 | else | |
2140 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
79e53945 | 2141 | |
2c07245f ZW |
2142 | if (!IS_IGDNG(dev)) |
2143 | dpll = DPLL_VGA_MODE_DIS; | |
2144 | ||
79e53945 JB |
2145 | if (IS_I9XX(dev)) { |
2146 | if (is_lvds) | |
2147 | dpll |= DPLLB_MODE_LVDS; | |
2148 | else | |
2149 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
2150 | if (is_sdvo) { | |
2151 | dpll |= DPLL_DVO_HIGH_SPEED; | |
2c07245f ZW |
2152 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
2153 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
79e53945 | 2154 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
2c07245f ZW |
2155 | else if (IS_IGDNG(dev)) |
2156 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 2157 | } |
a4fc5ed6 KP |
2158 | if (is_dp) |
2159 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 JB |
2160 | |
2161 | /* compute bitmask from p1 value */ | |
2177832f SL |
2162 | if (IS_IGD(dev)) |
2163 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; | |
2c07245f | 2164 | else { |
2177832f | 2165 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f ZW |
2166 | /* also FPA1 */ |
2167 | if (IS_IGDNG(dev)) | |
2168 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2169 | } | |
79e53945 JB |
2170 | switch (clock.p2) { |
2171 | case 5: | |
2172 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
2173 | break; | |
2174 | case 7: | |
2175 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
2176 | break; | |
2177 | case 10: | |
2178 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
2179 | break; | |
2180 | case 14: | |
2181 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
2182 | break; | |
2183 | } | |
2c07245f | 2184 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
2185 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
2186 | } else { | |
2187 | if (is_lvds) { | |
2188 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
2189 | } else { | |
2190 | if (clock.p1 == 2) | |
2191 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
2192 | else | |
2193 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
2194 | if (clock.p2 == 4) | |
2195 | dpll |= PLL_P2_DIVIDE_BY_4; | |
2196 | } | |
2197 | } | |
2198 | ||
43565a06 KH |
2199 | if (is_sdvo && is_tv) |
2200 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
2201 | else if (is_tv) | |
79e53945 | 2202 | /* XXX: just matching BIOS for now */ |
43565a06 | 2203 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 2204 | dpll |= 3; |
43565a06 KH |
2205 | else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) |
2206 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
79e53945 JB |
2207 | else |
2208 | dpll |= PLL_REF_INPUT_DREFCLK; | |
2209 | ||
2210 | /* setup pipeconf */ | |
2211 | pipeconf = I915_READ(pipeconf_reg); | |
2212 | ||
2213 | /* Set up the display plane register */ | |
2214 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
2215 | ||
2c07245f ZW |
2216 | /* IGDNG's plane is forced to pipe, bit 24 is to |
2217 | enable color space conversion */ | |
2218 | if (!IS_IGDNG(dev)) { | |
2219 | if (pipe == 0) | |
2220 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
2221 | else | |
2222 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2223 | } | |
79e53945 JB |
2224 | |
2225 | if (pipe == 0 && !IS_I965G(dev)) { | |
2226 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
2227 | * core speed. | |
2228 | * | |
2229 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
2230 | * pipe == 0 check? | |
2231 | */ | |
2232 | if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) | |
2233 | pipeconf |= PIPEACONF_DOUBLE_WIDE; | |
2234 | else | |
2235 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
2236 | } | |
2237 | ||
2238 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
2239 | pipeconf |= PIPEACONF_ENABLE; | |
2240 | dpll |= DPLL_VCO_ENABLE; | |
2241 | ||
2242 | ||
2243 | /* Disable the panel fitter if it was on our pipe */ | |
2c07245f | 2244 | if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) |
79e53945 JB |
2245 | I915_WRITE(PFIT_CONTROL, 0); |
2246 | ||
2247 | DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
2248 | drm_mode_debug_printmodeline(mode); | |
2249 | ||
2c07245f ZW |
2250 | /* assign to IGDNG registers */ |
2251 | if (IS_IGDNG(dev)) { | |
2252 | fp_reg = pch_fp_reg; | |
2253 | dpll_reg = pch_dpll_reg; | |
2254 | } | |
79e53945 JB |
2255 | |
2256 | if (dpll & DPLL_VCO_ENABLE) { | |
2257 | I915_WRITE(fp_reg, fp); | |
2258 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
2259 | I915_READ(dpll_reg); | |
2260 | udelay(150); | |
2261 | } | |
2262 | ||
2c07245f ZW |
2263 | if (IS_IGDNG(dev)) { |
2264 | /* enable PCH clock reference source */ | |
2265 | /* XXX need to change the setting for other outputs */ | |
2266 | u32 temp; | |
2267 | temp = I915_READ(PCH_DREF_CONTROL); | |
2268 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
2269 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
2270 | temp &= ~DREF_SSC_SOURCE_MASK; | |
2271 | temp |= DREF_SSC_SOURCE_ENABLE; | |
2272 | temp &= ~DREF_SSC1_ENABLE; | |
2273 | /* if no eDP, disable source output to CPU */ | |
2274 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
2275 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
2276 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
2277 | } | |
2278 | ||
79e53945 JB |
2279 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
2280 | * This is an exception to the general rule that mode_set doesn't turn | |
2281 | * things on. | |
2282 | */ | |
2283 | if (is_lvds) { | |
541998a1 | 2284 | u32 lvds; |
79e53945 | 2285 | |
541998a1 ZW |
2286 | if (IS_IGDNG(dev)) |
2287 | lvds_reg = PCH_LVDS; | |
2288 | ||
2289 | lvds = I915_READ(lvds_reg); | |
79e53945 JB |
2290 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; |
2291 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
2292 | * set the DPLLs for dual-channel mode or not. | |
2293 | */ | |
2294 | if (clock.p2 == 7) | |
2295 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
2296 | else | |
2297 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
2298 | ||
2299 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
2300 | * appropriately here, but we need to look more thoroughly into how | |
2301 | * panels behave in the two modes. | |
2302 | */ | |
2303 | ||
541998a1 ZW |
2304 | I915_WRITE(lvds_reg, lvds); |
2305 | I915_READ(lvds_reg); | |
79e53945 | 2306 | } |
a4fc5ed6 KP |
2307 | if (is_dp) |
2308 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
79e53945 JB |
2309 | |
2310 | I915_WRITE(fp_reg, fp); | |
2311 | I915_WRITE(dpll_reg, dpll); | |
2312 | I915_READ(dpll_reg); | |
2313 | /* Wait for the clocks to stabilize. */ | |
2314 | udelay(150); | |
2315 | ||
2c07245f ZW |
2316 | if (IS_I965G(dev) && !IS_IGDNG(dev)) { |
2317 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
79e53945 JB |
2318 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | |
2319 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | |
2320 | } else { | |
2321 | /* write it again -- the BIOS does, after all */ | |
2322 | I915_WRITE(dpll_reg, dpll); | |
2323 | } | |
2324 | I915_READ(dpll_reg); | |
2325 | /* Wait for the clocks to stabilize. */ | |
2326 | udelay(150); | |
2327 | ||
2328 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | | |
2329 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
2330 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
2331 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
2332 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
2333 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
2334 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
2335 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
2336 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
2337 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
2338 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
2339 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
2340 | /* pipesrc and dspsize control the size that is scaled from, which should | |
2341 | * always be the user's requested size. | |
2342 | */ | |
2c07245f ZW |
2343 | if (!IS_IGDNG(dev)) { |
2344 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | | |
2345 | (mode->hdisplay - 1)); | |
2346 | I915_WRITE(dsppos_reg, 0); | |
2347 | } | |
79e53945 | 2348 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
2c07245f ZW |
2349 | |
2350 | if (IS_IGDNG(dev)) { | |
2351 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); | |
2352 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); | |
2353 | I915_WRITE(link_m1_reg, m_n.link_m); | |
2354 | I915_WRITE(link_n1_reg, m_n.link_n); | |
2355 | ||
2356 | /* enable FDI RX PLL too */ | |
2357 | temp = I915_READ(fdi_rx_reg); | |
2358 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); | |
2359 | udelay(200); | |
2360 | } | |
2361 | ||
79e53945 JB |
2362 | I915_WRITE(pipeconf_reg, pipeconf); |
2363 | I915_READ(pipeconf_reg); | |
2364 | ||
2365 | intel_wait_for_vblank(dev); | |
2366 | ||
2367 | I915_WRITE(dspcntr_reg, dspcntr); | |
2368 | ||
2369 | /* Flush the plane changes */ | |
5c3b82e2 | 2370 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
2371 | |
2372 | intel_update_watermarks(dev); | |
2373 | ||
79e53945 | 2374 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 2375 | |
1f803ee5 | 2376 | return ret; |
79e53945 JB |
2377 | } |
2378 | ||
2379 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
2380 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
2381 | { | |
2382 | struct drm_device *dev = crtc->dev; | |
2383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2385 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
2386 | int i; | |
2387 | ||
2388 | /* The clocks have to be on to load the palette. */ | |
2389 | if (!crtc->enabled) | |
2390 | return; | |
2391 | ||
2c07245f ZW |
2392 | /* use legacy palette for IGDNG */ |
2393 | if (IS_IGDNG(dev)) | |
2394 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : | |
2395 | LGC_PALETTE_B; | |
2396 | ||
79e53945 JB |
2397 | for (i = 0; i < 256; i++) { |
2398 | I915_WRITE(palreg + 4 * i, | |
2399 | (intel_crtc->lut_r[i] << 16) | | |
2400 | (intel_crtc->lut_g[i] << 8) | | |
2401 | intel_crtc->lut_b[i]); | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, | |
2406 | struct drm_file *file_priv, | |
2407 | uint32_t handle, | |
2408 | uint32_t width, uint32_t height) | |
2409 | { | |
2410 | struct drm_device *dev = crtc->dev; | |
2411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2413 | struct drm_gem_object *bo; | |
2414 | struct drm_i915_gem_object *obj_priv; | |
2415 | int pipe = intel_crtc->pipe; | |
2416 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
2417 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
14b60391 | 2418 | uint32_t temp = I915_READ(control); |
79e53945 | 2419 | size_t addr; |
3f8bc370 | 2420 | int ret; |
79e53945 JB |
2421 | |
2422 | DRM_DEBUG("\n"); | |
2423 | ||
2424 | /* if we want to turn off the cursor ignore width and height */ | |
2425 | if (!handle) { | |
2426 | DRM_DEBUG("cursor off\n"); | |
14b60391 JB |
2427 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
2428 | temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
2429 | temp |= CURSOR_MODE_DISABLE; | |
2430 | } else { | |
2431 | temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
2432 | } | |
3f8bc370 KH |
2433 | addr = 0; |
2434 | bo = NULL; | |
5004417d | 2435 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 2436 | goto finish; |
79e53945 JB |
2437 | } |
2438 | ||
2439 | /* Currently we only support 64x64 cursors */ | |
2440 | if (width != 64 || height != 64) { | |
2441 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
2442 | return -EINVAL; | |
2443 | } | |
2444 | ||
2445 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
2446 | if (!bo) | |
2447 | return -ENOENT; | |
2448 | ||
2449 | obj_priv = bo->driver_private; | |
2450 | ||
2451 | if (bo->size < width * height * 4) { | |
2452 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
2453 | ret = -ENOMEM; |
2454 | goto fail; | |
79e53945 JB |
2455 | } |
2456 | ||
71acb5eb | 2457 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 2458 | mutex_lock(&dev->struct_mutex); |
71acb5eb DA |
2459 | if (!dev_priv->cursor_needs_physical) { |
2460 | ret = i915_gem_object_pin(bo, PAGE_SIZE); | |
2461 | if (ret) { | |
2462 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 2463 | goto fail_locked; |
71acb5eb | 2464 | } |
79e53945 | 2465 | addr = obj_priv->gtt_offset; |
71acb5eb DA |
2466 | } else { |
2467 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); | |
2468 | if (ret) { | |
2469 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 2470 | goto fail_locked; |
71acb5eb DA |
2471 | } |
2472 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
2473 | } |
2474 | ||
14b60391 JB |
2475 | if (!IS_I9XX(dev)) |
2476 | I915_WRITE(CURSIZE, (height << 12) | width); | |
2477 | ||
2478 | /* Hooray for CUR*CNTR differences */ | |
2479 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { | |
2480 | temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
2481 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
2482 | temp |= (pipe << 28); /* Connect to correct pipe */ | |
2483 | } else { | |
2484 | temp &= ~(CURSOR_FORMAT_MASK); | |
2485 | temp |= CURSOR_ENABLE; | |
2486 | temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; | |
2487 | } | |
79e53945 | 2488 | |
3f8bc370 | 2489 | finish: |
79e53945 JB |
2490 | I915_WRITE(control, temp); |
2491 | I915_WRITE(base, addr); | |
2492 | ||
3f8bc370 | 2493 | if (intel_crtc->cursor_bo) { |
71acb5eb DA |
2494 | if (dev_priv->cursor_needs_physical) { |
2495 | if (intel_crtc->cursor_bo != bo) | |
2496 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
2497 | } else | |
2498 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
2499 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
2500 | } | |
7f9872e0 | 2501 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
2502 | |
2503 | intel_crtc->cursor_addr = addr; | |
2504 | intel_crtc->cursor_bo = bo; | |
2505 | ||
79e53945 | 2506 | return 0; |
34b8686e DA |
2507 | fail: |
2508 | mutex_lock(&dev->struct_mutex); | |
7f9872e0 | 2509 | fail_locked: |
34b8686e DA |
2510 | drm_gem_object_unreference(bo); |
2511 | mutex_unlock(&dev->struct_mutex); | |
2512 | return ret; | |
79e53945 JB |
2513 | } |
2514 | ||
2515 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
2516 | { | |
2517 | struct drm_device *dev = crtc->dev; | |
2518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2519 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2520 | int pipe = intel_crtc->pipe; | |
2521 | uint32_t temp = 0; | |
2522 | uint32_t adder; | |
2523 | ||
2524 | if (x < 0) { | |
2245fda8 | 2525 | temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
79e53945 JB |
2526 | x = -x; |
2527 | } | |
2528 | if (y < 0) { | |
2245fda8 | 2529 | temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
79e53945 JB |
2530 | y = -y; |
2531 | } | |
2532 | ||
2245fda8 KP |
2533 | temp |= x << CURSOR_X_SHIFT; |
2534 | temp |= y << CURSOR_Y_SHIFT; | |
79e53945 JB |
2535 | |
2536 | adder = intel_crtc->cursor_addr; | |
2537 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
2538 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
2543 | /** Sets the color ramps on behalf of RandR */ | |
2544 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
2545 | u16 blue, int regno) | |
2546 | { | |
2547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2548 | ||
2549 | intel_crtc->lut_r[regno] = red >> 8; | |
2550 | intel_crtc->lut_g[regno] = green >> 8; | |
2551 | intel_crtc->lut_b[regno] = blue >> 8; | |
2552 | } | |
2553 | ||
2554 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
2555 | u16 *blue, uint32_t size) | |
2556 | { | |
2557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2558 | int i; | |
2559 | ||
2560 | if (size != 256) | |
2561 | return; | |
2562 | ||
2563 | for (i = 0; i < 256; i++) { | |
2564 | intel_crtc->lut_r[i] = red[i] >> 8; | |
2565 | intel_crtc->lut_g[i] = green[i] >> 8; | |
2566 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
2567 | } | |
2568 | ||
2569 | intel_crtc_load_lut(crtc); | |
2570 | } | |
2571 | ||
2572 | /** | |
2573 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
2574 | * detection. | |
2575 | * | |
2576 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
2577 | * its requirements. The pipe will be connected to no other outputs. | |
2578 | * | |
2579 | * Currently this code will only succeed if there is a pipe with no outputs | |
2580 | * configured for it. In the future, it could choose to temporarily disable | |
2581 | * some outputs to free up a pipe for its use. | |
2582 | * | |
2583 | * \return crtc, or NULL if no pipes are available. | |
2584 | */ | |
2585 | ||
2586 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
2587 | static struct drm_display_mode load_detect_mode = { | |
2588 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
2589 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
2590 | }; | |
2591 | ||
2592 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, | |
2593 | struct drm_display_mode *mode, | |
2594 | int *dpms_mode) | |
2595 | { | |
2596 | struct intel_crtc *intel_crtc; | |
2597 | struct drm_crtc *possible_crtc; | |
2598 | struct drm_crtc *supported_crtc =NULL; | |
2599 | struct drm_encoder *encoder = &intel_output->enc; | |
2600 | struct drm_crtc *crtc = NULL; | |
2601 | struct drm_device *dev = encoder->dev; | |
2602 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2603 | struct drm_crtc_helper_funcs *crtc_funcs; | |
2604 | int i = -1; | |
2605 | ||
2606 | /* | |
2607 | * Algorithm gets a little messy: | |
2608 | * - if the connector already has an assigned crtc, use it (but make | |
2609 | * sure it's on first) | |
2610 | * - try to find the first unused crtc that can drive this connector, | |
2611 | * and use that if we find one | |
2612 | * - if there are no unused crtcs available, try to use the first | |
2613 | * one we found that supports the connector | |
2614 | */ | |
2615 | ||
2616 | /* See if we already have a CRTC for this connector */ | |
2617 | if (encoder->crtc) { | |
2618 | crtc = encoder->crtc; | |
2619 | /* Make sure the crtc and connector are running */ | |
2620 | intel_crtc = to_intel_crtc(crtc); | |
2621 | *dpms_mode = intel_crtc->dpms_mode; | |
2622 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2623 | crtc_funcs = crtc->helper_private; | |
2624 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2625 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2626 | } | |
2627 | return crtc; | |
2628 | } | |
2629 | ||
2630 | /* Find an unused one (if possible) */ | |
2631 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
2632 | i++; | |
2633 | if (!(encoder->possible_crtcs & (1 << i))) | |
2634 | continue; | |
2635 | if (!possible_crtc->enabled) { | |
2636 | crtc = possible_crtc; | |
2637 | break; | |
2638 | } | |
2639 | if (!supported_crtc) | |
2640 | supported_crtc = possible_crtc; | |
2641 | } | |
2642 | ||
2643 | /* | |
2644 | * If we didn't find an unused CRTC, don't use any. | |
2645 | */ | |
2646 | if (!crtc) { | |
2647 | return NULL; | |
2648 | } | |
2649 | ||
2650 | encoder->crtc = crtc; | |
03d60699 | 2651 | intel_output->base.encoder = encoder; |
79e53945 JB |
2652 | intel_output->load_detect_temp = true; |
2653 | ||
2654 | intel_crtc = to_intel_crtc(crtc); | |
2655 | *dpms_mode = intel_crtc->dpms_mode; | |
2656 | ||
2657 | if (!crtc->enabled) { | |
2658 | if (!mode) | |
2659 | mode = &load_detect_mode; | |
3c4fdcfb | 2660 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
2661 | } else { |
2662 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2663 | crtc_funcs = crtc->helper_private; | |
2664 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2665 | } | |
2666 | ||
2667 | /* Add this connector to the crtc */ | |
2668 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
2669 | encoder_funcs->commit(encoder); | |
2670 | } | |
2671 | /* let the connector get through one full cycle before testing */ | |
2672 | intel_wait_for_vblank(dev); | |
2673 | ||
2674 | return crtc; | |
2675 | } | |
2676 | ||
2677 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) | |
2678 | { | |
2679 | struct drm_encoder *encoder = &intel_output->enc; | |
2680 | struct drm_device *dev = encoder->dev; | |
2681 | struct drm_crtc *crtc = encoder->crtc; | |
2682 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2683 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2684 | ||
2685 | if (intel_output->load_detect_temp) { | |
2686 | encoder->crtc = NULL; | |
03d60699 | 2687 | intel_output->base.encoder = NULL; |
79e53945 JB |
2688 | intel_output->load_detect_temp = false; |
2689 | crtc->enabled = drm_helper_crtc_in_use(crtc); | |
2690 | drm_helper_disable_unused_functions(dev); | |
2691 | } | |
2692 | ||
2693 | /* Switch crtc and output back off if necessary */ | |
2694 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { | |
2695 | if (encoder->crtc == crtc) | |
2696 | encoder_funcs->dpms(encoder, dpms_mode); | |
2697 | crtc_funcs->dpms(crtc, dpms_mode); | |
2698 | } | |
2699 | } | |
2700 | ||
2701 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
2702 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
2703 | { | |
2704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2706 | int pipe = intel_crtc->pipe; | |
2707 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
2708 | u32 fp; | |
2709 | intel_clock_t clock; | |
2710 | ||
2711 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
2712 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
2713 | else | |
2714 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
2715 | ||
2716 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
2177832f SL |
2717 | if (IS_IGD(dev)) { |
2718 | clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
2719 | clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2720 | } else { | |
2721 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
2722 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2723 | } | |
2724 | ||
79e53945 | 2725 | if (IS_I9XX(dev)) { |
2177832f SL |
2726 | if (IS_IGD(dev)) |
2727 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> | |
2728 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); | |
2729 | else | |
2730 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
2731 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
2732 | ||
2733 | switch (dpll & DPLL_MODE_MASK) { | |
2734 | case DPLLB_MODE_DAC_SERIAL: | |
2735 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
2736 | 5 : 10; | |
2737 | break; | |
2738 | case DPLLB_MODE_LVDS: | |
2739 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
2740 | 7 : 14; | |
2741 | break; | |
2742 | default: | |
2743 | DRM_DEBUG("Unknown DPLL mode %08x in programmed " | |
2744 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
2745 | return 0; | |
2746 | } | |
2747 | ||
2748 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 2749 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
2750 | } else { |
2751 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
2752 | ||
2753 | if (is_lvds) { | |
2754 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
2755 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
2756 | clock.p2 = 14; | |
2757 | ||
2758 | if ((dpll & PLL_REF_INPUT_MASK) == | |
2759 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
2760 | /* XXX: might not be 66MHz */ | |
2177832f | 2761 | intel_clock(dev, 66000, &clock); |
79e53945 | 2762 | } else |
2177832f | 2763 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2764 | } else { |
2765 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
2766 | clock.p1 = 2; | |
2767 | else { | |
2768 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
2769 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
2770 | } | |
2771 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
2772 | clock.p2 = 4; | |
2773 | else | |
2774 | clock.p2 = 2; | |
2775 | ||
2177832f | 2776 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2777 | } |
2778 | } | |
2779 | ||
2780 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
2781 | * i830PllIsValid() because it relies on the xf86_config connector | |
2782 | * configuration being accurate, which it isn't necessarily. | |
2783 | */ | |
2784 | ||
2785 | return clock.dot; | |
2786 | } | |
2787 | ||
2788 | /** Returns the currently programmed mode of the given pipe. */ | |
2789 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
2790 | struct drm_crtc *crtc) | |
2791 | { | |
2792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2794 | int pipe = intel_crtc->pipe; | |
2795 | struct drm_display_mode *mode; | |
2796 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
2797 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
2798 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
2799 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
2800 | ||
2801 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
2802 | if (!mode) | |
2803 | return NULL; | |
2804 | ||
2805 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
2806 | mode->hdisplay = (htot & 0xffff) + 1; | |
2807 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
2808 | mode->hsync_start = (hsync & 0xffff) + 1; | |
2809 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
2810 | mode->vdisplay = (vtot & 0xffff) + 1; | |
2811 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
2812 | mode->vsync_start = (vsync & 0xffff) + 1; | |
2813 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
2814 | ||
2815 | drm_mode_set_name(mode); | |
2816 | drm_mode_set_crtcinfo(mode, 0); | |
2817 | ||
2818 | return mode; | |
2819 | } | |
2820 | ||
2821 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
2822 | { | |
2823 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2824 | ||
7ff14559 DA |
2825 | if (intel_crtc->mode_set.mode) |
2826 | drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode); | |
79e53945 JB |
2827 | drm_crtc_cleanup(crtc); |
2828 | kfree(intel_crtc); | |
2829 | } | |
2830 | ||
2831 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
2832 | .dpms = intel_crtc_dpms, | |
2833 | .mode_fixup = intel_crtc_mode_fixup, | |
2834 | .mode_set = intel_crtc_mode_set, | |
2835 | .mode_set_base = intel_pipe_set_base, | |
2836 | .prepare = intel_crtc_prepare, | |
2837 | .commit = intel_crtc_commit, | |
2838 | }; | |
2839 | ||
2840 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
2841 | .cursor_set = intel_crtc_cursor_set, | |
2842 | .cursor_move = intel_crtc_cursor_move, | |
2843 | .gamma_set = intel_crtc_gamma_set, | |
2844 | .set_config = drm_crtc_helper_set_config, | |
2845 | .destroy = intel_crtc_destroy, | |
2846 | }; | |
2847 | ||
2848 | ||
b358d0a6 | 2849 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 JB |
2850 | { |
2851 | struct intel_crtc *intel_crtc; | |
2852 | int i; | |
2853 | ||
2854 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
2855 | if (intel_crtc == NULL) | |
2856 | return; | |
2857 | ||
2858 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
2859 | ||
2860 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
2861 | intel_crtc->pipe = pipe; | |
7662c8bd | 2862 | intel_crtc->plane = pipe; |
79e53945 JB |
2863 | for (i = 0; i < 256; i++) { |
2864 | intel_crtc->lut_r[i] = i; | |
2865 | intel_crtc->lut_g[i] = i; | |
2866 | intel_crtc->lut_b[i] = i; | |
2867 | } | |
2868 | ||
2869 | intel_crtc->cursor_addr = 0; | |
2870 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
2871 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
2872 | ||
2873 | intel_crtc->mode_set.crtc = &intel_crtc->base; | |
2874 | intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); | |
2875 | intel_crtc->mode_set.num_connectors = 0; | |
2876 | ||
2877 | if (i915_fbpercrtc) { | |
2878 | ||
2879 | ||
2880 | ||
2881 | } | |
2882 | } | |
2883 | ||
08d7b3d1 CW |
2884 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
2885 | struct drm_file *file_priv) | |
2886 | { | |
2887 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2888 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
2889 | struct drm_crtc *crtc = NULL; | |
2890 | int pipe = -1; | |
2891 | ||
2892 | if (!dev_priv) { | |
2893 | DRM_ERROR("called with no initialization\n"); | |
2894 | return -EINVAL; | |
2895 | } | |
2896 | ||
2897 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2899 | if (crtc->base.id == pipe_from_crtc_id->crtc_id) { | |
2900 | pipe = intel_crtc->pipe; | |
2901 | break; | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | if (pipe == -1) { | |
2906 | DRM_ERROR("no such CRTC id\n"); | |
2907 | return -EINVAL; | |
2908 | } | |
2909 | ||
2910 | pipe_from_crtc_id->pipe = pipe; | |
2911 | ||
2912 | return 0; | |
2913 | } | |
2914 | ||
79e53945 JB |
2915 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
2916 | { | |
2917 | struct drm_crtc *crtc = NULL; | |
2918 | ||
2919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2921 | if (intel_crtc->pipe == pipe) | |
2922 | break; | |
2923 | } | |
2924 | return crtc; | |
2925 | } | |
2926 | ||
b358d0a6 | 2927 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
79e53945 JB |
2928 | { |
2929 | int index_mask = 0; | |
2930 | struct drm_connector *connector; | |
2931 | int entry = 0; | |
2932 | ||
2933 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2934 | struct intel_output *intel_output = to_intel_output(connector); | |
2935 | if (type_mask & (1 << intel_output->type)) | |
2936 | index_mask |= (1 << entry); | |
2937 | entry++; | |
2938 | } | |
2939 | return index_mask; | |
2940 | } | |
2941 | ||
2942 | ||
2943 | static void intel_setup_outputs(struct drm_device *dev) | |
2944 | { | |
725e30ad | 2945 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
2946 | struct drm_connector *connector; |
2947 | ||
2948 | intel_crt_init(dev); | |
2949 | ||
2950 | /* Set up integrated LVDS */ | |
541998a1 | 2951 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
79e53945 JB |
2952 | intel_lvds_init(dev); |
2953 | ||
2c07245f | 2954 | if (IS_IGDNG(dev)) { |
30ad48b7 ZW |
2955 | int found; |
2956 | ||
2957 | if (I915_READ(HDMIB) & PORT_DETECTED) { | |
2958 | /* check SDVOB */ | |
2959 | /* found = intel_sdvo_init(dev, HDMIB); */ | |
2960 | found = 0; | |
2961 | if (!found) | |
2962 | intel_hdmi_init(dev, HDMIB); | |
2963 | } | |
2964 | ||
2965 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
2966 | intel_hdmi_init(dev, HDMIC); | |
2967 | ||
2968 | if (I915_READ(HDMID) & PORT_DETECTED) | |
2969 | intel_hdmi_init(dev, HDMID); | |
2970 | ||
2c07245f | 2971 | } else if (IS_I9XX(dev)) { |
7d57382e | 2972 | int found; |
13520b05 | 2973 | u32 reg; |
7d57382e | 2974 | |
725e30ad EA |
2975 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
2976 | found = intel_sdvo_init(dev, SDVOB); | |
2977 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
2978 | intel_hdmi_init(dev, SDVOB); | |
a4fc5ed6 KP |
2979 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
2980 | intel_dp_init(dev, DP_B); | |
725e30ad | 2981 | } |
13520b05 KH |
2982 | |
2983 | /* Before G4X SDVOC doesn't have its own detect register */ | |
2984 | if (IS_G4X(dev)) | |
2985 | reg = SDVOC; | |
2986 | else | |
2987 | reg = SDVOB; | |
2988 | ||
2989 | if (I915_READ(reg) & SDVO_DETECTED) { | |
725e30ad EA |
2990 | found = intel_sdvo_init(dev, SDVOC); |
2991 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
2992 | intel_hdmi_init(dev, SDVOC); | |
a4fc5ed6 KP |
2993 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
2994 | intel_dp_init(dev, DP_C); | |
725e30ad | 2995 | } |
a4fc5ed6 KP |
2996 | if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) |
2997 | intel_dp_init(dev, DP_D); | |
79e53945 JB |
2998 | } else |
2999 | intel_dvo_init(dev); | |
3000 | ||
2c07245f | 3001 | if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
3002 | intel_tv_init(dev); |
3003 | ||
3004 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3005 | struct intel_output *intel_output = to_intel_output(connector); | |
3006 | struct drm_encoder *encoder = &intel_output->enc; | |
3007 | int crtc_mask = 0, clone_mask = 0; | |
3008 | ||
3009 | /* valid crtcs */ | |
3010 | switch(intel_output->type) { | |
7d57382e EA |
3011 | case INTEL_OUTPUT_HDMI: |
3012 | crtc_mask = ((1 << 0)| | |
3013 | (1 << 1)); | |
3014 | clone_mask = ((1 << INTEL_OUTPUT_HDMI)); | |
3015 | break; | |
79e53945 JB |
3016 | case INTEL_OUTPUT_DVO: |
3017 | case INTEL_OUTPUT_SDVO: | |
3018 | crtc_mask = ((1 << 0)| | |
3019 | (1 << 1)); | |
3020 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
3021 | (1 << INTEL_OUTPUT_DVO) | | |
3022 | (1 << INTEL_OUTPUT_SDVO)); | |
3023 | break; | |
3024 | case INTEL_OUTPUT_ANALOG: | |
3025 | crtc_mask = ((1 << 0)| | |
3026 | (1 << 1)); | |
3027 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
3028 | (1 << INTEL_OUTPUT_DVO) | | |
3029 | (1 << INTEL_OUTPUT_SDVO)); | |
3030 | break; | |
3031 | case INTEL_OUTPUT_LVDS: | |
3032 | crtc_mask = (1 << 1); | |
3033 | clone_mask = (1 << INTEL_OUTPUT_LVDS); | |
3034 | break; | |
3035 | case INTEL_OUTPUT_TVOUT: | |
3036 | crtc_mask = ((1 << 0) | | |
3037 | (1 << 1)); | |
3038 | clone_mask = (1 << INTEL_OUTPUT_TVOUT); | |
3039 | break; | |
a4fc5ed6 KP |
3040 | case INTEL_OUTPUT_DISPLAYPORT: |
3041 | crtc_mask = ((1 << 0) | | |
3042 | (1 << 1)); | |
3043 | clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT); | |
3044 | break; | |
79e53945 JB |
3045 | } |
3046 | encoder->possible_crtcs = crtc_mask; | |
3047 | encoder->possible_clones = intel_connector_clones(dev, clone_mask); | |
3048 | } | |
3049 | } | |
3050 | ||
3051 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
3052 | { | |
3053 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
3054 | struct drm_device *dev = fb->dev; | |
3055 | ||
3056 | if (fb->fbdev) | |
3057 | intelfb_remove(dev, fb); | |
3058 | ||
3059 | drm_framebuffer_cleanup(fb); | |
3060 | mutex_lock(&dev->struct_mutex); | |
3061 | drm_gem_object_unreference(intel_fb->obj); | |
3062 | mutex_unlock(&dev->struct_mutex); | |
3063 | ||
3064 | kfree(intel_fb); | |
3065 | } | |
3066 | ||
3067 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
3068 | struct drm_file *file_priv, | |
3069 | unsigned int *handle) | |
3070 | { | |
3071 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
3072 | struct drm_gem_object *object = intel_fb->obj; | |
3073 | ||
3074 | return drm_gem_handle_create(file_priv, object, handle); | |
3075 | } | |
3076 | ||
3077 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
3078 | .destroy = intel_user_framebuffer_destroy, | |
3079 | .create_handle = intel_user_framebuffer_create_handle, | |
3080 | }; | |
3081 | ||
3082 | int intel_framebuffer_create(struct drm_device *dev, | |
3083 | struct drm_mode_fb_cmd *mode_cmd, | |
3084 | struct drm_framebuffer **fb, | |
3085 | struct drm_gem_object *obj) | |
3086 | { | |
3087 | struct intel_framebuffer *intel_fb; | |
3088 | int ret; | |
3089 | ||
3090 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
3091 | if (!intel_fb) | |
3092 | return -ENOMEM; | |
3093 | ||
3094 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
3095 | if (ret) { | |
3096 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
3097 | return ret; | |
3098 | } | |
3099 | ||
3100 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
3101 | ||
3102 | intel_fb->obj = obj; | |
3103 | ||
3104 | *fb = &intel_fb->base; | |
3105 | ||
3106 | return 0; | |
3107 | } | |
3108 | ||
3109 | ||
3110 | static struct drm_framebuffer * | |
3111 | intel_user_framebuffer_create(struct drm_device *dev, | |
3112 | struct drm_file *filp, | |
3113 | struct drm_mode_fb_cmd *mode_cmd) | |
3114 | { | |
3115 | struct drm_gem_object *obj; | |
3116 | struct drm_framebuffer *fb; | |
3117 | int ret; | |
3118 | ||
3119 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
3120 | if (!obj) | |
3121 | return NULL; | |
3122 | ||
3123 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); | |
3124 | if (ret) { | |
496818f0 | 3125 | mutex_lock(&dev->struct_mutex); |
79e53945 | 3126 | drm_gem_object_unreference(obj); |
496818f0 | 3127 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
3128 | return NULL; |
3129 | } | |
3130 | ||
3131 | return fb; | |
3132 | } | |
3133 | ||
79e53945 | 3134 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 JB |
3135 | .fb_create = intel_user_framebuffer_create, |
3136 | .fb_changed = intelfb_probe, | |
3137 | }; | |
3138 | ||
3139 | void intel_modeset_init(struct drm_device *dev) | |
3140 | { | |
3141 | int num_pipe; | |
3142 | int i; | |
3143 | ||
3144 | drm_mode_config_init(dev); | |
3145 | ||
3146 | dev->mode_config.min_width = 0; | |
3147 | dev->mode_config.min_height = 0; | |
3148 | ||
3149 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
3150 | ||
3151 | if (IS_I965G(dev)) { | |
3152 | dev->mode_config.max_width = 8192; | |
3153 | dev->mode_config.max_height = 8192; | |
3154 | } else { | |
3155 | dev->mode_config.max_width = 2048; | |
3156 | dev->mode_config.max_height = 2048; | |
3157 | } | |
3158 | ||
3159 | /* set memory base */ | |
3160 | if (IS_I9XX(dev)) | |
3161 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
3162 | else | |
3163 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
3164 | ||
3165 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
3166 | num_pipe = 2; | |
3167 | else | |
3168 | num_pipe = 1; | |
3169 | DRM_DEBUG("%d display pipe%s available.\n", | |
3170 | num_pipe, num_pipe > 1 ? "s" : ""); | |
3171 | ||
3172 | for (i = 0; i < num_pipe; i++) { | |
3173 | intel_crtc_init(dev, i); | |
3174 | } | |
3175 | ||
3176 | intel_setup_outputs(dev); | |
3177 | } | |
3178 | ||
3179 | void intel_modeset_cleanup(struct drm_device *dev) | |
3180 | { | |
3181 | drm_mode_config_cleanup(dev); | |
3182 | } | |
3183 | ||
3184 | ||
3185 | /* current intel driver doesn't take advantage of encoders | |
3186 | always give back the encoder for the connector | |
3187 | */ | |
3188 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
3189 | { | |
3190 | struct intel_output *intel_output = to_intel_output(connector); | |
3191 | ||
3192 | return &intel_output->enc; | |
3193 | } |