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drm/i915: Move gtt_mtrr to i915_gtt
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
79e53945
JB		 490{
491 struct drm_device *dev = crtc->dev;
79e53945 492 intel_clock_t clock;
79e53945
JB		 493 int err = target;
494
a210b028 495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 496 /*
a210b028
DV		 497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
79e53945 500 */
1974cad0 501 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
0206e353 512 memset(best_clock, 0, sizeof(*best_clock));
79e53945 513
42158660
ZY		 514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
42158660
ZY		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 524 int this_err;
525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
55607e8a
DV		 895void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
b24e7179
JB		 897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
b24e7179 909
55607e8a 910struct intel_shared_dpll *
e2b78267
DV		 911intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
912{
913 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
914
a43f6e0f 915 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 916 return NULL;
917
a43f6e0f 918 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 919}
920
040484af 921/* For ILK+ */
55607e8a
DV		 922void assert_shared_dpll(struct drm_i915_private *dev_priv,
923 struct intel_shared_dpll *pll,
924 bool state)
040484af 925{
040484af 926 bool cur_state;
5358901f 927 struct intel_dpll_hw_state hw_state;
040484af 928
9d82aa17
ED		 929 if (HAS_PCH_LPT(dev_priv->dev)) {
930 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
931 return;
932 }
933
92b27b08 934 if (WARN (!pll,
46edb027 935 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 936 return;
ee7b9f93 937
5358901f 938 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 939 WARN(cur_state != state,
5358901f
DV		 940 "%s assertion failure (expected %s, current %s)\n",
941 pll->name, state_string(state), state_string(cur_state));
040484af 942}
040484af
JB		 943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
ad80a810
PZ		 950 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
951 pipe);
040484af 952
affa9354
PZ		 953 if (HAS_DDI(dev_priv->dev)) {
954 /* DDI does not have a specific FDI_TX register */
ad80a810 955 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 956 val = I915_READ(reg);
ad80a810 957 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 958 } else {
959 reg = FDI_TX_CTL(pipe);
960 val = I915_READ(reg);
961 cur_state = !!(val & FDI_TX_ENABLE);
962 }
040484af
JB		 963 WARN(cur_state != state,
964 "FDI TX state assertion failure (expected %s, current %s)\n",
965 state_string(state), state_string(cur_state));
966}
967#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
968#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
969
970static void assert_fdi_rx(struct drm_i915_private *dev_priv,
971 enum pipe pipe, bool state)
972{
973 int reg;
974 u32 val;
975 bool cur_state;
976
d63fa0dc
PZ		 977 reg = FDI_RX_CTL(pipe);
978 val = I915_READ(reg);
979 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 980 WARN(cur_state != state,
981 "FDI RX state assertion failure (expected %s, current %s)\n",
982 state_string(state), state_string(cur_state));
983}
984#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
985#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
986
987static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
988 enum pipe pipe)
989{
990 int reg;
991 u32 val;
992
993 /* ILK FDI PLL is always enabled */
994 if (dev_priv->info->gen == 5)
995 return;
996
bf507ef7 997 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 998 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 999 return;
1000
040484af
JB		 1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004}
1005
55607e8a
DV		 1006void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007 enum pipe pipe, bool state)
040484af
JB		 1008{
1009 int reg;
1010 u32 val;
55607e8a 1011 bool cur_state;
040484af
JB		 1012
1013 reg = FDI_RX_CTL(pipe);
1014 val = I915_READ(reg);
55607e8a
DV		 1015 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016 WARN(cur_state != state,
1017 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018 state_string(state), state_string(cur_state));
040484af
JB		 1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
19332d7a 1142 val = I915_READ(reg);
20674eef 1143 WARN((val & SPRITE_ENABLE),
06da8da2 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
87442f73
DV		 1304static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305{
1306 int reg;
1307 u32 val;
1308
1309 assert_pipe_disabled(dev_priv, pipe);
1310
1311 /* No really, not for ILK+ */
1312 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314 /* PLL is protected by panel, make sure we can write it */
1315 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316 assert_panel_unlocked(dev_priv, pipe);
1317
1318 reg = DPLL(pipe);
1319 val = I915_READ(reg);
1320 val |= DPLL_VCO_ENABLE;
1321
1322 /* We do this three times for luck */
1323 I915_WRITE(reg, val);
1324 POSTING_READ(reg);
1325 udelay(150); /* wait for warmup */
1326 I915_WRITE(reg, val);
1327 POSTING_READ(reg);
1328 udelay(150); /* wait for warmup */
1329 I915_WRITE(reg, val);
1330 POSTING_READ(reg);
1331 udelay(150); /* wait for warmup */
1332}
1333
66e3d5c0 1334static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1335{
66e3d5c0
DV		 1336 struct drm_device *dev = crtc->base.dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int reg = DPLL(crtc->pipe);
1339 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1340
66e3d5c0 1341 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1342
63d7bbe9 1343 /* No really, not for ILK+ */
87442f73 1344 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1345
1346 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1347 if (IS_MOBILE(dev) && !IS_I830(dev))
1348 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1349
66e3d5c0
DV		 1350 I915_WRITE(reg, dpll);
1351
1352 /* Wait for the clocks to stabilize. */
1353 POSTING_READ(reg);
1354 udelay(150);
1355
1356 if (INTEL_INFO(dev)->gen >= 4) {
1357 I915_WRITE(DPLL_MD(crtc->pipe),
1358 crtc->config.dpll_hw_state.dpll_md);
1359 } else {
1360 /* The pixel multiplier can only be updated once the
1361 * DPLL is enabled and the clocks are stable.
1362 *
1363 * So write it again.
1364 */
1365 I915_WRITE(reg, dpll);
1366 }
63d7bbe9
JB		 1367
1368 /* We do this three times for luck */
66e3d5c0 1369 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1370 POSTING_READ(reg);
1371 udelay(150); /* wait for warmup */
66e3d5c0 1372 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1373 POSTING_READ(reg);
1374 udelay(150); /* wait for warmup */
66e3d5c0 1375 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1376 POSTING_READ(reg);
1377 udelay(150); /* wait for warmup */
1378}
1379
1380/**
1381 * intel_disable_pll - disable a PLL
1382 * @dev_priv: i915 private structure
1383 * @pipe: pipe PLL to disable
1384 *
1385 * Disable the PLL for @pipe, making sure the pipe is off first.
1386 *
1387 * Note! This is for pre-ILK only.
1388 */
1389static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1390{
1391 int reg;
1392 u32 val;
1393
1394 /* Don't disable pipe A or pipe A PLLs if needed */
1395 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1396 return;
1397
1398 /* Make sure the pipe isn't still relying on us */
1399 assert_pipe_disabled(dev_priv, pipe);
1400
1401 reg = DPLL(pipe);
1402 val = I915_READ(reg);
1403 val &= ~DPLL_VCO_ENABLE;
1404 I915_WRITE(reg, val);
1405 POSTING_READ(reg);
1406}
1407
89b667f8
JB		 1408void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1409{
1410 u32 port_mask;
1411
1412 if (!port)
1413 port_mask = DPLL_PORTB_READY_MASK;
1414 else
1415 port_mask = DPLL_PORTC_READY_MASK;
1416
1417 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1418 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1419 'B' + port, I915_READ(DPLL(0)));
1420}
1421
92f2584a 1422/**
e72f9fbf 1423 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1428 * drives the transcoder clock.
1429 */
e2b78267 1430static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1431{
e2b78267
DV		 1432 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1433 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1434
48da64a8 1435 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1436 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1437 if (WARN_ON(pll == NULL))
48da64a8
CW		 1438 return;
1439
1440 if (WARN_ON(pll->refcount == 0))
1441 return;
ee7b9f93 1442
46edb027
DV		 1443 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1444 pll->name, pll->active, pll->on,
e2b78267 1445 crtc->base.base.id);
92f2584a 1446
cdbd2316
DV		 1447 if (pll->active++) {
1448 WARN_ON(!pll->on);
e9d6944e 1449 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1450 return;
1451 }
f4a091c7 1452 WARN_ON(pll->on);
ee7b9f93 1453
46edb027 1454 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1455 pll->enable(dev_priv, pll);
ee7b9f93 1456 pll->on = true;
92f2584a
JB		 1457}
1458
e2b78267 1459static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1460{
e2b78267
DV		 1461 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1462 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1463
92f2584a
JB		 1464 /* PCH only available on ILK+ */
1465 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1466 if (WARN_ON(pll == NULL))
ee7b9f93 1467 return;
92f2584a 1468
48da64a8
CW		 1469 if (WARN_ON(pll->refcount == 0))
1470 return;
7a419866 1471
46edb027
DV		 1472 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1473 pll->name, pll->active, pll->on,
e2b78267 1474 crtc->base.base.id);
7a419866 1475
48da64a8 1476 if (WARN_ON(pll->active == 0)) {
e9d6944e 1477 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1478 return;
1479 }
1480
e9d6944e 1481 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1482 WARN_ON(!pll->on);
cdbd2316 1483 if (--pll->active)
7a419866 1484 return;
ee7b9f93 1485
46edb027 1486 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1487 pll->disable(dev_priv, pll);
ee7b9f93 1488 pll->on = false;
92f2584a
JB		 1489}
1490
b8a4f404
PZ		 1491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
040484af 1493{
23670b32 1494 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1497 uint32_t reg, val, pipeconf_val;
040484af
JB		 1498
1499 /* PCH only available on ILK+ */
1500 BUG_ON(dev_priv->info->gen < 5);
1501
1502 /* Make sure PCH DPLL is enabled */
e72f9fbf 1503 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1504 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
23670b32
DV		 1510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
59c859d6 1517 }
23670b32 1518
ab9412ba 1519 reg = PCH_TRANSCONF(pipe);
040484af 1520 val = I915_READ(reg);
5f7f726d 1521 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
dfd07d72
DV		 1528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1530 }
5f7f726d
PZ		 1531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1539 else
1540 val |= TRANS_PROGRESSIVE;
1541
040484af
JB		 1542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1545}
1546
8fb033d7 1547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1548 enum transcoder cpu_transcoder)
040484af 1549{
8fb033d7 1550 u32 val, pipeconf_val;
8fb033d7
PZ		 1551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
8fb033d7 1555 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1558
223a6fdf
PZ		 1559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
25f3ef11 1564 val = TRANS_ENABLE;
937bb610 1565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1566
9a76b1c6
PZ		 1567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
a35f2679 1569 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1570 else
1571 val |= TRANS_PROGRESSIVE;
1572
ab9412ba
DV		 1573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1575 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32
DV		 1581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
040484af
JB		 1583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
291906f1
JB		 1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
ab9412ba 1591 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
040484af
JB		 1606}
1607
ab4d966c 1608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1609{
8fb033d7
PZ		 1610 u32 val;
1611
ab9412ba 1612 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1613 val &= ~TRANS_ENABLE;
ab9412ba 1614 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1615 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1617 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1623}
1624
b24e7179 1625/**
309cfea8 1626 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
040484af 1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
040484af
JB		 1639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
b24e7179 1641{
702e7a56
PZ		 1642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
1a240d4d 1644 enum pipe pch_transcoder;
b24e7179
JB		 1645 int reg;
1646 u32 val;
1647
58c6eaa2
DV		 1648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
681e5811 1651 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
b24e7179
JB		 1656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
cc391bbb 1666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
040484af
JB		 1669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
b24e7179 1672
702e7a56 1673 reg = PIPECONF(cpu_transcoder);
b24e7179 1674 val = I915_READ(reg);
00d70b15
CW		 1675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
309cfea8 1683 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
702e7a56
PZ		 1697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
b24e7179
JB		 1699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
19332d7a 1707 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
702e7a56 1713 reg = PIPECONF(cpu_transcoder);
b24e7179 1714 val = I915_READ(reg);
00d70b15
CW		 1715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
d74362c9
KP		 1722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
6f1d69b0 1726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1727 enum plane plane)
1728{
14f86147
DL		 1729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1733}
1734
b24e7179
JB		 1735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1758 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
b24e7179
JB		 1762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
693db184
CW		 1786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
127bd2ac 1795int
48b956c5 1796intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1797 struct drm_i915_gem_object *obj,
919926ae 1798 struct intel_ring_buffer *pipelined)
6b95a207 1799{
ce453d81 1800 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1801 u32 alignment;
1802 int ret;
1803
05394f39 1804 switch (obj->tiling_mode) {
6b95a207 1805 case I915_TILING_NONE:
534843da
CW		 1806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
a6c45cf0 1808 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
6b95a207
KH		 1812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
8bb6e959
DV		 1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
693db184
CW		 1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
ce453d81 1835 dev_priv->mm.interruptible = false;
2da3b9b9 1836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1837 if (ret)
ce453d81 1838 goto err_interruptible;
6b95a207
KH		 1839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
06d98131 1845 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1846 if (ret)
1847 goto err_unpin;
1690e1eb 1848
9a5a53b3 1849 i915_gem_object_pin_fence(obj);
6b95a207 1850
ce453d81 1851 dev_priv->mm.interruptible = true;
6b95a207 1852 return 0;
48b956c5
CW		 1853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
ce453d81
CW		 1856err_interruptible:
1857 dev_priv->mm.interruptible = true;
48b956c5 1858 return ret;
6b95a207
KH		 1859}
1860
1690e1eb
CW		 1861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
c2c75131
DV		 1867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
bc752862
CW		 1869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
c2c75131 1873{
bc752862
CW		 1874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
c2c75131 1876
bc752862
CW		 1877 tile_rows = *y / 8;
1878 *y %= 8;
c2c75131 1879
bc752862
CW		 1880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
c2c75131
DV		 1892}
1893
17638cd6
JB		 1894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
81255565
JB		 1896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
05394f39 1901 struct drm_i915_gem_object *obj;
81255565 1902 int plane = intel_crtc->plane;
e506a0c6 1903 unsigned long linear_offset;
81255565 1904 u32 dspcntr;
5eddb70b 1905 u32 reg;
81255565
JB		 1906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
84f44ce7 1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
81255565 1918
5eddb70b
CW		 1919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
81255565
JB		 1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
81255565
JB		 1925 dspcntr |= DISPPLANE_8BPP;
1926 break;
57779d06
VS		 1927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
81255565 1930 break;
57779d06
VS		 1931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1949 break;
1950 default:
baba133a 1951 BUG();
81255565 1952 }
57779d06 1953
a6c45cf0 1954 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1955 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
de1aa629
VS		 1961 if (IS_G4X(dev))
1962 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
5eddb70b 1964 I915_WRITE(reg, dspcntr);
81255565 1965
e506a0c6 1966 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1967
c2c75131
DV		 1968 if (INTEL_INFO(dev)->gen >= 4) {
1969 intel_crtc->dspaddr_offset =
bc752862
CW		 1970 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971 fb->bits_per_pixel / 8,
1972 fb->pitches[0]);
c2c75131
DV		 1973 linear_offset -= intel_crtc->dspaddr_offset;
1974 } else {
e506a0c6 1975 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1976 }
e506a0c6
DV		 1977
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1982 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1984 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1985 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1986 } else
e506a0c6 1987 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1988 POSTING_READ(reg);
81255565 1989
17638cd6
JB		 1990 return 0;
1991}
1992
1993static int ironlake_update_plane(struct drm_crtc *crtc,
1994 struct drm_framebuffer *fb, int x, int y)
1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
2000 struct drm_i915_gem_object *obj;
2001 int plane = intel_crtc->plane;
e506a0c6 2002 unsigned long linear_offset;
17638cd6
JB		 2003 u32 dspcntr;
2004 u32 reg;
2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
27f8227b 2009 case 2:
17638cd6
JB		 2010 break;
2011 default:
84f44ce7 2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
17638cd6
JB		 2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
57779d06
VS		 2027 case DRM_FORMAT_RGB565:
2028 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB8888:
2031 case DRM_FORMAT_ARGB8888:
2032 dspcntr |= DISPPLANE_BGRX888;
2033 break;
2034 case DRM_FORMAT_XBGR8888:
2035 case DRM_FORMAT_ABGR8888:
2036 dspcntr |= DISPPLANE_RGBX888;
2037 break;
2038 case DRM_FORMAT_XRGB2101010:
2039 case DRM_FORMAT_ARGB2101010:
2040 dspcntr |= DISPPLANE_BGRX101010;
2041 break;
2042 case DRM_FORMAT_XBGR2101010:
2043 case DRM_FORMAT_ABGR2101010:
2044 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2045 break;
2046 default:
baba133a 2047 BUG();
17638cd6
JB		 2048 }
2049
2050 if (obj->tiling_mode != I915_TILING_NONE)
2051 dspcntr |= DISPPLANE_TILED;
2052 else
2053 dspcntr &= ~DISPPLANE_TILED;
2054
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
e506a0c6 2060 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2061 intel_crtc->dspaddr_offset =
bc752862
CW		 2062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
c2c75131 2065 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2066
e506a0c6
DV		 2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2070 I915_MODIFY_DISPBASE(DSPSURF(plane),
2071 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2072 if (IS_HASWELL(dev)) {
2073 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074 } else {
2075 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077 }
17638cd6
JB		 2078 POSTING_READ(reg);
2079
2080 return 0;
2081}
2082
2083/* Assume fb object is pinned & idle & fenced and just update base pointers */
2084static int
2085intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086 int x, int y, enum mode_set_atomic state)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2090
6b8e6ed0
CW		 2091 if (dev_priv->display.disable_fbc)
2092 dev_priv->display.disable_fbc(dev);
3dec0095 2093 intel_increase_pllclock(crtc);
81255565 2094
6b8e6ed0 2095 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2096}
2097
96a02917
VS		 2098void intel_display_handle_reset(struct drm_device *dev)
2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102
2103 /*
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2107 *
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2111 *
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2115 */
2116
2117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 enum plane plane = intel_crtc->plane;
2120
2121 intel_prepare_page_flip(dev, plane);
2122 intel_finish_page_flip_plane(dev, plane);
2123 }
2124
2125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128 mutex_lock(&crtc->mutex);
2129 if (intel_crtc->active)
2130 dev_priv->display.update_plane(crtc, crtc->fb,
2131 crtc->x, crtc->y);
2132 mutex_unlock(&crtc->mutex);
2133 }
2134}
2135
14667a4b
CW		 2136static int
2137intel_finish_fb(struct drm_framebuffer *old_fb)
2138{
2139 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 bool was_interruptible = dev_priv->mm.interruptible;
2142 int ret;
2143
14667a4b
CW		 2144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2147 * framebuffer.
2148 *
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2151 */
2152 dev_priv->mm.interruptible = false;
2153 ret = i915_gem_object_finish_gpu(obj);
2154 dev_priv->mm.interruptible = was_interruptible;
2155
2156 return ret;
2157}
2158
198598d0
VS		 2159static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_master_private *master_priv;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165 if (!dev->primary->master)
2166 return;
2167
2168 master_priv = dev->primary->master->driver_priv;
2169 if (!master_priv->sarea_priv)
2170 return;
2171
2172 switch (intel_crtc->pipe) {
2173 case 0:
2174 master_priv->sarea_priv->pipeA_x = x;
2175 master_priv->sarea_priv->pipeA_y = y;
2176 break;
2177 case 1:
2178 master_priv->sarea_priv->pipeB_x = x;
2179 master_priv->sarea_priv->pipeB_y = y;
2180 break;
2181 default:
2182 break;
2183 }
2184}
2185
5c3b82e2 2186static int
3c4fdcfb 2187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2188 struct drm_framebuffer *fb)
79e53945
JB		 2189{
2190 struct drm_device *dev = crtc->dev;
6b8e6ed0 2191 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2193 struct drm_framebuffer *old_fb;
5c3b82e2 2194 int ret;
79e53945
JB		 2195
2196 /* no fb bound */
94352cf9 2197 if (!fb) {
a5071c2f 2198 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2199 return 0;
2200 }
2201
7eb552ae 2202 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc->plane),
2205 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2206 return -EINVAL;
79e53945
JB		 2207 }
2208
5c3b82e2 2209 mutex_lock(&dev->struct_mutex);
265db958 2210 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2211 to_intel_framebuffer(fb)->obj,
919926ae 2212 NULL);
5c3b82e2
CW		 2213 if (ret != 0) {
2214 mutex_unlock(&dev->struct_mutex);
a5071c2f 2215 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2216 return ret;
2217 }
79e53945 2218
94352cf9 2219 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2220 if (ret) {
94352cf9 2221 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("failed to update base address\n");
4e6cfefc 2224 return ret;
79e53945 2225 }
3c4fdcfb 2226
94352cf9
DV		 2227 old_fb = crtc->fb;
2228 crtc->fb = fb;
6c4c86f5
DV		 2229 crtc->x = x;
2230 crtc->y = y;
94352cf9 2231
b7f1de28 2232 if (old_fb) {
d7697eea
DV		 2233 if (intel_crtc->active && old_fb != fb)
2234 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2236 }
652c393a 2237
6b8e6ed0 2238 intel_update_fbc(dev);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
79e53945 2240
198598d0 2241 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2242
2243 return 0;
79e53945
JB		 2244}
2245
5e84e1a4
ZW		 2246static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
2252 u32 reg, temp;
2253
2254 /* enable normal train */
2255 reg = FDI_TX_CTL(pipe);
2256 temp = I915_READ(reg);
61e499bf 2257 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2258 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2260 } else {
2261 temp &= ~FDI_LINK_TRAIN_NONE;
2262 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2263 }
5e84e1a4
ZW		 2264 I915_WRITE(reg, temp);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 if (HAS_PCH_CPT(dev)) {
2269 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271 } else {
2272 temp &= ~FDI_LINK_TRAIN_NONE;
2273 temp |= FDI_LINK_TRAIN_NONE;
2274 }
2275 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277 /* wait one idle pattern time */
2278 POSTING_READ(reg);
2279 udelay(1000);
357555c0
JB		 2280
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev))
2283 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2285}
2286
1e833f40
DV		 2287static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288{
2289 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290}
2291
01a415fd
DV		 2292static void ivb_modeset_global_resources(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *pipe_B_crtc =
2296 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297 struct intel_crtc *pipe_C_crtc =
2298 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299 uint32_t temp;
2300
1e833f40
DV		 2301 /*
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2305 */
2306 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 }
2316}
2317
8db9d77b
ZW		 2318/* The FDI link training functions for ILK/Ibexpeak. */
2319static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320{
2321 struct drm_device *dev = crtc->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 int pipe = intel_crtc->pipe;
0fc932b8 2325 int plane = intel_crtc->plane;
5eddb70b 2326 u32 reg, temp, tries;
8db9d77b 2327
0fc932b8
JB		 2328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv, pipe);
2330 assert_plane_enabled(dev_priv, plane);
2331
e1a44743
AJ		 2332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 for train result */
5eddb70b
CW		 2334 reg = FDI_RX_IMR(pipe);
2335 temp = I915_READ(reg);
e1a44743
AJ		 2336 temp &= ~FDI_RX_SYMBOL_LOCK;
2337 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339 I915_READ(reg);
e1a44743
AJ		 2340 udelay(150);
2341
8db9d77b 2342 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
627eb5a3
DV		 2345 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2349 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2350
5eddb70b
CW		 2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2355 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357 POSTING_READ(reg);
8db9d77b
ZW		 2358 udelay(150);
2359
5b2adf89 2360 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2364
5eddb70b 2365 reg = FDI_RX_IIR(pipe);
e1a44743 2366 for (tries = 0; tries < 5; tries++) {
5eddb70b 2367 temp = I915_READ(reg);
8db9d77b
ZW		 2368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370 if ((temp & FDI_RX_BIT_LOCK)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2372 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2373 break;
2374 }
8db9d77b 2375 }
e1a44743 2376 if (tries == 5)
5eddb70b 2377 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2378
2379 /* Train 2 */
5eddb70b
CW		 2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
8db9d77b
ZW		 2382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2384 I915_WRITE(reg, temp);
8db9d77b 2385
5eddb70b
CW		 2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
8db9d77b
ZW		 2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2390 I915_WRITE(reg, temp);
8db9d77b 2391
5eddb70b
CW		 2392 POSTING_READ(reg);
2393 udelay(150);
8db9d77b 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2408
2409 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2410
8db9d77b
ZW		 2411}
2412
0206e353 2413static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2414 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418};
2419
2420/* The FDI link training functions for SNB/Cougarpoint. */
2421static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
fa37d39e 2427 u32 reg, temp, i, retry;
8db9d77b 2428
e1a44743
AJ		 2429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 for train result */
5eddb70b
CW		 2431 reg = FDI_RX_IMR(pipe);
2432 temp = I915_READ(reg);
e1a44743
AJ		 2433 temp &= ~FDI_RX_SYMBOL_LOCK;
2434 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
e1a44743
AJ		 2438 udelay(150);
2439
8db9d77b 2440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
627eb5a3
DV		 2443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 /* SNB-B */
2449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2451
d74cf324
DV		 2452 I915_WRITE(FDI_RX_MISC(pipe),
2453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
5eddb70b
CW		 2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 if (HAS_PCH_CPT(dev)) {
2458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460 } else {
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 }
5eddb70b
CW		 2464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466 POSTING_READ(reg);
8db9d77b
ZW		 2467 udelay(150);
2468
0206e353 2469 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
8db9d77b
ZW		 2477 udelay(500);
2478
fa37d39e
SP		 2479 for (retry = 0; retry < 5; retry++) {
2480 reg = FDI_RX_IIR(pipe);
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483 if (temp & FDI_RX_BIT_LOCK) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 udelay(50);
8db9d77b 2489 }
fa37d39e
SP		 2490 if (retry < 5)
2491 break;
8db9d77b
ZW		 2492 }
2493 if (i == 4)
5eddb70b 2494 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2495
2496 /* Train 2 */
5eddb70b
CW		 2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 if (IS_GEN6(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 }
5eddb70b 2506 I915_WRITE(reg, temp);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516 }
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(150);
2521
0206e353 2522 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
8db9d77b
ZW		 2530 udelay(500);
2531
fa37d39e
SP		 2532 for (retry = 0; retry < 5; retry++) {
2533 reg = FDI_RX_IIR(pipe);
2534 temp = I915_READ(reg);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 udelay(50);
8db9d77b 2542 }
fa37d39e
SP		 2543 if (retry < 5)
2544 break;
8db9d77b
ZW		 2545 }
2546 if (i == 4)
5eddb70b 2547 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2548
2549 DRM_DEBUG_KMS("FDI train done.\n");
2550}
2551
357555c0
JB		 2552/* Manual link training for Ivy Bridge A0 parts */
2553static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
2559 u32 reg, temp, i;
2560
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
2570 udelay(150);
2571
01a415fd
DV		 2572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe)));
2574
357555c0
JB		 2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
627eb5a3
DV		 2578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2584 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
d74cf324
DV		 2587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
357555c0
JB		 2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~FDI_LINK_TRAIN_AUTO;
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2595 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
357555c0
JB		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615 if (temp & FDI_RX_BIT_LOCK ||
2616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2619 break;
2620 }
2621 }
2622 if (i == 4)
2623 DRM_ERROR("FDI train 1 fail!\n");
2624
2625 /* Train 2 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_SYMBOL_LOCK) {
2658 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 2 fail!\n");
2665
2666 DRM_DEBUG_KMS("FDI train done.\n");
2667}
2668
88cefb6c 2669static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2670{
88cefb6c 2671 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2672 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2673 int pipe = intel_crtc->pipe;
5eddb70b 2674 u32 reg, temp;
79e53945 2675
c64e311e 2676
c98e9dcf 2677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
627eb5a3
DV		 2680 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2682 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2683 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685 POSTING_READ(reg);
c98e9dcf
JB		 2686 udelay(200);
2687
2688 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2689 temp = I915_READ(reg);
2690 I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692 POSTING_READ(reg);
c98e9dcf
JB		 2693 udelay(200);
2694
20749730
PZ		 2695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2700
20749730
PZ		 2701 POSTING_READ(reg);
2702 udelay(100);
6be4a607 2703 }
0e23b99d
JB		 2704}
2705
88cefb6c
DV		 2706static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707{
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int pipe = intel_crtc->pipe;
2711 u32 reg, temp;
2712
2713 /* Switch from PCDclk to Rawclk */
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718 /* Disable CPU FDI TX PLL */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730 /* Wait for the clocks to turn off. */
2731 POSTING_READ(reg);
2732 udelay(100);
2733}
2734
0fc932b8
JB		 2735static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp;
2742
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747 POSTING_READ(reg);
2748
2749 reg = FDI_RX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(0x7 << 16);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755 POSTING_READ(reg);
2756 udelay(100);
2757
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2759 if (HAS_PCH_IBX(dev)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2761 }
0fc932b8
JB		 2762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
dfd07d72 2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
5bb61643
CW		 2788static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2793 unsigned long flags;
2794 bool pending;
2795
10d83730
VS		 2796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2798 return false;
2799
2800 spin_lock_irqsave(&dev->event_lock, flags);
2801 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802 spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804 return pending;
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
5bb61643 2810 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2811
2812 if (crtc->fb == NULL)
2813 return;
2814
2c10d571
DV		 2815 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
5bb61643
CW		 2817 wait_event(dev_priv->pending_flip_queue,
2818 !intel_crtc_has_pending_flip(crtc));
2819
0f91128d
CW		 2820 mutex_lock(&dev->struct_mutex);
2821 intel_finish_fb(crtc->fb);
2822 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2823}
2824
e615efe4
ED		 2825/* Program iCLKIP clock to the desired frequency */
2826static void lpt_program_iclkip(struct drm_crtc *crtc)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831 u32 temp;
2832
09153000
DV		 2833 mutex_lock(&dev_priv->dpio_lock);
2834
e615efe4
ED		 2835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2837 */
2838 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2842 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843 SBI_SSCCTL_DISABLE,
2844 SBI_ICLK);
e615efe4
ED		 2845
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc->mode.clock == 20000) {
2848 auxdiv = 1;
2849 divsel = 0x41;
2850 phaseinc = 0x20;
2851 } else {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2856 * precision.
2857 */
2858 u32 iclk_virtual_root_freq = 172800 * 1000;
2859 u32 iclk_pi_range = 64;
2860 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863 msb_divisor_value = desired_divisor / iclk_pi_range;
2864 pi_value = desired_divisor % iclk_pi_range;
2865
2866 auxdiv = 0;
2867 divsel = msb_divisor_value - 2;
2868 phaseinc = pi_value;
2869 }
2870
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878 crtc->mode.clock,
2879 auxdiv,
2880 divsel,
2881 phasedir,
2882 phaseinc);
2883
2884 /* Program SSCDIVINTPHASE6 */
988d6ee8 2885 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2886 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2892 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2893
2894 /* Program SSCAUXDIV */
988d6ee8 2895 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2896 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2898 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2899
2900 /* Enable modulator and associated divider */
988d6ee8 2901 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2902 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Wait for initialization time */
2906 udelay(24);
2907
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2909
2910 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2911}
2912
275f01b2
DV		 2913static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914 enum pipe pch_transcoder)
2915{
2916 struct drm_device *dev = crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921 I915_READ(HTOTAL(cpu_transcoder)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923 I915_READ(HBLANK(cpu_transcoder)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925 I915_READ(HSYNC(cpu_transcoder)));
2926
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928 I915_READ(VTOTAL(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930 I915_READ(VBLANK(cpu_transcoder)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932 I915_READ(VSYNC(cpu_transcoder)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935}
2936
f67a559d
JB		 2937/*
2938 * Enable PCH resources required for PCH ports:
2939 * - PCH PLLs
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2943 * - transcoder
2944 */
2945static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2946{
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
ee7b9f93 2951 u32 reg, temp;
2c07245f 2952
ab9412ba 2953 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2954
cd986abb
DV		 2955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
c98e9dcf 2960 /* For PCH output, training FDI link */
674cf967 2961 dev_priv->display.fdi_link_train(crtc);
2c07245f 2962
572deb37
DV		 2963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2966 *
e72f9fbf
DV		 2967 * Note that enable_shared_dpll tries to do the right thing, but
2968 * get_shared_dpll unconditionally resets the pll - we need that to have
2969 * the right LVDS enable sequence. */
2970 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2971
303b81e0 2972 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2973 u32 sel;
4b645f14 2974
c98e9dcf 2975 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2976 temp |= TRANS_DPLL_ENABLE(pipe);
2977 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2978 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2979 temp |= sel;
2980 else
2981 temp &= ~sel;
c98e9dcf 2982 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2983 }
5eddb70b 2984
d9b6cb56
JB		 2985 /* set transcoder timing, panel must allow it */
2986 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2987 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2988
303b81e0 2989 intel_fdi_normal_train(crtc);
5e84e1a4 2990
c98e9dcf
JB		 2991 /* For PCH DP, enable TRANS_DP_CTL */
2992 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2993 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2994 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2995 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2996 reg = TRANS_DP_CTL(pipe);
2997 temp = I915_READ(reg);
2998 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2999 TRANS_DP_SYNC_MASK |
3000 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3001 temp |= (TRANS_DP_OUTPUT_ENABLE |
3002 TRANS_DP_ENH_FRAMING);
9325c9f0 3003 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3004
3005 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3006 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3007 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3008 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3009
3010 switch (intel_trans_dp_port_sel(crtc)) {
3011 case PCH_DP_B:
5eddb70b 3012 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3013 break;
3014 case PCH_DP_C:
5eddb70b 3015 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3016 break;
3017 case PCH_DP_D:
5eddb70b 3018 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3019 break;
3020 default:
e95d41e1 3021 BUG();
32f9d658 3022 }
2c07245f 3023
5eddb70b 3024 I915_WRITE(reg, temp);
6be4a607 3025 }
b52eb4dc 3026
b8a4f404 3027 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3028}
3029
1507e5bd
PZ		 3030static void lpt_pch_enable(struct drm_crtc *crtc)
3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3035 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3036
ab9412ba 3037 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3038
8c52b5e8 3039 lpt_program_iclkip(crtc);
1507e5bd 3040
0540e488 3041 /* Set transcoder timing. */
275f01b2 3042 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3043
937bb610 3044 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3045}
3046
e2b78267 3047static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3048{
e2b78267 3049 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3050
3051 if (pll == NULL)
3052 return;
3053
3054 if (pll->refcount == 0) {
46edb027 3055 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3056 return;
3057 }
3058
f4a091c7
DV		 3059 if (--pll->refcount == 0) {
3060 WARN_ON(pll->on);
3061 WARN_ON(pll->active);
3062 }
3063
a43f6e0f 3064 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3065}
3066
b89a1d39 3067static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3068{
e2b78267
DV		 3069 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3070 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3071 enum intel_dpll_id i;
ee7b9f93 3072
ee7b9f93 3073 if (pll) {
46edb027
DV		 3074 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3075 crtc->base.base.id, pll->name);
e2b78267 3076 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3077 }
3078
98b6bd99
DV		 3079 if (HAS_PCH_IBX(dev_priv->dev)) {
3080 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3081 i = crtc->pipe;
e72f9fbf 3082 pll = &dev_priv->shared_dplls[i];
98b6bd99 3083
46edb027
DV		 3084 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3085 crtc->base.base.id, pll->name);
98b6bd99
DV		 3086
3087 goto found;
3088 }
3089
e72f9fbf
DV		 3090 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3091 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3092
3093 /* Only want to check enabled timings first */
3094 if (pll->refcount == 0)
3095 continue;
3096
b89a1d39
DV		 3097 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3098 sizeof(pll->hw_state)) == 0) {
46edb027 3099 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3100 crtc->base.base.id,
46edb027 3101 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3102
3103 goto found;
3104 }
3105 }
3106
3107 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3108 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3109 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3110 if (pll->refcount == 0) {
46edb027
DV		 3111 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3112 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3113 goto found;
3114 }
3115 }
3116
3117 return NULL;
3118
3119found:
a43f6e0f 3120 crtc->config.shared_dpll = i;
46edb027
DV		 3121 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3122 pipe_name(crtc->pipe));
ee7b9f93 3123
cdbd2316 3124 if (pll->active == 0) {
66e985c0
DV		 3125 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3126 sizeof(pll->hw_state));
3127
46edb027 3128 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3129 WARN_ON(pll->on);
e9d6944e 3130 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3131
15bdd4cf 3132 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3133 }
3134 pll->refcount++;
e04c7350 3135
ee7b9f93
JB		 3136 return pll;
3137}
3138
a1520318 3139static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3140{
3141 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3142 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3143 u32 temp;
3144
3145 temp = I915_READ(dslreg);
3146 udelay(500);
3147 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3148 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3149 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3150 }
3151}
3152
b074cec8
JB		 3153static void ironlake_pfit_enable(struct intel_crtc *crtc)
3154{
3155 struct drm_device *dev = crtc->base.dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 int pipe = crtc->pipe;
3158
0ef37f3f 3159 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3160 /* Force use of hard-coded filter coefficients
3161 * as some pre-programmed values are broken,
3162 * e.g. x201.
3163 */
3164 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3165 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3166 PF_PIPE_SEL_IVB(pipe));
3167 else
3168 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3169 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3170 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3171 }
3172}
3173
bb53d4ae
VS		 3174static void intel_enable_planes(struct drm_crtc *crtc)
3175{
3176 struct drm_device *dev = crtc->dev;
3177 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3178 struct intel_plane *intel_plane;
3179
3180 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3181 if (intel_plane->pipe == pipe)
3182 intel_plane_restore(&intel_plane->base);
3183}
3184
3185static void intel_disable_planes(struct drm_crtc *crtc)
3186{
3187 struct drm_device *dev = crtc->dev;
3188 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3189 struct intel_plane *intel_plane;
3190
3191 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3192 if (intel_plane->pipe == pipe)
3193 intel_plane_disable(&intel_plane->base);
3194}
3195
f67a559d
JB		 3196static void ironlake_crtc_enable(struct drm_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3201 struct intel_encoder *encoder;
f67a559d
JB		 3202 int pipe = intel_crtc->pipe;
3203 int plane = intel_crtc->plane;
f67a559d 3204
08a48469
DV		 3205 WARN_ON(!crtc->enabled);
3206
f67a559d
JB		 3207 if (intel_crtc->active)
3208 return;
3209
3210 intel_crtc->active = true;
8664281b
PZ		 3211
3212 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3213 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3214
f67a559d
JB		 3215 intel_update_watermarks(dev);
3216
f6736a1a 3217 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3218 if (encoder->pre_enable)
3219 encoder->pre_enable(encoder);
f67a559d 3220
5bfe2ac0 3221 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3222 /* Note: FDI PLL enabling _must_ be done before we enable the
3223 * cpu pipes, hence this is separate from all the other fdi/pch
3224 * enabling. */
88cefb6c 3225 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3226 } else {
3227 assert_fdi_tx_disabled(dev_priv, pipe);
3228 assert_fdi_rx_disabled(dev_priv, pipe);
3229 }
f67a559d 3230
b074cec8 3231 ironlake_pfit_enable(intel_crtc);
f67a559d 3232
9c54c0dd
JB		 3233 /*
3234 * On ILK+ LUT must be loaded before the pipe is running but with
3235 * clocks enabled
3236 */
3237 intel_crtc_load_lut(crtc);
3238
5bfe2ac0
DV		 3239 intel_enable_pipe(dev_priv, pipe,
3240 intel_crtc->config.has_pch_encoder);
f67a559d 3241 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3242 intel_enable_planes(crtc);
5c38d48c 3243 intel_crtc_update_cursor(crtc, true);
f67a559d 3244
5bfe2ac0 3245 if (intel_crtc->config.has_pch_encoder)
f67a559d 3246 ironlake_pch_enable(crtc);
c98e9dcf 3247
d1ebd816 3248 mutex_lock(&dev->struct_mutex);
bed4a673 3249 intel_update_fbc(dev);
d1ebd816
BW		 3250 mutex_unlock(&dev->struct_mutex);
3251
fa5c73b1
DV		 3252 for_each_encoder_on_crtc(dev, crtc, encoder)
3253 encoder->enable(encoder);
61b77ddd
DV		 3254
3255 if (HAS_PCH_CPT(dev))
a1520318 3256 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3257
3258 /*
3259 * There seems to be a race in PCH platform hw (at least on some
3260 * outputs) where an enabled pipe still completes any pageflip right
3261 * away (as if the pipe is off) instead of waiting for vblank. As soon
3262 * as the first vblank happend, everything works as expected. Hence just
3263 * wait for one vblank before returning to avoid strange things
3264 * happening.
3265 */
3266 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3267}
3268
42db64ef
PZ		 3269/* IPS only exists on ULT machines and is tied to pipe A. */
3270static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3271{
f5adf94e 3272 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3273}
3274
3275static void hsw_enable_ips(struct intel_crtc *crtc)
3276{
3277 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3278
3279 if (!crtc->config.ips_enabled)
3280 return;
3281
3282 /* We can only enable IPS after we enable a plane and wait for a vblank.
3283 * We guarantee that the plane is enabled by calling intel_enable_ips
3284 * only after intel_enable_plane. And intel_enable_plane already waits
3285 * for a vblank, so all we need to do here is to enable the IPS bit. */
3286 assert_plane_enabled(dev_priv, crtc->plane);
3287 I915_WRITE(IPS_CTL, IPS_ENABLE);
3288}
3289
3290static void hsw_disable_ips(struct intel_crtc *crtc)
3291{
3292 struct drm_device *dev = crtc->base.dev;
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294
3295 if (!crtc->config.ips_enabled)
3296 return;
3297
3298 assert_plane_enabled(dev_priv, crtc->plane);
3299 I915_WRITE(IPS_CTL, 0);
3300
3301 /* We need to wait for a vblank before we can disable the plane. */
3302 intel_wait_for_vblank(dev, crtc->pipe);
3303}
3304
4f771f10
PZ		 3305static void haswell_crtc_enable(struct drm_crtc *crtc)
3306{
3307 struct drm_device *dev = crtc->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3310 struct intel_encoder *encoder;
3311 int pipe = intel_crtc->pipe;
3312 int plane = intel_crtc->plane;
4f771f10
PZ		 3313
3314 WARN_ON(!crtc->enabled);
3315
3316 if (intel_crtc->active)
3317 return;
3318
3319 intel_crtc->active = true;
8664281b
PZ		 3320
3321 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3322 if (intel_crtc->config.has_pch_encoder)
3323 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3324
4f771f10
PZ		 3325 intel_update_watermarks(dev);
3326
5bfe2ac0 3327 if (intel_crtc->config.has_pch_encoder)
04945641 3328 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3329
3330 for_each_encoder_on_crtc(dev, crtc, encoder)
3331 if (encoder->pre_enable)
3332 encoder->pre_enable(encoder);
3333
1f544388 3334 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3335
b074cec8 3336 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3337
3338 /*
3339 * On ILK+ LUT must be loaded before the pipe is running but with
3340 * clocks enabled
3341 */
3342 intel_crtc_load_lut(crtc);
3343
1f544388 3344 intel_ddi_set_pipe_settings(crtc);
8228c251 3345 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3346
5bfe2ac0
DV		 3347 intel_enable_pipe(dev_priv, pipe,
3348 intel_crtc->config.has_pch_encoder);
4f771f10 3349 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3350 intel_enable_planes(crtc);
5c38d48c 3351 intel_crtc_update_cursor(crtc, true);
4f771f10 3352
42db64ef
PZ		 3353 hsw_enable_ips(intel_crtc);
3354
5bfe2ac0 3355 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3356 lpt_pch_enable(crtc);
4f771f10
PZ		 3357
3358 mutex_lock(&dev->struct_mutex);
3359 intel_update_fbc(dev);
3360 mutex_unlock(&dev->struct_mutex);
3361
4f771f10
PZ		 3362 for_each_encoder_on_crtc(dev, crtc, encoder)
3363 encoder->enable(encoder);
3364
4f771f10
PZ		 3365 /*
3366 * There seems to be a race in PCH platform hw (at least on some
3367 * outputs) where an enabled pipe still completes any pageflip right
3368 * away (as if the pipe is off) instead of waiting for vblank. As soon
3369 * as the first vblank happend, everything works as expected. Hence just
3370 * wait for one vblank before returning to avoid strange things
3371 * happening.
3372 */
3373 intel_wait_for_vblank(dev, intel_crtc->pipe);
3374}
3375
3f8dce3a
DV		 3376static void ironlake_pfit_disable(struct intel_crtc *crtc)
3377{
3378 struct drm_device *dev = crtc->base.dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 int pipe = crtc->pipe;
3381
3382 /* To avoid upsetting the power well on haswell only disable the pfit if
3383 * it's in use. The hw state code will make sure we get this right. */
3384 if (crtc->config.pch_pfit.size) {
3385 I915_WRITE(PF_CTL(pipe), 0);
3386 I915_WRITE(PF_WIN_POS(pipe), 0);
3387 I915_WRITE(PF_WIN_SZ(pipe), 0);
3388 }
3389}
3390
6be4a607
JB		 3391static void ironlake_crtc_disable(struct drm_crtc *crtc)
3392{
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3396 struct intel_encoder *encoder;
6be4a607
JB		 3397 int pipe = intel_crtc->pipe;
3398 int plane = intel_crtc->plane;
5eddb70b 3399 u32 reg, temp;
b52eb4dc 3400
ef9c3aee 3401
f7abfe8b
CW		 3402 if (!intel_crtc->active)
3403 return;
3404
ea9d758d
DV		 3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->disable(encoder);
3407
e6c3a2a6 3408 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3409 drm_vblank_off(dev, pipe);
913d8d11 3410
5c3fe8b0 3411 if (dev_priv->fbc.plane == plane)
973d04f9 3412 intel_disable_fbc(dev);
2c07245f 3413
0d5b8c61 3414 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3415 intel_disable_planes(crtc);
0d5b8c61
VS		 3416 intel_disable_plane(dev_priv, plane, pipe);
3417
d925c59a
DV		 3418 if (intel_crtc->config.has_pch_encoder)
3419 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3420
b24e7179 3421 intel_disable_pipe(dev_priv, pipe);
32f9d658 3422
3f8dce3a 3423 ironlake_pfit_disable(intel_crtc);
2c07245f 3424
bf49ec8c
DV		 3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->post_disable)
3427 encoder->post_disable(encoder);
2c07245f 3428
d925c59a
DV		 3429 if (intel_crtc->config.has_pch_encoder) {
3430 ironlake_fdi_disable(crtc);
913d8d11 3431
d925c59a
DV		 3432 ironlake_disable_pch_transcoder(dev_priv, pipe);
3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3434
d925c59a
DV		 3435 if (HAS_PCH_CPT(dev)) {
3436 /* disable TRANS_DP_CTL */
3437 reg = TRANS_DP_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3440 TRANS_DP_PORT_SEL_MASK);
3441 temp |= TRANS_DP_PORT_SEL_NONE;
3442 I915_WRITE(reg, temp);
3443
3444 /* disable DPLL_SEL */
3445 temp = I915_READ(PCH_DPLL_SEL);
11887397 3446 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3447 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3448 }
e3421a18 3449
d925c59a 3450 /* disable PCH DPLL */
e72f9fbf 3451 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3452
d925c59a
DV		 3453 ironlake_fdi_pll_disable(intel_crtc);
3454 }
6b383a7f 3455
f7abfe8b 3456 intel_crtc->active = false;
6b383a7f 3457 intel_update_watermarks(dev);
d1ebd816
BW		 3458
3459 mutex_lock(&dev->struct_mutex);
6b383a7f 3460 intel_update_fbc(dev);
d1ebd816 3461 mutex_unlock(&dev->struct_mutex);
6be4a607 3462}
1b3c7a47 3463
4f771f10 3464static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3465{
4f771f10
PZ		 3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3469 struct intel_encoder *encoder;
3470 int pipe = intel_crtc->pipe;
3471 int plane = intel_crtc->plane;
3b117c8f 3472 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3473
4f771f10
PZ		 3474 if (!intel_crtc->active)
3475 return;
3476
3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->disable(encoder);
3479
3480 intel_crtc_wait_for_pending_flips(crtc);
3481 drm_vblank_off(dev, pipe);
4f771f10 3482
891348b2 3483 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3484 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3485 intel_disable_fbc(dev);
3486
42db64ef
PZ		 3487 hsw_disable_ips(intel_crtc);
3488
0d5b8c61 3489 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3490 intel_disable_planes(crtc);
891348b2
RV		 3491 intel_disable_plane(dev_priv, plane, pipe);
3492
8664281b
PZ		 3493 if (intel_crtc->config.has_pch_encoder)
3494 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3495 intel_disable_pipe(dev_priv, pipe);
3496
ad80a810 3497 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3498
3f8dce3a 3499 ironlake_pfit_disable(intel_crtc);
4f771f10 3500
1f544388 3501 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3502
3503 for_each_encoder_on_crtc(dev, crtc, encoder)
3504 if (encoder->post_disable)
3505 encoder->post_disable(encoder);
3506
88adfff1 3507 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3508 lpt_disable_pch_transcoder(dev_priv);
8664281b 3509 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3510 intel_ddi_fdi_disable(crtc);
83616634 3511 }
4f771f10
PZ		 3512
3513 intel_crtc->active = false;
3514 intel_update_watermarks(dev);
3515
3516 mutex_lock(&dev->struct_mutex);
3517 intel_update_fbc(dev);
3518 mutex_unlock(&dev->struct_mutex);
3519}
3520
ee7b9f93
JB		 3521static void ironlake_crtc_off(struct drm_crtc *crtc)
3522{
3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3524 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3525}
3526
6441ab5f
PZ		 3527static void haswell_crtc_off(struct drm_crtc *crtc)
3528{
3529 intel_ddi_put_crtc_pll(crtc);
3530}
3531
02e792fb
DV		 3532static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3533{
02e792fb 3534 if (!enable && intel_crtc->overlay) {
23f09ce3 3535 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3536 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3537
23f09ce3 3538 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3539 dev_priv->mm.interruptible = false;
3540 (void) intel_overlay_switch_off(intel_crtc->overlay);
3541 dev_priv->mm.interruptible = true;
23f09ce3 3542 mutex_unlock(&dev->struct_mutex);
02e792fb 3543 }
02e792fb 3544
5dcdbcb0
CW		 3545 /* Let userspace switch the overlay on again. In most cases userspace
3546 * has to recompute where to put it anyway.
3547 */
02e792fb
DV		 3548}
3549
61bc95c1
EE		 3550/**
3551 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3552 * cursor plane briefly if not already running after enabling the display
3553 * plane.
3554 * This workaround avoids occasional blank screens when self refresh is
3555 * enabled.
3556 */
3557static void
3558g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3559{
3560 u32 cntl = I915_READ(CURCNTR(pipe));
3561
3562 if ((cntl & CURSOR_MODE) == 0) {
3563 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3564
3565 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3566 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3567 intel_wait_for_vblank(dev_priv->dev, pipe);
3568 I915_WRITE(CURCNTR(pipe), cntl);
3569 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3570 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3571 }
3572}
3573
2dd24552
JB		 3574static void i9xx_pfit_enable(struct intel_crtc *crtc)
3575{
3576 struct drm_device *dev = crtc->base.dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc_config *pipe_config = &crtc->config;
3579
328d8e82 3580 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3581 return;
3582
2dd24552 3583 /*
c0b03411
DV		 3584 * The panel fitter should only be adjusted whilst the pipe is disabled,
3585 * according to register description and PRM.
2dd24552 3586 */
c0b03411
DV		 3587 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3588 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3589
b074cec8
JB		 3590 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3591 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3592
3593 /* Border color in case we don't scale up to the full screen. Black by
3594 * default, change to something else for debugging. */
3595 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3596}
3597
89b667f8
JB		 3598static void valleyview_crtc_enable(struct drm_crtc *crtc)
3599{
3600 struct drm_device *dev = crtc->dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 struct intel_encoder *encoder;
3604 int pipe = intel_crtc->pipe;
3605 int plane = intel_crtc->plane;
3606
3607 WARN_ON(!crtc->enabled);
3608
3609 if (intel_crtc->active)
3610 return;
3611
3612 intel_crtc->active = true;
3613 intel_update_watermarks(dev);
3614
3615 mutex_lock(&dev_priv->dpio_lock);
3616
3617 for_each_encoder_on_crtc(dev, crtc, encoder)
3618 if (encoder->pre_pll_enable)
3619 encoder->pre_pll_enable(encoder);
3620
87442f73 3621 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3622
3623 for_each_encoder_on_crtc(dev, crtc, encoder)
3624 if (encoder->pre_enable)
3625 encoder->pre_enable(encoder);
3626
3627 /* VLV wants encoder enabling _before_ the pipe is up. */
3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 encoder->enable(encoder);
3630
2dd24552
JB		 3631 i9xx_pfit_enable(intel_crtc);
3632
63cbb074
VS		 3633 intel_crtc_load_lut(crtc);
3634
89b667f8
JB		 3635 intel_enable_pipe(dev_priv, pipe, false);
3636 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3637 intel_enable_planes(crtc);
5c38d48c 3638 intel_crtc_update_cursor(crtc, true);
89b667f8 3639
89b667f8
JB		 3640 intel_update_fbc(dev);
3641
89b667f8
JB		 3642 mutex_unlock(&dev_priv->dpio_lock);
3643}
3644
0b8765c6 3645static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3646{
3647 struct drm_device *dev = crtc->dev;
79e53945
JB		 3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3650 struct intel_encoder *encoder;
79e53945 3651 int pipe = intel_crtc->pipe;
80824003 3652 int plane = intel_crtc->plane;
79e53945 3653
08a48469
DV		 3654 WARN_ON(!crtc->enabled);
3655
f7abfe8b
CW		 3656 if (intel_crtc->active)
3657 return;
3658
3659 intel_crtc->active = true;
6b383a7f
CW		 3660 intel_update_watermarks(dev);
3661
9d6d9f19
MK		 3662 for_each_encoder_on_crtc(dev, crtc, encoder)
3663 if (encoder->pre_enable)
3664 encoder->pre_enable(encoder);
3665
f6736a1a
DV		 3666 i9xx_enable_pll(intel_crtc);
3667
2dd24552
JB		 3668 i9xx_pfit_enable(intel_crtc);
3669
63cbb074
VS		 3670 intel_crtc_load_lut(crtc);
3671
040484af 3672 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3673 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3674 intel_enable_planes(crtc);
22e407d7 3675 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3676 if (IS_G4X(dev))
3677 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3678 intel_crtc_update_cursor(crtc, true);
79e53945 3679
0b8765c6
JB		 3680 /* Give the overlay scaler a chance to enable if it's on this pipe */
3681 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3682
f440eb13 3683 intel_update_fbc(dev);
ef9c3aee 3684
fa5c73b1
DV		 3685 for_each_encoder_on_crtc(dev, crtc, encoder)
3686 encoder->enable(encoder);
0b8765c6 3687}
79e53945 3688
87476d63
DV		 3689static void i9xx_pfit_disable(struct intel_crtc *crtc)
3690{
3691 struct drm_device *dev = crtc->base.dev;
3692 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3693
328d8e82
DV		 3694 if (!crtc->config.gmch_pfit.control)
3695 return;
87476d63 3696
328d8e82 3697 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3698
328d8e82
DV		 3699 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3700 I915_READ(PFIT_CONTROL));
3701 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3702}
3703
0b8765c6
JB		 3704static void i9xx_crtc_disable(struct drm_crtc *crtc)
3705{
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3709 struct intel_encoder *encoder;
0b8765c6
JB		 3710 int pipe = intel_crtc->pipe;
3711 int plane = intel_crtc->plane;
ef9c3aee 3712
f7abfe8b
CW		 3713 if (!intel_crtc->active)
3714 return;
3715
ea9d758d
DV		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->disable(encoder);
3718
0b8765c6 3719 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3720 intel_crtc_wait_for_pending_flips(crtc);
3721 drm_vblank_off(dev, pipe);
0b8765c6 3722
5c3fe8b0 3723 if (dev_priv->fbc.plane == plane)
973d04f9 3724 intel_disable_fbc(dev);
79e53945 3725
0d5b8c61
VS		 3726 intel_crtc_dpms_overlay(intel_crtc, false);
3727 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3728 intel_disable_planes(crtc);
b24e7179 3729 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3730
b24e7179 3731 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3732
87476d63 3733 i9xx_pfit_disable(intel_crtc);
24a1f16d 3734
89b667f8
JB		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 if (encoder->post_disable)
3737 encoder->post_disable(encoder);
3738
63d7bbe9 3739 intel_disable_pll(dev_priv, pipe);
0b8765c6 3740
f7abfe8b 3741 intel_crtc->active = false;
6b383a7f
CW		 3742 intel_update_fbc(dev);
3743 intel_update_watermarks(dev);
0b8765c6
JB		 3744}
3745
ee7b9f93
JB		 3746static void i9xx_crtc_off(struct drm_crtc *crtc)
3747{
3748}
3749
976f8a20
DV		 3750static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3751 bool enabled)
2c07245f
ZW		 3752{
3753 struct drm_device *dev = crtc->dev;
3754 struct drm_i915_master_private *master_priv;
3755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756 int pipe = intel_crtc->pipe;
79e53945
JB		 3757
3758 if (!dev->primary->master)
3759 return;
3760
3761 master_priv = dev->primary->master->driver_priv;
3762 if (!master_priv->sarea_priv)
3763 return;
3764
79e53945
JB		 3765 switch (pipe) {
3766 case 0:
3767 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3768 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3769 break;
3770 case 1:
3771 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3772 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3773 break;
3774 default:
9db4a9c7 3775 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3776 break;
3777 }
79e53945
JB		 3778}
3779
976f8a20
DV		 3780/**
3781 * Sets the power management mode of the pipe and plane.
3782 */
3783void intel_crtc_update_dpms(struct drm_crtc *crtc)
3784{
3785 struct drm_device *dev = crtc->dev;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_encoder *intel_encoder;
3788 bool enable = false;
3789
3790 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3791 enable |= intel_encoder->connectors_active;
3792
3793 if (enable)
3794 dev_priv->display.crtc_enable(crtc);
3795 else
3796 dev_priv->display.crtc_disable(crtc);
3797
3798 intel_crtc_update_sarea(crtc, enable);
3799}
3800
cdd59983
CW		 3801static void intel_crtc_disable(struct drm_crtc *crtc)
3802{
cdd59983 3803 struct drm_device *dev = crtc->dev;
976f8a20 3804 struct drm_connector *connector;
ee7b9f93 3805 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3807
976f8a20
DV		 3808 /* crtc should still be enabled when we disable it. */
3809 WARN_ON(!crtc->enabled);
3810
3811 dev_priv->display.crtc_disable(crtc);
c77bf565 3812 intel_crtc->eld_vld = false;
976f8a20 3813 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3814 dev_priv->display.off(crtc);
3815
931872fc
CW		 3816 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3817 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3818
3819 if (crtc->fb) {
3820 mutex_lock(&dev->struct_mutex);
1690e1eb 3821 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3822 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3823 crtc->fb = NULL;
3824 }
3825
3826 /* Update computed state. */
3827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3828 if (!connector->encoder || !connector->encoder->crtc)
3829 continue;
3830
3831 if (connector->encoder->crtc != crtc)
3832 continue;
3833
3834 connector->dpms = DRM_MODE_DPMS_OFF;
3835 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3836 }
3837}
3838
a261b246 3839void intel_modeset_disable(struct drm_device *dev)
79e53945 3840{
a261b246
DV		 3841 struct drm_crtc *crtc;
3842
3843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3844 if (crtc->enabled)
3845 intel_crtc_disable(crtc);
3846 }
79e53945
JB		 3847}
3848
ea5b213a 3849void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3850{
4ef69c7a 3851 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3852
ea5b213a
CW		 3853 drm_encoder_cleanup(encoder);
3854 kfree(intel_encoder);
7e7d76c3
JB		 3855}
3856
5ab432ef
DV		 3857/* Simple dpms helper for encodres with just one connector, no cloning and only
3858 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3859 * state of the entire output pipe. */
3860void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3861{
5ab432ef
DV		 3862 if (mode == DRM_MODE_DPMS_ON) {
3863 encoder->connectors_active = true;
3864
b2cabb0e 3865 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3866 } else {
3867 encoder->connectors_active = false;
3868
b2cabb0e 3869 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3870 }
79e53945
JB		 3871}
3872
0a91ca29
DV		 3873/* Cross check the actual hw state with our own modeset state tracking (and it's
3874 * internal consistency). */
b980514c 3875static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3876{
0a91ca29
DV		 3877 if (connector->get_hw_state(connector)) {
3878 struct intel_encoder *encoder = connector->encoder;
3879 struct drm_crtc *crtc;
3880 bool encoder_enabled;
3881 enum pipe pipe;
3882
3883 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3884 connector->base.base.id,
3885 drm_get_connector_name(&connector->base));
3886
3887 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3888 "wrong connector dpms state\n");
3889 WARN(connector->base.encoder != &encoder->base,
3890 "active connector not linked to encoder\n");
3891 WARN(!encoder->connectors_active,
3892 "encoder->connectors_active not set\n");
3893
3894 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3895 WARN(!encoder_enabled, "encoder not enabled\n");
3896 if (WARN_ON(!encoder->base.crtc))
3897 return;
3898
3899 crtc = encoder->base.crtc;
3900
3901 WARN(!crtc->enabled, "crtc not enabled\n");
3902 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3903 WARN(pipe != to_intel_crtc(crtc)->pipe,
3904 "encoder active on the wrong pipe\n");
3905 }
79e53945
JB		 3906}
3907
5ab432ef
DV		 3908/* Even simpler default implementation, if there's really no special case to
3909 * consider. */
3910void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3911{
5ab432ef 3912 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3913
5ab432ef
DV		 3914 /* All the simple cases only support two dpms states. */
3915 if (mode != DRM_MODE_DPMS_ON)
3916 mode = DRM_MODE_DPMS_OFF;
d4270e57 3917
5ab432ef
DV		 3918 if (mode == connector->dpms)
3919 return;
3920
3921 connector->dpms = mode;
3922
3923 /* Only need to change hw state when actually enabled */
3924 if (encoder->base.crtc)
3925 intel_encoder_dpms(encoder, mode);
3926 else
8af6cf88 3927 WARN_ON(encoder->connectors_active != false);
0a91ca29 3928
b980514c 3929 intel_modeset_check_state(connector->dev);
79e53945
JB		 3930}
3931
f0947c37
DV		 3932/* Simple connector->get_hw_state implementation for encoders that support only
3933 * one connector and no cloning and hence the encoder state determines the state
3934 * of the connector. */
3935bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3936{
24929352 3937 enum pipe pipe = 0;
f0947c37 3938 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3939
f0947c37 3940 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3941}
3942
1857e1da
DV		 3943static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3944 struct intel_crtc_config *pipe_config)
3945{
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *pipe_B_crtc =
3948 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3949
3950 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3951 pipe_name(pipe), pipe_config->fdi_lanes);
3952 if (pipe_config->fdi_lanes > 4) {
3953 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3954 pipe_name(pipe), pipe_config->fdi_lanes);
3955 return false;
3956 }
3957
3958 if (IS_HASWELL(dev)) {
3959 if (pipe_config->fdi_lanes > 2) {
3960 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3961 pipe_config->fdi_lanes);
3962 return false;
3963 } else {
3964 return true;
3965 }
3966 }
3967
3968 if (INTEL_INFO(dev)->num_pipes == 2)
3969 return true;
3970
3971 /* Ivybridge 3 pipe is really complicated */
3972 switch (pipe) {
3973 case PIPE_A:
3974 return true;
3975 case PIPE_B:
3976 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3977 pipe_config->fdi_lanes > 2) {
3978 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3979 pipe_name(pipe), pipe_config->fdi_lanes);
3980 return false;
3981 }
3982 return true;
3983 case PIPE_C:
1e833f40 3984 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3985 pipe_B_crtc->config.fdi_lanes <= 2) {
3986 if (pipe_config->fdi_lanes > 2) {
3987 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3988 pipe_name(pipe), pipe_config->fdi_lanes);
3989 return false;
3990 }
3991 } else {
3992 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3993 return false;
3994 }
3995 return true;
3996 default:
3997 BUG();
3998 }
3999}
4000
e29c22c0
DV		 4001#define RETRY 1
4002static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4003 struct intel_crtc_config *pipe_config)
877d48d5 4004{
1857e1da 4005 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4006 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4007 int lane, link_bw, fdi_dotclock;
e29c22c0 4008 bool setup_ok, needs_recompute = false;
877d48d5 4009
e29c22c0 4010retry:
877d48d5
DV		 4011 /* FDI is a binary signal running at ~2.7GHz, encoding
4012 * each output octet as 10 bits. The actual frequency
4013 * is stored as a divider into a 100MHz clock, and the
4014 * mode pixel clock is stored in units of 1KHz.
4015 * Hence the bw of each lane in terms of the mode signal
4016 * is:
4017 */
4018 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4019
ff9a6750 4020 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4021 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4022
2bd89a07 4023 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4024 pipe_config->pipe_bpp);
4025
4026 pipe_config->fdi_lanes = lane;
4027
2bd89a07 4028 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4029 link_bw, &pipe_config->fdi_m_n);
1857e1da 4030
e29c22c0
DV		 4031 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4032 intel_crtc->pipe, pipe_config);
4033 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4034 pipe_config->pipe_bpp -= 2*3;
4035 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4036 pipe_config->pipe_bpp);
4037 needs_recompute = true;
4038 pipe_config->bw_constrained = true;
4039
4040 goto retry;
4041 }
4042
4043 if (needs_recompute)
4044 return RETRY;
4045
4046 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4047}
4048
42db64ef
PZ		 4049static void hsw_compute_ips_config(struct intel_crtc *crtc,
4050 struct intel_crtc_config *pipe_config)
4051{
3c4ca58c
PZ		 4052 pipe_config->ips_enabled = i915_enable_ips &&
4053 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4054 pipe_config->pipe_bpp == 24;
4055}
4056
a43f6e0f 4057static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4058 struct intel_crtc_config *pipe_config)
79e53945 4059{
a43f6e0f 4060 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4061 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4062
bad720ff 4063 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4064 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4065 if (pipe_config->requested_mode.clock * 3
4066 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4067 return -EINVAL;
2c07245f 4068 }
89749350 4069
f9bef081
DV		 4070 /* All interlaced capable intel hw wants timings in frames. Note though
4071 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4072 * timings, so we need to be careful not to clobber these.*/
7ae89233 4073 if (!pipe_config->timings_set)
f9bef081 4074 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4075
8693a824
DL		 4076 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4077 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4078 */
4079 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4080 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4081 return -EINVAL;
44f46b42 4082
bd080ee5 4083 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4084 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4085 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4086 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4087 * for lvds. */
4088 pipe_config->pipe_bpp = 8*3;
4089 }
4090
f5adf94e 4091 if (HAS_IPS(dev))
a43f6e0f
DV		 4092 hsw_compute_ips_config(crtc, pipe_config);
4093
4094 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4095 * clock survives for now. */
4096 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4097 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4098
877d48d5 4099 if (pipe_config->has_pch_encoder)
a43f6e0f 4100 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4101
e29c22c0 4102 return 0;
79e53945
JB		 4103}
4104
25eb05fc
JB		 4105static int valleyview_get_display_clock_speed(struct drm_device *dev)
4106{
4107 return 400000; /* FIXME */
4108}
4109
e70236a8
JB		 4110static int i945_get_display_clock_speed(struct drm_device *dev)
4111{
4112 return 400000;
4113}
79e53945 4114
e70236a8 4115static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4116{
e70236a8
JB		 4117 return 333000;
4118}
79e53945 4119
e70236a8
JB		 4120static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4121{
4122 return 200000;
4123}
79e53945 4124
e70236a8
JB		 4125static int i915gm_get_display_clock_speed(struct drm_device *dev)
4126{
4127 u16 gcfgc = 0;
79e53945 4128
e70236a8
JB		 4129 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4130
4131 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4132 return 133000;
4133 else {
4134 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4135 case GC_DISPLAY_CLOCK_333_MHZ:
4136 return 333000;
4137 default:
4138 case GC_DISPLAY_CLOCK_190_200_MHZ:
4139 return 190000;
79e53945 4140 }
e70236a8
JB		 4141 }
4142}
4143
4144static int i865_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 266000;
4147}
4148
4149static int i855_get_display_clock_speed(struct drm_device *dev)
4150{
4151 u16 hpllcc = 0;
4152 /* Assume that the hardware is in the high speed state. This
4153 * should be the default.
4154 */
4155 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4156 case GC_CLOCK_133_200:
4157 case GC_CLOCK_100_200:
4158 return 200000;
4159 case GC_CLOCK_166_250:
4160 return 250000;
4161 case GC_CLOCK_100_133:
79e53945 4162 return 133000;
e70236a8 4163 }
79e53945 4164
e70236a8
JB		 4165 /* Shouldn't happen */
4166 return 0;
4167}
79e53945 4168
e70236a8
JB		 4169static int i830_get_display_clock_speed(struct drm_device *dev)
4170{
4171 return 133000;
79e53945
JB		 4172}
4173
2c07245f 4174static void
a65851af 4175intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4176{
a65851af
VS		 4177 while (*num > DATA_LINK_M_N_MASK ||
4178 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4179 *num >>= 1;
4180 *den >>= 1;
4181 }
4182}
4183
a65851af
VS		 4184static void compute_m_n(unsigned int m, unsigned int n,
4185 uint32_t *ret_m, uint32_t *ret_n)
4186{
4187 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4188 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4189 intel_reduce_m_n_ratio(ret_m, ret_n);
4190}
4191
e69d0bc1
DV		 4192void
4193intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4194 int pixel_clock, int link_clock,
4195 struct intel_link_m_n *m_n)
2c07245f 4196{
e69d0bc1 4197 m_n->tu = 64;
a65851af
VS		 4198
4199 compute_m_n(bits_per_pixel * pixel_clock,
4200 link_clock * nlanes * 8,
4201 &m_n->gmch_m, &m_n->gmch_n);
4202
4203 compute_m_n(pixel_clock, link_clock,
4204 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4205}
4206
a7615030
CW		 4207static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4208{
72bbe58c
KP		 4209 if (i915_panel_use_ssc >= 0)
4210 return i915_panel_use_ssc != 0;
41aa3448 4211 return dev_priv->vbt.lvds_use_ssc
435793df 4212 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4213}
4214
a0c4da24
JB		 4215static int vlv_get_refclk(struct drm_crtc *crtc)
4216{
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 int refclk = 27000; /* for DP & HDMI */
4220
4221 return 100000; /* only one validated so far */
4222
4223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4224 refclk = 96000;
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 if (intel_panel_use_ssc(dev_priv))
4227 refclk = 100000;
4228 else
4229 refclk = 96000;
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4231 refclk = 100000;
4232 }
4233
4234 return refclk;
4235}
4236
c65d77d8
JB		 4237static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4238{
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 int refclk;
4242
a0c4da24
JB		 4243 if (IS_VALLEYVIEW(dev)) {
4244 refclk = vlv_get_refclk(crtc);
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4246 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4247 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4249 refclk / 1000);
4250 } else if (!IS_GEN2(dev)) {
4251 refclk = 96000;
4252 } else {
4253 refclk = 48000;
4254 }
4255
4256 return refclk;
4257}
4258
7429e9d4 4259static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4260{
7df00d7a 4261 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4262}
f47709a9 4263
7429e9d4
DV		 4264static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4265{
4266 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4267}
4268
f47709a9 4269static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4270 intel_clock_t *reduced_clock)
4271{
f47709a9 4272 struct drm_device *dev = crtc->base.dev;
a7516a05 4273 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4274 int pipe = crtc->pipe;
a7516a05
JB		 4275 u32 fp, fp2 = 0;
4276
4277 if (IS_PINEVIEW(dev)) {
7429e9d4 4278 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4279 if (reduced_clock)
7429e9d4 4280 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4281 } else {
7429e9d4 4282 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4283 if (reduced_clock)
7429e9d4 4284 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4285 }
4286
4287 I915_WRITE(FP0(pipe), fp);
8bcc2795 4288 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4289
f47709a9
DV		 4290 crtc->lowfreq_avail = false;
4291 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4292 reduced_clock && i915_powersave) {
4293 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4294 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4295 crtc->lowfreq_avail = true;
a7516a05
JB		 4296 } else {
4297 I915_WRITE(FP1(pipe), fp);
8bcc2795 4298 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4299 }
4300}
4301
89b667f8
JB		 4302static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4303{
4304 u32 reg_val;
4305
4306 /*
4307 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4308 * and set it to a reasonable value instead.
4309 */
ae99258f 4310 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4311 reg_val &= 0xffffff00;
4312 reg_val |= 0x00000030;
ae99258f 4313 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4314
ae99258f 4315 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4316 reg_val &= 0x8cffffff;
4317 reg_val = 0x8c000000;
ae99258f 4318 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4319
ae99258f 4320 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4321 reg_val &= 0xffffff00;
ae99258f 4322 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4323
ae99258f 4324 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4325 reg_val &= 0x00ffffff;
4326 reg_val |= 0xb0000000;
ae99258f 4327 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4328}
4329
b551842d
DV		 4330static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4331 struct intel_link_m_n *m_n)
4332{
4333 struct drm_device *dev = crtc->base.dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 int pipe = crtc->pipe;
4336
e3b95f1e
DV		 4337 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4338 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4339 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4340 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4341}
4342
4343static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4344 struct intel_link_m_n *m_n)
4345{
4346 struct drm_device *dev = crtc->base.dev;
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 int pipe = crtc->pipe;
4349 enum transcoder transcoder = crtc->config.cpu_transcoder;
4350
4351 if (INTEL_INFO(dev)->gen >= 5) {
4352 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4353 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4354 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4355 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4356 } else {
e3b95f1e
DV		 4357 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4359 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4360 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4361 }
4362}
4363
03afc4a2
DV		 4364static void intel_dp_set_m_n(struct intel_crtc *crtc)
4365{
4366 if (crtc->config.has_pch_encoder)
4367 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4368 else
4369 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4370}
4371
f47709a9 4372static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4373{
f47709a9 4374 struct drm_device *dev = crtc->base.dev;
a0c4da24 4375 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4376 struct intel_encoder *encoder;
f47709a9 4377 int pipe = crtc->pipe;
89b667f8 4378 u32 dpll, mdiv;
a0c4da24 4379 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4380 bool is_hdmi;
198a037f 4381 u32 coreclk, reg_val, dpll_md;
a0c4da24 4382
09153000
DV		 4383 mutex_lock(&dev_priv->dpio_lock);
4384
89b667f8 4385 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4386
f47709a9
DV		 4387 bestn = crtc->config.dpll.n;
4388 bestm1 = crtc->config.dpll.m1;
4389 bestm2 = crtc->config.dpll.m2;
4390 bestp1 = crtc->config.dpll.p1;
4391 bestp2 = crtc->config.dpll.p2;
a0c4da24 4392
89b667f8
JB		 4393 /* See eDP HDMI DPIO driver vbios notes doc */
4394
4395 /* PLL B needs special handling */
4396 if (pipe)
4397 vlv_pllb_recal_opamp(dev_priv);
4398
4399 /* Set up Tx target for periodic Rcomp update */
ae99258f 4400 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4401
4402 /* Disable target IRef on PLL */
ae99258f 4403 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4404 reg_val &= 0x00ffffff;
ae99258f 4405 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4406
4407 /* Disable fast lock */
ae99258f 4408 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4409
4410 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4411 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4412 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4413 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4414 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4415
4416 /*
4417 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4418 * but we don't support that).
4419 * Note: don't use the DAC post divider as it seems unstable.
4420 */
4421 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4423
a0c4da24 4424 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4425 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4426
89b667f8 4427 /* Set HBR and RBR LPF coefficients */
ff9a6750 4428 if (crtc->config.port_clock == 162000 ||
99750bd4 4429 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4430 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4431 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4432 0x005f0021);
4433 else
4abb2c39 4434 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4435 0x00d0000f);
4436
4437 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4438 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4439 /* Use SSC source */
4440 if (!pipe)
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4442 0x0df40000);
4443 else
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4445 0x0df70000);
4446 } else { /* HDMI or VGA */
4447 /* Use bend source */
4448 if (!pipe)
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4450 0x0df70000);
4451 else
ae99258f 4452 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4453 0x0df40000);
4454 }
a0c4da24 4455
ae99258f 4456 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4457 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4458 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4460 coreclk |= 0x01000000;
ae99258f 4461 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4462
ae99258f 4463 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4464
89b667f8
JB		 4465 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4466 if (encoder->pre_pll_enable)
4467 encoder->pre_pll_enable(encoder);
a0c4da24 4468
89b667f8
JB		 4469 /* Enable DPIO clock input */
4470 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4471 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4472 if (pipe)
4473 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4474
4475 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4476 crtc->config.dpll_hw_state.dpll = dpll;
4477
a0c4da24
JB		 4478 I915_WRITE(DPLL(pipe), dpll);
4479 POSTING_READ(DPLL(pipe));
2a8f64ca 4480 udelay(150);
a0c4da24 4481
a0c4da24
JB		 4482 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4483 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4484
ef1b460d
DV		 4485 dpll_md = (crtc->config.pixel_multiplier - 1)
4486 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4487 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4488
198a037f 4489 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4490 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4491
89b667f8
JB		 4492 if (crtc->config.has_dp_encoder)
4493 intel_dp_set_m_n(crtc);
09153000
DV		 4494
4495 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4496}
4497
f47709a9
DV		 4498static void i9xx_update_pll(struct intel_crtc *crtc,
4499 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4500 int num_connectors)
4501{
f47709a9 4502 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4503 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4504 u32 dpll;
4505 bool is_sdvo;
f47709a9 4506 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4507
f47709a9 4508 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4509
f47709a9
DV		 4510 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4511 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4512
4513 dpll = DPLL_VGA_MODE_DIS;
4514
f47709a9 4515 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4516 dpll |= DPLLB_MODE_LVDS;
4517 else
4518 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4519
ef1b460d 4520 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4521 dpll |= (crtc->config.pixel_multiplier - 1)
4522 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4523 }
198a037f
DV		 4524
4525 if (is_sdvo)
4526 dpll |= DPLL_DVO_HIGH_SPEED;
4527
f47709a9 4528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4529 dpll |= DPLL_DVO_HIGH_SPEED;
4530
4531 /* compute bitmask from p1 value */
4532 if (IS_PINEVIEW(dev))
4533 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4534 else {
4535 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4536 if (IS_G4X(dev) && reduced_clock)
4537 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4538 }
4539 switch (clock->p2) {
4540 case 5:
4541 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4542 break;
4543 case 7:
4544 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4545 break;
4546 case 10:
4547 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4548 break;
4549 case 14:
4550 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4551 break;
4552 }
4553 if (INTEL_INFO(dev)->gen >= 4)
4554 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4555
09ede541 4556 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4557 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4558 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4559 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4560 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4561 else
4562 dpll |= PLL_REF_INPUT_DREFCLK;
4563
4564 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4565 crtc->config.dpll_hw_state.dpll = dpll;
4566
eb1cbe48 4567 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4568 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4569 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4570 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4571 }
66e3d5c0
DV		 4572
4573 if (crtc->config.has_dp_encoder)
4574 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4575}
4576
f47709a9 4577static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4578 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4579 int num_connectors)
4580{
f47709a9 4581 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4582 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4583 u32 dpll;
f47709a9 4584 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4585
f47709a9 4586 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4587
eb1cbe48
DV		 4588 dpll = DPLL_VGA_MODE_DIS;
4589
f47709a9 4590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 } else {
4593 if (clock->p1 == 2)
4594 dpll |= PLL_P1_DIVIDE_BY_TWO;
4595 else
4596 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 if (clock->p2 == 4)
4598 dpll |= PLL_P2_DIVIDE_BY_4;
4599 }
4600
f47709a9 4601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604 else
4605 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4608 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4609}
4610
8a654f3b 4611static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4612{
4613 struct drm_device *dev = intel_crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4616 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4617 struct drm_display_mode *adjusted_mode =
4618 &intel_crtc->config.adjusted_mode;
4619 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4620 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4621
4622 /* We need to be careful not to changed the adjusted mode, for otherwise
4623 * the hw state checker will get angry at the mismatch. */
4624 crtc_vtotal = adjusted_mode->crtc_vtotal;
4625 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4626
4627 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4628 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4629 crtc_vtotal -= 1;
4630 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4631 vsyncshift = adjusted_mode->crtc_hsync_start
4632 - adjusted_mode->crtc_htotal / 2;
4633 } else {
4634 vsyncshift = 0;
4635 }
4636
4637 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4638 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4639
fe2b8f9d 4640 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4641 (adjusted_mode->crtc_hdisplay - 1) |
4642 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4643 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4644 (adjusted_mode->crtc_hblank_start - 1) |
4645 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4646 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4647 (adjusted_mode->crtc_hsync_start - 1) |
4648 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4649
fe2b8f9d 4650 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4651 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4652 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4653 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4654 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4655 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4656 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4657 (adjusted_mode->crtc_vsync_start - 1) |
4658 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4659
b5e508d4
PZ		 4660 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4661 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4662 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4663 * bits. */
4664 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4665 (pipe == PIPE_B || pipe == PIPE_C))
4666 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4667
b0e77b9c
PZ		 4668 /* pipesrc controls the size that is scaled from, which should
4669 * always be the user's requested size.
4670 */
4671 I915_WRITE(PIPESRC(pipe),
4672 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4673}
4674
1bd1bd80
DV		 4675static void intel_get_pipe_timings(struct intel_crtc *crtc,
4676 struct intel_crtc_config *pipe_config)
4677{
4678 struct drm_device *dev = crtc->base.dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4681 uint32_t tmp;
4682
4683 tmp = I915_READ(HTOTAL(cpu_transcoder));
4684 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4685 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4686 tmp = I915_READ(HBLANK(cpu_transcoder));
4687 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4688 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4689 tmp = I915_READ(HSYNC(cpu_transcoder));
4690 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4691 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4692
4693 tmp = I915_READ(VTOTAL(cpu_transcoder));
4694 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4695 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4696 tmp = I915_READ(VBLANK(cpu_transcoder));
4697 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4698 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4699 tmp = I915_READ(VSYNC(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4702
4703 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4704 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4705 pipe_config->adjusted_mode.crtc_vtotal += 1;
4706 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4707 }
4708
4709 tmp = I915_READ(PIPESRC(crtc->pipe));
4710 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4712}
4713
84b046f3
DV		 4714static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4715{
4716 struct drm_device *dev = intel_crtc->base.dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 uint32_t pipeconf;
4719
9f11a9e4 4720 pipeconf = 0;
84b046f3
DV		 4721
4722 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4723 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4724 * core speed.
4725 *
4726 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4727 * pipe == 0 check?
4728 */
4729 if (intel_crtc->config.requested_mode.clock >
4730 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4731 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4732 }
4733
ff9ce46e
DV		 4734 /* only g4x and later have fancy bpc/dither controls */
4735 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4736 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4737 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4738 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4739 PIPECONF_DITHER_TYPE_SP;
84b046f3 4740
ff9ce46e
DV		 4741 switch (intel_crtc->config.pipe_bpp) {
4742 case 18:
4743 pipeconf |= PIPECONF_6BPC;
4744 break;
4745 case 24:
4746 pipeconf |= PIPECONF_8BPC;
4747 break;
4748 case 30:
4749 pipeconf |= PIPECONF_10BPC;
4750 break;
4751 default:
4752 /* Case prevented by intel_choose_pipe_bpp_dither. */
4753 BUG();
84b046f3
DV		 4754 }
4755 }
4756
4757 if (HAS_PIPE_CXSR(dev)) {
4758 if (intel_crtc->lowfreq_avail) {
4759 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4760 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4761 } else {
4762 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4763 }
4764 }
4765
84b046f3
DV		 4766 if (!IS_GEN2(dev) &&
4767 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4768 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4769 else
4770 pipeconf |= PIPECONF_PROGRESSIVE;
4771
9f11a9e4
DV		 4772 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4773 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4774
84b046f3
DV		 4775 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4776 POSTING_READ(PIPECONF(intel_crtc->pipe));
4777}
4778
f564048e 4779static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4780 int x, int y,
94352cf9 4781 struct drm_framebuffer *fb)
79e53945
JB		 4782{
4783 struct drm_device *dev = crtc->dev;
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4786 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4787 int pipe = intel_crtc->pipe;
80824003 4788 int plane = intel_crtc->plane;
c751ce4f 4789 int refclk, num_connectors = 0;
652c393a 4790 intel_clock_t clock, reduced_clock;
84b046f3 4791 u32 dspcntr;
a16af721
DV		 4792 bool ok, has_reduced_clock = false;
4793 bool is_lvds = false;
5eddb70b 4794 struct intel_encoder *encoder;
d4906093 4795 const intel_limit_t *limit;
5c3b82e2 4796 int ret;
79e53945 4797
6c2b7c12 4798 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4799 switch (encoder->type) {
79e53945
JB		 4800 case INTEL_OUTPUT_LVDS:
4801 is_lvds = true;
4802 break;
79e53945 4803 }
43565a06 4804
c751ce4f 4805 num_connectors++;
79e53945
JB		 4806 }
4807
c65d77d8 4808 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4809
d4906093
ML		 4810 /*
4811 * Returns a set of divisors for the desired target clock with the given
4812 * refclk, or FALSE. The returned values represent the clock equation:
4813 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4814 */
1b894b59 4815 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4816 ok = dev_priv->display.find_dpll(limit, crtc,
4817 intel_crtc->config.port_clock,
ee9300bb
DV		 4818 refclk, NULL, &clock);
4819 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4820 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4821 return -EINVAL;
79e53945
JB		 4822 }
4823
cda4b7d3 4824 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4825 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4826
ddc9003c 4827 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4828 /*
4829 * Ensure we match the reduced clock's P to the target clock.
4830 * If the clocks don't match, we can't switch the display clock
4831 * by using the FP0/FP1. In such case we will disable the LVDS
4832 * downclock feature.
4833 */
ee9300bb
DV		 4834 has_reduced_clock =
4835 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4836 dev_priv->lvds_downclock,
ee9300bb 4837 refclk, &clock,
5eddb70b 4838 &reduced_clock);
7026d4ac 4839 }
f47709a9
DV		 4840 /* Compat-code for transition, will disappear. */
4841 if (!intel_crtc->config.clock_set) {
4842 intel_crtc->config.dpll.n = clock.n;
4843 intel_crtc->config.dpll.m1 = clock.m1;
4844 intel_crtc->config.dpll.m2 = clock.m2;
4845 intel_crtc->config.dpll.p1 = clock.p1;
4846 intel_crtc->config.dpll.p2 = clock.p2;
4847 }
7026d4ac 4848
eb1cbe48 4849 if (IS_GEN2(dev))
8a654f3b 4850 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4851 has_reduced_clock ? &reduced_clock : NULL,
4852 num_connectors);
a0c4da24 4853 else if (IS_VALLEYVIEW(dev))
f47709a9 4854 vlv_update_pll(intel_crtc);
79e53945 4855 else
f47709a9 4856 i9xx_update_pll(intel_crtc,
eb1cbe48 4857 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4858 num_connectors);
79e53945 4859
79e53945
JB		 4860 /* Set up the display plane register */
4861 dspcntr = DISPPLANE_GAMMA_ENABLE;
4862
da6ecc5d
JB		 4863 if (!IS_VALLEYVIEW(dev)) {
4864 if (pipe == 0)
4865 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4866 else
4867 dspcntr |= DISPPLANE_SEL_PIPE_B;
4868 }
79e53945 4869
8a654f3b 4870 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4871
4872 /* pipesrc and dspsize control the size that is scaled from,
4873 * which should always be the user's requested size.
79e53945 4874 */
929c77fb
EA		 4875 I915_WRITE(DSPSIZE(plane),
4876 ((mode->vdisplay - 1) << 16) |
4877 (mode->hdisplay - 1));
4878 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4879
84b046f3
DV		 4880 i9xx_set_pipeconf(intel_crtc);
4881
f564048e
EA		 4882 I915_WRITE(DSPCNTR(plane), dspcntr);
4883 POSTING_READ(DSPCNTR(plane));
4884
94352cf9 4885 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4886
4887 intel_update_watermarks(dev);
4888
f564048e
EA		 4889 return ret;
4890}
4891
2fa2fe9a
DV		 4892static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4893 struct intel_crtc_config *pipe_config)
4894{
4895 struct drm_device *dev = crtc->base.dev;
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897 uint32_t tmp;
4898
4899 tmp = I915_READ(PFIT_CONTROL);
4900
4901 if (INTEL_INFO(dev)->gen < 4) {
4902 if (crtc->pipe != PIPE_B)
4903 return;
4904
4905 /* gen2/3 store dither state in pfit control, needs to match */
4906 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4907 } else {
4908 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4909 return;
4910 }
4911
4912 if (!(tmp & PFIT_ENABLE))
4913 return;
4914
4915 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4916 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4917 if (INTEL_INFO(dev)->gen < 5)
4918 pipe_config->gmch_pfit.lvds_border_bits =
4919 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4920}
4921
0e8ffe1b
DV		 4922static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4923 struct intel_crtc_config *pipe_config)
4924{
4925 struct drm_device *dev = crtc->base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 uint32_t tmp;
4928
eccb140b 4929 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4930 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4931
0e8ffe1b
DV		 4932 tmp = I915_READ(PIPECONF(crtc->pipe));
4933 if (!(tmp & PIPECONF_ENABLE))
4934 return false;
4935
1bd1bd80
DV		 4936 intel_get_pipe_timings(crtc, pipe_config);
4937
2fa2fe9a
DV		 4938 i9xx_get_pfit_config(crtc, pipe_config);
4939
6c49f241
DV		 4940 if (INTEL_INFO(dev)->gen >= 4) {
4941 tmp = I915_READ(DPLL_MD(crtc->pipe));
4942 pipe_config->pixel_multiplier =
4943 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4944 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4945 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4946 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4947 tmp = I915_READ(DPLL(crtc->pipe));
4948 pipe_config->pixel_multiplier =
4949 ((tmp & SDVO_MULTIPLIER_MASK)
4950 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4951 } else {
4952 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4953 * port and will be fixed up in the encoder->get_config
4954 * function. */
4955 pipe_config->pixel_multiplier = 1;
4956 }
8bcc2795
DV		 4957 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4958 if (!IS_VALLEYVIEW(dev)) {
4959 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4960 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 4961 } else {
4962 /* Mask out read-only status bits. */
4963 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
4964 DPLL_PORTC_READY_MASK |
4965 DPLL_PORTB_READY_MASK);
8bcc2795 4966 }
6c49f241 4967
0e8ffe1b
DV		 4968 return true;
4969}
4970
dde86e2d 4971static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4972{
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4975 struct intel_encoder *encoder;
74cfd7ac 4976 u32 val, final;
13d83a67 4977 bool has_lvds = false;
199e5d79 4978 bool has_cpu_edp = false;
199e5d79 4979 bool has_panel = false;
99eb6a01
KP		 4980 bool has_ck505 = false;
4981 bool can_ssc = false;
13d83a67
JB		 4982
4983 /* We need to take the global config into account */
199e5d79
KP		 4984 list_for_each_entry(encoder, &mode_config->encoder_list,
4985 base.head) {
4986 switch (encoder->type) {
4987 case INTEL_OUTPUT_LVDS:
4988 has_panel = true;
4989 has_lvds = true;
4990 break;
4991 case INTEL_OUTPUT_EDP:
4992 has_panel = true;
2de6905f 4993 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4994 has_cpu_edp = true;
4995 break;
13d83a67
JB		 4996 }
4997 }
4998
99eb6a01 4999 if (HAS_PCH_IBX(dev)) {
41aa3448 5000 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5001 can_ssc = has_ck505;
5002 } else {
5003 has_ck505 = false;
5004 can_ssc = true;
5005 }
5006
2de6905f
ID		 5007 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5008 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5009
5010 /* Ironlake: try to setup display ref clock before DPLL
5011 * enabling. This is only under driver's control after
5012 * PCH B stepping, previous chipset stepping should be
5013 * ignoring this setting.
5014 */
74cfd7ac
CW		 5015 val = I915_READ(PCH_DREF_CONTROL);
5016
5017 /* As we must carefully and slowly disable/enable each source in turn,
5018 * compute the final state we want first and check if we need to
5019 * make any changes at all.
5020 */
5021 final = val;
5022 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5023 if (has_ck505)
5024 final |= DREF_NONSPREAD_CK505_ENABLE;
5025 else
5026 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5027
5028 final &= ~DREF_SSC_SOURCE_MASK;
5029 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5030 final &= ~DREF_SSC1_ENABLE;
5031
5032 if (has_panel) {
5033 final |= DREF_SSC_SOURCE_ENABLE;
5034
5035 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5036 final |= DREF_SSC1_ENABLE;
5037
5038 if (has_cpu_edp) {
5039 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5040 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5041 else
5042 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5043 } else
5044 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5045 } else {
5046 final |= DREF_SSC_SOURCE_DISABLE;
5047 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5048 }
5049
5050 if (final == val)
5051 return;
5052
13d83a67 5053 /* Always enable nonspread source */
74cfd7ac 5054 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5055
99eb6a01 5056 if (has_ck505)
74cfd7ac 5057 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5058 else
74cfd7ac 5059 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5060
199e5d79 5061 if (has_panel) {
74cfd7ac
CW		 5062 val &= ~DREF_SSC_SOURCE_MASK;
5063 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5064
199e5d79 5065 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5066 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5067 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5068 val |= DREF_SSC1_ENABLE;
e77166b5 5069 } else
74cfd7ac 5070 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5071
5072 /* Get SSC going before enabling the outputs */
74cfd7ac 5073 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5074 POSTING_READ(PCH_DREF_CONTROL);
5075 udelay(200);
5076
74cfd7ac 5077 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5078
5079 /* Enable CPU source on CPU attached eDP */
199e5d79 5080 if (has_cpu_edp) {
99eb6a01 5081 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5082 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5083 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5084 }
13d83a67 5085 else
74cfd7ac 5086 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5087 } else
74cfd7ac 5088 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5089
74cfd7ac 5090 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5091 POSTING_READ(PCH_DREF_CONTROL);
5092 udelay(200);
5093 } else {
5094 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5095
74cfd7ac 5096 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5097
5098 /* Turn off CPU output */
74cfd7ac 5099 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5100
74cfd7ac 5101 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5102 POSTING_READ(PCH_DREF_CONTROL);
5103 udelay(200);
5104
5105 /* Turn off the SSC source */
74cfd7ac
CW		 5106 val &= ~DREF_SSC_SOURCE_MASK;
5107 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5108
5109 /* Turn off SSC1 */
74cfd7ac 5110 val &= ~DREF_SSC1_ENABLE;
199e5d79 5111
74cfd7ac 5112 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5113 POSTING_READ(PCH_DREF_CONTROL);
5114 udelay(200);
5115 }
74cfd7ac
CW		 5116
5117 BUG_ON(val != final);
13d83a67
JB		 5118}
5119
dde86e2d
PZ		 5120/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5121static void lpt_init_pch_refclk(struct drm_device *dev)
5122{
5123 struct drm_i915_private *dev_priv = dev->dev_private;
5124 struct drm_mode_config *mode_config = &dev->mode_config;
5125 struct intel_encoder *encoder;
5126 bool has_vga = false;
5127 bool is_sdv = false;
5128 u32 tmp;
5129
5130 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5131 switch (encoder->type) {
5132 case INTEL_OUTPUT_ANALOG:
5133 has_vga = true;
5134 break;
5135 }
5136 }
5137
5138 if (!has_vga)
5139 return;
5140
c00db246
DV		 5141 mutex_lock(&dev_priv->dpio_lock);
5142
dde86e2d
PZ		 5143 /* XXX: Rip out SDV support once Haswell ships for real. */
5144 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5145 is_sdv = true;
5146
5147 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5148 tmp &= ~SBI_SSCCTL_DISABLE;
5149 tmp |= SBI_SSCCTL_PATHALT;
5150 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5151
5152 udelay(24);
5153
5154 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5155 tmp &= ~SBI_SSCCTL_PATHALT;
5156 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5157
5158 if (!is_sdv) {
5159 tmp = I915_READ(SOUTH_CHICKEN2);
5160 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5161 I915_WRITE(SOUTH_CHICKEN2, tmp);
5162
5163 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5164 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5165 DRM_ERROR("FDI mPHY reset assert timeout\n");
5166
5167 tmp = I915_READ(SOUTH_CHICKEN2);
5168 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5169 I915_WRITE(SOUTH_CHICKEN2, tmp);
5170
5171 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5172 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5173 100))
5174 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5175 }
5176
5177 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5178 tmp &= ~(0xFF << 24);
5179 tmp |= (0x12 << 24);
5180 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5181
dde86e2d
PZ		 5182 if (is_sdv) {
5183 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5184 tmp |= 0x7FFF;
5185 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5186 }
5187
5188 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5189 tmp |= (1 << 11);
5190 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5191
5192 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5193 tmp |= (1 << 11);
5194 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5195
5196 if (is_sdv) {
5197 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5198 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5199 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5200
5201 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5202 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5203 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5204
5205 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5206 tmp |= (0x3F << 8);
5207 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5208
5209 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5210 tmp |= (0x3F << 8);
5211 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5212 }
5213
5214 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5215 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5216 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5217
5218 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5219 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5220 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5221
5222 if (!is_sdv) {
5223 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5224 tmp &= ~(7 << 13);
5225 tmp |= (5 << 13);
5226 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5227
5228 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5229 tmp &= ~(7 << 13);
5230 tmp |= (5 << 13);
5231 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5232 }
5233
5234 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5235 tmp &= ~0xFF;
5236 tmp |= 0x1C;
5237 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5240 tmp &= ~0xFF;
5241 tmp |= 0x1C;
5242 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5245 tmp &= ~(0xFF << 16);
5246 tmp |= (0x1C << 16);
5247 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5250 tmp &= ~(0xFF << 16);
5251 tmp |= (0x1C << 16);
5252 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5253
5254 if (!is_sdv) {
5255 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5256 tmp |= (1 << 27);
5257 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5258
5259 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5260 tmp |= (1 << 27);
5261 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5264 tmp &= ~(0xF << 28);
5265 tmp |= (4 << 28);
5266 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5269 tmp &= ~(0xF << 28);
5270 tmp |= (4 << 28);
5271 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5272 }
5273
5274 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5275 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5276 tmp |= SBI_DBUFF0_ENABLE;
5277 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5278
5279 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5280}
5281
5282/*
5283 * Initialize reference clocks when the driver loads
5284 */
5285void intel_init_pch_refclk(struct drm_device *dev)
5286{
5287 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5288 ironlake_init_pch_refclk(dev);
5289 else if (HAS_PCH_LPT(dev))
5290 lpt_init_pch_refclk(dev);
5291}
5292
d9d444cb
JB		 5293static int ironlake_get_refclk(struct drm_crtc *crtc)
5294{
5295 struct drm_device *dev = crtc->dev;
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 struct intel_encoder *encoder;
d9d444cb
JB		 5298 int num_connectors = 0;
5299 bool is_lvds = false;
5300
6c2b7c12 5301 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5302 switch (encoder->type) {
5303 case INTEL_OUTPUT_LVDS:
5304 is_lvds = true;
5305 break;
d9d444cb
JB		 5306 }
5307 num_connectors++;
5308 }
5309
5310 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5311 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5312 dev_priv->vbt.lvds_ssc_freq);
5313 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5314 }
5315
5316 return 120000;
5317}
5318
6ff93609 5319static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5320{
c8203565 5321 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323 int pipe = intel_crtc->pipe;
c8203565
PZ		 5324 uint32_t val;
5325
78114071 5326 val = 0;
c8203565 5327
965e0c48 5328 switch (intel_crtc->config.pipe_bpp) {
c8203565 5329 case 18:
dfd07d72 5330 val |= PIPECONF_6BPC;
c8203565
PZ		 5331 break;
5332 case 24:
dfd07d72 5333 val |= PIPECONF_8BPC;
c8203565
PZ		 5334 break;
5335 case 30:
dfd07d72 5336 val |= PIPECONF_10BPC;
c8203565
PZ		 5337 break;
5338 case 36:
dfd07d72 5339 val |= PIPECONF_12BPC;
c8203565
PZ		 5340 break;
5341 default:
cc769b62
PZ		 5342 /* Case prevented by intel_choose_pipe_bpp_dither. */
5343 BUG();
c8203565
PZ		 5344 }
5345
d8b32247 5346 if (intel_crtc->config.dither)
c8203565
PZ		 5347 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5348
6ff93609 5349 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5350 val |= PIPECONF_INTERLACED_ILK;
5351 else
5352 val |= PIPECONF_PROGRESSIVE;
5353
50f3b016 5354 if (intel_crtc->config.limited_color_range)
3685a8f3 5355 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5356
c8203565
PZ		 5357 I915_WRITE(PIPECONF(pipe), val);
5358 POSTING_READ(PIPECONF(pipe));
5359}
5360
86d3efce
VS		 5361/*
5362 * Set up the pipe CSC unit.
5363 *
5364 * Currently only full range RGB to limited range RGB conversion
5365 * is supported, but eventually this should handle various
5366 * RGB<->YCbCr scenarios as well.
5367 */
50f3b016 5368static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5369{
5370 struct drm_device *dev = crtc->dev;
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373 int pipe = intel_crtc->pipe;
5374 uint16_t coeff = 0x7800; /* 1.0 */
5375
5376 /*
5377 * TODO: Check what kind of values actually come out of the pipe
5378 * with these coeff/postoff values and adjust to get the best
5379 * accuracy. Perhaps we even need to take the bpc value into
5380 * consideration.
5381 */
5382
50f3b016 5383 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5384 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5385
5386 /*
5387 * GY/GU and RY/RU should be the other way around according
5388 * to BSpec, but reality doesn't agree. Just set them up in
5389 * a way that results in the correct picture.
5390 */
5391 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5392 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5393
5394 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5395 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5396
5397 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5398 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5399
5400 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5401 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5402 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5403
5404 if (INTEL_INFO(dev)->gen > 6) {
5405 uint16_t postoff = 0;
5406
50f3b016 5407 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5408 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5409
5410 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5411 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5412 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5413
5414 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5415 } else {
5416 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5417
50f3b016 5418 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5419 mode |= CSC_BLACK_SCREEN_OFFSET;
5420
5421 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5422 }
5423}
5424
6ff93609 5425static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5426{
5427 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5429 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5430 uint32_t val;
5431
3eff4faa 5432 val = 0;
ee2b0b38 5433
d8b32247 5434 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5435 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5436
6ff93609 5437 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5438 val |= PIPECONF_INTERLACED_ILK;
5439 else
5440 val |= PIPECONF_PROGRESSIVE;
5441
702e7a56
PZ		 5442 I915_WRITE(PIPECONF(cpu_transcoder), val);
5443 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5444
5445 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5446 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5447}
5448
6591c6e4 5449static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5450 intel_clock_t *clock,
5451 bool *has_reduced_clock,
5452 intel_clock_t *reduced_clock)
5453{
5454 struct drm_device *dev = crtc->dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct intel_encoder *intel_encoder;
5457 int refclk;
d4906093 5458 const intel_limit_t *limit;
a16af721 5459 bool ret, is_lvds = false;
79e53945 5460
6591c6e4
PZ		 5461 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5462 switch (intel_encoder->type) {
79e53945
JB		 5463 case INTEL_OUTPUT_LVDS:
5464 is_lvds = true;
5465 break;
79e53945
JB		 5466 }
5467 }
5468
d9d444cb 5469 refclk = ironlake_get_refclk(crtc);
79e53945 5470
d4906093
ML		 5471 /*
5472 * Returns a set of divisors for the desired target clock with the given
5473 * refclk, or FALSE. The returned values represent the clock equation:
5474 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5475 */
1b894b59 5476 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5477 ret = dev_priv->display.find_dpll(limit, crtc,
5478 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5479 refclk, NULL, clock);
6591c6e4
PZ		 5480 if (!ret)
5481 return false;
cda4b7d3 5482
ddc9003c 5483 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5484 /*
5485 * Ensure we match the reduced clock's P to the target clock.
5486 * If the clocks don't match, we can't switch the display clock
5487 * by using the FP0/FP1. In such case we will disable the LVDS
5488 * downclock feature.
5489 */
ee9300bb
DV		 5490 *has_reduced_clock =
5491 dev_priv->display.find_dpll(limit, crtc,
5492 dev_priv->lvds_downclock,
5493 refclk, clock,
5494 reduced_clock);
652c393a 5495 }
61e9653f 5496
6591c6e4
PZ		 5497 return true;
5498}
5499
01a415fd
DV		 5500static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5501{
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 uint32_t temp;
5504
5505 temp = I915_READ(SOUTH_CHICKEN1);
5506 if (temp & FDI_BC_BIFURCATION_SELECT)
5507 return;
5508
5509 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5510 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5511
5512 temp |= FDI_BC_BIFURCATION_SELECT;
5513 DRM_DEBUG_KMS("enabling fdi C rx\n");
5514 I915_WRITE(SOUTH_CHICKEN1, temp);
5515 POSTING_READ(SOUTH_CHICKEN1);
5516}
5517
ebfd86fd 5518static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5519{
5520 struct drm_device *dev = intel_crtc->base.dev;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5522
5523 switch (intel_crtc->pipe) {
5524 case PIPE_A:
ebfd86fd 5525 break;
01a415fd 5526 case PIPE_B:
ebfd86fd 5527 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5528 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5529 else
5530 cpt_enable_fdi_bc_bifurcation(dev);
5531
ebfd86fd 5532 break;
01a415fd 5533 case PIPE_C:
01a415fd
DV		 5534 cpt_enable_fdi_bc_bifurcation(dev);
5535
ebfd86fd 5536 break;
01a415fd
DV		 5537 default:
5538 BUG();
5539 }
5540}
5541
d4b1931c
PZ		 5542int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5543{
5544 /*
5545 * Account for spread spectrum to avoid
5546 * oversubscribing the link. Max center spread
5547 * is 2.5%; use 5% for safety's sake.
5548 */
5549 u32 bps = target_clock * bpp * 21 / 20;
5550 return bps / (link_bw * 8) + 1;
5551}
5552
7429e9d4 5553static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5554{
7429e9d4 5555 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5556}
5557
de13a2e3 5558static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5559 u32 *fp,
9a7c7890 5560 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5561{
de13a2e3 5562 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5563 struct drm_device *dev = crtc->dev;
5564 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5565 struct intel_encoder *intel_encoder;
5566 uint32_t dpll;
6cc5f341 5567 int factor, num_connectors = 0;
09ede541 5568 bool is_lvds = false, is_sdvo = false;
79e53945 5569
de13a2e3
PZ		 5570 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5571 switch (intel_encoder->type) {
79e53945
JB		 5572 case INTEL_OUTPUT_LVDS:
5573 is_lvds = true;
5574 break;
5575 case INTEL_OUTPUT_SDVO:
7d57382e 5576 case INTEL_OUTPUT_HDMI:
79e53945 5577 is_sdvo = true;
79e53945 5578 break;
79e53945 5579 }
43565a06 5580
c751ce4f 5581 num_connectors++;
79e53945 5582 }
79e53945 5583
c1858123 5584 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5585 factor = 21;
5586 if (is_lvds) {
5587 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5588 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5589 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5590 factor = 25;
09ede541 5591 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5592 factor = 20;
c1858123 5593
7429e9d4 5594 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5595 *fp |= FP_CB_TUNE;
2c07245f 5596
9a7c7890
DV		 5597 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5598 *fp2 |= FP_CB_TUNE;
5599
5eddb70b 5600 dpll = 0;
2c07245f 5601
a07d6787
EA		 5602 if (is_lvds)
5603 dpll |= DPLLB_MODE_LVDS;
5604 else
5605 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5606
ef1b460d
DV		 5607 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5608 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5609
5610 if (is_sdvo)
5611 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5612 if (intel_crtc->config.has_dp_encoder)
a07d6787 5613 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5614
a07d6787 5615 /* compute bitmask from p1 value */
7429e9d4 5616 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5617 /* also FPA1 */
7429e9d4 5618 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5619
7429e9d4 5620 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5621 case 5:
5622 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5623 break;
5624 case 7:
5625 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5626 break;
5627 case 10:
5628 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5629 break;
5630 case 14:
5631 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5632 break;
79e53945
JB		 5633 }
5634
b4c09f3b 5635 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5637 else
5638 dpll |= PLL_REF_INPUT_DREFCLK;
5639
959e16d6 5640 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5641}
5642
5643static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5644 int x, int y,
5645 struct drm_framebuffer *fb)
5646{
5647 struct drm_device *dev = crtc->dev;
5648 struct drm_i915_private *dev_priv = dev->dev_private;
5649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5650 int pipe = intel_crtc->pipe;
5651 int plane = intel_crtc->plane;
5652 int num_connectors = 0;
5653 intel_clock_t clock, reduced_clock;
cbbab5bd 5654 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5655 bool ok, has_reduced_clock = false;
8b47047b 5656 bool is_lvds = false;
de13a2e3 5657 struct intel_encoder *encoder;
e2b78267 5658 struct intel_shared_dpll *pll;
de13a2e3 5659 int ret;
de13a2e3
PZ		 5660
5661 for_each_encoder_on_crtc(dev, crtc, encoder) {
5662 switch (encoder->type) {
5663 case INTEL_OUTPUT_LVDS:
5664 is_lvds = true;
5665 break;
de13a2e3
PZ		 5666 }
5667
5668 num_connectors++;
a07d6787 5669 }
79e53945 5670
5dc5298b
PZ		 5671 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5672 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5673
ff9a6750 5674 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5675 &has_reduced_clock, &reduced_clock);
ee9300bb 5676 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5677 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5678 return -EINVAL;
79e53945 5679 }
f47709a9
DV		 5680 /* Compat-code for transition, will disappear. */
5681 if (!intel_crtc->config.clock_set) {
5682 intel_crtc->config.dpll.n = clock.n;
5683 intel_crtc->config.dpll.m1 = clock.m1;
5684 intel_crtc->config.dpll.m2 = clock.m2;
5685 intel_crtc->config.dpll.p1 = clock.p1;
5686 intel_crtc->config.dpll.p2 = clock.p2;
5687 }
79e53945 5688
de13a2e3
PZ		 5689 /* Ensure that the cursor is valid for the new mode before changing... */
5690 intel_crtc_update_cursor(crtc, true);
5691
5dc5298b 5692 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5693 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5694 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5695 if (has_reduced_clock)
7429e9d4 5696 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5697
7429e9d4 5698 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5699 &fp, &reduced_clock,
5700 has_reduced_clock ? &fp2 : NULL);
5701
959e16d6 5702 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5703 intel_crtc->config.dpll_hw_state.fp0 = fp;
5704 if (has_reduced_clock)
5705 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5706 else
5707 intel_crtc->config.dpll_hw_state.fp1 = fp;
5708
b89a1d39 5709 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5710 if (pll == NULL) {
84f44ce7
VS		 5711 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5712 pipe_name(pipe));
4b645f14
JB		 5713 return -EINVAL;
5714 }
ee7b9f93 5715 } else
e72f9fbf 5716 intel_put_shared_dpll(intel_crtc);
79e53945 5717
03afc4a2
DV		 5718 if (intel_crtc->config.has_dp_encoder)
5719 intel_dp_set_m_n(intel_crtc);
79e53945 5720
bcd644e0
DV		 5721 if (is_lvds && has_reduced_clock && i915_powersave)
5722 intel_crtc->lowfreq_avail = true;
5723 else
5724 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5725
5726 if (intel_crtc->config.has_pch_encoder) {
5727 pll = intel_crtc_to_shared_dpll(intel_crtc);
5728
652c393a
JB		 5729 }
5730
8a654f3b 5731 intel_set_pipe_timings(intel_crtc);
5eddb70b 5732
ca3a0ff8 5733 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5734 intel_cpu_transcoder_set_m_n(intel_crtc,
5735 &intel_crtc->config.fdi_m_n);
5736 }
2c07245f 5737
ebfd86fd
DV		 5738 if (IS_IVYBRIDGE(dev))
5739 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5740
6ff93609 5741 ironlake_set_pipeconf(crtc);
79e53945 5742
a1f9e77e
PZ		 5743 /* Set up the display plane register */
5744 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5745 POSTING_READ(DSPCNTR(plane));
79e53945 5746
94352cf9 5747 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5748
5749 intel_update_watermarks(dev);
5750
1857e1da 5751 return ret;
79e53945
JB		 5752}
5753
72419203
DV		 5754static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5755 struct intel_crtc_config *pipe_config)
5756{
5757 struct drm_device *dev = crtc->base.dev;
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 enum transcoder transcoder = pipe_config->cpu_transcoder;
5760
5761 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5762 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5763 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5764 & ~TU_SIZE_MASK;
5765 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5766 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5767 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5768}
5769
2fa2fe9a
DV		 5770static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5771 struct intel_crtc_config *pipe_config)
5772{
5773 struct drm_device *dev = crtc->base.dev;
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 uint32_t tmp;
5776
5777 tmp = I915_READ(PF_CTL(crtc->pipe));
5778
5779 if (tmp & PF_ENABLE) {
5780 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5781 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5782
5783 /* We currently do not free assignements of panel fitters on
5784 * ivb/hsw (since we don't use the higher upscaling modes which
5785 * differentiates them) so just WARN about this case for now. */
5786 if (IS_GEN7(dev)) {
5787 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5788 PF_PIPE_SEL_IVB(crtc->pipe));
5789 }
2fa2fe9a 5790 }
79e53945
JB		 5791}
5792
0e8ffe1b
DV		 5793static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5794 struct intel_crtc_config *pipe_config)
5795{
5796 struct drm_device *dev = crtc->base.dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 uint32_t tmp;
5799
eccb140b 5800 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5801 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5802
0e8ffe1b
DV		 5803 tmp = I915_READ(PIPECONF(crtc->pipe));
5804 if (!(tmp & PIPECONF_ENABLE))
5805 return false;
5806
ab9412ba 5807 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5808 struct intel_shared_dpll *pll;
5809
88adfff1
DV		 5810 pipe_config->has_pch_encoder = true;
5811
627eb5a3
DV		 5812 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5813 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5814 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5815
5816 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5817
5818 /* XXX: Can't properly read out the pch dpll pixel multiplier
5819 * since we don't have state tracking for pch clocks yet. */
5820 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5821
5822 if (HAS_PCH_IBX(dev_priv->dev)) {
5823 pipe_config->shared_dpll = crtc->pipe;
5824 } else {
5825 tmp = I915_READ(PCH_DPLL_SEL);
5826 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5827 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5828 else
5829 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5830 }
66e985c0
DV		 5831
5832 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5833
5834 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5835 &pipe_config->dpll_hw_state));
6c49f241
DV		 5836 } else {
5837 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5838 }
5839
1bd1bd80
DV		 5840 intel_get_pipe_timings(crtc, pipe_config);
5841
2fa2fe9a
DV		 5842 ironlake_get_pfit_config(crtc, pipe_config);
5843
0e8ffe1b
DV		 5844 return true;
5845}
5846
d6dd9eb1
DV		 5847static void haswell_modeset_global_resources(struct drm_device *dev)
5848{
d6dd9eb1
DV		 5849 bool enable = false;
5850 struct intel_crtc *crtc;
d6dd9eb1
DV		 5851
5852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5853 if (!crtc->base.enabled)
5854 continue;
d6dd9eb1 5855
e7a639c4
DV		 5856 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5857 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5858 enable = true;
5859 }
5860
d6dd9eb1
DV		 5861 intel_set_power_well(dev, enable);
5862}
5863
09b4ddf9 5864static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5865 int x, int y,
5866 struct drm_framebuffer *fb)
5867{
5868 struct drm_device *dev = crtc->dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5871 int plane = intel_crtc->plane;
09b4ddf9 5872 int ret;
09b4ddf9 5873
ff9a6750 5874 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5875 return -EINVAL;
5876
09b4ddf9
PZ		 5877 /* Ensure that the cursor is valid for the new mode before changing... */
5878 intel_crtc_update_cursor(crtc, true);
5879
03afc4a2
DV		 5880 if (intel_crtc->config.has_dp_encoder)
5881 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5882
5883 intel_crtc->lowfreq_avail = false;
09b4ddf9 5884
8a654f3b 5885 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5886
ca3a0ff8 5887 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5888 intel_cpu_transcoder_set_m_n(intel_crtc,
5889 &intel_crtc->config.fdi_m_n);
5890 }
09b4ddf9 5891
6ff93609 5892 haswell_set_pipeconf(crtc);
09b4ddf9 5893
50f3b016 5894 intel_set_pipe_csc(crtc);
86d3efce 5895
09b4ddf9 5896 /* Set up the display plane register */
86d3efce 5897 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5898 POSTING_READ(DSPCNTR(plane));
5899
5900 ret = intel_pipe_set_base(crtc, x, y, fb);
5901
5902 intel_update_watermarks(dev);
5903
1f803ee5 5904 return ret;
79e53945
JB		 5905}
5906
0e8ffe1b
DV		 5907static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5908 struct intel_crtc_config *pipe_config)
5909{
5910 struct drm_device *dev = crtc->base.dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5912 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5913 uint32_t tmp;
5914
eccb140b 5915 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5916 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5917
eccb140b
DV		 5918 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5919 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5920 enum pipe trans_edp_pipe;
5921 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5922 default:
5923 WARN(1, "unknown pipe linked to edp transcoder\n");
5924 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5925 case TRANS_DDI_EDP_INPUT_A_ON:
5926 trans_edp_pipe = PIPE_A;
5927 break;
5928 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5929 trans_edp_pipe = PIPE_B;
5930 break;
5931 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5932 trans_edp_pipe = PIPE_C;
5933 break;
5934 }
5935
5936 if (trans_edp_pipe == crtc->pipe)
5937 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5938 }
5939
b97186f0 5940 if (!intel_display_power_enabled(dev,
eccb140b 5941 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5942 return false;
5943
eccb140b 5944 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5945 if (!(tmp & PIPECONF_ENABLE))
5946 return false;
5947
88adfff1 5948 /*
f196e6be 5949 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5950 * DDI E. So just check whether this pipe is wired to DDI E and whether
5951 * the PCH transcoder is on.
5952 */
eccb140b 5953 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5954 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5955 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5956 pipe_config->has_pch_encoder = true;
5957
627eb5a3
DV		 5958 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5959 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5960 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5961
5962 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5963 }
5964
1bd1bd80
DV		 5965 intel_get_pipe_timings(crtc, pipe_config);
5966
2fa2fe9a
DV		 5967 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5968 if (intel_display_power_enabled(dev, pfit_domain))
5969 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5970
42db64ef
PZ		 5971 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5972 (I915_READ(IPS_CTL) & IPS_ENABLE);
5973
6c49f241
DV		 5974 pipe_config->pixel_multiplier = 1;
5975
0e8ffe1b
DV		 5976 return true;
5977}
5978
f564048e 5979static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5980 int x, int y,
94352cf9 5981 struct drm_framebuffer *fb)
f564048e
EA		 5982{
5983 struct drm_device *dev = crtc->dev;
5984 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5985 struct drm_encoder_helper_funcs *encoder_funcs;
5986 struct intel_encoder *encoder;
0b701d27 5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5988 struct drm_display_mode *adjusted_mode =
5989 &intel_crtc->config.adjusted_mode;
5990 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5991 int pipe = intel_crtc->pipe;
f564048e
EA		 5992 int ret;
5993
0b701d27 5994 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5995
b8cecdf5
DV		 5996 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5997
79e53945 5998 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5999
9256aa19
DV		 6000 if (ret != 0)
6001 return ret;
6002
6003 for_each_encoder_on_crtc(dev, crtc, encoder) {
6004 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6005 encoder->base.base.id,
6006 drm_get_encoder_name(&encoder->base),
6007 mode->base.id, mode->name);
6cc5f341
DV		 6008 if (encoder->mode_set) {
6009 encoder->mode_set(encoder);
6010 } else {
6011 encoder_funcs = encoder->base.helper_private;
6012 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6013 }
9256aa19
DV		 6014 }
6015
6016 return 0;
79e53945
JB		 6017}
6018
3a9627f4
WF		 6019static bool intel_eld_uptodate(struct drm_connector *connector,
6020 int reg_eldv, uint32_t bits_eldv,
6021 int reg_elda, uint32_t bits_elda,
6022 int reg_edid)
6023{
6024 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6025 uint8_t *eld = connector->eld;
6026 uint32_t i;
6027
6028 i = I915_READ(reg_eldv);
6029 i &= bits_eldv;
6030
6031 if (!eld[0])
6032 return !i;
6033
6034 if (!i)
6035 return false;
6036
6037 i = I915_READ(reg_elda);
6038 i &= ~bits_elda;
6039 I915_WRITE(reg_elda, i);
6040
6041 for (i = 0; i < eld[2]; i++)
6042 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6043 return false;
6044
6045 return true;
6046}
6047
e0dac65e
WF		 6048static void g4x_write_eld(struct drm_connector *connector,
6049 struct drm_crtc *crtc)
6050{
6051 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6052 uint8_t *eld = connector->eld;
6053 uint32_t eldv;
6054 uint32_t len;
6055 uint32_t i;
6056
6057 i = I915_READ(G4X_AUD_VID_DID);
6058
6059 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6060 eldv = G4X_ELDV_DEVCL_DEVBLC;
6061 else
6062 eldv = G4X_ELDV_DEVCTG;
6063
3a9627f4
WF		 6064 if (intel_eld_uptodate(connector,
6065 G4X_AUD_CNTL_ST, eldv,
6066 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6067 G4X_HDMIW_HDMIEDID))
6068 return;
6069
e0dac65e
WF		 6070 i = I915_READ(G4X_AUD_CNTL_ST);
6071 i &= ~(eldv | G4X_ELD_ADDR);
6072 len = (i >> 9) & 0x1f; /* ELD buffer size */
6073 I915_WRITE(G4X_AUD_CNTL_ST, i);
6074
6075 if (!eld[0])
6076 return;
6077
6078 len = min_t(uint8_t, eld[2], len);
6079 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6080 for (i = 0; i < len; i++)
6081 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6082
6083 i = I915_READ(G4X_AUD_CNTL_ST);
6084 i |= eldv;
6085 I915_WRITE(G4X_AUD_CNTL_ST, i);
6086}
6087
83358c85
WX		 6088static void haswell_write_eld(struct drm_connector *connector,
6089 struct drm_crtc *crtc)
6090{
6091 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6092 uint8_t *eld = connector->eld;
6093 struct drm_device *dev = crtc->dev;
7b9f35a6 6094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6095 uint32_t eldv;
6096 uint32_t i;
6097 int len;
6098 int pipe = to_intel_crtc(crtc)->pipe;
6099 int tmp;
6100
6101 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6102 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6103 int aud_config = HSW_AUD_CFG(pipe);
6104 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6105
6106
6107 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6108
6109 /* Audio output enable */
6110 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6111 tmp = I915_READ(aud_cntrl_st2);
6112 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6113 I915_WRITE(aud_cntrl_st2, tmp);
6114
6115 /* Wait for 1 vertical blank */
6116 intel_wait_for_vblank(dev, pipe);
6117
6118 /* Set ELD valid state */
6119 tmp = I915_READ(aud_cntrl_st2);
6120 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6121 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6122 I915_WRITE(aud_cntrl_st2, tmp);
6123 tmp = I915_READ(aud_cntrl_st2);
6124 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6125
6126 /* Enable HDMI mode */
6127 tmp = I915_READ(aud_config);
6128 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6129 /* clear N_programing_enable and N_value_index */
6130 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6131 I915_WRITE(aud_config, tmp);
6132
6133 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6134
6135 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6136 intel_crtc->eld_vld = true;
83358c85
WX		 6137
6138 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6139 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6140 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6141 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6142 } else
6143 I915_WRITE(aud_config, 0);
6144
6145 if (intel_eld_uptodate(connector,
6146 aud_cntrl_st2, eldv,
6147 aud_cntl_st, IBX_ELD_ADDRESS,
6148 hdmiw_hdmiedid))
6149 return;
6150
6151 i = I915_READ(aud_cntrl_st2);
6152 i &= ~eldv;
6153 I915_WRITE(aud_cntrl_st2, i);
6154
6155 if (!eld[0])
6156 return;
6157
6158 i = I915_READ(aud_cntl_st);
6159 i &= ~IBX_ELD_ADDRESS;
6160 I915_WRITE(aud_cntl_st, i);
6161 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6162 DRM_DEBUG_DRIVER("port num:%d\n", i);
6163
6164 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6165 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6166 for (i = 0; i < len; i++)
6167 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6168
6169 i = I915_READ(aud_cntrl_st2);
6170 i |= eldv;
6171 I915_WRITE(aud_cntrl_st2, i);
6172
6173}
6174
e0dac65e
WF		 6175static void ironlake_write_eld(struct drm_connector *connector,
6176 struct drm_crtc *crtc)
6177{
6178 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6179 uint8_t *eld = connector->eld;
6180 uint32_t eldv;
6181 uint32_t i;
6182 int len;
6183 int hdmiw_hdmiedid;
b6daa025 6184 int aud_config;
e0dac65e
WF		 6185 int aud_cntl_st;
6186 int aud_cntrl_st2;
9b138a83 6187 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6188
b3f33cbf 6189 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6190 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6191 aud_config = IBX_AUD_CFG(pipe);
6192 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6193 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6194 } else {
9b138a83
WX		 6195 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6196 aud_config = CPT_AUD_CFG(pipe);
6197 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6198 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6199 }
6200
9b138a83 6201 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6202
6203 i = I915_READ(aud_cntl_st);
9b138a83 6204 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6205 if (!i) {
6206 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6207 /* operate blindly on all ports */
1202b4c6
WF		 6208 eldv = IBX_ELD_VALIDB;
6209 eldv |= IBX_ELD_VALIDB << 4;
6210 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6211 } else {
2582a850 6212 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6213 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6214 }
6215
3a9627f4
WF		 6216 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6217 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6218 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6219 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6220 } else
6221 I915_WRITE(aud_config, 0);
e0dac65e 6222
3a9627f4
WF		 6223 if (intel_eld_uptodate(connector,
6224 aud_cntrl_st2, eldv,
6225 aud_cntl_st, IBX_ELD_ADDRESS,
6226 hdmiw_hdmiedid))
6227 return;
6228
e0dac65e
WF		 6229 i = I915_READ(aud_cntrl_st2);
6230 i &= ~eldv;
6231 I915_WRITE(aud_cntrl_st2, i);
6232
6233 if (!eld[0])
6234 return;
6235
e0dac65e 6236 i = I915_READ(aud_cntl_st);
1202b4c6 6237 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6238 I915_WRITE(aud_cntl_st, i);
6239
6240 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6241 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6242 for (i = 0; i < len; i++)
6243 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6244
6245 i = I915_READ(aud_cntrl_st2);
6246 i |= eldv;
6247 I915_WRITE(aud_cntrl_st2, i);
6248}
6249
6250void intel_write_eld(struct drm_encoder *encoder,
6251 struct drm_display_mode *mode)
6252{
6253 struct drm_crtc *crtc = encoder->crtc;
6254 struct drm_connector *connector;
6255 struct drm_device *dev = encoder->dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257
6258 connector = drm_select_eld(encoder, mode);
6259 if (!connector)
6260 return;
6261
6262 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6263 connector->base.id,
6264 drm_get_connector_name(connector),
6265 connector->encoder->base.id,
6266 drm_get_encoder_name(connector->encoder));
6267
6268 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6269
6270 if (dev_priv->display.write_eld)
6271 dev_priv->display.write_eld(connector, crtc);
6272}
6273
79e53945
JB		 6274/** Loads the palette/gamma unit for the CRTC with the prepared values */
6275void intel_crtc_load_lut(struct drm_crtc *crtc)
6276{
6277 struct drm_device *dev = crtc->dev;
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6280 enum pipe pipe = intel_crtc->pipe;
6281 int palreg = PALETTE(pipe);
79e53945 6282 int i;
42db64ef 6283 bool reenable_ips = false;
79e53945
JB		 6284
6285 /* The clocks have to be on to load the palette. */
aed3f09d 6286 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6287 return;
6288
14420bd0
VS		 6289 if (!HAS_PCH_SPLIT(dev_priv->dev))
6290 assert_pll_enabled(dev_priv, pipe);
6291
f2b115e6 6292 /* use legacy palette for Ironlake */
bad720ff 6293 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6294 palreg = LGC_PALETTE(pipe);
6295
6296 /* Workaround : Do not read or write the pipe palette/gamma data while
6297 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6298 */
6299 if (intel_crtc->config.ips_enabled &&
6300 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6301 GAMMA_MODE_MODE_SPLIT)) {
6302 hsw_disable_ips(intel_crtc);
6303 reenable_ips = true;
6304 }
2c07245f 6305
79e53945
JB		 6306 for (i = 0; i < 256; i++) {
6307 I915_WRITE(palreg + 4 * i,
6308 (intel_crtc->lut_r[i] << 16) |
6309 (intel_crtc->lut_g[i] << 8) |
6310 intel_crtc->lut_b[i]);
6311 }
42db64ef
PZ		 6312
6313 if (reenable_ips)
6314 hsw_enable_ips(intel_crtc);
79e53945
JB		 6315}
6316
560b85bb
CW		 6317static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6318{
6319 struct drm_device *dev = crtc->dev;
6320 struct drm_i915_private *dev_priv = dev->dev_private;
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322 bool visible = base != 0;
6323 u32 cntl;
6324
6325 if (intel_crtc->cursor_visible == visible)
6326 return;
6327
9db4a9c7 6328 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6329 if (visible) {
6330 /* On these chipsets we can only modify the base whilst
6331 * the cursor is disabled.
6332 */
9db4a9c7 6333 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6334
6335 cntl &= ~(CURSOR_FORMAT_MASK);
6336 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6337 cntl |= CURSOR_ENABLE |
6338 CURSOR_GAMMA_ENABLE |
6339 CURSOR_FORMAT_ARGB;
6340 } else
6341 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6342 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6343
6344 intel_crtc->cursor_visible = visible;
6345}
6346
6347static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6348{
6349 struct drm_device *dev = crtc->dev;
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352 int pipe = intel_crtc->pipe;
6353 bool visible = base != 0;
6354
6355 if (intel_crtc->cursor_visible != visible) {
548f245b 6356 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6357 if (base) {
6358 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6359 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6360 cntl |= pipe << 28; /* Connect to correct pipe */
6361 } else {
6362 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6363 cntl |= CURSOR_MODE_DISABLE;
6364 }
9db4a9c7 6365 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6366
6367 intel_crtc->cursor_visible = visible;
6368 }
6369 /* and commit changes on next vblank */
9db4a9c7 6370 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6371}
6372
65a21cd6
JB		 6373static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6374{
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378 int pipe = intel_crtc->pipe;
6379 bool visible = base != 0;
6380
6381 if (intel_crtc->cursor_visible != visible) {
6382 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6383 if (base) {
6384 cntl &= ~CURSOR_MODE;
6385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6386 } else {
6387 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6388 cntl |= CURSOR_MODE_DISABLE;
6389 }
86d3efce
VS		 6390 if (IS_HASWELL(dev))
6391 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6392 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6393
6394 intel_crtc->cursor_visible = visible;
6395 }
6396 /* and commit changes on next vblank */
6397 I915_WRITE(CURBASE_IVB(pipe), base);
6398}
6399
cda4b7d3 6400/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6401static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6402 bool on)
cda4b7d3
CW		 6403{
6404 struct drm_device *dev = crtc->dev;
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6407 int pipe = intel_crtc->pipe;
6408 int x = intel_crtc->cursor_x;
6409 int y = intel_crtc->cursor_y;
560b85bb 6410 u32 base, pos;
cda4b7d3
CW		 6411 bool visible;
6412
6413 pos = 0;
6414
6b383a7f 6415 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6416 base = intel_crtc->cursor_addr;
6417 if (x > (int) crtc->fb->width)
6418 base = 0;
6419
6420 if (y > (int) crtc->fb->height)
6421 base = 0;
6422 } else
6423 base = 0;
6424
6425 if (x < 0) {
6426 if (x + intel_crtc->cursor_width < 0)
6427 base = 0;
6428
6429 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6430 x = -x;
6431 }
6432 pos |= x << CURSOR_X_SHIFT;
6433
6434 if (y < 0) {
6435 if (y + intel_crtc->cursor_height < 0)
6436 base = 0;
6437
6438 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6439 y = -y;
6440 }
6441 pos |= y << CURSOR_Y_SHIFT;
6442
6443 visible = base != 0;
560b85bb 6444 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6445 return;
6446
0cd83aa9 6447 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6448 I915_WRITE(CURPOS_IVB(pipe), pos);
6449 ivb_update_cursor(crtc, base);
6450 } else {
6451 I915_WRITE(CURPOS(pipe), pos);
6452 if (IS_845G(dev) || IS_I865G(dev))
6453 i845_update_cursor(crtc, base);
6454 else
6455 i9xx_update_cursor(crtc, base);
6456 }
cda4b7d3
CW		 6457}
6458
79e53945 6459static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6460 struct drm_file *file,
79e53945
JB		 6461 uint32_t handle,
6462 uint32_t width, uint32_t height)
6463{
6464 struct drm_device *dev = crtc->dev;
6465 struct drm_i915_private *dev_priv = dev->dev_private;
6466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6467 struct drm_i915_gem_object *obj;
cda4b7d3 6468 uint32_t addr;
3f8bc370 6469 int ret;
79e53945 6470
79e53945
JB		 6471 /* if we want to turn off the cursor ignore width and height */
6472 if (!handle) {
28c97730 6473 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6474 addr = 0;
05394f39 6475 obj = NULL;
5004417d 6476 mutex_lock(&dev->struct_mutex);
3f8bc370 6477 goto finish;
79e53945
JB		 6478 }
6479
6480 /* Currently we only support 64x64 cursors */
6481 if (width != 64 || height != 64) {
6482 DRM_ERROR("we currently only support 64x64 cursors\n");
6483 return -EINVAL;
6484 }
6485
05394f39 6486 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6487 if (&obj->base == NULL)
79e53945
JB		 6488 return -ENOENT;
6489
05394f39 6490 if (obj->base.size < width * height * 4) {
79e53945 6491 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6492 ret = -ENOMEM;
6493 goto fail;
79e53945
JB		 6494 }
6495
71acb5eb 6496 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6497 mutex_lock(&dev->struct_mutex);
b295d1b6 6498 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6499 unsigned alignment;
6500
d9e86c0e
CW		 6501 if (obj->tiling_mode) {
6502 DRM_ERROR("cursor cannot be tiled\n");
6503 ret = -EINVAL;
6504 goto fail_locked;
6505 }
6506
693db184
CW		 6507 /* Note that the w/a also requires 2 PTE of padding following
6508 * the bo. We currently fill all unused PTE with the shadow
6509 * page and so we should always have valid PTE following the
6510 * cursor preventing the VT-d warning.
6511 */
6512 alignment = 0;
6513 if (need_vtd_wa(dev))
6514 alignment = 64*1024;
6515
6516 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6517 if (ret) {
6518 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6519 goto fail_locked;
e7b526bb
CW		 6520 }
6521
d9e86c0e
CW		 6522 ret = i915_gem_object_put_fence(obj);
6523 if (ret) {
2da3b9b9 6524 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6525 goto fail_unpin;
6526 }
6527
05394f39 6528 addr = obj->gtt_offset;
71acb5eb 6529 } else {
6eeefaf3 6530 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6531 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6532 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6533 align);
71acb5eb
DA		 6534 if (ret) {
6535 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6536 goto fail_locked;
71acb5eb 6537 }
05394f39 6538 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6539 }
6540
a6c45cf0 6541 if (IS_GEN2(dev))
14b60391
JB		 6542 I915_WRITE(CURSIZE, (height << 12) | width);
6543
3f8bc370 6544 finish:
3f8bc370 6545 if (intel_crtc->cursor_bo) {
b295d1b6 6546 if (dev_priv->info->cursor_needs_physical) {
05394f39 6547 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6548 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6549 } else
6550 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6551 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6552 }
80824003 6553
7f9872e0 6554 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6555
6556 intel_crtc->cursor_addr = addr;
05394f39 6557 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6558 intel_crtc->cursor_width = width;
6559 intel_crtc->cursor_height = height;
6560
40ccc72b 6561 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6562
79e53945 6563 return 0;
e7b526bb 6564fail_unpin:
05394f39 6565 i915_gem_object_unpin(obj);
7f9872e0 6566fail_locked:
34b8686e 6567 mutex_unlock(&dev->struct_mutex);
bc9025bd 6568fail:
05394f39 6569 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6570 return ret;
79e53945
JB		 6571}
6572
6573static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6574{
79e53945 6575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6576
cda4b7d3
CW		 6577 intel_crtc->cursor_x = x;
6578 intel_crtc->cursor_y = y;
652c393a 6579
40ccc72b 6580 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6581
6582 return 0;
6583}
6584
6585/** Sets the color ramps on behalf of RandR */
6586void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6587 u16 blue, int regno)
6588{
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590
6591 intel_crtc->lut_r[regno] = red >> 8;
6592 intel_crtc->lut_g[regno] = green >> 8;
6593 intel_crtc->lut_b[regno] = blue >> 8;
6594}
6595
b8c00ac5
DA		 6596void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6597 u16 *blue, int regno)
6598{
6599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600
6601 *red = intel_crtc->lut_r[regno] << 8;
6602 *green = intel_crtc->lut_g[regno] << 8;
6603 *blue = intel_crtc->lut_b[regno] << 8;
6604}
6605
79e53945 6606static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6607 u16 *blue, uint32_t start, uint32_t size)
79e53945 6608{
7203425a 6609 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6611
7203425a 6612 for (i = start; i < end; i++) {
79e53945
JB		 6613 intel_crtc->lut_r[i] = red[i] >> 8;
6614 intel_crtc->lut_g[i] = green[i] >> 8;
6615 intel_crtc->lut_b[i] = blue[i] >> 8;
6616 }
6617
6618 intel_crtc_load_lut(crtc);
6619}
6620
79e53945
JB		 6621/* VESA 640x480x72Hz mode to set on the pipe */
6622static struct drm_display_mode load_detect_mode = {
6623 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6624 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6625};
6626
d2dff872
CW		 6627static struct drm_framebuffer *
6628intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6629 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6630 struct drm_i915_gem_object *obj)
6631{
6632 struct intel_framebuffer *intel_fb;
6633 int ret;
6634
6635 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6636 if (!intel_fb) {
6637 drm_gem_object_unreference_unlocked(&obj->base);
6638 return ERR_PTR(-ENOMEM);
6639 }
6640
6641 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6642 if (ret) {
6643 drm_gem_object_unreference_unlocked(&obj->base);
6644 kfree(intel_fb);
6645 return ERR_PTR(ret);
6646 }
6647
6648 return &intel_fb->base;
6649}
6650
6651static u32
6652intel_framebuffer_pitch_for_width(int width, int bpp)
6653{
6654 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6655 return ALIGN(pitch, 64);
6656}
6657
6658static u32
6659intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6660{
6661 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6662 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6663}
6664
6665static struct drm_framebuffer *
6666intel_framebuffer_create_for_mode(struct drm_device *dev,
6667 struct drm_display_mode *mode,
6668 int depth, int bpp)
6669{
6670 struct drm_i915_gem_object *obj;
0fed39bd 6671 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6672
6673 obj = i915_gem_alloc_object(dev,
6674 intel_framebuffer_size_for_mode(mode, bpp));
6675 if (obj == NULL)
6676 return ERR_PTR(-ENOMEM);
6677
6678 mode_cmd.width = mode->hdisplay;
6679 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6680 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6681 bpp);
5ca0c34a 6682 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6683
6684 return intel_framebuffer_create(dev, &mode_cmd, obj);
6685}
6686
6687static struct drm_framebuffer *
6688mode_fits_in_fbdev(struct drm_device *dev,
6689 struct drm_display_mode *mode)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 struct drm_i915_gem_object *obj;
6693 struct drm_framebuffer *fb;
6694
6695 if (dev_priv->fbdev == NULL)
6696 return NULL;
6697
6698 obj = dev_priv->fbdev->ifb.obj;
6699 if (obj == NULL)
6700 return NULL;
6701
6702 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6703 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6704 fb->bits_per_pixel))
d2dff872
CW		 6705 return NULL;
6706
01f2c773 6707 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6708 return NULL;
6709
6710 return fb;
6711}
6712
d2434ab7 6713bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6714 struct drm_display_mode *mode,
8261b191 6715 struct intel_load_detect_pipe *old)
79e53945
JB		 6716{
6717 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6718 struct intel_encoder *intel_encoder =
6719 intel_attached_encoder(connector);
79e53945 6720 struct drm_crtc *possible_crtc;
4ef69c7a 6721 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6722 struct drm_crtc *crtc = NULL;
6723 struct drm_device *dev = encoder->dev;
94352cf9 6724 struct drm_framebuffer *fb;
79e53945
JB		 6725 int i = -1;
6726
d2dff872
CW		 6727 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6728 connector->base.id, drm_get_connector_name(connector),
6729 encoder->base.id, drm_get_encoder_name(encoder));
6730
79e53945
JB		 6731 /*
6732 * Algorithm gets a little messy:
7a5e4805 6733 *
79e53945
JB		 6734 * - if the connector already has an assigned crtc, use it (but make
6735 * sure it's on first)
7a5e4805 6736 *
79e53945
JB		 6737 * - try to find the first unused crtc that can drive this connector,
6738 * and use that if we find one
79e53945
JB		 6739 */
6740
6741 /* See if we already have a CRTC for this connector */
6742 if (encoder->crtc) {
6743 crtc = encoder->crtc;
8261b191 6744
7b24056b
DV		 6745 mutex_lock(&crtc->mutex);
6746
24218aac 6747 old->dpms_mode = connector->dpms;
8261b191
CW		 6748 old->load_detect_temp = false;
6749
6750 /* Make sure the crtc and connector are running */
24218aac
DV		 6751 if (connector->dpms != DRM_MODE_DPMS_ON)
6752 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6753
7173188d 6754 return true;
79e53945
JB		 6755 }
6756
6757 /* Find an unused one (if possible) */
6758 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6759 i++;
6760 if (!(encoder->possible_crtcs & (1 << i)))
6761 continue;
6762 if (!possible_crtc->enabled) {
6763 crtc = possible_crtc;
6764 break;
6765 }
79e53945
JB		 6766 }
6767
6768 /*
6769 * If we didn't find an unused CRTC, don't use any.
6770 */
6771 if (!crtc) {
7173188d
CW		 6772 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6773 return false;
79e53945
JB		 6774 }
6775
7b24056b 6776 mutex_lock(&crtc->mutex);
fc303101
DV		 6777 intel_encoder->new_crtc = to_intel_crtc(crtc);
6778 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6779
6780 intel_crtc = to_intel_crtc(crtc);
24218aac 6781 old->dpms_mode = connector->dpms;
8261b191 6782 old->load_detect_temp = true;
d2dff872 6783 old->release_fb = NULL;
79e53945 6784
6492711d
CW		 6785 if (!mode)
6786 mode = &load_detect_mode;
79e53945 6787
d2dff872
CW		 6788 /* We need a framebuffer large enough to accommodate all accesses
6789 * that the plane may generate whilst we perform load detection.
6790 * We can not rely on the fbcon either being present (we get called
6791 * during its initialisation to detect all boot displays, or it may
6792 * not even exist) or that it is large enough to satisfy the
6793 * requested mode.
6794 */
94352cf9
DV		 6795 fb = mode_fits_in_fbdev(dev, mode);
6796 if (fb == NULL) {
d2dff872 6797 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6798 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6799 old->release_fb = fb;
d2dff872
CW		 6800 } else
6801 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6802 if (IS_ERR(fb)) {
d2dff872 6803 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6804 mutex_unlock(&crtc->mutex);
0e8b3d3e 6805 return false;
79e53945 6806 }
79e53945 6807
c0c36b94 6808 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6809 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6810 if (old->release_fb)
6811 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6812 mutex_unlock(&crtc->mutex);
0e8b3d3e 6813 return false;
79e53945 6814 }
7173188d 6815
79e53945 6816 /* let the connector get through one full cycle before testing */
9d0498a2 6817 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6818 return true;
79e53945
JB		 6819}
6820
d2434ab7 6821void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6822 struct intel_load_detect_pipe *old)
79e53945 6823{
d2434ab7
DV		 6824 struct intel_encoder *intel_encoder =
6825 intel_attached_encoder(connector);
4ef69c7a 6826 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6827 struct drm_crtc *crtc = encoder->crtc;
79e53945 6828
d2dff872
CW		 6829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6830 connector->base.id, drm_get_connector_name(connector),
6831 encoder->base.id, drm_get_encoder_name(encoder));
6832
8261b191 6833 if (old->load_detect_temp) {
fc303101
DV		 6834 to_intel_connector(connector)->new_encoder = NULL;
6835 intel_encoder->new_crtc = NULL;
6836 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6837
36206361
DV		 6838 if (old->release_fb) {
6839 drm_framebuffer_unregister_private(old->release_fb);
6840 drm_framebuffer_unreference(old->release_fb);
6841 }
d2dff872 6842
67c96400 6843 mutex_unlock(&crtc->mutex);
0622a53c 6844 return;
79e53945
JB		 6845 }
6846
c751ce4f 6847 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6848 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6849 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6850
6851 mutex_unlock(&crtc->mutex);
79e53945
JB		 6852}
6853
6854/* Returns the clock of the currently programmed mode of the given pipe. */
6855static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 int pipe = intel_crtc->pipe;
548f245b 6860 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6861 u32 fp;
6862 intel_clock_t clock;
6863
6864 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6865 fp = I915_READ(FP0(pipe));
79e53945 6866 else
39adb7a5 6867 fp = I915_READ(FP1(pipe));
79e53945
JB		 6868
6869 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6870 if (IS_PINEVIEW(dev)) {
6871 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6872 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6873 } else {
6874 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6875 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6876 }
6877
a6c45cf0 6878 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6879 if (IS_PINEVIEW(dev))
6880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6881 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6882 else
6883 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6884 DPLL_FPA01_P1_POST_DIV_SHIFT);
6885
6886 switch (dpll & DPLL_MODE_MASK) {
6887 case DPLLB_MODE_DAC_SERIAL:
6888 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6889 5 : 10;
6890 break;
6891 case DPLLB_MODE_LVDS:
6892 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6893 7 : 14;
6894 break;
6895 default:
28c97730 6896 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6897 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6898 return 0;
6899 }
6900
ac58c3f0
DV		 6901 if (IS_PINEVIEW(dev))
6902 pineview_clock(96000, &clock);
6903 else
6904 i9xx_clock(96000, &clock);
79e53945
JB		 6905 } else {
6906 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6907
6908 if (is_lvds) {
6909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6910 DPLL_FPA01_P1_POST_DIV_SHIFT);
6911 clock.p2 = 14;
6912
6913 if ((dpll & PLL_REF_INPUT_MASK) ==
6914 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6915 /* XXX: might not be 66MHz */
ac58c3f0 6916 i9xx_clock(66000, &clock);
79e53945 6917 } else
ac58c3f0 6918 i9xx_clock(48000, &clock);
79e53945
JB		 6919 } else {
6920 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6921 clock.p1 = 2;
6922 else {
6923 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6924 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6925 }
6926 if (dpll & PLL_P2_DIVIDE_BY_4)
6927 clock.p2 = 4;
6928 else
6929 clock.p2 = 2;
6930
ac58c3f0 6931 i9xx_clock(48000, &clock);
79e53945
JB		 6932 }
6933 }
6934
6935 /* XXX: It would be nice to validate the clocks, but we can't reuse
6936 * i830PllIsValid() because it relies on the xf86_config connector
6937 * configuration being accurate, which it isn't necessarily.
6938 */
6939
6940 return clock.dot;
6941}
6942
6943/** Returns the currently programmed mode of the given pipe. */
6944struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6945 struct drm_crtc *crtc)
6946{
548f245b 6947 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6949 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6950 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6951 int htot = I915_READ(HTOTAL(cpu_transcoder));
6952 int hsync = I915_READ(HSYNC(cpu_transcoder));
6953 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6954 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6955
6956 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6957 if (!mode)
6958 return NULL;
6959
6960 mode->clock = intel_crtc_clock_get(dev, crtc);
6961 mode->hdisplay = (htot & 0xffff) + 1;
6962 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6963 mode->hsync_start = (hsync & 0xffff) + 1;
6964 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6965 mode->vdisplay = (vtot & 0xffff) + 1;
6966 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6967 mode->vsync_start = (vsync & 0xffff) + 1;
6968 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6969
6970 drm_mode_set_name(mode);
79e53945
JB		 6971
6972 return mode;
6973}
6974
3dec0095 6975static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6976{
6977 struct drm_device *dev = crtc->dev;
6978 drm_i915_private_t *dev_priv = dev->dev_private;
6979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6980 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6981 int dpll_reg = DPLL(pipe);
6982 int dpll;
652c393a 6983
bad720ff 6984 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6985 return;
6986
6987 if (!dev_priv->lvds_downclock_avail)
6988 return;
6989
dbdc6479 6990 dpll = I915_READ(dpll_reg);
652c393a 6991 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6992 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6993
8ac5a6d5 6994 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6995
6996 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6997 I915_WRITE(dpll_reg, dpll);
9d0498a2 6998 intel_wait_for_vblank(dev, pipe);
dbdc6479 6999
652c393a
JB		 7000 dpll = I915_READ(dpll_reg);
7001 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7002 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7003 }
652c393a
JB		 7004}
7005
7006static void intel_decrease_pllclock(struct drm_crtc *crtc)
7007{
7008 struct drm_device *dev = crtc->dev;
7009 drm_i915_private_t *dev_priv = dev->dev_private;
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7011
bad720ff 7012 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7013 return;
7014
7015 if (!dev_priv->lvds_downclock_avail)
7016 return;
7017
7018 /*
7019 * Since this is called by a timer, we should never get here in
7020 * the manual case.
7021 */
7022 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7023 int pipe = intel_crtc->pipe;
7024 int dpll_reg = DPLL(pipe);
7025 int dpll;
f6e5b160 7026
44d98a61 7027 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7028
8ac5a6d5 7029 assert_panel_unlocked(dev_priv, pipe);
652c393a 7030
dc257cf1 7031 dpll = I915_READ(dpll_reg);
652c393a
JB		 7032 dpll |= DISPLAY_RATE_SELECT_FPA1;
7033 I915_WRITE(dpll_reg, dpll);
9d0498a2 7034 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7035 dpll = I915_READ(dpll_reg);
7036 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7037 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7038 }
7039
7040}
7041
f047e395
CW		 7042void intel_mark_busy(struct drm_device *dev)
7043{
f047e395
CW		 7044 i915_update_gfx_val(dev->dev_private);
7045}
7046
7047void intel_mark_idle(struct drm_device *dev)
652c393a 7048{
652c393a 7049 struct drm_crtc *crtc;
652c393a
JB		 7050
7051 if (!i915_powersave)
7052 return;
7053
652c393a 7054 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7055 if (!crtc->fb)
7056 continue;
7057
725a5b54 7058 intel_decrease_pllclock(crtc);
652c393a 7059 }
652c393a
JB		 7060}
7061
c65355bb
CW		 7062void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7063 struct intel_ring_buffer *ring)
652c393a 7064{
f047e395
CW		 7065 struct drm_device *dev = obj->base.dev;
7066 struct drm_crtc *crtc;
652c393a 7067
f047e395 7068 if (!i915_powersave)
acb87dfb
CW		 7069 return;
7070
652c393a
JB		 7071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7072 if (!crtc->fb)
7073 continue;
7074
c65355bb
CW		 7075 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7076 continue;
7077
7078 intel_increase_pllclock(crtc);
7079 if (ring && intel_fbc_enabled(dev))
7080 ring->fbc_dirty = true;
652c393a
JB		 7081 }
7082}
7083
79e53945
JB		 7084static void intel_crtc_destroy(struct drm_crtc *crtc)
7085{
7086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7087 struct drm_device *dev = crtc->dev;
7088 struct intel_unpin_work *work;
7089 unsigned long flags;
7090
7091 spin_lock_irqsave(&dev->event_lock, flags);
7092 work = intel_crtc->unpin_work;
7093 intel_crtc->unpin_work = NULL;
7094 spin_unlock_irqrestore(&dev->event_lock, flags);
7095
7096 if (work) {
7097 cancel_work_sync(&work->work);
7098 kfree(work);
7099 }
79e53945 7100
40ccc72b
MK		 7101 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7102
79e53945 7103 drm_crtc_cleanup(crtc);
67e77c5a 7104
79e53945
JB		 7105 kfree(intel_crtc);
7106}
7107
6b95a207
KH		 7108static void intel_unpin_work_fn(struct work_struct *__work)
7109{
7110 struct intel_unpin_work *work =
7111 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7112 struct drm_device *dev = work->crtc->dev;
6b95a207 7113
b4a98e57 7114 mutex_lock(&dev->struct_mutex);
1690e1eb 7115 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7116 drm_gem_object_unreference(&work->pending_flip_obj->base);
7117 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7118
b4a98e57
CW		 7119 intel_update_fbc(dev);
7120 mutex_unlock(&dev->struct_mutex);
7121
7122 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7123 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7124
6b95a207
KH		 7125 kfree(work);
7126}
7127
1afe3e9d 7128static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7129 struct drm_crtc *crtc)
6b95a207
KH		 7130{
7131 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133 struct intel_unpin_work *work;
6b95a207
KH		 7134 unsigned long flags;
7135
7136 /* Ignore early vblank irqs */
7137 if (intel_crtc == NULL)
7138 return;
7139
7140 spin_lock_irqsave(&dev->event_lock, flags);
7141 work = intel_crtc->unpin_work;
e7d841ca
CW		 7142
7143 /* Ensure we don't miss a work->pending update ... */
7144 smp_rmb();
7145
7146 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7147 spin_unlock_irqrestore(&dev->event_lock, flags);
7148 return;
7149 }
7150
e7d841ca
CW		 7151 /* and that the unpin work is consistent wrt ->pending. */
7152 smp_rmb();
7153
6b95a207 7154 intel_crtc->unpin_work = NULL;
6b95a207 7155
45a066eb
RC		 7156 if (work->event)
7157 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7158
0af7e4df
MK		 7159 drm_vblank_put(dev, intel_crtc->pipe);
7160
6b95a207
KH		 7161 spin_unlock_irqrestore(&dev->event_lock, flags);
7162
2c10d571 7163 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7164
7165 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7166
7167 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7168}
7169
1afe3e9d
JB		 7170void intel_finish_page_flip(struct drm_device *dev, int pipe)
7171{
7172 drm_i915_private_t *dev_priv = dev->dev_private;
7173 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7174
49b14a5c 7175 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7176}
7177
7178void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7179{
7180 drm_i915_private_t *dev_priv = dev->dev_private;
7181 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7182
49b14a5c 7183 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7184}
7185
6b95a207
KH		 7186void intel_prepare_page_flip(struct drm_device *dev, int plane)
7187{
7188 drm_i915_private_t *dev_priv = dev->dev_private;
7189 struct intel_crtc *intel_crtc =
7190 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7191 unsigned long flags;
7192
e7d841ca
CW		 7193 /* NB: An MMIO update of the plane base pointer will also
7194 * generate a page-flip completion irq, i.e. every modeset
7195 * is also accompanied by a spurious intel_prepare_page_flip().
7196 */
6b95a207 7197 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7198 if (intel_crtc->unpin_work)
7199 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7200 spin_unlock_irqrestore(&dev->event_lock, flags);
7201}
7202
e7d841ca
CW		 7203inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7204{
7205 /* Ensure that the work item is consistent when activating it ... */
7206 smp_wmb();
7207 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7208 /* and that it is marked active as soon as the irq could fire. */
7209 smp_wmb();
7210}
7211
8c9f3aaf
JB		 7212static int intel_gen2_queue_flip(struct drm_device *dev,
7213 struct drm_crtc *crtc,
7214 struct drm_framebuffer *fb,
7215 struct drm_i915_gem_object *obj)
7216{
7217 struct drm_i915_private *dev_priv = dev->dev_private;
7218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7219 u32 flip_mask;
6d90c952 7220 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7221 int ret;
7222
6d90c952 7223 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7224 if (ret)
83d4092b 7225 goto err;
8c9f3aaf 7226
6d90c952 7227 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7228 if (ret)
83d4092b 7229 goto err_unpin;
8c9f3aaf
JB		 7230
7231 /* Can't queue multiple flips, so wait for the previous
7232 * one to finish before executing the next.
7233 */
7234 if (intel_crtc->plane)
7235 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7236 else
7237 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7238 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7239 intel_ring_emit(ring, MI_NOOP);
7240 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7241 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7242 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7243 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7244 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7245
7246 intel_mark_page_flip_active(intel_crtc);
6d90c952 7247 intel_ring_advance(ring);
83d4092b
CW		 7248 return 0;
7249
7250err_unpin:
7251 intel_unpin_fb_obj(obj);
7252err:
8c9f3aaf
JB		 7253 return ret;
7254}
7255
7256static int intel_gen3_queue_flip(struct drm_device *dev,
7257 struct drm_crtc *crtc,
7258 struct drm_framebuffer *fb,
7259 struct drm_i915_gem_object *obj)
7260{
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7263 u32 flip_mask;
6d90c952 7264 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7265 int ret;
7266
6d90c952 7267 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7268 if (ret)
83d4092b 7269 goto err;
8c9f3aaf 7270
6d90c952 7271 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7272 if (ret)
83d4092b 7273 goto err_unpin;
8c9f3aaf
JB		 7274
7275 if (intel_crtc->plane)
7276 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7277 else
7278 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7279 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7280 intel_ring_emit(ring, MI_NOOP);
7281 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7282 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7283 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7284 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7285 intel_ring_emit(ring, MI_NOOP);
7286
e7d841ca 7287 intel_mark_page_flip_active(intel_crtc);
6d90c952 7288 intel_ring_advance(ring);
83d4092b
CW		 7289 return 0;
7290
7291err_unpin:
7292 intel_unpin_fb_obj(obj);
7293err:
8c9f3aaf
JB		 7294 return ret;
7295}
7296
7297static int intel_gen4_queue_flip(struct drm_device *dev,
7298 struct drm_crtc *crtc,
7299 struct drm_framebuffer *fb,
7300 struct drm_i915_gem_object *obj)
7301{
7302 struct drm_i915_private *dev_priv = dev->dev_private;
7303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7304 uint32_t pf, pipesrc;
6d90c952 7305 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7306 int ret;
7307
6d90c952 7308 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7309 if (ret)
83d4092b 7310 goto err;
8c9f3aaf 7311
6d90c952 7312 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7313 if (ret)
83d4092b 7314 goto err_unpin;
8c9f3aaf
JB		 7315
7316 /* i965+ uses the linear or tiled offsets from the
7317 * Display Registers (which do not change across a page-flip)
7318 * so we need only reprogram the base address.
7319 */
6d90c952
DV		 7320 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7322 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7323 intel_ring_emit(ring,
7324 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7325 obj->tiling_mode);
8c9f3aaf
JB		 7326
7327 /* XXX Enabling the panel-fitter across page-flip is so far
7328 * untested on non-native modes, so ignore it for now.
7329 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7330 */
7331 pf = 0;
7332 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7333 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7334
7335 intel_mark_page_flip_active(intel_crtc);
6d90c952 7336 intel_ring_advance(ring);
83d4092b
CW		 7337 return 0;
7338
7339err_unpin:
7340 intel_unpin_fb_obj(obj);
7341err:
8c9f3aaf
JB		 7342 return ret;
7343}
7344
7345static int intel_gen6_queue_flip(struct drm_device *dev,
7346 struct drm_crtc *crtc,
7347 struct drm_framebuffer *fb,
7348 struct drm_i915_gem_object *obj)
7349{
7350 struct drm_i915_private *dev_priv = dev->dev_private;
7351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7352 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7353 uint32_t pf, pipesrc;
7354 int ret;
7355
6d90c952 7356 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7357 if (ret)
83d4092b 7358 goto err;
8c9f3aaf 7359
6d90c952 7360 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7361 if (ret)
83d4092b 7362 goto err_unpin;
8c9f3aaf 7363
6d90c952
DV		 7364 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7365 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7366 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7367 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7368
dc257cf1
DV		 7369 /* Contrary to the suggestions in the documentation,
7370 * "Enable Panel Fitter" does not seem to be required when page
7371 * flipping with a non-native mode, and worse causes a normal
7372 * modeset to fail.
7373 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7374 */
7375 pf = 0;
8c9f3aaf 7376 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7377 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7378
7379 intel_mark_page_flip_active(intel_crtc);
6d90c952 7380 intel_ring_advance(ring);
83d4092b
CW		 7381 return 0;
7382
7383err_unpin:
7384 intel_unpin_fb_obj(obj);
7385err:
8c9f3aaf
JB		 7386 return ret;
7387}
7388
7c9017e5
JB		 7389/*
7390 * On gen7 we currently use the blit ring because (in early silicon at least)
7391 * the render ring doesn't give us interrpts for page flip completion, which
7392 * means clients will hang after the first flip is queued. Fortunately the
7393 * blit ring generates interrupts properly, so use it instead.
7394 */
7395static int intel_gen7_queue_flip(struct drm_device *dev,
7396 struct drm_crtc *crtc,
7397 struct drm_framebuffer *fb,
7398 struct drm_i915_gem_object *obj)
7399{
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7403 uint32_t plane_bit = 0;
7c9017e5
JB		 7404 int ret;
7405
7406 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7407 if (ret)
83d4092b 7408 goto err;
7c9017e5 7409
cb05d8de
DV		 7410 switch(intel_crtc->plane) {
7411 case PLANE_A:
7412 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7413 break;
7414 case PLANE_B:
7415 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7416 break;
7417 case PLANE_C:
7418 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7419 break;
7420 default:
7421 WARN_ONCE(1, "unknown plane in flip command\n");
7422 ret = -ENODEV;
ab3951eb 7423 goto err_unpin;
cb05d8de
DV		 7424 }
7425
7c9017e5
JB		 7426 ret = intel_ring_begin(ring, 4);
7427 if (ret)
83d4092b 7428 goto err_unpin;
7c9017e5 7429
cb05d8de 7430 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7431 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7432 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7433 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7434
7435 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7436 intel_ring_advance(ring);
83d4092b
CW		 7437 return 0;
7438
7439err_unpin:
7440 intel_unpin_fb_obj(obj);
7441err:
7c9017e5
JB		 7442 return ret;
7443}
7444
8c9f3aaf
JB		 7445static int intel_default_queue_flip(struct drm_device *dev,
7446 struct drm_crtc *crtc,
7447 struct drm_framebuffer *fb,
7448 struct drm_i915_gem_object *obj)
7449{
7450 return -ENODEV;
7451}
7452
6b95a207
KH		 7453static int intel_crtc_page_flip(struct drm_crtc *crtc,
7454 struct drm_framebuffer *fb,
7455 struct drm_pending_vblank_event *event)
7456{
7457 struct drm_device *dev = crtc->dev;
7458 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7459 struct drm_framebuffer *old_fb = crtc->fb;
7460 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7462 struct intel_unpin_work *work;
8c9f3aaf 7463 unsigned long flags;
52e68630 7464 int ret;
6b95a207 7465
e6a595d2
VS		 7466 /* Can't change pixel format via MI display flips. */
7467 if (fb->pixel_format != crtc->fb->pixel_format)
7468 return -EINVAL;
7469
7470 /*
7471 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7472 * Note that pitch changes could also affect these register.
7473 */
7474 if (INTEL_INFO(dev)->gen > 3 &&
7475 (fb->offsets[0] != crtc->fb->offsets[0] ||
7476 fb->pitches[0] != crtc->fb->pitches[0]))
7477 return -EINVAL;
7478
6b95a207
KH		 7479 work = kzalloc(sizeof *work, GFP_KERNEL);
7480 if (work == NULL)
7481 return -ENOMEM;
7482
6b95a207 7483 work->event = event;
b4a98e57 7484 work->crtc = crtc;
4a35f83b 7485 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7486 INIT_WORK(&work->work, intel_unpin_work_fn);
7487
7317c75e
JB		 7488 ret = drm_vblank_get(dev, intel_crtc->pipe);
7489 if (ret)
7490 goto free_work;
7491
6b95a207
KH		 7492 /* We borrow the event spin lock for protecting unpin_work */
7493 spin_lock_irqsave(&dev->event_lock, flags);
7494 if (intel_crtc->unpin_work) {
7495 spin_unlock_irqrestore(&dev->event_lock, flags);
7496 kfree(work);
7317c75e 7497 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7498
7499 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7500 return -EBUSY;
7501 }
7502 intel_crtc->unpin_work = work;
7503 spin_unlock_irqrestore(&dev->event_lock, flags);
7504
b4a98e57
CW		 7505 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7506 flush_workqueue(dev_priv->wq);
7507
79158103
CW		 7508 ret = i915_mutex_lock_interruptible(dev);
7509 if (ret)
7510 goto cleanup;
6b95a207 7511
75dfca80 7512 /* Reference the objects for the scheduled work. */
05394f39
CW		 7513 drm_gem_object_reference(&work->old_fb_obj->base);
7514 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7515
7516 crtc->fb = fb;
96b099fd 7517
e1f99ce6 7518 work->pending_flip_obj = obj;
e1f99ce6 7519
4e5359cd
SF		 7520 work->enable_stall_check = true;
7521
b4a98e57 7522 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7523 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7524
8c9f3aaf
JB		 7525 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7526 if (ret)
7527 goto cleanup_pending;
6b95a207 7528
7782de3b 7529 intel_disable_fbc(dev);
c65355bb 7530 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7531 mutex_unlock(&dev->struct_mutex);
7532
e5510fac
JB		 7533 trace_i915_flip_request(intel_crtc->plane, obj);
7534
6b95a207 7535 return 0;
96b099fd 7536
8c9f3aaf 7537cleanup_pending:
b4a98e57 7538 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7539 crtc->fb = old_fb;
05394f39
CW		 7540 drm_gem_object_unreference(&work->old_fb_obj->base);
7541 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7542 mutex_unlock(&dev->struct_mutex);
7543
79158103 7544cleanup:
96b099fd
CW		 7545 spin_lock_irqsave(&dev->event_lock, flags);
7546 intel_crtc->unpin_work = NULL;
7547 spin_unlock_irqrestore(&dev->event_lock, flags);
7548
7317c75e
JB		 7549 drm_vblank_put(dev, intel_crtc->pipe);
7550free_work:
96b099fd
CW		 7551 kfree(work);
7552
7553 return ret;
6b95a207
KH		 7554}
7555
f6e5b160 7556static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7557 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7558 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7559};
7560
50f56119
DV		 7561static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7562 struct drm_crtc *crtc)
7563{
7564 struct drm_device *dev;
7565 struct drm_crtc *tmp;
7566 int crtc_mask = 1;
47f1c6c9 7567
50f56119 7568 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7569
50f56119 7570 dev = crtc->dev;
47f1c6c9 7571
50f56119
DV		 7572 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7573 if (tmp == crtc)
7574 break;
7575 crtc_mask <<= 1;
7576 }
47f1c6c9 7577
50f56119
DV		 7578 if (encoder->possible_crtcs & crtc_mask)
7579 return true;
7580 return false;
47f1c6c9 7581}
79e53945 7582
9a935856
DV		 7583/**
7584 * intel_modeset_update_staged_output_state
7585 *
7586 * Updates the staged output configuration state, e.g. after we've read out the
7587 * current hw state.
7588 */
7589static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7590{
9a935856
DV		 7591 struct intel_encoder *encoder;
7592 struct intel_connector *connector;
f6e5b160 7593
9a935856
DV		 7594 list_for_each_entry(connector, &dev->mode_config.connector_list,
7595 base.head) {
7596 connector->new_encoder =
7597 to_intel_encoder(connector->base.encoder);
7598 }
f6e5b160 7599
9a935856
DV		 7600 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7601 base.head) {
7602 encoder->new_crtc =
7603 to_intel_crtc(encoder->base.crtc);
7604 }
f6e5b160
CW		 7605}
7606
9a935856
DV		 7607/**
7608 * intel_modeset_commit_output_state
7609 *
7610 * This function copies the stage display pipe configuration to the real one.
7611 */
7612static void intel_modeset_commit_output_state(struct drm_device *dev)
7613{
7614 struct intel_encoder *encoder;
7615 struct intel_connector *connector;
f6e5b160 7616
9a935856
DV		 7617 list_for_each_entry(connector, &dev->mode_config.connector_list,
7618 base.head) {
7619 connector->base.encoder = &connector->new_encoder->base;
7620 }
f6e5b160 7621
9a935856
DV		 7622 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7623 base.head) {
7624 encoder->base.crtc = &encoder->new_crtc->base;
7625 }
7626}
7627
050f7aeb
DV		 7628static void
7629connected_sink_compute_bpp(struct intel_connector * connector,
7630 struct intel_crtc_config *pipe_config)
7631{
7632 int bpp = pipe_config->pipe_bpp;
7633
7634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7635 connector->base.base.id,
7636 drm_get_connector_name(&connector->base));
7637
7638 /* Don't use an invalid EDID bpc value */
7639 if (connector->base.display_info.bpc &&
7640 connector->base.display_info.bpc * 3 < bpp) {
7641 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7642 bpp, connector->base.display_info.bpc*3);
7643 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7644 }
7645
7646 /* Clamp bpp to 8 on screens without EDID 1.4 */
7647 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7648 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7649 bpp);
7650 pipe_config->pipe_bpp = 24;
7651 }
7652}
7653
4e53c2e0 7654static int
050f7aeb
DV		 7655compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7656 struct drm_framebuffer *fb,
7657 struct intel_crtc_config *pipe_config)
4e53c2e0 7658{
050f7aeb
DV		 7659 struct drm_device *dev = crtc->base.dev;
7660 struct intel_connector *connector;
4e53c2e0
DV		 7661 int bpp;
7662
d42264b1
DV		 7663 switch (fb->pixel_format) {
7664 case DRM_FORMAT_C8:
4e53c2e0
DV		 7665 bpp = 8*3; /* since we go through a colormap */
7666 break;
d42264b1
DV		 7667 case DRM_FORMAT_XRGB1555:
7668 case DRM_FORMAT_ARGB1555:
7669 /* checked in intel_framebuffer_init already */
7670 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7671 return -EINVAL;
7672 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7673 bpp = 6*3; /* min is 18bpp */
7674 break;
d42264b1
DV		 7675 case DRM_FORMAT_XBGR8888:
7676 case DRM_FORMAT_ABGR8888:
7677 /* checked in intel_framebuffer_init already */
7678 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7679 return -EINVAL;
7680 case DRM_FORMAT_XRGB8888:
7681 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7682 bpp = 8*3;
7683 break;
d42264b1
DV		 7684 case DRM_FORMAT_XRGB2101010:
7685 case DRM_FORMAT_ARGB2101010:
7686 case DRM_FORMAT_XBGR2101010:
7687 case DRM_FORMAT_ABGR2101010:
7688 /* checked in intel_framebuffer_init already */
7689 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7690 return -EINVAL;
4e53c2e0
DV		 7691 bpp = 10*3;
7692 break;
baba133a 7693 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7694 default:
7695 DRM_DEBUG_KMS("unsupported depth\n");
7696 return -EINVAL;
7697 }
7698
4e53c2e0
DV		 7699 pipe_config->pipe_bpp = bpp;
7700
7701 /* Clamp display bpp to EDID value */
7702 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7703 base.head) {
1b829e05
DV		 7704 if (!connector->new_encoder ||
7705 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7706 continue;
7707
050f7aeb 7708 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7709 }
7710
7711 return bpp;
7712}
7713
c0b03411
DV		 7714static void intel_dump_pipe_config(struct intel_crtc *crtc,
7715 struct intel_crtc_config *pipe_config,
7716 const char *context)
7717{
7718 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7719 context, pipe_name(crtc->pipe));
7720
7721 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7722 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7723 pipe_config->pipe_bpp, pipe_config->dither);
7724 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7725 pipe_config->has_pch_encoder,
7726 pipe_config->fdi_lanes,
7727 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7728 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7729 pipe_config->fdi_m_n.tu);
7730 DRM_DEBUG_KMS("requested mode:\n");
7731 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7732 DRM_DEBUG_KMS("adjusted mode:\n");
7733 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7734 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7735 pipe_config->gmch_pfit.control,
7736 pipe_config->gmch_pfit.pgm_ratios,
7737 pipe_config->gmch_pfit.lvds_border_bits);
7738 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7739 pipe_config->pch_pfit.pos,
7740 pipe_config->pch_pfit.size);
42db64ef 7741 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7742}
7743
accfc0c5
DV		 7744static bool check_encoder_cloning(struct drm_crtc *crtc)
7745{
7746 int num_encoders = 0;
7747 bool uncloneable_encoders = false;
7748 struct intel_encoder *encoder;
7749
7750 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7751 base.head) {
7752 if (&encoder->new_crtc->base != crtc)
7753 continue;
7754
7755 num_encoders++;
7756 if (!encoder->cloneable)
7757 uncloneable_encoders = true;
7758 }
7759
7760 return !(num_encoders > 1 && uncloneable_encoders);
7761}
7762
b8cecdf5
DV		 7763static struct intel_crtc_config *
7764intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7765 struct drm_framebuffer *fb,
b8cecdf5 7766 struct drm_display_mode *mode)
ee7b9f93 7767{
7758a113 7768 struct drm_device *dev = crtc->dev;
7758a113
DV		 7769 struct drm_encoder_helper_funcs *encoder_funcs;
7770 struct intel_encoder *encoder;
b8cecdf5 7771 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7772 int plane_bpp, ret = -EINVAL;
7773 bool retry = true;
ee7b9f93 7774
accfc0c5
DV		 7775 if (!check_encoder_cloning(crtc)) {
7776 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7777 return ERR_PTR(-EINVAL);
7778 }
7779
b8cecdf5
DV		 7780 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7781 if (!pipe_config)
7758a113
DV		 7782 return ERR_PTR(-ENOMEM);
7783
b8cecdf5
DV		 7784 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7785 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7786 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7787 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7788
050f7aeb
DV		 7789 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7790 * plane pixel format and any sink constraints into account. Returns the
7791 * source plane bpp so that dithering can be selected on mismatches
7792 * after encoders and crtc also have had their say. */
7793 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7794 fb, pipe_config);
4e53c2e0
DV		 7795 if (plane_bpp < 0)
7796 goto fail;
7797
e29c22c0 7798encoder_retry:
ef1b460d 7799 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7800 pipe_config->port_clock = 0;
ef1b460d 7801 pipe_config->pixel_multiplier = 1;
ff9a6750 7802
7758a113
DV		 7803 /* Pass our mode to the connectors and the CRTC to give them a chance to
7804 * adjust it according to limitations or connector properties, and also
7805 * a chance to reject the mode entirely.
47f1c6c9 7806 */
7758a113
DV		 7807 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7808 base.head) {
47f1c6c9 7809
7758a113
DV		 7810 if (&encoder->new_crtc->base != crtc)
7811 continue;
7ae89233
DV		 7812
7813 if (encoder->compute_config) {
7814 if (!(encoder->compute_config(encoder, pipe_config))) {
7815 DRM_DEBUG_KMS("Encoder config failure\n");
7816 goto fail;
7817 }
7818
7819 continue;
7820 }
7821
7758a113 7822 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7823 if (!(encoder_funcs->mode_fixup(&encoder->base,
7824 &pipe_config->requested_mode,
7825 &pipe_config->adjusted_mode))) {
7758a113
DV		 7826 DRM_DEBUG_KMS("Encoder fixup failed\n");
7827 goto fail;
7828 }
ee7b9f93 7829 }
47f1c6c9 7830
ff9a6750
DV		 7831 /* Set default port clock if not overwritten by the encoder. Needs to be
7832 * done afterwards in case the encoder adjusts the mode. */
7833 if (!pipe_config->port_clock)
7834 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7835
a43f6e0f 7836 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7837 if (ret < 0) {
7758a113
DV		 7838 DRM_DEBUG_KMS("CRTC fixup failed\n");
7839 goto fail;
ee7b9f93 7840 }
e29c22c0
DV		 7841
7842 if (ret == RETRY) {
7843 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7844 ret = -EINVAL;
7845 goto fail;
7846 }
7847
7848 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7849 retry = false;
7850 goto encoder_retry;
7851 }
7852
4e53c2e0
DV		 7853 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7854 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7855 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7856
b8cecdf5 7857 return pipe_config;
7758a113 7858fail:
b8cecdf5 7859 kfree(pipe_config);
e29c22c0 7860 return ERR_PTR(ret);
ee7b9f93 7861}
47f1c6c9 7862
e2e1ed41
DV		 7863/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7864 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7865static void
7866intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7867 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7868{
7869 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7870 struct drm_device *dev = crtc->dev;
7871 struct intel_encoder *encoder;
7872 struct intel_connector *connector;
7873 struct drm_crtc *tmp_crtc;
79e53945 7874
e2e1ed41 7875 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7876
e2e1ed41
DV		 7877 /* Check which crtcs have changed outputs connected to them, these need
7878 * to be part of the prepare_pipes mask. We don't (yet) support global
7879 * modeset across multiple crtcs, so modeset_pipes will only have one
7880 * bit set at most. */
7881 list_for_each_entry(connector, &dev->mode_config.connector_list,
7882 base.head) {
7883 if (connector->base.encoder == &connector->new_encoder->base)
7884 continue;
79e53945 7885
e2e1ed41
DV		 7886 if (connector->base.encoder) {
7887 tmp_crtc = connector->base.encoder->crtc;
7888
7889 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7890 }
7891
7892 if (connector->new_encoder)
7893 *prepare_pipes |=
7894 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7895 }
7896
e2e1ed41
DV		 7897 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7898 base.head) {
7899 if (encoder->base.crtc == &encoder->new_crtc->base)
7900 continue;
7901
7902 if (encoder->base.crtc) {
7903 tmp_crtc = encoder->base.crtc;
7904
7905 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7906 }
7907
7908 if (encoder->new_crtc)
7909 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7910 }
7911
e2e1ed41
DV		 7912 /* Check for any pipes that will be fully disabled ... */
7913 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7914 base.head) {
7915 bool used = false;
22fd0fab 7916
e2e1ed41
DV		 7917 /* Don't try to disable disabled crtcs. */
7918 if (!intel_crtc->base.enabled)
7919 continue;
7e7d76c3 7920
e2e1ed41
DV		 7921 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7922 base.head) {
7923 if (encoder->new_crtc == intel_crtc)
7924 used = true;
7925 }
7926
7927 if (!used)
7928 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7929 }
7930
e2e1ed41
DV		 7931
7932 /* set_mode is also used to update properties on life display pipes. */
7933 intel_crtc = to_intel_crtc(crtc);
7934 if (crtc->enabled)
7935 *prepare_pipes |= 1 << intel_crtc->pipe;
7936
b6c5164d
DV		 7937 /*
7938 * For simplicity do a full modeset on any pipe where the output routing
7939 * changed. We could be more clever, but that would require us to be
7940 * more careful with calling the relevant encoder->mode_set functions.
7941 */
e2e1ed41
DV		 7942 if (*prepare_pipes)
7943 *modeset_pipes = *prepare_pipes;
7944
7945 /* ... and mask these out. */
7946 *modeset_pipes &= ~(*disable_pipes);
7947 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7948
7949 /*
7950 * HACK: We don't (yet) fully support global modesets. intel_set_config
7951 * obies this rule, but the modeset restore mode of
7952 * intel_modeset_setup_hw_state does not.
7953 */
7954 *modeset_pipes &= 1 << intel_crtc->pipe;
7955 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7956
7957 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7958 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7959}
79e53945 7960
ea9d758d 7961static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7962{
ea9d758d 7963 struct drm_encoder *encoder;
f6e5b160 7964 struct drm_device *dev = crtc->dev;
f6e5b160 7965
ea9d758d
DV		 7966 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7967 if (encoder->crtc == crtc)
7968 return true;
7969
7970 return false;
7971}
7972
7973static void
7974intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7975{
7976 struct intel_encoder *intel_encoder;
7977 struct intel_crtc *intel_crtc;
7978 struct drm_connector *connector;
7979
7980 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7981 base.head) {
7982 if (!intel_encoder->base.crtc)
7983 continue;
7984
7985 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7986
7987 if (prepare_pipes & (1 << intel_crtc->pipe))
7988 intel_encoder->connectors_active = false;
7989 }
7990
7991 intel_modeset_commit_output_state(dev);
7992
7993 /* Update computed state. */
7994 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7995 base.head) {
7996 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7997 }
7998
7999 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8000 if (!connector->encoder || !connector->encoder->crtc)
8001 continue;
8002
8003 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8004
8005 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8006 struct drm_property *dpms_property =
8007 dev->mode_config.dpms_property;
8008
ea9d758d 8009 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8010 drm_object_property_set_value(&connector->base,
68d34720
DV		 8011 dpms_property,
8012 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8013
8014 intel_encoder = to_intel_encoder(connector->encoder);
8015 intel_encoder->connectors_active = true;
8016 }
8017 }
8018
8019}
8020
25c5b266
DV		 8021#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8022 list_for_each_entry((intel_crtc), \
8023 &(dev)->mode_config.crtc_list, \
8024 base.head) \
0973f18f 8025 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8026
0e8ffe1b 8027static bool
2fa2fe9a
DV		 8028intel_pipe_config_compare(struct drm_device *dev,
8029 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8030 struct intel_crtc_config *pipe_config)
8031{
66e985c0
DV		 8032#define PIPE_CONF_CHECK_X(name) \
8033 if (current_config->name != pipe_config->name) { \
8034 DRM_ERROR("mismatch in " #name " " \
8035 "(expected 0x%08x, found 0x%08x)\n", \
8036 current_config->name, \
8037 pipe_config->name); \
8038 return false; \
8039 }
8040
08a24034
DV		 8041#define PIPE_CONF_CHECK_I(name) \
8042 if (current_config->name != pipe_config->name) { \
8043 DRM_ERROR("mismatch in " #name " " \
8044 "(expected %i, found %i)\n", \
8045 current_config->name, \
8046 pipe_config->name); \
8047 return false; \
88adfff1
DV		 8048 }
8049
1bd1bd80
DV		 8050#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8051 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8052 DRM_ERROR("mismatch in " #name " " \
8053 "(expected %i, found %i)\n", \
8054 current_config->name & (mask), \
8055 pipe_config->name & (mask)); \
8056 return false; \
8057 }
8058
bb760063
DV		 8059#define PIPE_CONF_QUIRK(quirk) \
8060 ((current_config->quirks | pipe_config->quirks) & (quirk))
8061
eccb140b
DV		 8062 PIPE_CONF_CHECK_I(cpu_transcoder);
8063
08a24034
DV		 8064 PIPE_CONF_CHECK_I(has_pch_encoder);
8065 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8066 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8067 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8068 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8069 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8070 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8071
1bd1bd80
DV		 8072 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8073 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8074 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8075 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8076 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8077 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8078
8079 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8080 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8081 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8082 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8083 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8084 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8085
6c49f241
DV		 8086 if (!HAS_PCH_SPLIT(dev))
8087 PIPE_CONF_CHECK_I(pixel_multiplier);
8088
1bd1bd80
DV		 8089 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8090 DRM_MODE_FLAG_INTERLACE);
8091
bb760063
DV		 8092 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8093 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8094 DRM_MODE_FLAG_PHSYNC);
8095 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8096 DRM_MODE_FLAG_NHSYNC);
8097 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8098 DRM_MODE_FLAG_PVSYNC);
8099 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8100 DRM_MODE_FLAG_NVSYNC);
8101 }
045ac3b5 8102
1bd1bd80
DV		 8103 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8104 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8105
2fa2fe9a
DV		 8106 PIPE_CONF_CHECK_I(gmch_pfit.control);
8107 /* pfit ratios are autocomputed by the hw on gen4+ */
8108 if (INTEL_INFO(dev)->gen < 4)
8109 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8110 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8111 PIPE_CONF_CHECK_I(pch_pfit.pos);
8112 PIPE_CONF_CHECK_I(pch_pfit.size);
8113
42db64ef
PZ		 8114 PIPE_CONF_CHECK_I(ips_enabled);
8115
c0d43d62 8116 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8117 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8118 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8119 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8120 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8121
66e985c0 8122#undef PIPE_CONF_CHECK_X
08a24034 8123#undef PIPE_CONF_CHECK_I
1bd1bd80 8124#undef PIPE_CONF_CHECK_FLAGS
bb760063 8125#undef PIPE_CONF_QUIRK
88adfff1 8126
0e8ffe1b
DV		 8127 return true;
8128}
8129
91d1b4bd
DV		 8130static void
8131check_connector_state(struct drm_device *dev)
8af6cf88 8132{
8af6cf88
DV		 8133 struct intel_connector *connector;
8134
8135 list_for_each_entry(connector, &dev->mode_config.connector_list,
8136 base.head) {
8137 /* This also checks the encoder/connector hw state with the
8138 * ->get_hw_state callbacks. */
8139 intel_connector_check_state(connector);
8140
8141 WARN(&connector->new_encoder->base != connector->base.encoder,
8142 "connector's staged encoder doesn't match current encoder\n");
8143 }
91d1b4bd
DV		 8144}
8145
8146static void
8147check_encoder_state(struct drm_device *dev)
8148{
8149 struct intel_encoder *encoder;
8150 struct intel_connector *connector;
8af6cf88
DV		 8151
8152 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8153 base.head) {
8154 bool enabled = false;
8155 bool active = false;
8156 enum pipe pipe, tracked_pipe;
8157
8158 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8159 encoder->base.base.id,
8160 drm_get_encoder_name(&encoder->base));
8161
8162 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8163 "encoder's stage crtc doesn't match current crtc\n");
8164 WARN(encoder->connectors_active && !encoder->base.crtc,
8165 "encoder's active_connectors set, but no crtc\n");
8166
8167 list_for_each_entry(connector, &dev->mode_config.connector_list,
8168 base.head) {
8169 if (connector->base.encoder != &encoder->base)
8170 continue;
8171 enabled = true;
8172 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8173 active = true;
8174 }
8175 WARN(!!encoder->base.crtc != enabled,
8176 "encoder's enabled state mismatch "
8177 "(expected %i, found %i)\n",
8178 !!encoder->base.crtc, enabled);
8179 WARN(active && !encoder->base.crtc,
8180 "active encoder with no crtc\n");
8181
8182 WARN(encoder->connectors_active != active,
8183 "encoder's computed active state doesn't match tracked active state "
8184 "(expected %i, found %i)\n", active, encoder->connectors_active);
8185
8186 active = encoder->get_hw_state(encoder, &pipe);
8187 WARN(active != encoder->connectors_active,
8188 "encoder's hw state doesn't match sw tracking "
8189 "(expected %i, found %i)\n",
8190 encoder->connectors_active, active);
8191
8192 if (!encoder->base.crtc)
8193 continue;
8194
8195 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8196 WARN(active && pipe != tracked_pipe,
8197 "active encoder's pipe doesn't match"
8198 "(expected %i, found %i)\n",
8199 tracked_pipe, pipe);
8200
8201 }
91d1b4bd
DV		 8202}
8203
8204static void
8205check_crtc_state(struct drm_device *dev)
8206{
8207 drm_i915_private_t *dev_priv = dev->dev_private;
8208 struct intel_crtc *crtc;
8209 struct intel_encoder *encoder;
8210 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8211
8212 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8213 base.head) {
8214 bool enabled = false;
8215 bool active = false;
8216
045ac3b5
JB		 8217 memset(&pipe_config, 0, sizeof(pipe_config));
8218
8af6cf88
DV		 8219 DRM_DEBUG_KMS("[CRTC:%d]\n",
8220 crtc->base.base.id);
8221
8222 WARN(crtc->active && !crtc->base.enabled,
8223 "active crtc, but not enabled in sw tracking\n");
8224
8225 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8226 base.head) {
8227 if (encoder->base.crtc != &crtc->base)
8228 continue;
8229 enabled = true;
8230 if (encoder->connectors_active)
8231 active = true;
8232 }
6c49f241 8233
8af6cf88
DV		 8234 WARN(active != crtc->active,
8235 "crtc's computed active state doesn't match tracked active state "
8236 "(expected %i, found %i)\n", active, crtc->active);
8237 WARN(enabled != crtc->base.enabled,
8238 "crtc's computed enabled state doesn't match tracked enabled state "
8239 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8240
0e8ffe1b
DV		 8241 active = dev_priv->display.get_pipe_config(crtc,
8242 &pipe_config);
d62cf62a
DV		 8243
8244 /* hw state is inconsistent with the pipe A quirk */
8245 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8246 active = crtc->active;
8247
6c49f241
DV		 8248 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8249 base.head) {
8250 if (encoder->base.crtc != &crtc->base)
8251 continue;
8252 if (encoder->get_config)
8253 encoder->get_config(encoder, &pipe_config);
8254 }
8255
0e8ffe1b
DV		 8256 WARN(crtc->active != active,
8257 "crtc active state doesn't match with hw state "
8258 "(expected %i, found %i)\n", crtc->active, active);
8259
c0b03411
DV		 8260 if (active &&
8261 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8262 WARN(1, "pipe state doesn't match!\n");
8263 intel_dump_pipe_config(crtc, &pipe_config,
8264 "[hw state]");
8265 intel_dump_pipe_config(crtc, &crtc->config,
8266 "[sw state]");
8267 }
8af6cf88
DV		 8268 }
8269}
8270
91d1b4bd
DV		 8271static void
8272check_shared_dpll_state(struct drm_device *dev)
8273{
8274 drm_i915_private_t *dev_priv = dev->dev_private;
8275 struct intel_crtc *crtc;
8276 struct intel_dpll_hw_state dpll_hw_state;
8277 int i;
5358901f
DV		 8278
8279 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8280 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8281 int enabled_crtcs = 0, active_crtcs = 0;
8282 bool active;
8283
8284 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8285
8286 DRM_DEBUG_KMS("%s\n", pll->name);
8287
8288 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8289
8290 WARN(pll->active > pll->refcount,
8291 "more active pll users than references: %i vs %i\n",
8292 pll->active, pll->refcount);
8293 WARN(pll->active && !pll->on,
8294 "pll in active use but not on in sw tracking\n");
8295 WARN(pll->on != active,
8296 "pll on state mismatch (expected %i, found %i)\n",
8297 pll->on, active);
8298
8299 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8300 base.head) {
8301 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8302 enabled_crtcs++;
8303 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8304 active_crtcs++;
8305 }
8306 WARN(pll->active != active_crtcs,
8307 "pll active crtcs mismatch (expected %i, found %i)\n",
8308 pll->active, active_crtcs);
8309 WARN(pll->refcount != enabled_crtcs,
8310 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8311 pll->refcount, enabled_crtcs);
66e985c0
DV		 8312
8313 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8314 sizeof(dpll_hw_state)),
8315 "pll hw state mismatch\n");
5358901f 8316 }
8af6cf88
DV		 8317}
8318
91d1b4bd
DV		 8319void
8320intel_modeset_check_state(struct drm_device *dev)
8321{
8322 check_connector_state(dev);
8323 check_encoder_state(dev);
8324 check_crtc_state(dev);
8325 check_shared_dpll_state(dev);
8326}
8327
f30da187
DV		 8328static int __intel_set_mode(struct drm_crtc *crtc,
8329 struct drm_display_mode *mode,
8330 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8331{
8332 struct drm_device *dev = crtc->dev;
dbf2b54e 8333 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8334 struct drm_display_mode *saved_mode, *saved_hwmode;
8335 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8336 struct intel_crtc *intel_crtc;
8337 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8338 int ret = 0;
a6778b3c 8339
3ac18232 8340 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8341 if (!saved_mode)
8342 return -ENOMEM;
3ac18232 8343 saved_hwmode = saved_mode + 1;
a6778b3c 8344
e2e1ed41 8345 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8346 &prepare_pipes, &disable_pipes);
8347
3ac18232
TG		 8348 *saved_hwmode = crtc->hwmode;
8349 *saved_mode = crtc->mode;
a6778b3c 8350
25c5b266
DV		 8351 /* Hack: Because we don't (yet) support global modeset on multiple
8352 * crtcs, we don't keep track of the new mode for more than one crtc.
8353 * Hence simply check whether any bit is set in modeset_pipes in all the
8354 * pieces of code that are not yet converted to deal with mutliple crtcs
8355 * changing their mode at the same time. */
25c5b266 8356 if (modeset_pipes) {
4e53c2e0 8357 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8358 if (IS_ERR(pipe_config)) {
8359 ret = PTR_ERR(pipe_config);
8360 pipe_config = NULL;
8361
3ac18232 8362 goto out;
25c5b266 8363 }
c0b03411
DV		 8364 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8365 "[modeset]");
25c5b266 8366 }
a6778b3c 8367
460da916
DV		 8368 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8369 intel_crtc_disable(&intel_crtc->base);
8370
ea9d758d
DV		 8371 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8372 if (intel_crtc->base.enabled)
8373 dev_priv->display.crtc_disable(&intel_crtc->base);
8374 }
a6778b3c 8375
6c4c86f5
DV		 8376 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8377 * to set it here already despite that we pass it down the callchain.
f6e5b160 8378 */
b8cecdf5 8379 if (modeset_pipes) {
25c5b266 8380 crtc->mode = *mode;
b8cecdf5
DV		 8381 /* mode_set/enable/disable functions rely on a correct pipe
8382 * config. */
8383 to_intel_crtc(crtc)->config = *pipe_config;
8384 }
7758a113 8385
ea9d758d
DV		 8386 /* Only after disabling all output pipelines that will be changed can we
8387 * update the the output configuration. */
8388 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8389
47fab737
DV		 8390 if (dev_priv->display.modeset_global_resources)
8391 dev_priv->display.modeset_global_resources(dev);
8392
a6778b3c
DV		 8393 /* Set up the DPLL and any encoders state that needs to adjust or depend
8394 * on the DPLL.
f6e5b160 8395 */
25c5b266 8396 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8397 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8398 x, y, fb);
8399 if (ret)
8400 goto done;
a6778b3c
DV		 8401 }
8402
8403 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8404 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8405 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8406
25c5b266
DV		 8407 if (modeset_pipes) {
8408 /* Store real post-adjustment hardware mode. */
b8cecdf5 8409 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8410
25c5b266
DV		 8411 /* Calculate and store various constants which
8412 * are later needed by vblank and swap-completion
8413 * timestamping. They are derived from true hwmode.
8414 */
8415 drm_calc_timestamping_constants(crtc);
8416 }
a6778b3c
DV		 8417
8418 /* FIXME: add subpixel order */
8419done:
c0c36b94 8420 if (ret && crtc->enabled) {
3ac18232
TG		 8421 crtc->hwmode = *saved_hwmode;
8422 crtc->mode = *saved_mode;
a6778b3c
DV		 8423 }
8424
3ac18232 8425out:
b8cecdf5 8426 kfree(pipe_config);
3ac18232 8427 kfree(saved_mode);
a6778b3c 8428 return ret;
f6e5b160
CW		 8429}
8430
f30da187
DV		 8431int intel_set_mode(struct drm_crtc *crtc,
8432 struct drm_display_mode *mode,
8433 int x, int y, struct drm_framebuffer *fb)
8434{
8435 int ret;
8436
8437 ret = __intel_set_mode(crtc, mode, x, y, fb);
8438
8439 if (ret == 0)
8440 intel_modeset_check_state(crtc->dev);
8441
8442 return ret;
8443}
8444
c0c36b94
CW		 8445void intel_crtc_restore_mode(struct drm_crtc *crtc)
8446{
8447 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8448}
8449
25c5b266
DV		 8450#undef for_each_intel_crtc_masked
8451
d9e55608
DV		 8452static void intel_set_config_free(struct intel_set_config *config)
8453{
8454 if (!config)
8455 return;
8456
1aa4b628
DV		 8457 kfree(config->save_connector_encoders);
8458 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8459 kfree(config);
8460}
8461
85f9eb71
DV		 8462static int intel_set_config_save_state(struct drm_device *dev,
8463 struct intel_set_config *config)
8464{
85f9eb71
DV		 8465 struct drm_encoder *encoder;
8466 struct drm_connector *connector;
8467 int count;
8468
1aa4b628
DV		 8469 config->save_encoder_crtcs =
8470 kcalloc(dev->mode_config.num_encoder,
8471 sizeof(struct drm_crtc *), GFP_KERNEL);
8472 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8473 return -ENOMEM;
8474
1aa4b628
DV		 8475 config->save_connector_encoders =
8476 kcalloc(dev->mode_config.num_connector,
8477 sizeof(struct drm_encoder *), GFP_KERNEL);
8478 if (!config->save_connector_encoders)
85f9eb71
DV		 8479 return -ENOMEM;
8480
8481 /* Copy data. Note that driver private data is not affected.
8482 * Should anything bad happen only the expected state is
8483 * restored, not the drivers personal bookkeeping.
8484 */
85f9eb71
DV		 8485 count = 0;
8486 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8487 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8488 }
8489
8490 count = 0;
8491 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8492 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8493 }
8494
8495 return 0;
8496}
8497
8498static void intel_set_config_restore_state(struct drm_device *dev,
8499 struct intel_set_config *config)
8500{
9a935856
DV		 8501 struct intel_encoder *encoder;
8502 struct intel_connector *connector;
85f9eb71
DV		 8503 int count;
8504
85f9eb71 8505 count = 0;
9a935856
DV		 8506 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8507 encoder->new_crtc =
8508 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8509 }
8510
8511 count = 0;
9a935856
DV		 8512 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8513 connector->new_encoder =
8514 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8515 }
8516}
8517
e3de42b6
ID		 8518static bool
8519is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8520 int num_connectors)
8521{
8522 int i;
8523
8524 for (i = 0; i < num_connectors; i++)
8525 if (connectors[i].encoder &&
8526 connectors[i].encoder->crtc == crtc &&
8527 connectors[i].dpms != DRM_MODE_DPMS_ON)
8528 return true;
8529
8530 return false;
8531}
8532
5e2b584e
DV		 8533static void
8534intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8535 struct intel_set_config *config)
8536{
8537
8538 /* We should be able to check here if the fb has the same properties
8539 * and then just flip_or_move it */
e3de42b6
ID		 8540 if (set->connectors != NULL &&
8541 is_crtc_connector_off(set->crtc, *set->connectors,
8542 set->num_connectors)) {
8543 config->mode_changed = true;
8544 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8545 /* If we have no fb then treat it as a full mode set */
8546 if (set->crtc->fb == NULL) {
8547 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8548 config->mode_changed = true;
8549 } else if (set->fb == NULL) {
8550 config->mode_changed = true;
72f4901e
DV		 8551 } else if (set->fb->pixel_format !=
8552 set->crtc->fb->pixel_format) {
5e2b584e 8553 config->mode_changed = true;
e3de42b6 8554 } else {
5e2b584e 8555 config->fb_changed = true;
e3de42b6 8556 }
5e2b584e
DV		 8557 }
8558
835c5873 8559 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8560 config->fb_changed = true;
8561
8562 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8563 DRM_DEBUG_KMS("modes are different, full mode set\n");
8564 drm_mode_debug_printmodeline(&set->crtc->mode);
8565 drm_mode_debug_printmodeline(set->mode);
8566 config->mode_changed = true;
8567 }
8568}
8569
2e431051 8570static int
9a935856
DV		 8571intel_modeset_stage_output_state(struct drm_device *dev,
8572 struct drm_mode_set *set,
8573 struct intel_set_config *config)
50f56119 8574{
85f9eb71 8575 struct drm_crtc *new_crtc;
9a935856
DV		 8576 struct intel_connector *connector;
8577 struct intel_encoder *encoder;
2e431051 8578 int count, ro;
50f56119 8579
9abdda74 8580 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8581 * of connectors. For paranoia, double-check this. */
8582 WARN_ON(!set->fb && (set->num_connectors != 0));
8583 WARN_ON(set->fb && (set->num_connectors == 0));
8584
50f56119 8585 count = 0;
9a935856
DV		 8586 list_for_each_entry(connector, &dev->mode_config.connector_list,
8587 base.head) {
8588 /* Otherwise traverse passed in connector list and get encoders
8589 * for them. */
50f56119 8590 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8591 if (set->connectors[ro] == &connector->base) {
8592 connector->new_encoder = connector->encoder;
50f56119
DV		 8593 break;
8594 }
8595 }
8596
9a935856
DV		 8597 /* If we disable the crtc, disable all its connectors. Also, if
8598 * the connector is on the changing crtc but not on the new
8599 * connector list, disable it. */
8600 if ((!set->fb || ro == set->num_connectors) &&
8601 connector->base.encoder &&
8602 connector->base.encoder->crtc == set->crtc) {
8603 connector->new_encoder = NULL;
8604
8605 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8606 connector->base.base.id,
8607 drm_get_connector_name(&connector->base));
8608 }
8609
8610
8611 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8612 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8613 config->mode_changed = true;
50f56119
DV		 8614 }
8615 }
9a935856 8616 /* connector->new_encoder is now updated for all connectors. */
50f56119 8617
9a935856 8618 /* Update crtc of enabled connectors. */
50f56119 8619 count = 0;
9a935856
DV		 8620 list_for_each_entry(connector, &dev->mode_config.connector_list,
8621 base.head) {
8622 if (!connector->new_encoder)
50f56119
DV		 8623 continue;
8624
9a935856 8625 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8626
8627 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8628 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8629 new_crtc = set->crtc;
8630 }
8631
8632 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8633 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8634 new_crtc)) {
5e2b584e 8635 return -EINVAL;
50f56119 8636 }
9a935856
DV		 8637 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8638
8639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8640 connector->base.base.id,
8641 drm_get_connector_name(&connector->base),
8642 new_crtc->base.id);
8643 }
8644
8645 /* Check for any encoders that needs to be disabled. */
8646 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8647 base.head) {
8648 list_for_each_entry(connector,
8649 &dev->mode_config.connector_list,
8650 base.head) {
8651 if (connector->new_encoder == encoder) {
8652 WARN_ON(!connector->new_encoder->new_crtc);
8653
8654 goto next_encoder;
8655 }
8656 }
8657 encoder->new_crtc = NULL;
8658next_encoder:
8659 /* Only now check for crtc changes so we don't miss encoders
8660 * that will be disabled. */
8661 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8662 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8663 config->mode_changed = true;
50f56119
DV		 8664 }
8665 }
9a935856 8666 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8667
2e431051
DV		 8668 return 0;
8669}
8670
8671static int intel_crtc_set_config(struct drm_mode_set *set)
8672{
8673 struct drm_device *dev;
2e431051
DV		 8674 struct drm_mode_set save_set;
8675 struct intel_set_config *config;
8676 int ret;
2e431051 8677
8d3e375e
DV		 8678 BUG_ON(!set);
8679 BUG_ON(!set->crtc);
8680 BUG_ON(!set->crtc->helper_private);
2e431051 8681
7e53f3a4
DV		 8682 /* Enforce sane interface api - has been abused by the fb helper. */
8683 BUG_ON(!set->mode && set->fb);
8684 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8685
2e431051
DV		 8686 if (set->fb) {
8687 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8688 set->crtc->base.id, set->fb->base.id,
8689 (int)set->num_connectors, set->x, set->y);
8690 } else {
8691 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8692 }
8693
8694 dev = set->crtc->dev;
8695
8696 ret = -ENOMEM;
8697 config = kzalloc(sizeof(*config), GFP_KERNEL);
8698 if (!config)
8699 goto out_config;
8700
8701 ret = intel_set_config_save_state(dev, config);
8702 if (ret)
8703 goto out_config;
8704
8705 save_set.crtc = set->crtc;
8706 save_set.mode = &set->crtc->mode;
8707 save_set.x = set->crtc->x;
8708 save_set.y = set->crtc->y;
8709 save_set.fb = set->crtc->fb;
8710
8711 /* Compute whether we need a full modeset, only an fb base update or no
8712 * change at all. In the future we might also check whether only the
8713 * mode changed, e.g. for LVDS where we only change the panel fitter in
8714 * such cases. */
8715 intel_set_config_compute_mode_changes(set, config);
8716
9a935856 8717 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8718 if (ret)
8719 goto fail;
8720
5e2b584e 8721 if (config->mode_changed) {
c0c36b94
CW		 8722 ret = intel_set_mode(set->crtc, set->mode,
8723 set->x, set->y, set->fb);
5e2b584e 8724 } else if (config->fb_changed) {
4878cae2
VS		 8725 intel_crtc_wait_for_pending_flips(set->crtc);
8726
4f660f49 8727 ret = intel_pipe_set_base(set->crtc,
94352cf9 8728 set->x, set->y, set->fb);
50f56119
DV		 8729 }
8730
2d05eae1 8731 if (ret) {
bf67dfeb
DV		 8732 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8733 set->crtc->base.id, ret);
50f56119 8734fail:
2d05eae1 8735 intel_set_config_restore_state(dev, config);
50f56119 8736
2d05eae1
CW		 8737 /* Try to restore the config */
8738 if (config->mode_changed &&
8739 intel_set_mode(save_set.crtc, save_set.mode,
8740 save_set.x, save_set.y, save_set.fb))
8741 DRM_ERROR("failed to restore config after modeset failure\n");
8742 }
50f56119 8743
d9e55608
DV		 8744out_config:
8745 intel_set_config_free(config);
50f56119
DV		 8746 return ret;
8747}
f6e5b160
CW		 8748
8749static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8750 .cursor_set = intel_crtc_cursor_set,
8751 .cursor_move = intel_crtc_cursor_move,
8752 .gamma_set = intel_crtc_gamma_set,
50f56119 8753 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8754 .destroy = intel_crtc_destroy,
8755 .page_flip = intel_crtc_page_flip,
8756};
8757
79f689aa
PZ		 8758static void intel_cpu_pll_init(struct drm_device *dev)
8759{
affa9354 8760 if (HAS_DDI(dev))
79f689aa
PZ		 8761 intel_ddi_pll_init(dev);
8762}
8763
5358901f
DV		 8764static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8765 struct intel_shared_dpll *pll,
8766 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8767{
5358901f 8768 uint32_t val;
ee7b9f93 8769
5358901f 8770 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8771 hw_state->dpll = val;
8772 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8773 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8774
8775 return val & DPLL_VCO_ENABLE;
8776}
8777
15bdd4cf
DV		 8778static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8779 struct intel_shared_dpll *pll)
8780{
8781 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8782 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8783}
8784
e7b903d2
DV		 8785static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8786 struct intel_shared_dpll *pll)
8787{
e7b903d2
DV		 8788 /* PCH refclock must be enabled first */
8789 assert_pch_refclk_enabled(dev_priv);
8790
15bdd4cf
DV		 8791 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8792
8793 /* Wait for the clocks to stabilize. */
8794 POSTING_READ(PCH_DPLL(pll->id));
8795 udelay(150);
8796
8797 /* The pixel multiplier can only be updated once the
8798 * DPLL is enabled and the clocks are stable.
8799 *
8800 * So write it again.
8801 */
8802 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8803 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8804 udelay(200);
8805}
8806
8807static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8808 struct intel_shared_dpll *pll)
8809{
8810 struct drm_device *dev = dev_priv->dev;
8811 struct intel_crtc *crtc;
e7b903d2
DV		 8812
8813 /* Make sure no transcoder isn't still depending on us. */
8814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8815 if (intel_crtc_to_shared_dpll(crtc) == pll)
8816 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8817 }
8818
15bdd4cf
DV		 8819 I915_WRITE(PCH_DPLL(pll->id), 0);
8820 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8821 udelay(200);
8822}
8823
46edb027
DV		 8824static char *ibx_pch_dpll_names[] = {
8825 "PCH DPLL A",
8826 "PCH DPLL B",
8827};
8828
7c74ade1 8829static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8830{
e7b903d2 8831 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8832 int i;
8833
7c74ade1 8834 dev_priv->num_shared_dpll = 2;
ee7b9f93 8835
e72f9fbf 8836 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8837 dev_priv->shared_dplls[i].id = i;
8838 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8839 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8840 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8841 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8842 dev_priv->shared_dplls[i].get_hw_state =
8843 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8844 }
8845}
8846
7c74ade1
DV		 8847static void intel_shared_dpll_init(struct drm_device *dev)
8848{
e7b903d2 8849 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8850
8851 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8852 ibx_pch_dpll_init(dev);
8853 else
8854 dev_priv->num_shared_dpll = 0;
8855
8856 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8857 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8858 dev_priv->num_shared_dpll);
8859}
8860
b358d0a6 8861static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8862{
22fd0fab 8863 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8864 struct intel_crtc *intel_crtc;
8865 int i;
8866
8867 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8868 if (intel_crtc == NULL)
8869 return;
8870
8871 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8872
8873 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8874 for (i = 0; i < 256; i++) {
8875 intel_crtc->lut_r[i] = i;
8876 intel_crtc->lut_g[i] = i;
8877 intel_crtc->lut_b[i] = i;
8878 }
8879
80824003
JB		 8880 /* Swap pipes & planes for FBC on pre-965 */
8881 intel_crtc->pipe = pipe;
8882 intel_crtc->plane = pipe;
e2e767ab 8883 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8884 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8885 intel_crtc->plane = !pipe;
80824003
JB		 8886 }
8887
22fd0fab
JB		 8888 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8889 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8890 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8891 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8892
79e53945 8893 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8894}
8895
08d7b3d1 8896int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8897 struct drm_file *file)
08d7b3d1 8898{
08d7b3d1 8899 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8900 struct drm_mode_object *drmmode_obj;
8901 struct intel_crtc *crtc;
08d7b3d1 8902
1cff8f6b
DV		 8903 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8904 return -ENODEV;
08d7b3d1 8905
c05422d5
DV		 8906 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8907 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8908
c05422d5 8909 if (!drmmode_obj) {
08d7b3d1
CW		 8910 DRM_ERROR("no such CRTC id\n");
8911 return -EINVAL;
8912 }
8913
c05422d5
DV		 8914 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8915 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8916
c05422d5 8917 return 0;
08d7b3d1
CW		 8918}
8919
66a9278e 8920static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8921{
66a9278e
DV		 8922 struct drm_device *dev = encoder->base.dev;
8923 struct intel_encoder *source_encoder;
79e53945 8924 int index_mask = 0;
79e53945
JB		 8925 int entry = 0;
8926
66a9278e
DV		 8927 list_for_each_entry(source_encoder,
8928 &dev->mode_config.encoder_list, base.head) {
8929
8930 if (encoder == source_encoder)
79e53945 8931 index_mask |= (1 << entry);
66a9278e
DV		 8932
8933 /* Intel hw has only one MUX where enocoders could be cloned. */
8934 if (encoder->cloneable && source_encoder->cloneable)
8935 index_mask |= (1 << entry);
8936
79e53945
JB		 8937 entry++;
8938 }
4ef69c7a 8939
79e53945
JB		 8940 return index_mask;
8941}
8942
4d302442
CW		 8943static bool has_edp_a(struct drm_device *dev)
8944{
8945 struct drm_i915_private *dev_priv = dev->dev_private;
8946
8947 if (!IS_MOBILE(dev))
8948 return false;
8949
8950 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8951 return false;
8952
8953 if (IS_GEN5(dev) &&
8954 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8955 return false;
8956
8957 return true;
8958}
8959
79e53945
JB		 8960static void intel_setup_outputs(struct drm_device *dev)
8961{
725e30ad 8962 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8963 struct intel_encoder *encoder;
cb0953d7 8964 bool dpd_is_edp = false;
79e53945 8965
c9093354 8966 intel_lvds_init(dev);
79e53945 8967
c40c0f5b 8968 if (!IS_ULT(dev))
79935fca 8969 intel_crt_init(dev);
cb0953d7 8970
affa9354 8971 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8972 int found;
8973
8974 /* Haswell uses DDI functions to detect digital outputs */
8975 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8976 /* DDI A only supports eDP */
8977 if (found)
8978 intel_ddi_init(dev, PORT_A);
8979
8980 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8981 * register */
8982 found = I915_READ(SFUSE_STRAP);
8983
8984 if (found & SFUSE_STRAP_DDIB_DETECTED)
8985 intel_ddi_init(dev, PORT_B);
8986 if (found & SFUSE_STRAP_DDIC_DETECTED)
8987 intel_ddi_init(dev, PORT_C);
8988 if (found & SFUSE_STRAP_DDID_DETECTED)
8989 intel_ddi_init(dev, PORT_D);
8990 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8991 int found;
270b3042
DV		 8992 dpd_is_edp = intel_dpd_is_edp(dev);
8993
8994 if (has_edp_a(dev))
8995 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8996
dc0fa718 8997 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8998 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8999 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9000 if (!found)
e2debe91 9001 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9002 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9003 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9004 }
9005
dc0fa718 9006 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9007 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9008
dc0fa718 9009 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9010 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9011
5eb08b69 9012 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9013 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9014
270b3042 9015 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9016 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9017 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9018 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9019 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9020 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9021
dc0fa718 9022 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9023 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9024 PORT_B);
67cfc203
VS		 9025 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9026 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9027 }
103a196f 9028 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9029 bool found = false;
7d57382e 9030
e2debe91 9031 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9032 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9033 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9034 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9035 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9036 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9037 }
27185ae1 9038
e7281eab 9039 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9040 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9041 }
13520b05
KH		 9042
9043 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9044
e2debe91 9045 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9046 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9047 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9048 }
27185ae1 9049
e2debe91 9050 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9051
b01f2c3a
JB		 9052 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9053 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9054 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9055 }
e7281eab 9056 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9057 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9058 }
27185ae1 9059
b01f2c3a 9060 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9061 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9062 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9063 } else if (IS_GEN2(dev))
79e53945
JB		 9064 intel_dvo_init(dev);
9065
103a196f 9066 if (SUPPORTS_TV(dev))
79e53945
JB		 9067 intel_tv_init(dev);
9068
4ef69c7a
CW		 9069 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9070 encoder->base.possible_crtcs = encoder->crtc_mask;
9071 encoder->base.possible_clones =
66a9278e 9072 intel_encoder_clones(encoder);
79e53945 9073 }
47356eb6 9074
dde86e2d 9075 intel_init_pch_refclk(dev);
270b3042
DV		 9076
9077 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9078}
9079
9080static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9081{
9082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9083
9084 drm_framebuffer_cleanup(fb);
05394f39 9085 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9086
9087 kfree(intel_fb);
9088}
9089
9090static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9091 struct drm_file *file,
79e53945
JB		 9092 unsigned int *handle)
9093{
9094 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9095 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9096
05394f39 9097 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9098}
9099
9100static const struct drm_framebuffer_funcs intel_fb_funcs = {
9101 .destroy = intel_user_framebuffer_destroy,
9102 .create_handle = intel_user_framebuffer_create_handle,
9103};
9104
38651674
DA		 9105int intel_framebuffer_init(struct drm_device *dev,
9106 struct intel_framebuffer *intel_fb,
308e5bcb 9107 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9108 struct drm_i915_gem_object *obj)
79e53945 9109{
a35cdaa0 9110 int pitch_limit;
79e53945
JB		 9111 int ret;
9112
c16ed4be
CW		 9113 if (obj->tiling_mode == I915_TILING_Y) {
9114 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9115 return -EINVAL;
c16ed4be 9116 }
57cd6508 9117
c16ed4be
CW		 9118 if (mode_cmd->pitches[0] & 63) {
9119 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9120 mode_cmd->pitches[0]);
57cd6508 9121 return -EINVAL;
c16ed4be 9122 }
57cd6508 9123
a35cdaa0
CW		 9124 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9125 pitch_limit = 32*1024;
9126 } else if (INTEL_INFO(dev)->gen >= 4) {
9127 if (obj->tiling_mode)
9128 pitch_limit = 16*1024;
9129 else
9130 pitch_limit = 32*1024;
9131 } else if (INTEL_INFO(dev)->gen >= 3) {
9132 if (obj->tiling_mode)
9133 pitch_limit = 8*1024;
9134 else
9135 pitch_limit = 16*1024;
9136 } else
9137 /* XXX DSPC is limited to 4k tiled */
9138 pitch_limit = 8*1024;
9139
9140 if (mode_cmd->pitches[0] > pitch_limit) {
9141 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9142 obj->tiling_mode ? "tiled" : "linear",
9143 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9144 return -EINVAL;
c16ed4be 9145 }
5d7bd705
VS		 9146
9147 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9148 mode_cmd->pitches[0] != obj->stride) {
9149 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9150 mode_cmd->pitches[0], obj->stride);
5d7bd705 9151 return -EINVAL;
c16ed4be 9152 }
5d7bd705 9153
57779d06 9154 /* Reject formats not supported by any plane early. */
308e5bcb 9155 switch (mode_cmd->pixel_format) {
57779d06 9156 case DRM_FORMAT_C8:
04b3924d
VS		 9157 case DRM_FORMAT_RGB565:
9158 case DRM_FORMAT_XRGB8888:
9159 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9160 break;
9161 case DRM_FORMAT_XRGB1555:
9162 case DRM_FORMAT_ARGB1555:
c16ed4be 9163 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9164 DRM_DEBUG("unsupported pixel format: %s\n",
9165 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9166 return -EINVAL;
c16ed4be 9167 }
57779d06
VS		 9168 break;
9169 case DRM_FORMAT_XBGR8888:
9170 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9171 case DRM_FORMAT_XRGB2101010:
9172 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9173 case DRM_FORMAT_XBGR2101010:
9174 case DRM_FORMAT_ABGR2101010:
c16ed4be 9175 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9176 DRM_DEBUG("unsupported pixel format: %s\n",
9177 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9178 return -EINVAL;
c16ed4be 9179 }
b5626747 9180 break;
04b3924d
VS		 9181 case DRM_FORMAT_YUYV:
9182 case DRM_FORMAT_UYVY:
9183 case DRM_FORMAT_YVYU:
9184 case DRM_FORMAT_VYUY:
c16ed4be 9185 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9186 DRM_DEBUG("unsupported pixel format: %s\n",
9187 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9188 return -EINVAL;
c16ed4be 9189 }
57cd6508
CW		 9190 break;
9191 default:
4ee62c76
VS		 9192 DRM_DEBUG("unsupported pixel format: %s\n",
9193 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9194 return -EINVAL;
9195 }
9196
90f9a336
VS		 9197 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9198 if (mode_cmd->offsets[0] != 0)
9199 return -EINVAL;
9200
c7d73f6a
DV		 9201 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9202 intel_fb->obj = obj;
9203
79e53945
JB		 9204 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9205 if (ret) {
9206 DRM_ERROR("framebuffer init failed %d\n", ret);
9207 return ret;
9208 }
9209
79e53945
JB		 9210 return 0;
9211}
9212
79e53945
JB		 9213static struct drm_framebuffer *
9214intel_user_framebuffer_create(struct drm_device *dev,
9215 struct drm_file *filp,
308e5bcb 9216 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9217{
05394f39 9218 struct drm_i915_gem_object *obj;
79e53945 9219
308e5bcb
JB		 9220 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9221 mode_cmd->handles[0]));
c8725226 9222 if (&obj->base == NULL)
cce13ff7 9223 return ERR_PTR(-ENOENT);
79e53945 9224
d2dff872 9225 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9226}
9227
79e53945 9228static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9229 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9230 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9231};
9232
e70236a8
JB		 9233/* Set up chip specific display functions */
9234static void intel_init_display(struct drm_device *dev)
9235{
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237
ee9300bb
DV		 9238 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9239 dev_priv->display.find_dpll = g4x_find_best_dpll;
9240 else if (IS_VALLEYVIEW(dev))
9241 dev_priv->display.find_dpll = vlv_find_best_dpll;
9242 else if (IS_PINEVIEW(dev))
9243 dev_priv->display.find_dpll = pnv_find_best_dpll;
9244 else
9245 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9246
affa9354 9247 if (HAS_DDI(dev)) {
0e8ffe1b 9248 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9249 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9250 dev_priv->display.crtc_enable = haswell_crtc_enable;
9251 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9252 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9253 dev_priv->display.update_plane = ironlake_update_plane;
9254 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9255 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9256 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9257 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9258 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9259 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9260 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9261 } else if (IS_VALLEYVIEW(dev)) {
9262 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9263 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9264 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9265 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9266 dev_priv->display.off = i9xx_crtc_off;
9267 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9268 } else {
0e8ffe1b 9269 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9270 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9271 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9272 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9273 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9274 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9275 }
e70236a8 9276
e70236a8 9277 /* Returns the core display clock speed */
25eb05fc
JB		 9278 if (IS_VALLEYVIEW(dev))
9279 dev_priv->display.get_display_clock_speed =
9280 valleyview_get_display_clock_speed;
9281 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9282 dev_priv->display.get_display_clock_speed =
9283 i945_get_display_clock_speed;
9284 else if (IS_I915G(dev))
9285 dev_priv->display.get_display_clock_speed =
9286 i915_get_display_clock_speed;
f2b115e6 9287 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9288 dev_priv->display.get_display_clock_speed =
9289 i9xx_misc_get_display_clock_speed;
9290 else if (IS_I915GM(dev))
9291 dev_priv->display.get_display_clock_speed =
9292 i915gm_get_display_clock_speed;
9293 else if (IS_I865G(dev))
9294 dev_priv->display.get_display_clock_speed =
9295 i865_get_display_clock_speed;
f0f8a9ce 9296 else if (IS_I85X(dev))
e70236a8
JB		 9297 dev_priv->display.get_display_clock_speed =
9298 i855_get_display_clock_speed;
9299 else /* 852, 830 */
9300 dev_priv->display.get_display_clock_speed =
9301 i830_get_display_clock_speed;
9302
7f8a8569 9303 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9304 if (IS_GEN5(dev)) {
674cf967 9305 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9306 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9307 } else if (IS_GEN6(dev)) {
674cf967 9308 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9309 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9310 } else if (IS_IVYBRIDGE(dev)) {
9311 /* FIXME: detect B0+ stepping and use auto training */
9312 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9313 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9314 dev_priv->display.modeset_global_resources =
9315 ivb_modeset_global_resources;
c82e4d26
ED		 9316 } else if (IS_HASWELL(dev)) {
9317 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9318 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9319 dev_priv->display.modeset_global_resources =
9320 haswell_modeset_global_resources;
a0e63c22 9321 }
6067aaea 9322 } else if (IS_G4X(dev)) {
e0dac65e 9323 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9324 }
8c9f3aaf
JB		 9325
9326 /* Default just returns -ENODEV to indicate unsupported */
9327 dev_priv->display.queue_flip = intel_default_queue_flip;
9328
9329 switch (INTEL_INFO(dev)->gen) {
9330 case 2:
9331 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9332 break;
9333
9334 case 3:
9335 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9336 break;
9337
9338 case 4:
9339 case 5:
9340 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9341 break;
9342
9343 case 6:
9344 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9345 break;
7c9017e5
JB		 9346 case 7:
9347 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9348 break;
8c9f3aaf 9349 }
e70236a8
JB		 9350}
9351
b690e96c
JB		 9352/*
9353 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9354 * resume, or other times. This quirk makes sure that's the case for
9355 * affected systems.
9356 */
0206e353 9357static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9358{
9359 struct drm_i915_private *dev_priv = dev->dev_private;
9360
9361 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9362 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9363}
9364
435793df
KP		 9365/*
9366 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9367 */
9368static void quirk_ssc_force_disable(struct drm_device *dev)
9369{
9370 struct drm_i915_private *dev_priv = dev->dev_private;
9371 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9372 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9373}
9374
4dca20ef 9375/*
5a15ab5b
CE		 9376 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9377 * brightness value
4dca20ef
CE		 9378 */
9379static void quirk_invert_brightness(struct drm_device *dev)
9380{
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9383 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9384}
9385
b690e96c
JB		 9386struct intel_quirk {
9387 int device;
9388 int subsystem_vendor;
9389 int subsystem_device;
9390 void (*hook)(struct drm_device *dev);
9391};
9392
5f85f176
EE		 9393/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9394struct intel_dmi_quirk {
9395 void (*hook)(struct drm_device *dev);
9396 const struct dmi_system_id (*dmi_id_list)[];
9397};
9398
9399static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9400{
9401 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9402 return 1;
9403}
9404
9405static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9406 {
9407 .dmi_id_list = &(const struct dmi_system_id[]) {
9408 {
9409 .callback = intel_dmi_reverse_brightness,
9410 .ident = "NCR Corporation",
9411 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9412 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9413 },
9414 },
9415 { } /* terminating entry */
9416 },
9417 .hook = quirk_invert_brightness,
9418 },
9419};
9420
c43b5634 9421static struct intel_quirk intel_quirks[] = {
b690e96c 9422 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9423 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9424
b690e96c
JB		 9425 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9426 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9427
b690e96c
JB		 9428 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9429 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9430
ccd0d36e 9431 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9432 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9433 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9434
9435 /* Lenovo U160 cannot use SSC on LVDS */
9436 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9437
9438 /* Sony Vaio Y cannot use SSC on LVDS */
9439 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9440
9441 /* Acer Aspire 5734Z must invert backlight brightness */
9442 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9443
9444 /* Acer/eMachines G725 */
9445 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9446
9447 /* Acer/eMachines e725 */
9448 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9449
9450 /* Acer/Packard Bell NCL20 */
9451 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9452
9453 /* Acer Aspire 4736Z */
9454 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9455};
9456
9457static void intel_init_quirks(struct drm_device *dev)
9458{
9459 struct pci_dev *d = dev->pdev;
9460 int i;
9461
9462 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9463 struct intel_quirk *q = &intel_quirks[i];
9464
9465 if (d->device == q->device &&
9466 (d->subsystem_vendor == q->subsystem_vendor ||
9467 q->subsystem_vendor == PCI_ANY_ID) &&
9468 (d->subsystem_device == q->subsystem_device ||
9469 q->subsystem_device == PCI_ANY_ID))
9470 q->hook(dev);
9471 }
5f85f176
EE		 9472 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9473 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9474 intel_dmi_quirks[i].hook(dev);
9475 }
b690e96c
JB		 9476}
9477
9cce37f4
JB		 9478/* Disable the VGA plane that we never use */
9479static void i915_disable_vga(struct drm_device *dev)
9480{
9481 struct drm_i915_private *dev_priv = dev->dev_private;
9482 u8 sr1;
766aa1c4 9483 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9484
9485 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9486 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9487 sr1 = inb(VGA_SR_DATA);
9488 outb(sr1 | 1<<5, VGA_SR_DATA);
9489 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9490 udelay(300);
9491
9492 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9493 POSTING_READ(vga_reg);
9494}
9495
f817586c
DV		 9496void intel_modeset_init_hw(struct drm_device *dev)
9497{
fa42e23c 9498 intel_init_power_well(dev);
0232e927 9499
a8f78b58
ED		 9500 intel_prepare_ddi(dev);
9501
f817586c
DV		 9502 intel_init_clock_gating(dev);
9503
79f5b2c7 9504 mutex_lock(&dev->struct_mutex);
8090c6b9 9505 intel_enable_gt_powersave(dev);
79f5b2c7 9506 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9507}
9508
7d708ee4
ID		 9509void intel_modeset_suspend_hw(struct drm_device *dev)
9510{
9511 intel_suspend_hw(dev);
9512}
9513
79e53945
JB		 9514void intel_modeset_init(struct drm_device *dev)
9515{
652c393a 9516 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9517 int i, j, ret;
79e53945
JB		 9518
9519 drm_mode_config_init(dev);
9520
9521 dev->mode_config.min_width = 0;
9522 dev->mode_config.min_height = 0;
9523
019d96cb
DA		 9524 dev->mode_config.preferred_depth = 24;
9525 dev->mode_config.prefer_shadow = 1;
9526
e6ecefaa 9527 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9528
b690e96c
JB		 9529 intel_init_quirks(dev);
9530
1fa61106
ED		 9531 intel_init_pm(dev);
9532
e3c74757
BW		 9533 if (INTEL_INFO(dev)->num_pipes == 0)
9534 return;
9535
e70236a8
JB		 9536 intel_init_display(dev);
9537
a6c45cf0
CW		 9538 if (IS_GEN2(dev)) {
9539 dev->mode_config.max_width = 2048;
9540 dev->mode_config.max_height = 2048;
9541 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9542 dev->mode_config.max_width = 4096;
9543 dev->mode_config.max_height = 4096;
79e53945 9544 } else {
a6c45cf0
CW		 9545 dev->mode_config.max_width = 8192;
9546 dev->mode_config.max_height = 8192;
79e53945 9547 }
5d4545ae 9548 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9549
28c97730 9550 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9551 INTEL_INFO(dev)->num_pipes,
9552 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9553
7eb552ae 9554 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9555 intel_crtc_init(dev, i);
7f1f3851
JB		 9556 for (j = 0; j < dev_priv->num_plane; j++) {
9557 ret = intel_plane_init(dev, i, j);
9558 if (ret)
06da8da2
VS		 9559 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9560 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9561 }
79e53945
JB		 9562 }
9563
79f689aa 9564 intel_cpu_pll_init(dev);
e72f9fbf 9565 intel_shared_dpll_init(dev);
ee7b9f93 9566
9cce37f4
JB		 9567 /* Just disable it once at startup */
9568 i915_disable_vga(dev);
79e53945 9569 intel_setup_outputs(dev);
11be49eb
CW		 9570
9571 /* Just in case the BIOS is doing something questionable. */
9572 intel_disable_fbc(dev);
2c7111db
CW		 9573}
9574
24929352
DV		 9575static void
9576intel_connector_break_all_links(struct intel_connector *connector)
9577{
9578 connector->base.dpms = DRM_MODE_DPMS_OFF;
9579 connector->base.encoder = NULL;
9580 connector->encoder->connectors_active = false;
9581 connector->encoder->base.crtc = NULL;
9582}
9583
7fad798e
DV		 9584static void intel_enable_pipe_a(struct drm_device *dev)
9585{
9586 struct intel_connector *connector;
9587 struct drm_connector *crt = NULL;
9588 struct intel_load_detect_pipe load_detect_temp;
9589
9590 /* We can't just switch on the pipe A, we need to set things up with a
9591 * proper mode and output configuration. As a gross hack, enable pipe A
9592 * by enabling the load detect pipe once. */
9593 list_for_each_entry(connector,
9594 &dev->mode_config.connector_list,
9595 base.head) {
9596 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9597 crt = &connector->base;
9598 break;
9599 }
9600 }
9601
9602 if (!crt)
9603 return;
9604
9605 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9606 intel_release_load_detect_pipe(crt, &load_detect_temp);
9607
652c393a 9608
7fad798e
DV		 9609}
9610
fa555837
DV		 9611static bool
9612intel_check_plane_mapping(struct intel_crtc *crtc)
9613{
7eb552ae
BW		 9614 struct drm_device *dev = crtc->base.dev;
9615 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9616 u32 reg, val;
9617
7eb552ae 9618 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9619 return true;
9620
9621 reg = DSPCNTR(!crtc->plane);
9622 val = I915_READ(reg);
9623
9624 if ((val & DISPLAY_PLANE_ENABLE) &&
9625 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9626 return false;
9627
9628 return true;
9629}
9630
24929352
DV		 9631static void intel_sanitize_crtc(struct intel_crtc *crtc)
9632{
9633 struct drm_device *dev = crtc->base.dev;
9634 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9635 u32 reg;
24929352 9636
24929352 9637 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9638 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9639 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9640
9641 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9642 * disable the crtc (and hence change the state) if it is wrong. Note
9643 * that gen4+ has a fixed plane -> pipe mapping. */
9644 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9645 struct intel_connector *connector;
9646 bool plane;
9647
24929352
DV		 9648 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9649 crtc->base.base.id);
9650
9651 /* Pipe has the wrong plane attached and the plane is active.
9652 * Temporarily change the plane mapping and disable everything
9653 * ... */
9654 plane = crtc->plane;
9655 crtc->plane = !plane;
9656 dev_priv->display.crtc_disable(&crtc->base);
9657 crtc->plane = plane;
9658
9659 /* ... and break all links. */
9660 list_for_each_entry(connector, &dev->mode_config.connector_list,
9661 base.head) {
9662 if (connector->encoder->base.crtc != &crtc->base)
9663 continue;
9664
9665 intel_connector_break_all_links(connector);
9666 }
9667
9668 WARN_ON(crtc->active);
9669 crtc->base.enabled = false;
9670 }
24929352 9671
7fad798e
DV		 9672 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9673 crtc->pipe == PIPE_A && !crtc->active) {
9674 /* BIOS forgot to enable pipe A, this mostly happens after
9675 * resume. Force-enable the pipe to fix this, the update_dpms
9676 * call below we restore the pipe to the right state, but leave
9677 * the required bits on. */
9678 intel_enable_pipe_a(dev);
9679 }
9680
24929352
DV		 9681 /* Adjust the state of the output pipe according to whether we
9682 * have active connectors/encoders. */
9683 intel_crtc_update_dpms(&crtc->base);
9684
9685 if (crtc->active != crtc->base.enabled) {
9686 struct intel_encoder *encoder;
9687
9688 /* This can happen either due to bugs in the get_hw_state
9689 * functions or because the pipe is force-enabled due to the
9690 * pipe A quirk. */
9691 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9692 crtc->base.base.id,
9693 crtc->base.enabled ? "enabled" : "disabled",
9694 crtc->active ? "enabled" : "disabled");
9695
9696 crtc->base.enabled = crtc->active;
9697
9698 /* Because we only establish the connector -> encoder ->
9699 * crtc links if something is active, this means the
9700 * crtc is now deactivated. Break the links. connector
9701 * -> encoder links are only establish when things are
9702 * actually up, hence no need to break them. */
9703 WARN_ON(crtc->active);
9704
9705 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9706 WARN_ON(encoder->connectors_active);
9707 encoder->base.crtc = NULL;
9708 }
9709 }
9710}
9711
9712static void intel_sanitize_encoder(struct intel_encoder *encoder)
9713{
9714 struct intel_connector *connector;
9715 struct drm_device *dev = encoder->base.dev;
9716
9717 /* We need to check both for a crtc link (meaning that the
9718 * encoder is active and trying to read from a pipe) and the
9719 * pipe itself being active. */
9720 bool has_active_crtc = encoder->base.crtc &&
9721 to_intel_crtc(encoder->base.crtc)->active;
9722
9723 if (encoder->connectors_active && !has_active_crtc) {
9724 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9725 encoder->base.base.id,
9726 drm_get_encoder_name(&encoder->base));
9727
9728 /* Connector is active, but has no active pipe. This is
9729 * fallout from our resume register restoring. Disable
9730 * the encoder manually again. */
9731 if (encoder->base.crtc) {
9732 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9733 encoder->base.base.id,
9734 drm_get_encoder_name(&encoder->base));
9735 encoder->disable(encoder);
9736 }
9737
9738 /* Inconsistent output/port/pipe state happens presumably due to
9739 * a bug in one of the get_hw_state functions. Or someplace else
9740 * in our code, like the register restore mess on resume. Clamp
9741 * things to off as a safer default. */
9742 list_for_each_entry(connector,
9743 &dev->mode_config.connector_list,
9744 base.head) {
9745 if (connector->encoder != encoder)
9746 continue;
9747
9748 intel_connector_break_all_links(connector);
9749 }
9750 }
9751 /* Enabled encoders without active connectors will be fixed in
9752 * the crtc fixup. */
9753}
9754
44cec740 9755void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9756{
9757 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9758 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9759
9760 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9761 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9762 i915_disable_vga(dev);
0fde901f
KM		 9763 }
9764}
9765
30e984df 9766static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9767{
9768 struct drm_i915_private *dev_priv = dev->dev_private;
9769 enum pipe pipe;
24929352
DV		 9770 struct intel_crtc *crtc;
9771 struct intel_encoder *encoder;
9772 struct intel_connector *connector;
5358901f 9773 int i;
24929352 9774
0e8ffe1b
DV		 9775 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9776 base.head) {
88adfff1 9777 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9778
0e8ffe1b
DV		 9779 crtc->active = dev_priv->display.get_pipe_config(crtc,
9780 &crtc->config);
24929352
DV		 9781
9782 crtc->base.enabled = crtc->active;
9783
9784 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9785 crtc->base.base.id,
9786 crtc->active ? "enabled" : "disabled");
9787 }
9788
5358901f 9789 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9790 if (HAS_DDI(dev))
6441ab5f
PZ		 9791 intel_ddi_setup_hw_pll_state(dev);
9792
5358901f
DV		 9793 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9794 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9795
9796 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9797 pll->active = 0;
9798 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9799 base.head) {
9800 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9801 pll->active++;
9802 }
9803 pll->refcount = pll->active;
9804
9805 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9806 pll->name, pll->refcount);
9807 }
9808
24929352
DV		 9809 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9810 base.head) {
9811 pipe = 0;
9812
9813 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9814 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9815 encoder->base.crtc = &crtc->base;
9816 if (encoder->get_config)
9817 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9818 } else {
9819 encoder->base.crtc = NULL;
9820 }
9821
9822 encoder->connectors_active = false;
9823 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9824 encoder->base.base.id,
9825 drm_get_encoder_name(&encoder->base),
9826 encoder->base.crtc ? "enabled" : "disabled",
9827 pipe);
9828 }
9829
9830 list_for_each_entry(connector, &dev->mode_config.connector_list,
9831 base.head) {
9832 if (connector->get_hw_state(connector)) {
9833 connector->base.dpms = DRM_MODE_DPMS_ON;
9834 connector->encoder->connectors_active = true;
9835 connector->base.encoder = &connector->encoder->base;
9836 } else {
9837 connector->base.dpms = DRM_MODE_DPMS_OFF;
9838 connector->base.encoder = NULL;
9839 }
9840 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9841 connector->base.base.id,
9842 drm_get_connector_name(&connector->base),
9843 connector->base.encoder ? "enabled" : "disabled");
9844 }
30e984df
DV		 9845}
9846
9847/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9848 * and i915 state tracking structures. */
9849void intel_modeset_setup_hw_state(struct drm_device *dev,
9850 bool force_restore)
9851{
9852 struct drm_i915_private *dev_priv = dev->dev_private;
9853 enum pipe pipe;
9854 struct drm_plane *plane;
9855 struct intel_crtc *crtc;
9856 struct intel_encoder *encoder;
9857
9858 intel_modeset_readout_hw_state(dev);
24929352
DV		 9859
9860 /* HW state is read out, now we need to sanitize this mess. */
9861 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9862 base.head) {
9863 intel_sanitize_encoder(encoder);
9864 }
9865
9866 for_each_pipe(pipe) {
9867 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9868 intel_sanitize_crtc(crtc);
c0b03411 9869 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9870 }
9a935856 9871
45e2b5f6 9872 if (force_restore) {
f30da187
DV		 9873 /*
9874 * We need to use raw interfaces for restoring state to avoid
9875 * checking (bogus) intermediate states.
9876 */
45e2b5f6 9877 for_each_pipe(pipe) {
b5644d05
JB		 9878 struct drm_crtc *crtc =
9879 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9880
9881 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9882 crtc->fb);
45e2b5f6 9883 }
b5644d05
JB		 9884 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9885 intel_plane_restore(plane);
0fde901f
KM		 9886
9887 i915_redisable_vga(dev);
45e2b5f6
DV		 9888 } else {
9889 intel_modeset_update_staged_output_state(dev);
9890 }
8af6cf88
DV		 9891
9892 intel_modeset_check_state(dev);
2e938892
DV		 9893
9894 drm_mode_config_reset(dev);
2c7111db
CW		 9895}
9896
9897void intel_modeset_gem_init(struct drm_device *dev)
9898{
1833b134 9899 intel_modeset_init_hw(dev);
02e792fb
DV		 9900
9901 intel_setup_overlay(dev);
24929352 9902
45e2b5f6 9903 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9904}
9905
9906void intel_modeset_cleanup(struct drm_device *dev)
9907{
652c393a
JB		 9908 struct drm_i915_private *dev_priv = dev->dev_private;
9909 struct drm_crtc *crtc;
9910 struct intel_crtc *intel_crtc;
9911
fd0c0642
DV		 9912 /*
9913 * Interrupts and polling as the first thing to avoid creating havoc.
9914 * Too much stuff here (turning of rps, connectors, ...) would
9915 * experience fancy races otherwise.
9916 */
9917 drm_irq_uninstall(dev);
9918 cancel_work_sync(&dev_priv->hotplug_work);
9919 /*
9920 * Due to the hpd irq storm handling the hotplug work can re-arm the
9921 * poll handlers. Hence disable polling after hpd handling is shut down.
9922 */
f87ea761 9923 drm_kms_helper_poll_fini(dev);
fd0c0642 9924
652c393a
JB		 9925 mutex_lock(&dev->struct_mutex);
9926
723bfd70
JB		 9927 intel_unregister_dsm_handler();
9928
652c393a
JB		 9929 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9930 /* Skip inactive CRTCs */
9931 if (!crtc->fb)
9932 continue;
9933
9934 intel_crtc = to_intel_crtc(crtc);
3dec0095 9935 intel_increase_pllclock(crtc);
652c393a
JB		 9936 }
9937
973d04f9 9938 intel_disable_fbc(dev);
e70236a8 9939
8090c6b9 9940 intel_disable_gt_powersave(dev);
0cdab21f 9941
930ebb46
DV		 9942 ironlake_teardown_rc6(dev);
9943
69341a5e
KH		 9944 mutex_unlock(&dev->struct_mutex);
9945
1630fe75
CW		 9946 /* flush any delayed tasks or pending work */
9947 flush_scheduled_work();
9948
dc652f90
JN		 9949 /* destroy backlight, if any, before the connectors */
9950 intel_panel_destroy_backlight(dev);
9951
79e53945 9952 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9953
9954 intel_cleanup_overlay(dev);
79e53945
JB		 9955}
9956
f1c79df3
ZW		 9957/*
9958 * Return which encoder is currently attached for connector.
9959 */
df0e9248 9960struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9961{
df0e9248
CW		 9962 return &intel_attached_encoder(connector)->base;
9963}
f1c79df3 9964
df0e9248
CW		 9965void intel_connector_attach_encoder(struct intel_connector *connector,
9966 struct intel_encoder *encoder)
9967{
9968 connector->encoder = encoder;
9969 drm_mode_connector_attach_encoder(&connector->base,
9970 &encoder->base);
79e53945 9971}
28d52043
DA		 9972
9973/*
9974 * set vga decode state - true == enable VGA decode
9975 */
9976int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9977{
9978 struct drm_i915_private *dev_priv = dev->dev_private;
9979 u16 gmch_ctrl;
9980
9981 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9982 if (state)
9983 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9984 else
9985 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9986 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9987 return 0;
9988}
c4a1d9e4
CW		 9989
9990#ifdef CONFIG_DEBUG_FS
9991#include <linux/seq_file.h>
9992
9993struct intel_display_error_state {
ff57f1b0
PZ		 9994
9995 u32 power_well_driver;
9996
c4a1d9e4
CW		 9997 struct intel_cursor_error_state {
9998 u32 control;
9999 u32 position;
10000 u32 base;
10001 u32 size;
52331309 10002 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10003
10004 struct intel_pipe_error_state {
ff57f1b0 10005 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10006 u32 conf;
10007 u32 source;
10008
10009 u32 htotal;
10010 u32 hblank;
10011 u32 hsync;
10012 u32 vtotal;
10013 u32 vblank;
10014 u32 vsync;
52331309 10015 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10016
10017 struct intel_plane_error_state {
10018 u32 control;
10019 u32 stride;
10020 u32 size;
10021 u32 pos;
10022 u32 addr;
10023 u32 surface;
10024 u32 tile_offset;
52331309 10025 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10026};
10027
10028struct intel_display_error_state *
10029intel_display_capture_error_state(struct drm_device *dev)
10030{
0206e353 10031 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10032 struct intel_display_error_state *error;
702e7a56 10033 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10034 int i;
10035
10036 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10037 if (error == NULL)
10038 return NULL;
10039
ff57f1b0
PZ		 10040 if (HAS_POWER_WELL(dev))
10041 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10042
52331309 10043 for_each_pipe(i) {
702e7a56 10044 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10045 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10046
a18c4c3d
PZ		 10047 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10048 error->cursor[i].control = I915_READ(CURCNTR(i));
10049 error->cursor[i].position = I915_READ(CURPOS(i));
10050 error->cursor[i].base = I915_READ(CURBASE(i));
10051 } else {
10052 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10053 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10054 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10055 }
c4a1d9e4
CW		 10056
10057 error->plane[i].control = I915_READ(DSPCNTR(i));
10058 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10059 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10060 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10061 error->plane[i].pos = I915_READ(DSPPOS(i));
10062 }
ca291363
PZ		 10063 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10064 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10065 if (INTEL_INFO(dev)->gen >= 4) {
10066 error->plane[i].surface = I915_READ(DSPSURF(i));
10067 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10068 }
10069
702e7a56 10070 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10071 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10072 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10073 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10074 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10075 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10076 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10077 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10078 }
10079
12d217c7
PZ		 10080 /* In the code above we read the registers without checking if the power
10081 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10082 * prevent the next I915_WRITE from detecting it and printing an error
10083 * message. */
10084 if (HAS_POWER_WELL(dev))
10085 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10086
c4a1d9e4
CW		 10087 return error;
10088}
10089
edc3d884
MK		 10090#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10091
c4a1d9e4 10092void
edc3d884 10093intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10094 struct drm_device *dev,
10095 struct intel_display_error_state *error)
10096{
10097 int i;
10098
edc3d884 10099 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10100 if (HAS_POWER_WELL(dev))
edc3d884 10101 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10102 error->power_well_driver);
52331309 10103 for_each_pipe(i) {
edc3d884
MK		 10104 err_printf(m, "Pipe [%d]:\n", i);
10105 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10106 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10107 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10108 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10109 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10110 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10111 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10112 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10113 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10114 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10115
10116 err_printf(m, "Plane [%d]:\n", i);
10117 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10118 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10119 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10120 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10121 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10122 }
4b71a570 10123 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10124 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10125 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10126 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10127 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10128 }
10129
edc3d884
MK		 10130 err_printf(m, "Cursor [%d]:\n", i);
10131 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10132 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10133 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10134 }
10135}
10136#endif
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