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drm/i915: use CPU and PCH transcoders on lpt_enable_pch_transcoder
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af
JB		 1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
5f7f726d 1694 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1695
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1697 /*
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1700 */
1701 val &= ~PIPE_BPC_MASK;
5f7f726d 1702 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1703 }
5f7f726d
PZ		 1704
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1710 else
1711 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1712 else
1713 val |= TRANS_PROGRESSIVE;
1714
040484af
JB		 1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718}
1719
8fb033d7 1720static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1721 enum transcoder cpu_transcoder)
8fb033d7 1722{
8fb033d7 1723 u32 val, pipeconf_val;
8fb033d7
PZ		 1724
1725 /* PCH only available on ILK+ */
1726 BUG_ON(dev_priv->info->gen < 5);
1727
8fb033d7 1728 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1729 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1731
937bb610
PZ		 1732 val = I915_READ(_TRANSACONF);
1733 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1734
8fb033d7
PZ		 1735 val &= ~TRANS_INTERLACE_MASK;
1736 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
a35f2679 1737 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1738 else
1739 val |= TRANS_PROGRESSIVE;
1740
937bb610
PZ		 1741 I915_WRITE(_TRANSACONF, val | TRANS_ENABLE);
1742 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1743 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1744}
1745
b8a4f404
PZ		 1746static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1747 enum pipe pipe)
040484af
JB		 1748{
1749 int reg;
1750 u32 val;
1751
1752 /* FDI relies on the transcoder */
1753 assert_fdi_tx_disabled(dev_priv, pipe);
1754 assert_fdi_rx_disabled(dev_priv, pipe);
1755
291906f1
JB		 1756 /* Ports must be off as well */
1757 assert_pch_ports_disabled(dev_priv, pipe);
1758
040484af
JB		 1759 reg = TRANSCONF(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_ENABLE;
1762 I915_WRITE(reg, val);
1763 /* wait for PCH transcoder off, transcoder state */
1764 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1765 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1766}
1767
8fb033d7
PZ		 1768static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
1770{
1771 int reg;
1772 u32 val;
1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788}
1789
b24e7179 1790/**
309cfea8 1791 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1792 * @dev_priv: i915 private structure
1793 * @pipe: pipe to enable
040484af 1794 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1795 *
1796 * Enable @pipe, making sure that various hardware specific requirements
1797 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1798 *
1799 * @pipe should be %PIPE_A or %PIPE_B.
1800 *
1801 * Will wait until the pipe is actually running (i.e. first vblank) before
1802 * returning.
1803 */
040484af
JB		 1804static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1805 bool pch_port)
b24e7179 1806{
702e7a56
PZ		 1807 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1808 pipe);
b24e7179
JB		 1809 int reg;
1810 u32 val;
1811
1812 /*
1813 * A pipe without a PLL won't actually be able to drive bits from
1814 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1815 * need the check.
1816 */
1817 if (!HAS_PCH_SPLIT(dev_priv->dev))
1818 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1819 else {
1820 if (pch_port) {
1821 /* if driving the PCH, we need FDI enabled */
1822 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1823 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
14667a4b
CW		 2221static int
2222intel_finish_fb(struct drm_framebuffer *old_fb)
2223{
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2227 int ret;
2228
2229 wait_event(dev_priv->pending_flip_queue,
2230 atomic_read(&dev_priv->mm.wedged) ||
2231 atomic_read(&obj->pending_flip) == 0);
2232
2233 /* Big Hammer, we also need to ensure that any pending
2234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235 * current scanout is retired before unpinning the old
2236 * framebuffer.
2237 *
2238 * This should only fail upon a hung GPU, in which case we
2239 * can safely continue.
2240 */
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_finish_gpu(obj);
2243 dev_priv->mm.interruptible = was_interruptible;
2244
2245 return ret;
2246}
2247
198598d0
VS		 2248static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_master_private *master_priv;
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254 if (!dev->primary->master)
2255 return;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return;
2260
2261 switch (intel_crtc->pipe) {
2262 case 0:
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
2265 break;
2266 case 1:
2267 master_priv->sarea_priv->pipeB_x = x;
2268 master_priv->sarea_priv->pipeB_y = y;
2269 break;
2270 default:
2271 break;
2272 }
2273}
2274
5c3b82e2 2275static int
3c4fdcfb 2276intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2277 struct drm_framebuffer *fb)
79e53945
JB		 2278{
2279 struct drm_device *dev = crtc->dev;
6b8e6ed0 2280 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2282 struct drm_framebuffer *old_fb;
5c3b82e2 2283 int ret;
79e53945
JB		 2284
2285 /* no fb bound */
94352cf9 2286 if (!fb) {
a5071c2f 2287 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2288 return 0;
2289 }
2290
5826eca5
ED		 2291 if(intel_crtc->plane > dev_priv->num_pipe) {
2292 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2293 intel_crtc->plane,
2294 dev_priv->num_pipe);
5c3b82e2 2295 return -EINVAL;
79e53945
JB		 2296 }
2297
5c3b82e2 2298 mutex_lock(&dev->struct_mutex);
265db958 2299 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2300 to_intel_framebuffer(fb)->obj,
919926ae 2301 NULL);
5c3b82e2
CW		 2302 if (ret != 0) {
2303 mutex_unlock(&dev->struct_mutex);
a5071c2f 2304 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2305 return ret;
2306 }
79e53945 2307
94352cf9
DV		 2308 if (crtc->fb)
2309 intel_finish_fb(crtc->fb);
265db958 2310
94352cf9 2311 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2312 if (ret) {
94352cf9 2313 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2314 mutex_unlock(&dev->struct_mutex);
a5071c2f 2315 DRM_ERROR("failed to update base address\n");
4e6cfefc 2316 return ret;
79e53945 2317 }
3c4fdcfb 2318
94352cf9
DV		 2319 old_fb = crtc->fb;
2320 crtc->fb = fb;
6c4c86f5
DV		 2321 crtc->x = x;
2322 crtc->y = y;
94352cf9 2323
b7f1de28
CW		 2324 if (old_fb) {
2325 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2326 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2327 }
652c393a 2328
6b8e6ed0 2329 intel_update_fbc(dev);
5c3b82e2 2330 mutex_unlock(&dev->struct_mutex);
79e53945 2331
198598d0 2332 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2333
2334 return 0;
79e53945
JB		 2335}
2336
5eddb70b 2337static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2338{
2339 struct drm_device *dev = crtc->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 u32 dpa_ctl;
2342
28c97730 2343 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2344 dpa_ctl = I915_READ(DP_A);
2345 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2346
2347 if (clock < 200000) {
2348 u32 temp;
2349 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2350 /* workaround for 160Mhz:
2351 1) program 0x4600c bits 15:0 = 0x8124
2352 2) program 0x46010 bit 0 = 1
2353 3) program 0x46034 bit 24 = 1
2354 4) program 0x64000 bit 14 = 1
2355 */
2356 temp = I915_READ(0x4600c);
2357 temp &= 0xffff0000;
2358 I915_WRITE(0x4600c, temp | 0x8124);
2359
2360 temp = I915_READ(0x46010);
2361 I915_WRITE(0x46010, temp | 1);
2362
2363 temp = I915_READ(0x46034);
2364 I915_WRITE(0x46034, temp | (1 << 24));
2365 } else {
2366 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2367 }
2368 I915_WRITE(DP_A, dpa_ctl);
2369
5eddb70b 2370 POSTING_READ(DP_A);
32f9d658
ZW		 2371 udelay(500);
2372}
2373
5e84e1a4
ZW		 2374static void intel_fdi_normal_train(struct drm_crtc *crtc)
2375{
2376 struct drm_device *dev = crtc->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 int pipe = intel_crtc->pipe;
2380 u32 reg, temp;
2381
2382 /* enable normal train */
2383 reg = FDI_TX_CTL(pipe);
2384 temp = I915_READ(reg);
61e499bf 2385 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2386 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2387 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2391 }
5e84e1a4
ZW		 2392 I915_WRITE(reg, temp);
2393
2394 reg = FDI_RX_CTL(pipe);
2395 temp = I915_READ(reg);
2396 if (HAS_PCH_CPT(dev)) {
2397 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2398 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2399 } else {
2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_NONE;
2402 }
2403 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2404
2405 /* wait one idle pattern time */
2406 POSTING_READ(reg);
2407 udelay(1000);
357555c0
JB		 2408
2409 /* IVB wants error correction enabled */
2410 if (IS_IVYBRIDGE(dev))
2411 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2412 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2413}
2414
291427f5
JB		 2415static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 u32 flags = I915_READ(SOUTH_CHICKEN1);
2419
2420 flags |= FDI_PHASE_SYNC_OVR(pipe);
2421 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2422 flags |= FDI_PHASE_SYNC_EN(pipe);
2423 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2424 POSTING_READ(SOUTH_CHICKEN1);
2425}
2426
01a415fd
DV		 2427static void ivb_modeset_global_resources(struct drm_device *dev)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *pipe_B_crtc =
2431 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432 struct intel_crtc *pipe_C_crtc =
2433 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434 uint32_t temp;
2435
2436 /* When everything is off disable fdi C so that we could enable fdi B
2437 * with all lanes. XXX: This misses the case where a pipe is not using
2438 * any pch resources and so doesn't need any fdi lanes. */
2439 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2442
2443 temp = I915_READ(SOUTH_CHICKEN1);
2444 temp &= ~FDI_BC_BIFURCATION_SELECT;
2445 DRM_DEBUG_KMS("disabling fdi C rx\n");
2446 I915_WRITE(SOUTH_CHICKEN1, temp);
2447 }
2448}
2449
8db9d77b
ZW		 2450/* The FDI link training functions for ILK/Ibexpeak. */
2451static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2452{
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
0fc932b8 2457 int plane = intel_crtc->plane;
5eddb70b 2458 u32 reg, temp, tries;
8db9d77b 2459
0fc932b8
JB		 2460 /* FDI needs bits from pipe & plane first */
2461 assert_pipe_enabled(dev_priv, pipe);
2462 assert_plane_enabled(dev_priv, plane);
2463
e1a44743
AJ		 2464 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2465 for train result */
5eddb70b
CW		 2466 reg = FDI_RX_IMR(pipe);
2467 temp = I915_READ(reg);
e1a44743
AJ		 2468 temp &= ~FDI_RX_SYMBOL_LOCK;
2469 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2470 I915_WRITE(reg, temp);
2471 I915_READ(reg);
e1a44743
AJ		 2472 udelay(150);
2473
8db9d77b 2474 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2475 reg = FDI_TX_CTL(pipe);
2476 temp = I915_READ(reg);
77ffb597
AJ		 2477 temp &= ~(7 << 19);
2478 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2479 temp &= ~FDI_LINK_TRAIN_NONE;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2482
5eddb70b
CW		 2483 reg = FDI_RX_CTL(pipe);
2484 temp = I915_READ(reg);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2487 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488
2489 POSTING_READ(reg);
8db9d77b
ZW		 2490 udelay(150);
2491
5b2adf89 2492 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2493 if (HAS_PCH_IBX(dev)) {
2494 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2495 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2496 FDI_RX_PHASE_SYNC_POINTER_EN);
2497 }
5b2adf89 2498
5eddb70b 2499 reg = FDI_RX_IIR(pipe);
e1a44743 2500 for (tries = 0; tries < 5; tries++) {
5eddb70b 2501 temp = I915_READ(reg);
8db9d77b
ZW		 2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503
2504 if ((temp & FDI_RX_BIT_LOCK)) {
2505 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2507 break;
2508 }
8db9d77b 2509 }
e1a44743 2510 if (tries == 5)
5eddb70b 2511 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2512
2513 /* Train 2 */
5eddb70b
CW		 2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
8db9d77b
ZW		 2516 temp &= ~FDI_LINK_TRAIN_NONE;
2517 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2518 I915_WRITE(reg, temp);
8db9d77b 2519
5eddb70b
CW		 2520 reg = FDI_RX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2524 I915_WRITE(reg, temp);
8db9d77b 2525
5eddb70b
CW		 2526 POSTING_READ(reg);
2527 udelay(150);
8db9d77b 2528
5eddb70b 2529 reg = FDI_RX_IIR(pipe);
e1a44743 2530 for (tries = 0; tries < 5; tries++) {
5eddb70b 2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2535 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI train 2 done.\n");
2537 break;
2538 }
8db9d77b 2539 }
e1a44743 2540 if (tries == 5)
5eddb70b 2541 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2542
2543 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2544
8db9d77b
ZW		 2545}
2546
0206e353 2547static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2548 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2552};
2553
2554/* The FDI link training functions for SNB/Cougarpoint. */
2555static void gen6_fdi_link_train(struct drm_crtc *crtc)
2556{
2557 struct drm_device *dev = crtc->dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560 int pipe = intel_crtc->pipe;
fa37d39e 2561 u32 reg, temp, i, retry;
8db9d77b 2562
e1a44743
AJ		 2563 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564 for train result */
5eddb70b
CW		 2565 reg = FDI_RX_IMR(pipe);
2566 temp = I915_READ(reg);
e1a44743
AJ		 2567 temp &= ~FDI_RX_SYMBOL_LOCK;
2568 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2569 I915_WRITE(reg, temp);
2570
2571 POSTING_READ(reg);
e1a44743
AJ		 2572 udelay(150);
2573
8db9d77b 2574 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2575 reg = FDI_TX_CTL(pipe);
2576 temp = I915_READ(reg);
77ffb597
AJ		 2577 temp &= ~(7 << 19);
2578 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2579 temp &= ~FDI_LINK_TRAIN_NONE;
2580 temp |= FDI_LINK_TRAIN_PATTERN_1;
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2584 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2585
d74cf324
DV		 2586 I915_WRITE(FDI_RX_MISC(pipe),
2587 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2588
5eddb70b
CW		 2589 reg = FDI_RX_CTL(pipe);
2590 temp = I915_READ(reg);
8db9d77b
ZW		 2591 if (HAS_PCH_CPT(dev)) {
2592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594 } else {
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597 }
5eddb70b
CW		 2598 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600 POSTING_READ(reg);
8db9d77b
ZW		 2601 udelay(150);
2602
291427f5
JB		 2603 if (HAS_PCH_CPT(dev))
2604 cpt_phase_pointer_enable(dev, pipe);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
8db9d77b
ZW		 2614 udelay(500);
2615
fa37d39e
SP		 2616 for (retry = 0; retry < 5; retry++) {
2617 reg = FDI_RX_IIR(pipe);
2618 temp = I915_READ(reg);
2619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620 if (temp & FDI_RX_BIT_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623 break;
2624 }
2625 udelay(50);
8db9d77b 2626 }
fa37d39e
SP		 2627 if (retry < 5)
2628 break;
8db9d77b
ZW		 2629 }
2630 if (i == 4)
5eddb70b 2631 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2632
2633 /* Train 2 */
5eddb70b
CW		 2634 reg = FDI_TX_CTL(pipe);
2635 temp = I915_READ(reg);
8db9d77b
ZW		 2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2;
2638 if (IS_GEN6(dev)) {
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 /* SNB-B */
2641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642 }
5eddb70b 2643 I915_WRITE(reg, temp);
8db9d77b 2644
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 if (HAS_PCH_CPT(dev)) {
2648 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650 } else {
2651 temp &= ~FDI_LINK_TRAIN_NONE;
2652 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653 }
5eddb70b
CW		 2654 I915_WRITE(reg, temp);
2655
2656 POSTING_READ(reg);
8db9d77b
ZW		 2657 udelay(150);
2658
0206e353 2659 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
8db9d77b
ZW		 2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2664 I915_WRITE(reg, temp);
2665
2666 POSTING_READ(reg);
8db9d77b
ZW		 2667 udelay(500);
2668
fa37d39e
SP		 2669 for (retry = 0; retry < 5; retry++) {
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673 if (temp & FDI_RX_SYMBOL_LOCK) {
2674 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676 break;
2677 }
2678 udelay(50);
8db9d77b 2679 }
fa37d39e
SP		 2680 if (retry < 5)
2681 break;
8db9d77b
ZW		 2682 }
2683 if (i == 4)
5eddb70b 2684 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2685
2686 DRM_DEBUG_KMS("FDI train done.\n");
2687}
2688
357555c0
JB		 2689/* Manual link training for Ivy Bridge A0 parts */
2690static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691{
2692 struct drm_device *dev = crtc->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp, i;
2697
2698 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699 for train result */
2700 reg = FDI_RX_IMR(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~FDI_RX_SYMBOL_LOCK;
2703 temp &= ~FDI_RX_BIT_LOCK;
2704 I915_WRITE(reg, temp);
2705
2706 POSTING_READ(reg);
2707 udelay(150);
2708
01a415fd
DV		 2709 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710 I915_READ(FDI_RX_IIR(pipe)));
2711
357555c0
JB		 2712 /* enable CPU FDI TX and PCH FDI RX */
2713 reg = FDI_TX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~(7 << 19);
2716 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2717 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2721 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2722 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2723
d74cf324
DV		 2724 I915_WRITE(FDI_RX_MISC(pipe),
2725 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2726
357555c0
JB		 2727 reg = FDI_RX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 temp &= ~FDI_LINK_TRAIN_AUTO;
2730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2732 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2733 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2734
2735 POSTING_READ(reg);
2736 udelay(150);
2737
291427f5
JB		 2738 if (HAS_PCH_CPT(dev))
2739 cpt_phase_pointer_enable(dev, pipe);
2740
0206e353 2741 for (i = 0; i < 4; i++) {
357555c0
JB		 2742 reg = FDI_TX_CTL(pipe);
2743 temp = I915_READ(reg);
2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= snb_b_fdi_train_param[i];
2746 I915_WRITE(reg, temp);
2747
2748 POSTING_READ(reg);
2749 udelay(500);
2750
2751 reg = FDI_RX_IIR(pipe);
2752 temp = I915_READ(reg);
2753 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2754
2755 if (temp & FDI_RX_BIT_LOCK ||
2756 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2757 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2758 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2759 break;
2760 }
2761 }
2762 if (i == 4)
2763 DRM_ERROR("FDI train 1 fail!\n");
2764
2765 /* Train 2 */
2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2769 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2770 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2771 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2772 I915_WRITE(reg, temp);
2773
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2778 I915_WRITE(reg, temp);
2779
2780 POSTING_READ(reg);
2781 udelay(150);
2782
0206e353 2783 for (i = 0; i < 4; i++) {
357555c0
JB		 2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787 temp |= snb_b_fdi_train_param[i];
2788 I915_WRITE(reg, temp);
2789
2790 POSTING_READ(reg);
2791 udelay(500);
2792
2793 reg = FDI_RX_IIR(pipe);
2794 temp = I915_READ(reg);
2795 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2796
2797 if (temp & FDI_RX_SYMBOL_LOCK) {
2798 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2799 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2800 break;
2801 }
2802 }
2803 if (i == 4)
2804 DRM_ERROR("FDI train 2 fail!\n");
2805
2806 DRM_DEBUG_KMS("FDI train done.\n");
2807}
2808
88cefb6c 2809static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2810{
88cefb6c 2811 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2812 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2813 int pipe = intel_crtc->pipe;
5eddb70b 2814 u32 reg, temp;
79e53945 2815
c64e311e 2816
c98e9dcf 2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2821 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825 POSTING_READ(reg);
c98e9dcf
JB		 2826 udelay(200);
2827
2828 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832 POSTING_READ(reg);
c98e9dcf
JB		 2833 udelay(200);
2834
bf507ef7
ED		 2835 /* On Haswell, the PLL configuration for ports and pipes is handled
2836 * separately, as part of DDI setup */
2837 if (!IS_HASWELL(dev)) {
2838 /* Enable CPU FDI TX PLL, always on for Ironlake */
2839 reg = FDI_TX_CTL(pipe);
2840 temp = I915_READ(reg);
2841 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2842 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2843
bf507ef7
ED		 2844 POSTING_READ(reg);
2845 udelay(100);
2846 }
6be4a607 2847 }
0e23b99d
JB		 2848}
2849
88cefb6c
DV		 2850static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2851{
2852 struct drm_device *dev = intel_crtc->base.dev;
2853 struct drm_i915_private *dev_priv = dev->dev_private;
2854 int pipe = intel_crtc->pipe;
2855 u32 reg, temp;
2856
2857 /* Switch from PCDclk to Rawclk */
2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2861
2862 /* Disable CPU FDI TX PLL */
2863 reg = FDI_TX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2866
2867 POSTING_READ(reg);
2868 udelay(100);
2869
2870 reg = FDI_RX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2873
2874 /* Wait for the clocks to turn off. */
2875 POSTING_READ(reg);
2876 udelay(100);
2877}
2878
291427f5
JB		 2879static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2880{
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 u32 flags = I915_READ(SOUTH_CHICKEN1);
2883
2884 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2885 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2886 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2887 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2888 POSTING_READ(SOUTH_CHICKEN1);
2889}
0fc932b8
JB		 2890static void ironlake_fdi_disable(struct drm_crtc *crtc)
2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp;
2897
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902 POSTING_READ(reg);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(0x7 << 16);
2907 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2908 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2909
2910 POSTING_READ(reg);
2911 udelay(100);
2912
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2914 if (HAS_PCH_IBX(dev)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2916 I915_WRITE(FDI_RX_CHICKEN(pipe),
2917 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2918 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2919 } else if (HAS_PCH_CPT(dev)) {
2920 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2921 }
0fc932b8
JB		 2922
2923 /* still set train pattern 1 */
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~FDI_LINK_TRAIN_NONE;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1;
2928 I915_WRITE(reg, temp);
2929
2930 reg = FDI_RX_CTL(pipe);
2931 temp = I915_READ(reg);
2932 if (HAS_PCH_CPT(dev)) {
2933 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2934 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2935 } else {
2936 temp &= ~FDI_LINK_TRAIN_NONE;
2937 temp |= FDI_LINK_TRAIN_PATTERN_1;
2938 }
2939 /* BPC in FDI rx is consistent with that in PIPECONF */
2940 temp &= ~(0x07 << 16);
2941 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2942 I915_WRITE(reg, temp);
2943
2944 POSTING_READ(reg);
2945 udelay(100);
2946}
2947
5bb61643
CW		 2948static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2949{
2950 struct drm_device *dev = crtc->dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 unsigned long flags;
2953 bool pending;
2954
2955 if (atomic_read(&dev_priv->mm.wedged))
2956 return false;
2957
2958 spin_lock_irqsave(&dev->event_lock, flags);
2959 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2960 spin_unlock_irqrestore(&dev->event_lock, flags);
2961
2962 return pending;
2963}
2964
e6c3a2a6
CW		 2965static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2966{
0f91128d 2967 struct drm_device *dev = crtc->dev;
5bb61643 2968 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2969
2970 if (crtc->fb == NULL)
2971 return;
2972
5bb61643
CW		 2973 wait_event(dev_priv->pending_flip_queue,
2974 !intel_crtc_has_pending_flip(crtc));
2975
0f91128d
CW		 2976 mutex_lock(&dev->struct_mutex);
2977 intel_finish_fb(crtc->fb);
2978 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2979}
2980
fc316cbe 2981static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2982{
2983 struct drm_device *dev = crtc->dev;
228d3e36 2984 struct intel_encoder *intel_encoder;
040484af
JB		 2985
2986 /*
2987 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2988 * must be driven by its own crtc; no sharing is possible.
2989 */
228d3e36 2990 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2991 switch (intel_encoder->type) {
040484af 2992 case INTEL_OUTPUT_EDP:
228d3e36 2993 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2994 return false;
2995 continue;
2996 }
2997 }
2998
2999 return true;
3000}
3001
fc316cbe
PZ		 3002static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3003{
3004 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3005}
3006
e615efe4
ED		 3007/* Program iCLKIP clock to the desired frequency */
3008static void lpt_program_iclkip(struct drm_crtc *crtc)
3009{
3010 struct drm_device *dev = crtc->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3013 u32 temp;
3014
3015 /* It is necessary to ungate the pixclk gate prior to programming
3016 * the divisors, and gate it back when it is done.
3017 */
3018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3019
3020 /* Disable SSCCTL */
3021 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3022 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3023 SBI_SSCCTL_DISABLE);
3024
3025 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3026 if (crtc->mode.clock == 20000) {
3027 auxdiv = 1;
3028 divsel = 0x41;
3029 phaseinc = 0x20;
3030 } else {
3031 /* The iCLK virtual clock root frequency is in MHz,
3032 * but the crtc->mode.clock in in KHz. To get the divisors,
3033 * it is necessary to divide one by another, so we
3034 * convert the virtual clock precision to KHz here for higher
3035 * precision.
3036 */
3037 u32 iclk_virtual_root_freq = 172800 * 1000;
3038 u32 iclk_pi_range = 64;
3039 u32 desired_divisor, msb_divisor_value, pi_value;
3040
3041 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3042 msb_divisor_value = desired_divisor / iclk_pi_range;
3043 pi_value = desired_divisor % iclk_pi_range;
3044
3045 auxdiv = 0;
3046 divsel = msb_divisor_value - 2;
3047 phaseinc = pi_value;
3048 }
3049
3050 /* This should not happen with any sane values */
3051 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3052 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3053 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3054 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3055
3056 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3057 crtc->mode.clock,
3058 auxdiv,
3059 divsel,
3060 phasedir,
3061 phaseinc);
3062
3063 /* Program SSCDIVINTPHASE6 */
3064 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3065 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3066 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3067 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3068 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3069 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3070 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3071
3072 intel_sbi_write(dev_priv,
3073 SBI_SSCDIVINTPHASE6,
3074 temp);
3075
3076 /* Program SSCAUXDIV */
3077 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3078 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3080 intel_sbi_write(dev_priv,
3081 SBI_SSCAUXDIV6,
3082 temp);
3083
3084
3085 /* Enable modulator and associated divider */
3086 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3087 temp &= ~SBI_SSCCTL_DISABLE;
3088 intel_sbi_write(dev_priv,
3089 SBI_SSCCTL6,
3090 temp);
3091
3092 /* Wait for initialization time */
3093 udelay(24);
3094
3095 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3096}
3097
f67a559d
JB		 3098/*
3099 * Enable PCH resources required for PCH ports:
3100 * - PCH PLLs
3101 * - FDI training & RX/TX
3102 * - update transcoder timings
3103 * - DP transcoding bits
3104 * - transcoder
3105 */
3106static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3107{
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3111 int pipe = intel_crtc->pipe;
ee7b9f93 3112 u32 reg, temp;
2c07245f 3113
e7e164db
CW		 3114 assert_transcoder_disabled(dev_priv, pipe);
3115
cd986abb
DV		 3116 /* Write the TU size bits before fdi link training, so that error
3117 * detection works. */
3118 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3119 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3120
c98e9dcf 3121 /* For PCH output, training FDI link */
674cf967 3122 dev_priv->display.fdi_link_train(crtc);
2c07245f 3123
572deb37
DV		 3124 /* XXX: pch pll's can be enabled any time before we enable the PCH
3125 * transcoder, and we actually should do this to not upset any PCH
3126 * transcoder that already use the clock when we share it.
3127 *
3128 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3129 * unconditionally resets the pll - we need that to have the right LVDS
3130 * enable sequence. */
b6b4e185 3131 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3132
303b81e0 3133 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3134 u32 sel;
4b645f14 3135
c98e9dcf 3136 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3137 switch (pipe) {
3138 default:
3139 case 0:
3140 temp |= TRANSA_DPLL_ENABLE;
3141 sel = TRANSA_DPLLB_SEL;
3142 break;
3143 case 1:
3144 temp |= TRANSB_DPLL_ENABLE;
3145 sel = TRANSB_DPLLB_SEL;
3146 break;
3147 case 2:
3148 temp |= TRANSC_DPLL_ENABLE;
3149 sel = TRANSC_DPLLB_SEL;
3150 break;
d64311ab 3151 }
ee7b9f93
JB		 3152 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3153 temp |= sel;
3154 else
3155 temp &= ~sel;
c98e9dcf 3156 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3157 }
5eddb70b 3158
d9b6cb56
JB		 3159 /* set transcoder timing, panel must allow it */
3160 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3161 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3162 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3163 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3164
5eddb70b
CW		 3165 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3166 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3167 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3168 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3169
303b81e0 3170 intel_fdi_normal_train(crtc);
5e84e1a4 3171
c98e9dcf
JB		 3172 /* For PCH DP, enable TRANS_DP_CTL */
3173 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3174 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3175 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3176 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3177 reg = TRANS_DP_CTL(pipe);
3178 temp = I915_READ(reg);
3179 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3180 TRANS_DP_SYNC_MASK |
3181 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3182 temp |= (TRANS_DP_OUTPUT_ENABLE |
3183 TRANS_DP_ENH_FRAMING);
9325c9f0 3184 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3185
3186 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3187 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3188 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3189 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3190
3191 switch (intel_trans_dp_port_sel(crtc)) {
3192 case PCH_DP_B:
5eddb70b 3193 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3194 break;
3195 case PCH_DP_C:
5eddb70b 3196 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3197 break;
3198 case PCH_DP_D:
5eddb70b 3199 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3200 break;
3201 default:
e95d41e1 3202 BUG();
32f9d658 3203 }
2c07245f 3204
5eddb70b 3205 I915_WRITE(reg, temp);
6be4a607 3206 }
b52eb4dc 3207
b8a4f404 3208 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3209}
3210
1507e5bd
PZ		 3211static void lpt_pch_enable(struct drm_crtc *crtc)
3212{
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 int pipe = intel_crtc->pipe;
daed2dbb 3217 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3218
daed2dbb 3219 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd
PZ		 3220
3221 /* Write the TU size bits before fdi link training, so that error
3222 * detection works. */
3223 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3224 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3225
3226 /* For PCH output, training FDI link */
3227 dev_priv->display.fdi_link_train(crtc);
3228
8c52b5e8 3229 lpt_program_iclkip(crtc);
1507e5bd 3230
0540e488 3231 /* Set transcoder timing. */
daed2dbb
PZ		 3232 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3233 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3234 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3235
daed2dbb
PZ		 3236 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3237 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3238 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3239 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3240
937bb610 3241 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
1507e5bd
PZ		 3242}
3243
ee7b9f93
JB		 3244static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3245{
3246 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3247
3248 if (pll == NULL)
3249 return;
3250
3251 if (pll->refcount == 0) {
3252 WARN(1, "bad PCH PLL refcount\n");
3253 return;
3254 }
3255
3256 --pll->refcount;
3257 intel_crtc->pch_pll = NULL;
3258}
3259
3260static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3261{
3262 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3263 struct intel_pch_pll *pll;
3264 int i;
3265
3266 pll = intel_crtc->pch_pll;
3267 if (pll) {
3268 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3269 intel_crtc->base.base.id, pll->pll_reg);
3270 goto prepare;
3271 }
3272
98b6bd99
DV		 3273 if (HAS_PCH_IBX(dev_priv->dev)) {
3274 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3275 i = intel_crtc->pipe;
3276 pll = &dev_priv->pch_plls[i];
3277
3278 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3279 intel_crtc->base.base.id, pll->pll_reg);
3280
3281 goto found;
3282 }
3283
ee7b9f93
JB		 3284 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3285 pll = &dev_priv->pch_plls[i];
3286
3287 /* Only want to check enabled timings first */
3288 if (pll->refcount == 0)
3289 continue;
3290
3291 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3292 fp == I915_READ(pll->fp0_reg)) {
3293 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3294 intel_crtc->base.base.id,
3295 pll->pll_reg, pll->refcount, pll->active);
3296
3297 goto found;
3298 }
3299 }
3300
3301 /* Ok no matching timings, maybe there's a free one? */
3302 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3303 pll = &dev_priv->pch_plls[i];
3304 if (pll->refcount == 0) {
3305 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3306 intel_crtc->base.base.id, pll->pll_reg);
3307 goto found;
3308 }
3309 }
3310
3311 return NULL;
3312
3313found:
3314 intel_crtc->pch_pll = pll;
3315 pll->refcount++;
3316 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3317prepare: /* separate function? */
3318 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3319
e04c7350
CW		 3320 /* Wait for the clocks to stabilize before rewriting the regs */
3321 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3322 POSTING_READ(pll->pll_reg);
3323 udelay(150);
e04c7350
CW		 3324
3325 I915_WRITE(pll->fp0_reg, fp);
3326 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3327 pll->on = false;
3328 return pll;
3329}
3330
d4270e57
JB		 3331void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3332{
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3335 u32 temp;
3336
3337 temp = I915_READ(dslreg);
3338 udelay(500);
3339 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3340 /* Without this, mode sets may fail silently on FDI */
3341 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3342 udelay(250);
3343 I915_WRITE(tc2reg, 0);
3344 if (wait_for(I915_READ(dslreg) != temp, 5))
3345 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3346 }
3347}
3348
f67a559d
JB		 3349static void ironlake_crtc_enable(struct drm_crtc *crtc)
3350{
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3354 struct intel_encoder *encoder;
f67a559d
JB		 3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
3357 u32 temp;
3358 bool is_pch_port;
3359
08a48469
DV		 3360 WARN_ON(!crtc->enabled);
3361
f67a559d
JB		 3362 if (intel_crtc->active)
3363 return;
3364
3365 intel_crtc->active = true;
3366 intel_update_watermarks(dev);
3367
3368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3369 temp = I915_READ(PCH_LVDS);
3370 if ((temp & LVDS_PORT_EN) == 0)
3371 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3372 }
3373
fc316cbe 3374 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3375
46b6f814 3376 if (is_pch_port) {
fff367c7
DV		 3377 /* Note: FDI PLL enabling _must_ be done before we enable the
3378 * cpu pipes, hence this is separate from all the other fdi/pch
3379 * enabling. */
88cefb6c 3380 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3381 } else {
3382 assert_fdi_tx_disabled(dev_priv, pipe);
3383 assert_fdi_rx_disabled(dev_priv, pipe);
3384 }
f67a559d 3385
bf49ec8c
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 if (encoder->pre_enable)
3388 encoder->pre_enable(encoder);
3389
f67a559d
JB		 3390 /* Enable panel fitting for LVDS */
3391 if (dev_priv->pch_pf_size &&
3392 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3393 /* Force use of hard-coded filter coefficients
3394 * as some pre-programmed values are broken,
3395 * e.g. x201.
3396 */
9db4a9c7
JB		 3397 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3398 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3400 }
3401
9c54c0dd
JB		 3402 /*
3403 * On ILK+ LUT must be loaded before the pipe is running but with
3404 * clocks enabled
3405 */
3406 intel_crtc_load_lut(crtc);
3407
f67a559d
JB		 3408 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3409 intel_enable_plane(dev_priv, plane, pipe);
3410
3411 if (is_pch_port)
3412 ironlake_pch_enable(crtc);
c98e9dcf 3413
d1ebd816 3414 mutex_lock(&dev->struct_mutex);
bed4a673 3415 intel_update_fbc(dev);
d1ebd816
BW		 3416 mutex_unlock(&dev->struct_mutex);
3417
6b383a7f 3418 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3419
fa5c73b1
DV		 3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 encoder->enable(encoder);
61b77ddd
DV		 3422
3423 if (HAS_PCH_CPT(dev))
3424 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3425
3426 /*
3427 * There seems to be a race in PCH platform hw (at least on some
3428 * outputs) where an enabled pipe still completes any pageflip right
3429 * away (as if the pipe is off) instead of waiting for vblank. As soon
3430 * as the first vblank happend, everything works as expected. Hence just
3431 * wait for one vblank before returning to avoid strange things
3432 * happening.
3433 */
3434 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3435}
3436
4f771f10
PZ		 3437static void haswell_crtc_enable(struct drm_crtc *crtc)
3438{
3439 struct drm_device *dev = crtc->dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442 struct intel_encoder *encoder;
3443 int pipe = intel_crtc->pipe;
3444 int plane = intel_crtc->plane;
4f771f10
PZ		 3445 bool is_pch_port;
3446
3447 WARN_ON(!crtc->enabled);
3448
3449 if (intel_crtc->active)
3450 return;
3451
3452 intel_crtc->active = true;
3453 intel_update_watermarks(dev);
3454
fc316cbe 3455 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3456
83616634 3457 if (is_pch_port)
4f771f10 3458 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3459
3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 if (encoder->pre_enable)
3462 encoder->pre_enable(encoder);
3463
1f544388 3464 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3465
1f544388
PZ		 3466 /* Enable panel fitting for eDP */
3467 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3468 /* Force use of hard-coded filter coefficients
3469 * as some pre-programmed values are broken,
3470 * e.g. x201.
3471 */
3472 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3473 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3474 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3475 }
3476
3477 /*
3478 * On ILK+ LUT must be loaded before the pipe is running but with
3479 * clocks enabled
3480 */
3481 intel_crtc_load_lut(crtc);
3482
1f544388
PZ		 3483 intel_ddi_set_pipe_settings(crtc);
3484 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3485
3486 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3487 intel_enable_plane(dev_priv, plane, pipe);
3488
3489 if (is_pch_port)
1507e5bd 3490 lpt_pch_enable(crtc);
4f771f10
PZ		 3491
3492 mutex_lock(&dev->struct_mutex);
3493 intel_update_fbc(dev);
3494 mutex_unlock(&dev->struct_mutex);
3495
3496 intel_crtc_update_cursor(crtc, true);
3497
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->enable(encoder);
3500
4f771f10
PZ		 3501 /*
3502 * There seems to be a race in PCH platform hw (at least on some
3503 * outputs) where an enabled pipe still completes any pageflip right
3504 * away (as if the pipe is off) instead of waiting for vblank. As soon
3505 * as the first vblank happend, everything works as expected. Hence just
3506 * wait for one vblank before returning to avoid strange things
3507 * happening.
3508 */
3509 intel_wait_for_vblank(dev, intel_crtc->pipe);
3510}
3511
6be4a607
JB		 3512static void ironlake_crtc_disable(struct drm_crtc *crtc)
3513{
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3517 struct intel_encoder *encoder;
6be4a607
JB		 3518 int pipe = intel_crtc->pipe;
3519 int plane = intel_crtc->plane;
5eddb70b 3520 u32 reg, temp;
b52eb4dc 3521
ef9c3aee 3522
f7abfe8b
CW		 3523 if (!intel_crtc->active)
3524 return;
3525
ea9d758d
DV		 3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 encoder->disable(encoder);
3528
e6c3a2a6 3529 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3530 drm_vblank_off(dev, pipe);
6b383a7f 3531 intel_crtc_update_cursor(crtc, false);
5eddb70b 3532
b24e7179 3533 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3534
973d04f9
CW		 3535 if (dev_priv->cfb_plane == plane)
3536 intel_disable_fbc(dev);
2c07245f 3537
b24e7179 3538 intel_disable_pipe(dev_priv, pipe);
32f9d658 3539
6be4a607 3540 /* Disable PF */
9db4a9c7
JB		 3541 I915_WRITE(PF_CTL(pipe), 0);
3542 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3543
bf49ec8c
DV		 3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
0fc932b8 3548 ironlake_fdi_disable(crtc);
2c07245f 3549
b8a4f404 3550 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3551
6be4a607
JB		 3552 if (HAS_PCH_CPT(dev)) {
3553 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3554 reg = TRANS_DP_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3557 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3558 I915_WRITE(reg, temp);
6be4a607
JB		 3559
3560 /* disable DPLL_SEL */
3561 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3562 switch (pipe) {
3563 case 0:
d64311ab 3564 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3565 break;
3566 case 1:
6be4a607 3567 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3568 break;
3569 case 2:
4b645f14 3570 /* C shares PLL A or B */
d64311ab 3571 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3572 break;
3573 default:
3574 BUG(); /* wtf */
3575 }
6be4a607 3576 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3577 }
e3421a18 3578
6be4a607 3579 /* disable PCH DPLL */
ee7b9f93 3580 intel_disable_pch_pll(intel_crtc);
8db9d77b 3581
88cefb6c 3582 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3583
f7abfe8b 3584 intel_crtc->active = false;
6b383a7f 3585 intel_update_watermarks(dev);
d1ebd816
BW		 3586
3587 mutex_lock(&dev->struct_mutex);
6b383a7f 3588 intel_update_fbc(dev);
d1ebd816 3589 mutex_unlock(&dev->struct_mutex);
6be4a607 3590}
1b3c7a47 3591
4f771f10
PZ		 3592static void haswell_crtc_disable(struct drm_crtc *crtc)
3593{
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 struct intel_encoder *encoder;
3598 int pipe = intel_crtc->pipe;
3599 int plane = intel_crtc->plane;
ad80a810 3600 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3601 bool is_pch_port;
4f771f10
PZ		 3602
3603 if (!intel_crtc->active)
3604 return;
3605
83616634
PZ		 3606 is_pch_port = haswell_crtc_driving_pch(crtc);
3607
4f771f10
PZ		 3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->disable(encoder);
3610
3611 intel_crtc_wait_for_pending_flips(crtc);
3612 drm_vblank_off(dev, pipe);
3613 intel_crtc_update_cursor(crtc, false);
3614
3615 intel_disable_plane(dev_priv, plane, pipe);
3616
3617 if (dev_priv->cfb_plane == plane)
3618 intel_disable_fbc(dev);
3619
3620 intel_disable_pipe(dev_priv, pipe);
3621
ad80a810 3622 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3623
3624 /* Disable PF */
3625 I915_WRITE(PF_CTL(pipe), 0);
3626 I915_WRITE(PF_WIN_SZ(pipe), 0);
3627
1f544388 3628 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3629
3630 for_each_encoder_on_crtc(dev, crtc, encoder)
3631 if (encoder->post_disable)
3632 encoder->post_disable(encoder);
3633
83616634
PZ		 3634 if (is_pch_port) {
3635 ironlake_fdi_disable(crtc);
8fb033d7 3636 lpt_disable_pch_transcoder(dev_priv, pipe);
83616634
PZ		 3637 intel_disable_pch_pll(intel_crtc);
3638 ironlake_fdi_pll_disable(intel_crtc);
3639 }
4f771f10
PZ		 3640
3641 intel_crtc->active = false;
3642 intel_update_watermarks(dev);
3643
3644 mutex_lock(&dev->struct_mutex);
3645 intel_update_fbc(dev);
3646 mutex_unlock(&dev->struct_mutex);
3647}
3648
ee7b9f93
JB		 3649static void ironlake_crtc_off(struct drm_crtc *crtc)
3650{
3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652 intel_put_pch_pll(intel_crtc);
3653}
3654
6441ab5f
PZ		 3655static void haswell_crtc_off(struct drm_crtc *crtc)
3656{
a5c961d1
PZ		 3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658
3659 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3660 * start using it. */
3661 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3662
6441ab5f
PZ		 3663 intel_ddi_put_crtc_pll(crtc);
3664}
3665
02e792fb
DV		 3666static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3667{
02e792fb 3668 if (!enable && intel_crtc->overlay) {
23f09ce3 3669 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3670 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3671
23f09ce3 3672 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3673 dev_priv->mm.interruptible = false;
3674 (void) intel_overlay_switch_off(intel_crtc->overlay);
3675 dev_priv->mm.interruptible = true;
23f09ce3 3676 mutex_unlock(&dev->struct_mutex);
02e792fb 3677 }
02e792fb 3678
5dcdbcb0
CW		 3679 /* Let userspace switch the overlay on again. In most cases userspace
3680 * has to recompute where to put it anyway.
3681 */
02e792fb
DV		 3682}
3683
0b8765c6 3684static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3685{
3686 struct drm_device *dev = crtc->dev;
79e53945
JB		 3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3689 struct intel_encoder *encoder;
79e53945 3690 int pipe = intel_crtc->pipe;
80824003 3691 int plane = intel_crtc->plane;
79e53945 3692
08a48469
DV		 3693 WARN_ON(!crtc->enabled);
3694
f7abfe8b
CW		 3695 if (intel_crtc->active)
3696 return;
3697
3698 intel_crtc->active = true;
6b383a7f
CW		 3699 intel_update_watermarks(dev);
3700
63d7bbe9 3701 intel_enable_pll(dev_priv, pipe);
040484af 3702 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3703 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3704
0b8765c6 3705 intel_crtc_load_lut(crtc);
bed4a673 3706 intel_update_fbc(dev);
79e53945 3707
0b8765c6
JB		 3708 /* Give the overlay scaler a chance to enable if it's on this pipe */
3709 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3710 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3711
fa5c73b1
DV		 3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->enable(encoder);
0b8765c6 3714}
79e53945 3715
0b8765c6
JB		 3716static void i9xx_crtc_disable(struct drm_crtc *crtc)
3717{
3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3721 struct intel_encoder *encoder;
0b8765c6
JB		 3722 int pipe = intel_crtc->pipe;
3723 int plane = intel_crtc->plane;
b690e96c 3724
ef9c3aee 3725
f7abfe8b
CW		 3726 if (!intel_crtc->active)
3727 return;
3728
ea9d758d
DV		 3729 for_each_encoder_on_crtc(dev, crtc, encoder)
3730 encoder->disable(encoder);
3731
0b8765c6 3732 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3733 intel_crtc_wait_for_pending_flips(crtc);
3734 drm_vblank_off(dev, pipe);
0b8765c6 3735 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3736 intel_crtc_update_cursor(crtc, false);
0b8765c6 3737
973d04f9
CW		 3738 if (dev_priv->cfb_plane == plane)
3739 intel_disable_fbc(dev);
79e53945 3740
b24e7179 3741 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3742 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3743 intel_disable_pll(dev_priv, pipe);
0b8765c6 3744
f7abfe8b 3745 intel_crtc->active = false;
6b383a7f
CW		 3746 intel_update_fbc(dev);
3747 intel_update_watermarks(dev);
0b8765c6
JB		 3748}
3749
ee7b9f93
JB		 3750static void i9xx_crtc_off(struct drm_crtc *crtc)
3751{
3752}
3753
976f8a20
DV		 3754static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3755 bool enabled)
2c07245f
ZW		 3756{
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_master_private *master_priv;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760 int pipe = intel_crtc->pipe;
79e53945
JB		 3761
3762 if (!dev->primary->master)
3763 return;
3764
3765 master_priv = dev->primary->master->driver_priv;
3766 if (!master_priv->sarea_priv)
3767 return;
3768
79e53945
JB		 3769 switch (pipe) {
3770 case 0:
3771 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3772 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3773 break;
3774 case 1:
3775 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3776 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3777 break;
3778 default:
9db4a9c7 3779 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3780 break;
3781 }
79e53945
JB		 3782}
3783
976f8a20
DV		 3784/**
3785 * Sets the power management mode of the pipe and plane.
3786 */
3787void intel_crtc_update_dpms(struct drm_crtc *crtc)
3788{
3789 struct drm_device *dev = crtc->dev;
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 struct intel_encoder *intel_encoder;
3792 bool enable = false;
3793
3794 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3795 enable |= intel_encoder->connectors_active;
3796
3797 if (enable)
3798 dev_priv->display.crtc_enable(crtc);
3799 else
3800 dev_priv->display.crtc_disable(crtc);
3801
3802 intel_crtc_update_sarea(crtc, enable);
3803}
3804
3805static void intel_crtc_noop(struct drm_crtc *crtc)
3806{
3807}
3808
cdd59983
CW		 3809static void intel_crtc_disable(struct drm_crtc *crtc)
3810{
cdd59983 3811 struct drm_device *dev = crtc->dev;
976f8a20 3812 struct drm_connector *connector;
ee7b9f93 3813 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3814
976f8a20
DV		 3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc->enabled);
3817
3818 dev_priv->display.crtc_disable(crtc);
3819 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3820 dev_priv->display.off(crtc);
3821
931872fc
CW		 3822 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3823 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3824
3825 if (crtc->fb) {
3826 mutex_lock(&dev->struct_mutex);
1690e1eb 3827 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3828 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3829 crtc->fb = NULL;
3830 }
3831
3832 /* Update computed state. */
3833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3834 if (!connector->encoder || !connector->encoder->crtc)
3835 continue;
3836
3837 if (connector->encoder->crtc != crtc)
3838 continue;
3839
3840 connector->dpms = DRM_MODE_DPMS_OFF;
3841 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3842 }
3843}
3844
a261b246 3845void intel_modeset_disable(struct drm_device *dev)
79e53945 3846{
a261b246
DV		 3847 struct drm_crtc *crtc;
3848
3849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3850 if (crtc->enabled)
3851 intel_crtc_disable(crtc);
3852 }
79e53945
JB		 3853}
3854
1f703855 3855void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3856{
7e7d76c3
JB		 3857}
3858
ea5b213a 3859void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3860{
4ef69c7a 3861 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3862
ea5b213a
CW		 3863 drm_encoder_cleanup(encoder);
3864 kfree(intel_encoder);
7e7d76c3
JB		 3865}
3866
5ab432ef
DV		 3867/* Simple dpms helper for encodres with just one connector, no cloning and only
3868 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3869 * state of the entire output pipe. */
3870void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3871{
5ab432ef
DV		 3872 if (mode == DRM_MODE_DPMS_ON) {
3873 encoder->connectors_active = true;
3874
b2cabb0e 3875 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3876 } else {
3877 encoder->connectors_active = false;
3878
b2cabb0e 3879 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3880 }
79e53945
JB		 3881}
3882
0a91ca29
DV		 3883/* Cross check the actual hw state with our own modeset state tracking (and it's
3884 * internal consistency). */
b980514c 3885static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3886{
0a91ca29
DV		 3887 if (connector->get_hw_state(connector)) {
3888 struct intel_encoder *encoder = connector->encoder;
3889 struct drm_crtc *crtc;
3890 bool encoder_enabled;
3891 enum pipe pipe;
3892
3893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3894 connector->base.base.id,
3895 drm_get_connector_name(&connector->base));
3896
3897 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3898 "wrong connector dpms state\n");
3899 WARN(connector->base.encoder != &encoder->base,
3900 "active connector not linked to encoder\n");
3901 WARN(!encoder->connectors_active,
3902 "encoder->connectors_active not set\n");
3903
3904 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3905 WARN(!encoder_enabled, "encoder not enabled\n");
3906 if (WARN_ON(!encoder->base.crtc))
3907 return;
3908
3909 crtc = encoder->base.crtc;
3910
3911 WARN(!crtc->enabled, "crtc not enabled\n");
3912 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3913 WARN(pipe != to_intel_crtc(crtc)->pipe,
3914 "encoder active on the wrong pipe\n");
3915 }
79e53945
JB		 3916}
3917
5ab432ef
DV		 3918/* Even simpler default implementation, if there's really no special case to
3919 * consider. */
3920void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3921{
5ab432ef 3922 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3923
5ab432ef
DV		 3924 /* All the simple cases only support two dpms states. */
3925 if (mode != DRM_MODE_DPMS_ON)
3926 mode = DRM_MODE_DPMS_OFF;
d4270e57 3927
5ab432ef
DV		 3928 if (mode == connector->dpms)
3929 return;
3930
3931 connector->dpms = mode;
3932
3933 /* Only need to change hw state when actually enabled */
3934 if (encoder->base.crtc)
3935 intel_encoder_dpms(encoder, mode);
3936 else
8af6cf88 3937 WARN_ON(encoder->connectors_active != false);
0a91ca29 3938
b980514c 3939 intel_modeset_check_state(connector->dev);
79e53945
JB		 3940}
3941
f0947c37
DV		 3942/* Simple connector->get_hw_state implementation for encoders that support only
3943 * one connector and no cloning and hence the encoder state determines the state
3944 * of the connector. */
3945bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3946{
24929352 3947 enum pipe pipe = 0;
f0947c37 3948 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3949
f0947c37 3950 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3951}
3952
79e53945 3953static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3954 const struct drm_display_mode *mode,
79e53945
JB		 3955 struct drm_display_mode *adjusted_mode)
3956{
2c07245f 3957 struct drm_device *dev = crtc->dev;
89749350 3958
bad720ff 3959 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3960 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3961 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3962 return false;
2c07245f 3963 }
89749350 3964
f9bef081
DV		 3965 /* All interlaced capable intel hw wants timings in frames. Note though
3966 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3967 * timings, so we need to be careful not to clobber these.*/
3968 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3969 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3970
44f46b42
CW		 3971 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3972 * with a hsync front porch of 0.
3973 */
3974 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3975 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3976 return false;
3977
79e53945
JB		 3978 return true;
3979}
3980
25eb05fc
JB		 3981static int valleyview_get_display_clock_speed(struct drm_device *dev)
3982{
3983 return 400000; /* FIXME */
3984}
3985
e70236a8
JB		 3986static int i945_get_display_clock_speed(struct drm_device *dev)
3987{
3988 return 400000;
3989}
79e53945 3990
e70236a8 3991static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3992{
e70236a8
JB		 3993 return 333000;
3994}
79e53945 3995
e70236a8
JB		 3996static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3997{
3998 return 200000;
3999}
79e53945 4000
e70236a8
JB		 4001static int i915gm_get_display_clock_speed(struct drm_device *dev)
4002{
4003 u16 gcfgc = 0;
79e53945 4004
e70236a8
JB		 4005 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4006
4007 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4008 return 133000;
4009 else {
4010 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4011 case GC_DISPLAY_CLOCK_333_MHZ:
4012 return 333000;
4013 default:
4014 case GC_DISPLAY_CLOCK_190_200_MHZ:
4015 return 190000;
79e53945 4016 }
e70236a8
JB		 4017 }
4018}
4019
4020static int i865_get_display_clock_speed(struct drm_device *dev)
4021{
4022 return 266000;
4023}
4024
4025static int i855_get_display_clock_speed(struct drm_device *dev)
4026{
4027 u16 hpllcc = 0;
4028 /* Assume that the hardware is in the high speed state. This
4029 * should be the default.
4030 */
4031 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4032 case GC_CLOCK_133_200:
4033 case GC_CLOCK_100_200:
4034 return 200000;
4035 case GC_CLOCK_166_250:
4036 return 250000;
4037 case GC_CLOCK_100_133:
79e53945 4038 return 133000;
e70236a8 4039 }
79e53945 4040
e70236a8
JB		 4041 /* Shouldn't happen */
4042 return 0;
4043}
79e53945 4044
e70236a8
JB		 4045static int i830_get_display_clock_speed(struct drm_device *dev)
4046{
4047 return 133000;
79e53945
JB		 4048}
4049
2c07245f
ZW		 4050struct fdi_m_n {
4051 u32 tu;
4052 u32 gmch_m;
4053 u32 gmch_n;
4054 u32 link_m;
4055 u32 link_n;
4056};
4057
4058static void
4059fdi_reduce_ratio(u32 *num, u32 *den)
4060{
4061 while (*num > 0xffffff || *den > 0xffffff) {
4062 *num >>= 1;
4063 *den >>= 1;
4064 }
4065}
4066
2c07245f 4067static void
f2b115e6
AJ		 4068ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4069 int link_clock, struct fdi_m_n *m_n)
2c07245f 4070{
2c07245f
ZW		 4071 m_n->tu = 64; /* default size */
4072
22ed1113
CW		 4073 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4074 m_n->gmch_m = bits_per_pixel * pixel_clock;
4075 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4076 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4077
22ed1113
CW		 4078 m_n->link_m = pixel_clock;
4079 m_n->link_n = link_clock;
2c07245f
ZW		 4080 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4081}
4082
a7615030
CW		 4083static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4084{
72bbe58c
KP		 4085 if (i915_panel_use_ssc >= 0)
4086 return i915_panel_use_ssc != 0;
4087 return dev_priv->lvds_use_ssc
435793df 4088 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4089}
4090
5a354204
JB		 4091/**
4092 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4093 * @crtc: CRTC structure
3b5c78a3 4094 * @mode: requested mode
5a354204
JB		 4095 *
4096 * A pipe may be connected to one or more outputs. Based on the depth of the
4097 * attached framebuffer, choose a good color depth to use on the pipe.
4098 *
4099 * If possible, match the pipe depth to the fb depth. In some cases, this
4100 * isn't ideal, because the connected output supports a lesser or restricted
4101 * set of depths. Resolve that here:
4102 * LVDS typically supports only 6bpc, so clamp down in that case
4103 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4104 * Displays may support a restricted set as well, check EDID and clamp as
4105 * appropriate.
3b5c78a3 4106 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4107 *
4108 * RETURNS:
4109 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4110 * true if they don't match).
4111 */
4112static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4113 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4114 unsigned int *pipe_bpp,
4115 struct drm_display_mode *mode)
5a354204
JB		 4116{
4117 struct drm_device *dev = crtc->dev;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4119 struct drm_connector *connector;
6c2b7c12 4120 struct intel_encoder *intel_encoder;
5a354204
JB		 4121 unsigned int display_bpc = UINT_MAX, bpc;
4122
4123 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4124 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4125
4126 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4127 unsigned int lvds_bpc;
4128
4129 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4130 LVDS_A3_POWER_UP)
4131 lvds_bpc = 8;
4132 else
4133 lvds_bpc = 6;
4134
4135 if (lvds_bpc < display_bpc) {
82820490 4136 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4137 display_bpc = lvds_bpc;
4138 }
4139 continue;
4140 }
4141
5a354204
JB		 4142 /* Not one of the known troublemakers, check the EDID */
4143 list_for_each_entry(connector, &dev->mode_config.connector_list,
4144 head) {
6c2b7c12 4145 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4146 continue;
4147
62ac41a6
JB		 4148 /* Don't use an invalid EDID bpc value */
4149 if (connector->display_info.bpc &&
4150 connector->display_info.bpc < display_bpc) {
82820490 4151 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4152 display_bpc = connector->display_info.bpc;
4153 }
4154 }
4155
4156 /*
4157 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4158 * through, clamp it down. (Note: >12bpc will be caught below.)
4159 */
4160 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4161 if (display_bpc > 8 && display_bpc < 12) {
82820490 4162 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4163 display_bpc = 12;
4164 } else {
82820490 4165 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4166 display_bpc = 8;
4167 }
4168 }
4169 }
4170
3b5c78a3
AJ		 4171 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4172 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4173 display_bpc = 6;
4174 }
4175
5a354204
JB		 4176 /*
4177 * We could just drive the pipe at the highest bpc all the time and
4178 * enable dithering as needed, but that costs bandwidth. So choose
4179 * the minimum value that expresses the full color range of the fb but
4180 * also stays within the max display bpc discovered above.
4181 */
4182
94352cf9 4183 switch (fb->depth) {
5a354204
JB		 4184 case 8:
4185 bpc = 8; /* since we go through a colormap */
4186 break;
4187 case 15:
4188 case 16:
4189 bpc = 6; /* min is 18bpp */
4190 break;
4191 case 24:
578393cd 4192 bpc = 8;
5a354204
JB		 4193 break;
4194 case 30:
578393cd 4195 bpc = 10;
5a354204
JB		 4196 break;
4197 case 48:
578393cd 4198 bpc = 12;
5a354204
JB		 4199 break;
4200 default:
4201 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4202 bpc = min((unsigned int)8, display_bpc);
4203 break;
4204 }
4205
578393cd
KP		 4206 display_bpc = min(display_bpc, bpc);
4207
82820490
AJ		 4208 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4209 bpc, display_bpc);
5a354204 4210
578393cd 4211 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4212
4213 return display_bpc != bpc;
4214}
4215
a0c4da24
JB		 4216static int vlv_get_refclk(struct drm_crtc *crtc)
4217{
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 int refclk = 27000; /* for DP & HDMI */
4221
4222 return 100000; /* only one validated so far */
4223
4224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4225 refclk = 96000;
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4227 if (intel_panel_use_ssc(dev_priv))
4228 refclk = 100000;
4229 else
4230 refclk = 96000;
4231 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4232 refclk = 100000;
4233 }
4234
4235 return refclk;
4236}
4237
c65d77d8
JB		 4238static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4239{
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 int refclk;
4243
a0c4da24
JB		 4244 if (IS_VALLEYVIEW(dev)) {
4245 refclk = vlv_get_refclk(crtc);
4246 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4247 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4248 refclk = dev_priv->lvds_ssc_freq * 1000;
4249 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4250 refclk / 1000);
4251 } else if (!IS_GEN2(dev)) {
4252 refclk = 96000;
4253 } else {
4254 refclk = 48000;
4255 }
4256
4257 return refclk;
4258}
4259
4260static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4261 intel_clock_t *clock)
4262{
4263 /* SDVO TV has fixed PLL values depend on its clock range,
4264 this mirrors vbios setting. */
4265 if (adjusted_mode->clock >= 100000
4266 && adjusted_mode->clock < 140500) {
4267 clock->p1 = 2;
4268 clock->p2 = 10;
4269 clock->n = 3;
4270 clock->m1 = 16;
4271 clock->m2 = 8;
4272 } else if (adjusted_mode->clock >= 140500
4273 && adjusted_mode->clock <= 200000) {
4274 clock->p1 = 1;
4275 clock->p2 = 10;
4276 clock->n = 6;
4277 clock->m1 = 12;
4278 clock->m2 = 8;
4279 }
4280}
4281
a7516a05
JB		 4282static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4283 intel_clock_t *clock,
4284 intel_clock_t *reduced_clock)
4285{
4286 struct drm_device *dev = crtc->dev;
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 int pipe = intel_crtc->pipe;
4290 u32 fp, fp2 = 0;
4291
4292 if (IS_PINEVIEW(dev)) {
4293 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4294 if (reduced_clock)
4295 fp2 = (1 << reduced_clock->n) << 16 |
4296 reduced_clock->m1 << 8 | reduced_clock->m2;
4297 } else {
4298 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4299 if (reduced_clock)
4300 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4301 reduced_clock->m2;
4302 }
4303
4304 I915_WRITE(FP0(pipe), fp);
4305
4306 intel_crtc->lowfreq_avail = false;
4307 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4308 reduced_clock && i915_powersave) {
4309 I915_WRITE(FP1(pipe), fp2);
4310 intel_crtc->lowfreq_avail = true;
4311 } else {
4312 I915_WRITE(FP1(pipe), fp);
4313 }
4314}
4315
93e537a1
DV		 4316static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4317 struct drm_display_mode *adjusted_mode)
4318{
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 int pipe = intel_crtc->pipe;
284d5df5 4323 u32 temp;
93e537a1
DV		 4324
4325 temp = I915_READ(LVDS);
4326 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4327 if (pipe == 1) {
4328 temp |= LVDS_PIPEB_SELECT;
4329 } else {
4330 temp &= ~LVDS_PIPEB_SELECT;
4331 }
4332 /* set the corresponsding LVDS_BORDER bit */
4333 temp |= dev_priv->lvds_border_bits;
4334 /* Set the B0-B3 data pairs corresponding to whether we're going to
4335 * set the DPLLs for dual-channel mode or not.
4336 */
4337 if (clock->p2 == 7)
4338 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4339 else
4340 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4341
4342 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4343 * appropriately here, but we need to look more thoroughly into how
4344 * panels behave in the two modes.
4345 */
4346 /* set the dithering flag on LVDS as needed */
4347 if (INTEL_INFO(dev)->gen >= 4) {
4348 if (dev_priv->lvds_dither)
4349 temp |= LVDS_ENABLE_DITHER;
4350 else
4351 temp &= ~LVDS_ENABLE_DITHER;
4352 }
284d5df5 4353 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4354 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4355 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4356 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4357 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4358 I915_WRITE(LVDS, temp);
4359}
4360
a0c4da24
JB		 4361static void vlv_update_pll(struct drm_crtc *crtc,
4362 struct drm_display_mode *mode,
4363 struct drm_display_mode *adjusted_mode,
4364 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4365 int num_connectors)
a0c4da24
JB		 4366{
4367 struct drm_device *dev = crtc->dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 int pipe = intel_crtc->pipe;
4371 u32 dpll, mdiv, pdiv;
4372 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4373 bool is_sdvo;
4374 u32 temp;
4375
4376 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4377 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4378
2a8f64ca
VP		 4379 dpll = DPLL_VGA_MODE_DIS;
4380 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4381 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4382 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4383
4384 I915_WRITE(DPLL(pipe), dpll);
4385 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4386
4387 bestn = clock->n;
4388 bestm1 = clock->m1;
4389 bestm2 = clock->m2;
4390 bestp1 = clock->p1;
4391 bestp2 = clock->p2;
4392
2a8f64ca
VP		 4393 /*
4394 * In Valleyview PLL and program lane counter registers are exposed
4395 * through DPIO interface
4396 */
a0c4da24
JB		 4397 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4398 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4399 mdiv |= ((bestn << DPIO_N_SHIFT));
4400 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4401 mdiv |= (1 << DPIO_K_SHIFT);
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4406
2a8f64ca 4407 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4408 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4409 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4410 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4411 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4412
2a8f64ca 4413 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4414
4415 dpll |= DPLL_VCO_ENABLE;
4416 I915_WRITE(DPLL(pipe), dpll);
4417 POSTING_READ(DPLL(pipe));
4418 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4419 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4420
2a8f64ca
VP		 4421 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4422
4423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4424 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4425
4426 I915_WRITE(DPLL(pipe), dpll);
4427
4428 /* Wait for the clocks to stabilize. */
4429 POSTING_READ(DPLL(pipe));
4430 udelay(150);
a0c4da24 4431
2a8f64ca
VP		 4432 temp = 0;
4433 if (is_sdvo) {
4434 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4435 if (temp > 1)
4436 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4437 else
4438 temp = 0;
a0c4da24 4439 }
2a8f64ca
VP		 4440 I915_WRITE(DPLL_MD(pipe), temp);
4441 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4442
2a8f64ca
VP		 4443 /* Now program lane control registers */
4444 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4445 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4446 {
4447 temp = 0x1000C4;
4448 if(pipe == 1)
4449 temp |= (1 << 21);
4450 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4451 }
4452 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4453 {
4454 temp = 0x1000C4;
4455 if(pipe == 1)
4456 temp |= (1 << 21);
4457 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4458 }
a0c4da24
JB		 4459}
4460
eb1cbe48
DV		 4461static void i9xx_update_pll(struct drm_crtc *crtc,
4462 struct drm_display_mode *mode,
4463 struct drm_display_mode *adjusted_mode,
4464 intel_clock_t *clock, intel_clock_t *reduced_clock,
4465 int num_connectors)
4466{
4467 struct drm_device *dev = crtc->dev;
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4470 int pipe = intel_crtc->pipe;
4471 u32 dpll;
4472 bool is_sdvo;
4473
2a8f64ca
VP		 4474 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4475
eb1cbe48
DV		 4476 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4477 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4478
4479 dpll = DPLL_VGA_MODE_DIS;
4480
4481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4482 dpll |= DPLLB_MODE_LVDS;
4483 else
4484 dpll |= DPLLB_MODE_DAC_SERIAL;
4485 if (is_sdvo) {
4486 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4487 if (pixel_multiplier > 1) {
4488 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4489 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4490 }
4491 dpll |= DPLL_DVO_HIGH_SPEED;
4492 }
4493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4494 dpll |= DPLL_DVO_HIGH_SPEED;
4495
4496 /* compute bitmask from p1 value */
4497 if (IS_PINEVIEW(dev))
4498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4499 else {
4500 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4501 if (IS_G4X(dev) && reduced_clock)
4502 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4503 }
4504 switch (clock->p2) {
4505 case 5:
4506 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4507 break;
4508 case 7:
4509 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4510 break;
4511 case 10:
4512 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4513 break;
4514 case 14:
4515 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4516 break;
4517 }
4518 if (INTEL_INFO(dev)->gen >= 4)
4519 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4520
4521 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4522 dpll |= PLL_REF_INPUT_TVCLKINBC;
4523 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4524 /* XXX: just matching BIOS for now */
4525 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4526 dpll |= 3;
4527 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4528 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4529 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4530 else
4531 dpll |= PLL_REF_INPUT_DREFCLK;
4532
4533 dpll |= DPLL_VCO_ENABLE;
4534 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4535 POSTING_READ(DPLL(pipe));
4536 udelay(150);
4537
4538 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4539 * This is an exception to the general rule that mode_set doesn't turn
4540 * things on.
4541 */
4542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4543 intel_update_lvds(crtc, clock, adjusted_mode);
4544
4545 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4546 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4547
4548 I915_WRITE(DPLL(pipe), dpll);
4549
4550 /* Wait for the clocks to stabilize. */
4551 POSTING_READ(DPLL(pipe));
4552 udelay(150);
4553
4554 if (INTEL_INFO(dev)->gen >= 4) {
4555 u32 temp = 0;
4556 if (is_sdvo) {
4557 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4558 if (temp > 1)
4559 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4560 else
4561 temp = 0;
4562 }
4563 I915_WRITE(DPLL_MD(pipe), temp);
4564 } else {
4565 /* The pixel multiplier can only be updated once the
4566 * DPLL is enabled and the clocks are stable.
4567 *
4568 * So write it again.
4569 */
4570 I915_WRITE(DPLL(pipe), dpll);
4571 }
4572}
4573
4574static void i8xx_update_pll(struct drm_crtc *crtc,
4575 struct drm_display_mode *adjusted_mode,
2a8f64ca 4576 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4577 int num_connectors)
4578{
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 int pipe = intel_crtc->pipe;
4583 u32 dpll;
4584
2a8f64ca
VP		 4585 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4586
eb1cbe48
DV		 4587 dpll = DPLL_VGA_MODE_DIS;
4588
4589 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 } else {
4592 if (clock->p1 == 2)
4593 dpll |= PLL_P1_DIVIDE_BY_TWO;
4594 else
4595 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596 if (clock->p2 == 4)
4597 dpll |= PLL_P2_DIVIDE_BY_4;
4598 }
4599
4600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4601 /* XXX: just matching BIOS for now */
4602 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4603 dpll |= 3;
4604 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4605 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4607 else
4608 dpll |= PLL_REF_INPUT_DREFCLK;
4609
4610 dpll |= DPLL_VCO_ENABLE;
4611 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4612 POSTING_READ(DPLL(pipe));
4613 udelay(150);
4614
eb1cbe48
DV		 4615 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4616 * This is an exception to the general rule that mode_set doesn't turn
4617 * things on.
4618 */
4619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4620 intel_update_lvds(crtc, clock, adjusted_mode);
4621
5b5896e4
DV		 4622 I915_WRITE(DPLL(pipe), dpll);
4623
4624 /* Wait for the clocks to stabilize. */
4625 POSTING_READ(DPLL(pipe));
4626 udelay(150);
4627
eb1cbe48
DV		 4628 /* The pixel multiplier can only be updated once the
4629 * DPLL is enabled and the clocks are stable.
4630 *
4631 * So write it again.
4632 */
4633 I915_WRITE(DPLL(pipe), dpll);
4634}
4635
b0e77b9c
PZ		 4636static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4637 struct drm_display_mode *mode,
4638 struct drm_display_mode *adjusted_mode)
4639{
4640 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4643 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4644 uint32_t vsyncshift;
4645
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
4648 adjusted_mode->crtc_vtotal -= 1;
4649 adjusted_mode->crtc_vblank_end -= 1;
4650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4652 } else {
4653 vsyncshift = 0;
4654 }
4655
4656 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4658
fe2b8f9d 4659 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4665 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
fe2b8f9d 4669 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_vdisplay - 1) |
4671 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_vblank_start - 1) |
4674 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4675 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
b5e508d4
PZ		 4679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682 * bits. */
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
b0e77b9c
PZ		 4687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4689 */
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692}
4693
f564048e
EA		 4694static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4695 struct drm_display_mode *mode,
4696 struct drm_display_mode *adjusted_mode,
4697 int x, int y,
94352cf9 4698 struct drm_framebuffer *fb)
79e53945
JB		 4699{
4700 struct drm_device *dev = crtc->dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int pipe = intel_crtc->pipe;
80824003 4704 int plane = intel_crtc->plane;
c751ce4f 4705 int refclk, num_connectors = 0;
652c393a 4706 intel_clock_t clock, reduced_clock;
b0e77b9c 4707 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4708 bool ok, has_reduced_clock = false, is_sdvo = false;
4709 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4710 struct intel_encoder *encoder;
d4906093 4711 const intel_limit_t *limit;
5c3b82e2 4712 int ret;
79e53945 4713
6c2b7c12 4714 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4715 switch (encoder->type) {
79e53945
JB		 4716 case INTEL_OUTPUT_LVDS:
4717 is_lvds = true;
4718 break;
4719 case INTEL_OUTPUT_SDVO:
7d57382e 4720 case INTEL_OUTPUT_HDMI:
79e53945 4721 is_sdvo = true;
5eddb70b 4722 if (encoder->needs_tv_clock)
e2f0ba97 4723 is_tv = true;
79e53945 4724 break;
79e53945
JB		 4725 case INTEL_OUTPUT_TVOUT:
4726 is_tv = true;
4727 break;
a4fc5ed6
KP		 4728 case INTEL_OUTPUT_DISPLAYPORT:
4729 is_dp = true;
4730 break;
79e53945 4731 }
43565a06 4732
c751ce4f 4733 num_connectors++;
79e53945
JB		 4734 }
4735
c65d77d8 4736 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4737
d4906093
ML		 4738 /*
4739 * Returns a set of divisors for the desired target clock with the given
4740 * refclk, or FALSE. The returned values represent the clock equation:
4741 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4742 */
1b894b59 4743 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4744 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4745 &clock);
79e53945
JB		 4746 if (!ok) {
4747 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4748 return -EINVAL;
79e53945
JB		 4749 }
4750
cda4b7d3 4751 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4752 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4753
ddc9003c 4754 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4755 /*
4756 * Ensure we match the reduced clock's P to the target clock.
4757 * If the clocks don't match, we can't switch the display clock
4758 * by using the FP0/FP1. In such case we will disable the LVDS
4759 * downclock feature.
4760 */
ddc9003c 4761 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4762 dev_priv->lvds_downclock,
4763 refclk,
cec2f356 4764 &clock,
5eddb70b 4765 &reduced_clock);
7026d4ac
ZW		 4766 }
4767
c65d77d8
JB		 4768 if (is_sdvo && is_tv)
4769 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4770
eb1cbe48 4771 if (IS_GEN2(dev))
2a8f64ca
VP		 4772 i8xx_update_pll(crtc, adjusted_mode, &clock,
4773 has_reduced_clock ? &reduced_clock : NULL,
4774 num_connectors);
a0c4da24 4775 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4776 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4777 has_reduced_clock ? &reduced_clock : NULL,
4778 num_connectors);
79e53945 4779 else
eb1cbe48
DV		 4780 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4781 has_reduced_clock ? &reduced_clock : NULL,
4782 num_connectors);
79e53945
JB		 4783
4784 /* setup pipeconf */
5eddb70b 4785 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4786
4787 /* Set up the display plane register */
4788 dspcntr = DISPPLANE_GAMMA_ENABLE;
4789
929c77fb
EA		 4790 if (pipe == 0)
4791 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4792 else
4793 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4794
a6c45cf0 4795 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4796 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4797 * core speed.
4798 *
4799 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4800 * pipe == 0 check?
4801 */
e70236a8
JB		 4802 if (mode->clock >
4803 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4804 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4805 else
5eddb70b 4806 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4807 }
4808
3b5c78a3
AJ		 4809 /* default to 8bpc */
4810 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4811 if (is_dp) {
0c96c65b 4812 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4813 pipeconf |= PIPECONF_BPP_6 |
4814 PIPECONF_DITHER_EN |
4815 PIPECONF_DITHER_TYPE_SP;
4816 }
4817 }
4818
19c03924
GB		 4819 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4820 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4821 pipeconf |= PIPECONF_BPP_6 |
4822 PIPECONF_ENABLE |
4823 I965_PIPECONF_ACTIVE;
4824 }
4825 }
4826
28c97730 4827 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4828 drm_mode_debug_printmodeline(mode);
4829
a7516a05
JB		 4830 if (HAS_PIPE_CXSR(dev)) {
4831 if (intel_crtc->lowfreq_avail) {
28c97730 4832 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4833 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4834 } else {
28c97730 4835 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4836 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4837 }
4838 }
4839
617cf884 4840 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4841 if (!IS_GEN2(dev) &&
b0e77b9c 4842 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4843 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4844 else
617cf884 4845 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4846
b0e77b9c 4847 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4848
4849 /* pipesrc and dspsize control the size that is scaled from,
4850 * which should always be the user's requested size.
79e53945 4851 */
929c77fb
EA		 4852 I915_WRITE(DSPSIZE(plane),
4853 ((mode->vdisplay - 1) << 16) |
4854 (mode->hdisplay - 1));
4855 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4856
f564048e
EA		 4857 I915_WRITE(PIPECONF(pipe), pipeconf);
4858 POSTING_READ(PIPECONF(pipe));
929c77fb 4859 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4860
4861 intel_wait_for_vblank(dev, pipe);
4862
f564048e
EA		 4863 I915_WRITE(DSPCNTR(plane), dspcntr);
4864 POSTING_READ(DSPCNTR(plane));
4865
94352cf9 4866 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4867
4868 intel_update_watermarks(dev);
4869
f564048e
EA		 4870 return ret;
4871}
4872
9fb526db
KP		 4873/*
4874 * Initialize reference clocks when the driver loads
4875 */
4876void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4877{
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4880 struct intel_encoder *encoder;
13d83a67
JB		 4881 u32 temp;
4882 bool has_lvds = false;
199e5d79
KP		 4883 bool has_cpu_edp = false;
4884 bool has_pch_edp = false;
4885 bool has_panel = false;
99eb6a01
KP		 4886 bool has_ck505 = false;
4887 bool can_ssc = false;
13d83a67
JB		 4888
4889 /* We need to take the global config into account */
199e5d79
KP		 4890 list_for_each_entry(encoder, &mode_config->encoder_list,
4891 base.head) {
4892 switch (encoder->type) {
4893 case INTEL_OUTPUT_LVDS:
4894 has_panel = true;
4895 has_lvds = true;
4896 break;
4897 case INTEL_OUTPUT_EDP:
4898 has_panel = true;
4899 if (intel_encoder_is_pch_edp(&encoder->base))
4900 has_pch_edp = true;
4901 else
4902 has_cpu_edp = true;
4903 break;
13d83a67
JB		 4904 }
4905 }
4906
99eb6a01
KP		 4907 if (HAS_PCH_IBX(dev)) {
4908 has_ck505 = dev_priv->display_clock_mode;
4909 can_ssc = has_ck505;
4910 } else {
4911 has_ck505 = false;
4912 can_ssc = true;
4913 }
4914
4915 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4916 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4917 has_ck505);
13d83a67
JB		 4918
4919 /* Ironlake: try to setup display ref clock before DPLL
4920 * enabling. This is only under driver's control after
4921 * PCH B stepping, previous chipset stepping should be
4922 * ignoring this setting.
4923 */
4924 temp = I915_READ(PCH_DREF_CONTROL);
4925 /* Always enable nonspread source */
4926 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4927
99eb6a01
KP		 4928 if (has_ck505)
4929 temp |= DREF_NONSPREAD_CK505_ENABLE;
4930 else
4931 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4932
199e5d79
KP		 4933 if (has_panel) {
4934 temp &= ~DREF_SSC_SOURCE_MASK;
4935 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4936
199e5d79 4937 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4938 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4939 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4940 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4941 } else
4942 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4943
4944 /* Get SSC going before enabling the outputs */
4945 I915_WRITE(PCH_DREF_CONTROL, temp);
4946 POSTING_READ(PCH_DREF_CONTROL);
4947 udelay(200);
4948
13d83a67
JB		 4949 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4950
4951 /* Enable CPU source on CPU attached eDP */
199e5d79 4952 if (has_cpu_edp) {
99eb6a01 4953 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4954 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4955 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4956 }
13d83a67
JB		 4957 else
4958 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4959 } else
4960 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4961
4962 I915_WRITE(PCH_DREF_CONTROL, temp);
4963 POSTING_READ(PCH_DREF_CONTROL);
4964 udelay(200);
4965 } else {
4966 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4967
4968 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4969
4970 /* Turn off CPU output */
4971 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4972
4973 I915_WRITE(PCH_DREF_CONTROL, temp);
4974 POSTING_READ(PCH_DREF_CONTROL);
4975 udelay(200);
4976
4977 /* Turn off the SSC source */
4978 temp &= ~DREF_SSC_SOURCE_MASK;
4979 temp |= DREF_SSC_SOURCE_DISABLE;
4980
4981 /* Turn off SSC1 */
4982 temp &= ~ DREF_SSC1_ENABLE;
4983
13d83a67
JB		 4984 I915_WRITE(PCH_DREF_CONTROL, temp);
4985 POSTING_READ(PCH_DREF_CONTROL);
4986 udelay(200);
4987 }
4988}
4989
d9d444cb
JB		 4990static int ironlake_get_refclk(struct drm_crtc *crtc)
4991{
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_encoder *encoder;
d9d444cb
JB		 4995 struct intel_encoder *edp_encoder = NULL;
4996 int num_connectors = 0;
4997 bool is_lvds = false;
4998
6c2b7c12 4999 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5000 switch (encoder->type) {
5001 case INTEL_OUTPUT_LVDS:
5002 is_lvds = true;
5003 break;
5004 case INTEL_OUTPUT_EDP:
5005 edp_encoder = encoder;
5006 break;
5007 }
5008 num_connectors++;
5009 }
5010
5011 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5012 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5013 dev_priv->lvds_ssc_freq);
5014 return dev_priv->lvds_ssc_freq * 1000;
5015 }
5016
5017 return 120000;
5018}
5019
c8203565
PZ		 5020static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5021 struct drm_display_mode *adjusted_mode,
5022 bool dither)
5023{
5024 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 int pipe = intel_crtc->pipe;
5027 uint32_t val;
5028
5029 val = I915_READ(PIPECONF(pipe));
5030
5031 val &= ~PIPE_BPC_MASK;
5032 switch (intel_crtc->bpp) {
5033 case 18:
5034 val |= PIPE_6BPC;
5035 break;
5036 case 24:
5037 val |= PIPE_8BPC;
5038 break;
5039 case 30:
5040 val |= PIPE_10BPC;
5041 break;
5042 case 36:
5043 val |= PIPE_12BPC;
5044 break;
5045 default:
cc769b62
PZ		 5046 /* Case prevented by intel_choose_pipe_bpp_dither. */
5047 BUG();
c8203565
PZ		 5048 }
5049
5050 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5051 if (dither)
5052 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5053
5054 val &= ~PIPECONF_INTERLACE_MASK;
5055 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5056 val |= PIPECONF_INTERLACED_ILK;
5057 else
5058 val |= PIPECONF_PROGRESSIVE;
5059
5060 I915_WRITE(PIPECONF(pipe), val);
5061 POSTING_READ(PIPECONF(pipe));
5062}
5063
ee2b0b38
PZ		 5064static void haswell_set_pipeconf(struct drm_crtc *crtc,
5065 struct drm_display_mode *adjusted_mode,
5066 bool dither)
5067{
5068 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5070 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5071 uint32_t val;
5072
702e7a56 5073 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5074
5075 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5076 if (dither)
5077 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5078
5079 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5080 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5081 val |= PIPECONF_INTERLACED_ILK;
5082 else
5083 val |= PIPECONF_PROGRESSIVE;
5084
702e7a56
PZ		 5085 I915_WRITE(PIPECONF(cpu_transcoder), val);
5086 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5087}
5088
6591c6e4
PZ		 5089static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5090 struct drm_display_mode *adjusted_mode,
5091 intel_clock_t *clock,
5092 bool *has_reduced_clock,
5093 intel_clock_t *reduced_clock)
5094{
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 struct intel_encoder *intel_encoder;
5098 int refclk;
5099 const intel_limit_t *limit;
5100 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5101
5102 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5103 switch (intel_encoder->type) {
5104 case INTEL_OUTPUT_LVDS:
5105 is_lvds = true;
5106 break;
5107 case INTEL_OUTPUT_SDVO:
5108 case INTEL_OUTPUT_HDMI:
5109 is_sdvo = true;
5110 if (intel_encoder->needs_tv_clock)
5111 is_tv = true;
5112 break;
5113 case INTEL_OUTPUT_TVOUT:
5114 is_tv = true;
5115 break;
5116 }
5117 }
5118
5119 refclk = ironlake_get_refclk(crtc);
5120
5121 /*
5122 * Returns a set of divisors for the desired target clock with the given
5123 * refclk, or FALSE. The returned values represent the clock equation:
5124 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5125 */
5126 limit = intel_limit(crtc, refclk);
5127 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5128 clock);
5129 if (!ret)
5130 return false;
5131
5132 if (is_lvds && dev_priv->lvds_downclock_avail) {
5133 /*
5134 * Ensure we match the reduced clock's P to the target clock.
5135 * If the clocks don't match, we can't switch the display clock
5136 * by using the FP0/FP1. In such case we will disable the LVDS
5137 * downclock feature.
5138 */
5139 *has_reduced_clock = limit->find_pll(limit, crtc,
5140 dev_priv->lvds_downclock,
5141 refclk,
5142 clock,
5143 reduced_clock);
5144 }
5145
5146 if (is_sdvo && is_tv)
5147 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5148
5149 return true;
5150}
5151
01a415fd
DV		 5152static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5153{
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 uint32_t temp;
5156
5157 temp = I915_READ(SOUTH_CHICKEN1);
5158 if (temp & FDI_BC_BIFURCATION_SELECT)
5159 return;
5160
5161 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5162 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5163
5164 temp |= FDI_BC_BIFURCATION_SELECT;
5165 DRM_DEBUG_KMS("enabling fdi C rx\n");
5166 I915_WRITE(SOUTH_CHICKEN1, temp);
5167 POSTING_READ(SOUTH_CHICKEN1);
5168}
5169
5170static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5171{
5172 struct drm_device *dev = intel_crtc->base.dev;
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 struct intel_crtc *pipe_B_crtc =
5175 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5176
5177 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5178 intel_crtc->pipe, intel_crtc->fdi_lanes);
5179 if (intel_crtc->fdi_lanes > 4) {
5180 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5181 intel_crtc->pipe, intel_crtc->fdi_lanes);
5182 /* Clamp lanes to avoid programming the hw with bogus values. */
5183 intel_crtc->fdi_lanes = 4;
5184
5185 return false;
5186 }
5187
5188 if (dev_priv->num_pipe == 2)
5189 return true;
5190
5191 switch (intel_crtc->pipe) {
5192 case PIPE_A:
5193 return true;
5194 case PIPE_B:
5195 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5196 intel_crtc->fdi_lanes > 2) {
5197 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5198 intel_crtc->pipe, intel_crtc->fdi_lanes);
5199 /* Clamp lanes to avoid programming the hw with bogus values. */
5200 intel_crtc->fdi_lanes = 2;
5201
5202 return false;
5203 }
5204
5205 if (intel_crtc->fdi_lanes > 2)
5206 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5207 else
5208 cpt_enable_fdi_bc_bifurcation(dev);
5209
5210 return true;
5211 case PIPE_C:
5212 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5213 if (intel_crtc->fdi_lanes > 2) {
5214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5215 intel_crtc->pipe, intel_crtc->fdi_lanes);
5216 /* Clamp lanes to avoid programming the hw with bogus values. */
5217 intel_crtc->fdi_lanes = 2;
5218
5219 return false;
5220 }
5221 } else {
5222 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5223 return false;
5224 }
5225
5226 cpt_enable_fdi_bc_bifurcation(dev);
5227
5228 return true;
5229 default:
5230 BUG();
5231 }
5232}
5233
f48d8f23
PZ		 5234static void ironlake_set_m_n(struct drm_crtc *crtc,
5235 struct drm_display_mode *mode,
5236 struct drm_display_mode *adjusted_mode)
5237{
5238 struct drm_device *dev = crtc->dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5241 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5242 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5243 struct fdi_m_n m_n = {0};
5244 int target_clock, pixel_multiplier, lane, link_bw;
5245 bool is_dp = false, is_cpu_edp = false;
5246
5247 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5248 switch (intel_encoder->type) {
5249 case INTEL_OUTPUT_DISPLAYPORT:
5250 is_dp = true;
5251 break;
5252 case INTEL_OUTPUT_EDP:
5253 is_dp = true;
5254 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5255 is_cpu_edp = true;
5256 edp_encoder = intel_encoder;
5257 break;
5258 }
5259 }
5260
5261 /* FDI link */
5262 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5263 lane = 0;
5264 /* CPU eDP doesn't require FDI link, so just set DP M/N
5265 according to current link config */
5266 if (is_cpu_edp) {
5267 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5268 } else {
5269 /* FDI is a binary signal running at ~2.7GHz, encoding
5270 * each output octet as 10 bits. The actual frequency
5271 * is stored as a divider into a 100MHz clock, and the
5272 * mode pixel clock is stored in units of 1KHz.
5273 * Hence the bw of each lane in terms of the mode signal
5274 * is:
5275 */
5276 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5277 }
5278
5279 /* [e]DP over FDI requires target mode clock instead of link clock. */
5280 if (edp_encoder)
5281 target_clock = intel_edp_target_clock(edp_encoder, mode);
5282 else if (is_dp)
5283 target_clock = mode->clock;
5284 else
5285 target_clock = adjusted_mode->clock;
5286
5287 if (!lane) {
5288 /*
5289 * Account for spread spectrum to avoid
5290 * oversubscribing the link. Max center spread
5291 * is 2.5%; use 5% for safety's sake.
5292 */
5293 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5294 lane = bps / (link_bw * 8) + 1;
5295 }
5296
5297 intel_crtc->fdi_lanes = lane;
5298
5299 if (pixel_multiplier > 1)
5300 link_bw *= pixel_multiplier;
5301 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5302 &m_n);
5303
afe2fcf5
PZ		 5304 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5305 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5306 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5307 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5308}
5309
de13a2e3
PZ		 5310static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5311 struct drm_display_mode *adjusted_mode,
5312 intel_clock_t *clock, u32 fp)
79e53945 5313{
de13a2e3 5314 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5317 struct intel_encoder *intel_encoder;
5318 uint32_t dpll;
5319 int factor, pixel_multiplier, num_connectors = 0;
5320 bool is_lvds = false, is_sdvo = false, is_tv = false;
5321 bool is_dp = false, is_cpu_edp = false;
79e53945 5322
de13a2e3
PZ		 5323 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5324 switch (intel_encoder->type) {
79e53945
JB		 5325 case INTEL_OUTPUT_LVDS:
5326 is_lvds = true;
5327 break;
5328 case INTEL_OUTPUT_SDVO:
7d57382e 5329 case INTEL_OUTPUT_HDMI:
79e53945 5330 is_sdvo = true;
de13a2e3 5331 if (intel_encoder->needs_tv_clock)
e2f0ba97 5332 is_tv = true;
79e53945 5333 break;
79e53945
JB		 5334 case INTEL_OUTPUT_TVOUT:
5335 is_tv = true;
5336 break;
a4fc5ed6
KP		 5337 case INTEL_OUTPUT_DISPLAYPORT:
5338 is_dp = true;
5339 break;
32f9d658 5340 case INTEL_OUTPUT_EDP:
e3aef172 5341 is_dp = true;
de13a2e3 5342 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5343 is_cpu_edp = true;
32f9d658 5344 break;
79e53945 5345 }
43565a06 5346
c751ce4f 5347 num_connectors++;
79e53945
JB		 5348 }
5349
c1858123 5350 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5351 factor = 21;
5352 if (is_lvds) {
5353 if ((intel_panel_use_ssc(dev_priv) &&
5354 dev_priv->lvds_ssc_freq == 100) ||
5355 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5356 factor = 25;
5357 } else if (is_sdvo && is_tv)
5358 factor = 20;
c1858123 5359
de13a2e3 5360 if (clock->m < factor * clock->n)
8febb297 5361 fp |= FP_CB_TUNE;
2c07245f 5362
5eddb70b 5363 dpll = 0;
2c07245f 5364
a07d6787
EA		 5365 if (is_lvds)
5366 dpll |= DPLLB_MODE_LVDS;
5367 else
5368 dpll |= DPLLB_MODE_DAC_SERIAL;
5369 if (is_sdvo) {
de13a2e3 5370 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5371 if (pixel_multiplier > 1) {
5372 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5373 }
a07d6787
EA		 5374 dpll |= DPLL_DVO_HIGH_SPEED;
5375 }
e3aef172 5376 if (is_dp && !is_cpu_edp)
a07d6787 5377 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5378
a07d6787 5379 /* compute bitmask from p1 value */
de13a2e3 5380 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5381 /* also FPA1 */
de13a2e3 5382 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5383
de13a2e3 5384 switch (clock->p2) {
a07d6787
EA		 5385 case 5:
5386 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5387 break;
5388 case 7:
5389 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5390 break;
5391 case 10:
5392 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5393 break;
5394 case 14:
5395 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5396 break;
79e53945
JB		 5397 }
5398
43565a06
KH		 5399 if (is_sdvo && is_tv)
5400 dpll |= PLL_REF_INPUT_TVCLKINBC;
5401 else if (is_tv)
79e53945 5402 /* XXX: just matching BIOS for now */
43565a06 5403 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5404 dpll |= 3;
a7615030 5405 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5406 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5407 else
5408 dpll |= PLL_REF_INPUT_DREFCLK;
5409
de13a2e3
PZ		 5410 return dpll;
5411}
5412
5413static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5414 struct drm_display_mode *mode,
5415 struct drm_display_mode *adjusted_mode,
5416 int x, int y,
5417 struct drm_framebuffer *fb)
5418{
5419 struct drm_device *dev = crtc->dev;
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5422 int pipe = intel_crtc->pipe;
5423 int plane = intel_crtc->plane;
5424 int num_connectors = 0;
5425 intel_clock_t clock, reduced_clock;
5426 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5427 bool ok, has_reduced_clock = false;
5428 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5429 struct intel_encoder *encoder;
5430 u32 temp;
5431 int ret;
01a415fd 5432 bool dither, fdi_config_ok;
de13a2e3
PZ		 5433
5434 for_each_encoder_on_crtc(dev, crtc, encoder) {
5435 switch (encoder->type) {
5436 case INTEL_OUTPUT_LVDS:
5437 is_lvds = true;
5438 break;
de13a2e3
PZ		 5439 case INTEL_OUTPUT_DISPLAYPORT:
5440 is_dp = true;
5441 break;
5442 case INTEL_OUTPUT_EDP:
5443 is_dp = true;
e2f12b07 5444 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5445 is_cpu_edp = true;
5446 break;
5447 }
5448
5449 num_connectors++;
5450 }
5451
5dc5298b
PZ		 5452 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5453 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5454
de13a2e3
PZ		 5455 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5456 &has_reduced_clock, &reduced_clock);
5457 if (!ok) {
5458 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5459 return -EINVAL;
5460 }
5461
5462 /* Ensure that the cursor is valid for the new mode before changing... */
5463 intel_crtc_update_cursor(crtc, true);
5464
5465 /* determine panel color depth */
c8241969
JN		 5466 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5467 adjusted_mode);
de13a2e3
PZ		 5468 if (is_lvds && dev_priv->lvds_dither)
5469 dither = true;
5470
5471 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5472 if (has_reduced_clock)
5473 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5474 reduced_clock.m2;
5475
5476 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5477
f7cb34d4 5478 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5479 drm_mode_debug_printmodeline(mode);
5480
5dc5298b
PZ		 5481 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5482 if (!is_cpu_edp) {
ee7b9f93 5483 struct intel_pch_pll *pll;
4b645f14 5484
ee7b9f93
JB		 5485 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5486 if (pll == NULL) {
5487 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5488 pipe);
4b645f14
JB		 5489 return -EINVAL;
5490 }
ee7b9f93
JB		 5491 } else
5492 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5493
5494 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5495 * This is an exception to the general rule that mode_set doesn't turn
5496 * things on.
5497 */
5498 if (is_lvds) {
fae14981 5499 temp = I915_READ(PCH_LVDS);
5eddb70b 5500 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5501 if (HAS_PCH_CPT(dev)) {
5502 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5503 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5504 } else {
5505 if (pipe == 1)
5506 temp |= LVDS_PIPEB_SELECT;
5507 else
5508 temp &= ~LVDS_PIPEB_SELECT;
5509 }
4b645f14 5510
a3e17eb8 5511 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5512 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5513 /* Set the B0-B3 data pairs corresponding to whether we're going to
5514 * set the DPLLs for dual-channel mode or not.
5515 */
5516 if (clock.p2 == 7)
5eddb70b 5517 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5518 else
5eddb70b 5519 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5520
5521 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5522 * appropriately here, but we need to look more thoroughly into how
5523 * panels behave in the two modes.
5524 */
284d5df5 5525 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5526 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5527 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5528 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5529 temp |= LVDS_VSYNC_POLARITY;
fae14981 5530 I915_WRITE(PCH_LVDS, temp);
79e53945 5531 }
434ed097 5532
e3aef172 5533 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5534 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5535 } else {
8db9d77b 5536 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5537 I915_WRITE(TRANSDATA_M1(pipe), 0);
5538 I915_WRITE(TRANSDATA_N1(pipe), 0);
5539 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5540 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5541 }
79e53945 5542
ee7b9f93
JB		 5543 if (intel_crtc->pch_pll) {
5544 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5545
32f9d658 5546 /* Wait for the clocks to stabilize. */
ee7b9f93 5547 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5548 udelay(150);
5549
8febb297
EA		 5550 /* The pixel multiplier can only be updated once the
5551 * DPLL is enabled and the clocks are stable.
5552 *
5553 * So write it again.
5554 */
ee7b9f93 5555 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5556 }
79e53945 5557
5eddb70b 5558 intel_crtc->lowfreq_avail = false;
ee7b9f93 5559 if (intel_crtc->pch_pll) {
4b645f14 5560 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5561 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5562 intel_crtc->lowfreq_avail = true;
4b645f14 5563 } else {
ee7b9f93 5564 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5565 }
5566 }
5567
b0e77b9c 5568 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5569
01a415fd
DV		 5570 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5571 * ironlake_check_fdi_lanes. */
f48d8f23 5572 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5573
01a415fd
DV		 5574 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5575
e3aef172 5576 if (is_cpu_edp)
8febb297 5577 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5578
c8203565 5579 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5580
9d0498a2 5581 intel_wait_for_vblank(dev, pipe);
79e53945 5582
a1f9e77e
PZ		 5583 /* Set up the display plane register */
5584 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5585 POSTING_READ(DSPCNTR(plane));
79e53945 5586
94352cf9 5587 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5588
5589 intel_update_watermarks(dev);
5590
1f8eeabf
ED		 5591 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5592
01a415fd 5593 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5594}
5595
09b4ddf9
PZ		 5596static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5597 struct drm_display_mode *mode,
5598 struct drm_display_mode *adjusted_mode,
5599 int x, int y,
5600 struct drm_framebuffer *fb)
5601{
5602 struct drm_device *dev = crtc->dev;
5603 struct drm_i915_private *dev_priv = dev->dev_private;
5604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5605 int pipe = intel_crtc->pipe;
5606 int plane = intel_crtc->plane;
5607 int num_connectors = 0;
5608 intel_clock_t clock, reduced_clock;
5dc5298b 5609 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5610 bool ok, has_reduced_clock = false;
5611 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5612 struct intel_encoder *encoder;
5613 u32 temp;
5614 int ret;
5615 bool dither;
5616
5617 for_each_encoder_on_crtc(dev, crtc, encoder) {
5618 switch (encoder->type) {
5619 case INTEL_OUTPUT_LVDS:
5620 is_lvds = true;
5621 break;
5622 case INTEL_OUTPUT_DISPLAYPORT:
5623 is_dp = true;
5624 break;
5625 case INTEL_OUTPUT_EDP:
5626 is_dp = true;
5627 if (!intel_encoder_is_pch_edp(&encoder->base))
5628 is_cpu_edp = true;
5629 break;
5630 }
5631
5632 num_connectors++;
5633 }
5634
a5c961d1
PZ		 5635 if (is_cpu_edp)
5636 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5637 else
5638 intel_crtc->cpu_transcoder = pipe;
5639
5dc5298b
PZ		 5640 /* We are not sure yet this won't happen. */
5641 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5642 INTEL_PCH_TYPE(dev));
5643
5644 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5645 num_connectors, pipe_name(pipe));
5646
702e7a56 5647 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5648 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5649
5650 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5651
6441ab5f
PZ		 5652 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5653 return -EINVAL;
5654
5dc5298b
PZ		 5655 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5656 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5657 &has_reduced_clock,
5658 &reduced_clock);
5659 if (!ok) {
5660 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5661 return -EINVAL;
5662 }
09b4ddf9
PZ		 5663 }
5664
5665 /* Ensure that the cursor is valid for the new mode before changing... */
5666 intel_crtc_update_cursor(crtc, true);
5667
5668 /* determine panel color depth */
c8241969
JN		 5669 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5670 adjusted_mode);
09b4ddf9
PZ		 5671 if (is_lvds && dev_priv->lvds_dither)
5672 dither = true;
5673
09b4ddf9
PZ		 5674 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5675 drm_mode_debug_printmodeline(mode);
5676
5dc5298b
PZ		 5677 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5678 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5679 if (has_reduced_clock)
5680 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5681 reduced_clock.m2;
5682
5683 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5684 fp);
5685
5686 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5687 * own on pre-Haswell/LPT generation */
5688 if (!is_cpu_edp) {
5689 struct intel_pch_pll *pll;
5690
5691 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5692 if (pll == NULL) {
5693 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5694 pipe);
5695 return -EINVAL;
5696 }
5697 } else
5698 intel_put_pch_pll(intel_crtc);
09b4ddf9 5699
5dc5298b
PZ		 5700 /* The LVDS pin pair needs to be on before the DPLLs are
5701 * enabled. This is an exception to the general rule that
5702 * mode_set doesn't turn things on.
5703 */
5704 if (is_lvds) {
5705 temp = I915_READ(PCH_LVDS);
5706 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5707 if (HAS_PCH_CPT(dev)) {
5708 temp &= ~PORT_TRANS_SEL_MASK;
5709 temp |= PORT_TRANS_SEL_CPT(pipe);
5710 } else {
5711 if (pipe == 1)
5712 temp |= LVDS_PIPEB_SELECT;
5713 else
5714 temp &= ~LVDS_PIPEB_SELECT;
5715 }
09b4ddf9 5716
5dc5298b
PZ		 5717 /* set the corresponsding LVDS_BORDER bit */
5718 temp |= dev_priv->lvds_border_bits;
5719 /* Set the B0-B3 data pairs corresponding to whether
5720 * we're going to set the DPLLs for dual-channel mode or
5721 * not.
5722 */
5723 if (clock.p2 == 7)
5724 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5725 else
5dc5298b
PZ		 5726 temp &= ~(LVDS_B0B3_POWER_UP |
5727 LVDS_CLKB_POWER_UP);
5728
5729 /* It would be nice to set 24 vs 18-bit mode
5730 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5731 * look more thoroughly into how panels behave in the
5732 * two modes.
5733 */
5734 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5735 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5736 temp |= LVDS_HSYNC_POLARITY;
5737 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5738 temp |= LVDS_VSYNC_POLARITY;
5739 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5740 }
09b4ddf9
PZ		 5741 }
5742
5743 if (is_dp && !is_cpu_edp) {
5744 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5745 } else {
5dc5298b
PZ		 5746 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5747 /* For non-DP output, clear any trans DP clock recovery
5748 * setting.*/
5749 I915_WRITE(TRANSDATA_M1(pipe), 0);
5750 I915_WRITE(TRANSDATA_N1(pipe), 0);
5751 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5752 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5753 }
09b4ddf9
PZ		 5754 }
5755
5756 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5757 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5758 if (intel_crtc->pch_pll) {
5759 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5760
5761 /* Wait for the clocks to stabilize. */
5762 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5763 udelay(150);
5764
5765 /* The pixel multiplier can only be updated once the
5766 * DPLL is enabled and the clocks are stable.
5767 *
5768 * So write it again.
5769 */
5770 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5771 }
5772
5773 if (intel_crtc->pch_pll) {
5774 if (is_lvds && has_reduced_clock && i915_powersave) {
5775 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5776 intel_crtc->lowfreq_avail = true;
5777 } else {
5778 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5779 }
09b4ddf9
PZ		 5780 }
5781 }
5782
5783 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5784
1eb8dfec
PZ		 5785 if (!is_dp || is_cpu_edp)
5786 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5787
5dc5298b
PZ		 5788 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5789 if (is_cpu_edp)
5790 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5791
ee2b0b38 5792 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5793
09b4ddf9
PZ		 5794 /* Set up the display plane register */
5795 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5796 POSTING_READ(DSPCNTR(plane));
5797
5798 ret = intel_pipe_set_base(crtc, x, y, fb);
5799
5800 intel_update_watermarks(dev);
5801
5802 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5803
5804 return ret;
5805}
5806
f564048e
EA		 5807static int intel_crtc_mode_set(struct drm_crtc *crtc,
5808 struct drm_display_mode *mode,
5809 struct drm_display_mode *adjusted_mode,
5810 int x, int y,
94352cf9 5811 struct drm_framebuffer *fb)
f564048e
EA		 5812{
5813 struct drm_device *dev = crtc->dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5815 struct drm_encoder_helper_funcs *encoder_funcs;
5816 struct intel_encoder *encoder;
0b701d27
EA		 5817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5818 int pipe = intel_crtc->pipe;
f564048e
EA		 5819 int ret;
5820
0b701d27 5821 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5822
f564048e 5823 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5824 x, y, fb);
79e53945 5825 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5826
9256aa19
DV		 5827 if (ret != 0)
5828 return ret;
5829
5830 for_each_encoder_on_crtc(dev, crtc, encoder) {
5831 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5832 encoder->base.base.id,
5833 drm_get_encoder_name(&encoder->base),
5834 mode->base.id, mode->name);
5835 encoder_funcs = encoder->base.helper_private;
5836 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5837 }
5838
5839 return 0;
79e53945
JB		 5840}
5841
3a9627f4
WF		 5842static bool intel_eld_uptodate(struct drm_connector *connector,
5843 int reg_eldv, uint32_t bits_eldv,
5844 int reg_elda, uint32_t bits_elda,
5845 int reg_edid)
5846{
5847 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5848 uint8_t *eld = connector->eld;
5849 uint32_t i;
5850
5851 i = I915_READ(reg_eldv);
5852 i &= bits_eldv;
5853
5854 if (!eld[0])
5855 return !i;
5856
5857 if (!i)
5858 return false;
5859
5860 i = I915_READ(reg_elda);
5861 i &= ~bits_elda;
5862 I915_WRITE(reg_elda, i);
5863
5864 for (i = 0; i < eld[2]; i++)
5865 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5866 return false;
5867
5868 return true;
5869}
5870
e0dac65e
WF		 5871static void g4x_write_eld(struct drm_connector *connector,
5872 struct drm_crtc *crtc)
5873{
5874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5875 uint8_t *eld = connector->eld;
5876 uint32_t eldv;
5877 uint32_t len;
5878 uint32_t i;
5879
5880 i = I915_READ(G4X_AUD_VID_DID);
5881
5882 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5883 eldv = G4X_ELDV_DEVCL_DEVBLC;
5884 else
5885 eldv = G4X_ELDV_DEVCTG;
5886
3a9627f4
WF		 5887 if (intel_eld_uptodate(connector,
5888 G4X_AUD_CNTL_ST, eldv,
5889 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5890 G4X_HDMIW_HDMIEDID))
5891 return;
5892
e0dac65e
WF		 5893 i = I915_READ(G4X_AUD_CNTL_ST);
5894 i &= ~(eldv | G4X_ELD_ADDR);
5895 len = (i >> 9) & 0x1f; /* ELD buffer size */
5896 I915_WRITE(G4X_AUD_CNTL_ST, i);
5897
5898 if (!eld[0])
5899 return;
5900
5901 len = min_t(uint8_t, eld[2], len);
5902 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5903 for (i = 0; i < len; i++)
5904 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5905
5906 i = I915_READ(G4X_AUD_CNTL_ST);
5907 i |= eldv;
5908 I915_WRITE(G4X_AUD_CNTL_ST, i);
5909}
5910
83358c85
WX		 5911static void haswell_write_eld(struct drm_connector *connector,
5912 struct drm_crtc *crtc)
5913{
5914 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5915 uint8_t *eld = connector->eld;
5916 struct drm_device *dev = crtc->dev;
5917 uint32_t eldv;
5918 uint32_t i;
5919 int len;
5920 int pipe = to_intel_crtc(crtc)->pipe;
5921 int tmp;
5922
5923 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5924 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5925 int aud_config = HSW_AUD_CFG(pipe);
5926 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5927
5928
5929 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5930
5931 /* Audio output enable */
5932 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5933 tmp = I915_READ(aud_cntrl_st2);
5934 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5935 I915_WRITE(aud_cntrl_st2, tmp);
5936
5937 /* Wait for 1 vertical blank */
5938 intel_wait_for_vblank(dev, pipe);
5939
5940 /* Set ELD valid state */
5941 tmp = I915_READ(aud_cntrl_st2);
5942 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5943 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5944 I915_WRITE(aud_cntrl_st2, tmp);
5945 tmp = I915_READ(aud_cntrl_st2);
5946 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5947
5948 /* Enable HDMI mode */
5949 tmp = I915_READ(aud_config);
5950 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5951 /* clear N_programing_enable and N_value_index */
5952 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5953 I915_WRITE(aud_config, tmp);
5954
5955 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5956
5957 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5958
5959 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5960 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5961 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5962 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5963 } else
5964 I915_WRITE(aud_config, 0);
5965
5966 if (intel_eld_uptodate(connector,
5967 aud_cntrl_st2, eldv,
5968 aud_cntl_st, IBX_ELD_ADDRESS,
5969 hdmiw_hdmiedid))
5970 return;
5971
5972 i = I915_READ(aud_cntrl_st2);
5973 i &= ~eldv;
5974 I915_WRITE(aud_cntrl_st2, i);
5975
5976 if (!eld[0])
5977 return;
5978
5979 i = I915_READ(aud_cntl_st);
5980 i &= ~IBX_ELD_ADDRESS;
5981 I915_WRITE(aud_cntl_st, i);
5982 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5983 DRM_DEBUG_DRIVER("port num:%d\n", i);
5984
5985 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5986 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5987 for (i = 0; i < len; i++)
5988 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5989
5990 i = I915_READ(aud_cntrl_st2);
5991 i |= eldv;
5992 I915_WRITE(aud_cntrl_st2, i);
5993
5994}
5995
e0dac65e
WF		 5996static void ironlake_write_eld(struct drm_connector *connector,
5997 struct drm_crtc *crtc)
5998{
5999 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6000 uint8_t *eld = connector->eld;
6001 uint32_t eldv;
6002 uint32_t i;
6003 int len;
6004 int hdmiw_hdmiedid;
b6daa025 6005 int aud_config;
e0dac65e
WF		 6006 int aud_cntl_st;
6007 int aud_cntrl_st2;
9b138a83 6008 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6009
b3f33cbf 6010 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6011 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6012 aud_config = IBX_AUD_CFG(pipe);
6013 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6014 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6015 } else {
9b138a83
WX		 6016 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6017 aud_config = CPT_AUD_CFG(pipe);
6018 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6019 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6020 }
6021
9b138a83 6022 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6023
6024 i = I915_READ(aud_cntl_st);
9b138a83 6025 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6026 if (!i) {
6027 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6028 /* operate blindly on all ports */
1202b4c6
WF		 6029 eldv = IBX_ELD_VALIDB;
6030 eldv |= IBX_ELD_VALIDB << 4;
6031 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6032 } else {
6033 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6034 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6035 }
6036
3a9627f4
WF		 6037 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6038 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6039 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6040 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6041 } else
6042 I915_WRITE(aud_config, 0);
e0dac65e 6043
3a9627f4
WF		 6044 if (intel_eld_uptodate(connector,
6045 aud_cntrl_st2, eldv,
6046 aud_cntl_st, IBX_ELD_ADDRESS,
6047 hdmiw_hdmiedid))
6048 return;
6049
e0dac65e
WF		 6050 i = I915_READ(aud_cntrl_st2);
6051 i &= ~eldv;
6052 I915_WRITE(aud_cntrl_st2, i);
6053
6054 if (!eld[0])
6055 return;
6056
e0dac65e 6057 i = I915_READ(aud_cntl_st);
1202b4c6 6058 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6059 I915_WRITE(aud_cntl_st, i);
6060
6061 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6062 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6063 for (i = 0; i < len; i++)
6064 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6065
6066 i = I915_READ(aud_cntrl_st2);
6067 i |= eldv;
6068 I915_WRITE(aud_cntrl_st2, i);
6069}
6070
6071void intel_write_eld(struct drm_encoder *encoder,
6072 struct drm_display_mode *mode)
6073{
6074 struct drm_crtc *crtc = encoder->crtc;
6075 struct drm_connector *connector;
6076 struct drm_device *dev = encoder->dev;
6077 struct drm_i915_private *dev_priv = dev->dev_private;
6078
6079 connector = drm_select_eld(encoder, mode);
6080 if (!connector)
6081 return;
6082
6083 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6084 connector->base.id,
6085 drm_get_connector_name(connector),
6086 connector->encoder->base.id,
6087 drm_get_encoder_name(connector->encoder));
6088
6089 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6090
6091 if (dev_priv->display.write_eld)
6092 dev_priv->display.write_eld(connector, crtc);
6093}
6094
79e53945
JB		 6095/** Loads the palette/gamma unit for the CRTC with the prepared values */
6096void intel_crtc_load_lut(struct drm_crtc *crtc)
6097{
6098 struct drm_device *dev = crtc->dev;
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6101 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6102 int i;
6103
6104 /* The clocks have to be on to load the palette. */
aed3f09d 6105 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6106 return;
6107
f2b115e6 6108 /* use legacy palette for Ironlake */
bad720ff 6109 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6110 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6111
79e53945
JB		 6112 for (i = 0; i < 256; i++) {
6113 I915_WRITE(palreg + 4 * i,
6114 (intel_crtc->lut_r[i] << 16) |
6115 (intel_crtc->lut_g[i] << 8) |
6116 intel_crtc->lut_b[i]);
6117 }
6118}
6119
560b85bb
CW		 6120static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6121{
6122 struct drm_device *dev = crtc->dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125 bool visible = base != 0;
6126 u32 cntl;
6127
6128 if (intel_crtc->cursor_visible == visible)
6129 return;
6130
9db4a9c7 6131 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6132 if (visible) {
6133 /* On these chipsets we can only modify the base whilst
6134 * the cursor is disabled.
6135 */
9db4a9c7 6136 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6137
6138 cntl &= ~(CURSOR_FORMAT_MASK);
6139 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6140 cntl |= CURSOR_ENABLE |
6141 CURSOR_GAMMA_ENABLE |
6142 CURSOR_FORMAT_ARGB;
6143 } else
6144 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6145 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6146
6147 intel_crtc->cursor_visible = visible;
6148}
6149
6150static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6151{
6152 struct drm_device *dev = crtc->dev;
6153 struct drm_i915_private *dev_priv = dev->dev_private;
6154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155 int pipe = intel_crtc->pipe;
6156 bool visible = base != 0;
6157
6158 if (intel_crtc->cursor_visible != visible) {
548f245b 6159 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6160 if (base) {
6161 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6162 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6163 cntl |= pipe << 28; /* Connect to correct pipe */
6164 } else {
6165 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6166 cntl |= CURSOR_MODE_DISABLE;
6167 }
9db4a9c7 6168 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6169
6170 intel_crtc->cursor_visible = visible;
6171 }
6172 /* and commit changes on next vblank */
9db4a9c7 6173 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6174}
6175
65a21cd6
JB		 6176static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6177{
6178 struct drm_device *dev = crtc->dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 int pipe = intel_crtc->pipe;
6182 bool visible = base != 0;
6183
6184 if (intel_crtc->cursor_visible != visible) {
6185 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6186 if (base) {
6187 cntl &= ~CURSOR_MODE;
6188 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6189 } else {
6190 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6191 cntl |= CURSOR_MODE_DISABLE;
6192 }
6193 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6194
6195 intel_crtc->cursor_visible = visible;
6196 }
6197 /* and commit changes on next vblank */
6198 I915_WRITE(CURBASE_IVB(pipe), base);
6199}
6200
cda4b7d3 6201/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6202static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6203 bool on)
cda4b7d3
CW		 6204{
6205 struct drm_device *dev = crtc->dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 int pipe = intel_crtc->pipe;
6209 int x = intel_crtc->cursor_x;
6210 int y = intel_crtc->cursor_y;
560b85bb 6211 u32 base, pos;
cda4b7d3
CW		 6212 bool visible;
6213
6214 pos = 0;
6215
6b383a7f 6216 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6217 base = intel_crtc->cursor_addr;
6218 if (x > (int) crtc->fb->width)
6219 base = 0;
6220
6221 if (y > (int) crtc->fb->height)
6222 base = 0;
6223 } else
6224 base = 0;
6225
6226 if (x < 0) {
6227 if (x + intel_crtc->cursor_width < 0)
6228 base = 0;
6229
6230 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6231 x = -x;
6232 }
6233 pos |= x << CURSOR_X_SHIFT;
6234
6235 if (y < 0) {
6236 if (y + intel_crtc->cursor_height < 0)
6237 base = 0;
6238
6239 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6240 y = -y;
6241 }
6242 pos |= y << CURSOR_Y_SHIFT;
6243
6244 visible = base != 0;
560b85bb 6245 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6246 return;
6247
0cd83aa9 6248 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6249 I915_WRITE(CURPOS_IVB(pipe), pos);
6250 ivb_update_cursor(crtc, base);
6251 } else {
6252 I915_WRITE(CURPOS(pipe), pos);
6253 if (IS_845G(dev) || IS_I865G(dev))
6254 i845_update_cursor(crtc, base);
6255 else
6256 i9xx_update_cursor(crtc, base);
6257 }
cda4b7d3
CW		 6258}
6259
79e53945 6260static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6261 struct drm_file *file,
79e53945
JB		 6262 uint32_t handle,
6263 uint32_t width, uint32_t height)
6264{
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6268 struct drm_i915_gem_object *obj;
cda4b7d3 6269 uint32_t addr;
3f8bc370 6270 int ret;
79e53945 6271
79e53945
JB		 6272 /* if we want to turn off the cursor ignore width and height */
6273 if (!handle) {
28c97730 6274 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6275 addr = 0;
05394f39 6276 obj = NULL;
5004417d 6277 mutex_lock(&dev->struct_mutex);
3f8bc370 6278 goto finish;
79e53945
JB		 6279 }
6280
6281 /* Currently we only support 64x64 cursors */
6282 if (width != 64 || height != 64) {
6283 DRM_ERROR("we currently only support 64x64 cursors\n");
6284 return -EINVAL;
6285 }
6286
05394f39 6287 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6288 if (&obj->base == NULL)
79e53945
JB		 6289 return -ENOENT;
6290
05394f39 6291 if (obj->base.size < width * height * 4) {
79e53945 6292 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6293 ret = -ENOMEM;
6294 goto fail;
79e53945
JB		 6295 }
6296
71acb5eb 6297 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6298 mutex_lock(&dev->struct_mutex);
b295d1b6 6299 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6300 if (obj->tiling_mode) {
6301 DRM_ERROR("cursor cannot be tiled\n");
6302 ret = -EINVAL;
6303 goto fail_locked;
6304 }
6305
2da3b9b9 6306 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6307 if (ret) {
6308 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6309 goto fail_locked;
e7b526bb
CW		 6310 }
6311
d9e86c0e
CW		 6312 ret = i915_gem_object_put_fence(obj);
6313 if (ret) {
2da3b9b9 6314 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6315 goto fail_unpin;
6316 }
6317
05394f39 6318 addr = obj->gtt_offset;
71acb5eb 6319 } else {
6eeefaf3 6320 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6321 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6322 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6323 align);
71acb5eb
DA		 6324 if (ret) {
6325 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6326 goto fail_locked;
71acb5eb 6327 }
05394f39 6328 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6329 }
6330
a6c45cf0 6331 if (IS_GEN2(dev))
14b60391
JB		 6332 I915_WRITE(CURSIZE, (height << 12) | width);
6333
3f8bc370 6334 finish:
3f8bc370 6335 if (intel_crtc->cursor_bo) {
b295d1b6 6336 if (dev_priv->info->cursor_needs_physical) {
05394f39 6337 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6338 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6339 } else
6340 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6341 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6342 }
80824003 6343
7f9872e0 6344 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6345
6346 intel_crtc->cursor_addr = addr;
05394f39 6347 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6348 intel_crtc->cursor_width = width;
6349 intel_crtc->cursor_height = height;
6350
6b383a7f 6351 intel_crtc_update_cursor(crtc, true);
3f8bc370 6352
79e53945 6353 return 0;
e7b526bb 6354fail_unpin:
05394f39 6355 i915_gem_object_unpin(obj);
7f9872e0 6356fail_locked:
34b8686e 6357 mutex_unlock(&dev->struct_mutex);
bc9025bd 6358fail:
05394f39 6359 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6360 return ret;
79e53945
JB		 6361}
6362
6363static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6364{
79e53945 6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6366
cda4b7d3
CW		 6367 intel_crtc->cursor_x = x;
6368 intel_crtc->cursor_y = y;
652c393a 6369
6b383a7f 6370 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6371
6372 return 0;
6373}
6374
6375/** Sets the color ramps on behalf of RandR */
6376void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6377 u16 blue, int regno)
6378{
6379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380
6381 intel_crtc->lut_r[regno] = red >> 8;
6382 intel_crtc->lut_g[regno] = green >> 8;
6383 intel_crtc->lut_b[regno] = blue >> 8;
6384}
6385
b8c00ac5
DA		 6386void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6387 u16 *blue, int regno)
6388{
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390
6391 *red = intel_crtc->lut_r[regno] << 8;
6392 *green = intel_crtc->lut_g[regno] << 8;
6393 *blue = intel_crtc->lut_b[regno] << 8;
6394}
6395
79e53945 6396static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6397 u16 *blue, uint32_t start, uint32_t size)
79e53945 6398{
7203425a 6399 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6401
7203425a 6402 for (i = start; i < end; i++) {
79e53945
JB		 6403 intel_crtc->lut_r[i] = red[i] >> 8;
6404 intel_crtc->lut_g[i] = green[i] >> 8;
6405 intel_crtc->lut_b[i] = blue[i] >> 8;
6406 }
6407
6408 intel_crtc_load_lut(crtc);
6409}
6410
6411/**
6412 * Get a pipe with a simple mode set on it for doing load-based monitor
6413 * detection.
6414 *
6415 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6416 * its requirements. The pipe will be connected to no other encoders.
79e53945 6417 *
c751ce4f 6418 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6419 * configured for it. In the future, it could choose to temporarily disable
6420 * some outputs to free up a pipe for its use.
6421 *
6422 * \return crtc, or NULL if no pipes are available.
6423 */
6424
6425/* VESA 640x480x72Hz mode to set on the pipe */
6426static struct drm_display_mode load_detect_mode = {
6427 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6428 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6429};
6430
d2dff872
CW		 6431static struct drm_framebuffer *
6432intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6433 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6434 struct drm_i915_gem_object *obj)
6435{
6436 struct intel_framebuffer *intel_fb;
6437 int ret;
6438
6439 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6440 if (!intel_fb) {
6441 drm_gem_object_unreference_unlocked(&obj->base);
6442 return ERR_PTR(-ENOMEM);
6443 }
6444
6445 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6446 if (ret) {
6447 drm_gem_object_unreference_unlocked(&obj->base);
6448 kfree(intel_fb);
6449 return ERR_PTR(ret);
6450 }
6451
6452 return &intel_fb->base;
6453}
6454
6455static u32
6456intel_framebuffer_pitch_for_width(int width, int bpp)
6457{
6458 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6459 return ALIGN(pitch, 64);
6460}
6461
6462static u32
6463intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6464{
6465 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6466 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6467}
6468
6469static struct drm_framebuffer *
6470intel_framebuffer_create_for_mode(struct drm_device *dev,
6471 struct drm_display_mode *mode,
6472 int depth, int bpp)
6473{
6474 struct drm_i915_gem_object *obj;
308e5bcb 6475 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6476
6477 obj = i915_gem_alloc_object(dev,
6478 intel_framebuffer_size_for_mode(mode, bpp));
6479 if (obj == NULL)
6480 return ERR_PTR(-ENOMEM);
6481
6482 mode_cmd.width = mode->hdisplay;
6483 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6484 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6485 bpp);
5ca0c34a 6486 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6487
6488 return intel_framebuffer_create(dev, &mode_cmd, obj);
6489}
6490
6491static struct drm_framebuffer *
6492mode_fits_in_fbdev(struct drm_device *dev,
6493 struct drm_display_mode *mode)
6494{
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 struct drm_i915_gem_object *obj;
6497 struct drm_framebuffer *fb;
6498
6499 if (dev_priv->fbdev == NULL)
6500 return NULL;
6501
6502 obj = dev_priv->fbdev->ifb.obj;
6503 if (obj == NULL)
6504 return NULL;
6505
6506 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6507 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6508 fb->bits_per_pixel))
d2dff872
CW		 6509 return NULL;
6510
01f2c773 6511 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6512 return NULL;
6513
6514 return fb;
6515}
6516
d2434ab7 6517bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6518 struct drm_display_mode *mode,
8261b191 6519 struct intel_load_detect_pipe *old)
79e53945
JB		 6520{
6521 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6522 struct intel_encoder *intel_encoder =
6523 intel_attached_encoder(connector);
79e53945 6524 struct drm_crtc *possible_crtc;
4ef69c7a 6525 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6526 struct drm_crtc *crtc = NULL;
6527 struct drm_device *dev = encoder->dev;
94352cf9 6528 struct drm_framebuffer *fb;
79e53945
JB		 6529 int i = -1;
6530
d2dff872
CW		 6531 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6532 connector->base.id, drm_get_connector_name(connector),
6533 encoder->base.id, drm_get_encoder_name(encoder));
6534
79e53945
JB		 6535 /*
6536 * Algorithm gets a little messy:
7a5e4805 6537 *
79e53945
JB		 6538 * - if the connector already has an assigned crtc, use it (but make
6539 * sure it's on first)
7a5e4805 6540 *
79e53945
JB		 6541 * - try to find the first unused crtc that can drive this connector,
6542 * and use that if we find one
79e53945
JB		 6543 */
6544
6545 /* See if we already have a CRTC for this connector */
6546 if (encoder->crtc) {
6547 crtc = encoder->crtc;
8261b191 6548
24218aac 6549 old->dpms_mode = connector->dpms;
8261b191
CW		 6550 old->load_detect_temp = false;
6551
6552 /* Make sure the crtc and connector are running */
24218aac
DV		 6553 if (connector->dpms != DRM_MODE_DPMS_ON)
6554 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6555
7173188d 6556 return true;
79e53945
JB		 6557 }
6558
6559 /* Find an unused one (if possible) */
6560 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6561 i++;
6562 if (!(encoder->possible_crtcs & (1 << i)))
6563 continue;
6564 if (!possible_crtc->enabled) {
6565 crtc = possible_crtc;
6566 break;
6567 }
79e53945
JB		 6568 }
6569
6570 /*
6571 * If we didn't find an unused CRTC, don't use any.
6572 */
6573 if (!crtc) {
7173188d
CW		 6574 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6575 return false;
79e53945
JB		 6576 }
6577
fc303101
DV		 6578 intel_encoder->new_crtc = to_intel_crtc(crtc);
6579 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6580
6581 intel_crtc = to_intel_crtc(crtc);
24218aac 6582 old->dpms_mode = connector->dpms;
8261b191 6583 old->load_detect_temp = true;
d2dff872 6584 old->release_fb = NULL;
79e53945 6585
6492711d
CW		 6586 if (!mode)
6587 mode = &load_detect_mode;
79e53945 6588
d2dff872
CW		 6589 /* We need a framebuffer large enough to accommodate all accesses
6590 * that the plane may generate whilst we perform load detection.
6591 * We can not rely on the fbcon either being present (we get called
6592 * during its initialisation to detect all boot displays, or it may
6593 * not even exist) or that it is large enough to satisfy the
6594 * requested mode.
6595 */
94352cf9
DV		 6596 fb = mode_fits_in_fbdev(dev, mode);
6597 if (fb == NULL) {
d2dff872 6598 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6599 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6600 old->release_fb = fb;
d2dff872
CW		 6601 } else
6602 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6603 if (IS_ERR(fb)) {
d2dff872 6604 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6605 goto fail;
79e53945 6606 }
79e53945 6607
94352cf9 6608 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6609 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6610 if (old->release_fb)
6611 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6612 goto fail;
79e53945 6613 }
7173188d 6614
79e53945 6615 /* let the connector get through one full cycle before testing */
9d0498a2 6616 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6617
7173188d 6618 return true;
24218aac
DV		 6619fail:
6620 connector->encoder = NULL;
6621 encoder->crtc = NULL;
24218aac 6622 return false;
79e53945
JB		 6623}
6624
d2434ab7 6625void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6626 struct intel_load_detect_pipe *old)
79e53945 6627{
d2434ab7
DV		 6628 struct intel_encoder *intel_encoder =
6629 intel_attached_encoder(connector);
4ef69c7a 6630 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6631
d2dff872
CW		 6632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6633 connector->base.id, drm_get_connector_name(connector),
6634 encoder->base.id, drm_get_encoder_name(encoder));
6635
8261b191 6636 if (old->load_detect_temp) {
fc303101
DV		 6637 struct drm_crtc *crtc = encoder->crtc;
6638
6639 to_intel_connector(connector)->new_encoder = NULL;
6640 intel_encoder->new_crtc = NULL;
6641 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6642
6643 if (old->release_fb)
6644 old->release_fb->funcs->destroy(old->release_fb);
6645
0622a53c 6646 return;
79e53945
JB		 6647 }
6648
c751ce4f 6649 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6650 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6651 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6652}
6653
6654/* Returns the clock of the currently programmed mode of the given pipe. */
6655static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6656{
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659 int pipe = intel_crtc->pipe;
548f245b 6660 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6661 u32 fp;
6662 intel_clock_t clock;
6663
6664 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6665 fp = I915_READ(FP0(pipe));
79e53945 6666 else
39adb7a5 6667 fp = I915_READ(FP1(pipe));
79e53945
JB		 6668
6669 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6670 if (IS_PINEVIEW(dev)) {
6671 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6672 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6673 } else {
6674 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6675 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6676 }
6677
a6c45cf0 6678 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6679 if (IS_PINEVIEW(dev))
6680 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6681 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6682 else
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6684 DPLL_FPA01_P1_POST_DIV_SHIFT);
6685
6686 switch (dpll & DPLL_MODE_MASK) {
6687 case DPLLB_MODE_DAC_SERIAL:
6688 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6689 5 : 10;
6690 break;
6691 case DPLLB_MODE_LVDS:
6692 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6693 7 : 14;
6694 break;
6695 default:
28c97730 6696 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6697 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6698 return 0;
6699 }
6700
6701 /* XXX: Handle the 100Mhz refclk */
2177832f 6702 intel_clock(dev, 96000, &clock);
79e53945
JB		 6703 } else {
6704 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6705
6706 if (is_lvds) {
6707 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6708 DPLL_FPA01_P1_POST_DIV_SHIFT);
6709 clock.p2 = 14;
6710
6711 if ((dpll & PLL_REF_INPUT_MASK) ==
6712 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6713 /* XXX: might not be 66MHz */
2177832f 6714 intel_clock(dev, 66000, &clock);
79e53945 6715 } else
2177832f 6716 intel_clock(dev, 48000, &clock);
79e53945
JB		 6717 } else {
6718 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6719 clock.p1 = 2;
6720 else {
6721 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6722 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6723 }
6724 if (dpll & PLL_P2_DIVIDE_BY_4)
6725 clock.p2 = 4;
6726 else
6727 clock.p2 = 2;
6728
2177832f 6729 intel_clock(dev, 48000, &clock);
79e53945
JB		 6730 }
6731 }
6732
6733 /* XXX: It would be nice to validate the clocks, but we can't reuse
6734 * i830PllIsValid() because it relies on the xf86_config connector
6735 * configuration being accurate, which it isn't necessarily.
6736 */
6737
6738 return clock.dot;
6739}
6740
6741/** Returns the currently programmed mode of the given pipe. */
6742struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6743 struct drm_crtc *crtc)
6744{
548f245b 6745 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6747 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6748 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6749 int htot = I915_READ(HTOTAL(cpu_transcoder));
6750 int hsync = I915_READ(HSYNC(cpu_transcoder));
6751 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6752 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6753
6754 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6755 if (!mode)
6756 return NULL;
6757
6758 mode->clock = intel_crtc_clock_get(dev, crtc);
6759 mode->hdisplay = (htot & 0xffff) + 1;
6760 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6761 mode->hsync_start = (hsync & 0xffff) + 1;
6762 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6763 mode->vdisplay = (vtot & 0xffff) + 1;
6764 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6765 mode->vsync_start = (vsync & 0xffff) + 1;
6766 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6767
6768 drm_mode_set_name(mode);
79e53945
JB		 6769
6770 return mode;
6771}
6772
3dec0095 6773static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6774{
6775 struct drm_device *dev = crtc->dev;
6776 drm_i915_private_t *dev_priv = dev->dev_private;
6777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6779 int dpll_reg = DPLL(pipe);
6780 int dpll;
652c393a 6781
bad720ff 6782 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6783 return;
6784
6785 if (!dev_priv->lvds_downclock_avail)
6786 return;
6787
dbdc6479 6788 dpll = I915_READ(dpll_reg);
652c393a 6789 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6790 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6791
8ac5a6d5 6792 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6793
6794 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6795 I915_WRITE(dpll_reg, dpll);
9d0498a2 6796 intel_wait_for_vblank(dev, pipe);
dbdc6479 6797
652c393a
JB		 6798 dpll = I915_READ(dpll_reg);
6799 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6800 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6801 }
652c393a
JB		 6802}
6803
6804static void intel_decrease_pllclock(struct drm_crtc *crtc)
6805{
6806 struct drm_device *dev = crtc->dev;
6807 drm_i915_private_t *dev_priv = dev->dev_private;
6808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6809
bad720ff 6810 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6811 return;
6812
6813 if (!dev_priv->lvds_downclock_avail)
6814 return;
6815
6816 /*
6817 * Since this is called by a timer, we should never get here in
6818 * the manual case.
6819 */
6820 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6821 int pipe = intel_crtc->pipe;
6822 int dpll_reg = DPLL(pipe);
6823 int dpll;
f6e5b160 6824
44d98a61 6825 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6826
8ac5a6d5 6827 assert_panel_unlocked(dev_priv, pipe);
652c393a 6828
dc257cf1 6829 dpll = I915_READ(dpll_reg);
652c393a
JB		 6830 dpll |= DISPLAY_RATE_SELECT_FPA1;
6831 I915_WRITE(dpll_reg, dpll);
9d0498a2 6832 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6833 dpll = I915_READ(dpll_reg);
6834 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6835 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6836 }
6837
6838}
6839
f047e395
CW		 6840void intel_mark_busy(struct drm_device *dev)
6841{
f047e395
CW		 6842 i915_update_gfx_val(dev->dev_private);
6843}
6844
6845void intel_mark_idle(struct drm_device *dev)
652c393a 6846{
f047e395
CW		 6847}
6848
6849void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6850{
6851 struct drm_device *dev = obj->base.dev;
652c393a 6852 struct drm_crtc *crtc;
652c393a
JB		 6853
6854 if (!i915_powersave)
6855 return;
6856
652c393a 6857 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6858 if (!crtc->fb)
6859 continue;
6860
f047e395
CW		 6861 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6862 intel_increase_pllclock(crtc);
652c393a 6863 }
652c393a
JB		 6864}
6865
f047e395 6866void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6867{
f047e395
CW		 6868 struct drm_device *dev = obj->base.dev;
6869 struct drm_crtc *crtc;
652c393a 6870
f047e395 6871 if (!i915_powersave)
acb87dfb
CW		 6872 return;
6873
652c393a
JB		 6874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6875 if (!crtc->fb)
6876 continue;
6877
f047e395
CW		 6878 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6879 intel_decrease_pllclock(crtc);
652c393a
JB		 6880 }
6881}
6882
79e53945
JB		 6883static void intel_crtc_destroy(struct drm_crtc *crtc)
6884{
6885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6886 struct drm_device *dev = crtc->dev;
6887 struct intel_unpin_work *work;
6888 unsigned long flags;
6889
6890 spin_lock_irqsave(&dev->event_lock, flags);
6891 work = intel_crtc->unpin_work;
6892 intel_crtc->unpin_work = NULL;
6893 spin_unlock_irqrestore(&dev->event_lock, flags);
6894
6895 if (work) {
6896 cancel_work_sync(&work->work);
6897 kfree(work);
6898 }
79e53945
JB		 6899
6900 drm_crtc_cleanup(crtc);
67e77c5a 6901
79e53945
JB		 6902 kfree(intel_crtc);
6903}
6904
6b95a207
KH		 6905static void intel_unpin_work_fn(struct work_struct *__work)
6906{
6907 struct intel_unpin_work *work =
6908 container_of(__work, struct intel_unpin_work, work);
6909
6910 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6911 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6912 drm_gem_object_unreference(&work->pending_flip_obj->base);
6913 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6914
7782de3b 6915 intel_update_fbc(work->dev);
6b95a207
KH		 6916 mutex_unlock(&work->dev->struct_mutex);
6917 kfree(work);
6918}
6919
1afe3e9d 6920static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6921 struct drm_crtc *crtc)
6b95a207
KH		 6922{
6923 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6925 struct intel_unpin_work *work;
05394f39 6926 struct drm_i915_gem_object *obj;
6b95a207 6927 struct drm_pending_vblank_event *e;
95cb1b02 6928 struct timeval tvbl;
6b95a207
KH		 6929 unsigned long flags;
6930
6931 /* Ignore early vblank irqs */
6932 if (intel_crtc == NULL)
6933 return;
6934
6935 spin_lock_irqsave(&dev->event_lock, flags);
6936 work = intel_crtc->unpin_work;
6937 if (work == NULL || !work->pending) {
6938 spin_unlock_irqrestore(&dev->event_lock, flags);
6939 return;
6940 }
6941
6942 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6943
6944 if (work->event) {
6945 e = work->event;
49b14a5c 6946 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6947
49b14a5c
MK		 6948 e->event.tv_sec = tvbl.tv_sec;
6949 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6950
6b95a207
KH		 6951 list_add_tail(&e->base.link,
6952 &e->base.file_priv->event_list);
6953 wake_up_interruptible(&e->base.file_priv->event_wait);
6954 }
6955
0af7e4df
MK		 6956 drm_vblank_put(dev, intel_crtc->pipe);
6957
6b95a207
KH		 6958 spin_unlock_irqrestore(&dev->event_lock, flags);
6959
05394f39 6960 obj = work->old_fb_obj;
d9e86c0e 6961
e59f2bac 6962 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6963 &obj->pending_flip.counter);
d9e86c0e 6964
5bb61643 6965 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6966 schedule_work(&work->work);
e5510fac
JB		 6967
6968 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6969}
6970
1afe3e9d
JB		 6971void intel_finish_page_flip(struct drm_device *dev, int pipe)
6972{
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6975
49b14a5c 6976 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6977}
6978
6979void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6980{
6981 drm_i915_private_t *dev_priv = dev->dev_private;
6982 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6983
49b14a5c 6984 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6985}
6986
6b95a207
KH		 6987void intel_prepare_page_flip(struct drm_device *dev, int plane)
6988{
6989 drm_i915_private_t *dev_priv = dev->dev_private;
6990 struct intel_crtc *intel_crtc =
6991 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6992 unsigned long flags;
6993
6994 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6995 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6996 if ((++intel_crtc->unpin_work->pending) > 1)
6997 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6998 } else {
6999 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7000 }
6b95a207
KH		 7001 spin_unlock_irqrestore(&dev->event_lock, flags);
7002}
7003
8c9f3aaf
JB		 7004static int intel_gen2_queue_flip(struct drm_device *dev,
7005 struct drm_crtc *crtc,
7006 struct drm_framebuffer *fb,
7007 struct drm_i915_gem_object *obj)
7008{
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7011 u32 flip_mask;
6d90c952 7012 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7013 int ret;
7014
6d90c952 7015 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7016 if (ret)
83d4092b 7017 goto err;
8c9f3aaf 7018
6d90c952 7019 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7020 if (ret)
83d4092b 7021 goto err_unpin;
8c9f3aaf
JB		 7022
7023 /* Can't queue multiple flips, so wait for the previous
7024 * one to finish before executing the next.
7025 */
7026 if (intel_crtc->plane)
7027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7028 else
7029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7030 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7031 intel_ring_emit(ring, MI_NOOP);
7032 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7033 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7034 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7035 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7036 intel_ring_emit(ring, 0); /* aux display base address, unused */
7037 intel_ring_advance(ring);
83d4092b
CW		 7038 return 0;
7039
7040err_unpin:
7041 intel_unpin_fb_obj(obj);
7042err:
8c9f3aaf
JB		 7043 return ret;
7044}
7045
7046static int intel_gen3_queue_flip(struct drm_device *dev,
7047 struct drm_crtc *crtc,
7048 struct drm_framebuffer *fb,
7049 struct drm_i915_gem_object *obj)
7050{
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7053 u32 flip_mask;
6d90c952 7054 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7055 int ret;
7056
6d90c952 7057 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7058 if (ret)
83d4092b 7059 goto err;
8c9f3aaf 7060
6d90c952 7061 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7062 if (ret)
83d4092b 7063 goto err_unpin;
8c9f3aaf
JB		 7064
7065 if (intel_crtc->plane)
7066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7067 else
7068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7069 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7070 intel_ring_emit(ring, MI_NOOP);
7071 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7073 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7074 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7075 intel_ring_emit(ring, MI_NOOP);
7076
7077 intel_ring_advance(ring);
83d4092b
CW		 7078 return 0;
7079
7080err_unpin:
7081 intel_unpin_fb_obj(obj);
7082err:
8c9f3aaf
JB		 7083 return ret;
7084}
7085
7086static int intel_gen4_queue_flip(struct drm_device *dev,
7087 struct drm_crtc *crtc,
7088 struct drm_framebuffer *fb,
7089 struct drm_i915_gem_object *obj)
7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7093 uint32_t pf, pipesrc;
6d90c952 7094 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7095 int ret;
7096
6d90c952 7097 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7098 if (ret)
83d4092b 7099 goto err;
8c9f3aaf 7100
6d90c952 7101 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7102 if (ret)
83d4092b 7103 goto err_unpin;
8c9f3aaf
JB		 7104
7105 /* i965+ uses the linear or tiled offsets from the
7106 * Display Registers (which do not change across a page-flip)
7107 * so we need only reprogram the base address.
7108 */
6d90c952
DV		 7109 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7110 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7111 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7112 intel_ring_emit(ring,
7113 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7114 obj->tiling_mode);
8c9f3aaf
JB		 7115
7116 /* XXX Enabling the panel-fitter across page-flip is so far
7117 * untested on non-native modes, so ignore it for now.
7118 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7119 */
7120 pf = 0;
7121 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7122 intel_ring_emit(ring, pf | pipesrc);
7123 intel_ring_advance(ring);
83d4092b
CW		 7124 return 0;
7125
7126err_unpin:
7127 intel_unpin_fb_obj(obj);
7128err:
8c9f3aaf
JB		 7129 return ret;
7130}
7131
7132static int intel_gen6_queue_flip(struct drm_device *dev,
7133 struct drm_crtc *crtc,
7134 struct drm_framebuffer *fb,
7135 struct drm_i915_gem_object *obj)
7136{
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7139 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7140 uint32_t pf, pipesrc;
7141 int ret;
7142
6d90c952 7143 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7144 if (ret)
83d4092b 7145 goto err;
8c9f3aaf 7146
6d90c952 7147 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7148 if (ret)
83d4092b 7149 goto err_unpin;
8c9f3aaf 7150
6d90c952
DV		 7151 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7152 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7153 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7154 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7155
dc257cf1
DV		 7156 /* Contrary to the suggestions in the documentation,
7157 * "Enable Panel Fitter" does not seem to be required when page
7158 * flipping with a non-native mode, and worse causes a normal
7159 * modeset to fail.
7160 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7161 */
7162 pf = 0;
8c9f3aaf 7163 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7164 intel_ring_emit(ring, pf | pipesrc);
7165 intel_ring_advance(ring);
83d4092b
CW		 7166 return 0;
7167
7168err_unpin:
7169 intel_unpin_fb_obj(obj);
7170err:
8c9f3aaf
JB		 7171 return ret;
7172}
7173
7c9017e5
JB		 7174/*
7175 * On gen7 we currently use the blit ring because (in early silicon at least)
7176 * the render ring doesn't give us interrpts for page flip completion, which
7177 * means clients will hang after the first flip is queued. Fortunately the
7178 * blit ring generates interrupts properly, so use it instead.
7179 */
7180static int intel_gen7_queue_flip(struct drm_device *dev,
7181 struct drm_crtc *crtc,
7182 struct drm_framebuffer *fb,
7183 struct drm_i915_gem_object *obj)
7184{
7185 struct drm_i915_private *dev_priv = dev->dev_private;
7186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7187 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7188 uint32_t plane_bit = 0;
7c9017e5
JB		 7189 int ret;
7190
7191 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7192 if (ret)
83d4092b 7193 goto err;
7c9017e5 7194
cb05d8de
DV		 7195 switch(intel_crtc->plane) {
7196 case PLANE_A:
7197 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7198 break;
7199 case PLANE_B:
7200 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7201 break;
7202 case PLANE_C:
7203 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7204 break;
7205 default:
7206 WARN_ONCE(1, "unknown plane in flip command\n");
7207 ret = -ENODEV;
ab3951eb 7208 goto err_unpin;
cb05d8de
DV		 7209 }
7210
7c9017e5
JB		 7211 ret = intel_ring_begin(ring, 4);
7212 if (ret)
83d4092b 7213 goto err_unpin;
7c9017e5 7214
cb05d8de 7215 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7216 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7217 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7218 intel_ring_emit(ring, (MI_NOOP));
7219 intel_ring_advance(ring);
83d4092b
CW		 7220 return 0;
7221
7222err_unpin:
7223 intel_unpin_fb_obj(obj);
7224err:
7c9017e5
JB		 7225 return ret;
7226}
7227
8c9f3aaf
JB		 7228static int intel_default_queue_flip(struct drm_device *dev,
7229 struct drm_crtc *crtc,
7230 struct drm_framebuffer *fb,
7231 struct drm_i915_gem_object *obj)
7232{
7233 return -ENODEV;
7234}
7235
6b95a207
KH		 7236static int intel_crtc_page_flip(struct drm_crtc *crtc,
7237 struct drm_framebuffer *fb,
7238 struct drm_pending_vblank_event *event)
7239{
7240 struct drm_device *dev = crtc->dev;
7241 struct drm_i915_private *dev_priv = dev->dev_private;
7242 struct intel_framebuffer *intel_fb;
05394f39 7243 struct drm_i915_gem_object *obj;
6b95a207
KH		 7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245 struct intel_unpin_work *work;
8c9f3aaf 7246 unsigned long flags;
52e68630 7247 int ret;
6b95a207 7248
e6a595d2
VS		 7249 /* Can't change pixel format via MI display flips. */
7250 if (fb->pixel_format != crtc->fb->pixel_format)
7251 return -EINVAL;
7252
7253 /*
7254 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7255 * Note that pitch changes could also affect these register.
7256 */
7257 if (INTEL_INFO(dev)->gen > 3 &&
7258 (fb->offsets[0] != crtc->fb->offsets[0] ||
7259 fb->pitches[0] != crtc->fb->pitches[0]))
7260 return -EINVAL;
7261
6b95a207
KH		 7262 work = kzalloc(sizeof *work, GFP_KERNEL);
7263 if (work == NULL)
7264 return -ENOMEM;
7265
6b95a207
KH		 7266 work->event = event;
7267 work->dev = crtc->dev;
7268 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7269 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7270 INIT_WORK(&work->work, intel_unpin_work_fn);
7271
7317c75e
JB		 7272 ret = drm_vblank_get(dev, intel_crtc->pipe);
7273 if (ret)
7274 goto free_work;
7275
6b95a207
KH		 7276 /* We borrow the event spin lock for protecting unpin_work */
7277 spin_lock_irqsave(&dev->event_lock, flags);
7278 if (intel_crtc->unpin_work) {
7279 spin_unlock_irqrestore(&dev->event_lock, flags);
7280 kfree(work);
7317c75e 7281 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7282
7283 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7284 return -EBUSY;
7285 }
7286 intel_crtc->unpin_work = work;
7287 spin_unlock_irqrestore(&dev->event_lock, flags);
7288
7289 intel_fb = to_intel_framebuffer(fb);
7290 obj = intel_fb->obj;
7291
79158103
CW		 7292 ret = i915_mutex_lock_interruptible(dev);
7293 if (ret)
7294 goto cleanup;
6b95a207 7295
75dfca80 7296 /* Reference the objects for the scheduled work. */
05394f39
CW		 7297 drm_gem_object_reference(&work->old_fb_obj->base);
7298 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7299
7300 crtc->fb = fb;
96b099fd 7301
e1f99ce6 7302 work->pending_flip_obj = obj;
e1f99ce6 7303
4e5359cd
SF		 7304 work->enable_stall_check = true;
7305
e1f99ce6
CW		 7306 /* Block clients from rendering to the new back buffer until
7307 * the flip occurs and the object is no longer visible.
7308 */
05394f39 7309 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7310
8c9f3aaf
JB		 7311 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7312 if (ret)
7313 goto cleanup_pending;
6b95a207 7314
7782de3b 7315 intel_disable_fbc(dev);
f047e395 7316 intel_mark_fb_busy(obj);
6b95a207
KH		 7317 mutex_unlock(&dev->struct_mutex);
7318
e5510fac
JB		 7319 trace_i915_flip_request(intel_crtc->plane, obj);
7320
6b95a207 7321 return 0;
96b099fd 7322
8c9f3aaf
JB		 7323cleanup_pending:
7324 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7325 drm_gem_object_unreference(&work->old_fb_obj->base);
7326 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7327 mutex_unlock(&dev->struct_mutex);
7328
79158103 7329cleanup:
96b099fd
CW		 7330 spin_lock_irqsave(&dev->event_lock, flags);
7331 intel_crtc->unpin_work = NULL;
7332 spin_unlock_irqrestore(&dev->event_lock, flags);
7333
7317c75e
JB		 7334 drm_vblank_put(dev, intel_crtc->pipe);
7335free_work:
96b099fd
CW		 7336 kfree(work);
7337
7338 return ret;
6b95a207
KH		 7339}
7340
f6e5b160 7341static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7342 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7343 .load_lut = intel_crtc_load_lut,
976f8a20 7344 .disable = intel_crtc_noop,
f6e5b160
CW		 7345};
7346
6ed0f796 7347bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7348{
6ed0f796
DV		 7349 struct intel_encoder *other_encoder;
7350 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7351
6ed0f796
DV		 7352 if (WARN_ON(!crtc))
7353 return false;
7354
7355 list_for_each_entry(other_encoder,
7356 &crtc->dev->mode_config.encoder_list,
7357 base.head) {
7358
7359 if (&other_encoder->new_crtc->base != crtc ||
7360 encoder == other_encoder)
7361 continue;
7362 else
7363 return true;
f47166d2
CW		 7364 }
7365
6ed0f796
DV		 7366 return false;
7367}
47f1c6c9 7368
50f56119
DV		 7369static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7370 struct drm_crtc *crtc)
7371{
7372 struct drm_device *dev;
7373 struct drm_crtc *tmp;
7374 int crtc_mask = 1;
47f1c6c9 7375
50f56119 7376 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7377
50f56119 7378 dev = crtc->dev;
47f1c6c9 7379
50f56119
DV		 7380 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7381 if (tmp == crtc)
7382 break;
7383 crtc_mask <<= 1;
7384 }
47f1c6c9 7385
50f56119
DV		 7386 if (encoder->possible_crtcs & crtc_mask)
7387 return true;
7388 return false;
47f1c6c9 7389}
79e53945 7390
9a935856
DV		 7391/**
7392 * intel_modeset_update_staged_output_state
7393 *
7394 * Updates the staged output configuration state, e.g. after we've read out the
7395 * current hw state.
7396 */
7397static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7398{
9a935856
DV		 7399 struct intel_encoder *encoder;
7400 struct intel_connector *connector;
f6e5b160 7401
9a935856
DV		 7402 list_for_each_entry(connector, &dev->mode_config.connector_list,
7403 base.head) {
7404 connector->new_encoder =
7405 to_intel_encoder(connector->base.encoder);
7406 }
f6e5b160 7407
9a935856
DV		 7408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7409 base.head) {
7410 encoder->new_crtc =
7411 to_intel_crtc(encoder->base.crtc);
7412 }
f6e5b160
CW		 7413}
7414
9a935856
DV		 7415/**
7416 * intel_modeset_commit_output_state
7417 *
7418 * This function copies the stage display pipe configuration to the real one.
7419 */
7420static void intel_modeset_commit_output_state(struct drm_device *dev)
7421{
7422 struct intel_encoder *encoder;
7423 struct intel_connector *connector;
f6e5b160 7424
9a935856
DV		 7425 list_for_each_entry(connector, &dev->mode_config.connector_list,
7426 base.head) {
7427 connector->base.encoder = &connector->new_encoder->base;
7428 }
f6e5b160 7429
9a935856
DV		 7430 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7431 base.head) {
7432 encoder->base.crtc = &encoder->new_crtc->base;
7433 }
7434}
7435
7758a113
DV		 7436static struct drm_display_mode *
7437intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7438 struct drm_display_mode *mode)
ee7b9f93 7439{
7758a113
DV		 7440 struct drm_device *dev = crtc->dev;
7441 struct drm_display_mode *adjusted_mode;
7442 struct drm_encoder_helper_funcs *encoder_funcs;
7443 struct intel_encoder *encoder;
ee7b9f93 7444
7758a113
DV		 7445 adjusted_mode = drm_mode_duplicate(dev, mode);
7446 if (!adjusted_mode)
7447 return ERR_PTR(-ENOMEM);
7448
7449 /* Pass our mode to the connectors and the CRTC to give them a chance to
7450 * adjust it according to limitations or connector properties, and also
7451 * a chance to reject the mode entirely.
7452 */
7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7454 base.head) {
7455
7456 if (&encoder->new_crtc->base != crtc)
7457 continue;
7458 encoder_funcs = encoder->base.helper_private;
7459 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7460 adjusted_mode))) {
7461 DRM_DEBUG_KMS("Encoder fixup failed\n");
7462 goto fail;
7463 }
ee7b9f93
JB		 7464 }
7465
7758a113
DV		 7466 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7467 DRM_DEBUG_KMS("CRTC fixup failed\n");
7468 goto fail;
ee7b9f93 7469 }
7758a113
DV		 7470 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7471
7472 return adjusted_mode;
7473fail:
7474 drm_mode_destroy(dev, adjusted_mode);
7475 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7476}
7477
e2e1ed41
DV		 7478/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7479 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7480static void
7481intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7482 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7483{
7484 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7485 struct drm_device *dev = crtc->dev;
7486 struct intel_encoder *encoder;
7487 struct intel_connector *connector;
7488 struct drm_crtc *tmp_crtc;
79e53945 7489
e2e1ed41 7490 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7491
e2e1ed41
DV		 7492 /* Check which crtcs have changed outputs connected to them, these need
7493 * to be part of the prepare_pipes mask. We don't (yet) support global
7494 * modeset across multiple crtcs, so modeset_pipes will only have one
7495 * bit set at most. */
7496 list_for_each_entry(connector, &dev->mode_config.connector_list,
7497 base.head) {
7498 if (connector->base.encoder == &connector->new_encoder->base)
7499 continue;
79e53945 7500
e2e1ed41
DV		 7501 if (connector->base.encoder) {
7502 tmp_crtc = connector->base.encoder->crtc;
7503
7504 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7505 }
7506
7507 if (connector->new_encoder)
7508 *prepare_pipes |=
7509 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7510 }
7511
e2e1ed41
DV		 7512 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7513 base.head) {
7514 if (encoder->base.crtc == &encoder->new_crtc->base)
7515 continue;
7516
7517 if (encoder->base.crtc) {
7518 tmp_crtc = encoder->base.crtc;
7519
7520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7521 }
7522
7523 if (encoder->new_crtc)
7524 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7525 }
7526
e2e1ed41
DV		 7527 /* Check for any pipes that will be fully disabled ... */
7528 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7529 base.head) {
7530 bool used = false;
22fd0fab 7531
e2e1ed41
DV		 7532 /* Don't try to disable disabled crtcs. */
7533 if (!intel_crtc->base.enabled)
7534 continue;
7e7d76c3 7535
e2e1ed41
DV		 7536 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7537 base.head) {
7538 if (encoder->new_crtc == intel_crtc)
7539 used = true;
7540 }
7541
7542 if (!used)
7543 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7544 }
7545
e2e1ed41
DV		 7546
7547 /* set_mode is also used to update properties on life display pipes. */
7548 intel_crtc = to_intel_crtc(crtc);
7549 if (crtc->enabled)
7550 *prepare_pipes |= 1 << intel_crtc->pipe;
7551
7552 /* We only support modeset on one single crtc, hence we need to do that
7553 * only for the passed in crtc iff we change anything else than just
7554 * disable crtcs.
7555 *
7556 * This is actually not true, to be fully compatible with the old crtc
7557 * helper we automatically disable _any_ output (i.e. doesn't need to be
7558 * connected to the crtc we're modesetting on) if it's disconnected.
7559 * Which is a rather nutty api (since changed the output configuration
7560 * without userspace's explicit request can lead to confusion), but
7561 * alas. Hence we currently need to modeset on all pipes we prepare. */
7562 if (*prepare_pipes)
7563 *modeset_pipes = *prepare_pipes;
7564
7565 /* ... and mask these out. */
7566 *modeset_pipes &= ~(*disable_pipes);
7567 *prepare_pipes &= ~(*disable_pipes);
7568}
7569
ea9d758d
DV		 7570static bool intel_crtc_in_use(struct drm_crtc *crtc)
7571{
7572 struct drm_encoder *encoder;
7573 struct drm_device *dev = crtc->dev;
7574
7575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7576 if (encoder->crtc == crtc)
7577 return true;
7578
7579 return false;
7580}
7581
7582static void
7583intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7584{
7585 struct intel_encoder *intel_encoder;
7586 struct intel_crtc *intel_crtc;
7587 struct drm_connector *connector;
7588
7589 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7590 base.head) {
7591 if (!intel_encoder->base.crtc)
7592 continue;
7593
7594 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7595
7596 if (prepare_pipes & (1 << intel_crtc->pipe))
7597 intel_encoder->connectors_active = false;
7598 }
7599
7600 intel_modeset_commit_output_state(dev);
7601
7602 /* Update computed state. */
7603 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7604 base.head) {
7605 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7606 }
7607
7608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7609 if (!connector->encoder || !connector->encoder->crtc)
7610 continue;
7611
7612 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7613
7614 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7615 struct drm_property *dpms_property =
7616 dev->mode_config.dpms_property;
7617
ea9d758d 7618 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7619 drm_connector_property_set_value(connector,
7620 dpms_property,
7621 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7622
7623 intel_encoder = to_intel_encoder(connector->encoder);
7624 intel_encoder->connectors_active = true;
7625 }
7626 }
7627
7628}
7629
25c5b266
DV		 7630#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7631 list_for_each_entry((intel_crtc), \
7632 &(dev)->mode_config.crtc_list, \
7633 base.head) \
7634 if (mask & (1 <<(intel_crtc)->pipe)) \
7635
b980514c 7636void
8af6cf88
DV		 7637intel_modeset_check_state(struct drm_device *dev)
7638{
7639 struct intel_crtc *crtc;
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
7642
7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 base.head) {
7645 /* This also checks the encoder/connector hw state with the
7646 * ->get_hw_state callbacks. */
7647 intel_connector_check_state(connector);
7648
7649 WARN(&connector->new_encoder->base != connector->base.encoder,
7650 "connector's staged encoder doesn't match current encoder\n");
7651 }
7652
7653 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7654 base.head) {
7655 bool enabled = false;
7656 bool active = false;
7657 enum pipe pipe, tracked_pipe;
7658
7659 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7660 encoder->base.base.id,
7661 drm_get_encoder_name(&encoder->base));
7662
7663 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7664 "encoder's stage crtc doesn't match current crtc\n");
7665 WARN(encoder->connectors_active && !encoder->base.crtc,
7666 "encoder's active_connectors set, but no crtc\n");
7667
7668 list_for_each_entry(connector, &dev->mode_config.connector_list,
7669 base.head) {
7670 if (connector->base.encoder != &encoder->base)
7671 continue;
7672 enabled = true;
7673 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7674 active = true;
7675 }
7676 WARN(!!encoder->base.crtc != enabled,
7677 "encoder's enabled state mismatch "
7678 "(expected %i, found %i)\n",
7679 !!encoder->base.crtc, enabled);
7680 WARN(active && !encoder->base.crtc,
7681 "active encoder with no crtc\n");
7682
7683 WARN(encoder->connectors_active != active,
7684 "encoder's computed active state doesn't match tracked active state "
7685 "(expected %i, found %i)\n", active, encoder->connectors_active);
7686
7687 active = encoder->get_hw_state(encoder, &pipe);
7688 WARN(active != encoder->connectors_active,
7689 "encoder's hw state doesn't match sw tracking "
7690 "(expected %i, found %i)\n",
7691 encoder->connectors_active, active);
7692
7693 if (!encoder->base.crtc)
7694 continue;
7695
7696 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7697 WARN(active && pipe != tracked_pipe,
7698 "active encoder's pipe doesn't match"
7699 "(expected %i, found %i)\n",
7700 tracked_pipe, pipe);
7701
7702 }
7703
7704 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7705 base.head) {
7706 bool enabled = false;
7707 bool active = false;
7708
7709 DRM_DEBUG_KMS("[CRTC:%d]\n",
7710 crtc->base.base.id);
7711
7712 WARN(crtc->active && !crtc->base.enabled,
7713 "active crtc, but not enabled in sw tracking\n");
7714
7715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7716 base.head) {
7717 if (encoder->base.crtc != &crtc->base)
7718 continue;
7719 enabled = true;
7720 if (encoder->connectors_active)
7721 active = true;
7722 }
7723 WARN(active != crtc->active,
7724 "crtc's computed active state doesn't match tracked active state "
7725 "(expected %i, found %i)\n", active, crtc->active);
7726 WARN(enabled != crtc->base.enabled,
7727 "crtc's computed enabled state doesn't match tracked enabled state "
7728 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7729
7730 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7731 }
7732}
7733
a6778b3c
DV		 7734bool intel_set_mode(struct drm_crtc *crtc,
7735 struct drm_display_mode *mode,
94352cf9 7736 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7737{
7738 struct drm_device *dev = crtc->dev;
dbf2b54e 7739 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7740 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7741 struct intel_crtc *intel_crtc;
7742 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7743 bool ret = true;
7744
e2e1ed41 7745 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7746 &prepare_pipes, &disable_pipes);
7747
7748 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7749 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7750
976f8a20
DV		 7751 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7752 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7753
a6778b3c
DV		 7754 saved_hwmode = crtc->hwmode;
7755 saved_mode = crtc->mode;
a6778b3c 7756
25c5b266
DV		 7757 /* Hack: Because we don't (yet) support global modeset on multiple
7758 * crtcs, we don't keep track of the new mode for more than one crtc.
7759 * Hence simply check whether any bit is set in modeset_pipes in all the
7760 * pieces of code that are not yet converted to deal with mutliple crtcs
7761 * changing their mode at the same time. */
7762 adjusted_mode = NULL;
7763 if (modeset_pipes) {
7764 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7765 if (IS_ERR(adjusted_mode)) {
7766 return false;
7767 }
25c5b266 7768 }
a6778b3c 7769
ea9d758d
DV		 7770 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7771 if (intel_crtc->base.enabled)
7772 dev_priv->display.crtc_disable(&intel_crtc->base);
7773 }
a6778b3c 7774
6c4c86f5
DV		 7775 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7776 * to set it here already despite that we pass it down the callchain.
7777 */
7778 if (modeset_pipes)
25c5b266 7779 crtc->mode = *mode;
7758a113 7780
ea9d758d
DV		 7781 /* Only after disabling all output pipelines that will be changed can we
7782 * update the the output configuration. */
7783 intel_modeset_update_state(dev, prepare_pipes);
7784
47fab737
DV		 7785 if (dev_priv->display.modeset_global_resources)
7786 dev_priv->display.modeset_global_resources(dev);
7787
a6778b3c
DV		 7788 /* Set up the DPLL and any encoders state that needs to adjust or depend
7789 * on the DPLL.
7790 */
25c5b266
DV		 7791 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7792 ret = !intel_crtc_mode_set(&intel_crtc->base,
7793 mode, adjusted_mode,
7794 x, y, fb);
7795 if (!ret)
7796 goto done;
a6778b3c
DV		 7797 }
7798
7799 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7800 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7801 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7802
25c5b266
DV		 7803 if (modeset_pipes) {
7804 /* Store real post-adjustment hardware mode. */
7805 crtc->hwmode = *adjusted_mode;
a6778b3c 7806
25c5b266
DV		 7807 /* Calculate and store various constants which
7808 * are later needed by vblank and swap-completion
7809 * timestamping. They are derived from true hwmode.
7810 */
7811 drm_calc_timestamping_constants(crtc);
7812 }
a6778b3c
DV		 7813
7814 /* FIXME: add subpixel order */
7815done:
7816 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7817 if (!ret && crtc->enabled) {
a6778b3c
DV		 7818 crtc->hwmode = saved_hwmode;
7819 crtc->mode = saved_mode;
8af6cf88
DV		 7820 } else {
7821 intel_modeset_check_state(dev);
a6778b3c
DV		 7822 }
7823
7824 return ret;
7825}
7826
25c5b266
DV		 7827#undef for_each_intel_crtc_masked
7828
d9e55608
DV		 7829static void intel_set_config_free(struct intel_set_config *config)
7830{
7831 if (!config)
7832 return;
7833
1aa4b628
DV		 7834 kfree(config->save_connector_encoders);
7835 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7836 kfree(config);
7837}
7838
85f9eb71
DV		 7839static int intel_set_config_save_state(struct drm_device *dev,
7840 struct intel_set_config *config)
7841{
85f9eb71
DV		 7842 struct drm_encoder *encoder;
7843 struct drm_connector *connector;
7844 int count;
7845
1aa4b628
DV		 7846 config->save_encoder_crtcs =
7847 kcalloc(dev->mode_config.num_encoder,
7848 sizeof(struct drm_crtc *), GFP_KERNEL);
7849 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7850 return -ENOMEM;
7851
1aa4b628
DV		 7852 config->save_connector_encoders =
7853 kcalloc(dev->mode_config.num_connector,
7854 sizeof(struct drm_encoder *), GFP_KERNEL);
7855 if (!config->save_connector_encoders)
85f9eb71
DV		 7856 return -ENOMEM;
7857
7858 /* Copy data. Note that driver private data is not affected.
7859 * Should anything bad happen only the expected state is
7860 * restored, not the drivers personal bookkeeping.
7861 */
85f9eb71
DV		 7862 count = 0;
7863 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7864 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7865 }
7866
7867 count = 0;
7868 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7869 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7870 }
7871
7872 return 0;
7873}
7874
7875static void intel_set_config_restore_state(struct drm_device *dev,
7876 struct intel_set_config *config)
7877{
9a935856
DV		 7878 struct intel_encoder *encoder;
7879 struct intel_connector *connector;
85f9eb71
DV		 7880 int count;
7881
85f9eb71 7882 count = 0;
9a935856
DV		 7883 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7884 encoder->new_crtc =
7885 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7886 }
7887
7888 count = 0;
9a935856
DV		 7889 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7890 connector->new_encoder =
7891 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7892 }
7893}
7894
5e2b584e
DV		 7895static void
7896intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7897 struct intel_set_config *config)
7898{
7899
7900 /* We should be able to check here if the fb has the same properties
7901 * and then just flip_or_move it */
7902 if (set->crtc->fb != set->fb) {
7903 /* If we have no fb then treat it as a full mode set */
7904 if (set->crtc->fb == NULL) {
7905 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7906 config->mode_changed = true;
7907 } else if (set->fb == NULL) {
7908 config->mode_changed = true;
7909 } else if (set->fb->depth != set->crtc->fb->depth) {
7910 config->mode_changed = true;
7911 } else if (set->fb->bits_per_pixel !=
7912 set->crtc->fb->bits_per_pixel) {
7913 config->mode_changed = true;
7914 } else
7915 config->fb_changed = true;
7916 }
7917
835c5873 7918 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7919 config->fb_changed = true;
7920
7921 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7922 DRM_DEBUG_KMS("modes are different, full mode set\n");
7923 drm_mode_debug_printmodeline(&set->crtc->mode);
7924 drm_mode_debug_printmodeline(set->mode);
7925 config->mode_changed = true;
7926 }
7927}
7928
2e431051 7929static int
9a935856
DV		 7930intel_modeset_stage_output_state(struct drm_device *dev,
7931 struct drm_mode_set *set,
7932 struct intel_set_config *config)
50f56119 7933{
85f9eb71 7934 struct drm_crtc *new_crtc;
9a935856
DV		 7935 struct intel_connector *connector;
7936 struct intel_encoder *encoder;
2e431051 7937 int count, ro;
50f56119 7938
9a935856
DV		 7939 /* The upper layers ensure that we either disabl a crtc or have a list
7940 * of connectors. For paranoia, double-check this. */
7941 WARN_ON(!set->fb && (set->num_connectors != 0));
7942 WARN_ON(set->fb && (set->num_connectors == 0));
7943
50f56119 7944 count = 0;
9a935856
DV		 7945 list_for_each_entry(connector, &dev->mode_config.connector_list,
7946 base.head) {
7947 /* Otherwise traverse passed in connector list and get encoders
7948 * for them. */
50f56119 7949 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7950 if (set->connectors[ro] == &connector->base) {
7951 connector->new_encoder = connector->encoder;
50f56119
DV		 7952 break;
7953 }
7954 }
7955
9a935856
DV		 7956 /* If we disable the crtc, disable all its connectors. Also, if
7957 * the connector is on the changing crtc but not on the new
7958 * connector list, disable it. */
7959 if ((!set->fb || ro == set->num_connectors) &&
7960 connector->base.encoder &&
7961 connector->base.encoder->crtc == set->crtc) {
7962 connector->new_encoder = NULL;
7963
7964 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7965 connector->base.base.id,
7966 drm_get_connector_name(&connector->base));
7967 }
7968
7969
7970 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7971 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7972 config->mode_changed = true;
50f56119 7973 }
9a935856
DV		 7974
7975 /* Disable all disconnected encoders. */
7976 if (connector->base.status == connector_status_disconnected)
7977 connector->new_encoder = NULL;
50f56119 7978 }
9a935856 7979 /* connector->new_encoder is now updated for all connectors. */
50f56119 7980
9a935856 7981 /* Update crtc of enabled connectors. */
50f56119 7982 count = 0;
9a935856
DV		 7983 list_for_each_entry(connector, &dev->mode_config.connector_list,
7984 base.head) {
7985 if (!connector->new_encoder)
50f56119
DV		 7986 continue;
7987
9a935856 7988 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7989
7990 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7991 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7992 new_crtc = set->crtc;
7993 }
7994
7995 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7996 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7997 new_crtc)) {
5e2b584e 7998 return -EINVAL;
50f56119 7999 }
9a935856
DV		 8000 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8001
8002 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8003 connector->base.base.id,
8004 drm_get_connector_name(&connector->base),
8005 new_crtc->base.id);
8006 }
8007
8008 /* Check for any encoders that needs to be disabled. */
8009 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8010 base.head) {
8011 list_for_each_entry(connector,
8012 &dev->mode_config.connector_list,
8013 base.head) {
8014 if (connector->new_encoder == encoder) {
8015 WARN_ON(!connector->new_encoder->new_crtc);
8016
8017 goto next_encoder;
8018 }
8019 }
8020 encoder->new_crtc = NULL;
8021next_encoder:
8022 /* Only now check for crtc changes so we don't miss encoders
8023 * that will be disabled. */
8024 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8025 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8026 config->mode_changed = true;
50f56119
DV		 8027 }
8028 }
9a935856 8029 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8030
2e431051
DV		 8031 return 0;
8032}
8033
8034static int intel_crtc_set_config(struct drm_mode_set *set)
8035{
8036 struct drm_device *dev;
2e431051
DV		 8037 struct drm_mode_set save_set;
8038 struct intel_set_config *config;
8039 int ret;
2e431051 8040
8d3e375e
DV		 8041 BUG_ON(!set);
8042 BUG_ON(!set->crtc);
8043 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8044
8045 if (!set->mode)
8046 set->fb = NULL;
8047
431e50f7
DV		 8048 /* The fb helper likes to play gross jokes with ->mode_set_config.
8049 * Unfortunately the crtc helper doesn't do much at all for this case,
8050 * so we have to cope with this madness until the fb helper is fixed up. */
8051 if (set->fb && set->num_connectors == 0)
8052 return 0;
8053
2e431051
DV		 8054 if (set->fb) {
8055 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8056 set->crtc->base.id, set->fb->base.id,
8057 (int)set->num_connectors, set->x, set->y);
8058 } else {
8059 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8060 }
8061
8062 dev = set->crtc->dev;
8063
8064 ret = -ENOMEM;
8065 config = kzalloc(sizeof(*config), GFP_KERNEL);
8066 if (!config)
8067 goto out_config;
8068
8069 ret = intel_set_config_save_state(dev, config);
8070 if (ret)
8071 goto out_config;
8072
8073 save_set.crtc = set->crtc;
8074 save_set.mode = &set->crtc->mode;
8075 save_set.x = set->crtc->x;
8076 save_set.y = set->crtc->y;
8077 save_set.fb = set->crtc->fb;
8078
8079 /* Compute whether we need a full modeset, only an fb base update or no
8080 * change at all. In the future we might also check whether only the
8081 * mode changed, e.g. for LVDS where we only change the panel fitter in
8082 * such cases. */
8083 intel_set_config_compute_mode_changes(set, config);
8084
9a935856 8085 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8086 if (ret)
8087 goto fail;
8088
5e2b584e 8089 if (config->mode_changed) {
87f1faa6 8090 if (set->mode) {
50f56119
DV		 8091 DRM_DEBUG_KMS("attempting to set mode from"
8092 " userspace\n");
8093 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8094 }
8095
8096 if (!intel_set_mode(set->crtc, set->mode,
8097 set->x, set->y, set->fb)) {
8098 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8099 set->crtc->base.id);
8100 ret = -EINVAL;
8101 goto fail;
8102 }
5e2b584e 8103 } else if (config->fb_changed) {
4f660f49 8104 ret = intel_pipe_set_base(set->crtc,
94352cf9 8105 set->x, set->y, set->fb);
50f56119
DV		 8106 }
8107
d9e55608
DV		 8108 intel_set_config_free(config);
8109
50f56119
DV		 8110 return 0;
8111
8112fail:
85f9eb71 8113 intel_set_config_restore_state(dev, config);
50f56119
DV		 8114
8115 /* Try to restore the config */
5e2b584e 8116 if (config->mode_changed &&
a6778b3c
DV		 8117 !intel_set_mode(save_set.crtc, save_set.mode,
8118 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8119 DRM_ERROR("failed to restore config after modeset failure\n");
8120
d9e55608
DV		 8121out_config:
8122 intel_set_config_free(config);
50f56119
DV		 8123 return ret;
8124}
8125
f6e5b160 8126static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8127 .cursor_set = intel_crtc_cursor_set,
8128 .cursor_move = intel_crtc_cursor_move,
8129 .gamma_set = intel_crtc_gamma_set,
50f56119 8130 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8131 .destroy = intel_crtc_destroy,
8132 .page_flip = intel_crtc_page_flip,
8133};
8134
79f689aa
PZ		 8135static void intel_cpu_pll_init(struct drm_device *dev)
8136{
8137 if (IS_HASWELL(dev))
8138 intel_ddi_pll_init(dev);
8139}
8140
ee7b9f93
JB		 8141static void intel_pch_pll_init(struct drm_device *dev)
8142{
8143 drm_i915_private_t *dev_priv = dev->dev_private;
8144 int i;
8145
8146 if (dev_priv->num_pch_pll == 0) {
8147 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8148 return;
8149 }
8150
8151 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8152 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8153 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8154 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8155 }
8156}
8157
b358d0a6 8158static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8159{
22fd0fab 8160 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8161 struct intel_crtc *intel_crtc;
8162 int i;
8163
8164 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8165 if (intel_crtc == NULL)
8166 return;
8167
8168 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8169
8170 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8171 for (i = 0; i < 256; i++) {
8172 intel_crtc->lut_r[i] = i;
8173 intel_crtc->lut_g[i] = i;
8174 intel_crtc->lut_b[i] = i;
8175 }
8176
80824003
JB		 8177 /* Swap pipes & planes for FBC on pre-965 */
8178 intel_crtc->pipe = pipe;
8179 intel_crtc->plane = pipe;
a5c961d1 8180 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8181 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8182 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8183 intel_crtc->plane = !pipe;
80824003
JB		 8184 }
8185
22fd0fab
JB		 8186 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8187 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8188 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8189 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8190
5a354204 8191 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8192
79e53945 8193 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8194}
8195
08d7b3d1 8196int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8197 struct drm_file *file)
08d7b3d1 8198{
08d7b3d1 8199 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8200 struct drm_mode_object *drmmode_obj;
8201 struct intel_crtc *crtc;
08d7b3d1 8202
1cff8f6b
DV		 8203 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8204 return -ENODEV;
08d7b3d1 8205
c05422d5
DV		 8206 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8207 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8208
c05422d5 8209 if (!drmmode_obj) {
08d7b3d1
CW		 8210 DRM_ERROR("no such CRTC id\n");
8211 return -EINVAL;
8212 }
8213
c05422d5
DV		 8214 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8215 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8216
c05422d5 8217 return 0;
08d7b3d1
CW		 8218}
8219
66a9278e 8220static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8221{
66a9278e
DV		 8222 struct drm_device *dev = encoder->base.dev;
8223 struct intel_encoder *source_encoder;
79e53945 8224 int index_mask = 0;
79e53945
JB		 8225 int entry = 0;
8226
66a9278e
DV		 8227 list_for_each_entry(source_encoder,
8228 &dev->mode_config.encoder_list, base.head) {
8229
8230 if (encoder == source_encoder)
79e53945 8231 index_mask |= (1 << entry);
66a9278e
DV		 8232
8233 /* Intel hw has only one MUX where enocoders could be cloned. */
8234 if (encoder->cloneable && source_encoder->cloneable)
8235 index_mask |= (1 << entry);
8236
79e53945
JB		 8237 entry++;
8238 }
4ef69c7a 8239
79e53945
JB		 8240 return index_mask;
8241}
8242
4d302442
CW		 8243static bool has_edp_a(struct drm_device *dev)
8244{
8245 struct drm_i915_private *dev_priv = dev->dev_private;
8246
8247 if (!IS_MOBILE(dev))
8248 return false;
8249
8250 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8251 return false;
8252
8253 if (IS_GEN5(dev) &&
8254 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8255 return false;
8256
8257 return true;
8258}
8259
79e53945
JB		 8260static void intel_setup_outputs(struct drm_device *dev)
8261{
725e30ad 8262 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8263 struct intel_encoder *encoder;
cb0953d7 8264 bool dpd_is_edp = false;
f3cfcba6 8265 bool has_lvds;
79e53945 8266
f3cfcba6 8267 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8268 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8269 /* disable the panel fitter on everything but LVDS */
8270 I915_WRITE(PFIT_CONTROL, 0);
8271 }
79e53945 8272
bad720ff 8273 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8274 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8275
4d302442 8276 if (has_edp_a(dev))
ab9d7c30 8277 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8278
cb0953d7 8279 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8280 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8281 }
8282
8283 intel_crt_init(dev);
8284
0e72a5b5
ED		 8285 if (IS_HASWELL(dev)) {
8286 int found;
8287
8288 /* Haswell uses DDI functions to detect digital outputs */
8289 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8290 /* DDI A only supports eDP */
8291 if (found)
8292 intel_ddi_init(dev, PORT_A);
8293
8294 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8295 * register */
8296 found = I915_READ(SFUSE_STRAP);
8297
8298 if (found & SFUSE_STRAP_DDIB_DETECTED)
8299 intel_ddi_init(dev, PORT_B);
8300 if (found & SFUSE_STRAP_DDIC_DETECTED)
8301 intel_ddi_init(dev, PORT_C);
8302 if (found & SFUSE_STRAP_DDID_DETECTED)
8303 intel_ddi_init(dev, PORT_D);
8304 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8305 int found;
8306
30ad48b7 8307 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8308 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8309 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8310 if (!found)
08d644ad 8311 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8312 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8313 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8314 }
8315
8316 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8317 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8318
b708a1d5 8319 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8320 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8321
5eb08b69 8322 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8323 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8324
cb0953d7 8325 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8326 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8327 } else if (IS_VALLEYVIEW(dev)) {
8328 int found;
8329
19c03924
GB		 8330 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8331 if (I915_READ(DP_C) & DP_DETECTED)
8332 intel_dp_init(dev, DP_C, PORT_C);
8333
4a87d65d
JB		 8334 if (I915_READ(SDVOB) & PORT_DETECTED) {
8335 /* SDVOB multiplex with HDMIB */
8336 found = intel_sdvo_init(dev, SDVOB, true);
8337 if (!found)
08d644ad 8338 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8339 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8340 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8341 }
8342
8343 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8344 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8345
103a196f 8346 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8347 bool found = false;
7d57382e 8348
725e30ad 8349 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8350 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8351 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8352 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8353 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8354 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8355 }
27185ae1 8356
b01f2c3a
JB		 8357 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8358 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8359 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8360 }
725e30ad 8361 }
13520b05
KH		 8362
8363 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8364
b01f2c3a
JB		 8365 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8366 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8367 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8368 }
27185ae1
ML		 8369
8370 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8371
b01f2c3a
JB		 8372 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8373 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8374 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8375 }
8376 if (SUPPORTS_INTEGRATED_DP(dev)) {
8377 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8378 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8379 }
725e30ad 8380 }
27185ae1 8381
b01f2c3a
JB		 8382 if (SUPPORTS_INTEGRATED_DP(dev) &&
8383 (I915_READ(DP_D) & DP_DETECTED)) {
8384 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8385 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8386 }
bad720ff 8387 } else if (IS_GEN2(dev))
79e53945
JB		 8388 intel_dvo_init(dev);
8389
103a196f 8390 if (SUPPORTS_TV(dev))
79e53945
JB		 8391 intel_tv_init(dev);
8392
4ef69c7a
CW		 8393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8394 encoder->base.possible_crtcs = encoder->crtc_mask;
8395 encoder->base.possible_clones =
66a9278e 8396 intel_encoder_clones(encoder);
79e53945 8397 }
47356eb6 8398
40579abe 8399 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8400 ironlake_init_pch_refclk(dev);
79e53945
JB		 8401}
8402
8403static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8404{
8405 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8406
8407 drm_framebuffer_cleanup(fb);
05394f39 8408 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8409
8410 kfree(intel_fb);
8411}
8412
8413static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8414 struct drm_file *file,
79e53945
JB		 8415 unsigned int *handle)
8416{
8417 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8418 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8419
05394f39 8420 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8421}
8422
8423static const struct drm_framebuffer_funcs intel_fb_funcs = {
8424 .destroy = intel_user_framebuffer_destroy,
8425 .create_handle = intel_user_framebuffer_create_handle,
8426};
8427
38651674
DA		 8428int intel_framebuffer_init(struct drm_device *dev,
8429 struct intel_framebuffer *intel_fb,
308e5bcb 8430 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8431 struct drm_i915_gem_object *obj)
79e53945 8432{
79e53945
JB		 8433 int ret;
8434
05394f39 8435 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8436 return -EINVAL;
8437
308e5bcb 8438 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8439 return -EINVAL;
8440
5d7bd705
VS		 8441 /* FIXME <= Gen4 stride limits are bit unclear */
8442 if (mode_cmd->pitches[0] > 32768)
8443 return -EINVAL;
8444
8445 if (obj->tiling_mode != I915_TILING_NONE &&
8446 mode_cmd->pitches[0] != obj->stride)
8447 return -EINVAL;
8448
57779d06 8449 /* Reject formats not supported by any plane early. */
308e5bcb 8450 switch (mode_cmd->pixel_format) {
57779d06 8451 case DRM_FORMAT_C8:
04b3924d
VS		 8452 case DRM_FORMAT_RGB565:
8453 case DRM_FORMAT_XRGB8888:
8454 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8455 break;
8456 case DRM_FORMAT_XRGB1555:
8457 case DRM_FORMAT_ARGB1555:
8458 if (INTEL_INFO(dev)->gen > 3)
8459 return -EINVAL;
8460 break;
8461 case DRM_FORMAT_XBGR8888:
8462 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8463 case DRM_FORMAT_XRGB2101010:
8464 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8465 case DRM_FORMAT_XBGR2101010:
8466 case DRM_FORMAT_ABGR2101010:
8467 if (INTEL_INFO(dev)->gen < 4)
8468 return -EINVAL;
b5626747 8469 break;
04b3924d
VS		 8470 case DRM_FORMAT_YUYV:
8471 case DRM_FORMAT_UYVY:
8472 case DRM_FORMAT_YVYU:
8473 case DRM_FORMAT_VYUY:
57779d06
VS		 8474 if (INTEL_INFO(dev)->gen < 6)
8475 return -EINVAL;
57cd6508
CW		 8476 break;
8477 default:
57779d06 8478 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8479 return -EINVAL;
8480 }
8481
90f9a336
VS		 8482 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8483 if (mode_cmd->offsets[0] != 0)
8484 return -EINVAL;
8485
79e53945
JB		 8486 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8487 if (ret) {
8488 DRM_ERROR("framebuffer init failed %d\n", ret);
8489 return ret;
8490 }
8491
8492 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8493 intel_fb->obj = obj;
79e53945
JB		 8494 return 0;
8495}
8496
79e53945
JB		 8497static struct drm_framebuffer *
8498intel_user_framebuffer_create(struct drm_device *dev,
8499 struct drm_file *filp,
308e5bcb 8500 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8501{
05394f39 8502 struct drm_i915_gem_object *obj;
79e53945 8503
308e5bcb
JB		 8504 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8505 mode_cmd->handles[0]));
c8725226 8506 if (&obj->base == NULL)
cce13ff7 8507 return ERR_PTR(-ENOENT);
79e53945 8508
d2dff872 8509 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8510}
8511
79e53945 8512static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8513 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8514 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8515};
8516
e70236a8
JB		 8517/* Set up chip specific display functions */
8518static void intel_init_display(struct drm_device *dev)
8519{
8520 struct drm_i915_private *dev_priv = dev->dev_private;
8521
8522 /* We always want a DPMS function */
09b4ddf9
PZ		 8523 if (IS_HASWELL(dev)) {
8524 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8525 dev_priv->display.crtc_enable = haswell_crtc_enable;
8526 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8527 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8528 dev_priv->display.update_plane = ironlake_update_plane;
8529 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8530 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8531 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8532 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8533 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8534 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8535 } else {
f564048e 8536 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8537 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8538 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8539 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8540 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8541 }
e70236a8 8542
e70236a8 8543 /* Returns the core display clock speed */
25eb05fc
JB		 8544 if (IS_VALLEYVIEW(dev))
8545 dev_priv->display.get_display_clock_speed =
8546 valleyview_get_display_clock_speed;
8547 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8548 dev_priv->display.get_display_clock_speed =
8549 i945_get_display_clock_speed;
8550 else if (IS_I915G(dev))
8551 dev_priv->display.get_display_clock_speed =
8552 i915_get_display_clock_speed;
f2b115e6 8553 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8554 dev_priv->display.get_display_clock_speed =
8555 i9xx_misc_get_display_clock_speed;
8556 else if (IS_I915GM(dev))
8557 dev_priv->display.get_display_clock_speed =
8558 i915gm_get_display_clock_speed;
8559 else if (IS_I865G(dev))
8560 dev_priv->display.get_display_clock_speed =
8561 i865_get_display_clock_speed;
f0f8a9ce 8562 else if (IS_I85X(dev))
e70236a8
JB		 8563 dev_priv->display.get_display_clock_speed =
8564 i855_get_display_clock_speed;
8565 else /* 852, 830 */
8566 dev_priv->display.get_display_clock_speed =
8567 i830_get_display_clock_speed;
8568
7f8a8569 8569 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8570 if (IS_GEN5(dev)) {
674cf967 8571 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8572 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8573 } else if (IS_GEN6(dev)) {
674cf967 8574 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8575 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8576 } else if (IS_IVYBRIDGE(dev)) {
8577 /* FIXME: detect B0+ stepping and use auto training */
8578 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8579 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8580 dev_priv->display.modeset_global_resources =
8581 ivb_modeset_global_resources;
c82e4d26
ED		 8582 } else if (IS_HASWELL(dev)) {
8583 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8584 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8585 } else
8586 dev_priv->display.update_wm = NULL;
6067aaea 8587 } else if (IS_G4X(dev)) {
e0dac65e 8588 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8589 }
8c9f3aaf
JB		 8590
8591 /* Default just returns -ENODEV to indicate unsupported */
8592 dev_priv->display.queue_flip = intel_default_queue_flip;
8593
8594 switch (INTEL_INFO(dev)->gen) {
8595 case 2:
8596 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8597 break;
8598
8599 case 3:
8600 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8601 break;
8602
8603 case 4:
8604 case 5:
8605 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8606 break;
8607
8608 case 6:
8609 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8610 break;
7c9017e5
JB		 8611 case 7:
8612 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8613 break;
8c9f3aaf 8614 }
e70236a8
JB		 8615}
8616
b690e96c
JB		 8617/*
8618 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8619 * resume, or other times. This quirk makes sure that's the case for
8620 * affected systems.
8621 */
0206e353 8622static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8623{
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8625
8626 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8627 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8628}
8629
435793df
KP		 8630/*
8631 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8632 */
8633static void quirk_ssc_force_disable(struct drm_device *dev)
8634{
8635 struct drm_i915_private *dev_priv = dev->dev_private;
8636 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8637 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8638}
8639
4dca20ef 8640/*
5a15ab5b
CE		 8641 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8642 * brightness value
4dca20ef
CE		 8643 */
8644static void quirk_invert_brightness(struct drm_device *dev)
8645{
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8648 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8649}
8650
b690e96c
JB		 8651struct intel_quirk {
8652 int device;
8653 int subsystem_vendor;
8654 int subsystem_device;
8655 void (*hook)(struct drm_device *dev);
8656};
8657
c43b5634 8658static struct intel_quirk intel_quirks[] = {
b690e96c 8659 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8660 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8661
b690e96c
JB		 8662 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8663 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8664
b690e96c
JB		 8665 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8666 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8667
ccd0d36e 8668 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8669 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8670 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8671
8672 /* Lenovo U160 cannot use SSC on LVDS */
8673 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8674
8675 /* Sony Vaio Y cannot use SSC on LVDS */
8676 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8677
8678 /* Acer Aspire 5734Z must invert backlight brightness */
8679 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8680};
8681
8682static void intel_init_quirks(struct drm_device *dev)
8683{
8684 struct pci_dev *d = dev->pdev;
8685 int i;
8686
8687 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8688 struct intel_quirk *q = &intel_quirks[i];
8689
8690 if (d->device == q->device &&
8691 (d->subsystem_vendor == q->subsystem_vendor ||
8692 q->subsystem_vendor == PCI_ANY_ID) &&
8693 (d->subsystem_device == q->subsystem_device ||
8694 q->subsystem_device == PCI_ANY_ID))
8695 q->hook(dev);
8696 }
8697}
8698
9cce37f4
JB		 8699/* Disable the VGA plane that we never use */
8700static void i915_disable_vga(struct drm_device *dev)
8701{
8702 struct drm_i915_private *dev_priv = dev->dev_private;
8703 u8 sr1;
8704 u32 vga_reg;
8705
8706 if (HAS_PCH_SPLIT(dev))
8707 vga_reg = CPU_VGACNTRL;
8708 else
8709 vga_reg = VGACNTRL;
8710
8711 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8712 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8713 sr1 = inb(VGA_SR_DATA);
8714 outb(sr1 | 1<<5, VGA_SR_DATA);
8715 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8716 udelay(300);
8717
8718 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8719 POSTING_READ(vga_reg);
8720}
8721
f817586c
DV		 8722void intel_modeset_init_hw(struct drm_device *dev)
8723{
0232e927
ED		 8724 /* We attempt to init the necessary power wells early in the initialization
8725 * time, so the subsystems that expect power to be enabled can work.
8726 */
8727 intel_init_power_wells(dev);
8728
a8f78b58
ED		 8729 intel_prepare_ddi(dev);
8730
f817586c
DV		 8731 intel_init_clock_gating(dev);
8732
79f5b2c7 8733 mutex_lock(&dev->struct_mutex);
8090c6b9 8734 intel_enable_gt_powersave(dev);
79f5b2c7 8735 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8736}
8737
79e53945
JB		 8738void intel_modeset_init(struct drm_device *dev)
8739{
652c393a 8740 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8741 int i, ret;
79e53945
JB		 8742
8743 drm_mode_config_init(dev);
8744
8745 dev->mode_config.min_width = 0;
8746 dev->mode_config.min_height = 0;
8747
019d96cb
DA		 8748 dev->mode_config.preferred_depth = 24;
8749 dev->mode_config.prefer_shadow = 1;
8750
e6ecefaa 8751 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8752
b690e96c
JB		 8753 intel_init_quirks(dev);
8754
1fa61106
ED		 8755 intel_init_pm(dev);
8756
e70236a8
JB		 8757 intel_init_display(dev);
8758
a6c45cf0
CW		 8759 if (IS_GEN2(dev)) {
8760 dev->mode_config.max_width = 2048;
8761 dev->mode_config.max_height = 2048;
8762 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8763 dev->mode_config.max_width = 4096;
8764 dev->mode_config.max_height = 4096;
79e53945 8765 } else {
a6c45cf0
CW		 8766 dev->mode_config.max_width = 8192;
8767 dev->mode_config.max_height = 8192;
79e53945 8768 }
dd2757f8 8769 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8770
28c97730 8771 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8772 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8773
a3524f1b 8774 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8775 intel_crtc_init(dev, i);
00c2064b
JB		 8776 ret = intel_plane_init(dev, i);
8777 if (ret)
8778 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8779 }
8780
79f689aa 8781 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8782 intel_pch_pll_init(dev);
8783
9cce37f4
JB		 8784 /* Just disable it once at startup */
8785 i915_disable_vga(dev);
79e53945 8786 intel_setup_outputs(dev);
2c7111db
CW		 8787}
8788
24929352
DV		 8789static void
8790intel_connector_break_all_links(struct intel_connector *connector)
8791{
8792 connector->base.dpms = DRM_MODE_DPMS_OFF;
8793 connector->base.encoder = NULL;
8794 connector->encoder->connectors_active = false;
8795 connector->encoder->base.crtc = NULL;
8796}
8797
7fad798e
DV		 8798static void intel_enable_pipe_a(struct drm_device *dev)
8799{
8800 struct intel_connector *connector;
8801 struct drm_connector *crt = NULL;
8802 struct intel_load_detect_pipe load_detect_temp;
8803
8804 /* We can't just switch on the pipe A, we need to set things up with a
8805 * proper mode and output configuration. As a gross hack, enable pipe A
8806 * by enabling the load detect pipe once. */
8807 list_for_each_entry(connector,
8808 &dev->mode_config.connector_list,
8809 base.head) {
8810 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8811 crt = &connector->base;
8812 break;
8813 }
8814 }
8815
8816 if (!crt)
8817 return;
8818
8819 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8820 intel_release_load_detect_pipe(crt, &load_detect_temp);
8821
8822
8823}
8824
fa555837
DV		 8825static bool
8826intel_check_plane_mapping(struct intel_crtc *crtc)
8827{
8828 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8829 u32 reg, val;
8830
8831 if (dev_priv->num_pipe == 1)
8832 return true;
8833
8834 reg = DSPCNTR(!crtc->plane);
8835 val = I915_READ(reg);
8836
8837 if ((val & DISPLAY_PLANE_ENABLE) &&
8838 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8839 return false;
8840
8841 return true;
8842}
8843
24929352
DV		 8844static void intel_sanitize_crtc(struct intel_crtc *crtc)
8845{
8846 struct drm_device *dev = crtc->base.dev;
8847 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8848 u32 reg;
24929352 8849
24929352 8850 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8851 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8852 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8853
8854 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8855 * disable the crtc (and hence change the state) if it is wrong. Note
8856 * that gen4+ has a fixed plane -> pipe mapping. */
8857 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8858 struct intel_connector *connector;
8859 bool plane;
8860
24929352
DV		 8861 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8862 crtc->base.base.id);
8863
8864 /* Pipe has the wrong plane attached and the plane is active.
8865 * Temporarily change the plane mapping and disable everything
8866 * ... */
8867 plane = crtc->plane;
8868 crtc->plane = !plane;
8869 dev_priv->display.crtc_disable(&crtc->base);
8870 crtc->plane = plane;
8871
8872 /* ... and break all links. */
8873 list_for_each_entry(connector, &dev->mode_config.connector_list,
8874 base.head) {
8875 if (connector->encoder->base.crtc != &crtc->base)
8876 continue;
8877
8878 intel_connector_break_all_links(connector);
8879 }
8880
8881 WARN_ON(crtc->active);
8882 crtc->base.enabled = false;
8883 }
24929352 8884
7fad798e
DV		 8885 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8886 crtc->pipe == PIPE_A && !crtc->active) {
8887 /* BIOS forgot to enable pipe A, this mostly happens after
8888 * resume. Force-enable the pipe to fix this, the update_dpms
8889 * call below we restore the pipe to the right state, but leave
8890 * the required bits on. */
8891 intel_enable_pipe_a(dev);
8892 }
8893
24929352
DV		 8894 /* Adjust the state of the output pipe according to whether we
8895 * have active connectors/encoders. */
8896 intel_crtc_update_dpms(&crtc->base);
8897
8898 if (crtc->active != crtc->base.enabled) {
8899 struct intel_encoder *encoder;
8900
8901 /* This can happen either due to bugs in the get_hw_state
8902 * functions or because the pipe is force-enabled due to the
8903 * pipe A quirk. */
8904 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8905 crtc->base.base.id,
8906 crtc->base.enabled ? "enabled" : "disabled",
8907 crtc->active ? "enabled" : "disabled");
8908
8909 crtc->base.enabled = crtc->active;
8910
8911 /* Because we only establish the connector -> encoder ->
8912 * crtc links if something is active, this means the
8913 * crtc is now deactivated. Break the links. connector
8914 * -> encoder links are only establish when things are
8915 * actually up, hence no need to break them. */
8916 WARN_ON(crtc->active);
8917
8918 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8919 WARN_ON(encoder->connectors_active);
8920 encoder->base.crtc = NULL;
8921 }
8922 }
8923}
8924
8925static void intel_sanitize_encoder(struct intel_encoder *encoder)
8926{
8927 struct intel_connector *connector;
8928 struct drm_device *dev = encoder->base.dev;
8929
8930 /* We need to check both for a crtc link (meaning that the
8931 * encoder is active and trying to read from a pipe) and the
8932 * pipe itself being active. */
8933 bool has_active_crtc = encoder->base.crtc &&
8934 to_intel_crtc(encoder->base.crtc)->active;
8935
8936 if (encoder->connectors_active && !has_active_crtc) {
8937 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8938 encoder->base.base.id,
8939 drm_get_encoder_name(&encoder->base));
8940
8941 /* Connector is active, but has no active pipe. This is
8942 * fallout from our resume register restoring. Disable
8943 * the encoder manually again. */
8944 if (encoder->base.crtc) {
8945 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8946 encoder->base.base.id,
8947 drm_get_encoder_name(&encoder->base));
8948 encoder->disable(encoder);
8949 }
8950
8951 /* Inconsistent output/port/pipe state happens presumably due to
8952 * a bug in one of the get_hw_state functions. Or someplace else
8953 * in our code, like the register restore mess on resume. Clamp
8954 * things to off as a safer default. */
8955 list_for_each_entry(connector,
8956 &dev->mode_config.connector_list,
8957 base.head) {
8958 if (connector->encoder != encoder)
8959 continue;
8960
8961 intel_connector_break_all_links(connector);
8962 }
8963 }
8964 /* Enabled encoders without active connectors will be fixed in
8965 * the crtc fixup. */
8966}
8967
8968/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8969 * and i915 state tracking structures. */
8970void intel_modeset_setup_hw_state(struct drm_device *dev)
8971{
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8973 enum pipe pipe;
8974 u32 tmp;
8975 struct intel_crtc *crtc;
8976 struct intel_encoder *encoder;
8977 struct intel_connector *connector;
8978
e28d54cb
PZ		 8979 if (IS_HASWELL(dev)) {
8980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8981
8982 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8983 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8984 case TRANS_DDI_EDP_INPUT_A_ON:
8985 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8986 pipe = PIPE_A;
8987 break;
8988 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8989 pipe = PIPE_B;
8990 break;
8991 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8992 pipe = PIPE_C;
8993 break;
8994 }
8995
8996 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8997 crtc->cpu_transcoder = TRANSCODER_EDP;
8998
8999 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9000 pipe_name(pipe));
9001 }
9002 }
9003
24929352
DV		 9004 for_each_pipe(pipe) {
9005 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9006
702e7a56 9007 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9008 if (tmp & PIPECONF_ENABLE)
9009 crtc->active = true;
9010 else
9011 crtc->active = false;
9012
9013 crtc->base.enabled = crtc->active;
9014
9015 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9016 crtc->base.base.id,
9017 crtc->active ? "enabled" : "disabled");
9018 }
9019
6441ab5f
PZ		 9020 if (IS_HASWELL(dev))
9021 intel_ddi_setup_hw_pll_state(dev);
9022
24929352
DV		 9023 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9024 base.head) {
9025 pipe = 0;
9026
9027 if (encoder->get_hw_state(encoder, &pipe)) {
9028 encoder->base.crtc =
9029 dev_priv->pipe_to_crtc_mapping[pipe];
9030 } else {
9031 encoder->base.crtc = NULL;
9032 }
9033
9034 encoder->connectors_active = false;
9035 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9036 encoder->base.base.id,
9037 drm_get_encoder_name(&encoder->base),
9038 encoder->base.crtc ? "enabled" : "disabled",
9039 pipe);
9040 }
9041
9042 list_for_each_entry(connector, &dev->mode_config.connector_list,
9043 base.head) {
9044 if (connector->get_hw_state(connector)) {
9045 connector->base.dpms = DRM_MODE_DPMS_ON;
9046 connector->encoder->connectors_active = true;
9047 connector->base.encoder = &connector->encoder->base;
9048 } else {
9049 connector->base.dpms = DRM_MODE_DPMS_OFF;
9050 connector->base.encoder = NULL;
9051 }
9052 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9053 connector->base.base.id,
9054 drm_get_connector_name(&connector->base),
9055 connector->base.encoder ? "enabled" : "disabled");
9056 }
9057
9058 /* HW state is read out, now we need to sanitize this mess. */
9059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9060 base.head) {
9061 intel_sanitize_encoder(encoder);
9062 }
9063
9064 for_each_pipe(pipe) {
9065 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9066 intel_sanitize_crtc(crtc);
9067 }
9a935856
DV		 9068
9069 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9070
9071 intel_modeset_check_state(dev);
2e938892
DV		 9072
9073 drm_mode_config_reset(dev);
24929352
DV		 9074}
9075
2c7111db
CW		 9076void intel_modeset_gem_init(struct drm_device *dev)
9077{
1833b134 9078 intel_modeset_init_hw(dev);
02e792fb
DV		 9079
9080 intel_setup_overlay(dev);
24929352
DV		 9081
9082 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9083}
9084
9085void intel_modeset_cleanup(struct drm_device *dev)
9086{
652c393a
JB		 9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 struct drm_crtc *crtc;
9089 struct intel_crtc *intel_crtc;
9090
f87ea761 9091 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9092 mutex_lock(&dev->struct_mutex);
9093
723bfd70
JB		 9094 intel_unregister_dsm_handler();
9095
9096
652c393a
JB		 9097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9098 /* Skip inactive CRTCs */
9099 if (!crtc->fb)
9100 continue;
9101
9102 intel_crtc = to_intel_crtc(crtc);
3dec0095 9103 intel_increase_pllclock(crtc);
652c393a
JB		 9104 }
9105
973d04f9 9106 intel_disable_fbc(dev);
e70236a8 9107
8090c6b9 9108 intel_disable_gt_powersave(dev);
0cdab21f 9109
930ebb46
DV		 9110 ironlake_teardown_rc6(dev);
9111
57f350b6
JB		 9112 if (IS_VALLEYVIEW(dev))
9113 vlv_init_dpio(dev);
9114
69341a5e
KH		 9115 mutex_unlock(&dev->struct_mutex);
9116
6c0d9350
DV		 9117 /* Disable the irq before mode object teardown, for the irq might
9118 * enqueue unpin/hotplug work. */
9119 drm_irq_uninstall(dev);
9120 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9121 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9122
1630fe75
CW		 9123 /* flush any delayed tasks or pending work */
9124 flush_scheduled_work();
9125
79e53945
JB		 9126 drm_mode_config_cleanup(dev);
9127}
9128
f1c79df3
ZW		 9129/*
9130 * Return which encoder is currently attached for connector.
9131 */
df0e9248 9132struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9133{
df0e9248
CW		 9134 return &intel_attached_encoder(connector)->base;
9135}
f1c79df3 9136
df0e9248
CW		 9137void intel_connector_attach_encoder(struct intel_connector *connector,
9138 struct intel_encoder *encoder)
9139{
9140 connector->encoder = encoder;
9141 drm_mode_connector_attach_encoder(&connector->base,
9142 &encoder->base);
79e53945 9143}
28d52043
DA		 9144
9145/*
9146 * set vga decode state - true == enable VGA decode
9147 */
9148int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9149{
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 u16 gmch_ctrl;
9152
9153 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9154 if (state)
9155 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9156 else
9157 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9158 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9159 return 0;
9160}
c4a1d9e4
CW		 9161
9162#ifdef CONFIG_DEBUG_FS
9163#include <linux/seq_file.h>
9164
9165struct intel_display_error_state {
9166 struct intel_cursor_error_state {
9167 u32 control;
9168 u32 position;
9169 u32 base;
9170 u32 size;
52331309 9171 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9172
9173 struct intel_pipe_error_state {
9174 u32 conf;
9175 u32 source;
9176
9177 u32 htotal;
9178 u32 hblank;
9179 u32 hsync;
9180 u32 vtotal;
9181 u32 vblank;
9182 u32 vsync;
52331309 9183 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9184
9185 struct intel_plane_error_state {
9186 u32 control;
9187 u32 stride;
9188 u32 size;
9189 u32 pos;
9190 u32 addr;
9191 u32 surface;
9192 u32 tile_offset;
52331309 9193 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9194};
9195
9196struct intel_display_error_state *
9197intel_display_capture_error_state(struct drm_device *dev)
9198{
0206e353 9199 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9200 struct intel_display_error_state *error;
702e7a56 9201 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9202 int i;
9203
9204 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9205 if (error == NULL)
9206 return NULL;
9207
52331309 9208 for_each_pipe(i) {
702e7a56
PZ		 9209 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9210
c4a1d9e4
CW		 9211 error->cursor[i].control = I915_READ(CURCNTR(i));
9212 error->cursor[i].position = I915_READ(CURPOS(i));
9213 error->cursor[i].base = I915_READ(CURBASE(i));
9214
9215 error->plane[i].control = I915_READ(DSPCNTR(i));
9216 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9217 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9218 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9219 error->plane[i].addr = I915_READ(DSPADDR(i));
9220 if (INTEL_INFO(dev)->gen >= 4) {
9221 error->plane[i].surface = I915_READ(DSPSURF(i));
9222 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9223 }
9224
702e7a56 9225 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9226 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9227 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9228 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9229 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9230 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9231 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9232 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9233 }
9234
9235 return error;
9236}
9237
9238void
9239intel_display_print_error_state(struct seq_file *m,
9240 struct drm_device *dev,
9241 struct intel_display_error_state *error)
9242{
52331309 9243 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9244 int i;
9245
52331309
DL		 9246 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9247 for_each_pipe(i) {
c4a1d9e4
CW		 9248 seq_printf(m, "Pipe [%d]:\n", i);
9249 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9250 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9251 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9252 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9253 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9254 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9255 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9256 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9257
9258 seq_printf(m, "Plane [%d]:\n", i);
9259 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9260 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9261 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9262 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9263 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9264 if (INTEL_INFO(dev)->gen >= 4) {
9265 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9266 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9267 }
9268
9269 seq_printf(m, "Cursor [%d]:\n", i);
9270 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9271 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9272 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9273 }
9274}
9275#endif
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