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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
28 | #include "drmP.h" | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | ||
35 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); | |
36 | ||
37 | typedef struct { | |
38 | /* given values */ | |
39 | int n; | |
40 | int m1, m2; | |
41 | int p1, p2; | |
42 | /* derived values */ | |
43 | int dot; | |
44 | int vco; | |
45 | int m; | |
46 | int p; | |
47 | } intel_clock_t; | |
48 | ||
49 | typedef struct { | |
50 | int min, max; | |
51 | } intel_range_t; | |
52 | ||
53 | typedef struct { | |
54 | int dot_limit; | |
55 | int p2_slow, p2_fast; | |
56 | } intel_p2_t; | |
57 | ||
58 | #define INTEL_P2_NUM 2 | |
59 | ||
60 | typedef struct { | |
61 | intel_range_t dot, vco, n, m, m1, m2, p, p1; | |
62 | intel_p2_t p2; | |
63 | } intel_limit_t; | |
64 | ||
65 | #define I8XX_DOT_MIN 25000 | |
66 | #define I8XX_DOT_MAX 350000 | |
67 | #define I8XX_VCO_MIN 930000 | |
68 | #define I8XX_VCO_MAX 1400000 | |
69 | #define I8XX_N_MIN 3 | |
70 | #define I8XX_N_MAX 16 | |
71 | #define I8XX_M_MIN 96 | |
72 | #define I8XX_M_MAX 140 | |
73 | #define I8XX_M1_MIN 18 | |
74 | #define I8XX_M1_MAX 26 | |
75 | #define I8XX_M2_MIN 6 | |
76 | #define I8XX_M2_MAX 16 | |
77 | #define I8XX_P_MIN 4 | |
78 | #define I8XX_P_MAX 128 | |
79 | #define I8XX_P1_MIN 2 | |
80 | #define I8XX_P1_MAX 33 | |
81 | #define I8XX_P1_LVDS_MIN 1 | |
82 | #define I8XX_P1_LVDS_MAX 6 | |
83 | #define I8XX_P2_SLOW 4 | |
84 | #define I8XX_P2_FAST 2 | |
85 | #define I8XX_P2_LVDS_SLOW 14 | |
86 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ | |
87 | #define I8XX_P2_SLOW_LIMIT 165000 | |
88 | ||
89 | #define I9XX_DOT_MIN 20000 | |
90 | #define I9XX_DOT_MAX 400000 | |
91 | #define I9XX_VCO_MIN 1400000 | |
92 | #define I9XX_VCO_MAX 2800000 | |
93 | #define I9XX_N_MIN 3 | |
94 | #define I9XX_N_MAX 8 | |
95 | #define I9XX_M_MIN 70 | |
96 | #define I9XX_M_MAX 120 | |
97 | #define I9XX_M1_MIN 10 | |
98 | #define I9XX_M1_MAX 20 | |
99 | #define I9XX_M2_MIN 5 | |
100 | #define I9XX_M2_MAX 9 | |
101 | #define I9XX_P_SDVO_DAC_MIN 5 | |
102 | #define I9XX_P_SDVO_DAC_MAX 80 | |
103 | #define I9XX_P_LVDS_MIN 7 | |
104 | #define I9XX_P_LVDS_MAX 98 | |
105 | #define I9XX_P1_MIN 1 | |
106 | #define I9XX_P1_MAX 8 | |
107 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
108 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
109 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
110 | #define I9XX_P2_LVDS_SLOW 14 | |
111 | #define I9XX_P2_LVDS_FAST 7 | |
112 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
113 | ||
114 | #define INTEL_LIMIT_I8XX_DVO_DAC 0 | |
115 | #define INTEL_LIMIT_I8XX_LVDS 1 | |
116 | #define INTEL_LIMIT_I9XX_SDVO_DAC 2 | |
117 | #define INTEL_LIMIT_I9XX_LVDS 3 | |
118 | ||
119 | static const intel_limit_t intel_limits[] = { | |
120 | { /* INTEL_LIMIT_I8XX_DVO_DAC */ | |
121 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
122 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
123 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
124 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
125 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
126 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
127 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
128 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
129 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
130 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
131 | }, | |
132 | { /* INTEL_LIMIT_I8XX_LVDS */ | |
133 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
134 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
135 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
136 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
137 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
138 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
139 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
140 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
141 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
142 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
143 | }, | |
144 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ | |
145 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
146 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
147 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
148 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
149 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
150 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
151 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
152 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
153 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
154 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
155 | }, | |
156 | { /* INTEL_LIMIT_I9XX_LVDS */ | |
157 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
158 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
159 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
160 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
161 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
162 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
163 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
164 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
165 | /* The single-channel range is 25-112Mhz, and dual-channel | |
166 | * is 80-224Mhz. Prefer single channel as much as possible. | |
167 | */ | |
168 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
169 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
170 | }, | |
171 | }; | |
172 | ||
173 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) | |
174 | { | |
175 | struct drm_device *dev = crtc->dev; | |
176 | const intel_limit_t *limit; | |
177 | ||
178 | if (IS_I9XX(dev)) { | |
179 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
180 | limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS]; | |
181 | else | |
182 | limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | |
183 | } else { | |
184 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
185 | limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS]; | |
186 | else | |
187 | limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC]; | |
188 | } | |
189 | return limit; | |
190 | } | |
191 | ||
192 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ | |
193 | ||
194 | static void i8xx_clock(int refclk, intel_clock_t *clock) | |
195 | { | |
196 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); | |
197 | clock->p = clock->p1 * clock->p2; | |
198 | clock->vco = refclk * clock->m / (clock->n + 2); | |
199 | clock->dot = clock->vco / clock->p; | |
200 | } | |
201 | ||
202 | /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */ | |
203 | ||
204 | static void i9xx_clock(int refclk, intel_clock_t *clock) | |
205 | { | |
206 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); | |
207 | clock->p = clock->p1 * clock->p2; | |
208 | clock->vco = refclk * clock->m / (clock->n + 2); | |
209 | clock->dot = clock->vco / clock->p; | |
210 | } | |
211 | ||
212 | static void intel_clock(struct drm_device *dev, int refclk, | |
213 | intel_clock_t *clock) | |
214 | { | |
215 | if (IS_I9XX(dev)) | |
d4da3af6 | 216 | i9xx_clock (refclk, clock); |
79e53945 | 217 | else |
d4da3af6 | 218 | i8xx_clock (refclk, clock); |
79e53945 JB |
219 | } |
220 | ||
221 | /** | |
222 | * Returns whether any output on the specified pipe is of the specified type | |
223 | */ | |
224 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) | |
225 | { | |
226 | struct drm_device *dev = crtc->dev; | |
227 | struct drm_mode_config *mode_config = &dev->mode_config; | |
228 | struct drm_connector *l_entry; | |
229 | ||
230 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | |
231 | if (l_entry->encoder && | |
232 | l_entry->encoder->crtc == crtc) { | |
233 | struct intel_output *intel_output = to_intel_output(l_entry); | |
234 | if (intel_output->type == type) | |
235 | return true; | |
236 | } | |
237 | } | |
238 | return false; | |
239 | } | |
240 | ||
241 | #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } | |
242 | /** | |
243 | * Returns whether the given set of divisors are valid for a given refclk with | |
244 | * the given connectors. | |
245 | */ | |
246 | ||
247 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
248 | { | |
249 | const intel_limit_t *limit = intel_limit (crtc); | |
250 | ||
251 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
252 | INTELPllInvalid ("p1 out of range\n"); | |
253 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
254 | INTELPllInvalid ("p out of range\n"); | |
255 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
256 | INTELPllInvalid ("m2 out of range\n"); | |
257 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
258 | INTELPllInvalid ("m1 out of range\n"); | |
259 | if (clock->m1 <= clock->m2) | |
260 | INTELPllInvalid ("m1 <= m2\n"); | |
261 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
262 | INTELPllInvalid ("m out of range\n"); | |
263 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
264 | INTELPllInvalid ("n out of range\n"); | |
265 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
266 | INTELPllInvalid ("vco out of range\n"); | |
267 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
268 | * connector, etc., rather than just a single range. | |
269 | */ | |
270 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
271 | INTELPllInvalid ("dot out of range\n"); | |
272 | ||
273 | return true; | |
274 | } | |
275 | ||
276 | /** | |
277 | * Returns a set of divisors for the desired target clock with the given | |
278 | * refclk, or FALSE. The returned values represent the clock equation: | |
279 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
280 | */ | |
281 | static bool intel_find_best_PLL(struct drm_crtc *crtc, int target, | |
282 | int refclk, intel_clock_t *best_clock) | |
283 | { | |
284 | struct drm_device *dev = crtc->dev; | |
285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
286 | intel_clock_t clock; | |
287 | const intel_limit_t *limit = intel_limit(crtc); | |
288 | int err = target; | |
289 | ||
290 | if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
291 | (I915_READ(LVDS) & LVDS_PORT_EN) != 0) { | |
292 | /* | |
293 | * For LVDS, if the panel is on, just rely on its current | |
294 | * settings for dual-channel. We haven't figured out how to | |
295 | * reliably set up different single/dual channel state, if we | |
296 | * even can. | |
297 | */ | |
298 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
299 | LVDS_CLKB_POWER_UP) | |
300 | clock.p2 = limit->p2.p2_fast; | |
301 | else | |
302 | clock.p2 = limit->p2.p2_slow; | |
303 | } else { | |
304 | if (target < limit->p2.dot_limit) | |
305 | clock.p2 = limit->p2.p2_slow; | |
306 | else | |
307 | clock.p2 = limit->p2.p2_fast; | |
308 | } | |
309 | ||
310 | memset (best_clock, 0, sizeof (*best_clock)); | |
311 | ||
312 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
313 | for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 && | |
314 | clock.m2 <= limit->m2.max; clock.m2++) { | |
315 | for (clock.n = limit->n.min; clock.n <= limit->n.max; | |
316 | clock.n++) { | |
317 | for (clock.p1 = limit->p1.min; | |
318 | clock.p1 <= limit->p1.max; clock.p1++) { | |
319 | int this_err; | |
320 | ||
321 | intel_clock(dev, refclk, &clock); | |
322 | ||
323 | if (!intel_PLL_is_valid(crtc, &clock)) | |
324 | continue; | |
325 | ||
326 | this_err = abs(clock.dot - target); | |
327 | if (this_err < err) { | |
328 | *best_clock = clock; | |
329 | err = this_err; | |
330 | } | |
331 | } | |
332 | } | |
333 | } | |
334 | } | |
335 | ||
336 | return (err != target); | |
337 | } | |
338 | ||
339 | void | |
340 | intel_wait_for_vblank(struct drm_device *dev) | |
341 | { | |
342 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | |
343 | udelay(20000); | |
344 | } | |
345 | ||
b358d0a6 | 346 | static void |
3c4fdcfb KH |
347 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
348 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
349 | { |
350 | struct drm_device *dev = crtc->dev; | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
352 | struct drm_i915_master_private *master_priv; | |
353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
354 | struct intel_framebuffer *intel_fb; | |
355 | struct drm_i915_gem_object *obj_priv; | |
356 | struct drm_gem_object *obj; | |
357 | int pipe = intel_crtc->pipe; | |
358 | unsigned long Start, Offset; | |
359 | int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); | |
360 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); | |
361 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
362 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
3c4fdcfb | 363 | u32 dspcntr, alignment; |
79e53945 JB |
364 | |
365 | /* no fb bound */ | |
366 | if (!crtc->fb) { | |
367 | DRM_DEBUG("No FB bound\n"); | |
368 | return; | |
369 | } | |
370 | ||
371 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 JB |
372 | obj = intel_fb->obj; |
373 | obj_priv = obj->driver_private; | |
374 | ||
3c4fdcfb KH |
375 | switch (obj_priv->tiling_mode) { |
376 | case I915_TILING_NONE: | |
377 | alignment = 64 * 1024; | |
378 | break; | |
379 | case I915_TILING_X: | |
380 | if (IS_I9XX(dev)) | |
381 | alignment = 1024 * 1024; | |
382 | else | |
383 | alignment = 512 * 1024; | |
384 | break; | |
385 | case I915_TILING_Y: | |
386 | /* FIXME: Is this true? */ | |
387 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
388 | return; | |
389 | default: | |
390 | BUG(); | |
391 | } | |
392 | ||
393 | if (i915_gem_object_pin(intel_fb->obj, alignment)) | |
394 | return; | |
395 | ||
396 | i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1); | |
397 | ||
79e53945 JB |
398 | Start = obj_priv->gtt_offset; |
399 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); | |
400 | ||
401 | I915_WRITE(dspstride, crtc->fb->pitch); | |
402 | ||
403 | dspcntr = I915_READ(dspcntr_reg); | |
404 | switch (crtc->fb->bits_per_pixel) { | |
405 | case 8: | |
406 | dspcntr |= DISPPLANE_8BPP; | |
407 | break; | |
408 | case 16: | |
409 | if (crtc->fb->depth == 15) | |
410 | dspcntr |= DISPPLANE_15_16BPP; | |
411 | else | |
412 | dspcntr |= DISPPLANE_16BPP; | |
413 | break; | |
414 | case 24: | |
415 | case 32: | |
416 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
417 | break; | |
418 | default: | |
419 | DRM_ERROR("Unknown color depth\n"); | |
420 | return; | |
421 | } | |
422 | I915_WRITE(dspcntr_reg, dspcntr); | |
423 | ||
424 | DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); | |
425 | if (IS_I965G(dev)) { | |
426 | I915_WRITE(dspbase, Offset); | |
427 | I915_READ(dspbase); | |
428 | I915_WRITE(dspsurf, Start); | |
429 | I915_READ(dspsurf); | |
430 | } else { | |
431 | I915_WRITE(dspbase, Start + Offset); | |
432 | I915_READ(dspbase); | |
433 | } | |
434 | ||
3c4fdcfb KH |
435 | intel_wait_for_vblank(dev); |
436 | ||
437 | if (old_fb) { | |
438 | intel_fb = to_intel_framebuffer(old_fb); | |
439 | i915_gem_object_unpin(intel_fb->obj); | |
440 | } | |
79e53945 JB |
441 | |
442 | if (!dev->primary->master) | |
443 | return; | |
444 | ||
445 | master_priv = dev->primary->master->driver_priv; | |
446 | if (!master_priv->sarea_priv) | |
447 | return; | |
448 | ||
449 | switch (pipe) { | |
450 | case 0: | |
451 | master_priv->sarea_priv->pipeA_x = x; | |
452 | master_priv->sarea_priv->pipeA_y = y; | |
453 | break; | |
454 | case 1: | |
455 | master_priv->sarea_priv->pipeB_x = x; | |
456 | master_priv->sarea_priv->pipeB_y = y; | |
457 | break; | |
458 | default: | |
459 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
460 | break; | |
461 | } | |
462 | } | |
463 | ||
464 | ||
465 | ||
466 | /** | |
467 | * Sets the power management mode of the pipe and plane. | |
468 | * | |
469 | * This code should probably grow support for turning the cursor off and back | |
470 | * on appropriately at the same time as we're turning the pipe off/on. | |
471 | */ | |
472 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
473 | { | |
474 | struct drm_device *dev = crtc->dev; | |
475 | struct drm_i915_master_private *master_priv; | |
476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
478 | int pipe = intel_crtc->pipe; | |
479 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
480 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
481 | int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; | |
482 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
483 | u32 temp; | |
484 | bool enabled; | |
485 | ||
486 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
487 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
488 | */ | |
489 | switch (mode) { | |
490 | case DRM_MODE_DPMS_ON: | |
491 | case DRM_MODE_DPMS_STANDBY: | |
492 | case DRM_MODE_DPMS_SUSPEND: | |
493 | /* Enable the DPLL */ | |
494 | temp = I915_READ(dpll_reg); | |
495 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
496 | I915_WRITE(dpll_reg, temp); | |
497 | I915_READ(dpll_reg); | |
498 | /* Wait for the clocks to stabilize. */ | |
499 | udelay(150); | |
500 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
501 | I915_READ(dpll_reg); | |
502 | /* Wait for the clocks to stabilize. */ | |
503 | udelay(150); | |
504 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
505 | I915_READ(dpll_reg); | |
506 | /* Wait for the clocks to stabilize. */ | |
507 | udelay(150); | |
508 | } | |
509 | ||
510 | /* Enable the pipe */ | |
511 | temp = I915_READ(pipeconf_reg); | |
512 | if ((temp & PIPEACONF_ENABLE) == 0) | |
513 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
514 | ||
515 | /* Enable the plane */ | |
516 | temp = I915_READ(dspcntr_reg); | |
517 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
518 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
519 | /* Flush the plane changes */ | |
520 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
521 | } | |
522 | ||
523 | intel_crtc_load_lut(crtc); | |
524 | ||
525 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
526 | //intel_crtc_dpms_video(crtc, true); TODO | |
527 | break; | |
528 | case DRM_MODE_DPMS_OFF: | |
529 | /* Give the overlay scaler a chance to disable if it's on this pipe */ | |
530 | //intel_crtc_dpms_video(crtc, FALSE); TODO | |
531 | ||
532 | /* Disable the VGA plane that we never use */ | |
533 | I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
534 | ||
535 | /* Disable display plane */ | |
536 | temp = I915_READ(dspcntr_reg); | |
537 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
538 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
539 | /* Flush the plane changes */ | |
540 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
541 | I915_READ(dspbase_reg); | |
542 | } | |
543 | ||
544 | if (!IS_I9XX(dev)) { | |
545 | /* Wait for vblank for the disable to take effect */ | |
546 | intel_wait_for_vblank(dev); | |
547 | } | |
548 | ||
549 | /* Next, disable display pipes */ | |
550 | temp = I915_READ(pipeconf_reg); | |
551 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
552 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
553 | I915_READ(pipeconf_reg); | |
554 | } | |
555 | ||
556 | /* Wait for vblank for the disable to take effect. */ | |
557 | intel_wait_for_vblank(dev); | |
558 | ||
559 | temp = I915_READ(dpll_reg); | |
560 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
561 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
562 | I915_READ(dpll_reg); | |
563 | } | |
564 | ||
565 | /* Wait for the clocks to turn off. */ | |
566 | udelay(150); | |
567 | break; | |
568 | } | |
569 | ||
570 | if (!dev->primary->master) | |
571 | return; | |
572 | ||
573 | master_priv = dev->primary->master->driver_priv; | |
574 | if (!master_priv->sarea_priv) | |
575 | return; | |
576 | ||
577 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
578 | ||
579 | switch (pipe) { | |
580 | case 0: | |
581 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
582 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
583 | break; | |
584 | case 1: | |
585 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
586 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
587 | break; | |
588 | default: | |
589 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
590 | break; | |
591 | } | |
592 | ||
593 | intel_crtc->dpms_mode = mode; | |
594 | } | |
595 | ||
596 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
597 | { | |
598 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
599 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
600 | } | |
601 | ||
602 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
603 | { | |
604 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
605 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
606 | } | |
607 | ||
608 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
609 | { | |
610 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
611 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
612 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
613 | } | |
614 | ||
615 | void intel_encoder_commit (struct drm_encoder *encoder) | |
616 | { | |
617 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
618 | /* lvds has its own version of commit see intel_lvds_commit */ | |
619 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
620 | } | |
621 | ||
622 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, | |
623 | struct drm_display_mode *mode, | |
624 | struct drm_display_mode *adjusted_mode) | |
625 | { | |
626 | return true; | |
627 | } | |
628 | ||
629 | ||
630 | /** Returns the core display clock speed for i830 - i945 */ | |
631 | static int intel_get_core_clock_speed(struct drm_device *dev) | |
632 | { | |
633 | ||
634 | /* Core clock values taken from the published datasheets. | |
635 | * The 830 may go up to 166 Mhz, which we should check. | |
636 | */ | |
637 | if (IS_I945G(dev)) | |
638 | return 400000; | |
639 | else if (IS_I915G(dev)) | |
640 | return 333000; | |
641 | else if (IS_I945GM(dev) || IS_845G(dev)) | |
642 | return 200000; | |
643 | else if (IS_I915GM(dev)) { | |
644 | u16 gcfgc = 0; | |
645 | ||
646 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
647 | ||
648 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
649 | return 133000; | |
650 | else { | |
651 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
652 | case GC_DISPLAY_CLOCK_333_MHZ: | |
653 | return 333000; | |
654 | default: | |
655 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
656 | return 190000; | |
657 | } | |
658 | } | |
659 | } else if (IS_I865G(dev)) | |
660 | return 266000; | |
661 | else if (IS_I855(dev)) { | |
662 | u16 hpllcc = 0; | |
663 | /* Assume that the hardware is in the high speed state. This | |
664 | * should be the default. | |
665 | */ | |
666 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
667 | case GC_CLOCK_133_200: | |
668 | case GC_CLOCK_100_200: | |
669 | return 200000; | |
670 | case GC_CLOCK_166_250: | |
671 | return 250000; | |
672 | case GC_CLOCK_100_133: | |
673 | return 133000; | |
674 | } | |
675 | } else /* 852, 830 */ | |
676 | return 133000; | |
677 | ||
678 | return 0; /* Silence gcc warning */ | |
679 | } | |
680 | ||
681 | ||
682 | /** | |
683 | * Return the pipe currently connected to the panel fitter, | |
684 | * or -1 if the panel fitter is not present or not in use | |
685 | */ | |
686 | static int intel_panel_fitter_pipe (struct drm_device *dev) | |
687 | { | |
688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
689 | u32 pfit_control; | |
690 | ||
691 | /* i830 doesn't have a panel fitter */ | |
692 | if (IS_I830(dev)) | |
693 | return -1; | |
694 | ||
695 | pfit_control = I915_READ(PFIT_CONTROL); | |
696 | ||
697 | /* See if the panel fitter is in use */ | |
698 | if ((pfit_control & PFIT_ENABLE) == 0) | |
699 | return -1; | |
700 | ||
701 | /* 965 can place panel fitter on either pipe */ | |
702 | if (IS_I965G(dev)) | |
703 | return (pfit_control >> 29) & 0x3; | |
704 | ||
705 | /* older chips can only use pipe 1 */ | |
706 | return 1; | |
707 | } | |
708 | ||
709 | static void intel_crtc_mode_set(struct drm_crtc *crtc, | |
710 | struct drm_display_mode *mode, | |
711 | struct drm_display_mode *adjusted_mode, | |
3c4fdcfb KH |
712 | int x, int y, |
713 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
714 | { |
715 | struct drm_device *dev = crtc->dev; | |
716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
717 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
718 | int pipe = intel_crtc->pipe; | |
719 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; | |
720 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
721 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
722 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
723 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
724 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
725 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
726 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
727 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
728 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
729 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
730 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
731 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
732 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
733 | int refclk; | |
734 | intel_clock_t clock; | |
735 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | |
736 | bool ok, is_sdvo = false, is_dvo = false; | |
737 | bool is_crt = false, is_lvds = false, is_tv = false; | |
738 | struct drm_mode_config *mode_config = &dev->mode_config; | |
739 | struct drm_connector *connector; | |
740 | ||
741 | drm_vblank_pre_modeset(dev, pipe); | |
742 | ||
743 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
744 | struct intel_output *intel_output = to_intel_output(connector); | |
745 | ||
746 | if (!connector->encoder || connector->encoder->crtc != crtc) | |
747 | continue; | |
748 | ||
749 | switch (intel_output->type) { | |
750 | case INTEL_OUTPUT_LVDS: | |
751 | is_lvds = true; | |
752 | break; | |
753 | case INTEL_OUTPUT_SDVO: | |
754 | is_sdvo = true; | |
755 | break; | |
756 | case INTEL_OUTPUT_DVO: | |
757 | is_dvo = true; | |
758 | break; | |
759 | case INTEL_OUTPUT_TVOUT: | |
760 | is_tv = true; | |
761 | break; | |
762 | case INTEL_OUTPUT_ANALOG: | |
763 | is_crt = true; | |
764 | break; | |
765 | } | |
766 | } | |
767 | ||
768 | if (IS_I9XX(dev)) { | |
769 | refclk = 96000; | |
770 | } else { | |
771 | refclk = 48000; | |
772 | } | |
773 | ||
774 | ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock); | |
775 | if (!ok) { | |
776 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
777 | return; | |
778 | } | |
779 | ||
780 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
781 | ||
782 | dpll = DPLL_VGA_MODE_DIS; | |
783 | if (IS_I9XX(dev)) { | |
784 | if (is_lvds) | |
785 | dpll |= DPLLB_MODE_LVDS; | |
786 | else | |
787 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
788 | if (is_sdvo) { | |
789 | dpll |= DPLL_DVO_HIGH_SPEED; | |
790 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
791 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
792 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
793 | } | |
794 | } | |
795 | ||
796 | /* compute bitmask from p1 value */ | |
797 | dpll |= (1 << (clock.p1 - 1)) << 16; | |
798 | switch (clock.p2) { | |
799 | case 5: | |
800 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
801 | break; | |
802 | case 7: | |
803 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
804 | break; | |
805 | case 10: | |
806 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
807 | break; | |
808 | case 14: | |
809 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
810 | break; | |
811 | } | |
812 | if (IS_I965G(dev)) | |
813 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
814 | } else { | |
815 | if (is_lvds) { | |
816 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
817 | } else { | |
818 | if (clock.p1 == 2) | |
819 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
820 | else | |
821 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
822 | if (clock.p2 == 4) | |
823 | dpll |= PLL_P2_DIVIDE_BY_4; | |
824 | } | |
825 | } | |
826 | ||
827 | if (is_tv) { | |
828 | /* XXX: just matching BIOS for now */ | |
829 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
830 | dpll |= 3; | |
831 | } | |
832 | else | |
833 | dpll |= PLL_REF_INPUT_DREFCLK; | |
834 | ||
835 | /* setup pipeconf */ | |
836 | pipeconf = I915_READ(pipeconf_reg); | |
837 | ||
838 | /* Set up the display plane register */ | |
839 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
840 | ||
841 | if (pipe == 0) | |
842 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
843 | else | |
844 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
845 | ||
846 | if (pipe == 0 && !IS_I965G(dev)) { | |
847 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
848 | * core speed. | |
849 | * | |
850 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
851 | * pipe == 0 check? | |
852 | */ | |
853 | if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) | |
854 | pipeconf |= PIPEACONF_DOUBLE_WIDE; | |
855 | else | |
856 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
857 | } | |
858 | ||
859 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
860 | pipeconf |= PIPEACONF_ENABLE; | |
861 | dpll |= DPLL_VCO_ENABLE; | |
862 | ||
863 | ||
864 | /* Disable the panel fitter if it was on our pipe */ | |
865 | if (intel_panel_fitter_pipe(dev) == pipe) | |
866 | I915_WRITE(PFIT_CONTROL, 0); | |
867 | ||
868 | DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
869 | drm_mode_debug_printmodeline(mode); | |
870 | ||
871 | ||
872 | if (dpll & DPLL_VCO_ENABLE) { | |
873 | I915_WRITE(fp_reg, fp); | |
874 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
875 | I915_READ(dpll_reg); | |
876 | udelay(150); | |
877 | } | |
878 | ||
879 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
880 | * This is an exception to the general rule that mode_set doesn't turn | |
881 | * things on. | |
882 | */ | |
883 | if (is_lvds) { | |
884 | u32 lvds = I915_READ(LVDS); | |
885 | ||
886 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; | |
887 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
888 | * set the DPLLs for dual-channel mode or not. | |
889 | */ | |
890 | if (clock.p2 == 7) | |
891 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
892 | else | |
893 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
894 | ||
895 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
896 | * appropriately here, but we need to look more thoroughly into how | |
897 | * panels behave in the two modes. | |
898 | */ | |
899 | ||
900 | I915_WRITE(LVDS, lvds); | |
901 | I915_READ(LVDS); | |
902 | } | |
903 | ||
904 | I915_WRITE(fp_reg, fp); | |
905 | I915_WRITE(dpll_reg, dpll); | |
906 | I915_READ(dpll_reg); | |
907 | /* Wait for the clocks to stabilize. */ | |
908 | udelay(150); | |
909 | ||
910 | if (IS_I965G(dev)) { | |
911 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
912 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | | |
913 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | |
914 | } else { | |
915 | /* write it again -- the BIOS does, after all */ | |
916 | I915_WRITE(dpll_reg, dpll); | |
917 | } | |
918 | I915_READ(dpll_reg); | |
919 | /* Wait for the clocks to stabilize. */ | |
920 | udelay(150); | |
921 | ||
922 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | | |
923 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
924 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
925 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
926 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
927 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
928 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
929 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
930 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
931 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
932 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
933 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
934 | /* pipesrc and dspsize control the size that is scaled from, which should | |
935 | * always be the user's requested size. | |
936 | */ | |
937 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); | |
938 | I915_WRITE(dsppos_reg, 0); | |
939 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
940 | I915_WRITE(pipeconf_reg, pipeconf); | |
941 | I915_READ(pipeconf_reg); | |
942 | ||
943 | intel_wait_for_vblank(dev); | |
944 | ||
945 | I915_WRITE(dspcntr_reg, dspcntr); | |
946 | ||
947 | /* Flush the plane changes */ | |
3c4fdcfb | 948 | intel_pipe_set_base(crtc, x, y, old_fb); |
79e53945 JB |
949 | |
950 | drm_vblank_post_modeset(dev, pipe); | |
951 | } | |
952 | ||
953 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
954 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
955 | { | |
956 | struct drm_device *dev = crtc->dev; | |
957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
959 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
960 | int i; | |
961 | ||
962 | /* The clocks have to be on to load the palette. */ | |
963 | if (!crtc->enabled) | |
964 | return; | |
965 | ||
966 | for (i = 0; i < 256; i++) { | |
967 | I915_WRITE(palreg + 4 * i, | |
968 | (intel_crtc->lut_r[i] << 16) | | |
969 | (intel_crtc->lut_g[i] << 8) | | |
970 | intel_crtc->lut_b[i]); | |
971 | } | |
972 | } | |
973 | ||
974 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, | |
975 | struct drm_file *file_priv, | |
976 | uint32_t handle, | |
977 | uint32_t width, uint32_t height) | |
978 | { | |
979 | struct drm_device *dev = crtc->dev; | |
980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
982 | struct drm_gem_object *bo; | |
983 | struct drm_i915_gem_object *obj_priv; | |
984 | int pipe = intel_crtc->pipe; | |
985 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
986 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
987 | uint32_t temp; | |
988 | size_t addr; | |
989 | ||
990 | DRM_DEBUG("\n"); | |
991 | ||
992 | /* if we want to turn off the cursor ignore width and height */ | |
993 | if (!handle) { | |
994 | DRM_DEBUG("cursor off\n"); | |
995 | /* turn of the cursor */ | |
996 | temp = 0; | |
997 | temp |= CURSOR_MODE_DISABLE; | |
998 | ||
999 | I915_WRITE(control, temp); | |
1000 | I915_WRITE(base, 0); | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | /* Currently we only support 64x64 cursors */ | |
1005 | if (width != 64 || height != 64) { | |
1006 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
1007 | return -EINVAL; | |
1008 | } | |
1009 | ||
1010 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
1011 | if (!bo) | |
1012 | return -ENOENT; | |
1013 | ||
1014 | obj_priv = bo->driver_private; | |
1015 | ||
1016 | if (bo->size < width * height * 4) { | |
1017 | DRM_ERROR("buffer is to small\n"); | |
1018 | drm_gem_object_unreference(bo); | |
1019 | return -ENOMEM; | |
1020 | } | |
1021 | ||
1022 | if (dev_priv->cursor_needs_physical) { | |
1023 | addr = dev->agp->base + obj_priv->gtt_offset; | |
1024 | } else { | |
1025 | addr = obj_priv->gtt_offset; | |
1026 | } | |
1027 | ||
1028 | intel_crtc->cursor_addr = addr; | |
1029 | temp = 0; | |
1030 | /* set the pipe for the cursor */ | |
1031 | temp |= (pipe << 28); | |
1032 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
1033 | ||
1034 | I915_WRITE(control, temp); | |
1035 | I915_WRITE(base, addr); | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
1041 | { | |
1042 | struct drm_device *dev = crtc->dev; | |
1043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1045 | int pipe = intel_crtc->pipe; | |
1046 | uint32_t temp = 0; | |
1047 | uint32_t adder; | |
1048 | ||
1049 | if (x < 0) { | |
1050 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | |
1051 | x = -x; | |
1052 | } | |
1053 | if (y < 0) { | |
1054 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | |
1055 | y = -y; | |
1056 | } | |
1057 | ||
1058 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | |
1059 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | |
1060 | ||
1061 | adder = intel_crtc->cursor_addr; | |
1062 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
1063 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | /** Sets the color ramps on behalf of RandR */ | |
1069 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
1070 | u16 blue, int regno) | |
1071 | { | |
1072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1073 | ||
1074 | intel_crtc->lut_r[regno] = red >> 8; | |
1075 | intel_crtc->lut_g[regno] = green >> 8; | |
1076 | intel_crtc->lut_b[regno] = blue >> 8; | |
1077 | } | |
1078 | ||
1079 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
1080 | u16 *blue, uint32_t size) | |
1081 | { | |
1082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1083 | int i; | |
1084 | ||
1085 | if (size != 256) | |
1086 | return; | |
1087 | ||
1088 | for (i = 0; i < 256; i++) { | |
1089 | intel_crtc->lut_r[i] = red[i] >> 8; | |
1090 | intel_crtc->lut_g[i] = green[i] >> 8; | |
1091 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
1092 | } | |
1093 | ||
1094 | intel_crtc_load_lut(crtc); | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
1099 | * detection. | |
1100 | * | |
1101 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
1102 | * its requirements. The pipe will be connected to no other outputs. | |
1103 | * | |
1104 | * Currently this code will only succeed if there is a pipe with no outputs | |
1105 | * configured for it. In the future, it could choose to temporarily disable | |
1106 | * some outputs to free up a pipe for its use. | |
1107 | * | |
1108 | * \return crtc, or NULL if no pipes are available. | |
1109 | */ | |
1110 | ||
1111 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
1112 | static struct drm_display_mode load_detect_mode = { | |
1113 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
1114 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
1115 | }; | |
1116 | ||
1117 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, | |
1118 | struct drm_display_mode *mode, | |
1119 | int *dpms_mode) | |
1120 | { | |
1121 | struct intel_crtc *intel_crtc; | |
1122 | struct drm_crtc *possible_crtc; | |
1123 | struct drm_crtc *supported_crtc =NULL; | |
1124 | struct drm_encoder *encoder = &intel_output->enc; | |
1125 | struct drm_crtc *crtc = NULL; | |
1126 | struct drm_device *dev = encoder->dev; | |
1127 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1128 | struct drm_crtc_helper_funcs *crtc_funcs; | |
1129 | int i = -1; | |
1130 | ||
1131 | /* | |
1132 | * Algorithm gets a little messy: | |
1133 | * - if the connector already has an assigned crtc, use it (but make | |
1134 | * sure it's on first) | |
1135 | * - try to find the first unused crtc that can drive this connector, | |
1136 | * and use that if we find one | |
1137 | * - if there are no unused crtcs available, try to use the first | |
1138 | * one we found that supports the connector | |
1139 | */ | |
1140 | ||
1141 | /* See if we already have a CRTC for this connector */ | |
1142 | if (encoder->crtc) { | |
1143 | crtc = encoder->crtc; | |
1144 | /* Make sure the crtc and connector are running */ | |
1145 | intel_crtc = to_intel_crtc(crtc); | |
1146 | *dpms_mode = intel_crtc->dpms_mode; | |
1147 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
1148 | crtc_funcs = crtc->helper_private; | |
1149 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1150 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
1151 | } | |
1152 | return crtc; | |
1153 | } | |
1154 | ||
1155 | /* Find an unused one (if possible) */ | |
1156 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
1157 | i++; | |
1158 | if (!(encoder->possible_crtcs & (1 << i))) | |
1159 | continue; | |
1160 | if (!possible_crtc->enabled) { | |
1161 | crtc = possible_crtc; | |
1162 | break; | |
1163 | } | |
1164 | if (!supported_crtc) | |
1165 | supported_crtc = possible_crtc; | |
1166 | } | |
1167 | ||
1168 | /* | |
1169 | * If we didn't find an unused CRTC, don't use any. | |
1170 | */ | |
1171 | if (!crtc) { | |
1172 | return NULL; | |
1173 | } | |
1174 | ||
1175 | encoder->crtc = crtc; | |
1176 | intel_output->load_detect_temp = true; | |
1177 | ||
1178 | intel_crtc = to_intel_crtc(crtc); | |
1179 | *dpms_mode = intel_crtc->dpms_mode; | |
1180 | ||
1181 | if (!crtc->enabled) { | |
1182 | if (!mode) | |
1183 | mode = &load_detect_mode; | |
3c4fdcfb | 1184 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
1185 | } else { |
1186 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
1187 | crtc_funcs = crtc->helper_private; | |
1188 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1189 | } | |
1190 | ||
1191 | /* Add this connector to the crtc */ | |
1192 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
1193 | encoder_funcs->commit(encoder); | |
1194 | } | |
1195 | /* let the connector get through one full cycle before testing */ | |
1196 | intel_wait_for_vblank(dev); | |
1197 | ||
1198 | return crtc; | |
1199 | } | |
1200 | ||
1201 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) | |
1202 | { | |
1203 | struct drm_encoder *encoder = &intel_output->enc; | |
1204 | struct drm_device *dev = encoder->dev; | |
1205 | struct drm_crtc *crtc = encoder->crtc; | |
1206 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1207 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1208 | ||
1209 | if (intel_output->load_detect_temp) { | |
1210 | encoder->crtc = NULL; | |
1211 | intel_output->load_detect_temp = false; | |
1212 | crtc->enabled = drm_helper_crtc_in_use(crtc); | |
1213 | drm_helper_disable_unused_functions(dev); | |
1214 | } | |
1215 | ||
1216 | /* Switch crtc and output back off if necessary */ | |
1217 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { | |
1218 | if (encoder->crtc == crtc) | |
1219 | encoder_funcs->dpms(encoder, dpms_mode); | |
1220 | crtc_funcs->dpms(crtc, dpms_mode); | |
1221 | } | |
1222 | } | |
1223 | ||
1224 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
1225 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
1226 | { | |
1227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1229 | int pipe = intel_crtc->pipe; | |
1230 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
1231 | u32 fp; | |
1232 | intel_clock_t clock; | |
1233 | ||
1234 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
1235 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
1236 | else | |
1237 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
1238 | ||
1239 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
1240 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
1241 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
1242 | if (IS_I9XX(dev)) { | |
1243 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
1244 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
1245 | ||
1246 | switch (dpll & DPLL_MODE_MASK) { | |
1247 | case DPLLB_MODE_DAC_SERIAL: | |
1248 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
1249 | 5 : 10; | |
1250 | break; | |
1251 | case DPLLB_MODE_LVDS: | |
1252 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
1253 | 7 : 14; | |
1254 | break; | |
1255 | default: | |
1256 | DRM_DEBUG("Unknown DPLL mode %08x in programmed " | |
1257 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | /* XXX: Handle the 100Mhz refclk */ | |
1262 | i9xx_clock(96000, &clock); | |
1263 | } else { | |
1264 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
1265 | ||
1266 | if (is_lvds) { | |
1267 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
1268 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
1269 | clock.p2 = 14; | |
1270 | ||
1271 | if ((dpll & PLL_REF_INPUT_MASK) == | |
1272 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
1273 | /* XXX: might not be 66MHz */ | |
1274 | i8xx_clock(66000, &clock); | |
1275 | } else | |
1276 | i8xx_clock(48000, &clock); | |
1277 | } else { | |
1278 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
1279 | clock.p1 = 2; | |
1280 | else { | |
1281 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
1282 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
1283 | } | |
1284 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
1285 | clock.p2 = 4; | |
1286 | else | |
1287 | clock.p2 = 2; | |
1288 | ||
1289 | i8xx_clock(48000, &clock); | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
1294 | * i830PllIsValid() because it relies on the xf86_config connector | |
1295 | * configuration being accurate, which it isn't necessarily. | |
1296 | */ | |
1297 | ||
1298 | return clock.dot; | |
1299 | } | |
1300 | ||
1301 | /** Returns the currently programmed mode of the given pipe. */ | |
1302 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1303 | struct drm_crtc *crtc) | |
1304 | { | |
1305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1307 | int pipe = intel_crtc->pipe; | |
1308 | struct drm_display_mode *mode; | |
1309 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
1310 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
1311 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
1312 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
1313 | ||
1314 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
1315 | if (!mode) | |
1316 | return NULL; | |
1317 | ||
1318 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
1319 | mode->hdisplay = (htot & 0xffff) + 1; | |
1320 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
1321 | mode->hsync_start = (hsync & 0xffff) + 1; | |
1322 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
1323 | mode->vdisplay = (vtot & 0xffff) + 1; | |
1324 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
1325 | mode->vsync_start = (vsync & 0xffff) + 1; | |
1326 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
1327 | ||
1328 | drm_mode_set_name(mode); | |
1329 | drm_mode_set_crtcinfo(mode, 0); | |
1330 | ||
1331 | return mode; | |
1332 | } | |
1333 | ||
1334 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
1335 | { | |
1336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1337 | ||
1338 | drm_crtc_cleanup(crtc); | |
1339 | kfree(intel_crtc); | |
1340 | } | |
1341 | ||
1342 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
1343 | .dpms = intel_crtc_dpms, | |
1344 | .mode_fixup = intel_crtc_mode_fixup, | |
1345 | .mode_set = intel_crtc_mode_set, | |
1346 | .mode_set_base = intel_pipe_set_base, | |
1347 | .prepare = intel_crtc_prepare, | |
1348 | .commit = intel_crtc_commit, | |
1349 | }; | |
1350 | ||
1351 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
1352 | .cursor_set = intel_crtc_cursor_set, | |
1353 | .cursor_move = intel_crtc_cursor_move, | |
1354 | .gamma_set = intel_crtc_gamma_set, | |
1355 | .set_config = drm_crtc_helper_set_config, | |
1356 | .destroy = intel_crtc_destroy, | |
1357 | }; | |
1358 | ||
1359 | ||
b358d0a6 | 1360 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 JB |
1361 | { |
1362 | struct intel_crtc *intel_crtc; | |
1363 | int i; | |
1364 | ||
1365 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
1366 | if (intel_crtc == NULL) | |
1367 | return; | |
1368 | ||
1369 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
1370 | ||
1371 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
1372 | intel_crtc->pipe = pipe; | |
1373 | for (i = 0; i < 256; i++) { | |
1374 | intel_crtc->lut_r[i] = i; | |
1375 | intel_crtc->lut_g[i] = i; | |
1376 | intel_crtc->lut_b[i] = i; | |
1377 | } | |
1378 | ||
1379 | intel_crtc->cursor_addr = 0; | |
1380 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
1381 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
1382 | ||
1383 | intel_crtc->mode_set.crtc = &intel_crtc->base; | |
1384 | intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); | |
1385 | intel_crtc->mode_set.num_connectors = 0; | |
1386 | ||
1387 | if (i915_fbpercrtc) { | |
1388 | ||
1389 | ||
1390 | ||
1391 | } | |
1392 | } | |
1393 | ||
1394 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) | |
1395 | { | |
1396 | struct drm_crtc *crtc = NULL; | |
1397 | ||
1398 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1400 | if (intel_crtc->pipe == pipe) | |
1401 | break; | |
1402 | } | |
1403 | return crtc; | |
1404 | } | |
1405 | ||
b358d0a6 | 1406 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
79e53945 JB |
1407 | { |
1408 | int index_mask = 0; | |
1409 | struct drm_connector *connector; | |
1410 | int entry = 0; | |
1411 | ||
1412 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1413 | struct intel_output *intel_output = to_intel_output(connector); | |
1414 | if (type_mask & (1 << intel_output->type)) | |
1415 | index_mask |= (1 << entry); | |
1416 | entry++; | |
1417 | } | |
1418 | return index_mask; | |
1419 | } | |
1420 | ||
1421 | ||
1422 | static void intel_setup_outputs(struct drm_device *dev) | |
1423 | { | |
1424 | struct drm_connector *connector; | |
1425 | ||
1426 | intel_crt_init(dev); | |
1427 | ||
1428 | /* Set up integrated LVDS */ | |
1429 | if (IS_MOBILE(dev) && !IS_I830(dev)) | |
1430 | intel_lvds_init(dev); | |
1431 | ||
1432 | if (IS_I9XX(dev)) { | |
1433 | intel_sdvo_init(dev, SDVOB); | |
1434 | intel_sdvo_init(dev, SDVOC); | |
1435 | } else | |
1436 | intel_dvo_init(dev); | |
1437 | ||
1438 | if (IS_I9XX(dev) && !IS_I915G(dev)) | |
1439 | intel_tv_init(dev); | |
1440 | ||
1441 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1442 | struct intel_output *intel_output = to_intel_output(connector); | |
1443 | struct drm_encoder *encoder = &intel_output->enc; | |
1444 | int crtc_mask = 0, clone_mask = 0; | |
1445 | ||
1446 | /* valid crtcs */ | |
1447 | switch(intel_output->type) { | |
1448 | case INTEL_OUTPUT_DVO: | |
1449 | case INTEL_OUTPUT_SDVO: | |
1450 | crtc_mask = ((1 << 0)| | |
1451 | (1 << 1)); | |
1452 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
1453 | (1 << INTEL_OUTPUT_DVO) | | |
1454 | (1 << INTEL_OUTPUT_SDVO)); | |
1455 | break; | |
1456 | case INTEL_OUTPUT_ANALOG: | |
1457 | crtc_mask = ((1 << 0)| | |
1458 | (1 << 1)); | |
1459 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
1460 | (1 << INTEL_OUTPUT_DVO) | | |
1461 | (1 << INTEL_OUTPUT_SDVO)); | |
1462 | break; | |
1463 | case INTEL_OUTPUT_LVDS: | |
1464 | crtc_mask = (1 << 1); | |
1465 | clone_mask = (1 << INTEL_OUTPUT_LVDS); | |
1466 | break; | |
1467 | case INTEL_OUTPUT_TVOUT: | |
1468 | crtc_mask = ((1 << 0) | | |
1469 | (1 << 1)); | |
1470 | clone_mask = (1 << INTEL_OUTPUT_TVOUT); | |
1471 | break; | |
1472 | } | |
1473 | encoder->possible_crtcs = crtc_mask; | |
1474 | encoder->possible_clones = intel_connector_clones(dev, clone_mask); | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
1479 | { | |
1480 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1481 | struct drm_device *dev = fb->dev; | |
1482 | ||
1483 | if (fb->fbdev) | |
1484 | intelfb_remove(dev, fb); | |
1485 | ||
1486 | drm_framebuffer_cleanup(fb); | |
1487 | mutex_lock(&dev->struct_mutex); | |
1488 | drm_gem_object_unreference(intel_fb->obj); | |
1489 | mutex_unlock(&dev->struct_mutex); | |
1490 | ||
1491 | kfree(intel_fb); | |
1492 | } | |
1493 | ||
1494 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
1495 | struct drm_file *file_priv, | |
1496 | unsigned int *handle) | |
1497 | { | |
1498 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1499 | struct drm_gem_object *object = intel_fb->obj; | |
1500 | ||
1501 | return drm_gem_handle_create(file_priv, object, handle); | |
1502 | } | |
1503 | ||
1504 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
1505 | .destroy = intel_user_framebuffer_destroy, | |
1506 | .create_handle = intel_user_framebuffer_create_handle, | |
1507 | }; | |
1508 | ||
1509 | int intel_framebuffer_create(struct drm_device *dev, | |
1510 | struct drm_mode_fb_cmd *mode_cmd, | |
1511 | struct drm_framebuffer **fb, | |
1512 | struct drm_gem_object *obj) | |
1513 | { | |
1514 | struct intel_framebuffer *intel_fb; | |
1515 | int ret; | |
1516 | ||
1517 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
1518 | if (!intel_fb) | |
1519 | return -ENOMEM; | |
1520 | ||
1521 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
1522 | if (ret) { | |
1523 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
1524 | return ret; | |
1525 | } | |
1526 | ||
1527 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
1528 | ||
1529 | intel_fb->obj = obj; | |
1530 | ||
1531 | *fb = &intel_fb->base; | |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | ||
1537 | static struct drm_framebuffer * | |
1538 | intel_user_framebuffer_create(struct drm_device *dev, | |
1539 | struct drm_file *filp, | |
1540 | struct drm_mode_fb_cmd *mode_cmd) | |
1541 | { | |
1542 | struct drm_gem_object *obj; | |
1543 | struct drm_framebuffer *fb; | |
1544 | int ret; | |
1545 | ||
1546 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
1547 | if (!obj) | |
1548 | return NULL; | |
1549 | ||
1550 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); | |
1551 | if (ret) { | |
1552 | drm_gem_object_unreference(obj); | |
1553 | return NULL; | |
1554 | } | |
1555 | ||
1556 | return fb; | |
1557 | } | |
1558 | ||
79e53945 | 1559 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 JB |
1560 | .fb_create = intel_user_framebuffer_create, |
1561 | .fb_changed = intelfb_probe, | |
1562 | }; | |
1563 | ||
1564 | void intel_modeset_init(struct drm_device *dev) | |
1565 | { | |
1566 | int num_pipe; | |
1567 | int i; | |
1568 | ||
1569 | drm_mode_config_init(dev); | |
1570 | ||
1571 | dev->mode_config.min_width = 0; | |
1572 | dev->mode_config.min_height = 0; | |
1573 | ||
1574 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
1575 | ||
1576 | if (IS_I965G(dev)) { | |
1577 | dev->mode_config.max_width = 8192; | |
1578 | dev->mode_config.max_height = 8192; | |
1579 | } else { | |
1580 | dev->mode_config.max_width = 2048; | |
1581 | dev->mode_config.max_height = 2048; | |
1582 | } | |
1583 | ||
1584 | /* set memory base */ | |
1585 | if (IS_I9XX(dev)) | |
1586 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
1587 | else | |
1588 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
1589 | ||
1590 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
1591 | num_pipe = 2; | |
1592 | else | |
1593 | num_pipe = 1; | |
1594 | DRM_DEBUG("%d display pipe%s available.\n", | |
1595 | num_pipe, num_pipe > 1 ? "s" : ""); | |
1596 | ||
1597 | for (i = 0; i < num_pipe; i++) { | |
1598 | intel_crtc_init(dev, i); | |
1599 | } | |
1600 | ||
1601 | intel_setup_outputs(dev); | |
1602 | } | |
1603 | ||
1604 | void intel_modeset_cleanup(struct drm_device *dev) | |
1605 | { | |
1606 | drm_mode_config_cleanup(dev); | |
1607 | } | |
1608 | ||
1609 | ||
1610 | /* current intel driver doesn't take advantage of encoders | |
1611 | always give back the encoder for the connector | |
1612 | */ | |
1613 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
1614 | { | |
1615 | struct intel_output *intel_output = to_intel_output(connector); | |
1616 | ||
1617 | return &intel_output->enc; | |
1618 | } |