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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
349 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
350 | } | |
351 | ||
e4b36699 | 352 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
353 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
354 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
355 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
356 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
357 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
358 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
359 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
360 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
361 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
362 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 363 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
364 | }; |
365 | ||
366 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
367 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
368 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
369 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
370 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
371 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
372 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
373 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
374 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
375 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
376 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 377 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
378 | }; |
379 | ||
380 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
381 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
382 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
383 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
384 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
385 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
386 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
387 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
388 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
389 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
390 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 391 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
392 | }; |
393 | ||
394 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
395 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
396 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
397 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
398 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
399 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
400 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
401 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
402 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
403 | /* The single-channel range is 25-112Mhz, and dual-channel | |
404 | * is 80-224Mhz. Prefer single channel as much as possible. | |
405 | */ | |
406 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
407 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 408 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
409 | }; |
410 | ||
044c7c41 | 411 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 412 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
413 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
414 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
415 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
416 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
417 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
418 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
419 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
420 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
421 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
422 | .p2_slow = G4X_P2_SDVO_SLOW, | |
423 | .p2_fast = G4X_P2_SDVO_FAST | |
424 | }, | |
d4906093 | 425 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
426 | }; |
427 | ||
428 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
429 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
430 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
431 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
432 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
433 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
434 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
435 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
436 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
437 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
438 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
439 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
440 | }, | |
d4906093 | 441 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
445 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
446 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
447 | .vco = { .min = G4X_VCO_MIN, | |
448 | .max = G4X_VCO_MAX }, | |
449 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
450 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
451 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
452 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
453 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
454 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
455 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
456 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
457 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
458 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
459 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
460 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
461 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
462 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
463 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
464 | }, | |
d4906093 | 465 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
466 | }; |
467 | ||
468 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
469 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
470 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
471 | .vco = { .min = G4X_VCO_MIN, | |
472 | .max = G4X_VCO_MAX }, | |
473 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
474 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
475 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
476 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
477 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
478 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
479 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
480 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
481 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
482 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
483 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
484 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
485 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
486 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
487 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
488 | }, | |
d4906093 | 489 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
490 | }; |
491 | ||
492 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
493 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
494 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
495 | .vco = { .min = G4X_VCO_MIN, | |
496 | .max = G4X_VCO_MAX}, | |
497 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
498 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
499 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
500 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
501 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
502 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
503 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
504 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
505 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
506 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
507 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
508 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
509 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
510 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
511 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
512 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
513 | }; |
514 | ||
f2b115e6 | 515 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 516 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
517 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
518 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
519 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
520 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
521 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
522 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
523 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
524 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
525 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 526 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
527 | }; |
528 | ||
f2b115e6 | 529 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 530 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
531 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
532 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
533 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
534 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
535 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
536 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 537 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 538 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
539 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
540 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 541 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
542 | }; |
543 | ||
b91ad0ec | 544 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
545 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
546 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
547 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
548 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
549 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
550 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
551 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
552 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 553 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
554 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
555 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 556 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
557 | }; |
558 | ||
b91ad0ec | 559 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
560 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
561 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
562 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
563 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
564 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
565 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
566 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
567 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 568 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
569 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
570 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
571 | .find_pll = intel_g4x_find_best_PLL, | |
572 | }; | |
573 | ||
574 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
575 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
576 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
577 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
578 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
579 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
580 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
581 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
582 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
583 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
584 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
585 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
586 | .find_pll = intel_g4x_find_best_PLL, | |
587 | }; | |
588 | ||
589 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
590 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
591 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
592 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
593 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
594 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
595 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
596 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
597 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
598 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
599 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
600 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
601 | .find_pll = intel_g4x_find_best_PLL, | |
602 | }; | |
603 | ||
604 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
605 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
606 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
607 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
608 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
609 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
610 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
611 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
612 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
613 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
614 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
615 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
616 | .find_pll = intel_g4x_find_best_PLL, |
617 | }; | |
618 | ||
619 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
620 | .dot = { .min = IRONLAKE_DOT_MIN, | |
621 | .max = IRONLAKE_DOT_MAX }, | |
622 | .vco = { .min = IRONLAKE_VCO_MIN, | |
623 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
624 | .n = { .min = IRONLAKE_DP_N_MIN, |
625 | .max = IRONLAKE_DP_N_MAX }, | |
626 | .m = { .min = IRONLAKE_DP_M_MIN, | |
627 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
628 | .m1 = { .min = IRONLAKE_M1_MIN, |
629 | .max = IRONLAKE_M1_MAX }, | |
630 | .m2 = { .min = IRONLAKE_M2_MIN, | |
631 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
632 | .p = { .min = IRONLAKE_DP_P_MIN, |
633 | .max = IRONLAKE_DP_P_MAX }, | |
634 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
635 | .max = IRONLAKE_DP_P1_MAX}, | |
636 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
637 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
638 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 639 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
640 | }; |
641 | ||
f2b115e6 | 642 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
2c07245f | 643 | { |
b91ad0ec ZW |
644 | struct drm_device *dev = crtc->dev; |
645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 646 | const intel_limit_t *limit; |
b91ad0ec ZW |
647 | int refclk = 120; |
648 | ||
649 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
650 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) | |
651 | refclk = 100; | |
652 | ||
653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == | |
654 | LVDS_CLKB_POWER_UP) { | |
655 | /* LVDS dual channel */ | |
656 | if (refclk == 100) | |
657 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
658 | else | |
659 | limit = &intel_limits_ironlake_dual_lvds; | |
660 | } else { | |
661 | if (refclk == 100) | |
662 | limit = &intel_limits_ironlake_single_lvds_100m; | |
663 | else | |
664 | limit = &intel_limits_ironlake_single_lvds; | |
665 | } | |
666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
667 | HAS_eDP) |
668 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 669 | else |
b91ad0ec | 670 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
671 | |
672 | return limit; | |
673 | } | |
674 | ||
044c7c41 ML |
675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
676 | { | |
677 | struct drm_device *dev = crtc->dev; | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | const intel_limit_t *limit; | |
680 | ||
681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
683 | LVDS_CLKB_POWER_UP) | |
684 | /* LVDS with dual channel */ | |
e4b36699 | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
686 | else |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 691 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 693 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 695 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 696 | } else /* The option is for other outputs */ |
e4b36699 | 697 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
698 | |
699 | return limit; | |
700 | } | |
701 | ||
79e53945 JB |
702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
703 | { | |
704 | struct drm_device *dev = crtc->dev; | |
705 | const intel_limit_t *limit; | |
706 | ||
bad720ff | 707 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 708 | limit = intel_ironlake_limit(crtc); |
2c07245f | 709 | else if (IS_G4X(dev)) { |
044c7c41 | 710 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 711 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 713 | limit = &intel_limits_pineview_lvds; |
2177832f | 714 | else |
f2b115e6 | 715 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
716 | } else if (!IS_GEN2(dev)) { |
717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
718 | limit = &intel_limits_i9xx_lvds; | |
719 | else | |
720 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
721 | } else { |
722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 723 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 724 | else |
e4b36699 | 725 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
726 | } |
727 | return limit; | |
728 | } | |
729 | ||
f2b115e6 AJ |
730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
731 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 732 | { |
2177832f SL |
733 | clock->m = clock->m2 + 2; |
734 | clock->p = clock->p1 * clock->p2; | |
735 | clock->vco = refclk * clock->m / clock->n; | |
736 | clock->dot = clock->vco / clock->p; | |
737 | } | |
738 | ||
739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
740 | { | |
f2b115e6 AJ |
741 | if (IS_PINEVIEW(dev)) { |
742 | pineview_clock(refclk, clock); | |
2177832f SL |
743 | return; |
744 | } | |
79e53945 JB |
745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
746 | clock->p = clock->p1 * clock->p2; | |
747 | clock->vco = refclk * clock->m / (clock->n + 2); | |
748 | clock->dot = clock->vco / clock->p; | |
749 | } | |
750 | ||
79e53945 JB |
751 | /** |
752 | * Returns whether any output on the specified pipe is of the specified type | |
753 | */ | |
4ef69c7a | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 755 | { |
4ef69c7a CW |
756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_mode_config *mode_config = &dev->mode_config; | |
758 | struct intel_encoder *encoder; | |
759 | ||
760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
761 | if (encoder->base.crtc == crtc && encoder->type == type) | |
762 | return true; | |
763 | ||
764 | return false; | |
79e53945 JB |
765 | } |
766 | ||
7c04d1d9 | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
768 | /** |
769 | * Returns whether the given set of divisors are valid for a given refclk with | |
770 | * the given connectors. | |
771 | */ | |
772 | ||
773 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
774 | { | |
775 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 776 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
777 | |
778 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
779 | INTELPllInvalid ("p1 out of range\n"); | |
780 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
781 | INTELPllInvalid ("p out of range\n"); | |
782 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
783 | INTELPllInvalid ("m2 out of range\n"); | |
784 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
785 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 786 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
787 | INTELPllInvalid ("m1 <= m2\n"); |
788 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
789 | INTELPllInvalid ("m out of range\n"); | |
790 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
791 | INTELPllInvalid ("n out of range\n"); | |
792 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
793 | INTELPllInvalid ("vco out of range\n"); | |
794 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
795 | * connector, etc., rather than just a single range. | |
796 | */ | |
797 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
798 | INTELPllInvalid ("dot out of range\n"); | |
799 | ||
800 | return true; | |
801 | } | |
802 | ||
d4906093 ML |
803 | static bool |
804 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
805 | int target, int refclk, intel_clock_t *best_clock) | |
806 | ||
79e53945 JB |
807 | { |
808 | struct drm_device *dev = crtc->dev; | |
809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
810 | intel_clock_t clock; | |
79e53945 JB |
811 | int err = target; |
812 | ||
bc5e5718 | 813 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 814 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
815 | /* |
816 | * For LVDS, if the panel is on, just rely on its current | |
817 | * settings for dual-channel. We haven't figured out how to | |
818 | * reliably set up different single/dual channel state, if we | |
819 | * even can. | |
820 | */ | |
821 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
822 | LVDS_CLKB_POWER_UP) | |
823 | clock.p2 = limit->p2.p2_fast; | |
824 | else | |
825 | clock.p2 = limit->p2.p2_slow; | |
826 | } else { | |
827 | if (target < limit->p2.dot_limit) | |
828 | clock.p2 = limit->p2.p2_slow; | |
829 | else | |
830 | clock.p2 = limit->p2.p2_fast; | |
831 | } | |
832 | ||
833 | memset (best_clock, 0, sizeof (*best_clock)); | |
834 | ||
42158660 ZY |
835 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
836 | clock.m1++) { | |
837 | for (clock.m2 = limit->m2.min; | |
838 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
839 | /* m1 is always 0 in Pineview */ |
840 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
841 | break; |
842 | for (clock.n = limit->n.min; | |
843 | clock.n <= limit->n.max; clock.n++) { | |
844 | for (clock.p1 = limit->p1.min; | |
845 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
846 | int this_err; |
847 | ||
2177832f | 848 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
849 | |
850 | if (!intel_PLL_is_valid(crtc, &clock)) | |
851 | continue; | |
852 | ||
853 | this_err = abs(clock.dot - target); | |
854 | if (this_err < err) { | |
855 | *best_clock = clock; | |
856 | err = this_err; | |
857 | } | |
858 | } | |
859 | } | |
860 | } | |
861 | } | |
862 | ||
863 | return (err != target); | |
864 | } | |
865 | ||
d4906093 ML |
866 | static bool |
867 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
868 | int target, int refclk, intel_clock_t *best_clock) | |
869 | { | |
870 | struct drm_device *dev = crtc->dev; | |
871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
872 | intel_clock_t clock; | |
873 | int max_n; | |
874 | bool found; | |
6ba770dc AJ |
875 | /* approximately equals target * 0.00585 */ |
876 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
877 | found = false; |
878 | ||
879 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
880 | int lvds_reg; |
881 | ||
c619eed4 | 882 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
883 | lvds_reg = PCH_LVDS; |
884 | else | |
885 | lvds_reg = LVDS; | |
886 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
887 | LVDS_CLKB_POWER_UP) |
888 | clock.p2 = limit->p2.p2_fast; | |
889 | else | |
890 | clock.p2 = limit->p2.p2_slow; | |
891 | } else { | |
892 | if (target < limit->p2.dot_limit) | |
893 | clock.p2 = limit->p2.p2_slow; | |
894 | else | |
895 | clock.p2 = limit->p2.p2_fast; | |
896 | } | |
897 | ||
898 | memset(best_clock, 0, sizeof(*best_clock)); | |
899 | max_n = limit->n.max; | |
f77f13e2 | 900 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 901 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 902 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
903 | for (clock.m1 = limit->m1.max; |
904 | clock.m1 >= limit->m1.min; clock.m1--) { | |
905 | for (clock.m2 = limit->m2.max; | |
906 | clock.m2 >= limit->m2.min; clock.m2--) { | |
907 | for (clock.p1 = limit->p1.max; | |
908 | clock.p1 >= limit->p1.min; clock.p1--) { | |
909 | int this_err; | |
910 | ||
2177832f | 911 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
912 | if (!intel_PLL_is_valid(crtc, &clock)) |
913 | continue; | |
914 | this_err = abs(clock.dot - target) ; | |
915 | if (this_err < err_most) { | |
916 | *best_clock = clock; | |
917 | err_most = this_err; | |
918 | max_n = clock.n; | |
919 | found = true; | |
920 | } | |
921 | } | |
922 | } | |
923 | } | |
924 | } | |
2c07245f ZW |
925 | return found; |
926 | } | |
927 | ||
5eb08b69 | 928 | static bool |
f2b115e6 AJ |
929 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
930 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
931 | { |
932 | struct drm_device *dev = crtc->dev; | |
933 | intel_clock_t clock; | |
4547668a | 934 | |
5eb08b69 ZW |
935 | if (target < 200000) { |
936 | clock.n = 1; | |
937 | clock.p1 = 2; | |
938 | clock.p2 = 10; | |
939 | clock.m1 = 12; | |
940 | clock.m2 = 9; | |
941 | } else { | |
942 | clock.n = 2; | |
943 | clock.p1 = 1; | |
944 | clock.p2 = 10; | |
945 | clock.m1 = 14; | |
946 | clock.m2 = 8; | |
947 | } | |
948 | intel_clock(dev, refclk, &clock); | |
949 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
950 | return true; | |
951 | } | |
952 | ||
a4fc5ed6 KP |
953 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
954 | static bool | |
955 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
956 | int target, int refclk, intel_clock_t *best_clock) | |
957 | { | |
5eddb70b CW |
958 | intel_clock_t clock; |
959 | if (target < 200000) { | |
960 | clock.p1 = 2; | |
961 | clock.p2 = 10; | |
962 | clock.n = 2; | |
963 | clock.m1 = 23; | |
964 | clock.m2 = 8; | |
965 | } else { | |
966 | clock.p1 = 1; | |
967 | clock.p2 = 10; | |
968 | clock.n = 1; | |
969 | clock.m1 = 14; | |
970 | clock.m2 = 2; | |
971 | } | |
972 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
973 | clock.p = (clock.p1 * clock.p2); | |
974 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
975 | clock.vco = 0; | |
976 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
977 | return true; | |
a4fc5ed6 KP |
978 | } |
979 | ||
9d0498a2 JB |
980 | /** |
981 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
982 | * @dev: drm device | |
983 | * @pipe: pipe to wait for | |
984 | * | |
985 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
986 | * mode setting code. | |
987 | */ | |
988 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 989 | { |
9d0498a2 JB |
990 | struct drm_i915_private *dev_priv = dev->dev_private; |
991 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
992 | ||
300387c0 CW |
993 | /* Clear existing vblank status. Note this will clear any other |
994 | * sticky status fields as well. | |
995 | * | |
996 | * This races with i915_driver_irq_handler() with the result | |
997 | * that either function could miss a vblank event. Here it is not | |
998 | * fatal, as we will either wait upon the next vblank interrupt or | |
999 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1000 | * called during modeset at which time the GPU should be idle and | |
1001 | * should *not* be performing page flips and thus not waiting on | |
1002 | * vblanks... | |
1003 | * Currently, the result of us stealing a vblank from the irq | |
1004 | * handler is that a single frame will be skipped during swapbuffers. | |
1005 | */ | |
1006 | I915_WRITE(pipestat_reg, | |
1007 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1008 | ||
9d0498a2 | 1009 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1010 | if (wait_for(I915_READ(pipestat_reg) & |
1011 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1012 | 50)) | |
9d0498a2 JB |
1013 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1014 | } | |
1015 | ||
ab7ad7f6 KP |
1016 | /* |
1017 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
1018 | * @dev: drm device |
1019 | * @pipe: pipe to wait for | |
1020 | * | |
1021 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1022 | * spinning on the vblank interrupt status bit, since we won't actually | |
1023 | * see an interrupt when the pipe is disabled. | |
1024 | * | |
ab7ad7f6 KP |
1025 | * On Gen4 and above: |
1026 | * wait for the pipe register state bit to turn off | |
1027 | * | |
1028 | * Otherwise: | |
1029 | * wait for the display line value to settle (it usually | |
1030 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1031 | * |
9d0498a2 | 1032 | */ |
58e10eb9 | 1033 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1034 | { |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1036 | |
1037 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1038 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1039 | |
1040 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1041 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1042 | 100)) | |
ab7ad7f6 KP |
1043 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1044 | } else { | |
1045 | u32 last_line; | |
58e10eb9 | 1046 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1047 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1048 | ||
1049 | /* Wait for the display line to settle */ | |
1050 | do { | |
58e10eb9 | 1051 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 1052 | mdelay(5); |
58e10eb9 | 1053 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
1054 | time_after(timeout, jiffies)); |
1055 | if (time_after(jiffies, timeout)) | |
1056 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1057 | } | |
79e53945 JB |
1058 | } |
1059 | ||
80824003 JB |
1060 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1061 | { | |
1062 | struct drm_device *dev = crtc->dev; | |
1063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1064 | struct drm_framebuffer *fb = crtc->fb; | |
1065 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1066 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
80824003 JB |
1067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1068 | int plane, i; | |
1069 | u32 fbc_ctl, fbc_ctl2; | |
1070 | ||
bed4a673 CW |
1071 | if (fb->pitch == dev_priv->cfb_pitch && |
1072 | obj_priv->fence_reg == dev_priv->cfb_fence && | |
1073 | intel_crtc->plane == dev_priv->cfb_plane && | |
1074 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1075 | return; | |
1076 | ||
1077 | i8xx_disable_fbc(dev); | |
1078 | ||
80824003 JB |
1079 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1080 | ||
1081 | if (fb->pitch < dev_priv->cfb_pitch) | |
1082 | dev_priv->cfb_pitch = fb->pitch; | |
1083 | ||
1084 | /* FBC_CTL wants 64B units */ | |
1085 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
1086 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1087 | dev_priv->cfb_plane = intel_crtc->plane; | |
1088 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1089 | ||
1090 | /* Clear old tags */ | |
1091 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1092 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1093 | ||
1094 | /* Set it up... */ | |
1095 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
1096 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1097 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; | |
1098 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1099 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1100 | ||
1101 | /* enable it... */ | |
1102 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1103 | if (IS_I945GM(dev)) |
49677901 | 1104 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1105 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1106 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
1107 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1108 | fbc_ctl |= dev_priv->cfb_fence; | |
1109 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1110 | ||
28c97730 | 1111 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1112 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1113 | } |
1114 | ||
1115 | void i8xx_disable_fbc(struct drm_device *dev) | |
1116 | { | |
1117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1118 | u32 fbc_ctl; | |
1119 | ||
1120 | /* Disable compression */ | |
1121 | fbc_ctl = I915_READ(FBC_CONTROL); | |
a5cad620 CW |
1122 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
1123 | return; | |
1124 | ||
80824003 JB |
1125 | fbc_ctl &= ~FBC_CTL_EN; |
1126 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1127 | ||
1128 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1129 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1130 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1131 | return; | |
9517a92f | 1132 | } |
80824003 | 1133 | |
28c97730 | 1134 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1135 | } |
1136 | ||
ee5382ae | 1137 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1138 | { |
80824003 JB |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
1140 | ||
1141 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1142 | } | |
1143 | ||
74dff282 JB |
1144 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1145 | { | |
1146 | struct drm_device *dev = crtc->dev; | |
1147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1148 | struct drm_framebuffer *fb = crtc->fb; | |
1149 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1150 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
74dff282 | 1151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1152 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1153 | unsigned long stall_watermark = 200; |
1154 | u32 dpfc_ctl; | |
1155 | ||
bed4a673 CW |
1156 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1157 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1158 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
1159 | dev_priv->cfb_fence == obj_priv->fence_reg && | |
1160 | dev_priv->cfb_plane == intel_crtc->plane && | |
1161 | dev_priv->cfb_y == crtc->y) | |
1162 | return; | |
1163 | ||
1164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1165 | POSTING_READ(DPFC_CONTROL); | |
1166 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1167 | } | |
1168 | ||
74dff282 JB |
1169 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
1170 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1171 | dev_priv->cfb_plane = intel_crtc->plane; | |
bed4a673 | 1172 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1173 | |
1174 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
1175 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1176 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; | |
1177 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1178 | } else { | |
1179 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1180 | } | |
1181 | ||
74dff282 JB |
1182 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1183 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1184 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1185 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1186 | ||
1187 | /* enable it... */ | |
1188 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1189 | ||
28c97730 | 1190 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1191 | } |
1192 | ||
1193 | void g4x_disable_fbc(struct drm_device *dev) | |
1194 | { | |
1195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1196 | u32 dpfc_ctl; | |
1197 | ||
1198 | /* Disable compression */ | |
1199 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1200 | if (dpfc_ctl & DPFC_CTL_EN) { |
1201 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1202 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1203 | |
bed4a673 CW |
1204 | DRM_DEBUG_KMS("disabled FBC\n"); |
1205 | } | |
74dff282 JB |
1206 | } |
1207 | ||
ee5382ae | 1208 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1209 | { |
74dff282 JB |
1210 | struct drm_i915_private *dev_priv = dev->dev_private; |
1211 | ||
1212 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1213 | } | |
1214 | ||
b52eb4dc ZY |
1215 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1216 | { | |
1217 | struct drm_device *dev = crtc->dev; | |
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1219 | struct drm_framebuffer *fb = crtc->fb; | |
1220 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1221 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); | |
1222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5eddb70b | 1223 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1224 | unsigned long stall_watermark = 200; |
1225 | u32 dpfc_ctl; | |
1226 | ||
bed4a673 CW |
1227 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1228 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1229 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
1230 | dev_priv->cfb_fence == obj_priv->fence_reg && | |
1231 | dev_priv->cfb_plane == intel_crtc->plane && | |
1232 | dev_priv->cfb_offset == obj_priv->gtt_offset && | |
1233 | dev_priv->cfb_y == crtc->y) | |
1234 | return; | |
1235 | ||
1236 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1237 | POSTING_READ(ILK_DPFC_CONTROL); | |
1238 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1239 | } | |
1240 | ||
b52eb4dc ZY |
1241 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
1242 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1243 | dev_priv->cfb_plane = intel_crtc->plane; | |
bed4a673 CW |
1244 | dev_priv->cfb_offset = obj_priv->gtt_offset; |
1245 | dev_priv->cfb_y = crtc->y; | |
b52eb4dc | 1246 | |
b52eb4dc ZY |
1247 | dpfc_ctl &= DPFC_RESERVED; |
1248 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
1249 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1250 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); | |
1251 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1252 | } else { | |
1253 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1254 | } | |
1255 | ||
b52eb4dc ZY |
1256 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1257 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1258 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1259 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
1260 | I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID); | |
1261 | /* enable it... */ | |
bed4a673 | 1262 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc ZY |
1263 | |
1264 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
1265 | } | |
1266 | ||
1267 | void ironlake_disable_fbc(struct drm_device *dev) | |
1268 | { | |
1269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1270 | u32 dpfc_ctl; | |
1271 | ||
1272 | /* Disable compression */ | |
1273 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1274 | if (dpfc_ctl & DPFC_CTL_EN) { |
1275 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1276 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1277 | |
bed4a673 CW |
1278 | DRM_DEBUG_KMS("disabled FBC\n"); |
1279 | } | |
b52eb4dc ZY |
1280 | } |
1281 | ||
1282 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1283 | { | |
1284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1285 | ||
1286 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1287 | } | |
1288 | ||
ee5382ae AJ |
1289 | bool intel_fbc_enabled(struct drm_device *dev) |
1290 | { | |
1291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1292 | ||
1293 | if (!dev_priv->display.fbc_enabled) | |
1294 | return false; | |
1295 | ||
1296 | return dev_priv->display.fbc_enabled(dev); | |
1297 | } | |
1298 | ||
1299 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1300 | { | |
1301 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1302 | ||
1303 | if (!dev_priv->display.enable_fbc) | |
1304 | return; | |
1305 | ||
1306 | dev_priv->display.enable_fbc(crtc, interval); | |
1307 | } | |
1308 | ||
1309 | void intel_disable_fbc(struct drm_device *dev) | |
1310 | { | |
1311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1312 | ||
1313 | if (!dev_priv->display.disable_fbc) | |
1314 | return; | |
1315 | ||
1316 | dev_priv->display.disable_fbc(dev); | |
1317 | } | |
1318 | ||
80824003 JB |
1319 | /** |
1320 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1321 | * @dev: the drm_device |
80824003 JB |
1322 | * |
1323 | * Set up the framebuffer compression hardware at mode set time. We | |
1324 | * enable it if possible: | |
1325 | * - plane A only (on pre-965) | |
1326 | * - no pixel mulitply/line duplication | |
1327 | * - no alpha buffer discard | |
1328 | * - no dual wide | |
1329 | * - framebuffer <= 2048 in width, 1536 in height | |
1330 | * | |
1331 | * We can't assume that any compression will take place (worst case), | |
1332 | * so the compressed buffer has to be the same size as the uncompressed | |
1333 | * one. It also must reside (along with the line length buffer) in | |
1334 | * stolen memory. | |
1335 | * | |
1336 | * We need to enable/disable FBC on a global basis. | |
1337 | */ | |
bed4a673 | 1338 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1339 | { |
80824003 | 1340 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1341 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1342 | struct intel_crtc *intel_crtc; | |
1343 | struct drm_framebuffer *fb; | |
80824003 JB |
1344 | struct intel_framebuffer *intel_fb; |
1345 | struct drm_i915_gem_object *obj_priv; | |
9c928d16 JB |
1346 | |
1347 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1348 | |
1349 | if (!i915_powersave) | |
1350 | return; | |
1351 | ||
ee5382ae | 1352 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1353 | return; |
1354 | ||
80824003 JB |
1355 | /* |
1356 | * If FBC is already on, we just have to verify that we can | |
1357 | * keep it that way... | |
1358 | * Need to disable if: | |
9c928d16 | 1359 | * - more than one pipe is active |
80824003 JB |
1360 | * - changing FBC params (stride, fence, mode) |
1361 | * - new fb is too large to fit in compressed buffer | |
1362 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1363 | */ | |
9c928d16 | 1364 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
bed4a673 CW |
1365 | if (tmp_crtc->enabled) { |
1366 | if (crtc) { | |
1367 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1368 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1369 | goto out_disable; | |
1370 | } | |
1371 | crtc = tmp_crtc; | |
1372 | } | |
9c928d16 | 1373 | } |
bed4a673 CW |
1374 | |
1375 | if (!crtc || crtc->fb == NULL) { | |
1376 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1377 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1378 | goto out_disable; |
1379 | } | |
bed4a673 CW |
1380 | |
1381 | intel_crtc = to_intel_crtc(crtc); | |
1382 | fb = crtc->fb; | |
1383 | intel_fb = to_intel_framebuffer(fb); | |
1384 | obj_priv = to_intel_bo(intel_fb->obj); | |
1385 | ||
80824003 | 1386 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
28c97730 | 1387 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1388 | "compression\n"); |
b5e50c3f | 1389 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1390 | goto out_disable; |
1391 | } | |
bed4a673 CW |
1392 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1393 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1394 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1395 | "disabling\n"); |
b5e50c3f | 1396 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1397 | goto out_disable; |
1398 | } | |
bed4a673 CW |
1399 | if ((crtc->mode.hdisplay > 2048) || |
1400 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1401 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1402 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1403 | goto out_disable; |
1404 | } | |
bed4a673 | 1405 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1406 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1407 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1408 | goto out_disable; |
1409 | } | |
1410 | if (obj_priv->tiling_mode != I915_TILING_X) { | |
28c97730 | 1411 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1412 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1413 | goto out_disable; |
1414 | } | |
1415 | ||
c924b934 JW |
1416 | /* If the kernel debugger is active, always disable compression */ |
1417 | if (in_dbg_master()) | |
1418 | goto out_disable; | |
1419 | ||
bed4a673 | 1420 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1421 | return; |
1422 | ||
1423 | out_disable: | |
80824003 | 1424 | /* Multiple disables should be harmless */ |
a939406f CW |
1425 | if (intel_fbc_enabled(dev)) { |
1426 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1427 | intel_disable_fbc(dev); |
a939406f | 1428 | } |
80824003 JB |
1429 | } |
1430 | ||
127bd2ac | 1431 | int |
48b956c5 CW |
1432 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1433 | struct drm_gem_object *obj, | |
1434 | bool pipelined) | |
6b95a207 | 1435 | { |
23010e43 | 1436 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
6b95a207 KH |
1437 | u32 alignment; |
1438 | int ret; | |
1439 | ||
1440 | switch (obj_priv->tiling_mode) { | |
1441 | case I915_TILING_NONE: | |
534843da CW |
1442 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1443 | alignment = 128 * 1024; | |
a6c45cf0 | 1444 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1445 | alignment = 4 * 1024; |
1446 | else | |
1447 | alignment = 64 * 1024; | |
6b95a207 KH |
1448 | break; |
1449 | case I915_TILING_X: | |
1450 | /* pin() will align the object as required by fence */ | |
1451 | alignment = 0; | |
1452 | break; | |
1453 | case I915_TILING_Y: | |
1454 | /* FIXME: Is this true? */ | |
1455 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1456 | return -EINVAL; | |
1457 | default: | |
1458 | BUG(); | |
1459 | } | |
1460 | ||
6b95a207 | 1461 | ret = i915_gem_object_pin(obj, alignment); |
48b956c5 | 1462 | if (ret) |
6b95a207 KH |
1463 | return ret; |
1464 | ||
48b956c5 CW |
1465 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
1466 | if (ret) | |
1467 | goto err_unpin; | |
7213342d | 1468 | |
6b95a207 KH |
1469 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1470 | * fence, whereas 965+ only requires a fence if using | |
1471 | * framebuffer compression. For simplicity, we always install | |
1472 | * a fence as the cost is not that onerous. | |
1473 | */ | |
1474 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
1475 | obj_priv->tiling_mode != I915_TILING_NONE) { | |
2cf34d7b | 1476 | ret = i915_gem_object_get_fence_reg(obj, false); |
48b956c5 CW |
1477 | if (ret) |
1478 | goto err_unpin; | |
6b95a207 KH |
1479 | } |
1480 | ||
1481 | return 0; | |
48b956c5 CW |
1482 | |
1483 | err_unpin: | |
1484 | i915_gem_object_unpin(obj); | |
1485 | return ret; | |
6b95a207 KH |
1486 | } |
1487 | ||
81255565 JB |
1488 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1489 | static int | |
1490 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
413d45d3 | 1491 | int x, int y, int enter) |
81255565 JB |
1492 | { |
1493 | struct drm_device *dev = crtc->dev; | |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1495 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1496 | struct intel_framebuffer *intel_fb; | |
1497 | struct drm_i915_gem_object *obj_priv; | |
1498 | struct drm_gem_object *obj; | |
1499 | int plane = intel_crtc->plane; | |
1500 | unsigned long Start, Offset; | |
81255565 | 1501 | u32 dspcntr; |
5eddb70b | 1502 | u32 reg; |
81255565 JB |
1503 | |
1504 | switch (plane) { | |
1505 | case 0: | |
1506 | case 1: | |
1507 | break; | |
1508 | default: | |
1509 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1510 | return -EINVAL; | |
1511 | } | |
1512 | ||
1513 | intel_fb = to_intel_framebuffer(fb); | |
1514 | obj = intel_fb->obj; | |
1515 | obj_priv = to_intel_bo(obj); | |
1516 | ||
5eddb70b CW |
1517 | reg = DSPCNTR(plane); |
1518 | dspcntr = I915_READ(reg); | |
81255565 JB |
1519 | /* Mask out pixel format bits in case we change it */ |
1520 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1521 | switch (fb->bits_per_pixel) { | |
1522 | case 8: | |
1523 | dspcntr |= DISPPLANE_8BPP; | |
1524 | break; | |
1525 | case 16: | |
1526 | if (fb->depth == 15) | |
1527 | dspcntr |= DISPPLANE_15_16BPP; | |
1528 | else | |
1529 | dspcntr |= DISPPLANE_16BPP; | |
1530 | break; | |
1531 | case 24: | |
1532 | case 32: | |
1533 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1534 | break; | |
1535 | default: | |
1536 | DRM_ERROR("Unknown color depth\n"); | |
1537 | return -EINVAL; | |
1538 | } | |
a6c45cf0 | 1539 | if (INTEL_INFO(dev)->gen >= 4) { |
81255565 JB |
1540 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1541 | dspcntr |= DISPPLANE_TILED; | |
1542 | else | |
1543 | dspcntr &= ~DISPPLANE_TILED; | |
1544 | } | |
1545 | ||
4e6cfefc | 1546 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1547 | /* must disable */ |
1548 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1549 | ||
5eddb70b | 1550 | I915_WRITE(reg, dspcntr); |
81255565 JB |
1551 | |
1552 | Start = obj_priv->gtt_offset; | |
1553 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); | |
1554 | ||
4e6cfefc CW |
1555 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1556 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 1557 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 1558 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
1559 | I915_WRITE(DSPSURF(plane), Start); |
1560 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
1561 | I915_WRITE(DSPADDR(plane), Offset); | |
1562 | } else | |
1563 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1564 | POSTING_READ(reg); | |
81255565 | 1565 | |
bed4a673 | 1566 | intel_update_fbc(dev); |
3dec0095 | 1567 | intel_increase_pllclock(crtc); |
81255565 JB |
1568 | |
1569 | return 0; | |
1570 | } | |
1571 | ||
5c3b82e2 | 1572 | static int |
3c4fdcfb KH |
1573 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1574 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1575 | { |
1576 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1577 | struct drm_i915_master_private *master_priv; |
1578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1579 | int ret; |
79e53945 JB |
1580 | |
1581 | /* no fb bound */ | |
1582 | if (!crtc->fb) { | |
28c97730 | 1583 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1584 | return 0; |
1585 | } | |
1586 | ||
265db958 | 1587 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1588 | case 0: |
1589 | case 1: | |
1590 | break; | |
1591 | default: | |
5c3b82e2 | 1592 | return -EINVAL; |
79e53945 JB |
1593 | } |
1594 | ||
5c3b82e2 | 1595 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1596 | ret = intel_pin_and_fence_fb_obj(dev, |
1597 | to_intel_framebuffer(crtc->fb)->obj, | |
1598 | false); | |
5c3b82e2 CW |
1599 | if (ret != 0) { |
1600 | mutex_unlock(&dev->struct_mutex); | |
1601 | return ret; | |
1602 | } | |
79e53945 | 1603 | |
265db958 | 1604 | if (old_fb) { |
e6c3a2a6 | 1605 | struct drm_i915_private *dev_priv = dev->dev_private; |
265db958 CW |
1606 | struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
1607 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1608 | ||
e6c3a2a6 CW |
1609 | wait_event(dev_priv->pending_flip_queue, |
1610 | atomic_read(&obj_priv->pending_flip) == 0); | |
265db958 CW |
1611 | } |
1612 | ||
413d45d3 | 1613 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 0); |
4e6cfefc | 1614 | if (ret) { |
265db958 | 1615 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1616 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1617 | return ret; |
79e53945 | 1618 | } |
3c4fdcfb | 1619 | |
265db958 CW |
1620 | if (old_fb) |
1621 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); | |
652c393a | 1622 | |
5c3b82e2 | 1623 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1624 | |
1625 | if (!dev->primary->master) | |
5c3b82e2 | 1626 | return 0; |
79e53945 JB |
1627 | |
1628 | master_priv = dev->primary->master->driver_priv; | |
1629 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1630 | return 0; |
79e53945 | 1631 | |
265db958 | 1632 | if (intel_crtc->pipe) { |
79e53945 JB |
1633 | master_priv->sarea_priv->pipeB_x = x; |
1634 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1635 | } else { |
1636 | master_priv->sarea_priv->pipeA_x = x; | |
1637 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1638 | } |
5c3b82e2 CW |
1639 | |
1640 | return 0; | |
79e53945 JB |
1641 | } |
1642 | ||
5eddb70b | 1643 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1644 | { |
1645 | struct drm_device *dev = crtc->dev; | |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1647 | u32 dpa_ctl; | |
1648 | ||
28c97730 | 1649 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1650 | dpa_ctl = I915_READ(DP_A); |
1651 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1652 | ||
1653 | if (clock < 200000) { | |
1654 | u32 temp; | |
1655 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1656 | /* workaround for 160Mhz: | |
1657 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1658 | 2) program 0x46010 bit 0 = 1 | |
1659 | 3) program 0x46034 bit 24 = 1 | |
1660 | 4) program 0x64000 bit 14 = 1 | |
1661 | */ | |
1662 | temp = I915_READ(0x4600c); | |
1663 | temp &= 0xffff0000; | |
1664 | I915_WRITE(0x4600c, temp | 0x8124); | |
1665 | ||
1666 | temp = I915_READ(0x46010); | |
1667 | I915_WRITE(0x46010, temp | 1); | |
1668 | ||
1669 | temp = I915_READ(0x46034); | |
1670 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1671 | } else { | |
1672 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1673 | } | |
1674 | I915_WRITE(DP_A, dpa_ctl); | |
1675 | ||
5eddb70b | 1676 | POSTING_READ(DP_A); |
32f9d658 ZW |
1677 | udelay(500); |
1678 | } | |
1679 | ||
8db9d77b ZW |
1680 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1681 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1682 | { | |
1683 | struct drm_device *dev = crtc->dev; | |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1686 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1687 | u32 reg, temp, tries; |
8db9d77b | 1688 | |
e1a44743 AJ |
1689 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1690 | for train result */ | |
5eddb70b CW |
1691 | reg = FDI_RX_IMR(pipe); |
1692 | temp = I915_READ(reg); | |
e1a44743 AJ |
1693 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1694 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1695 | I915_WRITE(reg, temp); |
1696 | I915_READ(reg); | |
e1a44743 AJ |
1697 | udelay(150); |
1698 | ||
8db9d77b | 1699 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1700 | reg = FDI_TX_CTL(pipe); |
1701 | temp = I915_READ(reg); | |
77ffb597 AJ |
1702 | temp &= ~(7 << 19); |
1703 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1704 | temp &= ~FDI_LINK_TRAIN_NONE; |
1705 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 1706 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1707 | |
5eddb70b CW |
1708 | reg = FDI_RX_CTL(pipe); |
1709 | temp = I915_READ(reg); | |
8db9d77b ZW |
1710 | temp &= ~FDI_LINK_TRAIN_NONE; |
1711 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
1712 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1713 | ||
1714 | POSTING_READ(reg); | |
8db9d77b ZW |
1715 | udelay(150); |
1716 | ||
5eddb70b | 1717 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1718 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1719 | temp = I915_READ(reg); |
8db9d77b ZW |
1720 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1721 | ||
1722 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1723 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 1724 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1725 | break; |
1726 | } | |
8db9d77b | 1727 | } |
e1a44743 | 1728 | if (tries == 5) |
5eddb70b | 1729 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1730 | |
1731 | /* Train 2 */ | |
5eddb70b CW |
1732 | reg = FDI_TX_CTL(pipe); |
1733 | temp = I915_READ(reg); | |
8db9d77b ZW |
1734 | temp &= ~FDI_LINK_TRAIN_NONE; |
1735 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1736 | I915_WRITE(reg, temp); |
8db9d77b | 1737 | |
5eddb70b CW |
1738 | reg = FDI_RX_CTL(pipe); |
1739 | temp = I915_READ(reg); | |
8db9d77b ZW |
1740 | temp &= ~FDI_LINK_TRAIN_NONE; |
1741 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1742 | I915_WRITE(reg, temp); |
8db9d77b | 1743 | |
5eddb70b CW |
1744 | POSTING_READ(reg); |
1745 | udelay(150); | |
8db9d77b | 1746 | |
5eddb70b | 1747 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1748 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1749 | temp = I915_READ(reg); |
8db9d77b ZW |
1750 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1751 | ||
1752 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1753 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1754 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1755 | break; | |
1756 | } | |
8db9d77b | 1757 | } |
e1a44743 | 1758 | if (tries == 5) |
5eddb70b | 1759 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1760 | |
1761 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 JB |
1762 | |
1763 | /* enable normal train */ | |
1764 | reg = FDI_TX_CTL(pipe); | |
1765 | temp = I915_READ(reg); | |
1766 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1767 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
1768 | I915_WRITE(reg, temp); | |
1769 | ||
1770 | reg = FDI_RX_CTL(pipe); | |
1771 | temp = I915_READ(reg); | |
1772 | if (HAS_PCH_CPT(dev)) { | |
1773 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1774 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
1775 | } else { | |
1776 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1777 | temp |= FDI_LINK_TRAIN_NONE; | |
1778 | } | |
1779 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1780 | ||
1781 | /* wait one idle pattern time */ | |
1782 | POSTING_READ(reg); | |
1783 | udelay(1000); | |
8db9d77b ZW |
1784 | } |
1785 | ||
5eddb70b | 1786 | static const int const snb_b_fdi_train_param [] = { |
8db9d77b ZW |
1787 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
1788 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
1789 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
1790 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
1791 | }; | |
1792 | ||
1793 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
1794 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
1795 | { | |
1796 | struct drm_device *dev = crtc->dev; | |
1797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1799 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1800 | u32 reg, temp, i; |
8db9d77b | 1801 | |
e1a44743 AJ |
1802 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1803 | for train result */ | |
5eddb70b CW |
1804 | reg = FDI_RX_IMR(pipe); |
1805 | temp = I915_READ(reg); | |
e1a44743 AJ |
1806 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1807 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1808 | I915_WRITE(reg, temp); |
1809 | ||
1810 | POSTING_READ(reg); | |
e1a44743 AJ |
1811 | udelay(150); |
1812 | ||
8db9d77b | 1813 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1814 | reg = FDI_TX_CTL(pipe); |
1815 | temp = I915_READ(reg); | |
77ffb597 AJ |
1816 | temp &= ~(7 << 19); |
1817 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1818 | temp &= ~FDI_LINK_TRAIN_NONE; |
1819 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1820 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1821 | /* SNB-B */ | |
1822 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 1823 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1824 | |
5eddb70b CW |
1825 | reg = FDI_RX_CTL(pipe); |
1826 | temp = I915_READ(reg); | |
8db9d77b ZW |
1827 | if (HAS_PCH_CPT(dev)) { |
1828 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1829 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
1830 | } else { | |
1831 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1832 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1833 | } | |
5eddb70b CW |
1834 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1835 | ||
1836 | POSTING_READ(reg); | |
8db9d77b ZW |
1837 | udelay(150); |
1838 | ||
8db9d77b | 1839 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
1840 | reg = FDI_TX_CTL(pipe); |
1841 | temp = I915_READ(reg); | |
8db9d77b ZW |
1842 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1843 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1844 | I915_WRITE(reg, temp); |
1845 | ||
1846 | POSTING_READ(reg); | |
8db9d77b ZW |
1847 | udelay(500); |
1848 | ||
5eddb70b CW |
1849 | reg = FDI_RX_IIR(pipe); |
1850 | temp = I915_READ(reg); | |
8db9d77b ZW |
1851 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1852 | ||
1853 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 1854 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1855 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
1856 | break; | |
1857 | } | |
1858 | } | |
1859 | if (i == 4) | |
5eddb70b | 1860 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1861 | |
1862 | /* Train 2 */ | |
5eddb70b CW |
1863 | reg = FDI_TX_CTL(pipe); |
1864 | temp = I915_READ(reg); | |
8db9d77b ZW |
1865 | temp &= ~FDI_LINK_TRAIN_NONE; |
1866 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1867 | if (IS_GEN6(dev)) { | |
1868 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1869 | /* SNB-B */ | |
1870 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1871 | } | |
5eddb70b | 1872 | I915_WRITE(reg, temp); |
8db9d77b | 1873 | |
5eddb70b CW |
1874 | reg = FDI_RX_CTL(pipe); |
1875 | temp = I915_READ(reg); | |
8db9d77b ZW |
1876 | if (HAS_PCH_CPT(dev)) { |
1877 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1878 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
1879 | } else { | |
1880 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1881 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1882 | } | |
5eddb70b CW |
1883 | I915_WRITE(reg, temp); |
1884 | ||
1885 | POSTING_READ(reg); | |
8db9d77b ZW |
1886 | udelay(150); |
1887 | ||
1888 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
1889 | reg = FDI_TX_CTL(pipe); |
1890 | temp = I915_READ(reg); | |
8db9d77b ZW |
1891 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1892 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1893 | I915_WRITE(reg, temp); |
1894 | ||
1895 | POSTING_READ(reg); | |
8db9d77b ZW |
1896 | udelay(500); |
1897 | ||
5eddb70b CW |
1898 | reg = FDI_RX_IIR(pipe); |
1899 | temp = I915_READ(reg); | |
8db9d77b ZW |
1900 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1901 | ||
1902 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1903 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1904 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1905 | break; | |
1906 | } | |
1907 | } | |
1908 | if (i == 4) | |
5eddb70b | 1909 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1910 | |
1911 | DRM_DEBUG_KMS("FDI train done.\n"); | |
1912 | } | |
1913 | ||
0e23b99d | 1914 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
1915 | { |
1916 | struct drm_device *dev = crtc->dev; | |
1917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1919 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1920 | u32 reg, temp; |
79e53945 | 1921 | |
c64e311e | 1922 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
1923 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
1924 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 1925 | |
c98e9dcf | 1926 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
1927 | reg = FDI_RX_CTL(pipe); |
1928 | temp = I915_READ(reg); | |
1929 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 1930 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
1931 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
1932 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
1933 | ||
1934 | POSTING_READ(reg); | |
c98e9dcf JB |
1935 | udelay(200); |
1936 | ||
1937 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
1938 | temp = I915_READ(reg); |
1939 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
1940 | ||
1941 | POSTING_READ(reg); | |
c98e9dcf JB |
1942 | udelay(200); |
1943 | ||
1944 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
1945 | reg = FDI_TX_CTL(pipe); |
1946 | temp = I915_READ(reg); | |
c98e9dcf | 1947 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
1948 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
1949 | ||
1950 | POSTING_READ(reg); | |
c98e9dcf | 1951 | udelay(100); |
6be4a607 | 1952 | } |
0e23b99d JB |
1953 | } |
1954 | ||
5eddb70b CW |
1955 | static void intel_flush_display_plane(struct drm_device *dev, |
1956 | int plane) | |
1957 | { | |
1958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1959 | u32 reg = DSPADDR(plane); | |
1960 | I915_WRITE(reg, I915_READ(reg)); | |
1961 | } | |
1962 | ||
6b383a7f CW |
1963 | /* |
1964 | * When we disable a pipe, we need to clear any pending scanline wait events | |
1965 | * to avoid hanging the ring, which we assume we are waiting on. | |
1966 | */ | |
1967 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
1968 | { | |
1969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1970 | u32 tmp; | |
1971 | ||
1972 | if (IS_GEN2(dev)) | |
1973 | /* Can't break the hang on i8xx */ | |
1974 | return; | |
1975 | ||
1976 | tmp = I915_READ(PRB0_CTL); | |
1977 | if (tmp & RING_WAIT) { | |
1978 | I915_WRITE(PRB0_CTL, tmp); | |
1979 | POSTING_READ(PRB0_CTL); | |
1980 | } | |
1981 | } | |
1982 | ||
e6c3a2a6 CW |
1983 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
1984 | { | |
1985 | struct drm_i915_gem_object *obj_priv; | |
1986 | struct drm_i915_private *dev_priv; | |
1987 | ||
1988 | if (crtc->fb == NULL) | |
1989 | return; | |
1990 | ||
1991 | obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj); | |
1992 | dev_priv = crtc->dev->dev_private; | |
1993 | wait_event(dev_priv->pending_flip_queue, | |
1994 | atomic_read(&obj_priv->pending_flip) == 0); | |
1995 | } | |
1996 | ||
0e23b99d JB |
1997 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
1998 | { | |
1999 | struct drm_device *dev = crtc->dev; | |
2000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2002 | int pipe = intel_crtc->pipe; | |
2003 | int plane = intel_crtc->plane; | |
5eddb70b | 2004 | u32 reg, temp; |
0e23b99d | 2005 | |
f7abfe8b CW |
2006 | if (intel_crtc->active) |
2007 | return; | |
2008 | ||
2009 | intel_crtc->active = true; | |
6b383a7f CW |
2010 | intel_update_watermarks(dev); |
2011 | ||
0e23b99d JB |
2012 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2013 | temp = I915_READ(PCH_LVDS); | |
5eddb70b | 2014 | if ((temp & LVDS_PORT_EN) == 0) |
0e23b99d | 2015 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
0e23b99d JB |
2016 | } |
2017 | ||
2018 | ironlake_fdi_enable(crtc); | |
2c07245f | 2019 | |
6be4a607 JB |
2020 | /* Enable panel fitting for LVDS */ |
2021 | if (dev_priv->pch_pf_size && | |
1d850362 | 2022 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
6be4a607 JB |
2023 | /* Force use of hard-coded filter coefficients |
2024 | * as some pre-programmed values are broken, | |
2025 | * e.g. x201. | |
2026 | */ | |
2027 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
2028 | PF_ENABLE | PF_FILTER_MED_3x3); | |
2029 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
2030 | dev_priv->pch_pf_pos); | |
2031 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
2032 | dev_priv->pch_pf_size); | |
2033 | } | |
2c07245f | 2034 | |
6be4a607 | 2035 | /* Enable CPU pipe */ |
5eddb70b CW |
2036 | reg = PIPECONF(pipe); |
2037 | temp = I915_READ(reg); | |
2038 | if ((temp & PIPECONF_ENABLE) == 0) { | |
2039 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
2040 | POSTING_READ(reg); | |
6be4a607 JB |
2041 | udelay(100); |
2042 | } | |
2c07245f | 2043 | |
6be4a607 | 2044 | /* configure and enable CPU plane */ |
5eddb70b CW |
2045 | reg = DSPCNTR(plane); |
2046 | temp = I915_READ(reg); | |
6be4a607 | 2047 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2048 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2049 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2050 | } |
2c07245f | 2051 | |
c98e9dcf JB |
2052 | /* For PCH output, training FDI link */ |
2053 | if (IS_GEN6(dev)) | |
2054 | gen6_fdi_link_train(crtc); | |
2055 | else | |
2056 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2057 | |
c98e9dcf | 2058 | /* enable PCH DPLL */ |
5eddb70b CW |
2059 | reg = PCH_DPLL(pipe); |
2060 | temp = I915_READ(reg); | |
c98e9dcf | 2061 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2062 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
2063 | POSTING_READ(reg); | |
8c4223be | 2064 | udelay(200); |
c98e9dcf | 2065 | } |
8db9d77b | 2066 | |
c98e9dcf JB |
2067 | if (HAS_PCH_CPT(dev)) { |
2068 | /* Be sure PCH DPLL SEL is set */ | |
2069 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2070 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2071 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2072 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2073 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2074 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2075 | } |
5eddb70b | 2076 | |
c98e9dcf | 2077 | /* set transcoder timing */ |
5eddb70b CW |
2078 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2079 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2080 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2081 | |
5eddb70b CW |
2082 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2083 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2084 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2085 | |
c98e9dcf JB |
2086 | /* For PCH DP, enable TRANS_DP_CTL */ |
2087 | if (HAS_PCH_CPT(dev) && | |
2088 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2089 | reg = TRANS_DP_CTL(pipe); |
2090 | temp = I915_READ(reg); | |
2091 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
2092 | TRANS_DP_SYNC_MASK); | |
2093 | temp |= (TRANS_DP_OUTPUT_ENABLE | | |
2094 | TRANS_DP_ENH_FRAMING); | |
c98e9dcf JB |
2095 | |
2096 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2097 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2098 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2099 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2100 | |
2101 | switch (intel_trans_dp_port_sel(crtc)) { | |
2102 | case PCH_DP_B: | |
5eddb70b | 2103 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2104 | break; |
2105 | case PCH_DP_C: | |
5eddb70b | 2106 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2107 | break; |
2108 | case PCH_DP_D: | |
5eddb70b | 2109 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2110 | break; |
2111 | default: | |
2112 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2113 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2114 | break; |
32f9d658 | 2115 | } |
2c07245f | 2116 | |
5eddb70b | 2117 | I915_WRITE(reg, temp); |
6be4a607 | 2118 | } |
b52eb4dc | 2119 | |
c98e9dcf | 2120 | /* enable PCH transcoder */ |
5eddb70b CW |
2121 | reg = TRANSCONF(pipe); |
2122 | temp = I915_READ(reg); | |
c98e9dcf JB |
2123 | /* |
2124 | * make the BPC in transcoder be consistent with | |
2125 | * that in pipeconf reg. | |
2126 | */ | |
2127 | temp &= ~PIPE_BPC_MASK; | |
5eddb70b CW |
2128 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
2129 | I915_WRITE(reg, temp | TRANS_ENABLE); | |
2130 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
c98e9dcf JB |
2131 | DRM_ERROR("failed to enable transcoder\n"); |
2132 | ||
6be4a607 | 2133 | intel_crtc_load_lut(crtc); |
bed4a673 | 2134 | intel_update_fbc(dev); |
6b383a7f | 2135 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2136 | } |
2137 | ||
2138 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2139 | { | |
2140 | struct drm_device *dev = crtc->dev; | |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2143 | int pipe = intel_crtc->pipe; | |
2144 | int plane = intel_crtc->plane; | |
5eddb70b | 2145 | u32 reg, temp; |
b52eb4dc | 2146 | |
f7abfe8b CW |
2147 | if (!intel_crtc->active) |
2148 | return; | |
2149 | ||
e6c3a2a6 | 2150 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2151 | drm_vblank_off(dev, pipe); |
6b383a7f | 2152 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2153 | |
6be4a607 | 2154 | /* Disable display plane */ |
5eddb70b CW |
2155 | reg = DSPCNTR(plane); |
2156 | temp = I915_READ(reg); | |
2157 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2158 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2159 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2160 | } |
913d8d11 | 2161 | |
6be4a607 JB |
2162 | if (dev_priv->cfb_plane == plane && |
2163 | dev_priv->display.disable_fbc) | |
2164 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2165 | |
6be4a607 | 2166 | /* disable cpu pipe, disable after all planes disabled */ |
5eddb70b CW |
2167 | reg = PIPECONF(pipe); |
2168 | temp = I915_READ(reg); | |
2169 | if (temp & PIPECONF_ENABLE) { | |
2170 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
6be4a607 | 2171 | /* wait for cpu pipe off, pipe state */ |
5eddb70b | 2172 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50)) |
6be4a607 | 2173 | DRM_ERROR("failed to turn off cpu pipe\n"); |
5eddb70b | 2174 | } |
32f9d658 | 2175 | |
6be4a607 JB |
2176 | /* Disable PF */ |
2177 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2178 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2179 | |
6be4a607 | 2180 | /* disable CPU FDI tx and PCH FDI rx */ |
5eddb70b CW |
2181 | reg = FDI_TX_CTL(pipe); |
2182 | temp = I915_READ(reg); | |
2183 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2184 | POSTING_READ(reg); | |
249c0e64 | 2185 | |
5eddb70b CW |
2186 | reg = FDI_RX_CTL(pipe); |
2187 | temp = I915_READ(reg); | |
2188 | temp &= ~(0x7 << 16); | |
2189 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2190 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
6be4a607 | 2191 | |
5eddb70b | 2192 | POSTING_READ(reg); |
6be4a607 JB |
2193 | udelay(100); |
2194 | ||
2195 | /* still set train pattern 1 */ | |
5eddb70b CW |
2196 | reg = FDI_TX_CTL(pipe); |
2197 | temp = I915_READ(reg); | |
6be4a607 JB |
2198 | temp &= ~FDI_LINK_TRAIN_NONE; |
2199 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2200 | I915_WRITE(reg, temp); |
6be4a607 | 2201 | |
5eddb70b CW |
2202 | reg = FDI_RX_CTL(pipe); |
2203 | temp = I915_READ(reg); | |
6be4a607 JB |
2204 | if (HAS_PCH_CPT(dev)) { |
2205 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2206 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2207 | } else { | |
2c07245f ZW |
2208 | temp &= ~FDI_LINK_TRAIN_NONE; |
2209 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 | 2210 | } |
5eddb70b CW |
2211 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2212 | temp &= ~(0x07 << 16); | |
2213 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2214 | I915_WRITE(reg, temp); | |
2c07245f | 2215 | |
5eddb70b | 2216 | POSTING_READ(reg); |
6be4a607 | 2217 | udelay(100); |
2c07245f | 2218 | |
6be4a607 JB |
2219 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2220 | temp = I915_READ(PCH_LVDS); | |
5eddb70b CW |
2221 | if (temp & LVDS_PORT_EN) { |
2222 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2223 | POSTING_READ(PCH_LVDS); | |
2224 | udelay(100); | |
2225 | } | |
6be4a607 | 2226 | } |
249c0e64 | 2227 | |
6be4a607 | 2228 | /* disable PCH transcoder */ |
5eddb70b CW |
2229 | reg = TRANSCONF(plane); |
2230 | temp = I915_READ(reg); | |
2231 | if (temp & TRANS_ENABLE) { | |
2232 | I915_WRITE(reg, temp & ~TRANS_ENABLE); | |
6be4a607 | 2233 | /* wait for PCH transcoder off, transcoder state */ |
5eddb70b | 2234 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
6be4a607 JB |
2235 | DRM_ERROR("failed to disable transcoder\n"); |
2236 | } | |
913d8d11 | 2237 | |
6be4a607 JB |
2238 | if (HAS_PCH_CPT(dev)) { |
2239 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2240 | reg = TRANS_DP_CTL(pipe); |
2241 | temp = I915_READ(reg); | |
2242 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2243 | I915_WRITE(reg, temp); | |
6be4a607 JB |
2244 | |
2245 | /* disable DPLL_SEL */ | |
2246 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2247 | if (pipe == 0) |
6be4a607 JB |
2248 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2249 | else | |
2250 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2251 | I915_WRITE(PCH_DPLL_SEL, temp); | |
6be4a607 | 2252 | } |
e3421a18 | 2253 | |
6be4a607 | 2254 | /* disable PCH DPLL */ |
5eddb70b CW |
2255 | reg = PCH_DPLL(pipe); |
2256 | temp = I915_READ(reg); | |
2257 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
8db9d77b | 2258 | |
6be4a607 | 2259 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2260 | reg = FDI_RX_CTL(pipe); |
2261 | temp = I915_READ(reg); | |
2262 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2263 | |
6be4a607 | 2264 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2265 | reg = FDI_TX_CTL(pipe); |
2266 | temp = I915_READ(reg); | |
2267 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2268 | ||
2269 | POSTING_READ(reg); | |
6be4a607 | 2270 | udelay(100); |
8db9d77b | 2271 | |
5eddb70b CW |
2272 | reg = FDI_RX_CTL(pipe); |
2273 | temp = I915_READ(reg); | |
2274 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2275 | |
6be4a607 | 2276 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2277 | POSTING_READ(reg); |
6be4a607 | 2278 | udelay(100); |
6b383a7f | 2279 | |
f7abfe8b | 2280 | intel_crtc->active = false; |
6b383a7f CW |
2281 | intel_update_watermarks(dev); |
2282 | intel_update_fbc(dev); | |
2283 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2284 | } |
1b3c7a47 | 2285 | |
6be4a607 JB |
2286 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2287 | { | |
2288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2289 | int pipe = intel_crtc->pipe; | |
2290 | int plane = intel_crtc->plane; | |
8db9d77b | 2291 | |
6be4a607 JB |
2292 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2293 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2294 | */ | |
2295 | switch (mode) { | |
2296 | case DRM_MODE_DPMS_ON: | |
2297 | case DRM_MODE_DPMS_STANDBY: | |
2298 | case DRM_MODE_DPMS_SUSPEND: | |
2299 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2300 | ironlake_crtc_enable(crtc); | |
2301 | break; | |
1b3c7a47 | 2302 | |
6be4a607 JB |
2303 | case DRM_MODE_DPMS_OFF: |
2304 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2305 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2306 | break; |
2307 | } | |
2308 | } | |
2309 | ||
02e792fb DV |
2310 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2311 | { | |
02e792fb | 2312 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2313 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2314 | |
23f09ce3 CW |
2315 | mutex_lock(&dev->struct_mutex); |
2316 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2317 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2318 | } |
02e792fb | 2319 | |
5dcdbcb0 CW |
2320 | /* Let userspace switch the overlay on again. In most cases userspace |
2321 | * has to recompute where to put it anyway. | |
2322 | */ | |
02e792fb DV |
2323 | } |
2324 | ||
0b8765c6 | 2325 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2326 | { |
2327 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2328 | struct drm_i915_private *dev_priv = dev->dev_private; |
2329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2330 | int pipe = intel_crtc->pipe; | |
80824003 | 2331 | int plane = intel_crtc->plane; |
5eddb70b | 2332 | u32 reg, temp; |
79e53945 | 2333 | |
f7abfe8b CW |
2334 | if (intel_crtc->active) |
2335 | return; | |
2336 | ||
2337 | intel_crtc->active = true; | |
6b383a7f CW |
2338 | intel_update_watermarks(dev); |
2339 | ||
0b8765c6 | 2340 | /* Enable the DPLL */ |
5eddb70b CW |
2341 | reg = DPLL(pipe); |
2342 | temp = I915_READ(reg); | |
0b8765c6 | 2343 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2344 | I915_WRITE(reg, temp); |
2345 | ||
0b8765c6 | 2346 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2347 | POSTING_READ(reg); |
0b8765c6 | 2348 | udelay(150); |
5eddb70b CW |
2349 | |
2350 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2351 | ||
0b8765c6 | 2352 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2353 | POSTING_READ(reg); |
0b8765c6 | 2354 | udelay(150); |
5eddb70b CW |
2355 | |
2356 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2357 | ||
0b8765c6 | 2358 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2359 | POSTING_READ(reg); |
0b8765c6 JB |
2360 | udelay(150); |
2361 | } | |
79e53945 | 2362 | |
0b8765c6 | 2363 | /* Enable the pipe */ |
5eddb70b CW |
2364 | reg = PIPECONF(pipe); |
2365 | temp = I915_READ(reg); | |
2366 | if ((temp & PIPECONF_ENABLE) == 0) | |
2367 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
79e53945 | 2368 | |
0b8765c6 | 2369 | /* Enable the plane */ |
5eddb70b CW |
2370 | reg = DSPCNTR(plane); |
2371 | temp = I915_READ(reg); | |
0b8765c6 | 2372 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2373 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2374 | intel_flush_display_plane(dev, plane); | |
0b8765c6 | 2375 | } |
79e53945 | 2376 | |
0b8765c6 | 2377 | intel_crtc_load_lut(crtc); |
bed4a673 | 2378 | intel_update_fbc(dev); |
79e53945 | 2379 | |
0b8765c6 JB |
2380 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2381 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2382 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2383 | } |
79e53945 | 2384 | |
0b8765c6 JB |
2385 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2386 | { | |
2387 | struct drm_device *dev = crtc->dev; | |
2388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2389 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2390 | int pipe = intel_crtc->pipe; | |
2391 | int plane = intel_crtc->plane; | |
5eddb70b | 2392 | u32 reg, temp; |
b690e96c | 2393 | |
f7abfe8b CW |
2394 | if (!intel_crtc->active) |
2395 | return; | |
2396 | ||
0b8765c6 | 2397 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
2398 | intel_crtc_wait_for_pending_flips(crtc); |
2399 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 2400 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 2401 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
2402 | |
2403 | if (dev_priv->cfb_plane == plane && | |
2404 | dev_priv->display.disable_fbc) | |
2405 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2406 | |
0b8765c6 | 2407 | /* Disable display plane */ |
5eddb70b CW |
2408 | reg = DSPCNTR(plane); |
2409 | temp = I915_READ(reg); | |
2410 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2411 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
0b8765c6 | 2412 | /* Flush the plane changes */ |
5eddb70b | 2413 | intel_flush_display_plane(dev, plane); |
0b8765c6 | 2414 | |
0b8765c6 | 2415 | /* Wait for vblank for the disable to take effect */ |
a6c45cf0 | 2416 | if (IS_GEN2(dev)) |
ab7ad7f6 | 2417 | intel_wait_for_vblank(dev, pipe); |
0b8765c6 | 2418 | } |
79e53945 | 2419 | |
0b8765c6 | 2420 | /* Don't disable pipe A or pipe A PLLs if needed */ |
5eddb70b | 2421 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
6b383a7f | 2422 | goto done; |
0b8765c6 JB |
2423 | |
2424 | /* Next, disable display pipes */ | |
5eddb70b CW |
2425 | reg = PIPECONF(pipe); |
2426 | temp = I915_READ(reg); | |
2427 | if (temp & PIPECONF_ENABLE) { | |
2428 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
2429 | ||
ab7ad7f6 | 2430 | /* Wait for the pipe to turn off */ |
5eddb70b | 2431 | POSTING_READ(reg); |
ab7ad7f6 | 2432 | intel_wait_for_pipe_off(dev, pipe); |
0b8765c6 JB |
2433 | } |
2434 | ||
5eddb70b CW |
2435 | reg = DPLL(pipe); |
2436 | temp = I915_READ(reg); | |
2437 | if (temp & DPLL_VCO_ENABLE) { | |
2438 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
0b8765c6 | 2439 | |
5eddb70b CW |
2440 | /* Wait for the clocks to turn off. */ |
2441 | POSTING_READ(reg); | |
2442 | udelay(150); | |
0b8765c6 | 2443 | } |
6b383a7f CW |
2444 | |
2445 | done: | |
f7abfe8b | 2446 | intel_crtc->active = false; |
6b383a7f CW |
2447 | intel_update_fbc(dev); |
2448 | intel_update_watermarks(dev); | |
2449 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2450 | } |
2451 | ||
2452 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2453 | { | |
2454 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2455 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2456 | */ | |
2457 | switch (mode) { | |
2458 | case DRM_MODE_DPMS_ON: | |
2459 | case DRM_MODE_DPMS_STANDBY: | |
2460 | case DRM_MODE_DPMS_SUSPEND: | |
2461 | i9xx_crtc_enable(crtc); | |
2462 | break; | |
2463 | case DRM_MODE_DPMS_OFF: | |
2464 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2465 | break; |
2466 | } | |
2c07245f ZW |
2467 | } |
2468 | ||
2469 | /** | |
2470 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2471 | */ |
2472 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2473 | { | |
2474 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2475 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2476 | struct drm_i915_master_private *master_priv; |
2477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2478 | int pipe = intel_crtc->pipe; | |
2479 | bool enabled; | |
2480 | ||
032d2a0d CW |
2481 | if (intel_crtc->dpms_mode == mode) |
2482 | return; | |
2483 | ||
65655d4a | 2484 | intel_crtc->dpms_mode = mode; |
debcaddc | 2485 | |
e70236a8 | 2486 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2487 | |
2488 | if (!dev->primary->master) | |
2489 | return; | |
2490 | ||
2491 | master_priv = dev->primary->master->driver_priv; | |
2492 | if (!master_priv->sarea_priv) | |
2493 | return; | |
2494 | ||
2495 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2496 | ||
2497 | switch (pipe) { | |
2498 | case 0: | |
2499 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2500 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2501 | break; | |
2502 | case 1: | |
2503 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2504 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2505 | break; | |
2506 | default: | |
2507 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2508 | break; | |
2509 | } | |
79e53945 JB |
2510 | } |
2511 | ||
cdd59983 CW |
2512 | static void intel_crtc_disable(struct drm_crtc *crtc) |
2513 | { | |
2514 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2515 | struct drm_device *dev = crtc->dev; | |
2516 | ||
2517 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
2518 | ||
2519 | if (crtc->fb) { | |
2520 | mutex_lock(&dev->struct_mutex); | |
2521 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
2522 | mutex_unlock(&dev->struct_mutex); | |
2523 | } | |
2524 | } | |
2525 | ||
7e7d76c3 JB |
2526 | /* Prepare for a mode set. |
2527 | * | |
2528 | * Note we could be a lot smarter here. We need to figure out which outputs | |
2529 | * will be enabled, which disabled (in short, how the config will changes) | |
2530 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
2531 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
2532 | * panel fitting is in the proper state, etc. | |
2533 | */ | |
2534 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 2535 | { |
7e7d76c3 | 2536 | i9xx_crtc_disable(crtc); |
79e53945 JB |
2537 | } |
2538 | ||
7e7d76c3 | 2539 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 2540 | { |
7e7d76c3 | 2541 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
2542 | } |
2543 | ||
2544 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
2545 | { | |
7e7d76c3 | 2546 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
2547 | } |
2548 | ||
2549 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
2550 | { | |
7e7d76c3 | 2551 | ironlake_crtc_enable(crtc); |
79e53945 JB |
2552 | } |
2553 | ||
2554 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2555 | { | |
2556 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2557 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2558 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2559 | } | |
2560 | ||
2561 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2562 | { | |
2563 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2564 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2565 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2566 | } | |
2567 | ||
ea5b213a CW |
2568 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2569 | { | |
4ef69c7a | 2570 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 2571 | |
ea5b213a CW |
2572 | drm_encoder_cleanup(encoder); |
2573 | kfree(intel_encoder); | |
2574 | } | |
2575 | ||
79e53945 JB |
2576 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2577 | struct drm_display_mode *mode, | |
2578 | struct drm_display_mode *adjusted_mode) | |
2579 | { | |
2c07245f | 2580 | struct drm_device *dev = crtc->dev; |
89749350 | 2581 | |
bad720ff | 2582 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2583 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2584 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2585 | return false; | |
2c07245f | 2586 | } |
89749350 CW |
2587 | |
2588 | /* XXX some encoders set the crtcinfo, others don't. | |
2589 | * Obviously we need some form of conflict resolution here... | |
2590 | */ | |
2591 | if (adjusted_mode->crtc_htotal == 0) | |
2592 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
2593 | ||
79e53945 JB |
2594 | return true; |
2595 | } | |
2596 | ||
e70236a8 JB |
2597 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2598 | { | |
2599 | return 400000; | |
2600 | } | |
79e53945 | 2601 | |
e70236a8 | 2602 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2603 | { |
e70236a8 JB |
2604 | return 333000; |
2605 | } | |
79e53945 | 2606 | |
e70236a8 JB |
2607 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2608 | { | |
2609 | return 200000; | |
2610 | } | |
79e53945 | 2611 | |
e70236a8 JB |
2612 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2613 | { | |
2614 | u16 gcfgc = 0; | |
79e53945 | 2615 | |
e70236a8 JB |
2616 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2617 | ||
2618 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2619 | return 133000; | |
2620 | else { | |
2621 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2622 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2623 | return 333000; | |
2624 | default: | |
2625 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2626 | return 190000; | |
79e53945 | 2627 | } |
e70236a8 JB |
2628 | } |
2629 | } | |
2630 | ||
2631 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2632 | { | |
2633 | return 266000; | |
2634 | } | |
2635 | ||
2636 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2637 | { | |
2638 | u16 hpllcc = 0; | |
2639 | /* Assume that the hardware is in the high speed state. This | |
2640 | * should be the default. | |
2641 | */ | |
2642 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2643 | case GC_CLOCK_133_200: | |
2644 | case GC_CLOCK_100_200: | |
2645 | return 200000; | |
2646 | case GC_CLOCK_166_250: | |
2647 | return 250000; | |
2648 | case GC_CLOCK_100_133: | |
79e53945 | 2649 | return 133000; |
e70236a8 | 2650 | } |
79e53945 | 2651 | |
e70236a8 JB |
2652 | /* Shouldn't happen */ |
2653 | return 0; | |
2654 | } | |
79e53945 | 2655 | |
e70236a8 JB |
2656 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2657 | { | |
2658 | return 133000; | |
79e53945 JB |
2659 | } |
2660 | ||
2c07245f ZW |
2661 | struct fdi_m_n { |
2662 | u32 tu; | |
2663 | u32 gmch_m; | |
2664 | u32 gmch_n; | |
2665 | u32 link_m; | |
2666 | u32 link_n; | |
2667 | }; | |
2668 | ||
2669 | static void | |
2670 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2671 | { | |
2672 | while (*num > 0xffffff || *den > 0xffffff) { | |
2673 | *num >>= 1; | |
2674 | *den >>= 1; | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | #define DATA_N 0x800000 | |
2679 | #define LINK_N 0x80000 | |
2680 | ||
2681 | static void | |
f2b115e6 AJ |
2682 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2683 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f ZW |
2684 | { |
2685 | u64 temp; | |
2686 | ||
2687 | m_n->tu = 64; /* default size */ | |
2688 | ||
2689 | temp = (u64) DATA_N * pixel_clock; | |
2690 | temp = div_u64(temp, link_clock); | |
58a27471 ZW |
2691 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
2692 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ | |
2c07245f ZW |
2693 | m_n->gmch_n = DATA_N; |
2694 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
2695 | ||
2696 | temp = (u64) LINK_N * pixel_clock; | |
2697 | m_n->link_m = div_u64(temp, link_clock); | |
2698 | m_n->link_n = LINK_N; | |
2699 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
2700 | } | |
2701 | ||
2702 | ||
7662c8bd SL |
2703 | struct intel_watermark_params { |
2704 | unsigned long fifo_size; | |
2705 | unsigned long max_wm; | |
2706 | unsigned long default_wm; | |
2707 | unsigned long guard_size; | |
2708 | unsigned long cacheline_size; | |
2709 | }; | |
2710 | ||
f2b115e6 AJ |
2711 | /* Pineview has different values for various configs */ |
2712 | static struct intel_watermark_params pineview_display_wm = { | |
2713 | PINEVIEW_DISPLAY_FIFO, | |
2714 | PINEVIEW_MAX_WM, | |
2715 | PINEVIEW_DFT_WM, | |
2716 | PINEVIEW_GUARD_WM, | |
2717 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2718 | }; |
f2b115e6 AJ |
2719 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2720 | PINEVIEW_DISPLAY_FIFO, | |
2721 | PINEVIEW_MAX_WM, | |
2722 | PINEVIEW_DFT_HPLLOFF_WM, | |
2723 | PINEVIEW_GUARD_WM, | |
2724 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2725 | }; |
f2b115e6 AJ |
2726 | static struct intel_watermark_params pineview_cursor_wm = { |
2727 | PINEVIEW_CURSOR_FIFO, | |
2728 | PINEVIEW_CURSOR_MAX_WM, | |
2729 | PINEVIEW_CURSOR_DFT_WM, | |
2730 | PINEVIEW_CURSOR_GUARD_WM, | |
2731 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2732 | }; |
f2b115e6 AJ |
2733 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2734 | PINEVIEW_CURSOR_FIFO, | |
2735 | PINEVIEW_CURSOR_MAX_WM, | |
2736 | PINEVIEW_CURSOR_DFT_WM, | |
2737 | PINEVIEW_CURSOR_GUARD_WM, | |
2738 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2739 | }; |
0e442c60 JB |
2740 | static struct intel_watermark_params g4x_wm_info = { |
2741 | G4X_FIFO_SIZE, | |
2742 | G4X_MAX_WM, | |
2743 | G4X_MAX_WM, | |
2744 | 2, | |
2745 | G4X_FIFO_LINE_SIZE, | |
2746 | }; | |
4fe5e611 ZY |
2747 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2748 | I965_CURSOR_FIFO, | |
2749 | I965_CURSOR_MAX_WM, | |
2750 | I965_CURSOR_DFT_WM, | |
2751 | 2, | |
2752 | G4X_FIFO_LINE_SIZE, | |
2753 | }; | |
2754 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2755 | I965_CURSOR_FIFO, | |
2756 | I965_CURSOR_MAX_WM, | |
2757 | I965_CURSOR_DFT_WM, | |
2758 | 2, | |
2759 | I915_FIFO_LINE_SIZE, | |
2760 | }; | |
7662c8bd | 2761 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2762 | I945_FIFO_SIZE, |
7662c8bd SL |
2763 | I915_MAX_WM, |
2764 | 1, | |
dff33cfc JB |
2765 | 2, |
2766 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2767 | }; |
2768 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2769 | I915_FIFO_SIZE, |
7662c8bd SL |
2770 | I915_MAX_WM, |
2771 | 1, | |
dff33cfc | 2772 | 2, |
7662c8bd SL |
2773 | I915_FIFO_LINE_SIZE |
2774 | }; | |
2775 | static struct intel_watermark_params i855_wm_info = { | |
2776 | I855GM_FIFO_SIZE, | |
2777 | I915_MAX_WM, | |
2778 | 1, | |
dff33cfc | 2779 | 2, |
7662c8bd SL |
2780 | I830_FIFO_LINE_SIZE |
2781 | }; | |
2782 | static struct intel_watermark_params i830_wm_info = { | |
2783 | I830_FIFO_SIZE, | |
2784 | I915_MAX_WM, | |
2785 | 1, | |
dff33cfc | 2786 | 2, |
7662c8bd SL |
2787 | I830_FIFO_LINE_SIZE |
2788 | }; | |
2789 | ||
7f8a8569 ZW |
2790 | static struct intel_watermark_params ironlake_display_wm_info = { |
2791 | ILK_DISPLAY_FIFO, | |
2792 | ILK_DISPLAY_MAXWM, | |
2793 | ILK_DISPLAY_DFTWM, | |
2794 | 2, | |
2795 | ILK_FIFO_LINE_SIZE | |
2796 | }; | |
2797 | ||
c936f44d ZY |
2798 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2799 | ILK_CURSOR_FIFO, | |
2800 | ILK_CURSOR_MAXWM, | |
2801 | ILK_CURSOR_DFTWM, | |
2802 | 2, | |
2803 | ILK_FIFO_LINE_SIZE | |
2804 | }; | |
2805 | ||
7f8a8569 ZW |
2806 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2807 | ILK_DISPLAY_SR_FIFO, | |
2808 | ILK_DISPLAY_MAX_SRWM, | |
2809 | ILK_DISPLAY_DFT_SRWM, | |
2810 | 2, | |
2811 | ILK_FIFO_LINE_SIZE | |
2812 | }; | |
2813 | ||
2814 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2815 | ILK_CURSOR_SR_FIFO, | |
2816 | ILK_CURSOR_MAX_SRWM, | |
2817 | ILK_CURSOR_DFT_SRWM, | |
2818 | 2, | |
2819 | ILK_FIFO_LINE_SIZE | |
2820 | }; | |
2821 | ||
dff33cfc JB |
2822 | /** |
2823 | * intel_calculate_wm - calculate watermark level | |
2824 | * @clock_in_khz: pixel clock | |
2825 | * @wm: chip FIFO params | |
2826 | * @pixel_size: display pixel size | |
2827 | * @latency_ns: memory latency for the platform | |
2828 | * | |
2829 | * Calculate the watermark level (the level at which the display plane will | |
2830 | * start fetching from memory again). Each chip has a different display | |
2831 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
2832 | * in the correct intel_watermark_params structure. | |
2833 | * | |
2834 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
2835 | * on the pixel size. When it reaches the watermark level, it'll start | |
2836 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
2837 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
2838 | * will occur, and a display engine hang could result. | |
2839 | */ | |
7662c8bd SL |
2840 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
2841 | struct intel_watermark_params *wm, | |
2842 | int pixel_size, | |
2843 | unsigned long latency_ns) | |
2844 | { | |
390c4dd4 | 2845 | long entries_required, wm_size; |
dff33cfc | 2846 | |
d660467c JB |
2847 | /* |
2848 | * Note: we need to make sure we don't overflow for various clock & | |
2849 | * latency values. | |
2850 | * clocks go from a few thousand to several hundred thousand. | |
2851 | * latency is usually a few thousand | |
2852 | */ | |
2853 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
2854 | 1000; | |
8de9b311 | 2855 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 2856 | |
28c97730 | 2857 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
2858 | |
2859 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
2860 | ||
28c97730 | 2861 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 2862 | |
390c4dd4 JB |
2863 | /* Don't promote wm_size to unsigned... */ |
2864 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 2865 | wm_size = wm->max_wm; |
c3add4b6 | 2866 | if (wm_size <= 0) |
7662c8bd SL |
2867 | wm_size = wm->default_wm; |
2868 | return wm_size; | |
2869 | } | |
2870 | ||
2871 | struct cxsr_latency { | |
2872 | int is_desktop; | |
95534263 | 2873 | int is_ddr3; |
7662c8bd SL |
2874 | unsigned long fsb_freq; |
2875 | unsigned long mem_freq; | |
2876 | unsigned long display_sr; | |
2877 | unsigned long display_hpll_disable; | |
2878 | unsigned long cursor_sr; | |
2879 | unsigned long cursor_hpll_disable; | |
2880 | }; | |
2881 | ||
403c89ff | 2882 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
2883 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
2884 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
2885 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
2886 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
2887 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
2888 | ||
2889 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
2890 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
2891 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
2892 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
2893 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
2894 | ||
2895 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
2896 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
2897 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
2898 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
2899 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
2900 | ||
2901 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
2902 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
2903 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
2904 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
2905 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
2906 | ||
2907 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
2908 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
2909 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
2910 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
2911 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
2912 | ||
2913 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
2914 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
2915 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
2916 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
2917 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
2918 | }; |
2919 | ||
403c89ff CW |
2920 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
2921 | int is_ddr3, | |
2922 | int fsb, | |
2923 | int mem) | |
7662c8bd | 2924 | { |
403c89ff | 2925 | const struct cxsr_latency *latency; |
7662c8bd | 2926 | int i; |
7662c8bd SL |
2927 | |
2928 | if (fsb == 0 || mem == 0) | |
2929 | return NULL; | |
2930 | ||
2931 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
2932 | latency = &cxsr_latency_table[i]; | |
2933 | if (is_desktop == latency->is_desktop && | |
95534263 | 2934 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
2935 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
2936 | return latency; | |
7662c8bd | 2937 | } |
decbbcda | 2938 | |
28c97730 | 2939 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
2940 | |
2941 | return NULL; | |
7662c8bd SL |
2942 | } |
2943 | ||
f2b115e6 | 2944 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
2945 | { |
2946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
2947 | |
2948 | /* deactivate cxsr */ | |
3e33d94d | 2949 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
2950 | } |
2951 | ||
bcc24fb4 JB |
2952 | /* |
2953 | * Latency for FIFO fetches is dependent on several factors: | |
2954 | * - memory configuration (speed, channels) | |
2955 | * - chipset | |
2956 | * - current MCH state | |
2957 | * It can be fairly high in some situations, so here we assume a fairly | |
2958 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
2959 | * set this value too high, the FIFO will fetch frequently to stay full) | |
2960 | * and power consumption (set it too low to save power and we might see | |
2961 | * FIFO underruns and display "flicker"). | |
2962 | * | |
2963 | * A value of 5us seems to be a good balance; safe for very low end | |
2964 | * platforms but not overly aggressive on lower latency configs. | |
2965 | */ | |
69e302a9 | 2966 | static const int latency_ns = 5000; |
7662c8bd | 2967 | |
e70236a8 | 2968 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
2969 | { |
2970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2971 | uint32_t dsparb = I915_READ(DSPARB); | |
2972 | int size; | |
2973 | ||
8de9b311 CW |
2974 | size = dsparb & 0x7f; |
2975 | if (plane) | |
2976 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 2977 | |
28c97730 | 2978 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 2979 | plane ? "B" : "A", size); |
dff33cfc JB |
2980 | |
2981 | return size; | |
2982 | } | |
7662c8bd | 2983 | |
e70236a8 JB |
2984 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
2985 | { | |
2986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2987 | uint32_t dsparb = I915_READ(DSPARB); | |
2988 | int size; | |
2989 | ||
8de9b311 CW |
2990 | size = dsparb & 0x1ff; |
2991 | if (plane) | |
2992 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 2993 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 2994 | |
28c97730 | 2995 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 2996 | plane ? "B" : "A", size); |
dff33cfc JB |
2997 | |
2998 | return size; | |
2999 | } | |
7662c8bd | 3000 | |
e70236a8 JB |
3001 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3002 | { | |
3003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3004 | uint32_t dsparb = I915_READ(DSPARB); | |
3005 | int size; | |
3006 | ||
3007 | size = dsparb & 0x7f; | |
3008 | size >>= 2; /* Convert to cachelines */ | |
3009 | ||
28c97730 | 3010 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3011 | plane ? "B" : "A", |
3012 | size); | |
e70236a8 JB |
3013 | |
3014 | return size; | |
3015 | } | |
3016 | ||
3017 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3018 | { | |
3019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3020 | uint32_t dsparb = I915_READ(DSPARB); | |
3021 | int size; | |
3022 | ||
3023 | size = dsparb & 0x7f; | |
3024 | size >>= 1; /* Convert to cachelines */ | |
3025 | ||
28c97730 | 3026 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3027 | plane ? "B" : "A", size); |
e70236a8 JB |
3028 | |
3029 | return size; | |
3030 | } | |
3031 | ||
d4294342 | 3032 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
5eddb70b CW |
3033 | int planeb_clock, int sr_hdisplay, int unused, |
3034 | int pixel_size) | |
d4294342 ZY |
3035 | { |
3036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3037 | const struct cxsr_latency *latency; |
d4294342 ZY |
3038 | u32 reg; |
3039 | unsigned long wm; | |
d4294342 ZY |
3040 | int sr_clock; |
3041 | ||
403c89ff | 3042 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3043 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3044 | if (!latency) { |
3045 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3046 | pineview_disable_cxsr(dev); | |
3047 | return; | |
3048 | } | |
3049 | ||
3050 | if (!planea_clock || !planeb_clock) { | |
3051 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3052 | ||
3053 | /* Display SR */ | |
3054 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3055 | pixel_size, latency->display_sr); | |
3056 | reg = I915_READ(DSPFW1); | |
3057 | reg &= ~DSPFW_SR_MASK; | |
3058 | reg |= wm << DSPFW_SR_SHIFT; | |
3059 | I915_WRITE(DSPFW1, reg); | |
3060 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3061 | ||
3062 | /* cursor SR */ | |
3063 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3064 | pixel_size, latency->cursor_sr); | |
3065 | reg = I915_READ(DSPFW3); | |
3066 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3067 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3068 | I915_WRITE(DSPFW3, reg); | |
3069 | ||
3070 | /* Display HPLL off SR */ | |
3071 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3072 | pixel_size, latency->display_hpll_disable); | |
3073 | reg = I915_READ(DSPFW3); | |
3074 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3075 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3076 | I915_WRITE(DSPFW3, reg); | |
3077 | ||
3078 | /* cursor HPLL off SR */ | |
3079 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3080 | pixel_size, latency->cursor_hpll_disable); | |
3081 | reg = I915_READ(DSPFW3); | |
3082 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3083 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3084 | I915_WRITE(DSPFW3, reg); | |
3085 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3086 | ||
3087 | /* activate cxsr */ | |
3e33d94d CW |
3088 | I915_WRITE(DSPFW3, |
3089 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3090 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3091 | } else { | |
3092 | pineview_disable_cxsr(dev); | |
3093 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3094 | } | |
3095 | } | |
3096 | ||
0e442c60 | 3097 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3098 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3099 | int pixel_size) | |
652c393a JB |
3100 | { |
3101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3102 | int total_size, cacheline_size; |
3103 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3104 | struct intel_watermark_params planea_params, planeb_params; | |
3105 | unsigned long line_time_us; | |
3106 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3107 | |
0e442c60 JB |
3108 | /* Create copies of the base settings for each pipe */ |
3109 | planea_params = planeb_params = g4x_wm_info; | |
3110 | ||
3111 | /* Grab a couple of global values before we overwrite them */ | |
3112 | total_size = planea_params.fifo_size; | |
3113 | cacheline_size = planea_params.cacheline_size; | |
3114 | ||
3115 | /* | |
3116 | * Note: we need to make sure we don't overflow for various clock & | |
3117 | * latency values. | |
3118 | * clocks go from a few thousand to several hundred thousand. | |
3119 | * latency is usually a few thousand | |
3120 | */ | |
3121 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3122 | 1000; | |
8de9b311 | 3123 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3124 | planea_wm = entries_required + planea_params.guard_size; |
3125 | ||
3126 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3127 | 1000; | |
8de9b311 | 3128 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3129 | planeb_wm = entries_required + planeb_params.guard_size; |
3130 | ||
3131 | cursora_wm = cursorb_wm = 16; | |
3132 | cursor_sr = 32; | |
3133 | ||
3134 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3135 | ||
3136 | /* Calc sr entries for one plane configs */ | |
3137 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3138 | /* self-refresh has much higher latency */ | |
69e302a9 | 3139 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3140 | |
3141 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3142 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3143 | |
3144 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3145 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3146 | pixel_size * sr_hdisplay; |
8de9b311 | 3147 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3148 | |
3149 | entries_required = (((sr_latency_ns / line_time_us) + | |
3150 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 | 3151 | entries_required = DIV_ROUND_UP(entries_required, |
5eddb70b | 3152 | g4x_cursor_wm_info.cacheline_size); |
4fe5e611 ZY |
3153 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3154 | ||
3155 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3156 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3157 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3158 | "cursor %d\n", sr_entries, cursor_sr); | |
3159 | ||
0e442c60 | 3160 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3161 | } else { |
3162 | /* Turn off self refresh if both pipes are enabled */ | |
3163 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
5eddb70b | 3164 | & ~FW_BLC_SELF_EN); |
0e442c60 JB |
3165 | } |
3166 | ||
3167 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3168 | planea_wm, planeb_wm, sr_entries); | |
3169 | ||
3170 | planea_wm &= 0x3f; | |
3171 | planeb_wm &= 0x3f; | |
3172 | ||
3173 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3174 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3175 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3176 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3177 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3178 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3179 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3180 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3181 | } |
3182 | ||
1dc7546d | 3183 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3184 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3185 | int pixel_size) | |
7662c8bd SL |
3186 | { |
3187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3188 | unsigned long line_time_us; |
3189 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3190 | int cursor_sr = 16; |
1dc7546d JB |
3191 | |
3192 | /* Calc sr entries for one plane configs */ | |
3193 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3194 | /* self-refresh has much higher latency */ | |
69e302a9 | 3195 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3196 | |
3197 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3198 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3199 | |
3200 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3201 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3202 | pixel_size * sr_hdisplay; |
8de9b311 | 3203 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3204 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3205 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3206 | if (srwm < 0) |
3207 | srwm = 1; | |
1b07e04e | 3208 | srwm &= 0x1ff; |
4fe5e611 ZY |
3209 | |
3210 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
5eddb70b | 3211 | pixel_size * 64; |
8de9b311 CW |
3212 | sr_entries = DIV_ROUND_UP(sr_entries, |
3213 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 | 3214 | cursor_sr = i965_cursor_wm_info.fifo_size - |
5eddb70b | 3215 | (sr_entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3216 | |
3217 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3218 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3219 | ||
3220 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3221 | "cursor %d\n", srwm, cursor_sr); | |
3222 | ||
a6c45cf0 | 3223 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3224 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3225 | } else { |
3226 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3227 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3228 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3229 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3230 | } |
7662c8bd | 3231 | |
1dc7546d JB |
3232 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3233 | srwm); | |
7662c8bd SL |
3234 | |
3235 | /* 965 has limitations... */ | |
1dc7546d JB |
3236 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3237 | (8 << 0)); | |
7662c8bd | 3238 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3239 | /* update cursor SR watermark */ |
3240 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3241 | } |
3242 | ||
3243 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3244 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3245 | int pixel_size) | |
7662c8bd SL |
3246 | { |
3247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3248 | uint32_t fwater_lo; |
3249 | uint32_t fwater_hi; | |
3250 | int total_size, cacheline_size, cwm, srwm = 1; | |
3251 | int planea_wm, planeb_wm; | |
3252 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3253 | unsigned long line_time_us; |
3254 | int sr_clock, sr_entries = 0; | |
3255 | ||
dff33cfc | 3256 | /* Create copies of the base settings for each pipe */ |
a6c45cf0 | 3257 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
dff33cfc | 3258 | planea_params = planeb_params = i945_wm_info; |
a6c45cf0 | 3259 | else if (!IS_GEN2(dev)) |
dff33cfc | 3260 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3261 | else |
dff33cfc | 3262 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3263 | |
dff33cfc JB |
3264 | /* Grab a couple of global values before we overwrite them */ |
3265 | total_size = planea_params.fifo_size; | |
3266 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3267 | |
dff33cfc | 3268 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3269 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3270 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3271 | |
dff33cfc JB |
3272 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3273 | pixel_size, latency_ns); | |
3274 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3275 | pixel_size, latency_ns); | |
28c97730 | 3276 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3277 | |
3278 | /* | |
3279 | * Overlay gets an aggressive default since video jitter is bad. | |
3280 | */ | |
3281 | cwm = 2; | |
3282 | ||
dff33cfc | 3283 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3284 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3285 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3286 | /* self-refresh has much higher latency */ |
69e302a9 | 3287 | static const int sr_latency_ns = 6000; |
dff33cfc | 3288 | |
7662c8bd | 3289 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3290 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3291 | |
3292 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3293 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3294 | pixel_size * sr_hdisplay; |
8de9b311 | 3295 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3296 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3297 | srwm = total_size - sr_entries; |
3298 | if (srwm < 0) | |
3299 | srwm = 1; | |
ee980b80 LP |
3300 | |
3301 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3302 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3303 | else if (IS_I915GM(dev)) { | |
3304 | /* 915M has a smaller SRWM field */ | |
3305 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3306 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3307 | } | |
33c5fd12 DJ |
3308 | } else { |
3309 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3310 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3311 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3312 | & ~FW_BLC_SELF_EN); | |
3313 | } else if (IS_I915GM(dev)) { | |
3314 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3315 | } | |
7662c8bd SL |
3316 | } |
3317 | ||
28c97730 | 3318 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 3319 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3320 | |
dff33cfc JB |
3321 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3322 | fwater_hi = (cwm & 0x1f); | |
3323 | ||
3324 | /* Set request length to 8 cachelines per fetch */ | |
3325 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3326 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3327 | |
3328 | I915_WRITE(FW_BLC, fwater_lo); | |
3329 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3330 | } |
3331 | ||
e70236a8 | 3332 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3333 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3334 | { |
3335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3336 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3337 | int planea_wm; |
7662c8bd | 3338 | |
e70236a8 | 3339 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3340 | |
dff33cfc JB |
3341 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3342 | pixel_size, latency_ns); | |
f3601326 JB |
3343 | fwater_lo |= (3<<8) | planea_wm; |
3344 | ||
28c97730 | 3345 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3346 | |
3347 | I915_WRITE(FW_BLC, fwater_lo); | |
3348 | } | |
3349 | ||
7f8a8569 | 3350 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3351 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 3352 | |
4ed765f9 CW |
3353 | static bool ironlake_compute_wm0(struct drm_device *dev, |
3354 | int pipe, | |
3355 | int *plane_wm, | |
3356 | int *cursor_wm) | |
7f8a8569 | 3357 | { |
c936f44d | 3358 | struct drm_crtc *crtc; |
4ed765f9 CW |
3359 | int htotal, hdisplay, clock, pixel_size = 0; |
3360 | int line_time_us, line_count, entries; | |
c936f44d | 3361 | |
4ed765f9 CW |
3362 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3363 | if (crtc->fb == NULL || !crtc->enabled) | |
3364 | return false; | |
7f8a8569 | 3365 | |
4ed765f9 CW |
3366 | htotal = crtc->mode.htotal; |
3367 | hdisplay = crtc->mode.hdisplay; | |
3368 | clock = crtc->mode.clock; | |
3369 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3370 | ||
3371 | /* Use the small buffer method to calculate plane watermark */ | |
3372 | entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000; | |
3373 | entries = DIV_ROUND_UP(entries, | |
3374 | ironlake_display_wm_info.cacheline_size); | |
3375 | *plane_wm = entries + ironlake_display_wm_info.guard_size; | |
3376 | if (*plane_wm > (int)ironlake_display_wm_info.max_wm) | |
3377 | *plane_wm = ironlake_display_wm_info.max_wm; | |
3378 | ||
3379 | /* Use the large buffer method to calculate cursor watermark */ | |
3380 | line_time_us = ((htotal * 1000) / clock); | |
3381 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; | |
3382 | entries = line_count * 64 * pixel_size; | |
3383 | entries = DIV_ROUND_UP(entries, | |
3384 | ironlake_cursor_wm_info.cacheline_size); | |
3385 | *cursor_wm = entries + ironlake_cursor_wm_info.guard_size; | |
3386 | if (*cursor_wm > ironlake_cursor_wm_info.max_wm) | |
3387 | *cursor_wm = ironlake_cursor_wm_info.max_wm; | |
7f8a8569 | 3388 | |
4ed765f9 CW |
3389 | return true; |
3390 | } | |
c936f44d | 3391 | |
4ed765f9 CW |
3392 | static void ironlake_update_wm(struct drm_device *dev, |
3393 | int planea_clock, int planeb_clock, | |
3394 | int sr_hdisplay, int sr_htotal, | |
3395 | int pixel_size) | |
3396 | { | |
3397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3398 | int plane_wm, cursor_wm, enabled; | |
3399 | int tmp; | |
c936f44d | 3400 | |
4ed765f9 CW |
3401 | enabled = 0; |
3402 | if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) { | |
3403 | I915_WRITE(WM0_PIPEA_ILK, | |
3404 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3405 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3406 | " plane %d, " "cursor: %d\n", | |
3407 | plane_wm, cursor_wm); | |
3408 | enabled++; | |
3409 | } | |
c936f44d | 3410 | |
4ed765f9 CW |
3411 | if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) { |
3412 | I915_WRITE(WM0_PIPEB_ILK, | |
3413 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3414 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3415 | " plane %d, cursor: %d\n", | |
3416 | plane_wm, cursor_wm); | |
3417 | enabled++; | |
7f8a8569 ZW |
3418 | } |
3419 | ||
3420 | /* | |
3421 | * Calculate and update the self-refresh watermark only when one | |
3422 | * display plane is used. | |
3423 | */ | |
4ed765f9 CW |
3424 | tmp = 0; |
3425 | if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) { | |
3426 | unsigned long line_time_us; | |
3427 | int small, large, plane_fbc; | |
3428 | int sr_clock, entries; | |
3429 | int line_count, line_size; | |
7f8a8569 ZW |
3430 | /* Read the self-refresh latency. The unit is 0.5us */ |
3431 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; | |
3432 | ||
3433 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
4ed765f9 | 3434 | line_time_us = (sr_htotal * 1000) / sr_clock; |
7f8a8569 ZW |
3435 | |
3436 | /* Use ns/us then divide to preserve precision */ | |
3437 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) | |
5eddb70b | 3438 | / 1000; |
4ed765f9 | 3439 | line_size = sr_hdisplay * pixel_size; |
7f8a8569 | 3440 | |
4ed765f9 CW |
3441 | /* Use the minimum of the small and large buffer method for primary */ |
3442 | small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000; | |
3443 | large = line_count * line_size; | |
7f8a8569 | 3444 | |
4ed765f9 CW |
3445 | entries = DIV_ROUND_UP(min(small, large), |
3446 | ironlake_display_srwm_info.cacheline_size); | |
7f8a8569 | 3447 | |
4ed765f9 CW |
3448 | plane_fbc = entries * 64; |
3449 | plane_fbc = DIV_ROUND_UP(plane_fbc, line_size); | |
7f8a8569 | 3450 | |
4ed765f9 CW |
3451 | plane_wm = entries + ironlake_display_srwm_info.guard_size; |
3452 | if (plane_wm > (int)ironlake_display_srwm_info.max_wm) | |
3453 | plane_wm = ironlake_display_srwm_info.max_wm; | |
7f8a8569 | 3454 | |
4ed765f9 CW |
3455 | /* calculate the self-refresh watermark for display cursor */ |
3456 | entries = line_count * pixel_size * 64; | |
3457 | entries = DIV_ROUND_UP(entries, | |
3458 | ironlake_cursor_srwm_info.cacheline_size); | |
3459 | ||
3460 | cursor_wm = entries + ironlake_cursor_srwm_info.guard_size; | |
3461 | if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm) | |
3462 | cursor_wm = ironlake_cursor_srwm_info.max_wm; | |
3463 | ||
3464 | /* configure watermark and enable self-refresh */ | |
3465 | tmp = (WM1_LP_SR_EN | | |
3466 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | | |
3467 | (plane_fbc << WM1_LP_FBC_SHIFT) | | |
3468 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3469 | cursor_wm); | |
3470 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d," | |
3471 | " cursor %d\n", plane_wm, plane_fbc, cursor_wm); | |
7f8a8569 | 3472 | } |
4ed765f9 CW |
3473 | I915_WRITE(WM1_LP_ILK, tmp); |
3474 | /* XXX setup WM2 and WM3 */ | |
7f8a8569 | 3475 | } |
4ed765f9 | 3476 | |
7662c8bd SL |
3477 | /** |
3478 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3479 | * | |
3480 | * Calculate watermark values for the various WM regs based on current mode | |
3481 | * and plane configuration. | |
3482 | * | |
3483 | * There are several cases to deal with here: | |
3484 | * - normal (i.e. non-self-refresh) | |
3485 | * - self-refresh (SR) mode | |
3486 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3487 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3488 | * lines), so need to account for TLB latency | |
3489 | * | |
3490 | * The normal calculation is: | |
3491 | * watermark = dotclock * bytes per pixel * latency | |
3492 | * where latency is platform & configuration dependent (we assume pessimal | |
3493 | * values here). | |
3494 | * | |
3495 | * The SR calculation is: | |
3496 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3497 | * bytes per pixel | |
3498 | * where | |
3499 | * line time = htotal / dotclock | |
fa143215 | 3500 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3501 | * and latency is assumed to be high, as above. |
3502 | * | |
3503 | * The final value programmed to the register should always be rounded up, | |
3504 | * and include an extra 2 entries to account for clock crossings. | |
3505 | * | |
3506 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3507 | * to set the non-SR watermarks to 8. | |
5eddb70b | 3508 | */ |
7662c8bd SL |
3509 | static void intel_update_watermarks(struct drm_device *dev) |
3510 | { | |
e70236a8 | 3511 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3512 | struct drm_crtc *crtc; |
7662c8bd SL |
3513 | int sr_hdisplay = 0; |
3514 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3515 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3516 | int sr_htotal = 0; |
7662c8bd | 3517 | |
c03342fa ZW |
3518 | if (!dev_priv->display.update_wm) |
3519 | return; | |
3520 | ||
7662c8bd SL |
3521 | /* Get the clock config from both planes */ |
3522 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc | 3523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f7abfe8b | 3524 | if (intel_crtc->active) { |
7662c8bd SL |
3525 | enabled++; |
3526 | if (intel_crtc->plane == 0) { | |
28c97730 | 3527 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
5eddb70b | 3528 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3529 | planea_clock = crtc->mode.clock; |
3530 | } else { | |
28c97730 | 3531 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
5eddb70b | 3532 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3533 | planeb_clock = crtc->mode.clock; |
3534 | } | |
3535 | sr_hdisplay = crtc->mode.hdisplay; | |
3536 | sr_clock = crtc->mode.clock; | |
fa143215 | 3537 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3538 | if (crtc->fb) |
3539 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3540 | else | |
3541 | pixel_size = 4; /* by default */ | |
3542 | } | |
3543 | } | |
3544 | ||
3545 | if (enabled <= 0) | |
3546 | return; | |
3547 | ||
e70236a8 | 3548 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3549 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3550 | } |
3551 | ||
5c3b82e2 CW |
3552 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3553 | struct drm_display_mode *mode, | |
3554 | struct drm_display_mode *adjusted_mode, | |
3555 | int x, int y, | |
3556 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3557 | { |
3558 | struct drm_device *dev = crtc->dev; | |
3559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3561 | int pipe = intel_crtc->pipe; | |
80824003 | 3562 | int plane = intel_crtc->plane; |
5eddb70b | 3563 | u32 fp_reg, dpll_reg; |
c751ce4f | 3564 | int refclk, num_connectors = 0; |
652c393a | 3565 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3566 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 3567 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 3568 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3569 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3570 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3571 | struct intel_encoder *encoder; |
d4906093 | 3572 | const intel_limit_t *limit; |
5c3b82e2 | 3573 | int ret; |
2c07245f | 3574 | struct fdi_m_n m_n = {0}; |
5eddb70b | 3575 | u32 reg, temp; |
5eb08b69 | 3576 | int target_clock; |
79e53945 JB |
3577 | |
3578 | drm_vblank_pre_modeset(dev, pipe); | |
3579 | ||
5eddb70b CW |
3580 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3581 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3582 | continue; |
3583 | ||
5eddb70b | 3584 | switch (encoder->type) { |
79e53945 JB |
3585 | case INTEL_OUTPUT_LVDS: |
3586 | is_lvds = true; | |
3587 | break; | |
3588 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3589 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3590 | is_sdvo = true; |
5eddb70b | 3591 | if (encoder->needs_tv_clock) |
e2f0ba97 | 3592 | is_tv = true; |
79e53945 JB |
3593 | break; |
3594 | case INTEL_OUTPUT_DVO: | |
3595 | is_dvo = true; | |
3596 | break; | |
3597 | case INTEL_OUTPUT_TVOUT: | |
3598 | is_tv = true; | |
3599 | break; | |
3600 | case INTEL_OUTPUT_ANALOG: | |
3601 | is_crt = true; | |
3602 | break; | |
a4fc5ed6 KP |
3603 | case INTEL_OUTPUT_DISPLAYPORT: |
3604 | is_dp = true; | |
3605 | break; | |
32f9d658 | 3606 | case INTEL_OUTPUT_EDP: |
5eddb70b | 3607 | has_edp_encoder = encoder; |
32f9d658 | 3608 | break; |
79e53945 | 3609 | } |
43565a06 | 3610 | |
c751ce4f | 3611 | num_connectors++; |
79e53945 JB |
3612 | } |
3613 | ||
c751ce4f | 3614 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
43565a06 | 3615 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 3616 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 3617 | refclk / 1000); |
a6c45cf0 | 3618 | } else if (!IS_GEN2(dev)) { |
79e53945 | 3619 | refclk = 96000; |
bad720ff | 3620 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3621 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
3622 | } else { |
3623 | refclk = 48000; | |
3624 | } | |
3625 | ||
d4906093 ML |
3626 | /* |
3627 | * Returns a set of divisors for the desired target clock with the given | |
3628 | * refclk, or FALSE. The returned values represent the clock equation: | |
3629 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3630 | */ | |
3631 | limit = intel_limit(crtc); | |
3632 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
3633 | if (!ok) { |
3634 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 3635 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 3636 | return -EINVAL; |
79e53945 JB |
3637 | } |
3638 | ||
cda4b7d3 | 3639 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 3640 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 3641 | |
ddc9003c ZY |
3642 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
3643 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
3644 | dev_priv->lvds_downclock, |
3645 | refclk, | |
3646 | &reduced_clock); | |
18f9ed12 ZY |
3647 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
3648 | /* | |
3649 | * If the different P is found, it means that we can't | |
3650 | * switch the display clock by using the FP0/FP1. | |
3651 | * In such case we will disable the LVDS downclock | |
3652 | * feature. | |
3653 | */ | |
3654 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 3655 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
3656 | has_reduced_clock = 0; |
3657 | } | |
652c393a | 3658 | } |
7026d4ac ZW |
3659 | /* SDVO TV has fixed PLL values depend on its clock range, |
3660 | this mirrors vbios setting. */ | |
3661 | if (is_sdvo && is_tv) { | |
3662 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 3663 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
3664 | clock.p1 = 2; |
3665 | clock.p2 = 10; | |
3666 | clock.n = 3; | |
3667 | clock.m1 = 16; | |
3668 | clock.m2 = 8; | |
3669 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 3670 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
3671 | clock.p1 = 1; |
3672 | clock.p2 = 10; | |
3673 | clock.n = 6; | |
3674 | clock.m1 = 12; | |
3675 | clock.m2 = 8; | |
3676 | } | |
3677 | } | |
3678 | ||
2c07245f | 3679 | /* FDI link */ |
bad720ff | 3680 | if (HAS_PCH_SPLIT(dev)) { |
77ffb597 | 3681 | int lane = 0, link_bw, bpp; |
5c5313c8 | 3682 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
32f9d658 | 3683 | according to current link config */ |
5c5313c8 | 3684 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) { |
5eb08b69 | 3685 | target_clock = mode->clock; |
8e647a27 CW |
3686 | intel_edp_link_config(has_edp_encoder, |
3687 | &lane, &link_bw); | |
32f9d658 | 3688 | } else { |
5c5313c8 | 3689 | /* [e]DP over FDI requires target mode clock |
32f9d658 | 3690 | instead of link clock */ |
5c5313c8 | 3691 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
32f9d658 ZW |
3692 | target_clock = mode->clock; |
3693 | else | |
3694 | target_clock = adjusted_mode->clock; | |
021357ac CW |
3695 | |
3696 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
3697 | * each output octet as 10 bits. The actual frequency | |
3698 | * is stored as a divider into a 100MHz clock, and the | |
3699 | * mode pixel clock is stored in units of 1KHz. | |
3700 | * Hence the bw of each lane in terms of the mode signal | |
3701 | * is: | |
3702 | */ | |
3703 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 3704 | } |
58a27471 ZW |
3705 | |
3706 | /* determine panel color depth */ | |
5eddb70b | 3707 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
3708 | temp &= ~PIPE_BPC_MASK; |
3709 | if (is_lvds) { | |
e5a95eb7 | 3710 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 3711 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
3712 | temp |= PIPE_8BPC; |
3713 | else | |
3714 | temp |= PIPE_6BPC; | |
1d850362 | 3715 | } else if (has_edp_encoder) { |
5ceb0f9b | 3716 | switch (dev_priv->edp.bpp/3) { |
885a5fb5 ZW |
3717 | case 8: |
3718 | temp |= PIPE_8BPC; | |
3719 | break; | |
3720 | case 10: | |
3721 | temp |= PIPE_10BPC; | |
3722 | break; | |
3723 | case 6: | |
3724 | temp |= PIPE_6BPC; | |
3725 | break; | |
3726 | case 12: | |
3727 | temp |= PIPE_12BPC; | |
3728 | break; | |
3729 | } | |
e5a95eb7 ZY |
3730 | } else |
3731 | temp |= PIPE_8BPC; | |
5eddb70b | 3732 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
3733 | |
3734 | switch (temp & PIPE_BPC_MASK) { | |
3735 | case PIPE_8BPC: | |
3736 | bpp = 24; | |
3737 | break; | |
3738 | case PIPE_10BPC: | |
3739 | bpp = 30; | |
3740 | break; | |
3741 | case PIPE_6BPC: | |
3742 | bpp = 18; | |
3743 | break; | |
3744 | case PIPE_12BPC: | |
3745 | bpp = 36; | |
3746 | break; | |
3747 | default: | |
3748 | DRM_ERROR("unknown pipe bpc value\n"); | |
3749 | bpp = 24; | |
3750 | } | |
3751 | ||
77ffb597 AJ |
3752 | if (!lane) { |
3753 | /* | |
3754 | * Account for spread spectrum to avoid | |
3755 | * oversubscribing the link. Max center spread | |
3756 | * is 2.5%; use 5% for safety's sake. | |
3757 | */ | |
3758 | u32 bps = target_clock * bpp * 21 / 20; | |
3759 | lane = bps / (link_bw * 8) + 1; | |
3760 | } | |
3761 | ||
3762 | intel_crtc->fdi_lanes = lane; | |
3763 | ||
f2b115e6 | 3764 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 3765 | } |
2c07245f | 3766 | |
c038e51e ZW |
3767 | /* Ironlake: try to setup display ref clock before DPLL |
3768 | * enabling. This is only under driver's control after | |
3769 | * PCH B stepping, previous chipset stepping should be | |
3770 | * ignoring this setting. | |
3771 | */ | |
bad720ff | 3772 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
3773 | temp = I915_READ(PCH_DREF_CONTROL); |
3774 | /* Always enable nonspread source */ | |
3775 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
3776 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
c038e51e ZW |
3777 | temp &= ~DREF_SSC_SOURCE_MASK; |
3778 | temp |= DREF_SSC_SOURCE_ENABLE; | |
3779 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3780 | |
5eddb70b | 3781 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
3782 | udelay(200); |
3783 | ||
8e647a27 | 3784 | if (has_edp_encoder) { |
c038e51e ZW |
3785 | if (dev_priv->lvds_use_ssc) { |
3786 | temp |= DREF_SSC1_ENABLE; | |
3787 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3788 | |
5eddb70b | 3789 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
3790 | udelay(200); |
3791 | ||
3792 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
3793 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
c038e51e ZW |
3794 | } else { |
3795 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
c038e51e | 3796 | } |
5eddb70b | 3797 | I915_WRITE(PCH_DREF_CONTROL, temp); |
c038e51e ZW |
3798 | } |
3799 | } | |
3800 | ||
f2b115e6 | 3801 | if (IS_PINEVIEW(dev)) { |
2177832f | 3802 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3803 | if (has_reduced_clock) |
3804 | fp2 = (1 << reduced_clock.n) << 16 | | |
3805 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
3806 | } else { | |
2177832f | 3807 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3808 | if (has_reduced_clock) |
3809 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
3810 | reduced_clock.m2; | |
3811 | } | |
79e53945 | 3812 | |
5eddb70b | 3813 | dpll = 0; |
bad720ff | 3814 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
3815 | dpll = DPLL_VGA_MODE_DIS; |
3816 | ||
a6c45cf0 | 3817 | if (!IS_GEN2(dev)) { |
79e53945 JB |
3818 | if (is_lvds) |
3819 | dpll |= DPLLB_MODE_LVDS; | |
3820 | else | |
3821 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
3822 | if (is_sdvo) { | |
6c9547ff CW |
3823 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
3824 | if (pixel_multiplier > 1) { | |
3825 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
3826 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
3827 | else if (HAS_PCH_SPLIT(dev)) | |
3828 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
3829 | } | |
79e53945 | 3830 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 3831 | } |
a4fc5ed6 KP |
3832 | if (is_dp) |
3833 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 JB |
3834 | |
3835 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
3836 | if (IS_PINEVIEW(dev)) |
3837 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 3838 | else { |
2177832f | 3839 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 3840 | /* also FPA1 */ |
bad720ff | 3841 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3842 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
3843 | if (IS_G4X(dev) && has_reduced_clock) |
3844 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 3845 | } |
79e53945 JB |
3846 | switch (clock.p2) { |
3847 | case 5: | |
3848 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
3849 | break; | |
3850 | case 7: | |
3851 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
3852 | break; | |
3853 | case 10: | |
3854 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
3855 | break; | |
3856 | case 14: | |
3857 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
3858 | break; | |
3859 | } | |
a6c45cf0 | 3860 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
3861 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
3862 | } else { | |
3863 | if (is_lvds) { | |
3864 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3865 | } else { | |
3866 | if (clock.p1 == 2) | |
3867 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
3868 | else | |
3869 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3870 | if (clock.p2 == 4) | |
3871 | dpll |= PLL_P2_DIVIDE_BY_4; | |
3872 | } | |
3873 | } | |
3874 | ||
43565a06 KH |
3875 | if (is_sdvo && is_tv) |
3876 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
3877 | else if (is_tv) | |
79e53945 | 3878 | /* XXX: just matching BIOS for now */ |
43565a06 | 3879 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 3880 | dpll |= 3; |
c751ce4f | 3881 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
43565a06 | 3882 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
3883 | else |
3884 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3885 | ||
3886 | /* setup pipeconf */ | |
5eddb70b | 3887 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
3888 | |
3889 | /* Set up the display plane register */ | |
3890 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
3891 | ||
f2b115e6 | 3892 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 3893 | enable color space conversion */ |
bad720ff | 3894 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 3895 | if (pipe == 0) |
80824003 | 3896 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
3897 | else |
3898 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3899 | } | |
79e53945 | 3900 | |
a6c45cf0 | 3901 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
3902 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
3903 | * core speed. | |
3904 | * | |
3905 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
3906 | * pipe == 0 check? | |
3907 | */ | |
e70236a8 JB |
3908 | if (mode->clock > |
3909 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 3910 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 3911 | else |
5eddb70b | 3912 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
3913 | } |
3914 | ||
8d86dc6a | 3915 | dspcntr |= DISPLAY_PLANE_ENABLE; |
5eddb70b | 3916 | pipeconf |= PIPECONF_ENABLE; |
8d86dc6a LT |
3917 | dpll |= DPLL_VCO_ENABLE; |
3918 | ||
28c97730 | 3919 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
3920 | drm_mode_debug_printmodeline(mode); |
3921 | ||
f2b115e6 | 3922 | /* assign to Ironlake registers */ |
bad720ff | 3923 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
3924 | fp_reg = PCH_FP0(pipe); |
3925 | dpll_reg = PCH_DPLL(pipe); | |
3926 | } else { | |
3927 | fp_reg = FP0(pipe); | |
3928 | dpll_reg = DPLL(pipe); | |
2c07245f | 3929 | } |
79e53945 | 3930 | |
5c5313c8 JB |
3931 | /* PCH eDP needs FDI, but CPU eDP does not */ |
3932 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
79e53945 JB |
3933 | I915_WRITE(fp_reg, fp); |
3934 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
3935 | |
3936 | POSTING_READ(dpll_reg); | |
79e53945 JB |
3937 | udelay(150); |
3938 | } | |
3939 | ||
8db9d77b ZW |
3940 | /* enable transcoder DPLL */ |
3941 | if (HAS_PCH_CPT(dev)) { | |
3942 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b CW |
3943 | if (pipe == 0) |
3944 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
8db9d77b | 3945 | else |
5eddb70b | 3946 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
8db9d77b | 3947 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
3948 | |
3949 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
3950 | udelay(150); |
3951 | } | |
3952 | ||
79e53945 JB |
3953 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
3954 | * This is an exception to the general rule that mode_set doesn't turn | |
3955 | * things on. | |
3956 | */ | |
3957 | if (is_lvds) { | |
5eddb70b | 3958 | reg = LVDS; |
bad720ff | 3959 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 3960 | reg = PCH_LVDS; |
541998a1 | 3961 | |
5eddb70b CW |
3962 | temp = I915_READ(reg); |
3963 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
3964 | if (pipe == 1) { |
3965 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 3966 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 3967 | else |
5eddb70b | 3968 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
3969 | } else { |
3970 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 3971 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 3972 | else |
5eddb70b | 3973 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 3974 | } |
a3e17eb8 | 3975 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 3976 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
3977 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
3978 | * set the DPLLs for dual-channel mode or not. | |
3979 | */ | |
3980 | if (clock.p2 == 7) | |
5eddb70b | 3981 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 3982 | else |
5eddb70b | 3983 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
3984 | |
3985 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
3986 | * appropriately here, but we need to look more thoroughly into how | |
3987 | * panels behave in the two modes. | |
3988 | */ | |
434ed097 | 3989 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 3990 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 3991 | if (dev_priv->lvds_dither) |
5eddb70b | 3992 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 3993 | else |
5eddb70b | 3994 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 3995 | } |
5eddb70b | 3996 | I915_WRITE(reg, temp); |
79e53945 | 3997 | } |
434ed097 JB |
3998 | |
3999 | /* set the dithering flag and clear for anything other than a panel. */ | |
4000 | if (HAS_PCH_SPLIT(dev)) { | |
4001 | pipeconf &= ~PIPECONF_DITHER_EN; | |
4002 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
4003 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
4004 | pipeconf |= PIPECONF_DITHER_EN; | |
4005 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
4006 | } | |
4007 | } | |
4008 | ||
5c5313c8 | 4009 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 4010 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5c5313c8 | 4011 | } else if (HAS_PCH_SPLIT(dev)) { |
8db9d77b ZW |
4012 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
4013 | if (pipe == 0) { | |
4014 | I915_WRITE(TRANSA_DATA_M1, 0); | |
4015 | I915_WRITE(TRANSA_DATA_N1, 0); | |
4016 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
4017 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
4018 | } else { | |
4019 | I915_WRITE(TRANSB_DATA_M1, 0); | |
4020 | I915_WRITE(TRANSB_DATA_N1, 0); | |
4021 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
4022 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
4023 | } | |
4024 | } | |
79e53945 | 4025 | |
5c5313c8 | 4026 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
32f9d658 | 4027 | I915_WRITE(fp_reg, fp); |
79e53945 | 4028 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 4029 | |
32f9d658 | 4030 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4031 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
4032 | udelay(150); |
4033 | ||
a6c45cf0 | 4034 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 4035 | temp = 0; |
bb66c512 | 4036 | if (is_sdvo) { |
5eddb70b CW |
4037 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4038 | if (temp > 1) | |
4039 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 4040 | else |
5eddb70b CW |
4041 | temp = 0; |
4042 | } | |
4043 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 ZW |
4044 | } else { |
4045 | /* write it again -- the BIOS does, after all */ | |
4046 | I915_WRITE(dpll_reg, dpll); | |
4047 | } | |
5eddb70b | 4048 | |
32f9d658 | 4049 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4050 | POSTING_READ(dpll_reg); |
32f9d658 | 4051 | udelay(150); |
79e53945 | 4052 | } |
79e53945 | 4053 | |
5eddb70b | 4054 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
4055 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4056 | I915_WRITE(fp_reg + 4, fp2); | |
4057 | intel_crtc->lowfreq_avail = true; | |
4058 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4059 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4060 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4061 | } | |
4062 | } else { | |
4063 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 4064 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 4065 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4066 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4067 | } | |
4068 | } | |
4069 | ||
734b4157 KH |
4070 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4071 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4072 | /* the chip adds 2 halflines automatically */ | |
4073 | adjusted_mode->crtc_vdisplay -= 1; | |
4074 | adjusted_mode->crtc_vtotal -= 1; | |
4075 | adjusted_mode->crtc_vblank_start -= 1; | |
4076 | adjusted_mode->crtc_vblank_end -= 1; | |
4077 | adjusted_mode->crtc_vsync_end -= 1; | |
4078 | adjusted_mode->crtc_vsync_start -= 1; | |
4079 | } else | |
4080 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4081 | ||
5eddb70b CW |
4082 | I915_WRITE(HTOTAL(pipe), |
4083 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4084 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4085 | I915_WRITE(HBLANK(pipe), |
4086 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4087 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4088 | I915_WRITE(HSYNC(pipe), |
4089 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4090 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4091 | |
4092 | I915_WRITE(VTOTAL(pipe), | |
4093 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4094 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4095 | I915_WRITE(VBLANK(pipe), |
4096 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4097 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4098 | I915_WRITE(VSYNC(pipe), |
4099 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4100 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4101 | |
4102 | /* pipesrc and dspsize control the size that is scaled from, | |
4103 | * which should always be the user's requested size. | |
79e53945 | 4104 | */ |
bad720ff | 4105 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4106 | I915_WRITE(DSPSIZE(plane), |
4107 | ((mode->vdisplay - 1) << 16) | | |
4108 | (mode->hdisplay - 1)); | |
4109 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4110 | } |
5eddb70b CW |
4111 | I915_WRITE(PIPESRC(pipe), |
4112 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4113 | |
bad720ff | 4114 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4115 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4116 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4117 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4118 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4119 | |
5c5313c8 | 4120 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
f2b115e6 | 4121 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 ZW |
4122 | } else { |
4123 | /* enable FDI RX PLL too */ | |
5eddb70b CW |
4124 | reg = FDI_RX_CTL(pipe); |
4125 | temp = I915_READ(reg); | |
4126 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
4127 | ||
4128 | POSTING_READ(reg); | |
8db9d77b ZW |
4129 | udelay(200); |
4130 | ||
4131 | /* enable FDI TX PLL too */ | |
5eddb70b CW |
4132 | reg = FDI_TX_CTL(pipe); |
4133 | temp = I915_READ(reg); | |
4134 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
8db9d77b ZW |
4135 | |
4136 | /* enable FDI RX PCDCLK */ | |
5eddb70b CW |
4137 | reg = FDI_RX_CTL(pipe); |
4138 | temp = I915_READ(reg); | |
4139 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4140 | ||
4141 | POSTING_READ(reg); | |
32f9d658 ZW |
4142 | udelay(200); |
4143 | } | |
2c07245f ZW |
4144 | } |
4145 | ||
5eddb70b CW |
4146 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4147 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4148 | |
9d0498a2 | 4149 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4150 | |
c2416fc6 | 4151 | if (IS_IRONLAKE(dev)) { |
553bd149 ZW |
4152 | /* enable address swizzle for tiling buffer */ |
4153 | temp = I915_READ(DISP_ARB_CTL); | |
4154 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4155 | } | |
4156 | ||
5eddb70b | 4157 | I915_WRITE(DSPCNTR(plane), dspcntr); |
79e53945 | 4158 | |
5c3b82e2 | 4159 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4160 | |
4161 | intel_update_watermarks(dev); | |
4162 | ||
79e53945 | 4163 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4164 | |
1f803ee5 | 4165 | return ret; |
79e53945 JB |
4166 | } |
4167 | ||
4168 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4169 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4170 | { | |
4171 | struct drm_device *dev = crtc->dev; | |
4172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4174 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4175 | int i; | |
4176 | ||
4177 | /* The clocks have to be on to load the palette. */ | |
4178 | if (!crtc->enabled) | |
4179 | return; | |
4180 | ||
f2b115e6 | 4181 | /* use legacy palette for Ironlake */ |
bad720ff | 4182 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4183 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4184 | LGC_PALETTE_B; | |
4185 | ||
79e53945 JB |
4186 | for (i = 0; i < 256; i++) { |
4187 | I915_WRITE(palreg + 4 * i, | |
4188 | (intel_crtc->lut_r[i] << 16) | | |
4189 | (intel_crtc->lut_g[i] << 8) | | |
4190 | intel_crtc->lut_b[i]); | |
4191 | } | |
4192 | } | |
4193 | ||
560b85bb CW |
4194 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4195 | { | |
4196 | struct drm_device *dev = crtc->dev; | |
4197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4199 | bool visible = base != 0; | |
4200 | u32 cntl; | |
4201 | ||
4202 | if (intel_crtc->cursor_visible == visible) | |
4203 | return; | |
4204 | ||
4205 | cntl = I915_READ(CURACNTR); | |
4206 | if (visible) { | |
4207 | /* On these chipsets we can only modify the base whilst | |
4208 | * the cursor is disabled. | |
4209 | */ | |
4210 | I915_WRITE(CURABASE, base); | |
4211 | ||
4212 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4213 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4214 | cntl |= CURSOR_ENABLE | | |
4215 | CURSOR_GAMMA_ENABLE | | |
4216 | CURSOR_FORMAT_ARGB; | |
4217 | } else | |
4218 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4219 | I915_WRITE(CURACNTR, cntl); | |
4220 | ||
4221 | intel_crtc->cursor_visible = visible; | |
4222 | } | |
4223 | ||
4224 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4225 | { | |
4226 | struct drm_device *dev = crtc->dev; | |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4229 | int pipe = intel_crtc->pipe; | |
4230 | bool visible = base != 0; | |
4231 | ||
4232 | if (intel_crtc->cursor_visible != visible) { | |
4233 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4234 | if (base) { | |
4235 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4236 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4237 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4238 | } else { | |
4239 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4240 | cntl |= CURSOR_MODE_DISABLE; | |
4241 | } | |
4242 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4243 | ||
4244 | intel_crtc->cursor_visible = visible; | |
4245 | } | |
4246 | /* and commit changes on next vblank */ | |
4247 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4248 | } | |
4249 | ||
cda4b7d3 | 4250 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4251 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4252 | bool on) | |
cda4b7d3 CW |
4253 | { |
4254 | struct drm_device *dev = crtc->dev; | |
4255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4257 | int pipe = intel_crtc->pipe; | |
4258 | int x = intel_crtc->cursor_x; | |
4259 | int y = intel_crtc->cursor_y; | |
560b85bb | 4260 | u32 base, pos; |
cda4b7d3 CW |
4261 | bool visible; |
4262 | ||
4263 | pos = 0; | |
4264 | ||
6b383a7f | 4265 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4266 | base = intel_crtc->cursor_addr; |
4267 | if (x > (int) crtc->fb->width) | |
4268 | base = 0; | |
4269 | ||
4270 | if (y > (int) crtc->fb->height) | |
4271 | base = 0; | |
4272 | } else | |
4273 | base = 0; | |
4274 | ||
4275 | if (x < 0) { | |
4276 | if (x + intel_crtc->cursor_width < 0) | |
4277 | base = 0; | |
4278 | ||
4279 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4280 | x = -x; | |
4281 | } | |
4282 | pos |= x << CURSOR_X_SHIFT; | |
4283 | ||
4284 | if (y < 0) { | |
4285 | if (y + intel_crtc->cursor_height < 0) | |
4286 | base = 0; | |
4287 | ||
4288 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4289 | y = -y; | |
4290 | } | |
4291 | pos |= y << CURSOR_Y_SHIFT; | |
4292 | ||
4293 | visible = base != 0; | |
560b85bb | 4294 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4295 | return; |
4296 | ||
4297 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4298 | if (IS_845G(dev) || IS_I865G(dev)) |
4299 | i845_update_cursor(crtc, base); | |
4300 | else | |
4301 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4302 | |
4303 | if (visible) | |
4304 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4305 | } | |
4306 | ||
79e53945 JB |
4307 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
4308 | struct drm_file *file_priv, | |
4309 | uint32_t handle, | |
4310 | uint32_t width, uint32_t height) | |
4311 | { | |
4312 | struct drm_device *dev = crtc->dev; | |
4313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4314 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4315 | struct drm_gem_object *bo; | |
4316 | struct drm_i915_gem_object *obj_priv; | |
cda4b7d3 | 4317 | uint32_t addr; |
3f8bc370 | 4318 | int ret; |
79e53945 | 4319 | |
28c97730 | 4320 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4321 | |
4322 | /* if we want to turn off the cursor ignore width and height */ | |
4323 | if (!handle) { | |
28c97730 | 4324 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 KH |
4325 | addr = 0; |
4326 | bo = NULL; | |
5004417d | 4327 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4328 | goto finish; |
79e53945 JB |
4329 | } |
4330 | ||
4331 | /* Currently we only support 64x64 cursors */ | |
4332 | if (width != 64 || height != 64) { | |
4333 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4334 | return -EINVAL; | |
4335 | } | |
4336 | ||
4337 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
4338 | if (!bo) | |
4339 | return -ENOENT; | |
4340 | ||
23010e43 | 4341 | obj_priv = to_intel_bo(bo); |
79e53945 JB |
4342 | |
4343 | if (bo->size < width * height * 4) { | |
4344 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
4345 | ret = -ENOMEM; |
4346 | goto fail; | |
79e53945 JB |
4347 | } |
4348 | ||
71acb5eb | 4349 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4350 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4351 | if (!dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4352 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
4353 | if (ret) { | |
4354 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4355 | goto fail_locked; |
71acb5eb | 4356 | } |
e7b526bb CW |
4357 | |
4358 | ret = i915_gem_object_set_to_gtt_domain(bo, 0); | |
4359 | if (ret) { | |
4360 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4361 | goto fail_unpin; | |
4362 | } | |
4363 | ||
79e53945 | 4364 | addr = obj_priv->gtt_offset; |
71acb5eb | 4365 | } else { |
6eeefaf3 | 4366 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
cda4b7d3 | 4367 | ret = i915_gem_attach_phys_object(dev, bo, |
6eeefaf3 CW |
4368 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4369 | align); | |
71acb5eb DA |
4370 | if (ret) { |
4371 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4372 | goto fail_locked; |
71acb5eb DA |
4373 | } |
4374 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
4375 | } |
4376 | ||
a6c45cf0 | 4377 | if (IS_GEN2(dev)) |
14b60391 JB |
4378 | I915_WRITE(CURSIZE, (height << 12) | width); |
4379 | ||
3f8bc370 | 4380 | finish: |
3f8bc370 | 4381 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4382 | if (dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4383 | if (intel_crtc->cursor_bo != bo) |
4384 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
4385 | } else | |
4386 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
4387 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
4388 | } | |
80824003 | 4389 | |
7f9872e0 | 4390 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4391 | |
4392 | intel_crtc->cursor_addr = addr; | |
4393 | intel_crtc->cursor_bo = bo; | |
cda4b7d3 CW |
4394 | intel_crtc->cursor_width = width; |
4395 | intel_crtc->cursor_height = height; | |
4396 | ||
6b383a7f | 4397 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4398 | |
79e53945 | 4399 | return 0; |
e7b526bb CW |
4400 | fail_unpin: |
4401 | i915_gem_object_unpin(bo); | |
7f9872e0 | 4402 | fail_locked: |
34b8686e | 4403 | mutex_unlock(&dev->struct_mutex); |
bc9025bd LB |
4404 | fail: |
4405 | drm_gem_object_unreference_unlocked(bo); | |
34b8686e | 4406 | return ret; |
79e53945 JB |
4407 | } |
4408 | ||
4409 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4410 | { | |
79e53945 | 4411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4412 | |
cda4b7d3 CW |
4413 | intel_crtc->cursor_x = x; |
4414 | intel_crtc->cursor_y = y; | |
652c393a | 4415 | |
6b383a7f | 4416 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4417 | |
4418 | return 0; | |
4419 | } | |
4420 | ||
4421 | /** Sets the color ramps on behalf of RandR */ | |
4422 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4423 | u16 blue, int regno) | |
4424 | { | |
4425 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4426 | ||
4427 | intel_crtc->lut_r[regno] = red >> 8; | |
4428 | intel_crtc->lut_g[regno] = green >> 8; | |
4429 | intel_crtc->lut_b[regno] = blue >> 8; | |
4430 | } | |
4431 | ||
b8c00ac5 DA |
4432 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4433 | u16 *blue, int regno) | |
4434 | { | |
4435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4436 | ||
4437 | *red = intel_crtc->lut_r[regno] << 8; | |
4438 | *green = intel_crtc->lut_g[regno] << 8; | |
4439 | *blue = intel_crtc->lut_b[regno] << 8; | |
4440 | } | |
4441 | ||
79e53945 | 4442 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4443 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4444 | { |
7203425a | 4445 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4447 | |
7203425a | 4448 | for (i = start; i < end; i++) { |
79e53945 JB |
4449 | intel_crtc->lut_r[i] = red[i] >> 8; |
4450 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4451 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4452 | } | |
4453 | ||
4454 | intel_crtc_load_lut(crtc); | |
4455 | } | |
4456 | ||
4457 | /** | |
4458 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4459 | * detection. | |
4460 | * | |
4461 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4462 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4463 | * |
c751ce4f | 4464 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4465 | * configured for it. In the future, it could choose to temporarily disable |
4466 | * some outputs to free up a pipe for its use. | |
4467 | * | |
4468 | * \return crtc, or NULL if no pipes are available. | |
4469 | */ | |
4470 | ||
4471 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4472 | static struct drm_display_mode load_detect_mode = { | |
4473 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4474 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4475 | }; | |
4476 | ||
21d40d37 | 4477 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4478 | struct drm_connector *connector, |
79e53945 JB |
4479 | struct drm_display_mode *mode, |
4480 | int *dpms_mode) | |
4481 | { | |
4482 | struct intel_crtc *intel_crtc; | |
4483 | struct drm_crtc *possible_crtc; | |
4484 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4485 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4486 | struct drm_crtc *crtc = NULL; |
4487 | struct drm_device *dev = encoder->dev; | |
4488 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4489 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4490 | int i = -1; | |
4491 | ||
4492 | /* | |
4493 | * Algorithm gets a little messy: | |
4494 | * - if the connector already has an assigned crtc, use it (but make | |
4495 | * sure it's on first) | |
4496 | * - try to find the first unused crtc that can drive this connector, | |
4497 | * and use that if we find one | |
4498 | * - if there are no unused crtcs available, try to use the first | |
4499 | * one we found that supports the connector | |
4500 | */ | |
4501 | ||
4502 | /* See if we already have a CRTC for this connector */ | |
4503 | if (encoder->crtc) { | |
4504 | crtc = encoder->crtc; | |
4505 | /* Make sure the crtc and connector are running */ | |
4506 | intel_crtc = to_intel_crtc(crtc); | |
4507 | *dpms_mode = intel_crtc->dpms_mode; | |
4508 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4509 | crtc_funcs = crtc->helper_private; | |
4510 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4511 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4512 | } | |
4513 | return crtc; | |
4514 | } | |
4515 | ||
4516 | /* Find an unused one (if possible) */ | |
4517 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4518 | i++; | |
4519 | if (!(encoder->possible_crtcs & (1 << i))) | |
4520 | continue; | |
4521 | if (!possible_crtc->enabled) { | |
4522 | crtc = possible_crtc; | |
4523 | break; | |
4524 | } | |
4525 | if (!supported_crtc) | |
4526 | supported_crtc = possible_crtc; | |
4527 | } | |
4528 | ||
4529 | /* | |
4530 | * If we didn't find an unused CRTC, don't use any. | |
4531 | */ | |
4532 | if (!crtc) { | |
4533 | return NULL; | |
4534 | } | |
4535 | ||
4536 | encoder->crtc = crtc; | |
c1c43977 | 4537 | connector->encoder = encoder; |
21d40d37 | 4538 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4539 | |
4540 | intel_crtc = to_intel_crtc(crtc); | |
4541 | *dpms_mode = intel_crtc->dpms_mode; | |
4542 | ||
4543 | if (!crtc->enabled) { | |
4544 | if (!mode) | |
4545 | mode = &load_detect_mode; | |
3c4fdcfb | 4546 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4547 | } else { |
4548 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4549 | crtc_funcs = crtc->helper_private; | |
4550 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4551 | } | |
4552 | ||
4553 | /* Add this connector to the crtc */ | |
4554 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4555 | encoder_funcs->commit(encoder); | |
4556 | } | |
4557 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4558 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4559 | |
4560 | return crtc; | |
4561 | } | |
4562 | ||
c1c43977 ZW |
4563 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4564 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4565 | { |
4ef69c7a | 4566 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4567 | struct drm_device *dev = encoder->dev; |
4568 | struct drm_crtc *crtc = encoder->crtc; | |
4569 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4570 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
4571 | ||
21d40d37 | 4572 | if (intel_encoder->load_detect_temp) { |
79e53945 | 4573 | encoder->crtc = NULL; |
c1c43977 | 4574 | connector->encoder = NULL; |
21d40d37 | 4575 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
4576 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
4577 | drm_helper_disable_unused_functions(dev); | |
4578 | } | |
4579 | ||
c751ce4f | 4580 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
4581 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
4582 | if (encoder->crtc == crtc) | |
4583 | encoder_funcs->dpms(encoder, dpms_mode); | |
4584 | crtc_funcs->dpms(crtc, dpms_mode); | |
4585 | } | |
4586 | } | |
4587 | ||
4588 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
4589 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
4590 | { | |
4591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4593 | int pipe = intel_crtc->pipe; | |
4594 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
4595 | u32 fp; | |
4596 | intel_clock_t clock; | |
4597 | ||
4598 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
4599 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
4600 | else | |
4601 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
4602 | ||
4603 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
4604 | if (IS_PINEVIEW(dev)) { |
4605 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
4606 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
4607 | } else { |
4608 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
4609 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
4610 | } | |
4611 | ||
a6c45cf0 | 4612 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
4613 | if (IS_PINEVIEW(dev)) |
4614 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
4615 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
4616 | else |
4617 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
4618 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
4619 | ||
4620 | switch (dpll & DPLL_MODE_MASK) { | |
4621 | case DPLLB_MODE_DAC_SERIAL: | |
4622 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
4623 | 5 : 10; | |
4624 | break; | |
4625 | case DPLLB_MODE_LVDS: | |
4626 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
4627 | 7 : 14; | |
4628 | break; | |
4629 | default: | |
28c97730 | 4630 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
4631 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
4632 | return 0; | |
4633 | } | |
4634 | ||
4635 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 4636 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
4637 | } else { |
4638 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
4639 | ||
4640 | if (is_lvds) { | |
4641 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
4642 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
4643 | clock.p2 = 14; | |
4644 | ||
4645 | if ((dpll & PLL_REF_INPUT_MASK) == | |
4646 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
4647 | /* XXX: might not be 66MHz */ | |
2177832f | 4648 | intel_clock(dev, 66000, &clock); |
79e53945 | 4649 | } else |
2177832f | 4650 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4651 | } else { |
4652 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
4653 | clock.p1 = 2; | |
4654 | else { | |
4655 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
4656 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
4657 | } | |
4658 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
4659 | clock.p2 = 4; | |
4660 | else | |
4661 | clock.p2 = 2; | |
4662 | ||
2177832f | 4663 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4664 | } |
4665 | } | |
4666 | ||
4667 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
4668 | * i830PllIsValid() because it relies on the xf86_config connector | |
4669 | * configuration being accurate, which it isn't necessarily. | |
4670 | */ | |
4671 | ||
4672 | return clock.dot; | |
4673 | } | |
4674 | ||
4675 | /** Returns the currently programmed mode of the given pipe. */ | |
4676 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
4677 | struct drm_crtc *crtc) | |
4678 | { | |
4679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4680 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4681 | int pipe = intel_crtc->pipe; | |
4682 | struct drm_display_mode *mode; | |
4683 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
4684 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
4685 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
4686 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
4687 | ||
4688 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
4689 | if (!mode) | |
4690 | return NULL; | |
4691 | ||
4692 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
4693 | mode->hdisplay = (htot & 0xffff) + 1; | |
4694 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
4695 | mode->hsync_start = (hsync & 0xffff) + 1; | |
4696 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
4697 | mode->vdisplay = (vtot & 0xffff) + 1; | |
4698 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
4699 | mode->vsync_start = (vsync & 0xffff) + 1; | |
4700 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
4701 | ||
4702 | drm_mode_set_name(mode); | |
4703 | drm_mode_set_crtcinfo(mode, 0); | |
4704 | ||
4705 | return mode; | |
4706 | } | |
4707 | ||
652c393a JB |
4708 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
4709 | ||
4710 | /* When this timer fires, we've been idle for awhile */ | |
4711 | static void intel_gpu_idle_timer(unsigned long arg) | |
4712 | { | |
4713 | struct drm_device *dev = (struct drm_device *)arg; | |
4714 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4715 | ||
652c393a JB |
4716 | dev_priv->busy = false; |
4717 | ||
01dfba93 | 4718 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4719 | } |
4720 | ||
652c393a JB |
4721 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
4722 | ||
4723 | static void intel_crtc_idle_timer(unsigned long arg) | |
4724 | { | |
4725 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
4726 | struct drm_crtc *crtc = &intel_crtc->base; | |
4727 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
4728 | ||
652c393a JB |
4729 | intel_crtc->busy = false; |
4730 | ||
01dfba93 | 4731 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4732 | } |
4733 | ||
3dec0095 | 4734 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
4735 | { |
4736 | struct drm_device *dev = crtc->dev; | |
4737 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4739 | int pipe = intel_crtc->pipe; | |
4740 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4741 | int dpll = I915_READ(dpll_reg); | |
4742 | ||
bad720ff | 4743 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4744 | return; |
4745 | ||
4746 | if (!dev_priv->lvds_downclock_avail) | |
4747 | return; | |
4748 | ||
4749 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { | |
44d98a61 | 4750 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
4751 | |
4752 | /* Unlock panel regs */ | |
4a655f04 JB |
4753 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4754 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4755 | |
4756 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
4757 | I915_WRITE(dpll_reg, dpll); | |
4758 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4759 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4760 | dpll = I915_READ(dpll_reg); |
4761 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 4762 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
4763 | |
4764 | /* ...and lock them again */ | |
4765 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4766 | } | |
4767 | ||
4768 | /* Schedule downclock */ | |
3dec0095 DV |
4769 | mod_timer(&intel_crtc->idle_timer, jiffies + |
4770 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
4771 | } |
4772 | ||
4773 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
4774 | { | |
4775 | struct drm_device *dev = crtc->dev; | |
4776 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4778 | int pipe = intel_crtc->pipe; | |
4779 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4780 | int dpll = I915_READ(dpll_reg); | |
4781 | ||
bad720ff | 4782 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4783 | return; |
4784 | ||
4785 | if (!dev_priv->lvds_downclock_avail) | |
4786 | return; | |
4787 | ||
4788 | /* | |
4789 | * Since this is called by a timer, we should never get here in | |
4790 | * the manual case. | |
4791 | */ | |
4792 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 4793 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
4794 | |
4795 | /* Unlock panel regs */ | |
4a655f04 JB |
4796 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4797 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4798 | |
4799 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
4800 | I915_WRITE(dpll_reg, dpll); | |
4801 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4802 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4803 | dpll = I915_READ(dpll_reg); |
4804 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 4805 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
4806 | |
4807 | /* ...and lock them again */ | |
4808 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4809 | } | |
4810 | ||
4811 | } | |
4812 | ||
4813 | /** | |
4814 | * intel_idle_update - adjust clocks for idleness | |
4815 | * @work: work struct | |
4816 | * | |
4817 | * Either the GPU or display (or both) went idle. Check the busy status | |
4818 | * here and adjust the CRTC and GPU clocks as necessary. | |
4819 | */ | |
4820 | static void intel_idle_update(struct work_struct *work) | |
4821 | { | |
4822 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
4823 | idle_work); | |
4824 | struct drm_device *dev = dev_priv->dev; | |
4825 | struct drm_crtc *crtc; | |
4826 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 4827 | int enabled = 0; |
652c393a JB |
4828 | |
4829 | if (!i915_powersave) | |
4830 | return; | |
4831 | ||
4832 | mutex_lock(&dev->struct_mutex); | |
4833 | ||
7648fa99 JB |
4834 | i915_update_gfx_val(dev_priv); |
4835 | ||
652c393a JB |
4836 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4837 | /* Skip inactive CRTCs */ | |
4838 | if (!crtc->fb) | |
4839 | continue; | |
4840 | ||
45ac22c8 | 4841 | enabled++; |
652c393a JB |
4842 | intel_crtc = to_intel_crtc(crtc); |
4843 | if (!intel_crtc->busy) | |
4844 | intel_decrease_pllclock(crtc); | |
4845 | } | |
4846 | ||
45ac22c8 LP |
4847 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
4848 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
4849 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4850 | } | |
4851 | ||
652c393a JB |
4852 | mutex_unlock(&dev->struct_mutex); |
4853 | } | |
4854 | ||
4855 | /** | |
4856 | * intel_mark_busy - mark the GPU and possibly the display busy | |
4857 | * @dev: drm device | |
4858 | * @obj: object we're operating on | |
4859 | * | |
4860 | * Callers can use this function to indicate that the GPU is busy processing | |
4861 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
4862 | * buffer), we'll also mark the display as busy, so we know to increase its | |
4863 | * clock frequency. | |
4864 | */ | |
4865 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) | |
4866 | { | |
4867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4868 | struct drm_crtc *crtc = NULL; | |
4869 | struct intel_framebuffer *intel_fb; | |
4870 | struct intel_crtc *intel_crtc; | |
4871 | ||
5e17ee74 ZW |
4872 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4873 | return; | |
4874 | ||
060e645a LP |
4875 | if (!dev_priv->busy) { |
4876 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
4877 | u32 fw_blc_self; | |
ee980b80 | 4878 | |
060e645a LP |
4879 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
4880 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4881 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4882 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4883 | } | |
28cf798f | 4884 | dev_priv->busy = true; |
060e645a | 4885 | } else |
28cf798f CW |
4886 | mod_timer(&dev_priv->idle_timer, jiffies + |
4887 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
4888 | |
4889 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4890 | if (!crtc->fb) | |
4891 | continue; | |
4892 | ||
4893 | intel_crtc = to_intel_crtc(crtc); | |
4894 | intel_fb = to_intel_framebuffer(crtc->fb); | |
4895 | if (intel_fb->obj == obj) { | |
4896 | if (!intel_crtc->busy) { | |
060e645a LP |
4897 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
4898 | u32 fw_blc_self; | |
4899 | ||
4900 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
4901 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4902 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4903 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4904 | } | |
652c393a | 4905 | /* Non-busy -> busy, upclock */ |
3dec0095 | 4906 | intel_increase_pllclock(crtc); |
652c393a JB |
4907 | intel_crtc->busy = true; |
4908 | } else { | |
4909 | /* Busy -> busy, put off timer */ | |
4910 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
4911 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
4912 | } | |
4913 | } | |
4914 | } | |
4915 | } | |
4916 | ||
79e53945 JB |
4917 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
4918 | { | |
4919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
4920 | struct drm_device *dev = crtc->dev; |
4921 | struct intel_unpin_work *work; | |
4922 | unsigned long flags; | |
4923 | ||
4924 | spin_lock_irqsave(&dev->event_lock, flags); | |
4925 | work = intel_crtc->unpin_work; | |
4926 | intel_crtc->unpin_work = NULL; | |
4927 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4928 | ||
4929 | if (work) { | |
4930 | cancel_work_sync(&work->work); | |
4931 | kfree(work); | |
4932 | } | |
79e53945 JB |
4933 | |
4934 | drm_crtc_cleanup(crtc); | |
67e77c5a | 4935 | |
79e53945 JB |
4936 | kfree(intel_crtc); |
4937 | } | |
4938 | ||
6b95a207 KH |
4939 | static void intel_unpin_work_fn(struct work_struct *__work) |
4940 | { | |
4941 | struct intel_unpin_work *work = | |
4942 | container_of(__work, struct intel_unpin_work, work); | |
4943 | ||
4944 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 4945 | i915_gem_object_unpin(work->old_fb_obj); |
75dfca80 | 4946 | drm_gem_object_unreference(work->pending_flip_obj); |
b1b87f6b | 4947 | drm_gem_object_unreference(work->old_fb_obj); |
6b95a207 KH |
4948 | mutex_unlock(&work->dev->struct_mutex); |
4949 | kfree(work); | |
4950 | } | |
4951 | ||
1afe3e9d JB |
4952 | static void do_intel_finish_page_flip(struct drm_device *dev, |
4953 | struct drm_crtc *crtc) | |
6b95a207 KH |
4954 | { |
4955 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
4956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4957 | struct intel_unpin_work *work; | |
4958 | struct drm_i915_gem_object *obj_priv; | |
4959 | struct drm_pending_vblank_event *e; | |
4960 | struct timeval now; | |
4961 | unsigned long flags; | |
4962 | ||
4963 | /* Ignore early vblank irqs */ | |
4964 | if (intel_crtc == NULL) | |
4965 | return; | |
4966 | ||
4967 | spin_lock_irqsave(&dev->event_lock, flags); | |
4968 | work = intel_crtc->unpin_work; | |
4969 | if (work == NULL || !work->pending) { | |
4970 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4971 | return; | |
4972 | } | |
4973 | ||
4974 | intel_crtc->unpin_work = NULL; | |
4975 | drm_vblank_put(dev, intel_crtc->pipe); | |
4976 | ||
4977 | if (work->event) { | |
4978 | e = work->event; | |
4979 | do_gettimeofday(&now); | |
4980 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); | |
4981 | e->event.tv_sec = now.tv_sec; | |
4982 | e->event.tv_usec = now.tv_usec; | |
4983 | list_add_tail(&e->base.link, | |
4984 | &e->base.file_priv->event_list); | |
4985 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
4986 | } | |
4987 | ||
4988 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4989 | ||
23010e43 | 4990 | obj_priv = to_intel_bo(work->pending_flip_obj); |
de3f440f JB |
4991 | |
4992 | /* Initial scanout buffer will have a 0 pending flip count */ | |
e59f2bac CW |
4993 | atomic_clear_mask(1 << intel_crtc->plane, |
4994 | &obj_priv->pending_flip.counter); | |
4995 | if (atomic_read(&obj_priv->pending_flip) == 0) | |
f787a5f5 | 4996 | wake_up(&dev_priv->pending_flip_queue); |
6b95a207 | 4997 | schedule_work(&work->work); |
e5510fac JB |
4998 | |
4999 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
5000 | } |
5001 | ||
1afe3e9d JB |
5002 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5003 | { | |
5004 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5005 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5006 | ||
5007 | do_intel_finish_page_flip(dev, crtc); | |
5008 | } | |
5009 | ||
5010 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5011 | { | |
5012 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5013 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5014 | ||
5015 | do_intel_finish_page_flip(dev, crtc); | |
5016 | } | |
5017 | ||
6b95a207 KH |
5018 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5019 | { | |
5020 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5021 | struct intel_crtc *intel_crtc = | |
5022 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5023 | unsigned long flags; | |
5024 | ||
5025 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5026 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5027 | if ((++intel_crtc->unpin_work->pending) > 1) |
5028 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5029 | } else { |
5030 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5031 | } | |
6b95a207 KH |
5032 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5033 | } | |
5034 | ||
5035 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5036 | struct drm_framebuffer *fb, | |
5037 | struct drm_pending_vblank_event *event) | |
5038 | { | |
5039 | struct drm_device *dev = crtc->dev; | |
5040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5041 | struct intel_framebuffer *intel_fb; | |
5042 | struct drm_i915_gem_object *obj_priv; | |
5043 | struct drm_gem_object *obj; | |
5044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5045 | struct intel_unpin_work *work; | |
be9a3dbf | 5046 | unsigned long flags, offset; |
52e68630 | 5047 | int pipe = intel_crtc->pipe; |
20f0cd55 | 5048 | u32 pf, pipesrc; |
52e68630 | 5049 | int ret; |
6b95a207 KH |
5050 | |
5051 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5052 | if (work == NULL) | |
5053 | return -ENOMEM; | |
5054 | ||
6b95a207 KH |
5055 | work->event = event; |
5056 | work->dev = crtc->dev; | |
5057 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5058 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5059 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5060 | ||
5061 | /* We borrow the event spin lock for protecting unpin_work */ | |
5062 | spin_lock_irqsave(&dev->event_lock, flags); | |
5063 | if (intel_crtc->unpin_work) { | |
5064 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5065 | kfree(work); | |
468f0b44 CW |
5066 | |
5067 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5068 | return -EBUSY; |
5069 | } | |
5070 | intel_crtc->unpin_work = work; | |
5071 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5072 | ||
5073 | intel_fb = to_intel_framebuffer(fb); | |
5074 | obj = intel_fb->obj; | |
5075 | ||
468f0b44 | 5076 | mutex_lock(&dev->struct_mutex); |
48b956c5 | 5077 | ret = intel_pin_and_fence_fb_obj(dev, obj, true); |
96b099fd CW |
5078 | if (ret) |
5079 | goto cleanup_work; | |
6b95a207 | 5080 | |
75dfca80 | 5081 | /* Reference the objects for the scheduled work. */ |
b1b87f6b | 5082 | drm_gem_object_reference(work->old_fb_obj); |
75dfca80 | 5083 | drm_gem_object_reference(obj); |
6b95a207 KH |
5084 | |
5085 | crtc->fb = fb; | |
96b099fd CW |
5086 | |
5087 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5088 | if (ret) | |
5089 | goto cleanup_objs; | |
5090 | ||
23010e43 | 5091 | obj_priv = to_intel_bo(obj); |
e59f2bac | 5092 | atomic_add(1 << intel_crtc->plane, &obj_priv->pending_flip); |
b1b87f6b | 5093 | work->pending_flip_obj = obj; |
6b95a207 | 5094 | |
c7f9f9a8 CW |
5095 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
5096 | u32 flip_mask; | |
48b956c5 | 5097 | |
c7f9f9a8 CW |
5098 | /* Can't queue multiple flips, so wait for the previous |
5099 | * one to finish before executing the next. | |
5100 | */ | |
5101 | BEGIN_LP_RING(2); | |
5102 | if (intel_crtc->plane) | |
5103 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5104 | else | |
5105 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5106 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5107 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
5108 | ADVANCE_LP_RING(); |
5109 | } | |
83f7fd05 | 5110 | |
4e5359cd SF |
5111 | work->enable_stall_check = true; |
5112 | ||
be9a3dbf | 5113 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5114 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5115 | |
6b95a207 | 5116 | BEGIN_LP_RING(4); |
52e68630 CW |
5117 | switch(INTEL_INFO(dev)->gen) { |
5118 | case 2: | |
1afe3e9d JB |
5119 | OUT_RING(MI_DISPLAY_FLIP | |
5120 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5121 | OUT_RING(fb->pitch); | |
52e68630 CW |
5122 | OUT_RING(obj_priv->gtt_offset + offset); |
5123 | OUT_RING(MI_NOOP); | |
5124 | break; | |
5125 | ||
5126 | case 3: | |
1afe3e9d JB |
5127 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5128 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5129 | OUT_RING(fb->pitch); | |
52e68630 | 5130 | OUT_RING(obj_priv->gtt_offset + offset); |
22fd0fab | 5131 | OUT_RING(MI_NOOP); |
52e68630 CW |
5132 | break; |
5133 | ||
5134 | case 4: | |
5135 | case 5: | |
5136 | /* i965+ uses the linear or tiled offsets from the | |
5137 | * Display Registers (which do not change across a page-flip) | |
5138 | * so we need only reprogram the base address. | |
5139 | */ | |
69d0b96c DV |
5140 | OUT_RING(MI_DISPLAY_FLIP | |
5141 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5142 | OUT_RING(fb->pitch); | |
52e68630 CW |
5143 | OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); |
5144 | ||
5145 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5146 | * untested on non-native modes, so ignore it for now. | |
5147 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5148 | */ | |
5149 | pf = 0; | |
5150 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5151 | OUT_RING(pf | pipesrc); | |
5152 | break; | |
5153 | ||
5154 | case 6: | |
5155 | OUT_RING(MI_DISPLAY_FLIP | | |
5156 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5157 | OUT_RING(fb->pitch | obj_priv->tiling_mode); | |
5158 | OUT_RING(obj_priv->gtt_offset); | |
5159 | ||
5160 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5161 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5162 | OUT_RING(pf | pipesrc); | |
5163 | break; | |
22fd0fab | 5164 | } |
6b95a207 KH |
5165 | ADVANCE_LP_RING(); |
5166 | ||
5167 | mutex_unlock(&dev->struct_mutex); | |
5168 | ||
e5510fac JB |
5169 | trace_i915_flip_request(intel_crtc->plane, obj); |
5170 | ||
6b95a207 | 5171 | return 0; |
96b099fd CW |
5172 | |
5173 | cleanup_objs: | |
5174 | drm_gem_object_unreference(work->old_fb_obj); | |
5175 | drm_gem_object_unreference(obj); | |
5176 | cleanup_work: | |
5177 | mutex_unlock(&dev->struct_mutex); | |
5178 | ||
5179 | spin_lock_irqsave(&dev->event_lock, flags); | |
5180 | intel_crtc->unpin_work = NULL; | |
5181 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5182 | ||
5183 | kfree(work); | |
5184 | ||
5185 | return ret; | |
6b95a207 KH |
5186 | } |
5187 | ||
7e7d76c3 | 5188 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
79e53945 JB |
5189 | .dpms = intel_crtc_dpms, |
5190 | .mode_fixup = intel_crtc_mode_fixup, | |
5191 | .mode_set = intel_crtc_mode_set, | |
5192 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5193 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
068143d3 | 5194 | .load_lut = intel_crtc_load_lut, |
cdd59983 | 5195 | .disable = intel_crtc_disable, |
79e53945 JB |
5196 | }; |
5197 | ||
5198 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5199 | .cursor_set = intel_crtc_cursor_set, | |
5200 | .cursor_move = intel_crtc_cursor_move, | |
5201 | .gamma_set = intel_crtc_gamma_set, | |
5202 | .set_config = drm_crtc_helper_set_config, | |
5203 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5204 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5205 | }; |
5206 | ||
5207 | ||
b358d0a6 | 5208 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5209 | { |
22fd0fab | 5210 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5211 | struct intel_crtc *intel_crtc; |
5212 | int i; | |
5213 | ||
5214 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5215 | if (intel_crtc == NULL) | |
5216 | return; | |
5217 | ||
5218 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5219 | ||
5220 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
5221 | for (i = 0; i < 256; i++) { |
5222 | intel_crtc->lut_r[i] = i; | |
5223 | intel_crtc->lut_g[i] = i; | |
5224 | intel_crtc->lut_b[i] = i; | |
5225 | } | |
5226 | ||
80824003 JB |
5227 | /* Swap pipes & planes for FBC on pre-965 */ |
5228 | intel_crtc->pipe = pipe; | |
5229 | intel_crtc->plane = pipe; | |
e2e767ab | 5230 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 5231 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 5232 | intel_crtc->plane = !pipe; |
80824003 JB |
5233 | } |
5234 | ||
22fd0fab JB |
5235 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5236 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5237 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5238 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5239 | ||
79e53945 | 5240 | intel_crtc->cursor_addr = 0; |
032d2a0d | 5241 | intel_crtc->dpms_mode = -1; |
e65d9305 | 5242 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
5243 | |
5244 | if (HAS_PCH_SPLIT(dev)) { | |
5245 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
5246 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
5247 | } else { | |
5248 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
5249 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
5250 | } | |
5251 | ||
79e53945 JB |
5252 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5253 | ||
652c393a JB |
5254 | intel_crtc->busy = false; |
5255 | ||
5256 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5257 | (unsigned long)intel_crtc); | |
79e53945 JB |
5258 | } |
5259 | ||
08d7b3d1 CW |
5260 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
5261 | struct drm_file *file_priv) | |
5262 | { | |
5263 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5264 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5265 | struct drm_mode_object *drmmode_obj; |
5266 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5267 | |
5268 | if (!dev_priv) { | |
5269 | DRM_ERROR("called with no initialization\n"); | |
5270 | return -EINVAL; | |
5271 | } | |
5272 | ||
c05422d5 DV |
5273 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5274 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5275 | |
c05422d5 | 5276 | if (!drmmode_obj) { |
08d7b3d1 CW |
5277 | DRM_ERROR("no such CRTC id\n"); |
5278 | return -EINVAL; | |
5279 | } | |
5280 | ||
c05422d5 DV |
5281 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5282 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5283 | |
c05422d5 | 5284 | return 0; |
08d7b3d1 CW |
5285 | } |
5286 | ||
c5e4df33 | 5287 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5288 | { |
4ef69c7a | 5289 | struct intel_encoder *encoder; |
79e53945 | 5290 | int index_mask = 0; |
79e53945 JB |
5291 | int entry = 0; |
5292 | ||
4ef69c7a CW |
5293 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5294 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5295 | index_mask |= (1 << entry); |
5296 | entry++; | |
5297 | } | |
4ef69c7a | 5298 | |
79e53945 JB |
5299 | return index_mask; |
5300 | } | |
5301 | ||
79e53945 JB |
5302 | static void intel_setup_outputs(struct drm_device *dev) |
5303 | { | |
725e30ad | 5304 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5305 | struct intel_encoder *encoder; |
cb0953d7 | 5306 | bool dpd_is_edp = false; |
79e53945 | 5307 | |
541998a1 | 5308 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
79e53945 JB |
5309 | intel_lvds_init(dev); |
5310 | ||
bad720ff | 5311 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5312 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5313 | |
32f9d658 ZW |
5314 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
5315 | intel_dp_init(dev, DP_A); | |
5316 | ||
cb0953d7 AJ |
5317 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5318 | intel_dp_init(dev, PCH_DP_D); | |
5319 | } | |
5320 | ||
5321 | intel_crt_init(dev); | |
5322 | ||
5323 | if (HAS_PCH_SPLIT(dev)) { | |
5324 | int found; | |
5325 | ||
30ad48b7 | 5326 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5327 | /* PCH SDVOB multiplex with HDMIB */ |
5328 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5329 | if (!found) |
5330 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5331 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5332 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5333 | } |
5334 | ||
5335 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5336 | intel_hdmi_init(dev, HDMIC); | |
5337 | ||
5338 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5339 | intel_hdmi_init(dev, HDMID); | |
5340 | ||
5eb08b69 ZW |
5341 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5342 | intel_dp_init(dev, PCH_DP_C); | |
5343 | ||
cb0953d7 | 5344 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5345 | intel_dp_init(dev, PCH_DP_D); |
5346 | ||
103a196f | 5347 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5348 | bool found = false; |
7d57382e | 5349 | |
725e30ad | 5350 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5351 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5352 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5353 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5354 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5355 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5356 | } |
27185ae1 | 5357 | |
b01f2c3a JB |
5358 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5359 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5360 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5361 | } |
725e30ad | 5362 | } |
13520b05 KH |
5363 | |
5364 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5365 | |
b01f2c3a JB |
5366 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5367 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5368 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5369 | } |
27185ae1 ML |
5370 | |
5371 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5372 | ||
b01f2c3a JB |
5373 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5374 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5375 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5376 | } |
5377 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5378 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5379 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5380 | } |
725e30ad | 5381 | } |
27185ae1 | 5382 | |
b01f2c3a JB |
5383 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5384 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5385 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5386 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5387 | } |
bad720ff | 5388 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5389 | intel_dvo_init(dev); |
5390 | ||
103a196f | 5391 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5392 | intel_tv_init(dev); |
5393 | ||
4ef69c7a CW |
5394 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5395 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5396 | encoder->base.possible_clones = | |
5397 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 JB |
5398 | } |
5399 | } | |
5400 | ||
5401 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5402 | { | |
5403 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5404 | |
5405 | drm_framebuffer_cleanup(fb); | |
bc9025bd | 5406 | drm_gem_object_unreference_unlocked(intel_fb->obj); |
79e53945 JB |
5407 | |
5408 | kfree(intel_fb); | |
5409 | } | |
5410 | ||
5411 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
5412 | struct drm_file *file_priv, | |
5413 | unsigned int *handle) | |
5414 | { | |
5415 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
5416 | struct drm_gem_object *object = intel_fb->obj; | |
5417 | ||
5418 | return drm_gem_handle_create(file_priv, object, handle); | |
5419 | } | |
5420 | ||
5421 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5422 | .destroy = intel_user_framebuffer_destroy, | |
5423 | .create_handle = intel_user_framebuffer_create_handle, | |
5424 | }; | |
5425 | ||
38651674 DA |
5426 | int intel_framebuffer_init(struct drm_device *dev, |
5427 | struct intel_framebuffer *intel_fb, | |
5428 | struct drm_mode_fb_cmd *mode_cmd, | |
5429 | struct drm_gem_object *obj) | |
79e53945 | 5430 | { |
57cd6508 | 5431 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
79e53945 JB |
5432 | int ret; |
5433 | ||
57cd6508 CW |
5434 | if (obj_priv->tiling_mode == I915_TILING_Y) |
5435 | return -EINVAL; | |
5436 | ||
5437 | if (mode_cmd->pitch & 63) | |
5438 | return -EINVAL; | |
5439 | ||
5440 | switch (mode_cmd->bpp) { | |
5441 | case 8: | |
5442 | case 16: | |
5443 | case 24: | |
5444 | case 32: | |
5445 | break; | |
5446 | default: | |
5447 | return -EINVAL; | |
5448 | } | |
5449 | ||
79e53945 JB |
5450 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5451 | if (ret) { | |
5452 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5453 | return ret; | |
5454 | } | |
5455 | ||
5456 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5457 | intel_fb->obj = obj; |
79e53945 JB |
5458 | return 0; |
5459 | } | |
5460 | ||
79e53945 JB |
5461 | static struct drm_framebuffer * |
5462 | intel_user_framebuffer_create(struct drm_device *dev, | |
5463 | struct drm_file *filp, | |
5464 | struct drm_mode_fb_cmd *mode_cmd) | |
5465 | { | |
5466 | struct drm_gem_object *obj; | |
38651674 | 5467 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
5468 | int ret; |
5469 | ||
5470 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
5471 | if (!obj) | |
cce13ff7 | 5472 | return ERR_PTR(-ENOENT); |
79e53945 | 5473 | |
38651674 DA |
5474 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5475 | if (!intel_fb) | |
cce13ff7 | 5476 | return ERR_PTR(-ENOMEM); |
38651674 DA |
5477 | |
5478 | ret = intel_framebuffer_init(dev, intel_fb, | |
5479 | mode_cmd, obj); | |
79e53945 | 5480 | if (ret) { |
bc9025bd | 5481 | drm_gem_object_unreference_unlocked(obj); |
38651674 | 5482 | kfree(intel_fb); |
cce13ff7 | 5483 | return ERR_PTR(ret); |
79e53945 JB |
5484 | } |
5485 | ||
38651674 | 5486 | return &intel_fb->base; |
79e53945 JB |
5487 | } |
5488 | ||
79e53945 | 5489 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 5490 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 5491 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
5492 | }; |
5493 | ||
9ea8d059 | 5494 | static struct drm_gem_object * |
aa40d6bb | 5495 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 5496 | { |
aa40d6bb | 5497 | struct drm_gem_object *ctx; |
9ea8d059 CW |
5498 | int ret; |
5499 | ||
aa40d6bb ZN |
5500 | ctx = i915_gem_alloc_object(dev, 4096); |
5501 | if (!ctx) { | |
9ea8d059 CW |
5502 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
5503 | return NULL; | |
5504 | } | |
5505 | ||
5506 | mutex_lock(&dev->struct_mutex); | |
aa40d6bb | 5507 | ret = i915_gem_object_pin(ctx, 4096); |
9ea8d059 CW |
5508 | if (ret) { |
5509 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
5510 | goto err_unref; | |
5511 | } | |
5512 | ||
aa40d6bb | 5513 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
5514 | if (ret) { |
5515 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
5516 | goto err_unpin; | |
5517 | } | |
5518 | mutex_unlock(&dev->struct_mutex); | |
5519 | ||
aa40d6bb | 5520 | return ctx; |
9ea8d059 CW |
5521 | |
5522 | err_unpin: | |
aa40d6bb | 5523 | i915_gem_object_unpin(ctx); |
9ea8d059 | 5524 | err_unref: |
aa40d6bb | 5525 | drm_gem_object_unreference(ctx); |
9ea8d059 CW |
5526 | mutex_unlock(&dev->struct_mutex); |
5527 | return NULL; | |
5528 | } | |
5529 | ||
7648fa99 JB |
5530 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
5531 | { | |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5533 | u16 rgvswctl; | |
5534 | ||
5535 | rgvswctl = I915_READ16(MEMSWCTL); | |
5536 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5537 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5538 | return false; /* still busy with another command */ | |
5539 | } | |
5540 | ||
5541 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5542 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5543 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5544 | POSTING_READ16(MEMSWCTL); | |
5545 | ||
5546 | rgvswctl |= MEMCTL_CMD_STS; | |
5547 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5548 | ||
5549 | return true; | |
5550 | } | |
5551 | ||
f97108d1 JB |
5552 | void ironlake_enable_drps(struct drm_device *dev) |
5553 | { | |
5554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5555 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 5556 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 5557 | |
ea056c14 JB |
5558 | /* Enable temp reporting */ |
5559 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5560 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5561 | ||
f97108d1 JB |
5562 | /* 100ms RC evaluation intervals */ |
5563 | I915_WRITE(RCUPEI, 100000); | |
5564 | I915_WRITE(RCDNEI, 100000); | |
5565 | ||
5566 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5567 | I915_WRITE(RCBMAXAVG, 90000); | |
5568 | I915_WRITE(RCBMINAVG, 80000); | |
5569 | ||
5570 | I915_WRITE(MEMIHYST, 1); | |
5571 | ||
5572 | /* Set up min, max, and cur for interrupt handling */ | |
5573 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5574 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5575 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5576 | MEMMODE_FSTART_SHIFT; | |
7648fa99 JB |
5577 | fstart = fmax; |
5578 | ||
f97108d1 JB |
5579 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
5580 | PXVFREQ_PX_SHIFT; | |
5581 | ||
7648fa99 JB |
5582 | dev_priv->fmax = fstart; /* IPS callback will increase this */ |
5583 | dev_priv->fstart = fstart; | |
5584 | ||
5585 | dev_priv->max_delay = fmax; | |
f97108d1 JB |
5586 | dev_priv->min_delay = fmin; |
5587 | dev_priv->cur_delay = fstart; | |
5588 | ||
7648fa99 JB |
5589 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, |
5590 | fstart); | |
5591 | ||
f97108d1 JB |
5592 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
5593 | ||
5594 | /* | |
5595 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5596 | */ | |
5597 | ||
5598 | I915_WRITE(VIDSTART, vstart); | |
5599 | POSTING_READ(VIDSTART); | |
5600 | ||
5601 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5602 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5603 | ||
481b6af3 | 5604 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 5605 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
5606 | msleep(1); |
5607 | ||
7648fa99 | 5608 | ironlake_set_drps(dev, fstart); |
f97108d1 | 5609 | |
7648fa99 JB |
5610 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
5611 | I915_READ(0x112e0); | |
5612 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
5613 | dev_priv->last_count2 = I915_READ(0x112f4); | |
5614 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
5615 | } |
5616 | ||
5617 | void ironlake_disable_drps(struct drm_device *dev) | |
5618 | { | |
5619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5620 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
5621 | |
5622 | /* Ack interrupts, disable EFC interrupt */ | |
5623 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5624 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5625 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5626 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5627 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5628 | ||
5629 | /* Go back to the starting frequency */ | |
7648fa99 | 5630 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
5631 | msleep(1); |
5632 | rgvswctl |= MEMCTL_CMD_STS; | |
5633 | I915_WRITE(MEMSWCTL, rgvswctl); | |
5634 | msleep(1); | |
5635 | ||
5636 | } | |
5637 | ||
7648fa99 JB |
5638 | static unsigned long intel_pxfreq(u32 vidfreq) |
5639 | { | |
5640 | unsigned long freq; | |
5641 | int div = (vidfreq & 0x3f0000) >> 16; | |
5642 | int post = (vidfreq & 0x3000) >> 12; | |
5643 | int pre = (vidfreq & 0x7); | |
5644 | ||
5645 | if (!pre) | |
5646 | return 0; | |
5647 | ||
5648 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5649 | ||
5650 | return freq; | |
5651 | } | |
5652 | ||
5653 | void intel_init_emon(struct drm_device *dev) | |
5654 | { | |
5655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5656 | u32 lcfuse; | |
5657 | u8 pxw[16]; | |
5658 | int i; | |
5659 | ||
5660 | /* Disable to program */ | |
5661 | I915_WRITE(ECR, 0); | |
5662 | POSTING_READ(ECR); | |
5663 | ||
5664 | /* Program energy weights for various events */ | |
5665 | I915_WRITE(SDEW, 0x15040d00); | |
5666 | I915_WRITE(CSIEW0, 0x007f0000); | |
5667 | I915_WRITE(CSIEW1, 0x1e220004); | |
5668 | I915_WRITE(CSIEW2, 0x04000004); | |
5669 | ||
5670 | for (i = 0; i < 5; i++) | |
5671 | I915_WRITE(PEW + (i * 4), 0); | |
5672 | for (i = 0; i < 3; i++) | |
5673 | I915_WRITE(DEW + (i * 4), 0); | |
5674 | ||
5675 | /* Program P-state weights to account for frequency power adjustment */ | |
5676 | for (i = 0; i < 16; i++) { | |
5677 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5678 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5679 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5680 | PXVFREQ_PX_SHIFT; | |
5681 | unsigned long val; | |
5682 | ||
5683 | val = vid * vid; | |
5684 | val *= (freq / 1000); | |
5685 | val *= 255; | |
5686 | val /= (127*127*900); | |
5687 | if (val > 0xff) | |
5688 | DRM_ERROR("bad pxval: %ld\n", val); | |
5689 | pxw[i] = val; | |
5690 | } | |
5691 | /* Render standby states get 0 weight */ | |
5692 | pxw[14] = 0; | |
5693 | pxw[15] = 0; | |
5694 | ||
5695 | for (i = 0; i < 4; i++) { | |
5696 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5697 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5698 | I915_WRITE(PXW + (i * 4), val); | |
5699 | } | |
5700 | ||
5701 | /* Adjust magic regs to magic values (more experimental results) */ | |
5702 | I915_WRITE(OGW0, 0); | |
5703 | I915_WRITE(OGW1, 0); | |
5704 | I915_WRITE(EG0, 0x00007f00); | |
5705 | I915_WRITE(EG1, 0x0000000e); | |
5706 | I915_WRITE(EG2, 0x000e0000); | |
5707 | I915_WRITE(EG3, 0x68000300); | |
5708 | I915_WRITE(EG4, 0x42000000); | |
5709 | I915_WRITE(EG5, 0x00140031); | |
5710 | I915_WRITE(EG6, 0); | |
5711 | I915_WRITE(EG7, 0); | |
5712 | ||
5713 | for (i = 0; i < 8; i++) | |
5714 | I915_WRITE(PXWL + (i * 4), 0); | |
5715 | ||
5716 | /* Enable PMON + select events */ | |
5717 | I915_WRITE(ECR, 0x80000019); | |
5718 | ||
5719 | lcfuse = I915_READ(LCFUSE02); | |
5720 | ||
5721 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
5722 | } | |
5723 | ||
652c393a JB |
5724 | void intel_init_clock_gating(struct drm_device *dev) |
5725 | { | |
5726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5727 | ||
5728 | /* | |
5729 | * Disable clock gating reported to work incorrectly according to the | |
5730 | * specs, but enable as much else as we can. | |
5731 | */ | |
bad720ff | 5732 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
5733 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
5734 | ||
5735 | if (IS_IRONLAKE(dev)) { | |
5736 | /* Required for FBC */ | |
5737 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | |
5738 | /* Required for CxSR */ | |
5739 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
5740 | ||
5741 | I915_WRITE(PCH_3DCGDIS0, | |
5742 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5743 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5744 | } | |
5745 | ||
5746 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 ZW |
5747 | |
5748 | /* | |
5749 | * According to the spec the following bits should be set in | |
5750 | * order to enable memory self-refresh | |
5751 | * The bit 22/21 of 0x42004 | |
5752 | * The bit 5 of 0x42020 | |
5753 | * The bit 15 of 0x45000 | |
5754 | */ | |
5755 | if (IS_IRONLAKE(dev)) { | |
5756 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5757 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5758 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
5759 | I915_WRITE(ILK_DSPCLK_GATE, | |
5760 | (I915_READ(ILK_DSPCLK_GATE) | | |
5761 | ILK_DPARB_CLK_GATE)); | |
5762 | I915_WRITE(DISP_ARB_CTL, | |
5763 | (I915_READ(DISP_ARB_CTL) | | |
5764 | DISP_FBC_WM_DIS)); | |
dd8849c8 JB |
5765 | I915_WRITE(WM3_LP_ILK, 0); |
5766 | I915_WRITE(WM2_LP_ILK, 0); | |
5767 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 5768 | } |
b52eb4dc ZY |
5769 | /* |
5770 | * Based on the document from hardware guys the following bits | |
5771 | * should be set unconditionally in order to enable FBC. | |
5772 | * The bit 22 of 0x42000 | |
5773 | * The bit 22 of 0x42004 | |
5774 | * The bit 7,8,9 of 0x42020. | |
5775 | */ | |
5776 | if (IS_IRONLAKE_M(dev)) { | |
5777 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5778 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5779 | ILK_FBCQ_DIS); | |
5780 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5781 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5782 | ILK_DPARB_GATE); | |
5783 | I915_WRITE(ILK_DSPCLK_GATE, | |
5784 | I915_READ(ILK_DSPCLK_GATE) | | |
5785 | ILK_DPFC_DIS1 | | |
5786 | ILK_DPFC_DIS2 | | |
5787 | ILK_CLK_FBC); | |
5788 | } | |
bc41606a | 5789 | return; |
c03342fa | 5790 | } else if (IS_G4X(dev)) { |
652c393a JB |
5791 | uint32_t dspclk_gate; |
5792 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5793 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5794 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5795 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5796 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5797 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5798 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5799 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5800 | if (IS_GM45(dev)) | |
5801 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5802 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 5803 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
5804 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
5805 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5806 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5807 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5808 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 5809 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
5810 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
5811 | I965_RCC_CLOCK_GATE_DISABLE | | |
5812 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5813 | I965_ISC_CLOCK_GATE_DISABLE | | |
5814 | I965_FBC_CLOCK_GATE_DISABLE); | |
5815 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 5816 | } else if (IS_GEN3(dev)) { |
652c393a JB |
5817 | u32 dstate = I915_READ(D_STATE); |
5818 | ||
5819 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5820 | DSTATE_DOT_CLOCK_GATING; | |
5821 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 5822 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
5823 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
5824 | } else if (IS_I830(dev)) { | |
5825 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5826 | } | |
97f5ab66 JB |
5827 | |
5828 | /* | |
5829 | * GPU can automatically power down the render unit if given a page | |
5830 | * to save state. | |
5831 | */ | |
aa40d6bb ZN |
5832 | if (IS_IRONLAKE_M(dev)) { |
5833 | if (dev_priv->renderctx == NULL) | |
5834 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
5835 | if (dev_priv->renderctx) { | |
5836 | struct drm_i915_gem_object *obj_priv; | |
5837 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
5838 | if (obj_priv) { | |
5839 | BEGIN_LP_RING(4); | |
5840 | OUT_RING(MI_SET_CONTEXT); | |
5841 | OUT_RING(obj_priv->gtt_offset | | |
5842 | MI_MM_SPACE_GTT | | |
5843 | MI_SAVE_EXT_STATE_EN | | |
5844 | MI_RESTORE_EXT_STATE_EN | | |
5845 | MI_RESTORE_INHIBIT); | |
5846 | OUT_RING(MI_NOOP); | |
5847 | OUT_RING(MI_FLUSH); | |
5848 | ADVANCE_LP_RING(); | |
5849 | } | |
bc41606a | 5850 | } else |
aa40d6bb | 5851 | DRM_DEBUG_KMS("Failed to allocate render context." |
bc41606a | 5852 | "Disable RC6\n"); |
aa40d6bb ZN |
5853 | } |
5854 | ||
1d3c36ad | 5855 | if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { |
9ea8d059 | 5856 | struct drm_i915_gem_object *obj_priv = NULL; |
97f5ab66 | 5857 | |
7e8b60fa | 5858 | if (dev_priv->pwrctx) { |
23010e43 | 5859 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
7e8b60fa | 5860 | } else { |
9ea8d059 | 5861 | struct drm_gem_object *pwrctx; |
97f5ab66 | 5862 | |
aa40d6bb | 5863 | pwrctx = intel_alloc_context_page(dev); |
9ea8d059 CW |
5864 | if (pwrctx) { |
5865 | dev_priv->pwrctx = pwrctx; | |
23010e43 | 5866 | obj_priv = to_intel_bo(pwrctx); |
7e8b60fa | 5867 | } |
7e8b60fa | 5868 | } |
97f5ab66 | 5869 | |
9ea8d059 CW |
5870 | if (obj_priv) { |
5871 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); | |
5872 | I915_WRITE(MCHBAR_RENDER_STANDBY, | |
5873 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); | |
5874 | } | |
97f5ab66 | 5875 | } |
652c393a JB |
5876 | } |
5877 | ||
e70236a8 JB |
5878 | /* Set up chip specific display functions */ |
5879 | static void intel_init_display(struct drm_device *dev) | |
5880 | { | |
5881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5882 | ||
5883 | /* We always want a DPMS function */ | |
bad720ff | 5884 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 5885 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
5886 | else |
5887 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
5888 | ||
ee5382ae | 5889 | if (I915_HAS_FBC(dev)) { |
b52eb4dc ZY |
5890 | if (IS_IRONLAKE_M(dev)) { |
5891 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
5892 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
5893 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
5894 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
5895 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
5896 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
5897 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 5898 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
5899 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
5900 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
5901 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
5902 | } | |
74dff282 | 5903 | /* 855GM needs testing */ |
e70236a8 JB |
5904 | } |
5905 | ||
5906 | /* Returns the core display clock speed */ | |
f2b115e6 | 5907 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
5908 | dev_priv->display.get_display_clock_speed = |
5909 | i945_get_display_clock_speed; | |
5910 | else if (IS_I915G(dev)) | |
5911 | dev_priv->display.get_display_clock_speed = | |
5912 | i915_get_display_clock_speed; | |
f2b115e6 | 5913 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
5914 | dev_priv->display.get_display_clock_speed = |
5915 | i9xx_misc_get_display_clock_speed; | |
5916 | else if (IS_I915GM(dev)) | |
5917 | dev_priv->display.get_display_clock_speed = | |
5918 | i915gm_get_display_clock_speed; | |
5919 | else if (IS_I865G(dev)) | |
5920 | dev_priv->display.get_display_clock_speed = | |
5921 | i865_get_display_clock_speed; | |
f0f8a9ce | 5922 | else if (IS_I85X(dev)) |
e70236a8 JB |
5923 | dev_priv->display.get_display_clock_speed = |
5924 | i855_get_display_clock_speed; | |
5925 | else /* 852, 830 */ | |
5926 | dev_priv->display.get_display_clock_speed = | |
5927 | i830_get_display_clock_speed; | |
5928 | ||
5929 | /* For FIFO watermark updates */ | |
7f8a8569 ZW |
5930 | if (HAS_PCH_SPLIT(dev)) { |
5931 | if (IS_IRONLAKE(dev)) { | |
5932 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) | |
5933 | dev_priv->display.update_wm = ironlake_update_wm; | |
5934 | else { | |
5935 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
5936 | "Disable CxSR\n"); | |
5937 | dev_priv->display.update_wm = NULL; | |
5938 | } | |
5939 | } else | |
5940 | dev_priv->display.update_wm = NULL; | |
5941 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 5942 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 5943 | dev_priv->is_ddr3, |
d4294342 ZY |
5944 | dev_priv->fsb_freq, |
5945 | dev_priv->mem_freq)) { | |
5946 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 5947 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 5948 | "disabling CxSR\n", |
95534263 | 5949 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
5950 | dev_priv->fsb_freq, dev_priv->mem_freq); |
5951 | /* Disable CxSR and never update its watermark again */ | |
5952 | pineview_disable_cxsr(dev); | |
5953 | dev_priv->display.update_wm = NULL; | |
5954 | } else | |
5955 | dev_priv->display.update_wm = pineview_update_wm; | |
5956 | } else if (IS_G4X(dev)) | |
e70236a8 | 5957 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 5958 | else if (IS_GEN4(dev)) |
e70236a8 | 5959 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 5960 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
5961 | dev_priv->display.update_wm = i9xx_update_wm; |
5962 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
5963 | } else if (IS_I85X(dev)) { |
5964 | dev_priv->display.update_wm = i9xx_update_wm; | |
5965 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 5966 | } else { |
8f4695ed AJ |
5967 | dev_priv->display.update_wm = i830_update_wm; |
5968 | if (IS_845G(dev)) | |
e70236a8 JB |
5969 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
5970 | else | |
5971 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
5972 | } |
5973 | } | |
5974 | ||
b690e96c JB |
5975 | /* |
5976 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
5977 | * resume, or other times. This quirk makes sure that's the case for | |
5978 | * affected systems. | |
5979 | */ | |
5980 | static void quirk_pipea_force (struct drm_device *dev) | |
5981 | { | |
5982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5983 | ||
5984 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
5985 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
5986 | } | |
5987 | ||
5988 | struct intel_quirk { | |
5989 | int device; | |
5990 | int subsystem_vendor; | |
5991 | int subsystem_device; | |
5992 | void (*hook)(struct drm_device *dev); | |
5993 | }; | |
5994 | ||
5995 | struct intel_quirk intel_quirks[] = { | |
5996 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
5997 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
5998 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
5999 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
6000 | ||
6001 | /* Thinkpad R31 needs pipe A force quirk */ | |
6002 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
6003 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
6004 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
6005 | ||
6006 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
6007 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
6008 | /* ThinkPad X40 needs pipe A force quirk */ | |
6009 | ||
6010 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
6011 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
6012 | ||
6013 | /* 855 & before need to leave pipe A & dpll A up */ | |
6014 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6015 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6016 | }; | |
6017 | ||
6018 | static void intel_init_quirks(struct drm_device *dev) | |
6019 | { | |
6020 | struct pci_dev *d = dev->pdev; | |
6021 | int i; | |
6022 | ||
6023 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6024 | struct intel_quirk *q = &intel_quirks[i]; | |
6025 | ||
6026 | if (d->device == q->device && | |
6027 | (d->subsystem_vendor == q->subsystem_vendor || | |
6028 | q->subsystem_vendor == PCI_ANY_ID) && | |
6029 | (d->subsystem_device == q->subsystem_device || | |
6030 | q->subsystem_device == PCI_ANY_ID)) | |
6031 | q->hook(dev); | |
6032 | } | |
6033 | } | |
6034 | ||
9cce37f4 JB |
6035 | /* Disable the VGA plane that we never use */ |
6036 | static void i915_disable_vga(struct drm_device *dev) | |
6037 | { | |
6038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6039 | u8 sr1; | |
6040 | u32 vga_reg; | |
6041 | ||
6042 | if (HAS_PCH_SPLIT(dev)) | |
6043 | vga_reg = CPU_VGACNTRL; | |
6044 | else | |
6045 | vga_reg = VGACNTRL; | |
6046 | ||
6047 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6048 | outb(1, VGA_SR_INDEX); | |
6049 | sr1 = inb(VGA_SR_DATA); | |
6050 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6051 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6052 | udelay(300); | |
6053 | ||
6054 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6055 | POSTING_READ(vga_reg); | |
6056 | } | |
6057 | ||
79e53945 JB |
6058 | void intel_modeset_init(struct drm_device *dev) |
6059 | { | |
652c393a | 6060 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6061 | int i; |
6062 | ||
6063 | drm_mode_config_init(dev); | |
6064 | ||
6065 | dev->mode_config.min_width = 0; | |
6066 | dev->mode_config.min_height = 0; | |
6067 | ||
6068 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6069 | ||
b690e96c JB |
6070 | intel_init_quirks(dev); |
6071 | ||
e70236a8 JB |
6072 | intel_init_display(dev); |
6073 | ||
a6c45cf0 CW |
6074 | if (IS_GEN2(dev)) { |
6075 | dev->mode_config.max_width = 2048; | |
6076 | dev->mode_config.max_height = 2048; | |
6077 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6078 | dev->mode_config.max_width = 4096; |
6079 | dev->mode_config.max_height = 4096; | |
79e53945 | 6080 | } else { |
a6c45cf0 CW |
6081 | dev->mode_config.max_width = 8192; |
6082 | dev->mode_config.max_height = 8192; | |
79e53945 JB |
6083 | } |
6084 | ||
6085 | /* set memory base */ | |
a6c45cf0 | 6086 | if (IS_GEN2(dev)) |
79e53945 | 6087 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
a6c45cf0 CW |
6088 | else |
6089 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
79e53945 | 6090 | |
a6c45cf0 | 6091 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
a3524f1b | 6092 | dev_priv->num_pipe = 2; |
79e53945 | 6093 | else |
a3524f1b | 6094 | dev_priv->num_pipe = 1; |
28c97730 | 6095 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6096 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6097 | |
a3524f1b | 6098 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6099 | intel_crtc_init(dev, i); |
6100 | } | |
6101 | ||
6102 | intel_setup_outputs(dev); | |
652c393a JB |
6103 | |
6104 | intel_init_clock_gating(dev); | |
6105 | ||
9cce37f4 JB |
6106 | /* Just disable it once at startup */ |
6107 | i915_disable_vga(dev); | |
6108 | ||
7648fa99 | 6109 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6110 | ironlake_enable_drps(dev); |
7648fa99 JB |
6111 | intel_init_emon(dev); |
6112 | } | |
f97108d1 | 6113 | |
652c393a JB |
6114 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6115 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6116 | (unsigned long)dev); | |
02e792fb DV |
6117 | |
6118 | intel_setup_overlay(dev); | |
79e53945 JB |
6119 | } |
6120 | ||
6121 | void intel_modeset_cleanup(struct drm_device *dev) | |
6122 | { | |
652c393a JB |
6123 | struct drm_i915_private *dev_priv = dev->dev_private; |
6124 | struct drm_crtc *crtc; | |
6125 | struct intel_crtc *intel_crtc; | |
6126 | ||
f87ea761 | 6127 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
6128 | mutex_lock(&dev->struct_mutex); |
6129 | ||
723bfd70 JB |
6130 | intel_unregister_dsm_handler(); |
6131 | ||
6132 | ||
652c393a JB |
6133 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6134 | /* Skip inactive CRTCs */ | |
6135 | if (!crtc->fb) | |
6136 | continue; | |
6137 | ||
6138 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6139 | intel_increase_pllclock(crtc); |
652c393a JB |
6140 | } |
6141 | ||
e70236a8 JB |
6142 | if (dev_priv->display.disable_fbc) |
6143 | dev_priv->display.disable_fbc(dev); | |
6144 | ||
aa40d6bb ZN |
6145 | if (dev_priv->renderctx) { |
6146 | struct drm_i915_gem_object *obj_priv; | |
6147 | ||
6148 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
6149 | I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN); | |
6150 | I915_READ(CCID); | |
6151 | i915_gem_object_unpin(dev_priv->renderctx); | |
6152 | drm_gem_object_unreference(dev_priv->renderctx); | |
6153 | } | |
6154 | ||
97f5ab66 | 6155 | if (dev_priv->pwrctx) { |
c1b5dea0 KH |
6156 | struct drm_i915_gem_object *obj_priv; |
6157 | ||
23010e43 | 6158 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
c1b5dea0 KH |
6159 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); |
6160 | I915_READ(PWRCTXA); | |
97f5ab66 JB |
6161 | i915_gem_object_unpin(dev_priv->pwrctx); |
6162 | drm_gem_object_unreference(dev_priv->pwrctx); | |
6163 | } | |
6164 | ||
f97108d1 JB |
6165 | if (IS_IRONLAKE_M(dev)) |
6166 | ironlake_disable_drps(dev); | |
6167 | ||
69341a5e KH |
6168 | mutex_unlock(&dev->struct_mutex); |
6169 | ||
6c0d9350 DV |
6170 | /* Disable the irq before mode object teardown, for the irq might |
6171 | * enqueue unpin/hotplug work. */ | |
6172 | drm_irq_uninstall(dev); | |
6173 | cancel_work_sync(&dev_priv->hotplug_work); | |
6174 | ||
3dec0095 DV |
6175 | /* Shut off idle work before the crtcs get freed. */ |
6176 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6177 | intel_crtc = to_intel_crtc(crtc); | |
6178 | del_timer_sync(&intel_crtc->idle_timer); | |
6179 | } | |
6180 | del_timer_sync(&dev_priv->idle_timer); | |
6181 | cancel_work_sync(&dev_priv->idle_work); | |
6182 | ||
79e53945 JB |
6183 | drm_mode_config_cleanup(dev); |
6184 | } | |
6185 | ||
f1c79df3 ZW |
6186 | /* |
6187 | * Return which encoder is currently attached for connector. | |
6188 | */ | |
df0e9248 | 6189 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6190 | { |
df0e9248 CW |
6191 | return &intel_attached_encoder(connector)->base; |
6192 | } | |
f1c79df3 | 6193 | |
df0e9248 CW |
6194 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6195 | struct intel_encoder *encoder) | |
6196 | { | |
6197 | connector->encoder = encoder; | |
6198 | drm_mode_connector_attach_encoder(&connector->base, | |
6199 | &encoder->base); | |
79e53945 | 6200 | } |
28d52043 DA |
6201 | |
6202 | /* | |
6203 | * set vga decode state - true == enable VGA decode | |
6204 | */ | |
6205 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6206 | { | |
6207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6208 | u16 gmch_ctrl; | |
6209 | ||
6210 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6211 | if (state) | |
6212 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6213 | else | |
6214 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6215 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6216 | return 0; | |
6217 | } |