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Merge tag 'sound-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179 938
8e636784
DV		 939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
b24e7179
JB		 943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
63d7bbe9
JB		 945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 948 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 949}
950
931872fc
CW		 951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
b24e7179
JB		 953{
954 int reg;
955 u32 val;
931872fc 956 bool cur_state;
b24e7179
JB		 957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
931872fc
CW		 960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 964}
965
931872fc
CW		 966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
b24e7179
JB		 969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
19ec1358 976 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
19ec1358 983 return;
28c05794 984 }
19ec1358 985
b24e7179
JB		 986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
b24e7179
JB		 995 }
996}
997
92f2584a
JB		 998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
92f2584a
JB		 1022}
1023
4e634389
KP		 1024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
1519b995
KP		 1042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
291906f1 1089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1090 enum pipe pipe, int reg, u32 port_sel)
291906f1 1091{
47a05eca 1092 u32 val = I915_READ(reg);
4e634389 1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1095 reg, pipe_name(pipe));
291906f1
JB		 1096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
47a05eca 1101 u32 val = I915_READ(reg);
1519b995 1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1104 reg, pipe_name(pipe));
291906f1
JB		 1105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
291906f1 1112
f0575e92
KP		 1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1519b995 1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1121 pipe_name(pipe));
291906f1
JB		 1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1519b995 1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1127 pipe_name(pipe));
291906f1
JB		 1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
63d7bbe9
JB		 1134/**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
92f2584a
JB		 1201/**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
4c609cb8
JB		 1215 if (pipe > 1)
1216 return;
1217
92f2584a
JB		 1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
7a419866
JB		 1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1238
4c609cb8
JB		 1239 if (pipe > 1)
1240 return;
1241
92f2584a
JB		 1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
7a419866
JB		 1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
92f2584a
JB		 1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
040484af
JB		 1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
5f7f726d 1269 u32 val, pipeconf_val;
7c26e5c6 1270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1271
1272 /* PCH only available on ILK+ */
1273 BUG_ON(dev_priv->info->gen < 5);
1274
1275 /* Make sure PCH DPLL is enabled */
1276 assert_pch_pll_enabled(dev_priv, pipe);
1277
1278 /* FDI must be feeding us bits for PCH ports */
1279 assert_fdi_tx_enabled(dev_priv, pipe);
1280 assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282 reg = TRANSCONF(pipe);
1283 val = I915_READ(reg);
5f7f726d 1284 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1285
1286 if (HAS_PCH_IBX(dev_priv->dev)) {
1287 /*
1288 * make the BPC in transcoder be consistent with
1289 * that in pipeconf reg.
1290 */
1291 val &= ~PIPE_BPC_MASK;
5f7f726d 1292 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1293 }
5f7f726d
PZ		 1294
1295 val &= ~TRANS_INTERLACE_MASK;
1296 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1297 if (HAS_PCH_IBX(dev_priv->dev) &&
1298 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299 val |= TRANS_LEGACY_INTERLACED_ILK;
1300 else
1301 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1302 else
1303 val |= TRANS_PROGRESSIVE;
1304
040484af
JB		 1305 I915_WRITE(reg, val | TRANS_ENABLE);
1306 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308}
1309
1310static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312{
1313 int reg;
1314 u32 val;
1315
1316 /* FDI relies on the transcoder */
1317 assert_fdi_tx_disabled(dev_priv, pipe);
1318 assert_fdi_rx_disabled(dev_priv, pipe);
1319
291906f1
JB		 1320 /* Ports must be off as well */
1321 assert_pch_ports_disabled(dev_priv, pipe);
1322
040484af
JB		 1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 val &= ~TRANS_ENABLE;
1326 I915_WRITE(reg, val);
1327 /* wait for PCH transcoder off, transcoder state */
1328 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1329 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1330}
1331
b24e7179 1332/**
309cfea8 1333 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1334 * @dev_priv: i915 private structure
1335 * @pipe: pipe to enable
040484af 1336 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1337 *
1338 * Enable @pipe, making sure that various hardware specific requirements
1339 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340 *
1341 * @pipe should be %PIPE_A or %PIPE_B.
1342 *
1343 * Will wait until the pipe is actually running (i.e. first vblank) before
1344 * returning.
1345 */
040484af
JB		 1346static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347 bool pch_port)
b24e7179
JB		 1348{
1349 int reg;
1350 u32 val;
1351
1352 /*
1353 * A pipe without a PLL won't actually be able to drive bits from
1354 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1355 * need the check.
1356 */
1357 if (!HAS_PCH_SPLIT(dev_priv->dev))
1358 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1359 else {
1360 if (pch_port) {
1361 /* if driving the PCH, we need FDI enabled */
1362 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364 }
1365 /* FIXME: assert CPU port conditions for SNB+ */
1366 }
b24e7179
JB		 1367
1368 reg = PIPECONF(pipe);
1369 val = I915_READ(reg);
00d70b15
CW		 1370 if (val & PIPECONF_ENABLE)
1371 return;
1372
1373 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1374 intel_wait_for_vblank(dev_priv->dev, pipe);
1375}
1376
1377/**
309cfea8 1378 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1379 * @dev_priv: i915 private structure
1380 * @pipe: pipe to disable
1381 *
1382 * Disable @pipe, making sure that various hardware specific requirements
1383 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384 *
1385 * @pipe should be %PIPE_A or %PIPE_B.
1386 *
1387 * Will wait until the pipe has shut down before returning.
1388 */
1389static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391{
1392 int reg;
1393 u32 val;
1394
1395 /*
1396 * Make sure planes won't keep trying to pump pixels to us,
1397 * or we might hang the display.
1398 */
1399 assert_planes_disabled(dev_priv, pipe);
1400
1401 /* Don't disable pipe A or pipe A PLLs if needed */
1402 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 return;
1404
1405 reg = PIPECONF(pipe);
1406 val = I915_READ(reg);
00d70b15
CW		 1407 if ((val & PIPECONF_ENABLE) == 0)
1408 return;
1409
1410 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1411 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412}
1413
d74362c9
KP		 1414/*
1415 * Plane regs are double buffered, going from enabled->disabled needs a
1416 * trigger in order to latch. The display address reg provides this.
1417 */
1418static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane)
1420{
1421 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423}
1424
b24e7179
JB		 1425/**
1426 * intel_enable_plane - enable a display plane on a given pipe
1427 * @dev_priv: i915 private structure
1428 * @plane: plane to enable
1429 * @pipe: pipe being fed
1430 *
1431 * Enable @plane on @pipe, making sure that @pipe is running first.
1432 */
1433static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434 enum plane plane, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440 assert_pipe_enabled(dev_priv, pipe);
1441
1442 reg = DSPCNTR(plane);
1443 val = I915_READ(reg);
00d70b15
CW		 1444 if (val & DISPLAY_PLANE_ENABLE)
1445 return;
1446
1447 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1448 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1449 intel_wait_for_vblank(dev_priv->dev, pipe);
1450}
1451
b24e7179
JB		 1452/**
1453 * intel_disable_plane - disable a display plane
1454 * @dev_priv: i915 private structure
1455 * @plane: plane to disable
1456 * @pipe: pipe consuming the data
1457 *
1458 * Disable @plane; should be an independent operation.
1459 */
1460static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461 enum plane plane, enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
1465
1466 reg = DSPCNTR(plane);
1467 val = I915_READ(reg);
00d70b15
CW		 1468 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469 return;
1470
1471 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1472 intel_flush_display_plane(dev_priv, plane);
1473 intel_wait_for_vblank(dev_priv->dev, pipe);
1474}
1475
47a05eca 1476static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1477 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1478{
1479 u32 val = I915_READ(reg);
4e634389 1480 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1481 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1482 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1483 }
47a05eca
JB		 1484}
1485
1486static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, int reg)
1488{
1489 u32 val = I915_READ(reg);
1519b995 1490 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1491 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492 reg, pipe);
47a05eca 1493 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1494 }
47a05eca
JB		 1495}
1496
1497/* Disable any ports connected to this transcoder */
1498static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499 enum pipe pipe)
1500{
1501 u32 reg, val;
1502
1503 val = I915_READ(PCH_PP_CONTROL);
1504 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
f0575e92
KP		 1506 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1509
1510 reg = PCH_ADPA;
1511 val = I915_READ(reg);
1519b995 1512 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1513 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515 reg = PCH_LVDS;
1516 val = I915_READ(reg);
1519b995
KP		 1517 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1519 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520 POSTING_READ(reg);
1521 udelay(100);
1522 }
1523
1524 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526 disable_pch_hdmi(dev_priv, pipe, HDMID);
1527}
1528
43a9539f
CW		 1529static void i8xx_disable_fbc(struct drm_device *dev)
1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 u32 fbc_ctl;
1533
1534 /* Disable compression */
1535 fbc_ctl = I915_READ(FBC_CONTROL);
1536 if ((fbc_ctl & FBC_CTL_EN) == 0)
1537 return;
1538
1539 fbc_ctl &= ~FBC_CTL_EN;
1540 I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542 /* Wait for compressing bit to clear */
1543 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544 DRM_DEBUG_KMS("FBC idle timed out\n");
1545 return;
1546 }
1547
1548 DRM_DEBUG_KMS("disabled FBC\n");
1549}
1550
80824003
JB		 1551static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1559 int cfb_pitch;
80824003
JB		 1560 int plane, i;
1561 u32 fbc_ctl, fbc_ctl2;
1562
016b9b61 1563 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1564 if (fb->pitches[0] < cfb_pitch)
1565 cfb_pitch = fb->pitches[0];
80824003
JB		 1566
1567 /* FBC_CTL wants 64B units */
016b9b61
CW		 1568 cfb_pitch = (cfb_pitch / 64) - 1;
1569 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1570
1571 /* Clear old tags */
1572 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575 /* Set it up... */
de568510
CW		 1576 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577 fbc_ctl2 |= plane;
80824003
JB		 1578 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581 /* enable it... */
1582 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1583 if (IS_I945GM(dev))
49677901 1584 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1585 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1586 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1587 fbc_ctl |= obj->fence_reg;
80824003
JB		 1588 I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
016b9b61
CW		 1590 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1592}
1593
ee5382ae 1594static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1595{
80824003
JB		 1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599}
1600
74dff282
JB		 1601static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602{
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1607 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
74dff282 1613 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1614 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1615 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1616
74dff282
JB		 1617 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622 /* enable it... */
1623 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
28c97730 1625 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1626}
1627
43a9539f 1628static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1629{
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 u32 dpfc_ctl;
1632
1633 /* Disable compression */
1634 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1635 if (dpfc_ctl & DPFC_CTL_EN) {
1636 dpfc_ctl &= ~DPFC_CTL_EN;
1637 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1638
bed4a673
CW		 1639 DRM_DEBUG_KMS("disabled FBC\n");
1640 }
74dff282
JB		 1641}
1642
ee5382ae 1643static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1644{
74dff282
JB		 1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648}
1649
4efe0708
JB		 1650static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 u32 blt_ecoskpd;
1654
1655 /* Make sure blitter notifies FBC of writes */
fcca7926 1656 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1657 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659 GEN6_BLITTER_LOCK_SHIFT;
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664 GEN6_BLITTER_LOCK_SHIFT);
1665 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1667 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1668}
1669
b52eb4dc
ZY		 1670static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_device *dev = crtc->dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 struct drm_framebuffer *fb = crtc->fb;
1675 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1676 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1678 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1679 unsigned long stall_watermark = 200;
1680 u32 dpfc_ctl;
1681
bed4a673 1682 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1683 dpfc_ctl &= DPFC_RESERVED;
1684 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1685 /* Set persistent mode for front-buffer rendering, ala X. */
1686 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1687 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1688 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1689
b52eb4dc
ZY		 1690 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1694 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1695 /* enable it... */
bed4a673 1696 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1697
9c04f015
YL		 1698 if (IS_GEN6(dev)) {
1699 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1700 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1701 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1702 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1703 }
1704
b52eb4dc
ZY		 1705 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706}
1707
43a9539f 1708static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1709{
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 u32 dpfc_ctl;
1712
1713 /* Disable compression */
1714 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1715 if (dpfc_ctl & DPFC_CTL_EN) {
1716 dpfc_ctl &= ~DPFC_CTL_EN;
1717 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1718
bed4a673
CW		 1719 DRM_DEBUG_KMS("disabled FBC\n");
1720 }
b52eb4dc
ZY		 1721}
1722
1723static bool ironlake_fbc_enabled(struct drm_device *dev)
1724{
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728}
1729
ee5382ae
AJ		 1730bool intel_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 if (!dev_priv->display.fbc_enabled)
1735 return false;
1736
1737 return dev_priv->display.fbc_enabled(dev);
1738}
1739
1630fe75
CW		 1740static void intel_fbc_work_fn(struct work_struct *__work)
1741{
1742 struct intel_fbc_work *work =
1743 container_of(to_delayed_work(__work),
1744 struct intel_fbc_work, work);
1745 struct drm_device *dev = work->crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 mutex_lock(&dev->struct_mutex);
1749 if (work == dev_priv->fbc_work) {
1750 /* Double check that we haven't switched fb without cancelling
1751 * the prior work.
1752 */
016b9b61 1753 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1754 dev_priv->display.enable_fbc(work->crtc,
1755 work->interval);
1756
016b9b61
CW		 1757 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758 dev_priv->cfb_fb = work->crtc->fb->base.id;
1759 dev_priv->cfb_y = work->crtc->y;
1760 }
1761
1630fe75
CW		 1762 dev_priv->fbc_work = NULL;
1763 }
1764 mutex_unlock(&dev->struct_mutex);
1765
1766 kfree(work);
1767}
1768
1769static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770{
1771 if (dev_priv->fbc_work == NULL)
1772 return;
1773
1774 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776 /* Synchronisation is provided by struct_mutex and checking of
1777 * dev_priv->fbc_work, so we can perform the cancellation
1778 * entirely asynchronously.
1779 */
1780 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781 /* tasklet was killed before being run, clean up */
1782 kfree(dev_priv->fbc_work);
1783
1784 /* Mark the work as no longer wanted so that if it does
1785 * wake-up (because the work was already running and waiting
1786 * for our mutex), it will discover that is no longer
1787 * necessary to run.
1788 */
1789 dev_priv->fbc_work = NULL;
1790}
1791
43a9539f 1792static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1793{
1630fe75
CW		 1794 struct intel_fbc_work *work;
1795 struct drm_device *dev = crtc->dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1797
1798 if (!dev_priv->display.enable_fbc)
1799 return;
1800
1630fe75
CW		 1801 intel_cancel_fbc_work(dev_priv);
1802
1803 work = kzalloc(sizeof *work, GFP_KERNEL);
1804 if (work == NULL) {
1805 dev_priv->display.enable_fbc(crtc, interval);
1806 return;
1807 }
1808
1809 work->crtc = crtc;
1810 work->fb = crtc->fb;
1811 work->interval = interval;
1812 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814 dev_priv->fbc_work = work;
1815
1816 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1819 * display to settle before starting the compression. Note that
1820 * this delay also serves a second purpose: it allows for a
1821 * vblank to pass after disabling the FBC before we attempt
1822 * to modify the control registers.
1630fe75
CW		 1823 *
1824 * A more complicated solution would involve tracking vblanks
1825 * following the termination of the page-flipping sequence
1826 * and indeed performing the enable as a co-routine and not
1827 * waiting synchronously upon the vblank.
1828 */
1829 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1830}
1831
1832void intel_disable_fbc(struct drm_device *dev)
1833{
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835
1630fe75
CW		 1836 intel_cancel_fbc_work(dev_priv);
1837
ee5382ae
AJ		 1838 if (!dev_priv->display.disable_fbc)
1839 return;
1840
1841 dev_priv->display.disable_fbc(dev);
016b9b61 1842 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1843}
1844
80824003
JB		 1845/**
1846 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1847 * @dev: the drm_device
80824003
JB		 1848 *
1849 * Set up the framebuffer compression hardware at mode set time. We
1850 * enable it if possible:
1851 * - plane A only (on pre-965)
1852 * - no pixel mulitply/line duplication
1853 * - no alpha buffer discard
1854 * - no dual wide
1855 * - framebuffer <= 2048 in width, 1536 in height
1856 *
1857 * We can't assume that any compression will take place (worst case),
1858 * so the compressed buffer has to be the same size as the uncompressed
1859 * one. It also must reside (along with the line length buffer) in
1860 * stolen memory.
1861 *
1862 * We need to enable/disable FBC on a global basis.
1863 */
bed4a673 1864static void intel_update_fbc(struct drm_device *dev)
80824003 1865{
80824003 1866 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1867 struct drm_crtc *crtc = NULL, *tmp_crtc;
1868 struct intel_crtc *intel_crtc;
1869 struct drm_framebuffer *fb;
80824003 1870 struct intel_framebuffer *intel_fb;
05394f39 1871 struct drm_i915_gem_object *obj;
cd0de039 1872 int enable_fbc;
9c928d16
JB		 1873
1874 DRM_DEBUG_KMS("\n");
80824003
JB		 1875
1876 if (!i915_powersave)
1877 return;
1878
ee5382ae 1879 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1880 return;
1881
80824003
JB		 1882 /*
1883 * If FBC is already on, we just have to verify that we can
1884 * keep it that way...
1885 * Need to disable if:
9c928d16 1886 * - more than one pipe is active
80824003
JB		 1887 * - changing FBC params (stride, fence, mode)
1888 * - new fb is too large to fit in compressed buffer
1889 * - going to an unsupported config (interlace, pixel multiply, etc.)
1890 */
9c928d16 1891 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1892 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1893 if (crtc) {
1894 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896 goto out_disable;
1897 }
1898 crtc = tmp_crtc;
1899 }
9c928d16 1900 }
bed4a673
CW		 1901
1902 if (!crtc || crtc->fb == NULL) {
1903 DRM_DEBUG_KMS("no output, disabling\n");
1904 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1905 goto out_disable;
1906 }
bed4a673
CW		 1907
1908 intel_crtc = to_intel_crtc(crtc);
1909 fb = crtc->fb;
1910 intel_fb = to_intel_framebuffer(fb);
05394f39 1911 obj = intel_fb->obj;
bed4a673 1912
cd0de039
KP		 1913 enable_fbc = i915_enable_fbc;
1914 if (enable_fbc < 0) {
1915 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916 enable_fbc = 1;
d56d8b28 1917 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1918 enable_fbc = 0;
1919 }
1920 if (!enable_fbc) {
1921 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1922 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923 goto out_disable;
1924 }
05394f39 1925 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1926 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1927 "compression\n");
b5e50c3f 1928 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1929 goto out_disable;
1930 }
bed4a673
CW		 1931 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1933 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1934 "disabling\n");
b5e50c3f 1935 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1936 goto out_disable;
1937 }
bed4a673
CW		 1938 if ((crtc->mode.hdisplay > 2048) ||
1939 (crtc->mode.vdisplay > 1536)) {
28c97730 1940 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1941 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1942 goto out_disable;
1943 }
bed4a673 1944 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1945 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1946 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1947 goto out_disable;
1948 }
de568510
CW		 1949
1950 /* The use of a CPU fence is mandatory in order to detect writes
1951 * by the CPU to the scanout and trigger updates to the FBC.
1952 */
1953 if (obj->tiling_mode != I915_TILING_X ||
1954 obj->fence_reg == I915_FENCE_REG_NONE) {
1955 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1956 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1957 goto out_disable;
1958 }
1959
c924b934
JW		 1960 /* If the kernel debugger is active, always disable compression */
1961 if (in_dbg_master())
1962 goto out_disable;
1963
016b9b61
CW		 1964 /* If the scanout has not changed, don't modify the FBC settings.
1965 * Note that we make the fundamental assumption that the fb->obj
1966 * cannot be unpinned (and have its GTT offset and fence revoked)
1967 * without first being decoupled from the scanout and FBC disabled.
1968 */
1969 if (dev_priv->cfb_plane == intel_crtc->plane &&
1970 dev_priv->cfb_fb == fb->base.id &&
1971 dev_priv->cfb_y == crtc->y)
1972 return;
1973
1974 if (intel_fbc_enabled(dev)) {
1975 /* We update FBC along two paths, after changing fb/crtc
1976 * configuration (modeswitching) and after page-flipping
1977 * finishes. For the latter, we know that not only did
1978 * we disable the FBC at the start of the page-flip
1979 * sequence, but also more than one vblank has passed.
1980 *
1981 * For the former case of modeswitching, it is possible
1982 * to switch between two FBC valid configurations
1983 * instantaneously so we do need to disable the FBC
1984 * before we can modify its control registers. We also
1985 * have to wait for the next vblank for that to take
1986 * effect. However, since we delay enabling FBC we can
1987 * assume that a vblank has passed since disabling and
1988 * that we can safely alter the registers in the deferred
1989 * callback.
1990 *
1991 * In the scenario that we go from a valid to invalid
1992 * and then back to valid FBC configuration we have
1993 * no strict enforcement that a vblank occurred since
1994 * disabling the FBC. However, along all current pipe
1995 * disabling paths we do need to wait for a vblank at
1996 * some point. And we wait before enabling FBC anyway.
1997 */
1998 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999 intel_disable_fbc(dev);
2000 }
2001
bed4a673 2002 intel_enable_fbc(crtc, 500);
80824003
JB		 2003 return;
2004
2005out_disable:
80824003 2006 /* Multiple disables should be harmless */
a939406f
CW		 2007 if (intel_fbc_enabled(dev)) {
2008 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 2009 intel_disable_fbc(dev);
a939406f 2010 }
80824003
JB		 2011}
2012
127bd2ac 2013int
48b956c5 2014intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2015 struct drm_i915_gem_object *obj,
919926ae 2016 struct intel_ring_buffer *pipelined)
6b95a207 2017{
ce453d81 2018 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2019 u32 alignment;
2020 int ret;
2021
05394f39 2022 switch (obj->tiling_mode) {
6b95a207 2023 case I915_TILING_NONE:
534843da
CW		 2024 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025 alignment = 128 * 1024;
a6c45cf0 2026 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2027 alignment = 4 * 1024;
2028 else
2029 alignment = 64 * 1024;
6b95a207
KH		 2030 break;
2031 case I915_TILING_X:
2032 /* pin() will align the object as required by fence */
2033 alignment = 0;
2034 break;
2035 case I915_TILING_Y:
2036 /* FIXME: Is this true? */
2037 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038 return -EINVAL;
2039 default:
2040 BUG();
2041 }
2042
ce453d81 2043 dev_priv->mm.interruptible = false;
2da3b9b9 2044 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2045 if (ret)
ce453d81 2046 goto err_interruptible;
6b95a207
KH		 2047
2048 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049 * fence, whereas 965+ only requires a fence if using
2050 * framebuffer compression. For simplicity, we always install
2051 * a fence as the cost is not that onerous.
2052 */
05394f39 2053 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2054 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2055 if (ret)
2056 goto err_unpin;
1690e1eb
CW		 2057
2058 i915_gem_object_pin_fence(obj);
6b95a207
KH		 2059 }
2060
ce453d81 2061 dev_priv->mm.interruptible = true;
6b95a207 2062 return 0;
48b956c5
CW		 2063
2064err_unpin:
2065 i915_gem_object_unpin(obj);
ce453d81
CW		 2066err_interruptible:
2067 dev_priv->mm.interruptible = true;
48b956c5 2068 return ret;
6b95a207
KH		 2069}
2070
1690e1eb
CW		 2071void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072{
2073 i915_gem_object_unpin_fence(obj);
2074 i915_gem_object_unpin(obj);
2075}
2076
17638cd6
JB		 2077static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078 int x, int y)
81255565
JB		 2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
05394f39 2084 struct drm_i915_gem_object *obj;
81255565
JB		 2085 int plane = intel_crtc->plane;
2086 unsigned long Start, Offset;
81255565 2087 u32 dspcntr;
5eddb70b 2088 u32 reg;
81255565
JB		 2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 break;
2094 default:
2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096 return -EINVAL;
2097 }
2098
2099 intel_fb = to_intel_framebuffer(fb);
2100 obj = intel_fb->obj;
81255565 2101
5eddb70b
CW		 2102 reg = DSPCNTR(plane);
2103 dspcntr = I915_READ(reg);
81255565
JB		 2104 /* Mask out pixel format bits in case we change it */
2105 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106 switch (fb->bits_per_pixel) {
2107 case 8:
2108 dspcntr |= DISPPLANE_8BPP;
2109 break;
2110 case 16:
2111 if (fb->depth == 15)
2112 dspcntr |= DISPPLANE_15_16BPP;
2113 else
2114 dspcntr |= DISPPLANE_16BPP;
2115 break;
2116 case 24:
2117 case 32:
2118 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119 break;
2120 default:
17638cd6 2121 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2122 return -EINVAL;
2123 }
a6c45cf0 2124 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2125 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2126 dspcntr |= DISPPLANE_TILED;
2127 else
2128 dspcntr &= ~DISPPLANE_TILED;
2129 }
2130
5eddb70b 2131 I915_WRITE(reg, dspcntr);
81255565 2132
05394f39 2133 Start = obj->gtt_offset;
01f2c773 2134 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2135
4e6cfefc 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2137 Start, Offset, x, y, fb->pitches[0]);
2138 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2140 I915_WRITE(DSPSURF(plane), Start);
2141 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142 I915_WRITE(DSPADDR(plane), Offset);
2143 } else
2144 I915_WRITE(DSPADDR(plane), Start + Offset);
2145 POSTING_READ(reg);
81255565 2146
17638cd6
JB		 2147 return 0;
2148}
2149
2150static int ironlake_update_plane(struct drm_crtc *crtc,
2151 struct drm_framebuffer *fb, int x, int y)
2152{
2153 struct drm_device *dev = crtc->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156 struct intel_framebuffer *intel_fb;
2157 struct drm_i915_gem_object *obj;
2158 int plane = intel_crtc->plane;
2159 unsigned long Start, Offset;
2160 u32 dspcntr;
2161 u32 reg;
2162
2163 switch (plane) {
2164 case 0:
2165 case 1:
27f8227b 2166 case 2:
17638cd6
JB		 2167 break;
2168 default:
2169 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170 return -EINVAL;
2171 }
2172
2173 intel_fb = to_intel_framebuffer(fb);
2174 obj = intel_fb->obj;
2175
2176 reg = DSPCNTR(plane);
2177 dspcntr = I915_READ(reg);
2178 /* Mask out pixel format bits in case we change it */
2179 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180 switch (fb->bits_per_pixel) {
2181 case 8:
2182 dspcntr |= DISPPLANE_8BPP;
2183 break;
2184 case 16:
2185 if (fb->depth != 16)
2186 return -EINVAL;
2187
2188 dspcntr |= DISPPLANE_16BPP;
2189 break;
2190 case 24:
2191 case 32:
2192 if (fb->depth == 24)
2193 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194 else if (fb->depth == 30)
2195 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196 else
2197 return -EINVAL;
2198 break;
2199 default:
2200 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201 return -EINVAL;
2202 }
2203
2204 if (obj->tiling_mode != I915_TILING_NONE)
2205 dspcntr |= DISPPLANE_TILED;
2206 else
2207 dspcntr &= ~DISPPLANE_TILED;
2208
2209 /* must disable */
2210 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212 I915_WRITE(reg, dspcntr);
2213
2214 Start = obj->gtt_offset;
01f2c773 2215 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2216
2217 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2218 Start, Offset, x, y, fb->pitches[0]);
2219 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2220 I915_WRITE(DSPSURF(plane), Start);
2221 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222 I915_WRITE(DSPADDR(plane), Offset);
2223 POSTING_READ(reg);
2224
2225 return 0;
2226}
2227
2228/* Assume fb object is pinned & idle & fenced and just update base pointers */
2229static int
2230intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231 int x, int y, enum mode_set_atomic state)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 int ret;
2236
2237 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238 if (ret)
2239 return ret;
2240
bed4a673 2241 intel_update_fbc(dev);
3dec0095 2242 intel_increase_pllclock(crtc);
81255565
JB		 2243
2244 return 0;
2245}
2246
14667a4b
CW		 2247static int
2248intel_finish_fb(struct drm_framebuffer *old_fb)
2249{
2250 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2251 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2252 bool was_interruptible = dev_priv->mm.interruptible;
2253 int ret;
2254
2255 wait_event(dev_priv->pending_flip_queue,
2256 atomic_read(&dev_priv->mm.wedged) ||
2257 atomic_read(&obj->pending_flip) == 0);
2258
2259 /* Big Hammer, we also need to ensure that any pending
2260 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2261 * current scanout is retired before unpinning the old
2262 * framebuffer.
2263 *
2264 * This should only fail upon a hung GPU, in which case we
2265 * can safely continue.
2266 */
2267 dev_priv->mm.interruptible = false;
2268 ret = i915_gem_object_finish_gpu(obj);
2269 dev_priv->mm.interruptible = was_interruptible;
2270
2271 return ret;
2272}
2273
5c3b82e2 2274static int
3c4fdcfb
KH		 2275intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2276 struct drm_framebuffer *old_fb)
79e53945
JB		 2277{
2278 struct drm_device *dev = crtc->dev;
79e53945
JB		 2279 struct drm_i915_master_private *master_priv;
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2281 int ret;
79e53945
JB		 2282
2283 /* no fb bound */
2284 if (!crtc->fb) {
a5071c2f 2285 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2286 return 0;
2287 }
2288
265db958 2289 switch (intel_crtc->plane) {
5c3b82e2
CW		 2290 case 0:
2291 case 1:
2292 break;
27f8227b
JB		 2293 case 2:
2294 if (IS_IVYBRIDGE(dev))
2295 break;
2296 /* fall through otherwise */
5c3b82e2 2297 default:
a5071c2f 2298 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2299 return -EINVAL;
79e53945
JB		 2300 }
2301
5c3b82e2 2302 mutex_lock(&dev->struct_mutex);
265db958
CW		 2303 ret = intel_pin_and_fence_fb_obj(dev,
2304 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2305 NULL);
5c3b82e2
CW		 2306 if (ret != 0) {
2307 mutex_unlock(&dev->struct_mutex);
a5071c2f 2308 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2309 return ret;
2310 }
79e53945 2311
14667a4b
CW		 2312 if (old_fb)
2313 intel_finish_fb(old_fb);
265db958 2314
21c74a8e
JW		 2315 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2316 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2317 if (ret) {
1690e1eb 2318 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2319 mutex_unlock(&dev->struct_mutex);
a5071c2f 2320 DRM_ERROR("failed to update base address\n");
4e6cfefc 2321 return ret;
79e53945 2322 }
3c4fdcfb 2323
b7f1de28
CW		 2324 if (old_fb) {
2325 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2326 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2327 }
652c393a 2328
5c3b82e2 2329 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2330
2331 if (!dev->primary->master)
5c3b82e2 2332 return 0;
79e53945
JB		 2333
2334 master_priv = dev->primary->master->driver_priv;
2335 if (!master_priv->sarea_priv)
5c3b82e2 2336 return 0;
79e53945 2337
265db958 2338 if (intel_crtc->pipe) {
79e53945
JB		 2339 master_priv->sarea_priv->pipeB_x = x;
2340 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2341 } else {
2342 master_priv->sarea_priv->pipeA_x = x;
2343 master_priv->sarea_priv->pipeA_y = y;
79e53945 2344 }
5c3b82e2
CW		 2345
2346 return 0;
79e53945
JB		 2347}
2348
5eddb70b 2349static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2350{
2351 struct drm_device *dev = crtc->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 dpa_ctl;
2354
28c97730 2355 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2356 dpa_ctl = I915_READ(DP_A);
2357 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359 if (clock < 200000) {
2360 u32 temp;
2361 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362 /* workaround for 160Mhz:
2363 1) program 0x4600c bits 15:0 = 0x8124
2364 2) program 0x46010 bit 0 = 1
2365 3) program 0x46034 bit 24 = 1
2366 4) program 0x64000 bit 14 = 1
2367 */
2368 temp = I915_READ(0x4600c);
2369 temp &= 0xffff0000;
2370 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372 temp = I915_READ(0x46010);
2373 I915_WRITE(0x46010, temp | 1);
2374
2375 temp = I915_READ(0x46034);
2376 I915_WRITE(0x46034, temp | (1 << 24));
2377 } else {
2378 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379 }
2380 I915_WRITE(DP_A, dpa_ctl);
2381
5eddb70b 2382 POSTING_READ(DP_A);
32f9d658
ZW		 2383 udelay(500);
2384}
2385
5e84e1a4
ZW		 2386static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387{
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 int pipe = intel_crtc->pipe;
2392 u32 reg, temp;
2393
2394 /* enable normal train */
2395 reg = FDI_TX_CTL(pipe);
2396 temp = I915_READ(reg);
61e499bf 2397 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2398 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2400 } else {
2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2403 }
5e84e1a4
ZW		 2404 I915_WRITE(reg, temp);
2405
2406 reg = FDI_RX_CTL(pipe);
2407 temp = I915_READ(reg);
2408 if (HAS_PCH_CPT(dev)) {
2409 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411 } else {
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_NONE;
2414 }
2415 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417 /* wait one idle pattern time */
2418 POSTING_READ(reg);
2419 udelay(1000);
357555c0
JB		 2420
2421 /* IVB wants error correction enabled */
2422 if (IS_IVYBRIDGE(dev))
2423 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2425}
2426
291427f5
JB		 2427static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432 flags |= FDI_PHASE_SYNC_OVR(pipe);
2433 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434 flags |= FDI_PHASE_SYNC_EN(pipe);
2435 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436 POSTING_READ(SOUTH_CHICKEN1);
2437}
2438
8db9d77b
ZW		 2439/* The FDI link training functions for ILK/Ibexpeak. */
2440static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2441{
2442 struct drm_device *dev = crtc->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445 int pipe = intel_crtc->pipe;
0fc932b8 2446 int plane = intel_crtc->plane;
5eddb70b 2447 u32 reg, temp, tries;
8db9d77b 2448
0fc932b8
JB		 2449 /* FDI needs bits from pipe & plane first */
2450 assert_pipe_enabled(dev_priv, pipe);
2451 assert_plane_enabled(dev_priv, plane);
2452
e1a44743
AJ		 2453 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2454 for train result */
5eddb70b
CW		 2455 reg = FDI_RX_IMR(pipe);
2456 temp = I915_READ(reg);
e1a44743
AJ		 2457 temp &= ~FDI_RX_SYMBOL_LOCK;
2458 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2459 I915_WRITE(reg, temp);
2460 I915_READ(reg);
e1a44743
AJ		 2461 udelay(150);
2462
8db9d77b 2463 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
77ffb597
AJ		 2466 temp &= ~(7 << 19);
2467 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2468 temp &= ~FDI_LINK_TRAIN_NONE;
2469 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2470 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2471
5eddb70b
CW		 2472 reg = FDI_RX_CTL(pipe);
2473 temp = I915_READ(reg);
8db9d77b
ZW		 2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2476 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2477
2478 POSTING_READ(reg);
8db9d77b
ZW		 2479 udelay(150);
2480
5b2adf89 2481 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2482 if (HAS_PCH_IBX(dev)) {
2483 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2484 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2485 FDI_RX_PHASE_SYNC_POINTER_EN);
2486 }
5b2adf89 2487
5eddb70b 2488 reg = FDI_RX_IIR(pipe);
e1a44743 2489 for (tries = 0; tries < 5; tries++) {
5eddb70b 2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2492
2493 if ((temp & FDI_RX_BIT_LOCK)) {
2494 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2495 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2496 break;
2497 }
8db9d77b 2498 }
e1a44743 2499 if (tries == 5)
5eddb70b 2500 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2501
2502 /* Train 2 */
5eddb70b
CW		 2503 reg = FDI_TX_CTL(pipe);
2504 temp = I915_READ(reg);
8db9d77b
ZW		 2505 temp &= ~FDI_LINK_TRAIN_NONE;
2506 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2507 I915_WRITE(reg, temp);
8db9d77b 2508
5eddb70b
CW		 2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 temp &= ~FDI_LINK_TRAIN_NONE;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2513 I915_WRITE(reg, temp);
8db9d77b 2514
5eddb70b
CW		 2515 POSTING_READ(reg);
2516 udelay(150);
8db9d77b 2517
5eddb70b 2518 reg = FDI_RX_IIR(pipe);
e1a44743 2519 for (tries = 0; tries < 5; tries++) {
5eddb70b 2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2524 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2525 DRM_DEBUG_KMS("FDI train 2 done.\n");
2526 break;
2527 }
8db9d77b 2528 }
e1a44743 2529 if (tries == 5)
5eddb70b 2530 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2531
2532 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2533
8db9d77b
ZW		 2534}
2535
0206e353 2536static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2537 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2538 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2539 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2540 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2541};
2542
2543/* The FDI link training functions for SNB/Cougarpoint. */
2544static void gen6_fdi_link_train(struct drm_crtc *crtc)
2545{
2546 struct drm_device *dev = crtc->dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549 int pipe = intel_crtc->pipe;
5eddb70b 2550 u32 reg, temp, i;
8db9d77b 2551
e1a44743
AJ		 2552 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553 for train result */
5eddb70b
CW		 2554 reg = FDI_RX_IMR(pipe);
2555 temp = I915_READ(reg);
e1a44743
AJ		 2556 temp &= ~FDI_RX_SYMBOL_LOCK;
2557 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
e1a44743
AJ		 2561 udelay(150);
2562
8db9d77b 2563 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
77ffb597
AJ		 2566 temp &= ~(7 << 19);
2567 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2568 temp &= ~FDI_LINK_TRAIN_NONE;
2569 temp |= FDI_LINK_TRAIN_PATTERN_1;
2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 /* SNB-B */
2572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2573 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2574
5eddb70b
CW		 2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
8db9d77b
ZW		 2577 if (HAS_PCH_CPT(dev)) {
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580 } else {
2581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 }
5eddb70b
CW		 2584 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2585
2586 POSTING_READ(reg);
8db9d77b
ZW		 2587 udelay(150);
2588
291427f5
JB		 2589 if (HAS_PCH_CPT(dev))
2590 cpt_phase_pointer_enable(dev, pipe);
2591
0206e353 2592 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
8db9d77b
ZW		 2600 udelay(500);
2601
5eddb70b
CW		 2602 reg = FDI_RX_IIR(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2605
2606 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2607 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2608 DRM_DEBUG_KMS("FDI train 1 done.\n");
2609 break;
2610 }
2611 }
2612 if (i == 4)
5eddb70b 2613 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2614
2615 /* Train 2 */
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_2;
2620 if (IS_GEN6(dev)) {
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 /* SNB-B */
2623 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2624 }
5eddb70b 2625 I915_WRITE(reg, temp);
8db9d77b 2626
5eddb70b
CW		 2627 reg = FDI_RX_CTL(pipe);
2628 temp = I915_READ(reg);
8db9d77b
ZW		 2629 if (HAS_PCH_CPT(dev)) {
2630 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2632 } else {
2633 temp &= ~FDI_LINK_TRAIN_NONE;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2;
2635 }
5eddb70b
CW		 2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
8db9d77b
ZW		 2639 udelay(150);
2640
0206e353 2641 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
8db9d77b
ZW		 2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
8db9d77b
ZW		 2649 udelay(500);
2650
5eddb70b
CW		 2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
8db9d77b
ZW		 2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
5eddb70b 2662 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665}
2666
357555c0
JB		 2667/* Manual link training for Ivy Bridge A0 parts */
2668static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2669{
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 int pipe = intel_crtc->pipe;
2674 u32 reg, temp, i;
2675
2676 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2677 for train result */
2678 reg = FDI_RX_IMR(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_RX_SYMBOL_LOCK;
2681 temp &= ~FDI_RX_BIT_LOCK;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
2687 /* enable CPU FDI TX and PCH FDI RX */
2688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~(7 << 19);
2691 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2692 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2693 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2696 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2697 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2698
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_LINK_TRAIN_AUTO;
2702 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2703 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2704 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2705 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
291427f5
JB		 2710 if (HAS_PCH_CPT(dev))
2711 cpt_phase_pointer_enable(dev, pipe);
2712
0206e353 2713 for (i = 0; i < 4; i++) {
357555c0
JB		 2714 reg = FDI_TX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717 temp |= snb_b_fdi_train_param[i];
2718 I915_WRITE(reg, temp);
2719
2720 POSTING_READ(reg);
2721 udelay(500);
2722
2723 reg = FDI_RX_IIR(pipe);
2724 temp = I915_READ(reg);
2725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2726
2727 if (temp & FDI_RX_BIT_LOCK ||
2728 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2729 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2730 DRM_DEBUG_KMS("FDI train 1 done.\n");
2731 break;
2732 }
2733 }
2734 if (i == 4)
2735 DRM_ERROR("FDI train 1 fail!\n");
2736
2737 /* Train 2 */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2744 I915_WRITE(reg, temp);
2745
2746 reg = FDI_RX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2750 I915_WRITE(reg, temp);
2751
2752 POSTING_READ(reg);
2753 udelay(150);
2754
0206e353 2755 for (i = 0; i < 4; i++) {
357555c0
JB		 2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2759 temp |= snb_b_fdi_train_param[i];
2760 I915_WRITE(reg, temp);
2761
2762 POSTING_READ(reg);
2763 udelay(500);
2764
2765 reg = FDI_RX_IIR(pipe);
2766 temp = I915_READ(reg);
2767 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2768
2769 if (temp & FDI_RX_SYMBOL_LOCK) {
2770 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2771 DRM_DEBUG_KMS("FDI train 2 done.\n");
2772 break;
2773 }
2774 }
2775 if (i == 4)
2776 DRM_ERROR("FDI train 2 fail!\n");
2777
2778 DRM_DEBUG_KMS("FDI train done.\n");
2779}
2780
2781static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2782{
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 int pipe = intel_crtc->pipe;
5eddb70b 2787 u32 reg, temp;
79e53945 2788
c64e311e 2789 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2790 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2791 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2792
c98e9dcf 2793 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2794 reg = FDI_RX_CTL(pipe);
2795 temp = I915_READ(reg);
2796 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2797 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2798 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2799 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2800
2801 POSTING_READ(reg);
c98e9dcf
JB		 2802 udelay(200);
2803
2804 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp | FDI_PCDCLK);
2807
2808 POSTING_READ(reg);
c98e9dcf
JB		 2809 udelay(200);
2810
2811 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2812 reg = FDI_TX_CTL(pipe);
2813 temp = I915_READ(reg);
c98e9dcf 2814 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2815 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2816
2817 POSTING_READ(reg);
c98e9dcf 2818 udelay(100);
6be4a607 2819 }
0e23b99d
JB		 2820}
2821
291427f5
JB		 2822static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2823{
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 u32 flags = I915_READ(SOUTH_CHICKEN1);
2826
2827 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2828 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2829 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2830 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2831 POSTING_READ(SOUTH_CHICKEN1);
2832}
0fc932b8
JB		 2833static void ironlake_fdi_disable(struct drm_crtc *crtc)
2834{
2835 struct drm_device *dev = crtc->dev;
2836 struct drm_i915_private *dev_priv = dev->dev_private;
2837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838 int pipe = intel_crtc->pipe;
2839 u32 reg, temp;
2840
2841 /* disable CPU FDI tx and PCH FDI rx */
2842 reg = FDI_TX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2845 POSTING_READ(reg);
2846
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 temp &= ~(0x7 << 16);
2850 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2851 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2852
2853 POSTING_READ(reg);
2854 udelay(100);
2855
2856 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2857 if (HAS_PCH_IBX(dev)) {
2858 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2859 I915_WRITE(FDI_RX_CHICKEN(pipe),
2860 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2861 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2862 } else if (HAS_PCH_CPT(dev)) {
2863 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2864 }
0fc932b8
JB		 2865
2866 /* still set train pattern 1 */
2867 reg = FDI_TX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_1;
2871 I915_WRITE(reg, temp);
2872
2873 reg = FDI_RX_CTL(pipe);
2874 temp = I915_READ(reg);
2875 if (HAS_PCH_CPT(dev)) {
2876 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2877 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2878 } else {
2879 temp &= ~FDI_LINK_TRAIN_NONE;
2880 temp |= FDI_LINK_TRAIN_PATTERN_1;
2881 }
2882 /* BPC in FDI rx is consistent with that in PIPECONF */
2883 temp &= ~(0x07 << 16);
2884 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2885 I915_WRITE(reg, temp);
2886
2887 POSTING_READ(reg);
2888 udelay(100);
2889}
2890
6b383a7f
CW		 2891/*
2892 * When we disable a pipe, we need to clear any pending scanline wait events
2893 * to avoid hanging the ring, which we assume we are waiting on.
2894 */
2895static void intel_clear_scanline_wait(struct drm_device *dev)
2896{
2897 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2898 struct intel_ring_buffer *ring;
6b383a7f
CW		 2899 u32 tmp;
2900
2901 if (IS_GEN2(dev))
2902 /* Can't break the hang on i8xx */
2903 return;
2904
1ec14ad3 2905 ring = LP_RING(dev_priv);
8168bd48
CW		 2906 tmp = I915_READ_CTL(ring);
2907 if (tmp & RING_WAIT)
2908 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2909}
2910
e6c3a2a6
CW		 2911static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2912{
05394f39 2913 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2914 struct drm_i915_private *dev_priv;
2915
2916 if (crtc->fb == NULL)
2917 return;
2918
05394f39 2919 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2920 dev_priv = crtc->dev->dev_private;
2921 wait_event(dev_priv->pending_flip_queue,
05394f39 2922 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2923}
2924
040484af
JB		 2925static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2926{
2927 struct drm_device *dev = crtc->dev;
2928 struct drm_mode_config *mode_config = &dev->mode_config;
2929 struct intel_encoder *encoder;
2930
2931 /*
2932 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2933 * must be driven by its own crtc; no sharing is possible.
2934 */
2935 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2936 if (encoder->base.crtc != crtc)
2937 continue;
2938
2939 switch (encoder->type) {
2940 case INTEL_OUTPUT_EDP:
2941 if (!intel_encoder_is_pch_edp(&encoder->base))
2942 return false;
2943 continue;
2944 }
2945 }
2946
2947 return true;
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
4b645f14 2964 u32 reg, temp, transc_sel;
2c07245f 2965
c98e9dcf 2966 /* For PCH output, training FDI link */
674cf967 2967 dev_priv->display.fdi_link_train(crtc);
2c07245f 2968
92f2584a 2969 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2970
c98e9dcf 2971 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2972 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2973 TRANSC_DPLLB_SEL;
2974
c98e9dcf
JB		 2975 /* Be sure PCH DPLL SEL is set */
2976 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2977 if (pipe == 0) {
2978 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2979 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2980 } else if (pipe == 1) {
2981 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2982 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2983 } else if (pipe == 2) {
2984 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2985 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2986 }
c98e9dcf 2987 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2988 }
5eddb70b 2989
d9b6cb56
JB		 2990 /* set transcoder timing, panel must allow it */
2991 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2992 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2993 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2994 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2995
5eddb70b
CW		 2996 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2997 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2998 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2999 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3000
5e84e1a4
ZW		 3001 intel_fdi_normal_train(crtc);
3002
c98e9dcf
JB		 3003 /* For PCH DP, enable TRANS_DP_CTL */
3004 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3005 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3006 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3007 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3008 reg = TRANS_DP_CTL(pipe);
3009 temp = I915_READ(reg);
3010 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3011 TRANS_DP_SYNC_MASK |
3012 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3013 temp |= (TRANS_DP_OUTPUT_ENABLE |
3014 TRANS_DP_ENH_FRAMING);
9325c9f0 3015 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3016
3017 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3018 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3019 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3020 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3021
3022 switch (intel_trans_dp_port_sel(crtc)) {
3023 case PCH_DP_B:
5eddb70b 3024 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3025 break;
3026 case PCH_DP_C:
5eddb70b 3027 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3028 break;
3029 case PCH_DP_D:
5eddb70b 3030 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3031 break;
3032 default:
3033 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3034 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3035 break;
32f9d658 3036 }
2c07245f 3037
5eddb70b 3038 I915_WRITE(reg, temp);
6be4a607 3039 }
b52eb4dc 3040
040484af 3041 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3042}
3043
d4270e57
JB		 3044void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3045{
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3048 u32 temp;
3049
3050 temp = I915_READ(dslreg);
3051 udelay(500);
3052 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3053 /* Without this, mode sets may fail silently on FDI */
3054 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3055 udelay(250);
3056 I915_WRITE(tc2reg, 0);
3057 if (wait_for(I915_READ(dslreg) != temp, 5))
3058 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3059 }
3060}
3061
f67a559d
JB		 3062static void ironlake_crtc_enable(struct drm_crtc *crtc)
3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
3068 int plane = intel_crtc->plane;
3069 u32 temp;
3070 bool is_pch_port;
3071
3072 if (intel_crtc->active)
3073 return;
3074
3075 intel_crtc->active = true;
3076 intel_update_watermarks(dev);
3077
3078 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3079 temp = I915_READ(PCH_LVDS);
3080 if ((temp & LVDS_PORT_EN) == 0)
3081 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3082 }
3083
3084 is_pch_port = intel_crtc_driving_pch(crtc);
3085
3086 if (is_pch_port)
357555c0 3087 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3088 else
3089 ironlake_fdi_disable(crtc);
3090
3091 /* Enable panel fitting for LVDS */
3092 if (dev_priv->pch_pf_size &&
3093 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3094 /* Force use of hard-coded filter coefficients
3095 * as some pre-programmed values are broken,
3096 * e.g. x201.
3097 */
9db4a9c7
JB		 3098 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3099 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3100 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3101 }
3102
9c54c0dd
JB		 3103 /*
3104 * On ILK+ LUT must be loaded before the pipe is running but with
3105 * clocks enabled
3106 */
3107 intel_crtc_load_lut(crtc);
3108
f67a559d
JB		 3109 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3110 intel_enable_plane(dev_priv, plane, pipe);
3111
3112 if (is_pch_port)
3113 ironlake_pch_enable(crtc);
c98e9dcf 3114
d1ebd816 3115 mutex_lock(&dev->struct_mutex);
bed4a673 3116 intel_update_fbc(dev);
d1ebd816
BW		 3117 mutex_unlock(&dev->struct_mutex);
3118
6b383a7f 3119 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3120}
3121
3122static void ironlake_crtc_disable(struct drm_crtc *crtc)
3123{
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 int pipe = intel_crtc->pipe;
3128 int plane = intel_crtc->plane;
5eddb70b 3129 u32 reg, temp;
b52eb4dc 3130
f7abfe8b
CW		 3131 if (!intel_crtc->active)
3132 return;
3133
e6c3a2a6 3134 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3135 drm_vblank_off(dev, pipe);
6b383a7f 3136 intel_crtc_update_cursor(crtc, false);
5eddb70b 3137
b24e7179 3138 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3139
973d04f9
CW		 3140 if (dev_priv->cfb_plane == plane)
3141 intel_disable_fbc(dev);
2c07245f 3142
b24e7179 3143 intel_disable_pipe(dev_priv, pipe);
32f9d658 3144
6be4a607 3145 /* Disable PF */
9db4a9c7
JB		 3146 I915_WRITE(PF_CTL(pipe), 0);
3147 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3148
0fc932b8 3149 ironlake_fdi_disable(crtc);
2c07245f 3150
47a05eca
JB		 3151 /* This is a horrible layering violation; we should be doing this in
3152 * the connector/encoder ->prepare instead, but we don't always have
3153 * enough information there about the config to know whether it will
3154 * actually be necessary or just cause undesired flicker.
3155 */
3156 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3157
040484af 3158 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3159
6be4a607
JB		 3160 if (HAS_PCH_CPT(dev)) {
3161 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3162 reg = TRANS_DP_CTL(pipe);
3163 temp = I915_READ(reg);
3164 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3165 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3166 I915_WRITE(reg, temp);
6be4a607
JB		 3167
3168 /* disable DPLL_SEL */
3169 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3170 switch (pipe) {
3171 case 0:
d64311ab 3172 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3173 break;
3174 case 1:
6be4a607 3175 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3176 break;
3177 case 2:
4b645f14 3178 /* C shares PLL A or B */
d64311ab 3179 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3180 break;
3181 default:
3182 BUG(); /* wtf */
3183 }
6be4a607 3184 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3185 }
e3421a18 3186
6be4a607 3187 /* disable PCH DPLL */
4b645f14
JB		 3188 if (!intel_crtc->no_pll)
3189 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3190
6be4a607 3191 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3192 reg = FDI_RX_CTL(pipe);
3193 temp = I915_READ(reg);
3194 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3195
6be4a607 3196 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3197 reg = FDI_TX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3200
3201 POSTING_READ(reg);
6be4a607 3202 udelay(100);
8db9d77b 3203
5eddb70b
CW		 3204 reg = FDI_RX_CTL(pipe);
3205 temp = I915_READ(reg);
3206 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3207
6be4a607 3208 /* Wait for the clocks to turn off. */
5eddb70b 3209 POSTING_READ(reg);
6be4a607 3210 udelay(100);
6b383a7f 3211
f7abfe8b 3212 intel_crtc->active = false;
6b383a7f 3213 intel_update_watermarks(dev);
d1ebd816
BW		 3214
3215 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3216 intel_update_fbc(dev);
3217 intel_clear_scanline_wait(dev);
d1ebd816 3218 mutex_unlock(&dev->struct_mutex);
6be4a607 3219}
1b3c7a47 3220
6be4a607
JB		 3221static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3222{
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224 int pipe = intel_crtc->pipe;
3225 int plane = intel_crtc->plane;
8db9d77b 3226
6be4a607
JB		 3227 /* XXX: When our outputs are all unaware of DPMS modes other than off
3228 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3229 */
3230 switch (mode) {
3231 case DRM_MODE_DPMS_ON:
3232 case DRM_MODE_DPMS_STANDBY:
3233 case DRM_MODE_DPMS_SUSPEND:
3234 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3235 ironlake_crtc_enable(crtc);
3236 break;
1b3c7a47 3237
6be4a607
JB		 3238 case DRM_MODE_DPMS_OFF:
3239 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3240 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3241 break;
3242 }
3243}
3244
02e792fb
DV		 3245static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3246{
02e792fb 3247 if (!enable && intel_crtc->overlay) {
23f09ce3 3248 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3249 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3250
23f09ce3 3251 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3252 dev_priv->mm.interruptible = false;
3253 (void) intel_overlay_switch_off(intel_crtc->overlay);
3254 dev_priv->mm.interruptible = true;
23f09ce3 3255 mutex_unlock(&dev->struct_mutex);
02e792fb 3256 }
02e792fb 3257
5dcdbcb0
CW		 3258 /* Let userspace switch the overlay on again. In most cases userspace
3259 * has to recompute where to put it anyway.
3260 */
02e792fb
DV		 3261}
3262
0b8765c6 3263static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3264{
3265 struct drm_device *dev = crtc->dev;
79e53945
JB		 3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268 int pipe = intel_crtc->pipe;
80824003 3269 int plane = intel_crtc->plane;
79e53945 3270
f7abfe8b
CW		 3271 if (intel_crtc->active)
3272 return;
3273
3274 intel_crtc->active = true;
6b383a7f
CW		 3275 intel_update_watermarks(dev);
3276
63d7bbe9 3277 intel_enable_pll(dev_priv, pipe);
040484af 3278 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3279 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3280
0b8765c6 3281 intel_crtc_load_lut(crtc);
bed4a673 3282 intel_update_fbc(dev);
79e53945 3283
0b8765c6
JB		 3284 /* Give the overlay scaler a chance to enable if it's on this pipe */
3285 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3286 intel_crtc_update_cursor(crtc, true);
0b8765c6 3287}
79e53945 3288
0b8765c6
JB		 3289static void i9xx_crtc_disable(struct drm_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294 int pipe = intel_crtc->pipe;
3295 int plane = intel_crtc->plane;
b690e96c 3296
f7abfe8b
CW		 3297 if (!intel_crtc->active)
3298 return;
3299
0b8765c6 3300 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3301 intel_crtc_wait_for_pending_flips(crtc);
3302 drm_vblank_off(dev, pipe);
0b8765c6 3303 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3304 intel_crtc_update_cursor(crtc, false);
0b8765c6 3305
973d04f9
CW		 3306 if (dev_priv->cfb_plane == plane)
3307 intel_disable_fbc(dev);
79e53945 3308
b24e7179 3309 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3310 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3311 intel_disable_pll(dev_priv, pipe);
0b8765c6 3312
f7abfe8b 3313 intel_crtc->active = false;
6b383a7f
CW		 3314 intel_update_fbc(dev);
3315 intel_update_watermarks(dev);
3316 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3317}
3318
3319static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3320{
3321 /* XXX: When our outputs are all unaware of DPMS modes other than off
3322 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3323 */
3324 switch (mode) {
3325 case DRM_MODE_DPMS_ON:
3326 case DRM_MODE_DPMS_STANDBY:
3327 case DRM_MODE_DPMS_SUSPEND:
3328 i9xx_crtc_enable(crtc);
3329 break;
3330 case DRM_MODE_DPMS_OFF:
3331 i9xx_crtc_disable(crtc);
79e53945
JB		 3332 break;
3333 }
2c07245f
ZW		 3334}
3335
3336/**
3337 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3338 */
3339static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3340{
3341 struct drm_device *dev = crtc->dev;
e70236a8 3342 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3343 struct drm_i915_master_private *master_priv;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 int pipe = intel_crtc->pipe;
3346 bool enabled;
3347
032d2a0d
CW		 3348 if (intel_crtc->dpms_mode == mode)
3349 return;
3350
65655d4a 3351 intel_crtc->dpms_mode = mode;
debcaddc 3352
e70236a8 3353 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3354
3355 if (!dev->primary->master)
3356 return;
3357
3358 master_priv = dev->primary->master->driver_priv;
3359 if (!master_priv->sarea_priv)
3360 return;
3361
3362 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3363
3364 switch (pipe) {
3365 case 0:
3366 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3367 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3368 break;
3369 case 1:
3370 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3371 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3372 break;
3373 default:
9db4a9c7 3374 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3375 break;
3376 }
79e53945
JB		 3377}
3378
cdd59983
CW		 3379static void intel_crtc_disable(struct drm_crtc *crtc)
3380{
3381 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3382 struct drm_device *dev = crtc->dev;
3383
14667a4b
CW		 3384 /* Flush any pending WAITs before we disable the pipe. Note that
3385 * we need to drop the struct_mutex in order to acquire it again
3386 * during the lowlevel dpms routines around a couple of the
3387 * operations. It does not look trivial nor desirable to move
3388 * that locking higher. So instead we leave a window for the
3389 * submission of further commands on the fb before we can actually
3390 * disable it. This race with userspace exists anyway, and we can
3391 * only rely on the pipe being disabled by userspace after it
3392 * receives the hotplug notification and has flushed any pending
3393 * batches.
3394 */
3395 if (crtc->fb) {
3396 mutex_lock(&dev->struct_mutex);
3397 intel_finish_fb(crtc->fb);
3398 mutex_unlock(&dev->struct_mutex);
3399 }
3400
cdd59983 3401 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3402 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3403 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3404
3405 if (crtc->fb) {
3406 mutex_lock(&dev->struct_mutex);
1690e1eb 3407 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3408 mutex_unlock(&dev->struct_mutex);
3409 }
3410}
3411
7e7d76c3
JB		 3412/* Prepare for a mode set.
3413 *
3414 * Note we could be a lot smarter here. We need to figure out which outputs
3415 * will be enabled, which disabled (in short, how the config will changes)
3416 * and perform the minimum necessary steps to accomplish that, e.g. updating
3417 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3418 * panel fitting is in the proper state, etc.
3419 */
3420static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3421{
7e7d76c3 3422 i9xx_crtc_disable(crtc);
79e53945
JB		 3423}
3424
7e7d76c3 3425static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3426{
7e7d76c3 3427 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3428}
3429
3430static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3431{
7e7d76c3 3432 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3433}
3434
3435static void ironlake_crtc_commit(struct drm_crtc *crtc)
3436{
7e7d76c3 3437 ironlake_crtc_enable(crtc);
79e53945
JB		 3438}
3439
0206e353 3440void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3441{
3442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3443 /* lvds has its own version of prepare see intel_lvds_prepare */
3444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3445}
3446
0206e353 3447void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3448{
3449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3450 struct drm_device *dev = encoder->dev;
3451 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3452 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3453
79e53945
JB		 3454 /* lvds has its own version of commit see intel_lvds_commit */
3455 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3456
3457 if (HAS_PCH_CPT(dev))
3458 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3459}
3460
ea5b213a
CW		 3461void intel_encoder_destroy(struct drm_encoder *encoder)
3462{
4ef69c7a 3463 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3464
ea5b213a
CW		 3465 drm_encoder_cleanup(encoder);
3466 kfree(intel_encoder);
3467}
3468
79e53945
JB		 3469static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3470 struct drm_display_mode *mode,
3471 struct drm_display_mode *adjusted_mode)
3472{
2c07245f 3473 struct drm_device *dev = crtc->dev;
89749350 3474
bad720ff 3475 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3476 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3477 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3478 return false;
2c07245f 3479 }
89749350 3480
f9bef081
DV		 3481 /* All interlaced capable intel hw wants timings in frames. Note though
3482 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3483 * timings, so we need to be careful not to clobber these.*/
3484 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3485 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3486
79e53945
JB		 3487 return true;
3488}
3489
e70236a8
JB		 3490static int i945_get_display_clock_speed(struct drm_device *dev)
3491{
3492 return 400000;
3493}
79e53945 3494
e70236a8 3495static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3496{
e70236a8
JB		 3497 return 333000;
3498}
79e53945 3499
e70236a8
JB		 3500static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3501{
3502 return 200000;
3503}
79e53945 3504
e70236a8
JB		 3505static int i915gm_get_display_clock_speed(struct drm_device *dev)
3506{
3507 u16 gcfgc = 0;
79e53945 3508
e70236a8
JB		 3509 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3510
3511 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3512 return 133000;
3513 else {
3514 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3515 case GC_DISPLAY_CLOCK_333_MHZ:
3516 return 333000;
3517 default:
3518 case GC_DISPLAY_CLOCK_190_200_MHZ:
3519 return 190000;
79e53945 3520 }
e70236a8
JB		 3521 }
3522}
3523
3524static int i865_get_display_clock_speed(struct drm_device *dev)
3525{
3526 return 266000;
3527}
3528
3529static int i855_get_display_clock_speed(struct drm_device *dev)
3530{
3531 u16 hpllcc = 0;
3532 /* Assume that the hardware is in the high speed state. This
3533 * should be the default.
3534 */
3535 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3536 case GC_CLOCK_133_200:
3537 case GC_CLOCK_100_200:
3538 return 200000;
3539 case GC_CLOCK_166_250:
3540 return 250000;
3541 case GC_CLOCK_100_133:
79e53945 3542 return 133000;
e70236a8 3543 }
79e53945 3544
e70236a8
JB		 3545 /* Shouldn't happen */
3546 return 0;
3547}
79e53945 3548
e70236a8
JB		 3549static int i830_get_display_clock_speed(struct drm_device *dev)
3550{
3551 return 133000;
79e53945
JB		 3552}
3553
2c07245f
ZW		 3554struct fdi_m_n {
3555 u32 tu;
3556 u32 gmch_m;
3557 u32 gmch_n;
3558 u32 link_m;
3559 u32 link_n;
3560};
3561
3562static void
3563fdi_reduce_ratio(u32 *num, u32 *den)
3564{
3565 while (*num > 0xffffff || *den > 0xffffff) {
3566 *num >>= 1;
3567 *den >>= 1;
3568 }
3569}
3570
2c07245f 3571static void
f2b115e6
AJ		 3572ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3573 int link_clock, struct fdi_m_n *m_n)
2c07245f 3574{
2c07245f
ZW		 3575 m_n->tu = 64; /* default size */
3576
22ed1113
CW		 3577 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3578 m_n->gmch_m = bits_per_pixel * pixel_clock;
3579 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3580 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3581
22ed1113
CW		 3582 m_n->link_m = pixel_clock;
3583 m_n->link_n = link_clock;
2c07245f
ZW		 3584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3585}
3586
3587
7662c8bd
SL		 3588struct intel_watermark_params {
3589 unsigned long fifo_size;
3590 unsigned long max_wm;
3591 unsigned long default_wm;
3592 unsigned long guard_size;
3593 unsigned long cacheline_size;
3594};
3595
f2b115e6 3596/* Pineview has different values for various configs */
d210246a 3597static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3598 PINEVIEW_DISPLAY_FIFO,
3599 PINEVIEW_MAX_WM,
3600 PINEVIEW_DFT_WM,
3601 PINEVIEW_GUARD_WM,
3602 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3603};
d210246a 3604static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3605 PINEVIEW_DISPLAY_FIFO,
3606 PINEVIEW_MAX_WM,
3607 PINEVIEW_DFT_HPLLOFF_WM,
3608 PINEVIEW_GUARD_WM,
3609 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3610};
d210246a 3611static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3612 PINEVIEW_CURSOR_FIFO,
3613 PINEVIEW_CURSOR_MAX_WM,
3614 PINEVIEW_CURSOR_DFT_WM,
3615 PINEVIEW_CURSOR_GUARD_WM,
3616 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3617};
d210246a 3618static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3619 PINEVIEW_CURSOR_FIFO,
3620 PINEVIEW_CURSOR_MAX_WM,
3621 PINEVIEW_CURSOR_DFT_WM,
3622 PINEVIEW_CURSOR_GUARD_WM,
3623 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3624};
d210246a 3625static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3626 G4X_FIFO_SIZE,
3627 G4X_MAX_WM,
3628 G4X_MAX_WM,
3629 2,
3630 G4X_FIFO_LINE_SIZE,
3631};
d210246a 3632static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3633 I965_CURSOR_FIFO,
3634 I965_CURSOR_MAX_WM,
3635 I965_CURSOR_DFT_WM,
3636 2,
3637 G4X_FIFO_LINE_SIZE,
3638};
d210246a 3639static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3640 I965_CURSOR_FIFO,
3641 I965_CURSOR_MAX_WM,
3642 I965_CURSOR_DFT_WM,
3643 2,
3644 I915_FIFO_LINE_SIZE,
3645};
d210246a 3646static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3647 I945_FIFO_SIZE,
7662c8bd
SL		 3648 I915_MAX_WM,
3649 1,
dff33cfc
JB		 3650 2,
3651 I915_FIFO_LINE_SIZE
7662c8bd 3652};
d210246a 3653static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3654 I915_FIFO_SIZE,
7662c8bd
SL		 3655 I915_MAX_WM,
3656 1,
dff33cfc 3657 2,
7662c8bd
SL		 3658 I915_FIFO_LINE_SIZE
3659};
d210246a 3660static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3661 I855GM_FIFO_SIZE,
3662 I915_MAX_WM,
3663 1,
dff33cfc 3664 2,
7662c8bd
SL		 3665 I830_FIFO_LINE_SIZE
3666};
d210246a 3667static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3668 I830_FIFO_SIZE,
3669 I915_MAX_WM,
3670 1,
dff33cfc 3671 2,
7662c8bd
SL		 3672 I830_FIFO_LINE_SIZE
3673};
3674
d210246a 3675static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3676 ILK_DISPLAY_FIFO,
3677 ILK_DISPLAY_MAXWM,
3678 ILK_DISPLAY_DFTWM,
3679 2,
3680 ILK_FIFO_LINE_SIZE
3681};
d210246a 3682static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3683 ILK_CURSOR_FIFO,
3684 ILK_CURSOR_MAXWM,
3685 ILK_CURSOR_DFTWM,
3686 2,
3687 ILK_FIFO_LINE_SIZE
3688};
d210246a 3689static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3690 ILK_DISPLAY_SR_FIFO,
3691 ILK_DISPLAY_MAX_SRWM,
3692 ILK_DISPLAY_DFT_SRWM,
3693 2,
3694 ILK_FIFO_LINE_SIZE
3695};
d210246a 3696static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3697 ILK_CURSOR_SR_FIFO,
3698 ILK_CURSOR_MAX_SRWM,
3699 ILK_CURSOR_DFT_SRWM,
3700 2,
3701 ILK_FIFO_LINE_SIZE
3702};
3703
d210246a 3704static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3705 SNB_DISPLAY_FIFO,
3706 SNB_DISPLAY_MAXWM,
3707 SNB_DISPLAY_DFTWM,
3708 2,
3709 SNB_FIFO_LINE_SIZE
3710};
d210246a 3711static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3712 SNB_CURSOR_FIFO,
3713 SNB_CURSOR_MAXWM,
3714 SNB_CURSOR_DFTWM,
3715 2,
3716 SNB_FIFO_LINE_SIZE
3717};
d210246a 3718static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3719 SNB_DISPLAY_SR_FIFO,
3720 SNB_DISPLAY_MAX_SRWM,
3721 SNB_DISPLAY_DFT_SRWM,
3722 2,
3723 SNB_FIFO_LINE_SIZE
3724};
d210246a 3725static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3726 SNB_CURSOR_SR_FIFO,
3727 SNB_CURSOR_MAX_SRWM,
3728 SNB_CURSOR_DFT_SRWM,
3729 2,
3730 SNB_FIFO_LINE_SIZE
3731};
3732
3733
dff33cfc
JB		 3734/**
3735 * intel_calculate_wm - calculate watermark level
3736 * @clock_in_khz: pixel clock
3737 * @wm: chip FIFO params
3738 * @pixel_size: display pixel size
3739 * @latency_ns: memory latency for the platform
3740 *
3741 * Calculate the watermark level (the level at which the display plane will
3742 * start fetching from memory again). Each chip has a different display
3743 * FIFO size and allocation, so the caller needs to figure that out and pass
3744 * in the correct intel_watermark_params structure.
3745 *
3746 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3747 * on the pixel size. When it reaches the watermark level, it'll start
3748 * fetching FIFO line sized based chunks from memory until the FIFO fills
3749 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3750 * will occur, and a display engine hang could result.
3751 */
7662c8bd 3752static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3753 const struct intel_watermark_params *wm,
3754 int fifo_size,
7662c8bd
SL		 3755 int pixel_size,
3756 unsigned long latency_ns)
3757{
390c4dd4 3758 long entries_required, wm_size;
dff33cfc 3759
d660467c
JB		 3760 /*
3761 * Note: we need to make sure we don't overflow for various clock &
3762 * latency values.
3763 * clocks go from a few thousand to several hundred thousand.
3764 * latency is usually a few thousand
3765 */
3766 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3767 1000;
8de9b311 3768 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3769
bbb0aef5 3770 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3771
d210246a 3772 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3773
bbb0aef5 3774 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3775
390c4dd4
JB		 3776 /* Don't promote wm_size to unsigned... */
3777 if (wm_size > (long)wm->max_wm)
7662c8bd 3778 wm_size = wm->max_wm;
c3add4b6 3779 if (wm_size <= 0)
7662c8bd
SL		 3780 wm_size = wm->default_wm;
3781 return wm_size;
3782}
3783
3784struct cxsr_latency {
3785 int is_desktop;
95534263 3786 int is_ddr3;
7662c8bd
SL		 3787 unsigned long fsb_freq;
3788 unsigned long mem_freq;
3789 unsigned long display_sr;
3790 unsigned long display_hpll_disable;
3791 unsigned long cursor_sr;
3792 unsigned long cursor_hpll_disable;
3793};
3794
403c89ff 3795static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3796 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3797 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3798 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3799 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3800 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3801
3802 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3803 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3804 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3805 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3806 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3807
3808 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3809 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3810 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3811 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3812 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3813
3814 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3815 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3816 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3817 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3818 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3819
3820 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3821 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3822 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3823 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3824 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3825
3826 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3827 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3828 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3829 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3830 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3831};
3832
403c89ff
CW		 3833static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3834 int is_ddr3,
3835 int fsb,
3836 int mem)
7662c8bd 3837{
403c89ff 3838 const struct cxsr_latency *latency;
7662c8bd 3839 int i;
7662c8bd
SL		 3840
3841 if (fsb == 0 || mem == 0)
3842 return NULL;
3843
3844 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3845 latency = &cxsr_latency_table[i];
3846 if (is_desktop == latency->is_desktop &&
95534263 3847 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3848 fsb == latency->fsb_freq && mem == latency->mem_freq)
3849 return latency;
7662c8bd 3850 }
decbbcda 3851
28c97730 3852 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3853
3854 return NULL;
7662c8bd
SL		 3855}
3856
f2b115e6 3857static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3858{
3859 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3860
3861 /* deactivate cxsr */
3e33d94d 3862 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3863}
3864
bcc24fb4
JB		 3865/*
3866 * Latency for FIFO fetches is dependent on several factors:
3867 * - memory configuration (speed, channels)
3868 * - chipset
3869 * - current MCH state
3870 * It can be fairly high in some situations, so here we assume a fairly
3871 * pessimal value. It's a tradeoff between extra memory fetches (if we
3872 * set this value too high, the FIFO will fetch frequently to stay full)
3873 * and power consumption (set it too low to save power and we might see
3874 * FIFO underruns and display "flicker").
3875 *
3876 * A value of 5us seems to be a good balance; safe for very low end
3877 * platforms but not overly aggressive on lower latency configs.
3878 */
69e302a9 3879static const int latency_ns = 5000;
7662c8bd 3880
e70236a8 3881static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3882{
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 uint32_t dsparb = I915_READ(DSPARB);
3885 int size;
3886
8de9b311
CW		 3887 size = dsparb & 0x7f;
3888 if (plane)
3889 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3890
28c97730 3891 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3892 plane ? "B" : "A", size);
dff33cfc
JB		 3893
3894 return size;
3895}
7662c8bd 3896
e70236a8
JB		 3897static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3898{
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 uint32_t dsparb = I915_READ(DSPARB);
3901 int size;
3902
8de9b311
CW		 3903 size = dsparb & 0x1ff;
3904 if (plane)
3905 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3906 size >>= 1; /* Convert to cachelines */
dff33cfc 3907
28c97730 3908 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3909 plane ? "B" : "A", size);
dff33cfc
JB		 3910
3911 return size;
3912}
7662c8bd 3913
e70236a8
JB		 3914static int i845_get_fifo_size(struct drm_device *dev, int plane)
3915{
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 uint32_t dsparb = I915_READ(DSPARB);
3918 int size;
3919
3920 size = dsparb & 0x7f;
3921 size >>= 2; /* Convert to cachelines */
3922
28c97730 3923 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3924 plane ? "B" : "A",
3925 size);
e70236a8
JB		 3926
3927 return size;
3928}
3929
3930static int i830_get_fifo_size(struct drm_device *dev, int plane)
3931{
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 uint32_t dsparb = I915_READ(DSPARB);
3934 int size;
3935
3936 size = dsparb & 0x7f;
3937 size >>= 1; /* Convert to cachelines */
3938
28c97730 3939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3940 plane ? "B" : "A", size);
e70236a8
JB		 3941
3942 return size;
3943}
3944
d210246a
CW		 3945static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3946{
3947 struct drm_crtc *crtc, *enabled = NULL;
3948
3949 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3950 if (crtc->enabled && crtc->fb) {
3951 if (enabled)
3952 return NULL;
3953 enabled = crtc;
3954 }
3955 }
3956
3957 return enabled;
3958}
3959
3960static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3963 struct drm_crtc *crtc;
403c89ff 3964 const struct cxsr_latency *latency;
d4294342
ZY		 3965 u32 reg;
3966 unsigned long wm;
d4294342 3967
403c89ff 3968 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3969 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3970 if (!latency) {
3971 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3972 pineview_disable_cxsr(dev);
3973 return;
3974 }
3975
d210246a
CW		 3976 crtc = single_enabled_crtc(dev);
3977 if (crtc) {
3978 int clock = crtc->mode.clock;
3979 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3980
3981 /* Display SR */
d210246a
CW		 3982 wm = intel_calculate_wm(clock, &pineview_display_wm,
3983 pineview_display_wm.fifo_size,
d4294342
ZY		 3984 pixel_size, latency->display_sr);
3985 reg = I915_READ(DSPFW1);
3986 reg &= ~DSPFW_SR_MASK;
3987 reg |= wm << DSPFW_SR_SHIFT;
3988 I915_WRITE(DSPFW1, reg);
3989 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3990
3991 /* cursor SR */
d210246a
CW		 3992 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3993 pineview_display_wm.fifo_size,
d4294342
ZY		 3994 pixel_size, latency->cursor_sr);
3995 reg = I915_READ(DSPFW3);
3996 reg &= ~DSPFW_CURSOR_SR_MASK;
3997 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3998 I915_WRITE(DSPFW3, reg);
3999
4000 /* Display HPLL off SR */
d210246a
CW		 4001 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4002 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 4003 pixel_size, latency->display_hpll_disable);
4004 reg = I915_READ(DSPFW3);
4005 reg &= ~DSPFW_HPLL_SR_MASK;
4006 reg |= wm & DSPFW_HPLL_SR_MASK;
4007 I915_WRITE(DSPFW3, reg);
4008
4009 /* cursor HPLL off SR */
d210246a
CW		 4010 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4011 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 4012 pixel_size, latency->cursor_hpll_disable);
4013 reg = I915_READ(DSPFW3);
4014 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4015 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4016 I915_WRITE(DSPFW3, reg);
4017 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4018
4019 /* activate cxsr */
3e33d94d
CW		 4020 I915_WRITE(DSPFW3,
4021 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 4022 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4023 } else {
4024 pineview_disable_cxsr(dev);
4025 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4026 }
4027}
4028
417ae147
CW		 4029static bool g4x_compute_wm0(struct drm_device *dev,
4030 int plane,
4031 const struct intel_watermark_params *display,
4032 int display_latency_ns,
4033 const struct intel_watermark_params *cursor,
4034 int cursor_latency_ns,
4035 int *plane_wm,
4036 int *cursor_wm)
4037{
4038 struct drm_crtc *crtc;
4039 int htotal, hdisplay, clock, pixel_size;
4040 int line_time_us, line_count;
4041 int entries, tlb_miss;
4042
4043 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4044 if (crtc->fb == NULL || !crtc->enabled) {
4045 *cursor_wm = cursor->guard_size;
4046 *plane_wm = display->guard_size;
417ae147 4047 return false;
5c72d064 4048 }
417ae147
CW		 4049
4050 htotal = crtc->mode.htotal;
4051 hdisplay = crtc->mode.hdisplay;
4052 clock = crtc->mode.clock;
4053 pixel_size = crtc->fb->bits_per_pixel / 8;
4054
4055 /* Use the small buffer method to calculate plane watermark */
4056 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4057 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4058 if (tlb_miss > 0)
4059 entries += tlb_miss;
4060 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4061 *plane_wm = entries + display->guard_size;
4062 if (*plane_wm > (int)display->max_wm)
4063 *plane_wm = display->max_wm;
4064
4065 /* Use the large buffer method to calculate cursor watermark */
4066 line_time_us = ((htotal * 1000) / clock);
4067 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4068 entries = line_count * 64 * pixel_size;
4069 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4070 if (tlb_miss > 0)
4071 entries += tlb_miss;
4072 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4073 *cursor_wm = entries + cursor->guard_size;
4074 if (*cursor_wm > (int)cursor->max_wm)
4075 *cursor_wm = (int)cursor->max_wm;
4076
4077 return true;
4078}
4079
4080/*
4081 * Check the wm result.
4082 *
4083 * If any calculated watermark values is larger than the maximum value that
4084 * can be programmed into the associated watermark register, that watermark
4085 * must be disabled.
4086 */
4087static bool g4x_check_srwm(struct drm_device *dev,
4088 int display_wm, int cursor_wm,
4089 const struct intel_watermark_params *display,
4090 const struct intel_watermark_params *cursor)
652c393a 4091{
417ae147
CW		 4092 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4093 display_wm, cursor_wm);
652c393a 4094
417ae147 4095 if (display_wm > display->max_wm) {
bbb0aef5 4096 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4097 display_wm, display->max_wm);
4098 return false;
4099 }
0e442c60 4100
417ae147 4101 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4102 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4103 cursor_wm, cursor->max_wm);
4104 return false;
4105 }
0e442c60 4106
417ae147
CW		 4107 if (!(display_wm || cursor_wm)) {
4108 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4109 return false;
4110 }
0e442c60 4111
417ae147
CW		 4112 return true;
4113}
0e442c60 4114
417ae147 4115static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4116 int plane,
4117 int latency_ns,
417ae147
CW		 4118 const struct intel_watermark_params *display,
4119 const struct intel_watermark_params *cursor,
4120 int *display_wm, int *cursor_wm)
4121{
d210246a
CW		 4122 struct drm_crtc *crtc;
4123 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4124 unsigned long line_time_us;
4125 int line_count, line_size;
4126 int small, large;
4127 int entries;
0e442c60 4128
417ae147
CW		 4129 if (!latency_ns) {
4130 *display_wm = *cursor_wm = 0;
4131 return false;
4132 }
0e442c60 4133
d210246a
CW		 4134 crtc = intel_get_crtc_for_plane(dev, plane);
4135 hdisplay = crtc->mode.hdisplay;
4136 htotal = crtc->mode.htotal;
4137 clock = crtc->mode.clock;
4138 pixel_size = crtc->fb->bits_per_pixel / 8;
4139
417ae147
CW		 4140 line_time_us = (htotal * 1000) / clock;
4141 line_count = (latency_ns / line_time_us + 1000) / 1000;
4142 line_size = hdisplay * pixel_size;
0e442c60 4143
417ae147
CW		 4144 /* Use the minimum of the small and large buffer method for primary */
4145 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4146 large = line_count * line_size;
0e442c60 4147
417ae147
CW		 4148 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4149 *display_wm = entries + display->guard_size;
4fe5e611 4150
417ae147
CW		 4151 /* calculate the self-refresh watermark for display cursor */
4152 entries = line_count * pixel_size * 64;
4153 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4154 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4155
417ae147
CW		 4156 return g4x_check_srwm(dev,
4157 *display_wm, *cursor_wm,
4158 display, cursor);
4159}
4fe5e611 4160
7ccb4a53 4161#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4162
4163static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4164{
4165 static const int sr_latency_ns = 12000;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4168 int plane_sr, cursor_sr;
4169 unsigned int enabled = 0;
417ae147
CW		 4170
4171 if (g4x_compute_wm0(dev, 0,
4172 &g4x_wm_info, latency_ns,
4173 &g4x_cursor_wm_info, latency_ns,
4174 &planea_wm, &cursora_wm))
d210246a 4175 enabled |= 1;
417ae147
CW		 4176
4177 if (g4x_compute_wm0(dev, 1,
4178 &g4x_wm_info, latency_ns,
4179 &g4x_cursor_wm_info, latency_ns,
4180 &planeb_wm, &cursorb_wm))
d210246a 4181 enabled |= 2;
417ae147
CW		 4182
4183 plane_sr = cursor_sr = 0;
d210246a
CW		 4184 if (single_plane_enabled(enabled) &&
4185 g4x_compute_srwm(dev, ffs(enabled) - 1,
4186 sr_latency_ns,
417ae147
CW		 4187 &g4x_wm_info,
4188 &g4x_cursor_wm_info,
4189 &plane_sr, &cursor_sr))
0e442c60 4190 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4191 else
4192 I915_WRITE(FW_BLC_SELF,
4193 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4194
308977ac
CW		 4195 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4196 planea_wm, cursora_wm,
4197 planeb_wm, cursorb_wm,
4198 plane_sr, cursor_sr);
0e442c60 4199
417ae147
CW		 4200 I915_WRITE(DSPFW1,
4201 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4202 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4203 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4204 planea_wm);
4205 I915_WRITE(DSPFW2,
4206 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4207 (cursora_wm << DSPFW_CURSORA_SHIFT));
4208 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4209 I915_WRITE(DSPFW3,
4210 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4211 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4212}
4213
d210246a 4214static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4215{
4216 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4217 struct drm_crtc *crtc;
4218 int srwm = 1;
4fe5e611 4219 int cursor_sr = 16;
1dc7546d
JB		 4220
4221 /* Calc sr entries for one plane configs */
d210246a
CW		 4222 crtc = single_enabled_crtc(dev);
4223 if (crtc) {
1dc7546d 4224 /* self-refresh has much higher latency */
69e302a9 4225 static const int sr_latency_ns = 12000;
d210246a
CW		 4226 int clock = crtc->mode.clock;
4227 int htotal = crtc->mode.htotal;
4228 int hdisplay = crtc->mode.hdisplay;
4229 int pixel_size = crtc->fb->bits_per_pixel / 8;
4230 unsigned long line_time_us;
4231 int entries;
1dc7546d 4232
d210246a 4233 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4234
4235 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4236 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4237 pixel_size * hdisplay;
4238 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4239 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4240 if (srwm < 0)
4241 srwm = 1;
1b07e04e 4242 srwm &= 0x1ff;
308977ac
CW		 4243 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4244 entries, srwm);
4fe5e611 4245
d210246a 4246 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4247 pixel_size * 64;
d210246a 4248 entries = DIV_ROUND_UP(entries,
8de9b311 4249 i965_cursor_wm_info.cacheline_size);
4fe5e611 4250 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4251 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4252
4253 if (cursor_sr > i965_cursor_wm_info.max_wm)
4254 cursor_sr = i965_cursor_wm_info.max_wm;
4255
4256 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4257 "cursor %d\n", srwm, cursor_sr);
4258
a6c45cf0 4259 if (IS_CRESTLINE(dev))
adcdbc66 4260 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4261 } else {
4262 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4263 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4264 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4265 & ~FW_BLC_SELF_EN);
1dc7546d 4266 }
7662c8bd 4267
1dc7546d
JB		 4268 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4269 srwm);
7662c8bd
SL		 4270
4271 /* 965 has limitations... */
417ae147
CW		 4272 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4273 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4274 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4275 /* update cursor SR watermark */
4276 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4277}
4278
d210246a 4279static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4280{
4281 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4282 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4283 uint32_t fwater_lo;
4284 uint32_t fwater_hi;
d210246a
CW		 4285 int cwm, srwm = 1;
4286 int fifo_size;
dff33cfc 4287 int planea_wm, planeb_wm;
d210246a 4288 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4289
72557b4f 4290 if (IS_I945GM(dev))
d210246a 4291 wm_info = &i945_wm_info;
a6c45cf0 4292 else if (!IS_GEN2(dev))
d210246a 4293 wm_info = &i915_wm_info;
7662c8bd 4294 else
d210246a
CW		 4295 wm_info = &i855_wm_info;
4296
4297 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4298 crtc = intel_get_crtc_for_plane(dev, 0);
4299 if (crtc->enabled && crtc->fb) {
4300 planea_wm = intel_calculate_wm(crtc->mode.clock,
4301 wm_info, fifo_size,
4302 crtc->fb->bits_per_pixel / 8,
4303 latency_ns);
4304 enabled = crtc;
4305 } else
4306 planea_wm = fifo_size - wm_info->guard_size;
4307
4308 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4309 crtc = intel_get_crtc_for_plane(dev, 1);
4310 if (crtc->enabled && crtc->fb) {
4311 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4312 wm_info, fifo_size,
4313 crtc->fb->bits_per_pixel / 8,
4314 latency_ns);
4315 if (enabled == NULL)
4316 enabled = crtc;
4317 else
4318 enabled = NULL;
4319 } else
4320 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4321
28c97730 4322 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4323
4324 /*
4325 * Overlay gets an aggressive default since video jitter is bad.
4326 */
4327 cwm = 2;
4328
18b2190c
AL		 4329 /* Play safe and disable self-refresh before adjusting watermarks. */
4330 if (IS_I945G(dev) || IS_I945GM(dev))
4331 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4332 else if (IS_I915GM(dev))
4333 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4334
dff33cfc 4335 /* Calc sr entries for one plane configs */
d210246a 4336 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4337 /* self-refresh has much higher latency */
69e302a9 4338 static const int sr_latency_ns = 6000;
d210246a
CW		 4339 int clock = enabled->mode.clock;
4340 int htotal = enabled->mode.htotal;
4341 int hdisplay = enabled->mode.hdisplay;
4342 int pixel_size = enabled->fb->bits_per_pixel / 8;
4343 unsigned long line_time_us;
4344 int entries;
dff33cfc 4345
d210246a 4346 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4347
4348 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4349 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4350 pixel_size * hdisplay;
4351 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4352 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4353 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4354 if (srwm < 0)
4355 srwm = 1;
ee980b80
LP		 4356
4357 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4358 I915_WRITE(FW_BLC_SELF,
4359 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4360 else if (IS_I915GM(dev))
ee980b80 4361 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4362 }
4363
28c97730 4364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4365 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4366
dff33cfc
JB		 4367 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4368 fwater_hi = (cwm & 0x1f);
4369
4370 /* Set request length to 8 cachelines per fetch */
4371 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4372 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4373
4374 I915_WRITE(FW_BLC, fwater_lo);
4375 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4376
d210246a
CW		 4377 if (HAS_FW_BLC(dev)) {
4378 if (enabled) {
4379 if (IS_I945G(dev) || IS_I945GM(dev))
4380 I915_WRITE(FW_BLC_SELF,
4381 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4382 else if (IS_I915GM(dev))
4383 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4384 DRM_DEBUG_KMS("memory self refresh enabled\n");
4385 } else
4386 DRM_DEBUG_KMS("memory self refresh disabled\n");
4387 }
7662c8bd
SL		 4388}
4389
d210246a 4390static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4391{
4392 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4393 struct drm_crtc *crtc;
4394 uint32_t fwater_lo;
dff33cfc 4395 int planea_wm;
7662c8bd 4396
d210246a
CW		 4397 crtc = single_enabled_crtc(dev);
4398 if (crtc == NULL)
4399 return;
7662c8bd 4400
d210246a
CW		 4401 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4402 dev_priv->display.get_fifo_size(dev, 0),
4403 crtc->fb->bits_per_pixel / 8,
4404 latency_ns);
4405 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4406 fwater_lo |= (3<<8) | planea_wm;
4407
28c97730 4408 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4409
4410 I915_WRITE(FW_BLC, fwater_lo);
4411}
4412
7f8a8569 4413#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4414#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4415
1398261a
YL		 4416/*
4417 * Check the wm result.
4418 *
4419 * If any calculated watermark values is larger than the maximum value that
4420 * can be programmed into the associated watermark register, that watermark
4421 * must be disabled.
1398261a 4422 */
b79d4990
JB		 4423static bool ironlake_check_srwm(struct drm_device *dev, int level,
4424 int fbc_wm, int display_wm, int cursor_wm,
4425 const struct intel_watermark_params *display,
4426 const struct intel_watermark_params *cursor)
1398261a
YL		 4427{
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429
4430 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4431 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4432
4433 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4434 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4435 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4436
4437 /* fbc has it's own way to disable FBC WM */
4438 I915_WRITE(DISP_ARB_CTL,
4439 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4440 return false;
4441 }
4442
b79d4990 4443 if (display_wm > display->max_wm) {
1398261a 4444 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4445 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4446 return false;
4447 }
4448
b79d4990 4449 if (cursor_wm > cursor->max_wm) {
1398261a 4450 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4451 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4452 return false;
4453 }
4454
4455 if (!(fbc_wm || display_wm || cursor_wm)) {
4456 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4457 return false;
4458 }
4459
4460 return true;
4461}
4462
4463/*
4464 * Compute watermark values of WM[1-3],
4465 */
d210246a
CW		 4466static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4467 int latency_ns,
b79d4990
JB		 4468 const struct intel_watermark_params *display,
4469 const struct intel_watermark_params *cursor,
4470 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4471{
d210246a 4472 struct drm_crtc *crtc;
1398261a 4473 unsigned long line_time_us;
d210246a 4474 int hdisplay, htotal, pixel_size, clock;
b79d4990 4475 int line_count, line_size;
1398261a
YL		 4476 int small, large;
4477 int entries;
1398261a
YL		 4478
4479 if (!latency_ns) {
4480 *fbc_wm = *display_wm = *cursor_wm = 0;
4481 return false;
4482 }
4483
d210246a
CW		 4484 crtc = intel_get_crtc_for_plane(dev, plane);
4485 hdisplay = crtc->mode.hdisplay;
4486 htotal = crtc->mode.htotal;
4487 clock = crtc->mode.clock;
4488 pixel_size = crtc->fb->bits_per_pixel / 8;
4489
1398261a
YL		 4490 line_time_us = (htotal * 1000) / clock;
4491 line_count = (latency_ns / line_time_us + 1000) / 1000;
4492 line_size = hdisplay * pixel_size;
4493
4494 /* Use the minimum of the small and large buffer method for primary */
4495 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4496 large = line_count * line_size;
4497
b79d4990
JB		 4498 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4499 *display_wm = entries + display->guard_size;
1398261a
YL		 4500
4501 /*
b79d4990 4502 * Spec says:
1398261a
YL		 4503 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4504 */
4505 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4506
4507 /* calculate the self-refresh watermark for display cursor */
4508 entries = line_count * pixel_size * 64;
b79d4990
JB		 4509 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4510 *cursor_wm = entries + cursor->guard_size;
1398261a 4511
b79d4990
JB		 4512 return ironlake_check_srwm(dev, level,
4513 *fbc_wm, *display_wm, *cursor_wm,
4514 display, cursor);
4515}
4516
d210246a 4517static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4518{
4519 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4520 int fbc_wm, plane_wm, cursor_wm;
4521 unsigned int enabled;
b79d4990
JB		 4522
4523 enabled = 0;
9f405100
CW		 4524 if (g4x_compute_wm0(dev, 0,
4525 &ironlake_display_wm_info,
4526 ILK_LP0_PLANE_LATENCY,
4527 &ironlake_cursor_wm_info,
4528 ILK_LP0_CURSOR_LATENCY,
4529 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4530 I915_WRITE(WM0_PIPEA_ILK,
4531 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4532 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4533 " plane %d, " "cursor: %d\n",
4534 plane_wm, cursor_wm);
d210246a 4535 enabled |= 1;
b79d4990
JB		 4536 }
4537
9f405100
CW		 4538 if (g4x_compute_wm0(dev, 1,
4539 &ironlake_display_wm_info,
4540 ILK_LP0_PLANE_LATENCY,
4541 &ironlake_cursor_wm_info,
4542 ILK_LP0_CURSOR_LATENCY,
4543 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
d210246a 4549 enabled |= 2;
b79d4990
JB		 4550 }
4551
4552 /*
4553 * Calculate and update the self-refresh watermark only when one
4554 * display plane is used.
4555 */
4556 I915_WRITE(WM3_LP_ILK, 0);
4557 I915_WRITE(WM2_LP_ILK, 0);
4558 I915_WRITE(WM1_LP_ILK, 0);
4559
d210246a 4560 if (!single_plane_enabled(enabled))
b79d4990 4561 return;
d210246a 4562 enabled = ffs(enabled) - 1;
b79d4990
JB		 4563
4564 /* WM1 */
d210246a
CW		 4565 if (!ironlake_compute_srwm(dev, 1, enabled,
4566 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4567 &ironlake_display_srwm_info,
4568 &ironlake_cursor_srwm_info,
4569 &fbc_wm, &plane_wm, &cursor_wm))
4570 return;
4571
4572 I915_WRITE(WM1_LP_ILK,
4573 WM1_LP_SR_EN |
4574 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4575 (fbc_wm << WM1_LP_FBC_SHIFT) |
4576 (plane_wm << WM1_LP_SR_SHIFT) |
4577 cursor_wm);
4578
4579 /* WM2 */
d210246a
CW		 4580 if (!ironlake_compute_srwm(dev, 2, enabled,
4581 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4582 &ironlake_display_srwm_info,
4583 &ironlake_cursor_srwm_info,
4584 &fbc_wm, &plane_wm, &cursor_wm))
4585 return;
4586
4587 I915_WRITE(WM2_LP_ILK,
4588 WM2_LP_EN |
4589 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4590 (fbc_wm << WM1_LP_FBC_SHIFT) |
4591 (plane_wm << WM1_LP_SR_SHIFT) |
4592 cursor_wm);
4593
4594 /*
4595 * WM3 is unsupported on ILK, probably because we don't have latency
4596 * data for that power state
4597 */
1398261a
YL		 4598}
4599
b840d907 4600void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4601{
4602 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4603 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4604 u32 val;
d210246a
CW		 4605 int fbc_wm, plane_wm, cursor_wm;
4606 unsigned int enabled;
1398261a
YL		 4607
4608 enabled = 0;
9f405100
CW		 4609 if (g4x_compute_wm0(dev, 0,
4610 &sandybridge_display_wm_info, latency,
4611 &sandybridge_cursor_wm_info, latency,
4612 &plane_wm, &cursor_wm)) {
47842649
JB		 4613 val = I915_READ(WM0_PIPEA_ILK);
4614 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615 I915_WRITE(WM0_PIPEA_ILK, val |
4616 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4617 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4618 " plane %d, " "cursor: %d\n",
4619 plane_wm, cursor_wm);
d210246a 4620 enabled |= 1;
1398261a
YL		 4621 }
4622
9f405100
CW		 4623 if (g4x_compute_wm0(dev, 1,
4624 &sandybridge_display_wm_info, latency,
4625 &sandybridge_cursor_wm_info, latency,
4626 &plane_wm, &cursor_wm)) {
47842649
JB		 4627 val = I915_READ(WM0_PIPEB_ILK);
4628 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4629 I915_WRITE(WM0_PIPEB_ILK, val |
4630 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4631 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4632 " plane %d, cursor: %d\n",
4633 plane_wm, cursor_wm);
d210246a 4634 enabled |= 2;
1398261a
YL		 4635 }
4636
d6c892df
JB		 4637 /* IVB has 3 pipes */
4638 if (IS_IVYBRIDGE(dev) &&
4639 g4x_compute_wm0(dev, 2,
4640 &sandybridge_display_wm_info, latency,
4641 &sandybridge_cursor_wm_info, latency,
4642 &plane_wm, &cursor_wm)) {
47842649
JB		 4643 val = I915_READ(WM0_PIPEC_IVB);
4644 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4645 I915_WRITE(WM0_PIPEC_IVB, val |
4646 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4647 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4648 " plane %d, cursor: %d\n",
4649 plane_wm, cursor_wm);
4650 enabled |= 3;
4651 }
4652
1398261a
YL		 4653 /*
4654 * Calculate and update the self-refresh watermark only when one
4655 * display plane is used.
4656 *
4657 * SNB support 3 levels of watermark.
4658 *
4659 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4660 * and disabled in the descending order
4661 *
4662 */
4663 I915_WRITE(WM3_LP_ILK, 0);
4664 I915_WRITE(WM2_LP_ILK, 0);
4665 I915_WRITE(WM1_LP_ILK, 0);
4666
b840d907
JB		 4667 if (!single_plane_enabled(enabled) ||
4668 dev_priv->sprite_scaling_enabled)
1398261a 4669 return;
d210246a 4670 enabled = ffs(enabled) - 1;
1398261a
YL		 4671
4672 /* WM1 */
d210246a
CW		 4673 if (!ironlake_compute_srwm(dev, 1, enabled,
4674 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4675 &sandybridge_display_srwm_info,
4676 &sandybridge_cursor_srwm_info,
4677 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4678 return;
4679
4680 I915_WRITE(WM1_LP_ILK,
4681 WM1_LP_SR_EN |
4682 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683 (fbc_wm << WM1_LP_FBC_SHIFT) |
4684 (plane_wm << WM1_LP_SR_SHIFT) |
4685 cursor_wm);
4686
4687 /* WM2 */
d210246a
CW		 4688 if (!ironlake_compute_srwm(dev, 2, enabled,
4689 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4690 &sandybridge_display_srwm_info,
4691 &sandybridge_cursor_srwm_info,
4692 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4693 return;
4694
4695 I915_WRITE(WM2_LP_ILK,
4696 WM2_LP_EN |
4697 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4698 (fbc_wm << WM1_LP_FBC_SHIFT) |
4699 (plane_wm << WM1_LP_SR_SHIFT) |
4700 cursor_wm);
4701
4702 /* WM3 */
d210246a
CW		 4703 if (!ironlake_compute_srwm(dev, 3, enabled,
4704 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4705 &sandybridge_display_srwm_info,
4706 &sandybridge_cursor_srwm_info,
4707 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4708 return;
4709
4710 I915_WRITE(WM3_LP_ILK,
4711 WM3_LP_EN |
4712 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4713 (fbc_wm << WM1_LP_FBC_SHIFT) |
4714 (plane_wm << WM1_LP_SR_SHIFT) |
4715 cursor_wm);
4716}
4717
b840d907
JB		 4718static bool
4719sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4720 uint32_t sprite_width, int pixel_size,
4721 const struct intel_watermark_params *display,
4722 int display_latency_ns, int *sprite_wm)
4723{
4724 struct drm_crtc *crtc;
4725 int clock;
4726 int entries, tlb_miss;
4727
4728 crtc = intel_get_crtc_for_plane(dev, plane);
4729 if (crtc->fb == NULL || !crtc->enabled) {
4730 *sprite_wm = display->guard_size;
4731 return false;
4732 }
4733
4734 clock = crtc->mode.clock;
4735
4736 /* Use the small buffer method to calculate the sprite watermark */
4737 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4738 tlb_miss = display->fifo_size*display->cacheline_size -
4739 sprite_width * 8;
4740 if (tlb_miss > 0)
4741 entries += tlb_miss;
4742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4743 *sprite_wm = entries + display->guard_size;
4744 if (*sprite_wm > (int)display->max_wm)
4745 *sprite_wm = display->max_wm;
4746
4747 return true;
4748}
4749
4750static bool
4751sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4752 uint32_t sprite_width, int pixel_size,
4753 const struct intel_watermark_params *display,
4754 int latency_ns, int *sprite_wm)
4755{
4756 struct drm_crtc *crtc;
4757 unsigned long line_time_us;
4758 int clock;
4759 int line_count, line_size;
4760 int small, large;
4761 int entries;
4762
4763 if (!latency_ns) {
4764 *sprite_wm = 0;
4765 return false;
4766 }
4767
4768 crtc = intel_get_crtc_for_plane(dev, plane);
4769 clock = crtc->mode.clock;
4e9bb47b
HL		 4770 if (!clock) {
4771 *sprite_wm = 0;
4772 return false;
4773 }
b840d907
JB		 4774
4775 line_time_us = (sprite_width * 1000) / clock;
4e9bb47b
HL		 4776 if (!line_time_us) {
4777 *sprite_wm = 0;
4778 return false;
4779 }
4780
b840d907
JB		 4781 line_count = (latency_ns / line_time_us + 1000) / 1000;
4782 line_size = sprite_width * pixel_size;
4783
4784 /* Use the minimum of the small and large buffer method for primary */
4785 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4786 large = line_count * line_size;
4787
4788 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4789 *sprite_wm = entries + display->guard_size;
4790
4791 return *sprite_wm > 0x3ff ? false : true;
4792}
4793
4794static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4795 uint32_t sprite_width, int pixel_size)
4796{
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4799 u32 val;
b840d907
JB		 4800 int sprite_wm, reg;
4801 int ret;
4802
4803 switch (pipe) {
4804 case 0:
4805 reg = WM0_PIPEA_ILK;
4806 break;
4807 case 1:
4808 reg = WM0_PIPEB_ILK;
4809 break;
4810 case 2:
4811 reg = WM0_PIPEC_IVB;
4812 break;
4813 default:
4814 return; /* bad pipe */
4815 }
4816
4817 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4818 &sandybridge_display_wm_info,
4819 latency, &sprite_wm);
4820 if (!ret) {
4821 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4822 pipe);
4823 return;
4824 }
4825
47842649
JB		 4826 val = I915_READ(reg);
4827 val &= ~WM0_PIPE_SPRITE_MASK;
4828 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4829 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4830
4831
4832 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4833 pixel_size,
4834 &sandybridge_display_srwm_info,
4835 SNB_READ_WM1_LATENCY() * 500,
4836 &sprite_wm);
4837 if (!ret) {
4838 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4839 pipe);
4840 return;
4841 }
4842 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4843
4844 /* Only IVB has two more LP watermarks for sprite */
4845 if (!IS_IVYBRIDGE(dev))
4846 return;
4847
4848 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4849 pixel_size,
4850 &sandybridge_display_srwm_info,
4851 SNB_READ_WM2_LATENCY() * 500,
4852 &sprite_wm);
4853 if (!ret) {
4854 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4855 pipe);
4856 return;
4857 }
4858 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4859
4860 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4861 pixel_size,
4862 &sandybridge_display_srwm_info,
4863 SNB_READ_WM3_LATENCY() * 500,
4864 &sprite_wm);
4865 if (!ret) {
4866 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4867 pipe);
4868 return;
4869 }
4870 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4871}
4872
7662c8bd
SL		 4873/**
4874 * intel_update_watermarks - update FIFO watermark values based on current modes
4875 *
4876 * Calculate watermark values for the various WM regs based on current mode
4877 * and plane configuration.
4878 *
4879 * There are several cases to deal with here:
4880 * - normal (i.e. non-self-refresh)
4881 * - self-refresh (SR) mode
4882 * - lines are large relative to FIFO size (buffer can hold up to 2)
4883 * - lines are small relative to FIFO size (buffer can hold more than 2
4884 * lines), so need to account for TLB latency
4885 *
4886 * The normal calculation is:
4887 * watermark = dotclock * bytes per pixel * latency
4888 * where latency is platform & configuration dependent (we assume pessimal
4889 * values here).
4890 *
4891 * The SR calculation is:
4892 * watermark = (trunc(latency/line time)+1) * surface width *
4893 * bytes per pixel
4894 * where
4895 * line time = htotal / dotclock
fa143215 4896 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4897 * and latency is assumed to be high, as above.
4898 *
4899 * The final value programmed to the register should always be rounded up,
4900 * and include an extra 2 entries to account for clock crossings.
4901 *
4902 * We don't use the sprite, so we can ignore that. And on Crestline we have
4903 * to set the non-SR watermarks to 8.
5eddb70b 4904 */
7662c8bd
SL		 4905static void intel_update_watermarks(struct drm_device *dev)
4906{
e70236a8 4907 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4908
d210246a
CW		 4909 if (dev_priv->display.update_wm)
4910 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4911}
4912
b840d907
JB		 4913void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4914 uint32_t sprite_width, int pixel_size)
4915{
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917
4918 if (dev_priv->display.update_sprite_wm)
4919 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4920 pixel_size);
4921}
4922
a7615030
CW		 4923static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4924{
72bbe58c
KP		 4925 if (i915_panel_use_ssc >= 0)
4926 return i915_panel_use_ssc != 0;
4927 return dev_priv->lvds_use_ssc
435793df 4928 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4929}
4930
5a354204
JB		 4931/**
4932 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4933 * @crtc: CRTC structure
3b5c78a3 4934 * @mode: requested mode
5a354204
JB		 4935 *
4936 * A pipe may be connected to one or more outputs. Based on the depth of the
4937 * attached framebuffer, choose a good color depth to use on the pipe.
4938 *
4939 * If possible, match the pipe depth to the fb depth. In some cases, this
4940 * isn't ideal, because the connected output supports a lesser or restricted
4941 * set of depths. Resolve that here:
4942 * LVDS typically supports only 6bpc, so clamp down in that case
4943 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4944 * Displays may support a restricted set as well, check EDID and clamp as
4945 * appropriate.
3b5c78a3 4946 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4947 *
4948 * RETURNS:
4949 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4950 * true if they don't match).
4951 */
4952static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4953 unsigned int *pipe_bpp,
4954 struct drm_display_mode *mode)
5a354204
JB		 4955{
4956 struct drm_device *dev = crtc->dev;
4957 struct drm_i915_private *dev_priv = dev->dev_private;
4958 struct drm_encoder *encoder;
4959 struct drm_connector *connector;
4960 unsigned int display_bpc = UINT_MAX, bpc;
4961
4962 /* Walk the encoders & connectors on this crtc, get min bpc */
4963 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4964 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4965
4966 if (encoder->crtc != crtc)
4967 continue;
4968
4969 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4970 unsigned int lvds_bpc;
4971
4972 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4973 LVDS_A3_POWER_UP)
4974 lvds_bpc = 8;
4975 else
4976 lvds_bpc = 6;
4977
4978 if (lvds_bpc < display_bpc) {
82820490 4979 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4980 display_bpc = lvds_bpc;
4981 }
4982 continue;
4983 }
4984
4985 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4986 /* Use VBT settings if we have an eDP panel */
4987 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4988
4989 if (edp_bpc < display_bpc) {
82820490 4990 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4991 display_bpc = edp_bpc;
4992 }
4993 continue;
4994 }
4995
4996 /* Not one of the known troublemakers, check the EDID */
4997 list_for_each_entry(connector, &dev->mode_config.connector_list,
4998 head) {
4999 if (connector->encoder != encoder)
5000 continue;
5001
62ac41a6
JB		 5002 /* Don't use an invalid EDID bpc value */
5003 if (connector->display_info.bpc &&
5004 connector->display_info.bpc < display_bpc) {
82820490 5005 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 5006 display_bpc = connector->display_info.bpc;
5007 }
5008 }
5009
5010 /*
5011 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5012 * through, clamp it down. (Note: >12bpc will be caught below.)
5013 */
5014 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5015 if (display_bpc > 8 && display_bpc < 12) {
82820490 5016 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 5017 display_bpc = 12;
5018 } else {
82820490 5019 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 5020 display_bpc = 8;
5021 }
5022 }
5023 }
5024
3b5c78a3
AJ		 5025 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5026 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5027 display_bpc = 6;
5028 }
5029
5a354204
JB		 5030 /*
5031 * We could just drive the pipe at the highest bpc all the time and
5032 * enable dithering as needed, but that costs bandwidth. So choose
5033 * the minimum value that expresses the full color range of the fb but
5034 * also stays within the max display bpc discovered above.
5035 */
5036
5037 switch (crtc->fb->depth) {
5038 case 8:
5039 bpc = 8; /* since we go through a colormap */
5040 break;
5041 case 15:
5042 case 16:
5043 bpc = 6; /* min is 18bpp */
5044 break;
5045 case 24:
578393cd 5046 bpc = 8;
5a354204
JB		 5047 break;
5048 case 30:
578393cd 5049 bpc = 10;
5a354204
JB		 5050 break;
5051 case 48:
578393cd 5052 bpc = 12;
5a354204
JB		 5053 break;
5054 default:
5055 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5056 bpc = min((unsigned int)8, display_bpc);
5057 break;
5058 }
5059
578393cd
KP		 5060 display_bpc = min(display_bpc, bpc);
5061
82820490
AJ		 5062 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5063 bpc, display_bpc);
5a354204 5064
578393cd 5065 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5066
5067 return display_bpc != bpc;
5068}
5069
c65d77d8
JB		 5070static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5071{
5072 struct drm_device *dev = crtc->dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 int refclk;
5075
5076 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5077 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5078 refclk = dev_priv->lvds_ssc_freq * 1000;
5079 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5080 refclk / 1000);
5081 } else if (!IS_GEN2(dev)) {
5082 refclk = 96000;
5083 } else {
5084 refclk = 48000;
5085 }
5086
5087 return refclk;
5088}
5089
5090static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5091 intel_clock_t *clock)
5092{
5093 /* SDVO TV has fixed PLL values depend on its clock range,
5094 this mirrors vbios setting. */
5095 if (adjusted_mode->clock >= 100000
5096 && adjusted_mode->clock < 140500) {
5097 clock->p1 = 2;
5098 clock->p2 = 10;
5099 clock->n = 3;
5100 clock->m1 = 16;
5101 clock->m2 = 8;
5102 } else if (adjusted_mode->clock >= 140500
5103 && adjusted_mode->clock <= 200000) {
5104 clock->p1 = 1;
5105 clock->p2 = 10;
5106 clock->n = 6;
5107 clock->m1 = 12;
5108 clock->m2 = 8;
5109 }
5110}
5111
a7516a05
JB		 5112static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5113 intel_clock_t *clock,
5114 intel_clock_t *reduced_clock)
5115{
5116 struct drm_device *dev = crtc->dev;
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5119 int pipe = intel_crtc->pipe;
5120 u32 fp, fp2 = 0;
5121
5122 if (IS_PINEVIEW(dev)) {
5123 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5124 if (reduced_clock)
5125 fp2 = (1 << reduced_clock->n) << 16 |
5126 reduced_clock->m1 << 8 | reduced_clock->m2;
5127 } else {
5128 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5129 if (reduced_clock)
5130 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5131 reduced_clock->m2;
5132 }
5133
5134 I915_WRITE(FP0(pipe), fp);
5135
5136 intel_crtc->lowfreq_avail = false;
5137 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5138 reduced_clock && i915_powersave) {
5139 I915_WRITE(FP1(pipe), fp2);
5140 intel_crtc->lowfreq_avail = true;
5141 } else {
5142 I915_WRITE(FP1(pipe), fp);
5143 }
5144}
5145
f564048e
EA		 5146static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5147 struct drm_display_mode *mode,
5148 struct drm_display_mode *adjusted_mode,
5149 int x, int y,
5150 struct drm_framebuffer *old_fb)
79e53945
JB		 5151{
5152 struct drm_device *dev = crtc->dev;
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5155 int pipe = intel_crtc->pipe;
80824003 5156 int plane = intel_crtc->plane;
c751ce4f 5157 int refclk, num_connectors = 0;
652c393a 5158 intel_clock_t clock, reduced_clock;
0529a0d9 5159 u32 dpll, dspcntr, pipeconf, vsyncshift;
652c393a 5160 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5161 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5162 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5163 struct intel_encoder *encoder;
d4906093 5164 const intel_limit_t *limit;
5c3b82e2 5165 int ret;
fae14981 5166 u32 temp;
aa9b500d 5167 u32 lvds_sync = 0;
79e53945 5168
5eddb70b
CW		 5169 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5170 if (encoder->base.crtc != crtc)
79e53945
JB		 5171 continue;
5172
5eddb70b 5173 switch (encoder->type) {
79e53945
JB		 5174 case INTEL_OUTPUT_LVDS:
5175 is_lvds = true;
5176 break;
5177 case INTEL_OUTPUT_SDVO:
7d57382e 5178 case INTEL_OUTPUT_HDMI:
79e53945 5179 is_sdvo = true;
5eddb70b 5180 if (encoder->needs_tv_clock)
e2f0ba97 5181 is_tv = true;
79e53945
JB		 5182 break;
5183 case INTEL_OUTPUT_DVO:
5184 is_dvo = true;
5185 break;
5186 case INTEL_OUTPUT_TVOUT:
5187 is_tv = true;
5188 break;
5189 case INTEL_OUTPUT_ANALOG:
5190 is_crt = true;
5191 break;
a4fc5ed6
KP		 5192 case INTEL_OUTPUT_DISPLAYPORT:
5193 is_dp = true;
5194 break;
79e53945 5195 }
43565a06 5196
c751ce4f 5197 num_connectors++;
79e53945
JB		 5198 }
5199
c65d77d8 5200 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5201
d4906093
ML		 5202 /*
5203 * Returns a set of divisors for the desired target clock with the given
5204 * refclk, or FALSE. The returned values represent the clock equation:
5205 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5206 */
1b894b59 5207 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5208 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5209 &clock);
79e53945
JB		 5210 if (!ok) {
5211 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5212 return -EINVAL;
79e53945
JB		 5213 }
5214
cda4b7d3 5215 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5216 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5217
ddc9003c 5218 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5219 /*
5220 * Ensure we match the reduced clock's P to the target clock.
5221 * If the clocks don't match, we can't switch the display clock
5222 * by using the FP0/FP1. In such case we will disable the LVDS
5223 * downclock feature.
5224 */
ddc9003c 5225 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5226 dev_priv->lvds_downclock,
5227 refclk,
cec2f356 5228 &clock,
5eddb70b 5229 &reduced_clock);
7026d4ac
ZW		 5230 }
5231
c65d77d8
JB		 5232 if (is_sdvo && is_tv)
5233 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5234
a7516a05
JB		 5235 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5236 &reduced_clock : NULL);
79e53945 5237
929c77fb 5238 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5239
a6c45cf0 5240 if (!IS_GEN2(dev)) {
79e53945
JB		 5241 if (is_lvds)
5242 dpll |= DPLLB_MODE_LVDS;
5243 else
5244 dpll |= DPLLB_MODE_DAC_SERIAL;
5245 if (is_sdvo) {
6c9547ff
CW		 5246 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5247 if (pixel_multiplier > 1) {
5248 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5249 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5250 }
79e53945 5251 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5252 }
929c77fb 5253 if (is_dp)
a4fc5ed6 5254 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5255
5256 /* compute bitmask from p1 value */
f2b115e6
AJ		 5257 if (IS_PINEVIEW(dev))
5258 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5259 else {
2177832f 5260 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5261 if (IS_G4X(dev) && has_reduced_clock)
5262 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5263 }
79e53945
JB		 5264 switch (clock.p2) {
5265 case 5:
5266 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5267 break;
5268 case 7:
5269 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5270 break;
5271 case 10:
5272 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5273 break;
5274 case 14:
5275 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5276 break;
5277 }
929c77fb 5278 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5279 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5280 } else {
5281 if (is_lvds) {
5282 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5283 } else {
5284 if (clock.p1 == 2)
5285 dpll |= PLL_P1_DIVIDE_BY_TWO;
5286 else
5287 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5288 if (clock.p2 == 4)
5289 dpll |= PLL_P2_DIVIDE_BY_4;
5290 }
5291 }
5292
43565a06
KH		 5293 if (is_sdvo && is_tv)
5294 dpll |= PLL_REF_INPUT_TVCLKINBC;
5295 else if (is_tv)
79e53945 5296 /* XXX: just matching BIOS for now */
43565a06 5297 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5298 dpll |= 3;
a7615030 5299 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5300 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5301 else
5302 dpll |= PLL_REF_INPUT_DREFCLK;
5303
5304 /* setup pipeconf */
5eddb70b 5305 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5306
5307 /* Set up the display plane register */
5308 dspcntr = DISPPLANE_GAMMA_ENABLE;
5309
929c77fb
EA		 5310 if (pipe == 0)
5311 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5312 else
5313 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5314
a6c45cf0 5315 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5316 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5317 * core speed.
5318 *
5319 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5320 * pipe == 0 check?
5321 */
e70236a8
JB		 5322 if (mode->clock >
5323 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5324 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5325 else
5eddb70b 5326 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5327 }
5328
3b5c78a3
AJ		 5329 /* default to 8bpc */
5330 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5331 if (is_dp) {
5332 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5333 pipeconf |= PIPECONF_BPP_6 |
5334 PIPECONF_DITHER_EN |
5335 PIPECONF_DITHER_TYPE_SP;
5336 }
5337 }
5338
929c77fb 5339 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5340
28c97730 5341 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5342 drm_mode_debug_printmodeline(mode);
5343
fae14981 5344 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5345
fae14981 5346 POSTING_READ(DPLL(pipe));
c713bb08 5347 udelay(150);
8db9d77b 5348
79e53945
JB		 5349 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5350 * This is an exception to the general rule that mode_set doesn't turn
5351 * things on.
5352 */
5353 if (is_lvds) {
fae14981 5354 temp = I915_READ(LVDS);
5eddb70b 5355 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5356 if (pipe == 1) {
929c77fb 5357 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5358 } else {
929c77fb 5359 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5360 }
a3e17eb8 5361 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5362 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5363 /* Set the B0-B3 data pairs corresponding to whether we're going to
5364 * set the DPLLs for dual-channel mode or not.
5365 */
5366 if (clock.p2 == 7)
5eddb70b 5367 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5368 else
5eddb70b 5369 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5370
5371 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5372 * appropriately here, but we need to look more thoroughly into how
5373 * panels behave in the two modes.
5374 */
929c77fb
EA		 5375 /* set the dithering flag on LVDS as needed */
5376 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5377 if (dev_priv->lvds_dither)
5eddb70b 5378 temp |= LVDS_ENABLE_DITHER;
434ed097 5379 else
5eddb70b 5380 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5381 }
aa9b500d
BF		 5382 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5383 lvds_sync |= LVDS_HSYNC_POLARITY;
5384 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5385 lvds_sync |= LVDS_VSYNC_POLARITY;
5386 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5387 != lvds_sync) {
5388 char flags[2] = "-+";
5389 DRM_INFO("Changing LVDS panel from "
5390 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5391 flags[!(temp & LVDS_HSYNC_POLARITY)],
5392 flags[!(temp & LVDS_VSYNC_POLARITY)],
5393 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5394 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5395 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5396 temp |= lvds_sync;
5397 }
fae14981 5398 I915_WRITE(LVDS, temp);
79e53945 5399 }
434ed097 5400
929c77fb 5401 if (is_dp) {
a4fc5ed6 5402 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5403 }
5404
fae14981 5405 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5406
c713bb08 5407 /* Wait for the clocks to stabilize. */
fae14981 5408 POSTING_READ(DPLL(pipe));
c713bb08 5409 udelay(150);
32f9d658 5410
c713bb08
EA		 5411 if (INTEL_INFO(dev)->gen >= 4) {
5412 temp = 0;
5413 if (is_sdvo) {
5414 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5415 if (temp > 1)
5416 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5417 else
5418 temp = 0;
32f9d658 5419 }
c713bb08
EA		 5420 I915_WRITE(DPLL_MD(pipe), temp);
5421 } else {
5422 /* The pixel multiplier can only be updated once the
5423 * DPLL is enabled and the clocks are stable.
5424 *
5425 * So write it again.
5426 */
fae14981 5427 I915_WRITE(DPLL(pipe), dpll);
79e53945 5428 }
79e53945 5429
a7516a05
JB		 5430 if (HAS_PIPE_CXSR(dev)) {
5431 if (intel_crtc->lowfreq_avail) {
28c97730 5432 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5433 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5434 } else {
28c97730 5435 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5436 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5437 }
5438 }
5439
617cf884 5440 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 5441 if (!IS_GEN2(dev) &&
5442 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 5443 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5444 /* the chip adds 2 halflines automatically */
734b4157 5445 adjusted_mode->crtc_vtotal -= 1;
734b4157 5446 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5447 vsyncshift = adjusted_mode->crtc_hsync_start
5448 - adjusted_mode->crtc_htotal/2;
5449 } else {
617cf884 5450 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 5451 vsyncshift = 0;
5452 }
5453
5454 if (!IS_GEN3(dev))
5455 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 5456
5eddb70b
CW		 5457 I915_WRITE(HTOTAL(pipe),
5458 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5459 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5460 I915_WRITE(HBLANK(pipe),
5461 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5462 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5463 I915_WRITE(HSYNC(pipe),
5464 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5465 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5466
5467 I915_WRITE(VTOTAL(pipe),
5468 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5469 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5470 I915_WRITE(VBLANK(pipe),
5471 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5472 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5473 I915_WRITE(VSYNC(pipe),
5474 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5475 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5476
5477 /* pipesrc and dspsize control the size that is scaled from,
5478 * which should always be the user's requested size.
79e53945 5479 */
929c77fb
EA		 5480 I915_WRITE(DSPSIZE(plane),
5481 ((mode->vdisplay - 1) << 16) |
5482 (mode->hdisplay - 1));
5483 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5484 I915_WRITE(PIPESRC(pipe),
5485 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5486
f564048e
EA		 5487 I915_WRITE(PIPECONF(pipe), pipeconf);
5488 POSTING_READ(PIPECONF(pipe));
929c77fb 5489 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5490
5491 intel_wait_for_vblank(dev, pipe);
5492
f564048e
EA		 5493 I915_WRITE(DSPCNTR(plane), dspcntr);
5494 POSTING_READ(DSPCNTR(plane));
284d9529 5495 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5496
5497 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5498
5499 intel_update_watermarks(dev);
5500
f564048e
EA		 5501 return ret;
5502}
5503
9fb526db
KP		 5504/*
5505 * Initialize reference clocks when the driver loads
5506 */
5507void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5508{
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5511 struct intel_encoder *encoder;
13d83a67
JB		 5512 u32 temp;
5513 bool has_lvds = false;
199e5d79
KP		 5514 bool has_cpu_edp = false;
5515 bool has_pch_edp = false;
5516 bool has_panel = false;
99eb6a01
KP		 5517 bool has_ck505 = false;
5518 bool can_ssc = false;
13d83a67
JB		 5519
5520 /* We need to take the global config into account */
199e5d79
KP		 5521 list_for_each_entry(encoder, &mode_config->encoder_list,
5522 base.head) {
5523 switch (encoder->type) {
5524 case INTEL_OUTPUT_LVDS:
5525 has_panel = true;
5526 has_lvds = true;
5527 break;
5528 case INTEL_OUTPUT_EDP:
5529 has_panel = true;
5530 if (intel_encoder_is_pch_edp(&encoder->base))
5531 has_pch_edp = true;
5532 else
5533 has_cpu_edp = true;
5534 break;
13d83a67
JB		 5535 }
5536 }
5537
99eb6a01
KP		 5538 if (HAS_PCH_IBX(dev)) {
5539 has_ck505 = dev_priv->display_clock_mode;
5540 can_ssc = has_ck505;
5541 } else {
5542 has_ck505 = false;
5543 can_ssc = true;
5544 }
5545
5546 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5547 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5548 has_ck505);
13d83a67
JB		 5549
5550 /* Ironlake: try to setup display ref clock before DPLL
5551 * enabling. This is only under driver's control after
5552 * PCH B stepping, previous chipset stepping should be
5553 * ignoring this setting.
5554 */
5555 temp = I915_READ(PCH_DREF_CONTROL);
5556 /* Always enable nonspread source */
5557 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5558
99eb6a01
KP		 5559 if (has_ck505)
5560 temp |= DREF_NONSPREAD_CK505_ENABLE;
5561 else
5562 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5563
199e5d79
KP		 5564 if (has_panel) {
5565 temp &= ~DREF_SSC_SOURCE_MASK;
5566 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5567
199e5d79 5568 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5569 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5570 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5571 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 5572 } else
5573 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5574
5575 /* Get SSC going before enabling the outputs */
5576 I915_WRITE(PCH_DREF_CONTROL, temp);
5577 POSTING_READ(PCH_DREF_CONTROL);
5578 udelay(200);
5579
13d83a67
JB		 5580 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5581
5582 /* Enable CPU source on CPU attached eDP */
199e5d79 5583 if (has_cpu_edp) {
99eb6a01 5584 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5585 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5586 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5587 }
13d83a67
JB		 5588 else
5589 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5590 } else
5591 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5592
5593 I915_WRITE(PCH_DREF_CONTROL, temp);
5594 POSTING_READ(PCH_DREF_CONTROL);
5595 udelay(200);
5596 } else {
5597 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5598
5599 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5600
5601 /* Turn off CPU output */
5602 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5603
5604 I915_WRITE(PCH_DREF_CONTROL, temp);
5605 POSTING_READ(PCH_DREF_CONTROL);
5606 udelay(200);
5607
5608 /* Turn off the SSC source */
5609 temp &= ~DREF_SSC_SOURCE_MASK;
5610 temp |= DREF_SSC_SOURCE_DISABLE;
5611
5612 /* Turn off SSC1 */
5613 temp &= ~ DREF_SSC1_ENABLE;
5614
13d83a67
JB		 5615 I915_WRITE(PCH_DREF_CONTROL, temp);
5616 POSTING_READ(PCH_DREF_CONTROL);
5617 udelay(200);
5618 }
5619}
5620
d9d444cb
JB		 5621static int ironlake_get_refclk(struct drm_crtc *crtc)
5622{
5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 struct intel_encoder *encoder;
5626 struct drm_mode_config *mode_config = &dev->mode_config;
5627 struct intel_encoder *edp_encoder = NULL;
5628 int num_connectors = 0;
5629 bool is_lvds = false;
5630
5631 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5632 if (encoder->base.crtc != crtc)
5633 continue;
5634
5635 switch (encoder->type) {
5636 case INTEL_OUTPUT_LVDS:
5637 is_lvds = true;
5638 break;
5639 case INTEL_OUTPUT_EDP:
5640 edp_encoder = encoder;
5641 break;
5642 }
5643 num_connectors++;
5644 }
5645
5646 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5647 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5648 dev_priv->lvds_ssc_freq);
5649 return dev_priv->lvds_ssc_freq * 1000;
5650 }
5651
5652 return 120000;
5653}
5654
f564048e
EA		 5655static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5656 struct drm_display_mode *mode,
5657 struct drm_display_mode *adjusted_mode,
5658 int x, int y,
5659 struct drm_framebuffer *old_fb)
79e53945
JB		 5660{
5661 struct drm_device *dev = crtc->dev;
5662 struct drm_i915_private *dev_priv = dev->dev_private;
5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664 int pipe = intel_crtc->pipe;
80824003 5665 int plane = intel_crtc->plane;
c751ce4f 5666 int refclk, num_connectors = 0;
652c393a 5667 intel_clock_t clock, reduced_clock;
5eddb70b 5668 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5669 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5670 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5671 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5672 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5673 struct intel_encoder *encoder;
d4906093 5674 const intel_limit_t *limit;
5c3b82e2 5675 int ret;
2c07245f 5676 struct fdi_m_n m_n = {0};
fae14981 5677 u32 temp;
aa9b500d 5678 u32 lvds_sync = 0;
5a354204
JB		 5679 int target_clock, pixel_multiplier, lane, link_bw, factor;
5680 unsigned int pipe_bpp;
5681 bool dither;
79e53945 5682
5eddb70b
CW		 5683 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5684 if (encoder->base.crtc != crtc)
79e53945
JB		 5685 continue;
5686
5eddb70b 5687 switch (encoder->type) {
79e53945
JB		 5688 case INTEL_OUTPUT_LVDS:
5689 is_lvds = true;
5690 break;
5691 case INTEL_OUTPUT_SDVO:
7d57382e 5692 case INTEL_OUTPUT_HDMI:
79e53945 5693 is_sdvo = true;
5eddb70b 5694 if (encoder->needs_tv_clock)
e2f0ba97 5695 is_tv = true;
79e53945 5696 break;
79e53945
JB		 5697 case INTEL_OUTPUT_TVOUT:
5698 is_tv = true;
5699 break;
5700 case INTEL_OUTPUT_ANALOG:
5701 is_crt = true;
5702 break;
a4fc5ed6
KP		 5703 case INTEL_OUTPUT_DISPLAYPORT:
5704 is_dp = true;
5705 break;
32f9d658 5706 case INTEL_OUTPUT_EDP:
5eddb70b 5707 has_edp_encoder = encoder;
32f9d658 5708 break;
79e53945 5709 }
43565a06 5710
c751ce4f 5711 num_connectors++;
79e53945
JB		 5712 }
5713
d9d444cb 5714 refclk = ironlake_get_refclk(crtc);
79e53945 5715
d4906093
ML		 5716 /*
5717 * Returns a set of divisors for the desired target clock with the given
5718 * refclk, or FALSE. The returned values represent the clock equation:
5719 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5720 */
1b894b59 5721 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5722 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5723 &clock);
79e53945
JB		 5724 if (!ok) {
5725 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5726 return -EINVAL;
79e53945
JB		 5727 }
5728
cda4b7d3 5729 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5730 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5731
ddc9003c 5732 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5733 /*
5734 * Ensure we match the reduced clock's P to the target clock.
5735 * If the clocks don't match, we can't switch the display clock
5736 * by using the FP0/FP1. In such case we will disable the LVDS
5737 * downclock feature.
5738 */
ddc9003c 5739 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5740 dev_priv->lvds_downclock,
5741 refclk,
cec2f356 5742 &clock,
5eddb70b 5743 &reduced_clock);
652c393a 5744 }
7026d4ac
ZW		 5745 /* SDVO TV has fixed PLL values depend on its clock range,
5746 this mirrors vbios setting. */
5747 if (is_sdvo && is_tv) {
5748 if (adjusted_mode->clock >= 100000
5eddb70b 5749 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5750 clock.p1 = 2;
5751 clock.p2 = 10;
5752 clock.n = 3;
5753 clock.m1 = 16;
5754 clock.m2 = 8;
5755 } else if (adjusted_mode->clock >= 140500
5eddb70b 5756 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5757 clock.p1 = 1;
5758 clock.p2 = 10;
5759 clock.n = 6;
5760 clock.m1 = 12;
5761 clock.m2 = 8;
5762 }
5763 }
5764
2c07245f 5765 /* FDI link */
8febb297
EA		 5766 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5767 lane = 0;
5768 /* CPU eDP doesn't require FDI link, so just set DP M/N
5769 according to current link config */
5770 if (has_edp_encoder &&
5771 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5772 target_clock = mode->clock;
5773 intel_edp_link_config(has_edp_encoder,
5774 &lane, &link_bw);
5775 } else {
5776 /* [e]DP over FDI requires target mode clock
5777 instead of link clock */
5778 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5779 target_clock = mode->clock;
8febb297
EA		 5780 else
5781 target_clock = adjusted_mode->clock;
5782
5783 /* FDI is a binary signal running at ~2.7GHz, encoding
5784 * each output octet as 10 bits. The actual frequency
5785 * is stored as a divider into a 100MHz clock, and the
5786 * mode pixel clock is stored in units of 1KHz.
5787 * Hence the bw of each lane in terms of the mode signal
5788 * is:
5789 */
5790 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5791 }
58a27471 5792
8febb297
EA		 5793 /* determine panel color depth */
5794 temp = I915_READ(PIPECONF(pipe));
5795 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5796 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5797 switch (pipe_bpp) {
5798 case 18:
5799 temp |= PIPE_6BPC;
8febb297 5800 break;
5a354204
JB		 5801 case 24:
5802 temp |= PIPE_8BPC;
8febb297 5803 break;
5a354204
JB		 5804 case 30:
5805 temp |= PIPE_10BPC;
8febb297 5806 break;
5a354204
JB		 5807 case 36:
5808 temp |= PIPE_12BPC;
8febb297
EA		 5809 break;
5810 default:
62ac41a6
JB		 5811 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5812 pipe_bpp);
5a354204
JB		 5813 temp |= PIPE_8BPC;
5814 pipe_bpp = 24;
5815 break;
8febb297 5816 }
77ffb597 5817
5a354204
JB		 5818 intel_crtc->bpp = pipe_bpp;
5819 I915_WRITE(PIPECONF(pipe), temp);
5820
8febb297
EA		 5821 if (!lane) {
5822 /*
5823 * Account for spread spectrum to avoid
5824 * oversubscribing the link. Max center spread
5825 * is 2.5%; use 5% for safety's sake.
5826 */
5a354204 5827 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5828 lane = bps / (link_bw * 8) + 1;
5eb08b69 5829 }
2c07245f 5830
8febb297
EA		 5831 intel_crtc->fdi_lanes = lane;
5832
5833 if (pixel_multiplier > 1)
5834 link_bw *= pixel_multiplier;
5a354204
JB		 5835 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5836 &m_n);
8febb297 5837
a07d6787
EA		 5838 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5839 if (has_reduced_clock)
5840 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5841 reduced_clock.m2;
79e53945 5842
c1858123 5843 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5844 factor = 21;
5845 if (is_lvds) {
5846 if ((intel_panel_use_ssc(dev_priv) &&
5847 dev_priv->lvds_ssc_freq == 100) ||
5848 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5849 factor = 25;
5850 } else if (is_sdvo && is_tv)
5851 factor = 20;
c1858123 5852
cb0e0931 5853 if (clock.m < factor * clock.n)
8febb297 5854 fp |= FP_CB_TUNE;
2c07245f 5855
5eddb70b 5856 dpll = 0;
2c07245f 5857
a07d6787
EA		 5858 if (is_lvds)
5859 dpll |= DPLLB_MODE_LVDS;
5860 else
5861 dpll |= DPLLB_MODE_DAC_SERIAL;
5862 if (is_sdvo) {
5863 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5864 if (pixel_multiplier > 1) {
5865 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5866 }
a07d6787
EA		 5867 dpll |= DPLL_DVO_HIGH_SPEED;
5868 }
5869 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5870 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5871
a07d6787
EA		 5872 /* compute bitmask from p1 value */
5873 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5874 /* also FPA1 */
5875 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5876
5877 switch (clock.p2) {
5878 case 5:
5879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5880 break;
5881 case 7:
5882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5883 break;
5884 case 10:
5885 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5886 break;
5887 case 14:
5888 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5889 break;
79e53945
JB		 5890 }
5891
43565a06
KH		 5892 if (is_sdvo && is_tv)
5893 dpll |= PLL_REF_INPUT_TVCLKINBC;
5894 else if (is_tv)
79e53945 5895 /* XXX: just matching BIOS for now */
43565a06 5896 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5897 dpll |= 3;
a7615030 5898 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5899 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5900 else
5901 dpll |= PLL_REF_INPUT_DREFCLK;
5902
5903 /* setup pipeconf */
5eddb70b 5904 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5905
5906 /* Set up the display plane register */
5907 dspcntr = DISPPLANE_GAMMA_ENABLE;
5908
f7cb34d4 5909 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5910 drm_mode_debug_printmodeline(mode);
5911
5c5313c8 5912 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5913 if (!intel_crtc->no_pll) {
5914 if (!has_edp_encoder ||
5915 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5916 I915_WRITE(PCH_FP0(pipe), fp);
5917 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5918
5919 POSTING_READ(PCH_DPLL(pipe));
5920 udelay(150);
5921 }
5922 } else {
5923 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5924 fp == I915_READ(PCH_FP0(0))) {
5925 intel_crtc->use_pll_a = true;
5926 DRM_DEBUG_KMS("using pipe a dpll\n");
5927 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5928 fp == I915_READ(PCH_FP0(1))) {
5929 intel_crtc->use_pll_a = false;
5930 DRM_DEBUG_KMS("using pipe b dpll\n");
5931 } else {
5932 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5933 return -EINVAL;
5934 }
79e53945
JB		 5935 }
5936
5937 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5938 * This is an exception to the general rule that mode_set doesn't turn
5939 * things on.
5940 */
5941 if (is_lvds) {
fae14981 5942 temp = I915_READ(PCH_LVDS);
5eddb70b 5943 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5944 if (HAS_PCH_CPT(dev)) {
5945 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5946 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5947 } else {
5948 if (pipe == 1)
5949 temp |= LVDS_PIPEB_SELECT;
5950 else
5951 temp &= ~LVDS_PIPEB_SELECT;
5952 }
4b645f14 5953
a3e17eb8 5954 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5955 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5956 /* Set the B0-B3 data pairs corresponding to whether we're going to
5957 * set the DPLLs for dual-channel mode or not.
5958 */
5959 if (clock.p2 == 7)
5eddb70b 5960 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5961 else
5eddb70b 5962 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5963
5964 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5965 * appropriately here, but we need to look more thoroughly into how
5966 * panels behave in the two modes.
5967 */
aa9b500d
BF		 5968 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5969 lvds_sync |= LVDS_HSYNC_POLARITY;
5970 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5971 lvds_sync |= LVDS_VSYNC_POLARITY;
5972 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5973 != lvds_sync) {
5974 char flags[2] = "-+";
5975 DRM_INFO("Changing LVDS panel from "
5976 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5977 flags[!(temp & LVDS_HSYNC_POLARITY)],
5978 flags[!(temp & LVDS_VSYNC_POLARITY)],
5979 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5980 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5981 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5982 temp |= lvds_sync;
5983 }
fae14981 5984 I915_WRITE(PCH_LVDS, temp);
79e53945 5985 }
434ed097 5986
8febb297
EA		 5987 pipeconf &= ~PIPECONF_DITHER_EN;
5988 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5989 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5990 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5991 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5992 }
5c5313c8 5993 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5994 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5995 } else {
8db9d77b 5996 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5997 I915_WRITE(TRANSDATA_M1(pipe), 0);
5998 I915_WRITE(TRANSDATA_N1(pipe), 0);
5999 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6000 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 6001 }
79e53945 6002
4b645f14
JB		 6003 if (!intel_crtc->no_pll &&
6004 (!has_edp_encoder ||
6005 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 6006 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 6007
32f9d658 6008 /* Wait for the clocks to stabilize. */
fae14981 6009 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 6010 udelay(150);
6011
8febb297
EA		 6012 /* The pixel multiplier can only be updated once the
6013 * DPLL is enabled and the clocks are stable.
6014 *
6015 * So write it again.
6016 */
fae14981 6017 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 6018 }
79e53945 6019
5eddb70b 6020 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 6021 if (!intel_crtc->no_pll) {
6022 if (is_lvds && has_reduced_clock && i915_powersave) {
6023 I915_WRITE(PCH_FP1(pipe), fp2);
6024 intel_crtc->lowfreq_avail = true;
6025 if (HAS_PIPE_CXSR(dev)) {
6026 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6027 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6028 }
6029 } else {
6030 I915_WRITE(PCH_FP1(pipe), fp);
6031 if (HAS_PIPE_CXSR(dev)) {
6032 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6033 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6034 }
652c393a
JB		 6035 }
6036 }
6037
617cf884 6038 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 6039 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 6040 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 6041 /* the chip adds 2 halflines automatically */
734b4157 6042 adjusted_mode->crtc_vtotal -= 1;
734b4157 6043 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 6044 I915_WRITE(VSYNCSHIFT(pipe),
6045 adjusted_mode->crtc_hsync_start
6046 - adjusted_mode->crtc_htotal/2);
6047 } else {
617cf884 6048 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 6049 I915_WRITE(VSYNCSHIFT(pipe), 0);
6050 }
734b4157 6051
5eddb70b
CW		 6052 I915_WRITE(HTOTAL(pipe),
6053 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 6054 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 6055 I915_WRITE(HBLANK(pipe),
6056 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 6057 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 6058 I915_WRITE(HSYNC(pipe),
6059 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 6060 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 6061
6062 I915_WRITE(VTOTAL(pipe),
6063 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 6064 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 6065 I915_WRITE(VBLANK(pipe),
6066 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6067 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6068 I915_WRITE(VSYNC(pipe),
6069 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6070 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6071
8febb297
EA		 6072 /* pipesrc controls the size that is scaled from, which should
6073 * always be the user's requested size.
79e53945 6074 */
5eddb70b
CW		 6075 I915_WRITE(PIPESRC(pipe),
6076 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6077
8febb297
EA		 6078 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6079 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6080 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6081 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6082
8febb297
EA		 6083 if (has_edp_encoder &&
6084 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6085 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6086 }
6087
5eddb70b
CW		 6088 I915_WRITE(PIPECONF(pipe), pipeconf);
6089 POSTING_READ(PIPECONF(pipe));
79e53945 6090
9d0498a2 6091 intel_wait_for_vblank(dev, pipe);
79e53945 6092
5eddb70b 6093 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6094 POSTING_READ(DSPCNTR(plane));
79e53945 6095
5c3b82e2 6096 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6097
6098 intel_update_watermarks(dev);
6099
1f803ee5 6100 return ret;
79e53945
JB		 6101}
6102
f564048e
EA		 6103static int intel_crtc_mode_set(struct drm_crtc *crtc,
6104 struct drm_display_mode *mode,
6105 struct drm_display_mode *adjusted_mode,
6106 int x, int y,
6107 struct drm_framebuffer *old_fb)
6108{
6109 struct drm_device *dev = crtc->dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112 int pipe = intel_crtc->pipe;
f564048e
EA		 6113 int ret;
6114
0b701d27 6115 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6116
f564048e
EA		 6117 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6118 x, y, old_fb);
79e53945 6119 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6120
d8e70a25
JB		 6121 if (ret)
6122 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6123 else
6124 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6125
1f803ee5 6126 return ret;
79e53945
JB		 6127}
6128
3a9627f4
WF		 6129static bool intel_eld_uptodate(struct drm_connector *connector,
6130 int reg_eldv, uint32_t bits_eldv,
6131 int reg_elda, uint32_t bits_elda,
6132 int reg_edid)
6133{
6134 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135 uint8_t *eld = connector->eld;
6136 uint32_t i;
6137
6138 i = I915_READ(reg_eldv);
6139 i &= bits_eldv;
6140
6141 if (!eld[0])
6142 return !i;
6143
6144 if (!i)
6145 return false;
6146
6147 i = I915_READ(reg_elda);
6148 i &= ~bits_elda;
6149 I915_WRITE(reg_elda, i);
6150
6151 for (i = 0; i < eld[2]; i++)
6152 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6153 return false;
6154
6155 return true;
6156}
6157
e0dac65e
WF		 6158static void g4x_write_eld(struct drm_connector *connector,
6159 struct drm_crtc *crtc)
6160{
6161 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162 uint8_t *eld = connector->eld;
6163 uint32_t eldv;
6164 uint32_t len;
6165 uint32_t i;
6166
6167 i = I915_READ(G4X_AUD_VID_DID);
6168
6169 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6170 eldv = G4X_ELDV_DEVCL_DEVBLC;
6171 else
6172 eldv = G4X_ELDV_DEVCTG;
6173
3a9627f4
WF		 6174 if (intel_eld_uptodate(connector,
6175 G4X_AUD_CNTL_ST, eldv,
6176 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6177 G4X_HDMIW_HDMIEDID))
6178 return;
6179
e0dac65e
WF		 6180 i = I915_READ(G4X_AUD_CNTL_ST);
6181 i &= ~(eldv | G4X_ELD_ADDR);
6182 len = (i >> 9) & 0x1f; /* ELD buffer size */
6183 I915_WRITE(G4X_AUD_CNTL_ST, i);
6184
6185 if (!eld[0])
6186 return;
6187
6188 len = min_t(uint8_t, eld[2], len);
6189 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6190 for (i = 0; i < len; i++)
6191 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6192
6193 i = I915_READ(G4X_AUD_CNTL_ST);
6194 i |= eldv;
6195 I915_WRITE(G4X_AUD_CNTL_ST, i);
6196}
6197
6198static void ironlake_write_eld(struct drm_connector *connector,
6199 struct drm_crtc *crtc)
6200{
6201 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6202 uint8_t *eld = connector->eld;
6203 uint32_t eldv;
6204 uint32_t i;
6205 int len;
6206 int hdmiw_hdmiedid;
b6daa025 6207 int aud_config;
e0dac65e
WF		 6208 int aud_cntl_st;
6209 int aud_cntrl_st2;
6210
b3f33cbf 6211 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6212 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6213 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6214 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6215 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6216 } else {
1202b4c6 6217 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6218 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6219 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6220 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6221 }
6222
6223 i = to_intel_crtc(crtc)->pipe;
6224 hdmiw_hdmiedid += i * 0x100;
6225 aud_cntl_st += i * 0x100;
b6daa025 6226 aud_config += i * 0x100;
e0dac65e
WF		 6227
6228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6229
6230 i = I915_READ(aud_cntl_st);
6231 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6232 if (!i) {
6233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6234 /* operate blindly on all ports */
1202b4c6
WF		 6235 eldv = IBX_ELD_VALIDB;
6236 eldv |= IBX_ELD_VALIDB << 4;
6237 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6238 } else {
6239 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6241 }
6242
3a9627f4
WF		 6243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6247 } else
6248 I915_WRITE(aud_config, 0);
e0dac65e 6249
3a9627f4
WF		 6250 if (intel_eld_uptodate(connector,
6251 aud_cntrl_st2, eldv,
6252 aud_cntl_st, IBX_ELD_ADDRESS,
6253 hdmiw_hdmiedid))
6254 return;
6255
e0dac65e
WF		 6256 i = I915_READ(aud_cntrl_st2);
6257 i &= ~eldv;
6258 I915_WRITE(aud_cntrl_st2, i);
6259
6260 if (!eld[0])
6261 return;
6262
e0dac65e 6263 i = I915_READ(aud_cntl_st);
1202b4c6 6264 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6265 I915_WRITE(aud_cntl_st, i);
6266
6267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6269 for (i = 0; i < len; i++)
6270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6271
6272 i = I915_READ(aud_cntrl_st2);
6273 i |= eldv;
6274 I915_WRITE(aud_cntrl_st2, i);
6275}
6276
6277void intel_write_eld(struct drm_encoder *encoder,
6278 struct drm_display_mode *mode)
6279{
6280 struct drm_crtc *crtc = encoder->crtc;
6281 struct drm_connector *connector;
6282 struct drm_device *dev = encoder->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285 connector = drm_select_eld(encoder, mode);
6286 if (!connector)
6287 return;
6288
6289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6290 connector->base.id,
6291 drm_get_connector_name(connector),
6292 connector->encoder->base.id,
6293 drm_get_encoder_name(connector->encoder));
6294
6295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6296
6297 if (dev_priv->display.write_eld)
6298 dev_priv->display.write_eld(connector, crtc);
6299}
6300
79e53945
JB		 6301/** Loads the palette/gamma unit for the CRTC with the prepared values */
6302void intel_crtc_load_lut(struct drm_crtc *crtc)
6303{
6304 struct drm_device *dev = crtc->dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6307 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6308 int i;
6309
6310 /* The clocks have to be on to load the palette. */
aed3f09d 6311 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6312 return;
6313
f2b115e6 6314 /* use legacy palette for Ironlake */
bad720ff 6315 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6316 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6317
79e53945
JB		 6318 for (i = 0; i < 256; i++) {
6319 I915_WRITE(palreg + 4 * i,
6320 (intel_crtc->lut_r[i] << 16) |
6321 (intel_crtc->lut_g[i] << 8) |
6322 intel_crtc->lut_b[i]);
6323 }
6324}
6325
560b85bb
CW		 6326static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6327{
6328 struct drm_device *dev = crtc->dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331 bool visible = base != 0;
6332 u32 cntl;
6333
6334 if (intel_crtc->cursor_visible == visible)
6335 return;
6336
9db4a9c7 6337 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6338 if (visible) {
6339 /* On these chipsets we can only modify the base whilst
6340 * the cursor is disabled.
6341 */
9db4a9c7 6342 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6343
6344 cntl &= ~(CURSOR_FORMAT_MASK);
6345 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6346 cntl |= CURSOR_ENABLE |
6347 CURSOR_GAMMA_ENABLE |
6348 CURSOR_FORMAT_ARGB;
6349 } else
6350 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6351 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6352
6353 intel_crtc->cursor_visible = visible;
6354}
6355
6356static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6357{
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 int pipe = intel_crtc->pipe;
6362 bool visible = base != 0;
6363
6364 if (intel_crtc->cursor_visible != visible) {
548f245b 6365 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6366 if (base) {
6367 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6369 cntl |= pipe << 28; /* Connect to correct pipe */
6370 } else {
6371 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6372 cntl |= CURSOR_MODE_DISABLE;
6373 }
9db4a9c7 6374 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6375
6376 intel_crtc->cursor_visible = visible;
6377 }
6378 /* and commit changes on next vblank */
9db4a9c7 6379 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6380}
6381
65a21cd6
JB		 6382static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6383{
6384 struct drm_device *dev = crtc->dev;
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387 int pipe = intel_crtc->pipe;
6388 bool visible = base != 0;
6389
6390 if (intel_crtc->cursor_visible != visible) {
6391 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6392 if (base) {
6393 cntl &= ~CURSOR_MODE;
6394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6395 } else {
6396 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6397 cntl |= CURSOR_MODE_DISABLE;
6398 }
6399 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6400
6401 intel_crtc->cursor_visible = visible;
6402 }
6403 /* and commit changes on next vblank */
6404 I915_WRITE(CURBASE_IVB(pipe), base);
6405}
6406
cda4b7d3 6407/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6408static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6409 bool on)
cda4b7d3
CW		 6410{
6411 struct drm_device *dev = crtc->dev;
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414 int pipe = intel_crtc->pipe;
6415 int x = intel_crtc->cursor_x;
6416 int y = intel_crtc->cursor_y;
560b85bb 6417 u32 base, pos;
cda4b7d3
CW		 6418 bool visible;
6419
6420 pos = 0;
6421
6b383a7f 6422 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6423 base = intel_crtc->cursor_addr;
6424 if (x > (int) crtc->fb->width)
6425 base = 0;
6426
6427 if (y > (int) crtc->fb->height)
6428 base = 0;
6429 } else
6430 base = 0;
6431
6432 if (x < 0) {
6433 if (x + intel_crtc->cursor_width < 0)
6434 base = 0;
6435
6436 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6437 x = -x;
6438 }
6439 pos |= x << CURSOR_X_SHIFT;
6440
6441 if (y < 0) {
6442 if (y + intel_crtc->cursor_height < 0)
6443 base = 0;
6444
6445 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6446 y = -y;
6447 }
6448 pos |= y << CURSOR_Y_SHIFT;
6449
6450 visible = base != 0;
560b85bb 6451 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6452 return;
6453
65a21cd6
JB		 6454 if (IS_IVYBRIDGE(dev)) {
6455 I915_WRITE(CURPOS_IVB(pipe), pos);
6456 ivb_update_cursor(crtc, base);
6457 } else {
6458 I915_WRITE(CURPOS(pipe), pos);
6459 if (IS_845G(dev) || IS_I865G(dev))
6460 i845_update_cursor(crtc, base);
6461 else
6462 i9xx_update_cursor(crtc, base);
6463 }
cda4b7d3
CW		 6464
6465 if (visible)
6466 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6467}
6468
79e53945 6469static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6470 struct drm_file *file,
79e53945
JB		 6471 uint32_t handle,
6472 uint32_t width, uint32_t height)
6473{
6474 struct drm_device *dev = crtc->dev;
6475 struct drm_i915_private *dev_priv = dev->dev_private;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6477 struct drm_i915_gem_object *obj;
cda4b7d3 6478 uint32_t addr;
3f8bc370 6479 int ret;
79e53945 6480
28c97730 6481 DRM_DEBUG_KMS("\n");
79e53945
JB		 6482
6483 /* if we want to turn off the cursor ignore width and height */
6484 if (!handle) {
28c97730 6485 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6486 addr = 0;
05394f39 6487 obj = NULL;
5004417d 6488 mutex_lock(&dev->struct_mutex);
3f8bc370 6489 goto finish;
79e53945
JB		 6490 }
6491
6492 /* Currently we only support 64x64 cursors */
6493 if (width != 64 || height != 64) {
6494 DRM_ERROR("we currently only support 64x64 cursors\n");
6495 return -EINVAL;
6496 }
6497
05394f39 6498 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6499 if (&obj->base == NULL)
79e53945
JB		 6500 return -ENOENT;
6501
05394f39 6502 if (obj->base.size < width * height * 4) {
79e53945 6503 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6504 ret = -ENOMEM;
6505 goto fail;
79e53945
JB		 6506 }
6507
71acb5eb 6508 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6509 mutex_lock(&dev->struct_mutex);
b295d1b6 6510 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6511 if (obj->tiling_mode) {
6512 DRM_ERROR("cursor cannot be tiled\n");
6513 ret = -EINVAL;
6514 goto fail_locked;
6515 }
6516
2da3b9b9 6517 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6518 if (ret) {
6519 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6520 goto fail_locked;
e7b526bb
CW		 6521 }
6522
d9e86c0e
CW		 6523 ret = i915_gem_object_put_fence(obj);
6524 if (ret) {
2da3b9b9 6525 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6526 goto fail_unpin;
6527 }
6528
05394f39 6529 addr = obj->gtt_offset;
71acb5eb 6530 } else {
6eeefaf3 6531 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6532 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6533 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6534 align);
71acb5eb
DA		 6535 if (ret) {
6536 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6537 goto fail_locked;
71acb5eb 6538 }
05394f39 6539 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6540 }
6541
a6c45cf0 6542 if (IS_GEN2(dev))
14b60391
JB		 6543 I915_WRITE(CURSIZE, (height << 12) | width);
6544
3f8bc370 6545 finish:
3f8bc370 6546 if (intel_crtc->cursor_bo) {
b295d1b6 6547 if (dev_priv->info->cursor_needs_physical) {
05394f39 6548 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6549 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6550 } else
6551 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6552 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6553 }
80824003 6554
7f9872e0 6555 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6556
6557 intel_crtc->cursor_addr = addr;
05394f39 6558 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6559 intel_crtc->cursor_width = width;
6560 intel_crtc->cursor_height = height;
6561
6b383a7f 6562 intel_crtc_update_cursor(crtc, true);
3f8bc370 6563
79e53945 6564 return 0;
e7b526bb 6565fail_unpin:
05394f39 6566 i915_gem_object_unpin(obj);
7f9872e0 6567fail_locked:
34b8686e 6568 mutex_unlock(&dev->struct_mutex);
bc9025bd 6569fail:
05394f39 6570 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6571 return ret;
79e53945
JB		 6572}
6573
6574static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6575{
79e53945 6576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6577
cda4b7d3
CW		 6578 intel_crtc->cursor_x = x;
6579 intel_crtc->cursor_y = y;
652c393a 6580
6b383a7f 6581 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6582
6583 return 0;
6584}
6585
6586/** Sets the color ramps on behalf of RandR */
6587void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6588 u16 blue, int regno)
6589{
6590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591
6592 intel_crtc->lut_r[regno] = red >> 8;
6593 intel_crtc->lut_g[regno] = green >> 8;
6594 intel_crtc->lut_b[regno] = blue >> 8;
6595}
6596
b8c00ac5
DA		 6597void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6598 u16 *blue, int regno)
6599{
6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601
6602 *red = intel_crtc->lut_r[regno] << 8;
6603 *green = intel_crtc->lut_g[regno] << 8;
6604 *blue = intel_crtc->lut_b[regno] << 8;
6605}
6606
79e53945 6607static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6608 u16 *blue, uint32_t start, uint32_t size)
79e53945 6609{
7203425a 6610 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6612
7203425a 6613 for (i = start; i < end; i++) {
79e53945
JB		 6614 intel_crtc->lut_r[i] = red[i] >> 8;
6615 intel_crtc->lut_g[i] = green[i] >> 8;
6616 intel_crtc->lut_b[i] = blue[i] >> 8;
6617 }
6618
6619 intel_crtc_load_lut(crtc);
6620}
6621
6622/**
6623 * Get a pipe with a simple mode set on it for doing load-based monitor
6624 * detection.
6625 *
6626 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6627 * its requirements. The pipe will be connected to no other encoders.
79e53945 6628 *
c751ce4f 6629 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6630 * configured for it. In the future, it could choose to temporarily disable
6631 * some outputs to free up a pipe for its use.
6632 *
6633 * \return crtc, or NULL if no pipes are available.
6634 */
6635
6636/* VESA 640x480x72Hz mode to set on the pipe */
6637static struct drm_display_mode load_detect_mode = {
6638 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6639 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6640};
6641
d2dff872
CW		 6642static struct drm_framebuffer *
6643intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6644 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6645 struct drm_i915_gem_object *obj)
6646{
6647 struct intel_framebuffer *intel_fb;
6648 int ret;
6649
6650 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6651 if (!intel_fb) {
6652 drm_gem_object_unreference_unlocked(&obj->base);
6653 return ERR_PTR(-ENOMEM);
6654 }
6655
6656 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6657 if (ret) {
6658 drm_gem_object_unreference_unlocked(&obj->base);
6659 kfree(intel_fb);
6660 return ERR_PTR(ret);
6661 }
6662
6663 return &intel_fb->base;
6664}
6665
6666static u32
6667intel_framebuffer_pitch_for_width(int width, int bpp)
6668{
6669 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6670 return ALIGN(pitch, 64);
6671}
6672
6673static u32
6674intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6675{
6676 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6677 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6678}
6679
6680static struct drm_framebuffer *
6681intel_framebuffer_create_for_mode(struct drm_device *dev,
6682 struct drm_display_mode *mode,
6683 int depth, int bpp)
6684{
6685 struct drm_i915_gem_object *obj;
308e5bcb 6686 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6687
6688 obj = i915_gem_alloc_object(dev,
6689 intel_framebuffer_size_for_mode(mode, bpp));
6690 if (obj == NULL)
6691 return ERR_PTR(-ENOMEM);
6692
6693 mode_cmd.width = mode->hdisplay;
6694 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6695 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6696 bpp);
5ca0c34a 6697 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6698
6699 return intel_framebuffer_create(dev, &mode_cmd, obj);
6700}
6701
6702static struct drm_framebuffer *
6703mode_fits_in_fbdev(struct drm_device *dev,
6704 struct drm_display_mode *mode)
6705{
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707 struct drm_i915_gem_object *obj;
6708 struct drm_framebuffer *fb;
6709
6710 if (dev_priv->fbdev == NULL)
6711 return NULL;
6712
6713 obj = dev_priv->fbdev->ifb.obj;
6714 if (obj == NULL)
6715 return NULL;
6716
6717 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6718 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6719 fb->bits_per_pixel))
d2dff872
CW		 6720 return NULL;
6721
01f2c773 6722 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6723 return NULL;
6724
6725 return fb;
6726}
6727
7173188d
CW		 6728bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6729 struct drm_connector *connector,
6730 struct drm_display_mode *mode,
8261b191 6731 struct intel_load_detect_pipe *old)
79e53945
JB		 6732{
6733 struct intel_crtc *intel_crtc;
6734 struct drm_crtc *possible_crtc;
4ef69c7a 6735 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6736 struct drm_crtc *crtc = NULL;
6737 struct drm_device *dev = encoder->dev;
d2dff872 6738 struct drm_framebuffer *old_fb;
79e53945
JB		 6739 int i = -1;
6740
d2dff872
CW		 6741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6742 connector->base.id, drm_get_connector_name(connector),
6743 encoder->base.id, drm_get_encoder_name(encoder));
6744
79e53945
JB		 6745 /*
6746 * Algorithm gets a little messy:
7a5e4805 6747 *
79e53945
JB		 6748 * - if the connector already has an assigned crtc, use it (but make
6749 * sure it's on first)
7a5e4805 6750 *
79e53945
JB		 6751 * - try to find the first unused crtc that can drive this connector,
6752 * and use that if we find one
79e53945
JB		 6753 */
6754
6755 /* See if we already have a CRTC for this connector */
6756 if (encoder->crtc) {
6757 crtc = encoder->crtc;
8261b191 6758
79e53945 6759 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6760 old->dpms_mode = intel_crtc->dpms_mode;
6761 old->load_detect_temp = false;
6762
6763 /* Make sure the crtc and connector are running */
79e53945 6764 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6765 struct drm_encoder_helper_funcs *encoder_funcs;
6766 struct drm_crtc_helper_funcs *crtc_funcs;
6767
79e53945
JB		 6768 crtc_funcs = crtc->helper_private;
6769 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6770
6771 encoder_funcs = encoder->helper_private;
79e53945
JB		 6772 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6773 }
8261b191 6774
7173188d 6775 return true;
79e53945
JB		 6776 }
6777
6778 /* Find an unused one (if possible) */
6779 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6780 i++;
6781 if (!(encoder->possible_crtcs & (1 << i)))
6782 continue;
6783 if (!possible_crtc->enabled) {
6784 crtc = possible_crtc;
6785 break;
6786 }
79e53945
JB		 6787 }
6788
6789 /*
6790 * If we didn't find an unused CRTC, don't use any.
6791 */
6792 if (!crtc) {
7173188d
CW		 6793 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6794 return false;
79e53945
JB		 6795 }
6796
6797 encoder->crtc = crtc;
c1c43977 6798 connector->encoder = encoder;
79e53945
JB		 6799
6800 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6801 old->dpms_mode = intel_crtc->dpms_mode;
6802 old->load_detect_temp = true;
d2dff872 6803 old->release_fb = NULL;
79e53945 6804
6492711d
CW		 6805 if (!mode)
6806 mode = &load_detect_mode;
79e53945 6807
d2dff872
CW		 6808 old_fb = crtc->fb;
6809
6810 /* We need a framebuffer large enough to accommodate all accesses
6811 * that the plane may generate whilst we perform load detection.
6812 * We can not rely on the fbcon either being present (we get called
6813 * during its initialisation to detect all boot displays, or it may
6814 * not even exist) or that it is large enough to satisfy the
6815 * requested mode.
6816 */
6817 crtc->fb = mode_fits_in_fbdev(dev, mode);
6818 if (crtc->fb == NULL) {
6819 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6820 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6821 old->release_fb = crtc->fb;
6822 } else
6823 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6824 if (IS_ERR(crtc->fb)) {
6825 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6826 crtc->fb = old_fb;
6827 return false;
79e53945 6828 }
79e53945 6829
d2dff872 6830 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6831 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6832 if (old->release_fb)
6833 old->release_fb->funcs->destroy(old->release_fb);
6834 crtc->fb = old_fb;
6492711d 6835 return false;
79e53945 6836 }
7173188d 6837
79e53945 6838 /* let the connector get through one full cycle before testing */
9d0498a2 6839 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6840
7173188d 6841 return true;
79e53945
JB		 6842}
6843
c1c43977 6844void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6845 struct drm_connector *connector,
6846 struct intel_load_detect_pipe *old)
79e53945 6847{
4ef69c7a 6848 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6849 struct drm_device *dev = encoder->dev;
6850 struct drm_crtc *crtc = encoder->crtc;
6851 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6852 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6853
d2dff872
CW		 6854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855 connector->base.id, drm_get_connector_name(connector),
6856 encoder->base.id, drm_get_encoder_name(encoder));
6857
8261b191 6858 if (old->load_detect_temp) {
c1c43977 6859 connector->encoder = NULL;
79e53945 6860 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6861
6862 if (old->release_fb)
6863 old->release_fb->funcs->destroy(old->release_fb);
6864
0622a53c 6865 return;
79e53945
JB		 6866 }
6867
c751ce4f 6868 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6869 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6870 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6871 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6872 }
6873}
6874
6875/* Returns the clock of the currently programmed mode of the given pipe. */
6876static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6877{
6878 struct drm_i915_private *dev_priv = dev->dev_private;
6879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6880 int pipe = intel_crtc->pipe;
548f245b 6881 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6882 u32 fp;
6883 intel_clock_t clock;
6884
6885 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6886 fp = I915_READ(FP0(pipe));
79e53945 6887 else
39adb7a5 6888 fp = I915_READ(FP1(pipe));
79e53945
JB		 6889
6890 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6891 if (IS_PINEVIEW(dev)) {
6892 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6893 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6894 } else {
6895 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6896 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6897 }
6898
a6c45cf0 6899 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6900 if (IS_PINEVIEW(dev))
6901 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6902 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6903 else
6904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6905 DPLL_FPA01_P1_POST_DIV_SHIFT);
6906
6907 switch (dpll & DPLL_MODE_MASK) {
6908 case DPLLB_MODE_DAC_SERIAL:
6909 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6910 5 : 10;
6911 break;
6912 case DPLLB_MODE_LVDS:
6913 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6914 7 : 14;
6915 break;
6916 default:
28c97730 6917 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6918 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6919 return 0;
6920 }
6921
6922 /* XXX: Handle the 100Mhz refclk */
2177832f 6923 intel_clock(dev, 96000, &clock);
79e53945
JB		 6924 } else {
6925 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6926
6927 if (is_lvds) {
6928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6929 DPLL_FPA01_P1_POST_DIV_SHIFT);
6930 clock.p2 = 14;
6931
6932 if ((dpll & PLL_REF_INPUT_MASK) ==
6933 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6934 /* XXX: might not be 66MHz */
2177832f 6935 intel_clock(dev, 66000, &clock);
79e53945 6936 } else
2177832f 6937 intel_clock(dev, 48000, &clock);
79e53945
JB		 6938 } else {
6939 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6940 clock.p1 = 2;
6941 else {
6942 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6943 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6944 }
6945 if (dpll & PLL_P2_DIVIDE_BY_4)
6946 clock.p2 = 4;
6947 else
6948 clock.p2 = 2;
6949
2177832f 6950 intel_clock(dev, 48000, &clock);
79e53945
JB		 6951 }
6952 }
6953
6954 /* XXX: It would be nice to validate the clocks, but we can't reuse
6955 * i830PllIsValid() because it relies on the xf86_config connector
6956 * configuration being accurate, which it isn't necessarily.
6957 */
6958
6959 return clock.dot;
6960}
6961
6962/** Returns the currently programmed mode of the given pipe. */
6963struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6964 struct drm_crtc *crtc)
6965{
548f245b 6966 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968 int pipe = intel_crtc->pipe;
6969 struct drm_display_mode *mode;
548f245b
JB		 6970 int htot = I915_READ(HTOTAL(pipe));
6971 int hsync = I915_READ(HSYNC(pipe));
6972 int vtot = I915_READ(VTOTAL(pipe));
6973 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6974
6975 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6976 if (!mode)
6977 return NULL;
6978
6979 mode->clock = intel_crtc_clock_get(dev, crtc);
6980 mode->hdisplay = (htot & 0xffff) + 1;
6981 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6982 mode->hsync_start = (hsync & 0xffff) + 1;
6983 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6984 mode->vdisplay = (vtot & 0xffff) + 1;
6985 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6986 mode->vsync_start = (vsync & 0xffff) + 1;
6987 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6988
6989 drm_mode_set_name(mode);
6990 drm_mode_set_crtcinfo(mode, 0);
6991
6992 return mode;
6993}
6994
652c393a
JB		 6995#define GPU_IDLE_TIMEOUT 500 /* ms */
6996
6997/* When this timer fires, we've been idle for awhile */
6998static void intel_gpu_idle_timer(unsigned long arg)
6999{
7000 struct drm_device *dev = (struct drm_device *)arg;
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7002
ff7ea4c0
CW		 7003 if (!list_empty(&dev_priv->mm.active_list)) {
7004 /* Still processing requests, so just re-arm the timer. */
7005 mod_timer(&dev_priv->idle_timer, jiffies +
7006 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7007 return;
7008 }
652c393a 7009
ff7ea4c0 7010 dev_priv->busy = false;
01dfba93 7011 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 7012}
7013
652c393a
JB		 7014#define CRTC_IDLE_TIMEOUT 1000 /* ms */
7015
7016static void intel_crtc_idle_timer(unsigned long arg)
7017{
7018 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7019 struct drm_crtc *crtc = &intel_crtc->base;
7020 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 7021 struct intel_framebuffer *intel_fb;
652c393a 7022
ff7ea4c0
CW		 7023 intel_fb = to_intel_framebuffer(crtc->fb);
7024 if (intel_fb && intel_fb->obj->active) {
7025 /* The framebuffer is still being accessed by the GPU. */
7026 mod_timer(&intel_crtc->idle_timer, jiffies +
7027 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7028 return;
7029 }
652c393a 7030
ff7ea4c0 7031 intel_crtc->busy = false;
01dfba93 7032 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 7033}
7034
3dec0095 7035static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7036{
7037 struct drm_device *dev = crtc->dev;
7038 drm_i915_private_t *dev_priv = dev->dev_private;
7039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7041 int dpll_reg = DPLL(pipe);
7042 int dpll;
652c393a 7043
bad720ff 7044 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7045 return;
7046
7047 if (!dev_priv->lvds_downclock_avail)
7048 return;
7049
dbdc6479 7050 dpll = I915_READ(dpll_reg);
652c393a 7051 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7052 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7053
8ac5a6d5 7054 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7055
7056 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7057 I915_WRITE(dpll_reg, dpll);
9d0498a2 7058 intel_wait_for_vblank(dev, pipe);
dbdc6479 7059
652c393a
JB		 7060 dpll = I915_READ(dpll_reg);
7061 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7062 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 7063 }
7064
7065 /* Schedule downclock */
3dec0095
DV		 7066 mod_timer(&intel_crtc->idle_timer, jiffies +
7067 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7068}
7069
7070static void intel_decrease_pllclock(struct drm_crtc *crtc)
7071{
7072 struct drm_device *dev = crtc->dev;
7073 drm_i915_private_t *dev_priv = dev->dev_private;
7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7075 int pipe = intel_crtc->pipe;
9db4a9c7 7076 int dpll_reg = DPLL(pipe);
652c393a
JB		 7077 int dpll = I915_READ(dpll_reg);
7078
bad720ff 7079 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7080 return;
7081
7082 if (!dev_priv->lvds_downclock_avail)
7083 return;
7084
7085 /*
7086 * Since this is called by a timer, we should never get here in
7087 * the manual case.
7088 */
7089 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7090 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7091
8ac5a6d5 7092 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7093
7094 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
9d0498a2 7096 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7097 dpll = I915_READ(dpll_reg);
7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7100 }
7101
7102}
7103
7104/**
7105 * intel_idle_update - adjust clocks for idleness
7106 * @work: work struct
7107 *
7108 * Either the GPU or display (or both) went idle. Check the busy status
7109 * here and adjust the CRTC and GPU clocks as necessary.
7110 */
7111static void intel_idle_update(struct work_struct *work)
7112{
7113 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7114 idle_work);
7115 struct drm_device *dev = dev_priv->dev;
7116 struct drm_crtc *crtc;
7117 struct intel_crtc *intel_crtc;
7118
7119 if (!i915_powersave)
7120 return;
7121
7122 mutex_lock(&dev->struct_mutex);
7123
7648fa99
JB		 7124 i915_update_gfx_val(dev_priv);
7125
652c393a
JB		 7126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7127 /* Skip inactive CRTCs */
7128 if (!crtc->fb)
7129 continue;
7130
7131 intel_crtc = to_intel_crtc(crtc);
7132 if (!intel_crtc->busy)
7133 intel_decrease_pllclock(crtc);
7134 }
7135
45ac22c8 7136
652c393a
JB		 7137 mutex_unlock(&dev->struct_mutex);
7138}
7139
7140/**
7141 * intel_mark_busy - mark the GPU and possibly the display busy
7142 * @dev: drm device
7143 * @obj: object we're operating on
7144 *
7145 * Callers can use this function to indicate that the GPU is busy processing
7146 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7147 * buffer), we'll also mark the display as busy, so we know to increase its
7148 * clock frequency.
7149 */
05394f39 7150void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7151{
7152 drm_i915_private_t *dev_priv = dev->dev_private;
7153 struct drm_crtc *crtc = NULL;
7154 struct intel_framebuffer *intel_fb;
7155 struct intel_crtc *intel_crtc;
7156
5e17ee74
ZW		 7157 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7158 return;
7159
18b2190c 7160 if (!dev_priv->busy)
28cf798f 7161 dev_priv->busy = true;
18b2190c 7162 else
28cf798f
CW		 7163 mod_timer(&dev_priv->idle_timer, jiffies +
7164 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7165
7166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7167 if (!crtc->fb)
7168 continue;
7169
7170 intel_crtc = to_intel_crtc(crtc);
7171 intel_fb = to_intel_framebuffer(crtc->fb);
7172 if (intel_fb->obj == obj) {
7173 if (!intel_crtc->busy) {
7174 /* Non-busy -> busy, upclock */
3dec0095 7175 intel_increase_pllclock(crtc);
652c393a
JB		 7176 intel_crtc->busy = true;
7177 } else {
7178 /* Busy -> busy, put off timer */
7179 mod_timer(&intel_crtc->idle_timer, jiffies +
7180 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7181 }
7182 }
7183 }
7184}
7185
79e53945
JB		 7186static void intel_crtc_destroy(struct drm_crtc *crtc)
7187{
7188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7189 struct drm_device *dev = crtc->dev;
7190 struct intel_unpin_work *work;
7191 unsigned long flags;
7192
7193 spin_lock_irqsave(&dev->event_lock, flags);
7194 work = intel_crtc->unpin_work;
7195 intel_crtc->unpin_work = NULL;
7196 spin_unlock_irqrestore(&dev->event_lock, flags);
7197
7198 if (work) {
7199 cancel_work_sync(&work->work);
7200 kfree(work);
7201 }
79e53945
JB		 7202
7203 drm_crtc_cleanup(crtc);
67e77c5a 7204
79e53945
JB		 7205 kfree(intel_crtc);
7206}
7207
6b95a207
KH		 7208static void intel_unpin_work_fn(struct work_struct *__work)
7209{
7210 struct intel_unpin_work *work =
7211 container_of(__work, struct intel_unpin_work, work);
7212
7213 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7214 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7215 drm_gem_object_unreference(&work->pending_flip_obj->base);
7216 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7217
7782de3b 7218 intel_update_fbc(work->dev);
6b95a207
KH		 7219 mutex_unlock(&work->dev->struct_mutex);
7220 kfree(work);
7221}
7222
1afe3e9d 7223static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7224 struct drm_crtc *crtc)
6b95a207
KH		 7225{
7226 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7228 struct intel_unpin_work *work;
05394f39 7229 struct drm_i915_gem_object *obj;
6b95a207 7230 struct drm_pending_vblank_event *e;
49b14a5c 7231 struct timeval tnow, tvbl;
6b95a207
KH		 7232 unsigned long flags;
7233
7234 /* Ignore early vblank irqs */
7235 if (intel_crtc == NULL)
7236 return;
7237
49b14a5c
MK		 7238 do_gettimeofday(&tnow);
7239
6b95a207
KH		 7240 spin_lock_irqsave(&dev->event_lock, flags);
7241 work = intel_crtc->unpin_work;
7242 if (work == NULL || !work->pending) {
7243 spin_unlock_irqrestore(&dev->event_lock, flags);
7244 return;
7245 }
7246
7247 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7248
7249 if (work->event) {
7250 e = work->event;
49b14a5c 7251 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7252
7253 /* Called before vblank count and timestamps have
7254 * been updated for the vblank interval of flip
7255 * completion? Need to increment vblank count and
7256 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7257 * to account for this. We assume this happened if we
7258 * get called over 0.9 frame durations after the last
7259 * timestamped vblank.
7260 *
7261 * This calculation can not be used with vrefresh rates
7262 * below 5Hz (10Hz to be on the safe side) without
7263 * promoting to 64 integers.
0af7e4df 7264 */
49b14a5c
MK		 7265 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7266 9 * crtc->framedur_ns) {
0af7e4df 7267 e->event.sequence++;
49b14a5c
MK		 7268 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7269 crtc->framedur_ns);
0af7e4df
MK		 7270 }
7271
49b14a5c
MK		 7272 e->event.tv_sec = tvbl.tv_sec;
7273 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7274
6b95a207
KH		 7275 list_add_tail(&e->base.link,
7276 &e->base.file_priv->event_list);
7277 wake_up_interruptible(&e->base.file_priv->event_wait);
7278 }
7279
0af7e4df
MK		 7280 drm_vblank_put(dev, intel_crtc->pipe);
7281
6b95a207
KH		 7282 spin_unlock_irqrestore(&dev->event_lock, flags);
7283
05394f39 7284 obj = work->old_fb_obj;
d9e86c0e 7285
e59f2bac 7286 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7287 &obj->pending_flip.counter);
7288 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7289 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7290
6b95a207 7291 schedule_work(&work->work);
e5510fac
JB		 7292
7293 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7294}
7295
1afe3e9d
JB		 7296void intel_finish_page_flip(struct drm_device *dev, int pipe)
7297{
7298 drm_i915_private_t *dev_priv = dev->dev_private;
7299 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7300
49b14a5c 7301 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7302}
7303
7304void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7305{
7306 drm_i915_private_t *dev_priv = dev->dev_private;
7307 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7308
49b14a5c 7309 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7310}
7311
6b95a207
KH		 7312void intel_prepare_page_flip(struct drm_device *dev, int plane)
7313{
7314 drm_i915_private_t *dev_priv = dev->dev_private;
7315 struct intel_crtc *intel_crtc =
7316 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7317 unsigned long flags;
7318
7319 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7320 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7321 if ((++intel_crtc->unpin_work->pending) > 1)
7322 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7323 } else {
7324 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7325 }
6b95a207
KH		 7326 spin_unlock_irqrestore(&dev->event_lock, flags);
7327}
7328
8c9f3aaf
JB		 7329static int intel_gen2_queue_flip(struct drm_device *dev,
7330 struct drm_crtc *crtc,
7331 struct drm_framebuffer *fb,
7332 struct drm_i915_gem_object *obj)
7333{
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7336 unsigned long offset;
7337 u32 flip_mask;
7338 int ret;
7339
7340 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7341 if (ret)
7342 goto out;
7343
7344 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7345 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7346
7347 ret = BEGIN_LP_RING(6);
7348 if (ret)
7349 goto out;
7350
7351 /* Can't queue multiple flips, so wait for the previous
7352 * one to finish before executing the next.
7353 */
7354 if (intel_crtc->plane)
7355 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7356 else
7357 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7358 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7359 OUT_RING(MI_NOOP);
7360 OUT_RING(MI_DISPLAY_FLIP |
7361 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7362 OUT_RING(fb->pitches[0]);
8c9f3aaf 7363 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7364 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7365 ADVANCE_LP_RING();
7366out:
7367 return ret;
7368}
7369
7370static int intel_gen3_queue_flip(struct drm_device *dev,
7371 struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_i915_gem_object *obj)
7374{
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7377 unsigned long offset;
7378 u32 flip_mask;
7379 int ret;
7380
7381 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7382 if (ret)
7383 goto out;
7384
7385 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7386 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7387
7388 ret = BEGIN_LP_RING(6);
7389 if (ret)
7390 goto out;
7391
7392 if (intel_crtc->plane)
7393 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7394 else
7395 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7396 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7397 OUT_RING(MI_NOOP);
7398 OUT_RING(MI_DISPLAY_FLIP_I915 |
7399 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7400 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7401 OUT_RING(obj->gtt_offset + offset);
7402 OUT_RING(MI_NOOP);
7403
7404 ADVANCE_LP_RING();
7405out:
7406 return ret;
7407}
7408
7409static int intel_gen4_queue_flip(struct drm_device *dev,
7410 struct drm_crtc *crtc,
7411 struct drm_framebuffer *fb,
7412 struct drm_i915_gem_object *obj)
7413{
7414 struct drm_i915_private *dev_priv = dev->dev_private;
7415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416 uint32_t pf, pipesrc;
7417 int ret;
7418
7419 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7420 if (ret)
7421 goto out;
7422
7423 ret = BEGIN_LP_RING(4);
7424 if (ret)
7425 goto out;
7426
7427 /* i965+ uses the linear or tiled offsets from the
7428 * Display Registers (which do not change across a page-flip)
7429 * so we need only reprogram the base address.
7430 */
7431 OUT_RING(MI_DISPLAY_FLIP |
7432 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7433 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7434 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7435
7436 /* XXX Enabling the panel-fitter across page-flip is so far
7437 * untested on non-native modes, so ignore it for now.
7438 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7439 */
7440 pf = 0;
7441 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7442 OUT_RING(pf | pipesrc);
7443 ADVANCE_LP_RING();
7444out:
7445 return ret;
7446}
7447
7448static int intel_gen6_queue_flip(struct drm_device *dev,
7449 struct drm_crtc *crtc,
7450 struct drm_framebuffer *fb,
7451 struct drm_i915_gem_object *obj)
7452{
7453 struct drm_i915_private *dev_priv = dev->dev_private;
7454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7455 uint32_t pf, pipesrc;
7456 int ret;
7457
7458 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7459 if (ret)
7460 goto out;
7461
7462 ret = BEGIN_LP_RING(4);
7463 if (ret)
7464 goto out;
7465
7466 OUT_RING(MI_DISPLAY_FLIP |
7467 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7468 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7469 OUT_RING(obj->gtt_offset);
7470
99d9acdd
CW		 7471 /* Contrary to the suggestions in the documentation,
7472 * "Enable Panel Fitter" does not seem to be required when page
7473 * flipping with a non-native mode, and worse causes a normal
7474 * modeset to fail.
7475 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7476 */
7477 pf = 0;
8c9f3aaf
JB		 7478 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7479 OUT_RING(pf | pipesrc);
7480 ADVANCE_LP_RING();
7481out:
7482 return ret;
7483}
7484
7c9017e5
JB		 7485/*
7486 * On gen7 we currently use the blit ring because (in early silicon at least)
7487 * the render ring doesn't give us interrpts for page flip completion, which
7488 * means clients will hang after the first flip is queued. Fortunately the
7489 * blit ring generates interrupts properly, so use it instead.
7490 */
7491static int intel_gen7_queue_flip(struct drm_device *dev,
7492 struct drm_crtc *crtc,
7493 struct drm_framebuffer *fb,
7494 struct drm_i915_gem_object *obj)
7495{
7496 struct drm_i915_private *dev_priv = dev->dev_private;
7497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7498 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7499 int ret;
7500
7501 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7502 if (ret)
7503 goto out;
7504
7505 ret = intel_ring_begin(ring, 4);
7506 if (ret)
7507 goto out;
7508
7509 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7510 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7511 intel_ring_emit(ring, (obj->gtt_offset));
7512 intel_ring_emit(ring, (MI_NOOP));
7513 intel_ring_advance(ring);
7514out:
7515 return ret;
7516}
7517
8c9f3aaf
JB		 7518static int intel_default_queue_flip(struct drm_device *dev,
7519 struct drm_crtc *crtc,
7520 struct drm_framebuffer *fb,
7521 struct drm_i915_gem_object *obj)
7522{
7523 return -ENODEV;
7524}
7525
6b95a207
KH		 7526static int intel_crtc_page_flip(struct drm_crtc *crtc,
7527 struct drm_framebuffer *fb,
7528 struct drm_pending_vblank_event *event)
7529{
7530 struct drm_device *dev = crtc->dev;
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7532 struct intel_framebuffer *intel_fb;
05394f39 7533 struct drm_i915_gem_object *obj;
6b95a207
KH		 7534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7535 struct intel_unpin_work *work;
8c9f3aaf 7536 unsigned long flags;
52e68630 7537 int ret;
6b95a207
KH		 7538
7539 work = kzalloc(sizeof *work, GFP_KERNEL);
7540 if (work == NULL)
7541 return -ENOMEM;
7542
6b95a207
KH		 7543 work->event = event;
7544 work->dev = crtc->dev;
7545 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7546 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7547 INIT_WORK(&work->work, intel_unpin_work_fn);
7548
7317c75e
JB		 7549 ret = drm_vblank_get(dev, intel_crtc->pipe);
7550 if (ret)
7551 goto free_work;
7552
6b95a207
KH		 7553 /* We borrow the event spin lock for protecting unpin_work */
7554 spin_lock_irqsave(&dev->event_lock, flags);
7555 if (intel_crtc->unpin_work) {
7556 spin_unlock_irqrestore(&dev->event_lock, flags);
7557 kfree(work);
7317c75e 7558 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7559
7560 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7561 return -EBUSY;
7562 }
7563 intel_crtc->unpin_work = work;
7564 spin_unlock_irqrestore(&dev->event_lock, flags);
7565
7566 intel_fb = to_intel_framebuffer(fb);
7567 obj = intel_fb->obj;
7568
468f0b44 7569 mutex_lock(&dev->struct_mutex);
6b95a207 7570
75dfca80 7571 /* Reference the objects for the scheduled work. */
05394f39
CW		 7572 drm_gem_object_reference(&work->old_fb_obj->base);
7573 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7574
7575 crtc->fb = fb;
96b099fd 7576
e1f99ce6 7577 work->pending_flip_obj = obj;
e1f99ce6 7578
4e5359cd
SF		 7579 work->enable_stall_check = true;
7580
e1f99ce6
CW		 7581 /* Block clients from rendering to the new back buffer until
7582 * the flip occurs and the object is no longer visible.
7583 */
05394f39 7584 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7585
8c9f3aaf
JB		 7586 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7587 if (ret)
7588 goto cleanup_pending;
6b95a207 7589
7782de3b 7590 intel_disable_fbc(dev);
6b95a207
KH		 7591 mutex_unlock(&dev->struct_mutex);
7592
e5510fac
JB		 7593 trace_i915_flip_request(intel_crtc->plane, obj);
7594
6b95a207 7595 return 0;
96b099fd 7596
8c9f3aaf
JB		 7597cleanup_pending:
7598 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7599 drm_gem_object_unreference(&work->old_fb_obj->base);
7600 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7601 mutex_unlock(&dev->struct_mutex);
7602
7603 spin_lock_irqsave(&dev->event_lock, flags);
7604 intel_crtc->unpin_work = NULL;
7605 spin_unlock_irqrestore(&dev->event_lock, flags);
7606
7317c75e
JB		 7607 drm_vblank_put(dev, intel_crtc->pipe);
7608free_work:
96b099fd
CW		 7609 kfree(work);
7610
7611 return ret;
6b95a207
KH		 7612}
7613
47f1c6c9
CW		 7614static void intel_sanitize_modesetting(struct drm_device *dev,
7615 int pipe, int plane)
7616{
7617 struct drm_i915_private *dev_priv = dev->dev_private;
7618 u32 reg, val;
7619
f47166d2
CW		 7620 /* Clear any frame start delays used for debugging left by the BIOS */
7621 for_each_pipe(pipe) {
7622 reg = PIPECONF(pipe);
7623 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7624 }
7625
47f1c6c9
CW		 7626 if (HAS_PCH_SPLIT(dev))
7627 return;
7628
7629 /* Who knows what state these registers were left in by the BIOS or
7630 * grub?
7631 *
7632 * If we leave the registers in a conflicting state (e.g. with the
7633 * display plane reading from the other pipe than the one we intend
7634 * to use) then when we attempt to teardown the active mode, we will
7635 * not disable the pipes and planes in the correct order -- leaving
7636 * a plane reading from a disabled pipe and possibly leading to
7637 * undefined behaviour.
7638 */
7639
7640 reg = DSPCNTR(plane);
7641 val = I915_READ(reg);
7642
7643 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7644 return;
7645 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7646 return;
7647
7648 /* This display plane is active and attached to the other CPU pipe. */
7649 pipe = !pipe;
7650
7651 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7652 intel_disable_plane(dev_priv, plane, pipe);
7653 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7654}
79e53945 7655
f6e5b160
CW		 7656static void intel_crtc_reset(struct drm_crtc *crtc)
7657{
7658 struct drm_device *dev = crtc->dev;
7659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7660
7661 /* Reset flags back to the 'unknown' status so that they
7662 * will be correctly set on the initial modeset.
7663 */
7664 intel_crtc->dpms_mode = -1;
7665
7666 /* We need to fix up any BIOS configuration that conflicts with
7667 * our expectations.
7668 */
7669 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7670}
7671
7672static struct drm_crtc_helper_funcs intel_helper_funcs = {
7673 .dpms = intel_crtc_dpms,
7674 .mode_fixup = intel_crtc_mode_fixup,
7675 .mode_set = intel_crtc_mode_set,
7676 .mode_set_base = intel_pipe_set_base,
7677 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7678 .load_lut = intel_crtc_load_lut,
7679 .disable = intel_crtc_disable,
7680};
7681
7682static const struct drm_crtc_funcs intel_crtc_funcs = {
7683 .reset = intel_crtc_reset,
7684 .cursor_set = intel_crtc_cursor_set,
7685 .cursor_move = intel_crtc_cursor_move,
7686 .gamma_set = intel_crtc_gamma_set,
7687 .set_config = drm_crtc_helper_set_config,
7688 .destroy = intel_crtc_destroy,
7689 .page_flip = intel_crtc_page_flip,
7690};
7691
b358d0a6 7692static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7693{
22fd0fab 7694 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7695 struct intel_crtc *intel_crtc;
7696 int i;
7697
7698 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7699 if (intel_crtc == NULL)
7700 return;
7701
7702 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7703
7704 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7705 for (i = 0; i < 256; i++) {
7706 intel_crtc->lut_r[i] = i;
7707 intel_crtc->lut_g[i] = i;
7708 intel_crtc->lut_b[i] = i;
7709 }
7710
80824003
JB		 7711 /* Swap pipes & planes for FBC on pre-965 */
7712 intel_crtc->pipe = pipe;
7713 intel_crtc->plane = pipe;
e2e767ab 7714 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7715 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7716 intel_crtc->plane = !pipe;
80824003
JB		 7717 }
7718
22fd0fab
JB		 7719 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7720 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7721 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7722 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7723
5d1d0cc8 7724 intel_crtc_reset(&intel_crtc->base);
04dbff52 7725 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7726 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7727
7728 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7729 if (pipe == 2 && IS_IVYBRIDGE(dev))
7730 intel_crtc->no_pll = true;
7e7d76c3
JB		 7731 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7732 intel_helper_funcs.commit = ironlake_crtc_commit;
7733 } else {
7734 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7735 intel_helper_funcs.commit = i9xx_crtc_commit;
7736 }
7737
79e53945
JB		 7738 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7739
652c393a
JB		 7740 intel_crtc->busy = false;
7741
7742 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7743 (unsigned long)intel_crtc);
79e53945
JB		 7744}
7745
08d7b3d1 7746int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7747 struct drm_file *file)
08d7b3d1
CW		 7748{
7749 drm_i915_private_t *dev_priv = dev->dev_private;
7750 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7751 struct drm_mode_object *drmmode_obj;
7752 struct intel_crtc *crtc;
08d7b3d1
CW		 7753
7754 if (!dev_priv) {
7755 DRM_ERROR("called with no initialization\n");
7756 return -EINVAL;
7757 }
7758
c05422d5
DV		 7759 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7760 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7761
c05422d5 7762 if (!drmmode_obj) {
08d7b3d1
CW		 7763 DRM_ERROR("no such CRTC id\n");
7764 return -EINVAL;
7765 }
7766
c05422d5
DV		 7767 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7768 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7769
c05422d5 7770 return 0;
08d7b3d1
CW		 7771}
7772
c5e4df33 7773static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7774{
4ef69c7a 7775 struct intel_encoder *encoder;
79e53945 7776 int index_mask = 0;
79e53945
JB		 7777 int entry = 0;
7778
4ef69c7a
CW		 7779 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7780 if (type_mask & encoder->clone_mask)
79e53945
JB		 7781 index_mask |= (1 << entry);
7782 entry++;
7783 }
4ef69c7a 7784
79e53945
JB		 7785 return index_mask;
7786}
7787
4d302442
CW		 7788static bool has_edp_a(struct drm_device *dev)
7789{
7790 struct drm_i915_private *dev_priv = dev->dev_private;
7791
7792 if (!IS_MOBILE(dev))
7793 return false;
7794
7795 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7796 return false;
7797
7798 if (IS_GEN5(dev) &&
7799 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7800 return false;
7801
7802 return true;
7803}
7804
79e53945
JB		 7805static void intel_setup_outputs(struct drm_device *dev)
7806{
725e30ad 7807 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7808 struct intel_encoder *encoder;
cb0953d7 7809 bool dpd_is_edp = false;
f3cfcba6 7810 bool has_lvds;
79e53945 7811
f3cfcba6 7812 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7813 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7814 /* disable the panel fitter on everything but LVDS */
7815 I915_WRITE(PFIT_CONTROL, 0);
7816 }
79e53945 7817
bad720ff 7818 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7819 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7820
4d302442 7821 if (has_edp_a(dev))
32f9d658
ZW		 7822 intel_dp_init(dev, DP_A);
7823
cb0953d7
AJ		 7824 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7825 intel_dp_init(dev, PCH_DP_D);
7826 }
7827
7828 intel_crt_init(dev);
7829
7830 if (HAS_PCH_SPLIT(dev)) {
7831 int found;
7832
30ad48b7 7833 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7834 /* PCH SDVOB multiplex with HDMIB */
7835 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7836 if (!found)
7837 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7838 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7839 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7840 }
7841
7842 if (I915_READ(HDMIC) & PORT_DETECTED)
7843 intel_hdmi_init(dev, HDMIC);
7844
7845 if (I915_READ(HDMID) & PORT_DETECTED)
7846 intel_hdmi_init(dev, HDMID);
7847
5eb08b69
ZW		 7848 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7849 intel_dp_init(dev, PCH_DP_C);
7850
cb0953d7 7851 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7852 intel_dp_init(dev, PCH_DP_D);
7853
103a196f 7854 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7855 bool found = false;
7d57382e 7856
725e30ad 7857 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7858 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7859 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7860 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7861 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7862 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7863 }
27185ae1 7864
b01f2c3a
JB		 7865 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7866 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7867 intel_dp_init(dev, DP_B);
b01f2c3a 7868 }
725e30ad 7869 }
13520b05
KH		 7870
7871 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7872
b01f2c3a
JB		 7873 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7874 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7875 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7876 }
27185ae1
ML		 7877
7878 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7879
b01f2c3a
JB		 7880 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7881 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7882 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7883 }
7884 if (SUPPORTS_INTEGRATED_DP(dev)) {
7885 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7886 intel_dp_init(dev, DP_C);
b01f2c3a 7887 }
725e30ad 7888 }
27185ae1 7889
b01f2c3a
JB		 7890 if (SUPPORTS_INTEGRATED_DP(dev) &&
7891 (I915_READ(DP_D) & DP_DETECTED)) {
7892 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7893 intel_dp_init(dev, DP_D);
b01f2c3a 7894 }
bad720ff 7895 } else if (IS_GEN2(dev))
79e53945
JB		 7896 intel_dvo_init(dev);
7897
103a196f 7898 if (SUPPORTS_TV(dev))
79e53945
JB		 7899 intel_tv_init(dev);
7900
4ef69c7a
CW		 7901 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7902 encoder->base.possible_crtcs = encoder->crtc_mask;
7903 encoder->base.possible_clones =
7904 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7905 }
47356eb6 7906
2c7111db
CW		 7907 /* disable all the possible outputs/crtcs before entering KMS mode */
7908 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7909
7910 if (HAS_PCH_SPLIT(dev))
7911 ironlake_init_pch_refclk(dev);
79e53945
JB		 7912}
7913
7914static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7915{
7916 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7917
7918 drm_framebuffer_cleanup(fb);
05394f39 7919 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7920
7921 kfree(intel_fb);
7922}
7923
7924static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7925 struct drm_file *file,
79e53945
JB		 7926 unsigned int *handle)
7927{
7928 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7929 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7930
05394f39 7931 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7932}
7933
7934static const struct drm_framebuffer_funcs intel_fb_funcs = {
7935 .destroy = intel_user_framebuffer_destroy,
7936 .create_handle = intel_user_framebuffer_create_handle,
7937};
7938
38651674
DA		 7939int intel_framebuffer_init(struct drm_device *dev,
7940 struct intel_framebuffer *intel_fb,
308e5bcb 7941 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7942 struct drm_i915_gem_object *obj)
79e53945 7943{
79e53945
JB		 7944 int ret;
7945
05394f39 7946 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7947 return -EINVAL;
7948
308e5bcb 7949 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7950 return -EINVAL;
7951
308e5bcb 7952 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7953 case DRM_FORMAT_RGB332:
7954 case DRM_FORMAT_RGB565:
7955 case DRM_FORMAT_XRGB8888:
b250da79 7956 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7957 case DRM_FORMAT_ARGB8888:
7958 case DRM_FORMAT_XRGB2101010:
7959 case DRM_FORMAT_ARGB2101010:
308e5bcb 7960 /* RGB formats are common across chipsets */
b5626747 7961 break;
04b3924d
VS		 7962 case DRM_FORMAT_YUYV:
7963 case DRM_FORMAT_UYVY:
7964 case DRM_FORMAT_YVYU:
7965 case DRM_FORMAT_VYUY:
57cd6508
CW		 7966 break;
7967 default:
aca25848
ED		 7968 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7969 mode_cmd->pixel_format);
57cd6508
CW		 7970 return -EINVAL;
7971 }
7972
79e53945
JB		 7973 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7974 if (ret) {
7975 DRM_ERROR("framebuffer init failed %d\n", ret);
7976 return ret;
7977 }
7978
7979 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7980 intel_fb->obj = obj;
79e53945
JB		 7981 return 0;
7982}
7983
79e53945
JB		 7984static struct drm_framebuffer *
7985intel_user_framebuffer_create(struct drm_device *dev,
7986 struct drm_file *filp,
308e5bcb 7987 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7988{
05394f39 7989 struct drm_i915_gem_object *obj;
79e53945 7990
308e5bcb
JB		 7991 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7992 mode_cmd->handles[0]));
c8725226 7993 if (&obj->base == NULL)
cce13ff7 7994 return ERR_PTR(-ENOENT);
79e53945 7995
d2dff872 7996 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7997}
7998
79e53945 7999static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8000 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8001 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8002};
8003
05394f39 8004static struct drm_i915_gem_object *
aa40d6bb 8005intel_alloc_context_page(struct drm_device *dev)
9ea8d059 8006{
05394f39 8007 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 8008 int ret;
8009
2c34b850
BW		 8010 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8011
aa40d6bb
ZN		 8012 ctx = i915_gem_alloc_object(dev, 4096);
8013 if (!ctx) {
9ea8d059
CW		 8014 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8015 return NULL;
8016 }
8017
75e9e915 8018 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 8019 if (ret) {
8020 DRM_ERROR("failed to pin power context: %d\n", ret);
8021 goto err_unref;
8022 }
8023
aa40d6bb 8024 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 8025 if (ret) {
8026 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8027 goto err_unpin;
8028 }
9ea8d059 8029
aa40d6bb 8030 return ctx;
9ea8d059
CW		 8031
8032err_unpin:
aa40d6bb 8033 i915_gem_object_unpin(ctx);
9ea8d059 8034err_unref:
05394f39 8035 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 8036 mutex_unlock(&dev->struct_mutex);
8037 return NULL;
8038}
8039
7648fa99
JB		 8040bool ironlake_set_drps(struct drm_device *dev, u8 val)
8041{
8042 struct drm_i915_private *dev_priv = dev->dev_private;
8043 u16 rgvswctl;
8044
8045 rgvswctl = I915_READ16(MEMSWCTL);
8046 if (rgvswctl & MEMCTL_CMD_STS) {
8047 DRM_DEBUG("gpu busy, RCS change rejected\n");
8048 return false; /* still busy with another command */
8049 }
8050
8051 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8052 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8053 I915_WRITE16(MEMSWCTL, rgvswctl);
8054 POSTING_READ16(MEMSWCTL);
8055
8056 rgvswctl |= MEMCTL_CMD_STS;
8057 I915_WRITE16(MEMSWCTL, rgvswctl);
8058
8059 return true;
8060}
8061
f97108d1
JB		 8062void ironlake_enable_drps(struct drm_device *dev)
8063{
8064 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8065 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 8066 u8 fmax, fmin, fstart, vstart;
f97108d1 8067
ea056c14
JB		 8068 /* Enable temp reporting */
8069 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8070 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8071
f97108d1
JB		 8072 /* 100ms RC evaluation intervals */
8073 I915_WRITE(RCUPEI, 100000);
8074 I915_WRITE(RCDNEI, 100000);
8075
8076 /* Set max/min thresholds to 90ms and 80ms respectively */
8077 I915_WRITE(RCBMAXAVG, 90000);
8078 I915_WRITE(RCBMINAVG, 80000);
8079
8080 I915_WRITE(MEMIHYST, 1);
8081
8082 /* Set up min, max, and cur for interrupt handling */
8083 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8084 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8085 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8086 MEMMODE_FSTART_SHIFT;
7648fa99 8087
f97108d1
JB		 8088 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8089 PXVFREQ_PX_SHIFT;
8090
80dbf4b7 8091 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8092 dev_priv->fstart = fstart;
8093
80dbf4b7 8094 dev_priv->max_delay = fstart;
f97108d1
JB		 8095 dev_priv->min_delay = fmin;
8096 dev_priv->cur_delay = fstart;
8097
80dbf4b7
JB		 8098 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8099 fmax, fmin, fstart);
7648fa99 8100
f97108d1
JB		 8101 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8102
8103 /*
8104 * Interrupts will be enabled in ironlake_irq_postinstall
8105 */
8106
8107 I915_WRITE(VIDSTART, vstart);
8108 POSTING_READ(VIDSTART);
8109
8110 rgvmodectl |= MEMMODE_SWMODE_EN;
8111 I915_WRITE(MEMMODECTL, rgvmodectl);
8112
481b6af3 8113 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8114 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8115 msleep(1);
8116
7648fa99 8117 ironlake_set_drps(dev, fstart);
f97108d1 8118
7648fa99
JB		 8119 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8120 I915_READ(0x112e0);
8121 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8122 dev_priv->last_count2 = I915_READ(0x112f4);
8123 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8124}
8125
8126void ironlake_disable_drps(struct drm_device *dev)
8127{
8128 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8129 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8130
8131 /* Ack interrupts, disable EFC interrupt */
8132 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8133 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8134 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8135 I915_WRITE(DEIIR, DE_PCU_EVENT);
8136 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8137
8138 /* Go back to the starting frequency */
7648fa99 8139 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8140 msleep(1);
8141 rgvswctl |= MEMCTL_CMD_STS;
8142 I915_WRITE(MEMSWCTL, rgvswctl);
8143 msleep(1);
8144
8145}
8146
3b8d8d91
JB		 8147void gen6_set_rps(struct drm_device *dev, u8 val)
8148{
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 u32 swreq;
8151
8152 swreq = (val & 0x3ff) << 25;
8153 I915_WRITE(GEN6_RPNSWREQ, swreq);
8154}
8155
8156void gen6_disable_rps(struct drm_device *dev)
8157{
8158 struct drm_i915_private *dev_priv = dev->dev_private;
8159
8160 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8161 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8162 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8163 /* Complete PM interrupt masking here doesn't race with the rps work
8164 * item again unmasking PM interrupts because that is using a different
8165 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8166 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8167
8168 spin_lock_irq(&dev_priv->rps_lock);
8169 dev_priv->pm_iir = 0;
8170 spin_unlock_irq(&dev_priv->rps_lock);
8171
3b8d8d91
JB		 8172 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8173}
8174
7648fa99
JB		 8175static unsigned long intel_pxfreq(u32 vidfreq)
8176{
8177 unsigned long freq;
8178 int div = (vidfreq & 0x3f0000) >> 16;
8179 int post = (vidfreq & 0x3000) >> 12;
8180 int pre = (vidfreq & 0x7);
8181
8182 if (!pre)
8183 return 0;
8184
8185 freq = ((div * 133333) / ((1<<post) * pre));
8186
8187 return freq;
8188}
8189
8190void intel_init_emon(struct drm_device *dev)
8191{
8192 struct drm_i915_private *dev_priv = dev->dev_private;
8193 u32 lcfuse;
8194 u8 pxw[16];
8195 int i;
8196
8197 /* Disable to program */
8198 I915_WRITE(ECR, 0);
8199 POSTING_READ(ECR);
8200
8201 /* Program energy weights for various events */
8202 I915_WRITE(SDEW, 0x15040d00);
8203 I915_WRITE(CSIEW0, 0x007f0000);
8204 I915_WRITE(CSIEW1, 0x1e220004);
8205 I915_WRITE(CSIEW2, 0x04000004);
8206
8207 for (i = 0; i < 5; i++)
8208 I915_WRITE(PEW + (i * 4), 0);
8209 for (i = 0; i < 3; i++)
8210 I915_WRITE(DEW + (i * 4), 0);
8211
8212 /* Program P-state weights to account for frequency power adjustment */
8213 for (i = 0; i < 16; i++) {
8214 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8215 unsigned long freq = intel_pxfreq(pxvidfreq);
8216 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8217 PXVFREQ_PX_SHIFT;
8218 unsigned long val;
8219
8220 val = vid * vid;
8221 val *= (freq / 1000);
8222 val *= 255;
8223 val /= (127*127*900);
8224 if (val > 0xff)
8225 DRM_ERROR("bad pxval: %ld\n", val);
8226 pxw[i] = val;
8227 }
8228 /* Render standby states get 0 weight */
8229 pxw[14] = 0;
8230 pxw[15] = 0;
8231
8232 for (i = 0; i < 4; i++) {
8233 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8234 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8235 I915_WRITE(PXW + (i * 4), val);
8236 }
8237
8238 /* Adjust magic regs to magic values (more experimental results) */
8239 I915_WRITE(OGW0, 0);
8240 I915_WRITE(OGW1, 0);
8241 I915_WRITE(EG0, 0x00007f00);
8242 I915_WRITE(EG1, 0x0000000e);
8243 I915_WRITE(EG2, 0x000e0000);
8244 I915_WRITE(EG3, 0x68000300);
8245 I915_WRITE(EG4, 0x42000000);
8246 I915_WRITE(EG5, 0x00140031);
8247 I915_WRITE(EG6, 0);
8248 I915_WRITE(EG7, 0);
8249
8250 for (i = 0; i < 8; i++)
8251 I915_WRITE(PXWL + (i * 4), 0);
8252
8253 /* Enable PMON + select events */
8254 I915_WRITE(ECR, 0x80000019);
8255
8256 lcfuse = I915_READ(LCFUSE02);
8257
8258 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8259}
8260
83b7f9ac 8261static int intel_enable_rc6(struct drm_device *dev)
c0f372b3
KP		 8262{
8263 /*
8264 * Respect the kernel parameter if it is set
8265 */
8266 if (i915_enable_rc6 >= 0)
8267 return i915_enable_rc6;
8268
8269 /*
8270 * Disable RC6 on Ironlake
8271 */
8272 if (INTEL_INFO(dev)->gen == 5)
8273 return 0;
8274
8275 /*
371de6e4 8276 * Disable rc6 on Sandybridge
c0f372b3
KP		 8277 */
8278 if (INTEL_INFO(dev)->gen == 6) {
aa464191
ED		 8279 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8280 return INTEL_RC6_ENABLE;
c0f372b3 8281 }
aa464191
ED		 8282 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8283 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
c0f372b3
KP		 8284}
8285
3b8d8d91 8286void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8287{
a6044e23
JB		 8288 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8289 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8290 u32 pcu_mbox, rc6_mask = 0;
dd202c6d 8291 u32 gtfifodbg;
a6044e23 8292 int cur_freq, min_freq, max_freq;
83b7f9ac 8293 int rc6_mode;
8fd26859
CW		 8294 int i;
8295
8296 /* Here begins a magic sequence of register writes to enable
8297 * auto-downclocking.
8298 *
8299 * Perhaps there might be some value in exposing these to
8300 * userspace...
8301 */
8302 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8303 mutex_lock(&dev_priv->dev->struct_mutex);
dd202c6d
BW		 8304
8305 /* Clear the DBG now so we don't confuse earlier errors */
8306 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8307 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8308 I915_WRITE(GTFIFODBG, gtfifodbg);
8309 }
8310
fcca7926 8311 gen6_gt_force_wake_get(dev_priv);
8fd26859 8312
3b8d8d91 8313 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8314 I915_WRITE(GEN6_RC_CONTROL, 0);
8315
8316 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8317 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8318 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8319 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8320 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8321
8322 for (i = 0; i < I915_NUM_RINGS; i++)
8323 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8324
8325 I915_WRITE(GEN6_RC_SLEEP, 0);
8326 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8327 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8328 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8329 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8330
83b7f9ac
ED		 8331 rc6_mode = intel_enable_rc6(dev_priv->dev);
8332 if (rc6_mode & INTEL_RC6_ENABLE)
8333 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8334
8335 if (rc6_mode & INTEL_RC6p_ENABLE)
8336 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8337
8338 if (rc6_mode & INTEL_RC6pp_ENABLE)
8339 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8340
8341 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8342 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8343 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8344 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
7df8721b 8345
8fd26859 8346 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8347 rc6_mask |
9c3d2f7f 8348 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8349 GEN6_RC_CTL_HW_ENABLE);
8350
3b8d8d91 8351 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8352 GEN6_FREQUENCY(10) |
8353 GEN6_OFFSET(0) |
8354 GEN6_AGGRESSIVE_TURBO);
8355 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8356 GEN6_FREQUENCY(12));
8357
8358 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8359 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8360 18 << 24 |
8361 6 << 16);
ccab5c82
JB		 8362 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8363 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8364 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8365 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8366 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8367 I915_WRITE(GEN6_RP_CONTROL,
8368 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8369 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8370 GEN6_RP_MEDIA_IS_GFX |
8371 GEN6_RP_ENABLE |
ccab5c82
JB		 8372 GEN6_RP_UP_BUSY_AVG |
8373 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8374
8375 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8376 500))
8377 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8378
8379 I915_WRITE(GEN6_PCODE_DATA, 0);
8380 I915_WRITE(GEN6_PCODE_MAILBOX,
8381 GEN6_PCODE_READY |
8382 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8383 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8384 500))
8385 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8386
a6044e23
JB		 8387 min_freq = (rp_state_cap & 0xff0000) >> 16;
8388 max_freq = rp_state_cap & 0xff;
8389 cur_freq = (gt_perf_status & 0xff00) >> 8;
8390
8391 /* Check for overclock support */
8392 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8393 500))
8394 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8395 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8396 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8397 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8398 500))
8399 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8400 if (pcu_mbox & (1<<31)) { /* OC supported */
8401 max_freq = pcu_mbox & 0xff;
e281fcaa 8402 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8403 }
8404
8405 /* In units of 100MHz */
8406 dev_priv->max_delay = max_freq;
8407 dev_priv->min_delay = min_freq;
8408 dev_priv->cur_delay = cur_freq;
8409
8fd26859
CW		 8410 /* requires MSI enabled */
8411 I915_WRITE(GEN6_PMIER,
8412 GEN6_PM_MBOX_EVENT |
8413 GEN6_PM_THERMAL_EVENT |
8414 GEN6_PM_RP_DOWN_TIMEOUT |
8415 GEN6_PM_RP_UP_THRESHOLD |
8416 GEN6_PM_RP_DOWN_THRESHOLD |
8417 GEN6_PM_RP_UP_EI_EXPIRED |
8418 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8419 spin_lock_irq(&dev_priv->rps_lock);
8420 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8421 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8422 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8423 /* enable all PM interrupts */
8424 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8425
fcca7926 8426 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8427 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8428}
8429
23b2f8bb
JB		 8430void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8431{
8432 int min_freq = 15;
8433 int gpu_freq, ia_freq, max_ia_freq;
8434 int scaling_factor = 180;
8435
8436 max_ia_freq = cpufreq_quick_get_max(0);
8437 /*
8438 * Default to measured freq if none found, PCU will ensure we don't go
8439 * over
8440 */
8441 if (!max_ia_freq)
8442 max_ia_freq = tsc_khz;
8443
8444 /* Convert from kHz to MHz */
8445 max_ia_freq /= 1000;
8446
8447 mutex_lock(&dev_priv->dev->struct_mutex);
8448
8449 /*
8450 * For each potential GPU frequency, load a ring frequency we'd like
8451 * to use for memory access. We do this by specifying the IA frequency
8452 * the PCU should use as a reference to determine the ring frequency.
8453 */
8454 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8455 gpu_freq--) {
8456 int diff = dev_priv->max_delay - gpu_freq;
8457
8458 /*
8459 * For GPU frequencies less than 750MHz, just use the lowest
8460 * ring freq.
8461 */
8462 if (gpu_freq < min_freq)
8463 ia_freq = 800;
8464 else
8465 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8466 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8467
8468 I915_WRITE(GEN6_PCODE_DATA,
8469 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8470 gpu_freq);
8471 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8472 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8473 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8474 GEN6_PCODE_READY) == 0, 10)) {
8475 DRM_ERROR("pcode write of freq table timed out\n");
8476 continue;
8477 }
8478 }
8479
8480 mutex_unlock(&dev_priv->dev->struct_mutex);
8481}
8482
6067aaea
JB		 8483static void ironlake_init_clock_gating(struct drm_device *dev)
8484{
8485 struct drm_i915_private *dev_priv = dev->dev_private;
8486 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8487
8488 /* Required for FBC */
8489 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8490 DPFCRUNIT_CLOCK_GATE_DISABLE |
8491 DPFDUNIT_CLOCK_GATE_DISABLE;
8492 /* Required for CxSR */
8493 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8494
8495 I915_WRITE(PCH_3DCGDIS0,
8496 MARIUNIT_CLOCK_GATE_DISABLE |
8497 SVSMUNIT_CLOCK_GATE_DISABLE);
8498 I915_WRITE(PCH_3DCGDIS1,
8499 VFMUNIT_CLOCK_GATE_DISABLE);
8500
8501 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8502
6067aaea
JB		 8503 /*
8504 * According to the spec the following bits should be set in
8505 * order to enable memory self-refresh
8506 * The bit 22/21 of 0x42004
8507 * The bit 5 of 0x42020
8508 * The bit 15 of 0x45000
8509 */
8510 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8511 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8512 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8513 I915_WRITE(ILK_DSPCLK_GATE,
8514 (I915_READ(ILK_DSPCLK_GATE) |
8515 ILK_DPARB_CLK_GATE));
8516 I915_WRITE(DISP_ARB_CTL,
8517 (I915_READ(DISP_ARB_CTL) |
8518 DISP_FBC_WM_DIS));
8519 I915_WRITE(WM3_LP_ILK, 0);
8520 I915_WRITE(WM2_LP_ILK, 0);
8521 I915_WRITE(WM1_LP_ILK, 0);
8522
8523 /*
8524 * Based on the document from hardware guys the following bits
8525 * should be set unconditionally in order to enable FBC.
8526 * The bit 22 of 0x42000
8527 * The bit 22 of 0x42004
8528 * The bit 7,8,9 of 0x42020.
8529 */
8530 if (IS_IRONLAKE_M(dev)) {
8531 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8532 I915_READ(ILK_DISPLAY_CHICKEN1) |
8533 ILK_FBCQ_DIS);
8534 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8535 I915_READ(ILK_DISPLAY_CHICKEN2) |
8536 ILK_DPARB_GATE);
8537 I915_WRITE(ILK_DSPCLK_GATE,
8538 I915_READ(ILK_DSPCLK_GATE) |
8539 ILK_DPFC_DIS1 |
8540 ILK_DPFC_DIS2 |
8541 ILK_CLK_FBC);
8542 }
8543
8544 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8545 I915_READ(ILK_DISPLAY_CHICKEN2) |
8546 ILK_ELPIN_409_SELECT);
8547 I915_WRITE(_3D_CHICKEN2,
8548 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8549 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8550}
8551
6067aaea 8552static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8553{
8554 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8555 int pipe;
6067aaea
JB		 8556 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8557
8558 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8559
6067aaea
JB		 8560 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8561 I915_READ(ILK_DISPLAY_CHICKEN2) |
8562 ILK_ELPIN_409_SELECT);
8956c8bb 8563
6067aaea
JB		 8564 I915_WRITE(WM3_LP_ILK, 0);
8565 I915_WRITE(WM2_LP_ILK, 0);
8566 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8567
80e829fa
DV		 8568 I915_WRITE(GEN6_UCGCTL1,
8569 I915_READ(GEN6_UCGCTL1) |
8570 GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8571
406478dc
EA		 8572 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8573 * gating disable must be set. Failure to set it results in
8574 * flickering pixels due to Z write ordering failures after
8575 * some amount of runtime in the Mesa "fire" demo, and Unigine
8576 * Sanctuary and Tropics, and apparently anything else with
8577 * alpha test or pixel discard.
9ca1d10d
EA		 8578 *
8579 * According to the spec, bit 11 (RCCUNIT) must also be set,
8580 * but we didn't debug actual testcases to find it out.
406478dc 8581 */
9ca1d10d
EA		 8582 I915_WRITE(GEN6_UCGCTL2,
8583 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8584 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8585
652c393a 8586 /*
6067aaea
JB		 8587 * According to the spec the following bits should be
8588 * set in order to enable memory self-refresh and fbc:
8589 * The bit21 and bit22 of 0x42000
8590 * The bit21 and bit22 of 0x42004
8591 * The bit5 and bit7 of 0x42020
8592 * The bit14 of 0x70180
8593 * The bit14 of 0x71180
652c393a 8594 */
6067aaea
JB		 8595 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8596 I915_READ(ILK_DISPLAY_CHICKEN1) |
8597 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8598 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8599 I915_READ(ILK_DISPLAY_CHICKEN2) |
8600 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8601 I915_WRITE(ILK_DSPCLK_GATE,
8602 I915_READ(ILK_DSPCLK_GATE) |
8603 ILK_DPARB_CLK_GATE |
8604 ILK_DPFD_CLK_GATE);
8956c8bb 8605
d74362c9 8606 for_each_pipe(pipe) {
6067aaea
JB		 8607 I915_WRITE(DSPCNTR(pipe),
8608 I915_READ(DSPCNTR(pipe)) |
8609 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8610 intel_flush_display_plane(dev_priv, pipe);
8611 }
6067aaea 8612}
8956c8bb 8613
28963a3e
JB		 8614static void ivybridge_init_clock_gating(struct drm_device *dev)
8615{
8616 struct drm_i915_private *dev_priv = dev->dev_private;
8617 int pipe;
8618 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8619
28963a3e 8620 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8621
28963a3e
JB		 8622 I915_WRITE(WM3_LP_ILK, 0);
8623 I915_WRITE(WM2_LP_ILK, 0);
8624 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8625
eae66b50
ED		 8626 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8627 * This implements the WaDisableRCZUnitClockGating workaround.
8628 */
8629 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8630
28963a3e 8631 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8632
116ac8d2
EA		 8633 I915_WRITE(IVB_CHICKEN3,
8634 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8635 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8636
d71de14d
KG		 8637 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8638 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8639 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8640
e4e0c058
ED		 8641 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8642 I915_WRITE(GEN7_L3CNTLREG1,
8643 GEN7_WA_FOR_GEN7_L3_CONTROL);
8644 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8645 GEN7_WA_L3_CHICKEN_MODE);
8646
db099c8f
ED		 8647 /* This is required by WaCatErrorRejectionIssue */
8648 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8649 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8650 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8651
d74362c9 8652 for_each_pipe(pipe) {
28963a3e
JB		 8653 I915_WRITE(DSPCNTR(pipe),
8654 I915_READ(DSPCNTR(pipe)) |
8655 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8656 intel_flush_display_plane(dev_priv, pipe);
8657 }
28963a3e
JB		 8658}
8659
6067aaea
JB		 8660static void g4x_init_clock_gating(struct drm_device *dev)
8661{
8662 struct drm_i915_private *dev_priv = dev->dev_private;
8663 uint32_t dspclk_gate;
8fd26859 8664
6067aaea
JB		 8665 I915_WRITE(RENCLK_GATE_D1, 0);
8666 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8667 GS_UNIT_CLOCK_GATE_DISABLE |
8668 CL_UNIT_CLOCK_GATE_DISABLE);
8669 I915_WRITE(RAMCLK_GATE_D, 0);
8670 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8671 OVRUNIT_CLOCK_GATE_DISABLE |
8672 OVCUNIT_CLOCK_GATE_DISABLE;
8673 if (IS_GM45(dev))
8674 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8675 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8676}
1398261a 8677
6067aaea
JB		 8678static void crestline_init_clock_gating(struct drm_device *dev)
8679{
8680 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8681
6067aaea
JB		 8682 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8683 I915_WRITE(RENCLK_GATE_D2, 0);
8684 I915_WRITE(DSPCLK_GATE_D, 0);
8685 I915_WRITE(RAMCLK_GATE_D, 0);
8686 I915_WRITE16(DEUC, 0);
8687}
652c393a 8688
6067aaea
JB		 8689static void broadwater_init_clock_gating(struct drm_device *dev)
8690{
8691 struct drm_i915_private *dev_priv = dev->dev_private;
8692
8693 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8694 I965_RCC_CLOCK_GATE_DISABLE |
8695 I965_RCPB_CLOCK_GATE_DISABLE |
8696 I965_ISC_CLOCK_GATE_DISABLE |
8697 I965_FBC_CLOCK_GATE_DISABLE);
8698 I915_WRITE(RENCLK_GATE_D2, 0);
8699}
8700
8701static void gen3_init_clock_gating(struct drm_device *dev)
8702{
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 u32 dstate = I915_READ(D_STATE);
8705
8706 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8707 DSTATE_DOT_CLOCK_GATING;
8708 I915_WRITE(D_STATE, dstate);
8709}
8710
8711static void i85x_init_clock_gating(struct drm_device *dev)
8712{
8713 struct drm_i915_private *dev_priv = dev->dev_private;
8714
8715 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8716}
8717
8718static void i830_init_clock_gating(struct drm_device *dev)
8719{
8720 struct drm_i915_private *dev_priv = dev->dev_private;
8721
8722 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8723}
8724
645c62a5
JB		 8725static void ibx_init_clock_gating(struct drm_device *dev)
8726{
8727 struct drm_i915_private *dev_priv = dev->dev_private;
8728
8729 /*
8730 * On Ibex Peak and Cougar Point, we need to disable clock
8731 * gating for the panel power sequencer or it will fail to
8732 * start up when no ports are active.
8733 */
8734 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8735}
8736
8737static void cpt_init_clock_gating(struct drm_device *dev)
8738{
8739 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8740 int pipe;
645c62a5
JB		 8741
8742 /*
8743 * On Ibex Peak and Cougar Point, we need to disable clock
8744 * gating for the panel power sequencer or it will fail to
8745 * start up when no ports are active.
8746 */
8747 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8748 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8749 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8750 /* Without this, mode sets may fail silently on FDI */
8751 for_each_pipe(pipe)
8752 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8753}
8754
ac668088 8755static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8756{
8757 struct drm_i915_private *dev_priv = dev->dev_private;
8758
8759 if (dev_priv->renderctx) {
ac668088
CW		 8760 i915_gem_object_unpin(dev_priv->renderctx);
8761 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8762 dev_priv->renderctx = NULL;
8763 }
8764
8765 if (dev_priv->pwrctx) {
ac668088
CW		 8766 i915_gem_object_unpin(dev_priv->pwrctx);
8767 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8768 dev_priv->pwrctx = NULL;
8769 }
8770}
8771
8772static void ironlake_disable_rc6(struct drm_device *dev)
8773{
8774 struct drm_i915_private *dev_priv = dev->dev_private;
8775
8776 if (I915_READ(PWRCTXA)) {
8777 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8778 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8779 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8780 50);
0cdab21f
CW		 8781
8782 I915_WRITE(PWRCTXA, 0);
8783 POSTING_READ(PWRCTXA);
8784
ac668088
CW		 8785 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8786 POSTING_READ(RSTDBYCTL);
0cdab21f 8787 }
ac668088 8788
99507307 8789 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8790}
8791
ac668088 8792static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8793{
8794 struct drm_i915_private *dev_priv = dev->dev_private;
8795
ac668088
CW		 8796 if (dev_priv->renderctx == NULL)
8797 dev_priv->renderctx = intel_alloc_context_page(dev);
8798 if (!dev_priv->renderctx)
8799 return -ENOMEM;
8800
8801 if (dev_priv->pwrctx == NULL)
8802 dev_priv->pwrctx = intel_alloc_context_page(dev);
8803 if (!dev_priv->pwrctx) {
8804 ironlake_teardown_rc6(dev);
8805 return -ENOMEM;
8806 }
8807
8808 return 0;
d5bb081b
JB		 8809}
8810
8811void ironlake_enable_rc6(struct drm_device *dev)
8812{
8813 struct drm_i915_private *dev_priv = dev->dev_private;
8814 int ret;
8815
ac668088
CW		 8816 /* rc6 disabled by default due to repeated reports of hanging during
8817 * boot and resume.
8818 */
c0f372b3 8819 if (!intel_enable_rc6(dev))
ac668088
CW		 8820 return;
8821
2c34b850 8822 mutex_lock(&dev->struct_mutex);
ac668088 8823 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8824 if (ret) {
8825 mutex_unlock(&dev->struct_mutex);
ac668088 8826 return;
2c34b850 8827 }
ac668088 8828
d5bb081b
JB		 8829 /*
8830 * GPU can automatically power down the render unit if given a page
8831 * to save state.
8832 */
8833 ret = BEGIN_LP_RING(6);
8834 if (ret) {
ac668088 8835 ironlake_teardown_rc6(dev);
2c34b850 8836 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8837 return;
8838 }
ac668088 8839
d5bb081b
JB		 8840 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8841 OUT_RING(MI_SET_CONTEXT);
8842 OUT_RING(dev_priv->renderctx->gtt_offset |
8843 MI_MM_SPACE_GTT |
8844 MI_SAVE_EXT_STATE_EN |
8845 MI_RESTORE_EXT_STATE_EN |
8846 MI_RESTORE_INHIBIT);
8847 OUT_RING(MI_SUSPEND_FLUSH);
8848 OUT_RING(MI_NOOP);
8849 OUT_RING(MI_FLUSH);
8850 ADVANCE_LP_RING();
8851
4a246cfc
BW		 8852 /*
8853 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8854 * does an implicit flush, combined with MI_FLUSH above, it should be
8855 * safe to assume that renderctx is valid
8856 */
8857 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8858 if (ret) {
8859 DRM_ERROR("failed to enable ironlake power power savings\n");
8860 ironlake_teardown_rc6(dev);
8861 mutex_unlock(&dev->struct_mutex);
8862 return;
8863 }
8864
d5bb081b
JB		 8865 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8866 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8867 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8868}
8869
645c62a5
JB		 8870void intel_init_clock_gating(struct drm_device *dev)
8871{
8872 struct drm_i915_private *dev_priv = dev->dev_private;
8873
8874 dev_priv->display.init_clock_gating(dev);
8875
8876 if (dev_priv->display.init_pch_clock_gating)
8877 dev_priv->display.init_pch_clock_gating(dev);
8878}
ac668088 8879
e70236a8
JB		 8880/* Set up chip specific display functions */
8881static void intel_init_display(struct drm_device *dev)
8882{
8883 struct drm_i915_private *dev_priv = dev->dev_private;
8884
8885 /* We always want a DPMS function */
f564048e 8886 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8887 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8888 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8889 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8890 } else {
e70236a8 8891 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8892 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8893 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8894 }
e70236a8 8895
ee5382ae 8896 if (I915_HAS_FBC(dev)) {
9c04f015 8897 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8898 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8899 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8900 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8901 } else if (IS_GM45(dev)) {
74dff282
JB		 8902 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8903 dev_priv->display.enable_fbc = g4x_enable_fbc;
8904 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8905 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8906 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8907 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8908 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8909 }
74dff282 8910 /* 855GM needs testing */
e70236a8
JB		 8911 }
8912
8913 /* Returns the core display clock speed */
0206e353 8914 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8915 dev_priv->display.get_display_clock_speed =
8916 i945_get_display_clock_speed;
8917 else if (IS_I915G(dev))
8918 dev_priv->display.get_display_clock_speed =
8919 i915_get_display_clock_speed;
f2b115e6 8920 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8921 dev_priv->display.get_display_clock_speed =
8922 i9xx_misc_get_display_clock_speed;
8923 else if (IS_I915GM(dev))
8924 dev_priv->display.get_display_clock_speed =
8925 i915gm_get_display_clock_speed;
8926 else if (IS_I865G(dev))
8927 dev_priv->display.get_display_clock_speed =
8928 i865_get_display_clock_speed;
f0f8a9ce 8929 else if (IS_I85X(dev))
e70236a8
JB		 8930 dev_priv->display.get_display_clock_speed =
8931 i855_get_display_clock_speed;
8932 else /* 852, 830 */
8933 dev_priv->display.get_display_clock_speed =
8934 i830_get_display_clock_speed;
8935
8936 /* For FIFO watermark updates */
7f8a8569 8937 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8938 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8939 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8940
8941 /* IVB configs may use multi-threaded forcewake */
8942 if (IS_IVYBRIDGE(dev)) {
8943 u32 ecobus;
8944
c7dffff7
KP		 8945 /* A small trick here - if the bios hasn't configured MT forcewake,
8946 * and if the device is in RC6, then force_wake_mt_get will not wake
8947 * the device and the ECOBUS read will return zero. Which will be
8948 * (correctly) interpreted by the test below as MT forcewake being
8949 * disabled.
8950 */
8d715f00
KP		 8951 mutex_lock(&dev->struct_mutex);
8952 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8953 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8954 __gen6_gt_force_wake_mt_put(dev_priv);
8955 mutex_unlock(&dev->struct_mutex);
8956
8957 if (ecobus & FORCEWAKE_MT_ENABLE) {
8958 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8959 dev_priv->display.force_wake_get =
8960 __gen6_gt_force_wake_mt_get;
8961 dev_priv->display.force_wake_put =
8962 __gen6_gt_force_wake_mt_put;
8963 }
8964 }
8965
645c62a5
JB		 8966 if (HAS_PCH_IBX(dev))
8967 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8968 else if (HAS_PCH_CPT(dev))
8969 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8970
f00a3ddf 8971 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8972 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8973 dev_priv->display.update_wm = ironlake_update_wm;
8974 else {
8975 DRM_DEBUG_KMS("Failed to get proper latency. "
8976 "Disable CxSR\n");
8977 dev_priv->display.update_wm = NULL;
1398261a 8978 }
674cf967 8979 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8980 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8981 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8982 } else if (IS_GEN6(dev)) {
8983 if (SNB_READ_WM0_LATENCY()) {
8984 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8985 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8986 } else {
8987 DRM_DEBUG_KMS("Failed to read display plane latency. "
8988 "Disable CxSR\n");
8989 dev_priv->display.update_wm = NULL;
7f8a8569 8990 }
674cf967 8991 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8992 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8993 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8994 } else if (IS_IVYBRIDGE(dev)) {
8995 /* FIXME: detect B0+ stepping and use auto training */
8996 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8997 if (SNB_READ_WM0_LATENCY()) {
8998 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8999 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 9000 } else {
9001 DRM_DEBUG_KMS("Failed to read display plane latency. "
9002 "Disable CxSR\n");
9003 dev_priv->display.update_wm = NULL;
9004 }
28963a3e 9005 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 9006 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 9007 } else
9008 dev_priv->display.update_wm = NULL;
9009 } else if (IS_PINEVIEW(dev)) {
d4294342 9010 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 9011 dev_priv->is_ddr3,
d4294342
ZY		 9012 dev_priv->fsb_freq,
9013 dev_priv->mem_freq)) {
9014 DRM_INFO("failed to find known CxSR latency "
95534263 9015 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 9016 "disabling CxSR\n",
0206e353 9017 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 9018 dev_priv->fsb_freq, dev_priv->mem_freq);
9019 /* Disable CxSR and never update its watermark again */
9020 pineview_disable_cxsr(dev);
9021 dev_priv->display.update_wm = NULL;
9022 } else
9023 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 9024 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 9025 } else if (IS_G4X(dev)) {
e0dac65e 9026 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9027 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 9028 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9029 } else if (IS_GEN4(dev)) {
e70236a8 9030 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 9031 if (IS_CRESTLINE(dev))
9032 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9033 else if (IS_BROADWATER(dev))
9034 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9035 } else if (IS_GEN3(dev)) {
e70236a8
JB		 9036 dev_priv->display.update_wm = i9xx_update_wm;
9037 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 9038 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9039 } else if (IS_I865G(dev)) {
9040 dev_priv->display.update_wm = i830_update_wm;
9041 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9042 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 9043 } else if (IS_I85X(dev)) {
9044 dev_priv->display.update_wm = i9xx_update_wm;
9045 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 9046 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 9047 } else {
8f4695ed 9048 dev_priv->display.update_wm = i830_update_wm;
6067aaea 9049 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 9050 if (IS_845G(dev))
e70236a8
JB		 9051 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9052 else
9053 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 9054 }
8c9f3aaf
JB		 9055
9056 /* Default just returns -ENODEV to indicate unsupported */
9057 dev_priv->display.queue_flip = intel_default_queue_flip;
9058
9059 switch (INTEL_INFO(dev)->gen) {
9060 case 2:
9061 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9062 break;
9063
9064 case 3:
9065 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9066 break;
9067
9068 case 4:
9069 case 5:
9070 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9071 break;
9072
9073 case 6:
9074 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9075 break;
7c9017e5
JB		 9076 case 7:
9077 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9078 break;
8c9f3aaf 9079 }
e70236a8
JB		 9080}
9081
b690e96c
JB		 9082/*
9083 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9084 * resume, or other times. This quirk makes sure that's the case for
9085 * affected systems.
9086 */
0206e353 9087static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9088{
9089 struct drm_i915_private *dev_priv = dev->dev_private;
9090
9091 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9092 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9093}
9094
435793df
KP		 9095/*
9096 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9097 */
9098static void quirk_ssc_force_disable(struct drm_device *dev)
9099{
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9102}
9103
b690e96c
JB		 9104struct intel_quirk {
9105 int device;
9106 int subsystem_vendor;
9107 int subsystem_device;
9108 void (*hook)(struct drm_device *dev);
9109};
9110
9111struct intel_quirk intel_quirks[] = {
b690e96c 9112 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9113 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9114
9115 /* Thinkpad R31 needs pipe A force quirk */
9116 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9117 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9118 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9119
9120 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9121 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9122 /* ThinkPad X40 needs pipe A force quirk */
9123
9124 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9125 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9126
9127 /* 855 & before need to leave pipe A & dpll A up */
9128 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9129 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9130
9131 /* Lenovo U160 cannot use SSC on LVDS */
9132 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9133
9134 /* Sony Vaio Y cannot use SSC on LVDS */
9135 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9136};
9137
9138static void intel_init_quirks(struct drm_device *dev)
9139{
9140 struct pci_dev *d = dev->pdev;
9141 int i;
9142
9143 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9144 struct intel_quirk *q = &intel_quirks[i];
9145
9146 if (d->device == q->device &&
9147 (d->subsystem_vendor == q->subsystem_vendor ||
9148 q->subsystem_vendor == PCI_ANY_ID) &&
9149 (d->subsystem_device == q->subsystem_device ||
9150 q->subsystem_device == PCI_ANY_ID))
9151 q->hook(dev);
9152 }
9153}
9154
9cce37f4
JB		 9155/* Disable the VGA plane that we never use */
9156static void i915_disable_vga(struct drm_device *dev)
9157{
9158 struct drm_i915_private *dev_priv = dev->dev_private;
9159 u8 sr1;
9160 u32 vga_reg;
9161
9162 if (HAS_PCH_SPLIT(dev))
9163 vga_reg = CPU_VGACNTRL;
9164 else
9165 vga_reg = VGACNTRL;
9166
9167 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9168 outb(1, VGA_SR_INDEX);
9169 sr1 = inb(VGA_SR_DATA);
9170 outb(sr1 | 1<<5, VGA_SR_DATA);
9171 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9172 udelay(300);
9173
9174 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9175 POSTING_READ(vga_reg);
9176}
9177
79e53945
JB		 9178void intel_modeset_init(struct drm_device *dev)
9179{
652c393a 9180 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9181 int i, ret;
79e53945
JB		 9182
9183 drm_mode_config_init(dev);
9184
9185 dev->mode_config.min_width = 0;
9186 dev->mode_config.min_height = 0;
9187
019d96cb
DA		 9188 dev->mode_config.preferred_depth = 24;
9189 dev->mode_config.prefer_shadow = 1;
9190
79e53945
JB		 9191 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9192
b690e96c
JB		 9193 intel_init_quirks(dev);
9194
e70236a8
JB		 9195 intel_init_display(dev);
9196
a6c45cf0
CW		 9197 if (IS_GEN2(dev)) {
9198 dev->mode_config.max_width = 2048;
9199 dev->mode_config.max_height = 2048;
9200 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9201 dev->mode_config.max_width = 4096;
9202 dev->mode_config.max_height = 4096;
79e53945 9203 } else {
a6c45cf0
CW		 9204 dev->mode_config.max_width = 8192;
9205 dev->mode_config.max_height = 8192;
79e53945 9206 }
35c3047a 9207 dev->mode_config.fb_base = dev->agp->base;
79e53945 9208
28c97730 9209 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9210 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9211
a3524f1b 9212 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9213 intel_crtc_init(dev, i);
00c2064b
JB		 9214 ret = intel_plane_init(dev, i);
9215 if (ret)
9216 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9217 }
9218
9cce37f4
JB		 9219 /* Just disable it once at startup */
9220 i915_disable_vga(dev);
79e53945 9221 intel_setup_outputs(dev);
652c393a 9222
645c62a5 9223 intel_init_clock_gating(dev);
9cce37f4 9224
7648fa99 9225 if (IS_IRONLAKE_M(dev)) {
f97108d1 9226 ironlake_enable_drps(dev);
7648fa99
JB		 9227 intel_init_emon(dev);
9228 }
f97108d1 9229
1c70c0ce 9230 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9231 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9232 gen6_update_ring_freq(dev_priv);
9233 }
3b8d8d91 9234
652c393a
JB		 9235 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9236 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9237 (unsigned long)dev);
2c7111db
CW		 9238}
9239
9240void intel_modeset_gem_init(struct drm_device *dev)
9241{
9242 if (IS_IRONLAKE_M(dev))
9243 ironlake_enable_rc6(dev);
02e792fb
DV		 9244
9245 intel_setup_overlay(dev);
79e53945
JB		 9246}
9247
9248void intel_modeset_cleanup(struct drm_device *dev)
9249{
652c393a
JB		 9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251 struct drm_crtc *crtc;
9252 struct intel_crtc *intel_crtc;
9253
f87ea761 9254 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9255 mutex_lock(&dev->struct_mutex);
9256
723bfd70
JB		 9257 intel_unregister_dsm_handler();
9258
9259
652c393a
JB		 9260 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9261 /* Skip inactive CRTCs */
9262 if (!crtc->fb)
9263 continue;
9264
9265 intel_crtc = to_intel_crtc(crtc);
3dec0095 9266 intel_increase_pllclock(crtc);
652c393a
JB		 9267 }
9268
973d04f9 9269 intel_disable_fbc(dev);
e70236a8 9270
f97108d1
JB		 9271 if (IS_IRONLAKE_M(dev))
9272 ironlake_disable_drps(dev);
1c70c0ce 9273 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9274 gen6_disable_rps(dev);
f97108d1 9275
d5bb081b
JB		 9276 if (IS_IRONLAKE_M(dev))
9277 ironlake_disable_rc6(dev);
0cdab21f 9278
69341a5e
KH		 9279 mutex_unlock(&dev->struct_mutex);
9280
6c0d9350
DV		 9281 /* Disable the irq before mode object teardown, for the irq might
9282 * enqueue unpin/hotplug work. */
9283 drm_irq_uninstall(dev);
9284 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9285 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9286
1630fe75
CW		 9287 /* flush any delayed tasks or pending work */
9288 flush_scheduled_work();
9289
3dec0095
DV		 9290 /* Shut off idle work before the crtcs get freed. */
9291 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9292 intel_crtc = to_intel_crtc(crtc);
9293 del_timer_sync(&intel_crtc->idle_timer);
9294 }
9295 del_timer_sync(&dev_priv->idle_timer);
9296 cancel_work_sync(&dev_priv->idle_work);
9297
79e53945
JB		 9298 drm_mode_config_cleanup(dev);
9299}
9300
f1c79df3
ZW		 9301/*
9302 * Return which encoder is currently attached for connector.
9303 */
df0e9248 9304struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9305{
df0e9248
CW		 9306 return &intel_attached_encoder(connector)->base;
9307}
f1c79df3 9308
df0e9248
CW		 9309void intel_connector_attach_encoder(struct intel_connector *connector,
9310 struct intel_encoder *encoder)
9311{
9312 connector->encoder = encoder;
9313 drm_mode_connector_attach_encoder(&connector->base,
9314 &encoder->base);
79e53945 9315}
28d52043
DA		 9316
9317/*
9318 * set vga decode state - true == enable VGA decode
9319 */
9320int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9321{
9322 struct drm_i915_private *dev_priv = dev->dev_private;
9323 u16 gmch_ctrl;
9324
9325 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9326 if (state)
9327 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9328 else
9329 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9330 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9331 return 0;
9332}
c4a1d9e4
CW		 9333
9334#ifdef CONFIG_DEBUG_FS
9335#include <linux/seq_file.h>
9336
9337struct intel_display_error_state {
9338 struct intel_cursor_error_state {
9339 u32 control;
9340 u32 position;
9341 u32 base;
9342 u32 size;
9343 } cursor[2];
9344
9345 struct intel_pipe_error_state {
9346 u32 conf;
9347 u32 source;
9348
9349 u32 htotal;
9350 u32 hblank;
9351 u32 hsync;
9352 u32 vtotal;
9353 u32 vblank;
9354 u32 vsync;
9355 } pipe[2];
9356
9357 struct intel_plane_error_state {
9358 u32 control;
9359 u32 stride;
9360 u32 size;
9361 u32 pos;
9362 u32 addr;
9363 u32 surface;
9364 u32 tile_offset;
9365 } plane[2];
9366};
9367
9368struct intel_display_error_state *
9369intel_display_capture_error_state(struct drm_device *dev)
9370{
0206e353 9371 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9372 struct intel_display_error_state *error;
9373 int i;
9374
9375 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9376 if (error == NULL)
9377 return NULL;
9378
9379 for (i = 0; i < 2; i++) {
9380 error->cursor[i].control = I915_READ(CURCNTR(i));
9381 error->cursor[i].position = I915_READ(CURPOS(i));
9382 error->cursor[i].base = I915_READ(CURBASE(i));
9383
9384 error->plane[i].control = I915_READ(DSPCNTR(i));
9385 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9386 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9387 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9388 error->plane[i].addr = I915_READ(DSPADDR(i));
9389 if (INTEL_INFO(dev)->gen >= 4) {
9390 error->plane[i].surface = I915_READ(DSPSURF(i));
9391 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9392 }
9393
9394 error->pipe[i].conf = I915_READ(PIPECONF(i));
9395 error->pipe[i].source = I915_READ(PIPESRC(i));
9396 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9397 error->pipe[i].hblank = I915_READ(HBLANK(i));
9398 error->pipe[i].hsync = I915_READ(HSYNC(i));
9399 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9400 error->pipe[i].vblank = I915_READ(VBLANK(i));
9401 error->pipe[i].vsync = I915_READ(VSYNC(i));
9402 }
9403
9404 return error;
9405}
9406
9407void
9408intel_display_print_error_state(struct seq_file *m,
9409 struct drm_device *dev,
9410 struct intel_display_error_state *error)
9411{
9412 int i;
9413
9414 for (i = 0; i < 2; i++) {
9415 seq_printf(m, "Pipe [%d]:\n", i);
9416 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9417 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9418 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9419 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9420 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9421 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9422 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9423 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9424
9425 seq_printf(m, "Plane [%d]:\n", i);
9426 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9427 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9428 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9429 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9430 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9431 if (INTEL_INFO(dev)->gen >= 4) {
9432 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9433 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9434 }
9435
9436 seq_printf(m, "Cursor [%d]:\n", i);
9437 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9438 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9439 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9440 }
9441}
9442#endif
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