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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
95 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
96 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
97 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
98 | struct intel_link_m_n *m_n); | |
99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 103 | |
79e53945 | 104 | typedef struct { |
0206e353 | 105 | int min, max; |
79e53945 JB |
106 | } intel_range_t; |
107 | ||
108 | typedef struct { | |
0206e353 AJ |
109 | int dot_limit; |
110 | int p2_slow, p2_fast; | |
79e53945 JB |
111 | } intel_p2_t; |
112 | ||
d4906093 ML |
113 | typedef struct intel_limit intel_limit_t; |
114 | struct intel_limit { | |
0206e353 AJ |
115 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
116 | intel_p2_t p2; | |
d4906093 | 117 | }; |
79e53945 | 118 | |
d2acd215 DV |
119 | int |
120 | intel_pch_rawclk(struct drm_device *dev) | |
121 | { | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
125 | ||
126 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
127 | } | |
128 | ||
021357ac CW |
129 | static inline u32 /* units of 100MHz */ |
130 | intel_fdi_link_freq(struct drm_device *dev) | |
131 | { | |
8b99e68c CW |
132 | if (IS_GEN5(dev)) { |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
135 | } else | |
136 | return 27; | |
021357ac CW |
137 | } |
138 | ||
5d536e28 | 139 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 140 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 141 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 142 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
143 | .m = { .min = 96, .max = 140 }, |
144 | .m1 = { .min = 18, .max = 26 }, | |
145 | .m2 = { .min = 6, .max = 16 }, | |
146 | .p = { .min = 4, .max = 128 }, | |
147 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
148 | .p2 = { .dot_limit = 165000, |
149 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
150 | }; |
151 | ||
5d536e28 DV |
152 | static const intel_limit_t intel_limits_i8xx_dvo = { |
153 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 154 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 155 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
156 | .m = { .min = 96, .max = 140 }, |
157 | .m1 = { .min = 18, .max = 26 }, | |
158 | .m2 = { .min = 6, .max = 16 }, | |
159 | .p = { .min = 4, .max = 128 }, | |
160 | .p1 = { .min = 2, .max = 33 }, | |
161 | .p2 = { .dot_limit = 165000, | |
162 | .p2_slow = 4, .p2_fast = 4 }, | |
163 | }; | |
164 | ||
e4b36699 | 165 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 166 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 167 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 168 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
169 | .m = { .min = 96, .max = 140 }, |
170 | .m1 = { .min = 18, .max = 26 }, | |
171 | .m2 = { .min = 6, .max = 16 }, | |
172 | .p = { .min = 4, .max = 128 }, | |
173 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
174 | .p2 = { .dot_limit = 165000, |
175 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 176 | }; |
273e27ca | 177 | |
e4b36699 | 178 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
179 | .dot = { .min = 20000, .max = 400000 }, |
180 | .vco = { .min = 1400000, .max = 2800000 }, | |
181 | .n = { .min = 1, .max = 6 }, | |
182 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
183 | .m1 = { .min = 8, .max = 18 }, |
184 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
185 | .p = { .min = 5, .max = 80 }, |
186 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
187 | .p2 = { .dot_limit = 200000, |
188 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
189 | }; |
190 | ||
191 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
192 | .dot = { .min = 20000, .max = 400000 }, |
193 | .vco = { .min = 1400000, .max = 2800000 }, | |
194 | .n = { .min = 1, .max = 6 }, | |
195 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
196 | .m1 = { .min = 8, .max = 18 }, |
197 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
198 | .p = { .min = 7, .max = 98 }, |
199 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
200 | .p2 = { .dot_limit = 112000, |
201 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
202 | }; |
203 | ||
273e27ca | 204 | |
e4b36699 | 205 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
206 | .dot = { .min = 25000, .max = 270000 }, |
207 | .vco = { .min = 1750000, .max = 3500000}, | |
208 | .n = { .min = 1, .max = 4 }, | |
209 | .m = { .min = 104, .max = 138 }, | |
210 | .m1 = { .min = 17, .max = 23 }, | |
211 | .m2 = { .min = 5, .max = 11 }, | |
212 | .p = { .min = 10, .max = 30 }, | |
213 | .p1 = { .min = 1, .max = 3}, | |
214 | .p2 = { .dot_limit = 270000, | |
215 | .p2_slow = 10, | |
216 | .p2_fast = 10 | |
044c7c41 | 217 | }, |
e4b36699 KP |
218 | }; |
219 | ||
220 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
221 | .dot = { .min = 22000, .max = 400000 }, |
222 | .vco = { .min = 1750000, .max = 3500000}, | |
223 | .n = { .min = 1, .max = 4 }, | |
224 | .m = { .min = 104, .max = 138 }, | |
225 | .m1 = { .min = 16, .max = 23 }, | |
226 | .m2 = { .min = 5, .max = 11 }, | |
227 | .p = { .min = 5, .max = 80 }, | |
228 | .p1 = { .min = 1, .max = 8}, | |
229 | .p2 = { .dot_limit = 165000, | |
230 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
234 | .dot = { .min = 20000, .max = 115000 }, |
235 | .vco = { .min = 1750000, .max = 3500000 }, | |
236 | .n = { .min = 1, .max = 3 }, | |
237 | .m = { .min = 104, .max = 138 }, | |
238 | .m1 = { .min = 17, .max = 23 }, | |
239 | .m2 = { .min = 5, .max = 11 }, | |
240 | .p = { .min = 28, .max = 112 }, | |
241 | .p1 = { .min = 2, .max = 8 }, | |
242 | .p2 = { .dot_limit = 0, | |
243 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 244 | }, |
e4b36699 KP |
245 | }; |
246 | ||
247 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
248 | .dot = { .min = 80000, .max = 224000 }, |
249 | .vco = { .min = 1750000, .max = 3500000 }, | |
250 | .n = { .min = 1, .max = 3 }, | |
251 | .m = { .min = 104, .max = 138 }, | |
252 | .m1 = { .min = 17, .max = 23 }, | |
253 | .m2 = { .min = 5, .max = 11 }, | |
254 | .p = { .min = 14, .max = 42 }, | |
255 | .p1 = { .min = 2, .max = 6 }, | |
256 | .p2 = { .dot_limit = 0, | |
257 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 258 | }, |
e4b36699 KP |
259 | }; |
260 | ||
f2b115e6 | 261 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
262 | .dot = { .min = 20000, .max = 400000}, |
263 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 264 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
265 | .n = { .min = 3, .max = 6 }, |
266 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 267 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
268 | .m1 = { .min = 0, .max = 0 }, |
269 | .m2 = { .min = 0, .max = 254 }, | |
270 | .p = { .min = 5, .max = 80 }, | |
271 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 200000, |
273 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
274 | }; |
275 | ||
f2b115e6 | 276 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
277 | .dot = { .min = 20000, .max = 400000 }, |
278 | .vco = { .min = 1700000, .max = 3500000 }, | |
279 | .n = { .min = 3, .max = 6 }, | |
280 | .m = { .min = 2, .max = 256 }, | |
281 | .m1 = { .min = 0, .max = 0 }, | |
282 | .m2 = { .min = 0, .max = 254 }, | |
283 | .p = { .min = 7, .max = 112 }, | |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 112000, |
286 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
287 | }; |
288 | ||
273e27ca EA |
289 | /* Ironlake / Sandybridge |
290 | * | |
291 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
292 | * the range value for them is (actual_value - 2). | |
293 | */ | |
b91ad0ec | 294 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 350000 }, |
296 | .vco = { .min = 1760000, .max = 3510000 }, | |
297 | .n = { .min = 1, .max = 5 }, | |
298 | .m = { .min = 79, .max = 127 }, | |
299 | .m1 = { .min = 12, .max = 22 }, | |
300 | .m2 = { .min = 5, .max = 9 }, | |
301 | .p = { .min = 5, .max = 80 }, | |
302 | .p1 = { .min = 1, .max = 8 }, | |
303 | .p2 = { .dot_limit = 225000, | |
304 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
305 | }; |
306 | ||
b91ad0ec | 307 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 3 }, | |
311 | .m = { .min = 79, .max = 118 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 28, .max = 112 }, | |
315 | .p1 = { .min = 2, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
318 | }; |
319 | ||
320 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 127 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 14, .max = 56 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
331 | }; |
332 | ||
273e27ca | 333 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 334 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
335 | .dot = { .min = 25000, .max = 350000 }, |
336 | .vco = { .min = 1760000, .max = 3510000 }, | |
337 | .n = { .min = 1, .max = 2 }, | |
338 | .m = { .min = 79, .max = 126 }, | |
339 | .m1 = { .min = 12, .max = 22 }, | |
340 | .m2 = { .min = 5, .max = 9 }, | |
341 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 342 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
343 | .p2 = { .dot_limit = 225000, |
344 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
345 | }; |
346 | ||
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 3 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
358 | }; |
359 | ||
dc730512 | 360 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
361 | /* |
362 | * These are the data rate limits (measured in fast clocks) | |
363 | * since those are the strictest limits we have. The fast | |
364 | * clock and actual rate limits are more relaxed, so checking | |
365 | * them would make no difference. | |
366 | */ | |
367 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 368 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 369 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
370 | .m1 = { .min = 2, .max = 3 }, |
371 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 372 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 373 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
374 | }; |
375 | ||
ef9348c8 CML |
376 | static const intel_limit_t intel_limits_chv = { |
377 | /* | |
378 | * These are the data rate limits (measured in fast clocks) | |
379 | * since those are the strictest limits we have. The fast | |
380 | * clock and actual rate limits are more relaxed, so checking | |
381 | * them would make no difference. | |
382 | */ | |
383 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
384 | .vco = { .min = 4860000, .max = 6700000 }, | |
385 | .n = { .min = 1, .max = 1 }, | |
386 | .m1 = { .min = 2, .max = 2 }, | |
387 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
388 | .p1 = { .min = 2, .max = 4 }, | |
389 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
390 | }; | |
391 | ||
6b4bf1c4 VS |
392 | static void vlv_clock(int refclk, intel_clock_t *clock) |
393 | { | |
394 | clock->m = clock->m1 * clock->m2; | |
395 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
396 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
397 | return; | |
fb03ac01 VS |
398 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
399 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
400 | } |
401 | ||
e0638cdf PZ |
402 | /** |
403 | * Returns whether any output on the specified pipe is of the specified type | |
404 | */ | |
405 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
406 | { | |
407 | struct drm_device *dev = crtc->dev; | |
408 | struct intel_encoder *encoder; | |
409 | ||
410 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
411 | if (encoder->type == type) | |
412 | return true; | |
413 | ||
414 | return false; | |
415 | } | |
416 | ||
1b894b59 CW |
417 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
418 | int refclk) | |
2c07245f | 419 | { |
b91ad0ec | 420 | struct drm_device *dev = crtc->dev; |
2c07245f | 421 | const intel_limit_t *limit; |
b91ad0ec ZW |
422 | |
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 424 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 425 | if (refclk == 100000) |
b91ad0ec ZW |
426 | limit = &intel_limits_ironlake_dual_lvds_100m; |
427 | else | |
428 | limit = &intel_limits_ironlake_dual_lvds; | |
429 | } else { | |
1b894b59 | 430 | if (refclk == 100000) |
b91ad0ec ZW |
431 | limit = &intel_limits_ironlake_single_lvds_100m; |
432 | else | |
433 | limit = &intel_limits_ironlake_single_lvds; | |
434 | } | |
c6bb3538 | 435 | } else |
b91ad0ec | 436 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
437 | |
438 | return limit; | |
439 | } | |
440 | ||
044c7c41 ML |
441 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
442 | { | |
443 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
444 | const intel_limit_t *limit; |
445 | ||
446 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 447 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 448 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 449 | else |
e4b36699 | 450 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
451 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
452 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 453 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 454 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 455 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 456 | } else /* The option is for other outputs */ |
e4b36699 | 457 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
458 | |
459 | return limit; | |
460 | } | |
461 | ||
1b894b59 | 462 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
463 | { |
464 | struct drm_device *dev = crtc->dev; | |
465 | const intel_limit_t *limit; | |
466 | ||
bad720ff | 467 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 468 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 469 | else if (IS_G4X(dev)) { |
044c7c41 | 470 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 471 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 472 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 473 | limit = &intel_limits_pineview_lvds; |
2177832f | 474 | else |
f2b115e6 | 475 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
476 | } else if (IS_CHERRYVIEW(dev)) { |
477 | limit = &intel_limits_chv; | |
a0c4da24 | 478 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 479 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
480 | } else if (!IS_GEN2(dev)) { |
481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
482 | limit = &intel_limits_i9xx_lvds; | |
483 | else | |
484 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
485 | } else { |
486 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 487 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 488 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 489 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
490 | else |
491 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
492 | } |
493 | return limit; | |
494 | } | |
495 | ||
f2b115e6 AJ |
496 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
497 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 498 | { |
2177832f SL |
499 | clock->m = clock->m2 + 2; |
500 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
501 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
502 | return; | |
fb03ac01 VS |
503 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
504 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
505 | } |
506 | ||
7429e9d4 DV |
507 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
508 | { | |
509 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
510 | } | |
511 | ||
ac58c3f0 | 512 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 513 | { |
7429e9d4 | 514 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 515 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
516 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
517 | return; | |
fb03ac01 VS |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
520 | } |
521 | ||
ef9348c8 CML |
522 | static void chv_clock(int refclk, intel_clock_t *clock) |
523 | { | |
524 | clock->m = clock->m1 * clock->m2; | |
525 | clock->p = clock->p1 * clock->p2; | |
526 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
527 | return; | |
528 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
529 | clock->n << 22); | |
530 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
531 | } | |
532 | ||
7c04d1d9 | 533 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
534 | /** |
535 | * Returns whether the given set of divisors are valid for a given refclk with | |
536 | * the given connectors. | |
537 | */ | |
538 | ||
1b894b59 CW |
539 | static bool intel_PLL_is_valid(struct drm_device *dev, |
540 | const intel_limit_t *limit, | |
541 | const intel_clock_t *clock) | |
79e53945 | 542 | { |
f01b7962 VS |
543 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
544 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 545 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 546 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 547 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 548 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 549 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 550 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
551 | |
552 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
553 | if (clock->m1 <= clock->m2) | |
554 | INTELPllInvalid("m1 <= m2\n"); | |
555 | ||
556 | if (!IS_VALLEYVIEW(dev)) { | |
557 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
558 | INTELPllInvalid("p out of range\n"); | |
559 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
560 | INTELPllInvalid("m out of range\n"); | |
561 | } | |
562 | ||
79e53945 | 563 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 564 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
565 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
566 | * connector, etc., rather than just a single range. | |
567 | */ | |
568 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 569 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
570 | |
571 | return true; | |
572 | } | |
573 | ||
d4906093 | 574 | static bool |
ee9300bb | 575 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
576 | int target, int refclk, intel_clock_t *match_clock, |
577 | intel_clock_t *best_clock) | |
79e53945 JB |
578 | { |
579 | struct drm_device *dev = crtc->dev; | |
79e53945 | 580 | intel_clock_t clock; |
79e53945 JB |
581 | int err = target; |
582 | ||
a210b028 | 583 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 584 | /* |
a210b028 DV |
585 | * For LVDS just rely on its current settings for dual-channel. |
586 | * We haven't figured out how to reliably set up different | |
587 | * single/dual channel state, if we even can. | |
79e53945 | 588 | */ |
1974cad0 | 589 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
590 | clock.p2 = limit->p2.p2_fast; |
591 | else | |
592 | clock.p2 = limit->p2.p2_slow; | |
593 | } else { | |
594 | if (target < limit->p2.dot_limit) | |
595 | clock.p2 = limit->p2.p2_slow; | |
596 | else | |
597 | clock.p2 = limit->p2.p2_fast; | |
598 | } | |
599 | ||
0206e353 | 600 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 601 | |
42158660 ZY |
602 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
603 | clock.m1++) { | |
604 | for (clock.m2 = limit->m2.min; | |
605 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 606 | if (clock.m2 >= clock.m1) |
42158660 ZY |
607 | break; |
608 | for (clock.n = limit->n.min; | |
609 | clock.n <= limit->n.max; clock.n++) { | |
610 | for (clock.p1 = limit->p1.min; | |
611 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
612 | int this_err; |
613 | ||
ac58c3f0 DV |
614 | i9xx_clock(refclk, &clock); |
615 | if (!intel_PLL_is_valid(dev, limit, | |
616 | &clock)) | |
617 | continue; | |
618 | if (match_clock && | |
619 | clock.p != match_clock->p) | |
620 | continue; | |
621 | ||
622 | this_err = abs(clock.dot - target); | |
623 | if (this_err < err) { | |
624 | *best_clock = clock; | |
625 | err = this_err; | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | } | |
631 | ||
632 | return (err != target); | |
633 | } | |
634 | ||
635 | static bool | |
ee9300bb DV |
636 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
637 | int target, int refclk, intel_clock_t *match_clock, | |
638 | intel_clock_t *best_clock) | |
79e53945 JB |
639 | { |
640 | struct drm_device *dev = crtc->dev; | |
79e53945 | 641 | intel_clock_t clock; |
79e53945 JB |
642 | int err = target; |
643 | ||
a210b028 | 644 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 645 | /* |
a210b028 DV |
646 | * For LVDS just rely on its current settings for dual-channel. |
647 | * We haven't figured out how to reliably set up different | |
648 | * single/dual channel state, if we even can. | |
79e53945 | 649 | */ |
1974cad0 | 650 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
651 | clock.p2 = limit->p2.p2_fast; |
652 | else | |
653 | clock.p2 = limit->p2.p2_slow; | |
654 | } else { | |
655 | if (target < limit->p2.dot_limit) | |
656 | clock.p2 = limit->p2.p2_slow; | |
657 | else | |
658 | clock.p2 = limit->p2.p2_fast; | |
659 | } | |
660 | ||
0206e353 | 661 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 662 | |
42158660 ZY |
663 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
664 | clock.m1++) { | |
665 | for (clock.m2 = limit->m2.min; | |
666 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
667 | for (clock.n = limit->n.min; |
668 | clock.n <= limit->n.max; clock.n++) { | |
669 | for (clock.p1 = limit->p1.min; | |
670 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
671 | int this_err; |
672 | ||
ac58c3f0 | 673 | pineview_clock(refclk, &clock); |
1b894b59 CW |
674 | if (!intel_PLL_is_valid(dev, limit, |
675 | &clock)) | |
79e53945 | 676 | continue; |
cec2f356 SP |
677 | if (match_clock && |
678 | clock.p != match_clock->p) | |
679 | continue; | |
79e53945 JB |
680 | |
681 | this_err = abs(clock.dot - target); | |
682 | if (this_err < err) { | |
683 | *best_clock = clock; | |
684 | err = this_err; | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | } | |
690 | ||
691 | return (err != target); | |
692 | } | |
693 | ||
d4906093 | 694 | static bool |
ee9300bb DV |
695 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
696 | int target, int refclk, intel_clock_t *match_clock, | |
697 | intel_clock_t *best_clock) | |
d4906093 ML |
698 | { |
699 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
700 | intel_clock_t clock; |
701 | int max_n; | |
702 | bool found; | |
6ba770dc AJ |
703 | /* approximately equals target * 0.00585 */ |
704 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
705 | found = false; |
706 | ||
707 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 708 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
709 | clock.p2 = limit->p2.p2_fast; |
710 | else | |
711 | clock.p2 = limit->p2.p2_slow; | |
712 | } else { | |
713 | if (target < limit->p2.dot_limit) | |
714 | clock.p2 = limit->p2.p2_slow; | |
715 | else | |
716 | clock.p2 = limit->p2.p2_fast; | |
717 | } | |
718 | ||
719 | memset(best_clock, 0, sizeof(*best_clock)); | |
720 | max_n = limit->n.max; | |
f77f13e2 | 721 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 722 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 723 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
724 | for (clock.m1 = limit->m1.max; |
725 | clock.m1 >= limit->m1.min; clock.m1--) { | |
726 | for (clock.m2 = limit->m2.max; | |
727 | clock.m2 >= limit->m2.min; clock.m2--) { | |
728 | for (clock.p1 = limit->p1.max; | |
729 | clock.p1 >= limit->p1.min; clock.p1--) { | |
730 | int this_err; | |
731 | ||
ac58c3f0 | 732 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
733 | if (!intel_PLL_is_valid(dev, limit, |
734 | &clock)) | |
d4906093 | 735 | continue; |
1b894b59 CW |
736 | |
737 | this_err = abs(clock.dot - target); | |
d4906093 ML |
738 | if (this_err < err_most) { |
739 | *best_clock = clock; | |
740 | err_most = this_err; | |
741 | max_n = clock.n; | |
742 | found = true; | |
743 | } | |
744 | } | |
745 | } | |
746 | } | |
747 | } | |
2c07245f ZW |
748 | return found; |
749 | } | |
750 | ||
a0c4da24 | 751 | static bool |
ee9300bb DV |
752 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
753 | int target, int refclk, intel_clock_t *match_clock, | |
754 | intel_clock_t *best_clock) | |
a0c4da24 | 755 | { |
f01b7962 | 756 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 757 | intel_clock_t clock; |
69e4f900 | 758 | unsigned int bestppm = 1000000; |
27e639bf VS |
759 | /* min update 19.2 MHz */ |
760 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 761 | bool found = false; |
a0c4da24 | 762 | |
6b4bf1c4 VS |
763 | target *= 5; /* fast clock */ |
764 | ||
765 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
766 | |
767 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 768 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 769 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 770 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 771 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 772 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 773 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 774 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
775 | unsigned int ppm, diff; |
776 | ||
6b4bf1c4 VS |
777 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
778 | refclk * clock.m1); | |
779 | ||
780 | vlv_clock(refclk, &clock); | |
43b0ac53 | 781 | |
f01b7962 VS |
782 | if (!intel_PLL_is_valid(dev, limit, |
783 | &clock)) | |
43b0ac53 VS |
784 | continue; |
785 | ||
6b4bf1c4 VS |
786 | diff = abs(clock.dot - target); |
787 | ppm = div_u64(1000000ULL * diff, target); | |
788 | ||
789 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 790 | bestppm = 0; |
6b4bf1c4 | 791 | *best_clock = clock; |
49e497ef | 792 | found = true; |
43b0ac53 | 793 | } |
6b4bf1c4 | 794 | |
c686122c | 795 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 796 | bestppm = ppm; |
6b4bf1c4 | 797 | *best_clock = clock; |
49e497ef | 798 | found = true; |
a0c4da24 JB |
799 | } |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
a0c4da24 | 804 | |
49e497ef | 805 | return found; |
a0c4da24 | 806 | } |
a4fc5ed6 | 807 | |
ef9348c8 CML |
808 | static bool |
809 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
810 | int target, int refclk, intel_clock_t *match_clock, | |
811 | intel_clock_t *best_clock) | |
812 | { | |
813 | struct drm_device *dev = crtc->dev; | |
814 | intel_clock_t clock; | |
815 | uint64_t m2; | |
816 | int found = false; | |
817 | ||
818 | memset(best_clock, 0, sizeof(*best_clock)); | |
819 | ||
820 | /* | |
821 | * Based on hardware doc, the n always set to 1, and m1 always | |
822 | * set to 2. If requires to support 200Mhz refclk, we need to | |
823 | * revisit this because n may not 1 anymore. | |
824 | */ | |
825 | clock.n = 1, clock.m1 = 2; | |
826 | target *= 5; /* fast clock */ | |
827 | ||
828 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
829 | for (clock.p2 = limit->p2.p2_fast; | |
830 | clock.p2 >= limit->p2.p2_slow; | |
831 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
832 | ||
833 | clock.p = clock.p1 * clock.p2; | |
834 | ||
835 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
836 | clock.n) << 22, refclk * clock.m1); | |
837 | ||
838 | if (m2 > INT_MAX/clock.m1) | |
839 | continue; | |
840 | ||
841 | clock.m2 = m2; | |
842 | ||
843 | chv_clock(refclk, &clock); | |
844 | ||
845 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
846 | continue; | |
847 | ||
848 | /* based on hardware requirement, prefer bigger p | |
849 | */ | |
850 | if (clock.p > best_clock->p) { | |
851 | *best_clock = clock; | |
852 | found = true; | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return found; | |
858 | } | |
859 | ||
20ddf665 VS |
860 | bool intel_crtc_active(struct drm_crtc *crtc) |
861 | { | |
862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
863 | ||
864 | /* Be paranoid as we can arrive here with only partial | |
865 | * state retrieved from the hardware during setup. | |
866 | * | |
241bfc38 | 867 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
868 | * as Haswell has gained clock readout/fastboot support. |
869 | * | |
66e514c1 | 870 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
871 | * properly reconstruct framebuffers. |
872 | */ | |
f4510a27 | 873 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 874 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
875 | } |
876 | ||
a5c961d1 PZ |
877 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
878 | enum pipe pipe) | |
879 | { | |
880 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
882 | ||
3b117c8f | 883 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
884 | } |
885 | ||
57e22f4a | 886 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
887 | { |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 889 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
890 | |
891 | frame = I915_READ(frame_reg); | |
892 | ||
893 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 894 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
895 | } |
896 | ||
9d0498a2 JB |
897 | /** |
898 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
899 | * @dev: drm device | |
900 | * @pipe: pipe to wait for | |
901 | * | |
902 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
903 | * mode setting code. | |
904 | */ | |
905 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 906 | { |
9d0498a2 | 907 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 908 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 909 | |
57e22f4a VS |
910 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
911 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
912 | return; |
913 | } | |
914 | ||
300387c0 CW |
915 | /* Clear existing vblank status. Note this will clear any other |
916 | * sticky status fields as well. | |
917 | * | |
918 | * This races with i915_driver_irq_handler() with the result | |
919 | * that either function could miss a vblank event. Here it is not | |
920 | * fatal, as we will either wait upon the next vblank interrupt or | |
921 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
922 | * called during modeset at which time the GPU should be idle and | |
923 | * should *not* be performing page flips and thus not waiting on | |
924 | * vblanks... | |
925 | * Currently, the result of us stealing a vblank from the irq | |
926 | * handler is that a single frame will be skipped during swapbuffers. | |
927 | */ | |
928 | I915_WRITE(pipestat_reg, | |
929 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
930 | ||
9d0498a2 | 931 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
932 | if (wait_for(I915_READ(pipestat_reg) & |
933 | PIPE_VBLANK_INTERRUPT_STATUS, | |
934 | 50)) | |
9d0498a2 JB |
935 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
936 | } | |
937 | ||
fbf49ea2 VS |
938 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
939 | { | |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | u32 reg = PIPEDSL(pipe); | |
942 | u32 line1, line2; | |
943 | u32 line_mask; | |
944 | ||
945 | if (IS_GEN2(dev)) | |
946 | line_mask = DSL_LINEMASK_GEN2; | |
947 | else | |
948 | line_mask = DSL_LINEMASK_GEN3; | |
949 | ||
950 | line1 = I915_READ(reg) & line_mask; | |
951 | mdelay(5); | |
952 | line2 = I915_READ(reg) & line_mask; | |
953 | ||
954 | return line1 == line2; | |
955 | } | |
956 | ||
ab7ad7f6 KP |
957 | /* |
958 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
959 | * @dev: drm device |
960 | * @pipe: pipe to wait for | |
961 | * | |
962 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
963 | * spinning on the vblank interrupt status bit, since we won't actually | |
964 | * see an interrupt when the pipe is disabled. | |
965 | * | |
ab7ad7f6 KP |
966 | * On Gen4 and above: |
967 | * wait for the pipe register state bit to turn off | |
968 | * | |
969 | * Otherwise: | |
970 | * wait for the display line value to settle (it usually | |
971 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 972 | * |
9d0498a2 | 973 | */ |
58e10eb9 | 974 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
975 | { |
976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
977 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
978 | pipe); | |
ab7ad7f6 KP |
979 | |
980 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 981 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
982 | |
983 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
984 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
985 | 100)) | |
284637d9 | 986 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 987 | } else { |
ab7ad7f6 | 988 | /* Wait for the display line to settle */ |
fbf49ea2 | 989 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 990 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 991 | } |
79e53945 JB |
992 | } |
993 | ||
b0ea7d37 DL |
994 | /* |
995 | * ibx_digital_port_connected - is the specified port connected? | |
996 | * @dev_priv: i915 private structure | |
997 | * @port: the port to test | |
998 | * | |
999 | * Returns true if @port is connected, false otherwise. | |
1000 | */ | |
1001 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1002 | struct intel_digital_port *port) | |
1003 | { | |
1004 | u32 bit; | |
1005 | ||
c36346e3 | 1006 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1007 | switch (port->port) { |
c36346e3 DL |
1008 | case PORT_B: |
1009 | bit = SDE_PORTB_HOTPLUG; | |
1010 | break; | |
1011 | case PORT_C: | |
1012 | bit = SDE_PORTC_HOTPLUG; | |
1013 | break; | |
1014 | case PORT_D: | |
1015 | bit = SDE_PORTD_HOTPLUG; | |
1016 | break; | |
1017 | default: | |
1018 | return true; | |
1019 | } | |
1020 | } else { | |
eba905b2 | 1021 | switch (port->port) { |
c36346e3 DL |
1022 | case PORT_B: |
1023 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1024 | break; | |
1025 | case PORT_C: | |
1026 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1027 | break; | |
1028 | case PORT_D: | |
1029 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1030 | break; | |
1031 | default: | |
1032 | return true; | |
1033 | } | |
b0ea7d37 DL |
1034 | } |
1035 | ||
1036 | return I915_READ(SDEISR) & bit; | |
1037 | } | |
1038 | ||
b24e7179 JB |
1039 | static const char *state_string(bool enabled) |
1040 | { | |
1041 | return enabled ? "on" : "off"; | |
1042 | } | |
1043 | ||
1044 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1045 | void assert_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
b24e7179 JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
1050 | bool cur_state; | |
1051 | ||
1052 | reg = DPLL(pipe); | |
1053 | val = I915_READ(reg); | |
1054 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1055 | WARN(cur_state != state, | |
1056 | "PLL state assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
1058 | } | |
b24e7179 | 1059 | |
23538ef1 JN |
1060 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1061 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1062 | { | |
1063 | u32 val; | |
1064 | bool cur_state; | |
1065 | ||
1066 | mutex_lock(&dev_priv->dpio_lock); | |
1067 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1068 | mutex_unlock(&dev_priv->dpio_lock); | |
1069 | ||
1070 | cur_state = val & DSI_PLL_VCO_EN; | |
1071 | WARN(cur_state != state, | |
1072 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1073 | state_string(state), state_string(cur_state)); | |
1074 | } | |
1075 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1076 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1077 | ||
55607e8a | 1078 | struct intel_shared_dpll * |
e2b78267 DV |
1079 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1080 | { | |
1081 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1082 | ||
a43f6e0f | 1083 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1084 | return NULL; |
1085 | ||
a43f6e0f | 1086 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1087 | } |
1088 | ||
040484af | 1089 | /* For ILK+ */ |
55607e8a DV |
1090 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1091 | struct intel_shared_dpll *pll, | |
1092 | bool state) | |
040484af | 1093 | { |
040484af | 1094 | bool cur_state; |
5358901f | 1095 | struct intel_dpll_hw_state hw_state; |
040484af | 1096 | |
9d82aa17 ED |
1097 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1098 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1099 | return; | |
1100 | } | |
1101 | ||
92b27b08 | 1102 | if (WARN (!pll, |
46edb027 | 1103 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1104 | return; |
ee7b9f93 | 1105 | |
5358901f | 1106 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1107 | WARN(cur_state != state, |
5358901f DV |
1108 | "%s assertion failure (expected %s, current %s)\n", |
1109 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1110 | } |
040484af JB |
1111 | |
1112 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1113 | enum pipe pipe, bool state) | |
1114 | { | |
1115 | int reg; | |
1116 | u32 val; | |
1117 | bool cur_state; | |
ad80a810 PZ |
1118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1119 | pipe); | |
040484af | 1120 | |
affa9354 PZ |
1121 | if (HAS_DDI(dev_priv->dev)) { |
1122 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1123 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1124 | val = I915_READ(reg); |
ad80a810 | 1125 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1126 | } else { |
1127 | reg = FDI_TX_CTL(pipe); | |
1128 | val = I915_READ(reg); | |
1129 | cur_state = !!(val & FDI_TX_ENABLE); | |
1130 | } | |
040484af JB |
1131 | WARN(cur_state != state, |
1132 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1133 | state_string(state), state_string(cur_state)); | |
1134 | } | |
1135 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1136 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1137 | ||
1138 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1139 | enum pipe pipe, bool state) | |
1140 | { | |
1141 | int reg; | |
1142 | u32 val; | |
1143 | bool cur_state; | |
1144 | ||
d63fa0dc PZ |
1145 | reg = FDI_RX_CTL(pipe); |
1146 | val = I915_READ(reg); | |
1147 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1148 | WARN(cur_state != state, |
1149 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1150 | state_string(state), state_string(cur_state)); | |
1151 | } | |
1152 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1153 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1154 | ||
1155 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1156 | enum pipe pipe) | |
1157 | { | |
1158 | int reg; | |
1159 | u32 val; | |
1160 | ||
1161 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1162 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1163 | return; |
1164 | ||
bf507ef7 | 1165 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1166 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1167 | return; |
1168 | ||
040484af JB |
1169 | reg = FDI_TX_CTL(pipe); |
1170 | val = I915_READ(reg); | |
1171 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1172 | } | |
1173 | ||
55607e8a DV |
1174 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1175 | enum pipe pipe, bool state) | |
040484af JB |
1176 | { |
1177 | int reg; | |
1178 | u32 val; | |
55607e8a | 1179 | bool cur_state; |
040484af JB |
1180 | |
1181 | reg = FDI_RX_CTL(pipe); | |
1182 | val = I915_READ(reg); | |
55607e8a DV |
1183 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1184 | WARN(cur_state != state, | |
1185 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1186 | state_string(state), state_string(cur_state)); | |
040484af JB |
1187 | } |
1188 | ||
ea0760cf JB |
1189 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe) | |
1191 | { | |
1192 | int pp_reg, lvds_reg; | |
1193 | u32 val; | |
1194 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1195 | bool locked = true; |
ea0760cf JB |
1196 | |
1197 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1198 | pp_reg = PCH_PP_CONTROL; | |
1199 | lvds_reg = PCH_LVDS; | |
1200 | } else { | |
1201 | pp_reg = PP_CONTROL; | |
1202 | lvds_reg = LVDS; | |
1203 | } | |
1204 | ||
1205 | val = I915_READ(pp_reg); | |
1206 | if (!(val & PANEL_POWER_ON) || | |
1207 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1208 | locked = false; | |
1209 | ||
1210 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1211 | panel_pipe = PIPE_B; | |
1212 | ||
1213 | WARN(panel_pipe == pipe && locked, | |
1214 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1215 | pipe_name(pipe)); |
ea0760cf JB |
1216 | } |
1217 | ||
93ce0ba6 JN |
1218 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1219 | enum pipe pipe, bool state) | |
1220 | { | |
1221 | struct drm_device *dev = dev_priv->dev; | |
1222 | bool cur_state; | |
1223 | ||
d9d82081 | 1224 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1225 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1226 | else |
5efb3e28 | 1227 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1228 | |
1229 | WARN(cur_state != state, | |
1230 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1231 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1232 | } | |
1233 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1234 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1235 | ||
b840d907 JB |
1236 | void assert_pipe(struct drm_i915_private *dev_priv, |
1237 | enum pipe pipe, bool state) | |
b24e7179 JB |
1238 | { |
1239 | int reg; | |
1240 | u32 val; | |
63d7bbe9 | 1241 | bool cur_state; |
702e7a56 PZ |
1242 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1243 | pipe); | |
b24e7179 | 1244 | |
8e636784 DV |
1245 | /* if we need the pipe A quirk it must be always on */ |
1246 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1247 | state = true; | |
1248 | ||
da7e29bd | 1249 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1250 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1251 | cur_state = false; |
1252 | } else { | |
1253 | reg = PIPECONF(cpu_transcoder); | |
1254 | val = I915_READ(reg); | |
1255 | cur_state = !!(val & PIPECONF_ENABLE); | |
1256 | } | |
1257 | ||
63d7bbe9 JB |
1258 | WARN(cur_state != state, |
1259 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1260 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1261 | } |
1262 | ||
931872fc CW |
1263 | static void assert_plane(struct drm_i915_private *dev_priv, |
1264 | enum plane plane, bool state) | |
b24e7179 JB |
1265 | { |
1266 | int reg; | |
1267 | u32 val; | |
931872fc | 1268 | bool cur_state; |
b24e7179 JB |
1269 | |
1270 | reg = DSPCNTR(plane); | |
1271 | val = I915_READ(reg); | |
931872fc CW |
1272 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1273 | WARN(cur_state != state, | |
1274 | "plane %c assertion failure (expected %s, current %s)\n", | |
1275 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1279 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1280 | ||
b24e7179 JB |
1281 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1282 | enum pipe pipe) | |
1283 | { | |
653e1026 | 1284 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1285 | int reg, i; |
1286 | u32 val; | |
1287 | int cur_pipe; | |
1288 | ||
653e1026 VS |
1289 | /* Primary planes are fixed to pipes on gen4+ */ |
1290 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1291 | reg = DSPCNTR(pipe); |
1292 | val = I915_READ(reg); | |
83f26f16 | 1293 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1294 | "plane %c assertion failure, should be disabled but not\n", |
1295 | plane_name(pipe)); | |
19ec1358 | 1296 | return; |
28c05794 | 1297 | } |
19ec1358 | 1298 | |
b24e7179 | 1299 | /* Need to check both planes against the pipe */ |
08e2a7de | 1300 | for_each_pipe(i) { |
b24e7179 JB |
1301 | reg = DSPCNTR(i); |
1302 | val = I915_READ(reg); | |
1303 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1304 | DISPPLANE_SEL_PIPE_SHIFT; | |
1305 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1306 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1307 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1308 | } |
1309 | } | |
1310 | ||
19332d7a JB |
1311 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1312 | enum pipe pipe) | |
1313 | { | |
20674eef | 1314 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1315 | int reg, sprite; |
19332d7a JB |
1316 | u32 val; |
1317 | ||
20674eef | 1318 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1319 | for_each_sprite(pipe, sprite) { |
1320 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1321 | val = I915_READ(reg); |
83f26f16 | 1322 | WARN(val & SP_ENABLE, |
20674eef | 1323 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1324 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1325 | } |
1326 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1327 | reg = SPRCTL(pipe); | |
19332d7a | 1328 | val = I915_READ(reg); |
83f26f16 | 1329 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1330 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1331 | plane_name(pipe), pipe_name(pipe)); |
1332 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1333 | reg = DVSCNTR(pipe); | |
19332d7a | 1334 | val = I915_READ(reg); |
83f26f16 | 1335 | WARN(val & DVS_ENABLE, |
06da8da2 | 1336 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1337 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1338 | } |
1339 | } | |
1340 | ||
89eff4be | 1341 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1342 | { |
1343 | u32 val; | |
1344 | bool enabled; | |
1345 | ||
89eff4be | 1346 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1347 | |
92f2584a JB |
1348 | val = I915_READ(PCH_DREF_CONTROL); |
1349 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1350 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1351 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1352 | } | |
1353 | ||
ab9412ba DV |
1354 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1355 | enum pipe pipe) | |
92f2584a JB |
1356 | { |
1357 | int reg; | |
1358 | u32 val; | |
1359 | bool enabled; | |
1360 | ||
ab9412ba | 1361 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1362 | val = I915_READ(reg); |
1363 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1364 | WARN(enabled, |
1365 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1366 | pipe_name(pipe)); | |
92f2584a JB |
1367 | } |
1368 | ||
4e634389 KP |
1369 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1370 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1371 | { |
1372 | if ((val & DP_PORT_EN) == 0) | |
1373 | return false; | |
1374 | ||
1375 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1376 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1377 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1378 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1379 | return false; | |
44f37d1f CML |
1380 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1381 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1382 | return false; | |
f0575e92 KP |
1383 | } else { |
1384 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1385 | return false; | |
1386 | } | |
1387 | return true; | |
1388 | } | |
1389 | ||
1519b995 KP |
1390 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1391 | enum pipe pipe, u32 val) | |
1392 | { | |
dc0fa718 | 1393 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1394 | return false; |
1395 | ||
1396 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1397 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1398 | return false; |
44f37d1f CML |
1399 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1400 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1401 | return false; | |
1519b995 | 1402 | } else { |
dc0fa718 | 1403 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1404 | return false; |
1405 | } | |
1406 | return true; | |
1407 | } | |
1408 | ||
1409 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1410 | enum pipe pipe, u32 val) | |
1411 | { | |
1412 | if ((val & LVDS_PORT_EN) == 0) | |
1413 | return false; | |
1414 | ||
1415 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1416 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1417 | return false; | |
1418 | } else { | |
1419 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1420 | return false; | |
1421 | } | |
1422 | return true; | |
1423 | } | |
1424 | ||
1425 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1426 | enum pipe pipe, u32 val) | |
1427 | { | |
1428 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1429 | return false; | |
1430 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1431 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1432 | return false; | |
1433 | } else { | |
1434 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1435 | return false; | |
1436 | } | |
1437 | return true; | |
1438 | } | |
1439 | ||
291906f1 | 1440 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1441 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1442 | { |
47a05eca | 1443 | u32 val = I915_READ(reg); |
4e634389 | 1444 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1445 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1446 | reg, pipe_name(pipe)); |
de9a35ab | 1447 | |
75c5da27 DV |
1448 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1449 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1450 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1451 | } |
1452 | ||
1453 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1454 | enum pipe pipe, int reg) | |
1455 | { | |
47a05eca | 1456 | u32 val = I915_READ(reg); |
b70ad586 | 1457 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1458 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1459 | reg, pipe_name(pipe)); |
de9a35ab | 1460 | |
dc0fa718 | 1461 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1462 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1463 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1464 | } |
1465 | ||
1466 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1467 | enum pipe pipe) | |
1468 | { | |
1469 | int reg; | |
1470 | u32 val; | |
291906f1 | 1471 | |
f0575e92 KP |
1472 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1475 | |
1476 | reg = PCH_ADPA; | |
1477 | val = I915_READ(reg); | |
b70ad586 | 1478 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 JB |
1481 | |
1482 | reg = PCH_LVDS; | |
1483 | val = I915_READ(reg); | |
b70ad586 | 1484 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
40e9cf64 JB |
1493 | static void intel_init_dpio(struct drm_device *dev) |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | ||
1497 | if (!IS_VALLEYVIEW(dev)) | |
1498 | return; | |
1499 | ||
a09caddd CML |
1500 | /* |
1501 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1502 | * CHV x1 PHY (DP/HDMI D) | |
1503 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1504 | */ | |
1505 | if (IS_CHERRYVIEW(dev)) { | |
1506 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1507 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1508 | } else { | |
1509 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1510 | } | |
5382f5f3 JB |
1511 | } |
1512 | ||
1513 | static void intel_reset_dpio(struct drm_device *dev) | |
1514 | { | |
1515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1516 | ||
076ed3b2 CML |
1517 | if (IS_CHERRYVIEW(dev)) { |
1518 | enum dpio_phy phy; | |
1519 | u32 val; | |
1520 | ||
1521 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1522 | /* Poll for phypwrgood signal */ | |
1523 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1524 | PHY_POWERGOOD(phy), 1)) | |
1525 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1526 | ||
1527 | /* | |
1528 | * Deassert common lane reset for PHY. | |
1529 | * | |
1530 | * This should only be done on init and resume from S3 | |
1531 | * with both PLLs disabled, or we risk losing DPIO and | |
1532 | * PLL synchronization. | |
1533 | */ | |
1534 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1535 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1536 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1537 | } | |
076ed3b2 | 1538 | } |
40e9cf64 JB |
1539 | } |
1540 | ||
426115cf | 1541 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1542 | { |
426115cf DV |
1543 | struct drm_device *dev = crtc->base.dev; |
1544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1545 | int reg = DPLL(crtc->pipe); | |
1546 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1547 | |
426115cf | 1548 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1549 | |
1550 | /* No really, not for ILK+ */ | |
1551 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1552 | ||
1553 | /* PLL is protected by panel, make sure we can write it */ | |
1554 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1555 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1556 | |
426115cf DV |
1557 | I915_WRITE(reg, dpll); |
1558 | POSTING_READ(reg); | |
1559 | udelay(150); | |
1560 | ||
1561 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1562 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1563 | ||
1564 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1565 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1566 | |
1567 | /* We do this three times for luck */ | |
426115cf | 1568 | I915_WRITE(reg, dpll); |
87442f73 DV |
1569 | POSTING_READ(reg); |
1570 | udelay(150); /* wait for warmup */ | |
426115cf | 1571 | I915_WRITE(reg, dpll); |
87442f73 DV |
1572 | POSTING_READ(reg); |
1573 | udelay(150); /* wait for warmup */ | |
426115cf | 1574 | I915_WRITE(reg, dpll); |
87442f73 DV |
1575 | POSTING_READ(reg); |
1576 | udelay(150); /* wait for warmup */ | |
1577 | } | |
1578 | ||
9d556c99 CML |
1579 | static void chv_enable_pll(struct intel_crtc *crtc) |
1580 | { | |
1581 | struct drm_device *dev = crtc->base.dev; | |
1582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1583 | int pipe = crtc->pipe; | |
1584 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1585 | u32 tmp; |
1586 | ||
1587 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1588 | ||
1589 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1590 | ||
1591 | mutex_lock(&dev_priv->dpio_lock); | |
1592 | ||
1593 | /* Enable back the 10bit clock to display controller */ | |
1594 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1595 | tmp |= DPIO_DCLKP_EN; | |
1596 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1597 | ||
1598 | /* | |
1599 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1600 | */ | |
1601 | udelay(1); | |
1602 | ||
1603 | /* Enable PLL */ | |
a11b0703 | 1604 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1605 | |
1606 | /* Check PLL is locked */ | |
a11b0703 | 1607 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1608 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1609 | ||
a11b0703 VS |
1610 | /* not sure when this should be written */ |
1611 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1612 | POSTING_READ(DPLL_MD(pipe)); | |
1613 | ||
9d556c99 CML |
1614 | mutex_unlock(&dev_priv->dpio_lock); |
1615 | } | |
1616 | ||
66e3d5c0 | 1617 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1618 | { |
66e3d5c0 DV |
1619 | struct drm_device *dev = crtc->base.dev; |
1620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1621 | int reg = DPLL(crtc->pipe); | |
1622 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1623 | |
66e3d5c0 | 1624 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1625 | |
63d7bbe9 | 1626 | /* No really, not for ILK+ */ |
3d13ef2e | 1627 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1628 | |
1629 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1630 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1631 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1632 | |
66e3d5c0 DV |
1633 | I915_WRITE(reg, dpll); |
1634 | ||
1635 | /* Wait for the clocks to stabilize. */ | |
1636 | POSTING_READ(reg); | |
1637 | udelay(150); | |
1638 | ||
1639 | if (INTEL_INFO(dev)->gen >= 4) { | |
1640 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1641 | crtc->config.dpll_hw_state.dpll_md); | |
1642 | } else { | |
1643 | /* The pixel multiplier can only be updated once the | |
1644 | * DPLL is enabled and the clocks are stable. | |
1645 | * | |
1646 | * So write it again. | |
1647 | */ | |
1648 | I915_WRITE(reg, dpll); | |
1649 | } | |
63d7bbe9 JB |
1650 | |
1651 | /* We do this three times for luck */ | |
66e3d5c0 | 1652 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1653 | POSTING_READ(reg); |
1654 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1655 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1656 | POSTING_READ(reg); |
1657 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1658 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1659 | POSTING_READ(reg); |
1660 | udelay(150); /* wait for warmup */ | |
1661 | } | |
1662 | ||
1663 | /** | |
50b44a44 | 1664 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1665 | * @dev_priv: i915 private structure |
1666 | * @pipe: pipe PLL to disable | |
1667 | * | |
1668 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1669 | * | |
1670 | * Note! This is for pre-ILK only. | |
1671 | */ | |
50b44a44 | 1672 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1673 | { |
63d7bbe9 JB |
1674 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1675 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1676 | return; | |
1677 | ||
1678 | /* Make sure the pipe isn't still relying on us */ | |
1679 | assert_pipe_disabled(dev_priv, pipe); | |
1680 | ||
50b44a44 DV |
1681 | I915_WRITE(DPLL(pipe), 0); |
1682 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1683 | } |
1684 | ||
f6071166 JB |
1685 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1686 | { | |
1687 | u32 val = 0; | |
1688 | ||
1689 | /* Make sure the pipe isn't still relying on us */ | |
1690 | assert_pipe_disabled(dev_priv, pipe); | |
1691 | ||
e5cbfbfb ID |
1692 | /* |
1693 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1694 | * The latter is needed for VGA hotplug / manual detection. | |
1695 | */ | |
f6071166 | 1696 | if (pipe == PIPE_B) |
e5cbfbfb | 1697 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1698 | I915_WRITE(DPLL(pipe), val); |
1699 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1700 | |
1701 | } | |
1702 | ||
1703 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1704 | { | |
d752048d | 1705 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1706 | u32 val; |
1707 | ||
a11b0703 VS |
1708 | /* Make sure the pipe isn't still relying on us */ |
1709 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1710 | |
a11b0703 VS |
1711 | /* Set PLL en = 0 */ |
1712 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1713 | if (pipe != PIPE_A) | |
1714 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1715 | I915_WRITE(DPLL(pipe), val); | |
1716 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1717 | |
1718 | mutex_lock(&dev_priv->dpio_lock); | |
1719 | ||
1720 | /* Disable 10bit clock to display controller */ | |
1721 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1722 | val &= ~DPIO_DCLKP_EN; | |
1723 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1724 | ||
61407f6d VS |
1725 | /* disable left/right clock distribution */ |
1726 | if (pipe != PIPE_B) { | |
1727 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1728 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1729 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1730 | } else { | |
1731 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1732 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1733 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1734 | } | |
1735 | ||
d752048d | 1736 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1737 | } |
1738 | ||
e4607fcf CML |
1739 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1740 | struct intel_digital_port *dport) | |
89b667f8 JB |
1741 | { |
1742 | u32 port_mask; | |
00fc31b7 | 1743 | int dpll_reg; |
89b667f8 | 1744 | |
e4607fcf CML |
1745 | switch (dport->port) { |
1746 | case PORT_B: | |
89b667f8 | 1747 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1748 | dpll_reg = DPLL(0); |
e4607fcf CML |
1749 | break; |
1750 | case PORT_C: | |
89b667f8 | 1751 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1752 | dpll_reg = DPLL(0); |
1753 | break; | |
1754 | case PORT_D: | |
1755 | port_mask = DPLL_PORTD_READY_MASK; | |
1756 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1757 | break; |
1758 | default: | |
1759 | BUG(); | |
1760 | } | |
89b667f8 | 1761 | |
00fc31b7 | 1762 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1763 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1764 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1765 | } |
1766 | ||
b14b1055 DV |
1767 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1768 | { | |
1769 | struct drm_device *dev = crtc->base.dev; | |
1770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1771 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1772 | ||
be19f0ff CW |
1773 | if (WARN_ON(pll == NULL)) |
1774 | return; | |
1775 | ||
b14b1055 DV |
1776 | WARN_ON(!pll->refcount); |
1777 | if (pll->active == 0) { | |
1778 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1779 | WARN_ON(pll->on); | |
1780 | assert_shared_dpll_disabled(dev_priv, pll); | |
1781 | ||
1782 | pll->mode_set(dev_priv, pll); | |
1783 | } | |
1784 | } | |
1785 | ||
92f2584a | 1786 | /** |
85b3894f | 1787 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1788 | * @dev_priv: i915 private structure |
1789 | * @pipe: pipe PLL to enable | |
1790 | * | |
1791 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1792 | * drives the transcoder clock. | |
1793 | */ | |
85b3894f | 1794 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1795 | { |
3d13ef2e DL |
1796 | struct drm_device *dev = crtc->base.dev; |
1797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1798 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1799 | |
87a875bb | 1800 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1801 | return; |
1802 | ||
1803 | if (WARN_ON(pll->refcount == 0)) | |
1804 | return; | |
ee7b9f93 | 1805 | |
46edb027 DV |
1806 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1807 | pll->name, pll->active, pll->on, | |
e2b78267 | 1808 | crtc->base.base.id); |
92f2584a | 1809 | |
cdbd2316 DV |
1810 | if (pll->active++) { |
1811 | WARN_ON(!pll->on); | |
e9d6944e | 1812 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1813 | return; |
1814 | } | |
f4a091c7 | 1815 | WARN_ON(pll->on); |
ee7b9f93 | 1816 | |
46edb027 | 1817 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1818 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1819 | pll->on = true; |
92f2584a JB |
1820 | } |
1821 | ||
e2b78267 | 1822 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1823 | { |
3d13ef2e DL |
1824 | struct drm_device *dev = crtc->base.dev; |
1825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1826 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1827 | |
92f2584a | 1828 | /* PCH only available on ILK+ */ |
3d13ef2e | 1829 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1830 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1831 | return; |
92f2584a | 1832 | |
48da64a8 CW |
1833 | if (WARN_ON(pll->refcount == 0)) |
1834 | return; | |
7a419866 | 1835 | |
46edb027 DV |
1836 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1837 | pll->name, pll->active, pll->on, | |
e2b78267 | 1838 | crtc->base.base.id); |
7a419866 | 1839 | |
48da64a8 | 1840 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1841 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1842 | return; |
1843 | } | |
1844 | ||
e9d6944e | 1845 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1846 | WARN_ON(!pll->on); |
cdbd2316 | 1847 | if (--pll->active) |
7a419866 | 1848 | return; |
ee7b9f93 | 1849 | |
46edb027 | 1850 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1851 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1852 | pll->on = false; |
92f2584a JB |
1853 | } |
1854 | ||
b8a4f404 PZ |
1855 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1856 | enum pipe pipe) | |
040484af | 1857 | { |
23670b32 | 1858 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1859 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1861 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1862 | |
1863 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1864 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1865 | |
1866 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1867 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1868 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1869 | |
1870 | /* FDI must be feeding us bits for PCH ports */ | |
1871 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1872 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1873 | ||
23670b32 DV |
1874 | if (HAS_PCH_CPT(dev)) { |
1875 | /* Workaround: Set the timing override bit before enabling the | |
1876 | * pch transcoder. */ | |
1877 | reg = TRANS_CHICKEN2(pipe); | |
1878 | val = I915_READ(reg); | |
1879 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1880 | I915_WRITE(reg, val); | |
59c859d6 | 1881 | } |
23670b32 | 1882 | |
ab9412ba | 1883 | reg = PCH_TRANSCONF(pipe); |
040484af | 1884 | val = I915_READ(reg); |
5f7f726d | 1885 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1886 | |
1887 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1888 | /* | |
1889 | * make the BPC in transcoder be consistent with | |
1890 | * that in pipeconf reg. | |
1891 | */ | |
dfd07d72 DV |
1892 | val &= ~PIPECONF_BPC_MASK; |
1893 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1894 | } |
5f7f726d PZ |
1895 | |
1896 | val &= ~TRANS_INTERLACE_MASK; | |
1897 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1898 | if (HAS_PCH_IBX(dev_priv->dev) && |
1899 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1900 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1901 | else | |
1902 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1903 | else |
1904 | val |= TRANS_PROGRESSIVE; | |
1905 | ||
040484af JB |
1906 | I915_WRITE(reg, val | TRANS_ENABLE); |
1907 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1908 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1909 | } |
1910 | ||
8fb033d7 | 1911 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1912 | enum transcoder cpu_transcoder) |
040484af | 1913 | { |
8fb033d7 | 1914 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1915 | |
1916 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1917 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1918 | |
8fb033d7 | 1919 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1920 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1921 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1922 | |
223a6fdf PZ |
1923 | /* Workaround: set timing override bit. */ |
1924 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1925 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1926 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1927 | ||
25f3ef11 | 1928 | val = TRANS_ENABLE; |
937bb610 | 1929 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1930 | |
9a76b1c6 PZ |
1931 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1932 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1933 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1934 | else |
1935 | val |= TRANS_PROGRESSIVE; | |
1936 | ||
ab9412ba DV |
1937 | I915_WRITE(LPT_TRANSCONF, val); |
1938 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1939 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1940 | } |
1941 | ||
b8a4f404 PZ |
1942 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1943 | enum pipe pipe) | |
040484af | 1944 | { |
23670b32 DV |
1945 | struct drm_device *dev = dev_priv->dev; |
1946 | uint32_t reg, val; | |
040484af JB |
1947 | |
1948 | /* FDI relies on the transcoder */ | |
1949 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1950 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1951 | ||
291906f1 JB |
1952 | /* Ports must be off as well */ |
1953 | assert_pch_ports_disabled(dev_priv, pipe); | |
1954 | ||
ab9412ba | 1955 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1956 | val = I915_READ(reg); |
1957 | val &= ~TRANS_ENABLE; | |
1958 | I915_WRITE(reg, val); | |
1959 | /* wait for PCH transcoder off, transcoder state */ | |
1960 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1961 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1962 | |
1963 | if (!HAS_PCH_IBX(dev)) { | |
1964 | /* Workaround: Clear the timing override chicken bit again. */ | |
1965 | reg = TRANS_CHICKEN2(pipe); | |
1966 | val = I915_READ(reg); | |
1967 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1968 | I915_WRITE(reg, val); | |
1969 | } | |
040484af JB |
1970 | } |
1971 | ||
ab4d966c | 1972 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1973 | { |
8fb033d7 PZ |
1974 | u32 val; |
1975 | ||
ab9412ba | 1976 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1977 | val &= ~TRANS_ENABLE; |
ab9412ba | 1978 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1979 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1980 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1981 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1982 | |
1983 | /* Workaround: clear timing override bit. */ | |
1984 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1985 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1986 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1987 | } |
1988 | ||
b24e7179 | 1989 | /** |
309cfea8 | 1990 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1991 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1992 | * |
0372264a | 1993 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1994 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1995 | */ |
e1fdc473 | 1996 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1997 | { |
0372264a PZ |
1998 | struct drm_device *dev = crtc->base.dev; |
1999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2000 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2001 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2002 | pipe); | |
1a240d4d | 2003 | enum pipe pch_transcoder; |
b24e7179 JB |
2004 | int reg; |
2005 | u32 val; | |
2006 | ||
58c6eaa2 | 2007 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2008 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2009 | assert_sprites_disabled(dev_priv, pipe); |
2010 | ||
681e5811 | 2011 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2012 | pch_transcoder = TRANSCODER_A; |
2013 | else | |
2014 | pch_transcoder = pipe; | |
2015 | ||
b24e7179 JB |
2016 | /* |
2017 | * A pipe without a PLL won't actually be able to drive bits from | |
2018 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2019 | * need the check. | |
2020 | */ | |
2021 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2022 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2023 | assert_dsi_pll_enabled(dev_priv); |
2024 | else | |
2025 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2026 | else { |
30421c4f | 2027 | if (crtc->config.has_pch_encoder) { |
040484af | 2028 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2029 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2030 | assert_fdi_tx_pll_enabled(dev_priv, |
2031 | (enum pipe) cpu_transcoder); | |
040484af JB |
2032 | } |
2033 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2034 | } | |
b24e7179 | 2035 | |
702e7a56 | 2036 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2037 | val = I915_READ(reg); |
7ad25d48 PZ |
2038 | if (val & PIPECONF_ENABLE) { |
2039 | WARN_ON(!(pipe == PIPE_A && | |
2040 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2041 | return; |
7ad25d48 | 2042 | } |
00d70b15 CW |
2043 | |
2044 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2045 | POSTING_READ(reg); |
b24e7179 JB |
2046 | } |
2047 | ||
2048 | /** | |
309cfea8 | 2049 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2050 | * @dev_priv: i915 private structure |
2051 | * @pipe: pipe to disable | |
2052 | * | |
2053 | * Disable @pipe, making sure that various hardware specific requirements | |
2054 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2055 | * | |
2056 | * @pipe should be %PIPE_A or %PIPE_B. | |
2057 | * | |
2058 | * Will wait until the pipe has shut down before returning. | |
2059 | */ | |
2060 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2061 | enum pipe pipe) | |
2062 | { | |
702e7a56 PZ |
2063 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2064 | pipe); | |
b24e7179 JB |
2065 | int reg; |
2066 | u32 val; | |
2067 | ||
2068 | /* | |
2069 | * Make sure planes won't keep trying to pump pixels to us, | |
2070 | * or we might hang the display. | |
2071 | */ | |
2072 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2073 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2074 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2075 | |
2076 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2077 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2078 | return; | |
2079 | ||
702e7a56 | 2080 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2081 | val = I915_READ(reg); |
00d70b15 CW |
2082 | if ((val & PIPECONF_ENABLE) == 0) |
2083 | return; | |
2084 | ||
2085 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2086 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2087 | } | |
2088 | ||
d74362c9 KP |
2089 | /* |
2090 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2091 | * trigger in order to latch. The display address reg provides this. | |
2092 | */ | |
1dba99f4 VS |
2093 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2094 | enum plane plane) | |
d74362c9 | 2095 | { |
3d13ef2e DL |
2096 | struct drm_device *dev = dev_priv->dev; |
2097 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2098 | |
2099 | I915_WRITE(reg, I915_READ(reg)); | |
2100 | POSTING_READ(reg); | |
d74362c9 KP |
2101 | } |
2102 | ||
b24e7179 | 2103 | /** |
262ca2b0 | 2104 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2105 | * @dev_priv: i915 private structure |
2106 | * @plane: plane to enable | |
2107 | * @pipe: pipe being fed | |
2108 | * | |
2109 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2110 | */ | |
262ca2b0 MR |
2111 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2112 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2113 | { |
33c3b0d1 | 2114 | struct drm_device *dev = dev_priv->dev; |
939c2fe8 VS |
2115 | struct intel_crtc *intel_crtc = |
2116 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2117 | int reg; |
2118 | u32 val; | |
2119 | ||
2120 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2121 | assert_pipe_enabled(dev_priv, pipe); | |
2122 | ||
98ec7739 VS |
2123 | if (intel_crtc->primary_enabled) |
2124 | return; | |
0037f71c | 2125 | |
4c445e0e | 2126 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2127 | |
b24e7179 JB |
2128 | reg = DSPCNTR(plane); |
2129 | val = I915_READ(reg); | |
10efa932 | 2130 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2131 | |
2132 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2133 | intel_flush_primary_plane(dev_priv, plane); |
33c3b0d1 VS |
2134 | |
2135 | /* | |
2136 | * BDW signals flip done immediately if the plane | |
2137 | * is disabled, even if the plane enable is already | |
2138 | * armed to occur at the next vblank :( | |
2139 | */ | |
2140 | if (IS_BROADWELL(dev)) | |
2141 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2142 | } |
2143 | ||
b24e7179 | 2144 | /** |
262ca2b0 | 2145 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2146 | * @dev_priv: i915 private structure |
2147 | * @plane: plane to disable | |
2148 | * @pipe: pipe consuming the data | |
2149 | * | |
2150 | * Disable @plane; should be an independent operation. | |
2151 | */ | |
262ca2b0 MR |
2152 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2153 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2154 | { |
939c2fe8 VS |
2155 | struct intel_crtc *intel_crtc = |
2156 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2157 | int reg; |
2158 | u32 val; | |
2159 | ||
98ec7739 VS |
2160 | if (!intel_crtc->primary_enabled) |
2161 | return; | |
0037f71c | 2162 | |
4c445e0e | 2163 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2164 | |
b24e7179 JB |
2165 | reg = DSPCNTR(plane); |
2166 | val = I915_READ(reg); | |
10efa932 | 2167 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2168 | |
2169 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2170 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2171 | } |
2172 | ||
693db184 CW |
2173 | static bool need_vtd_wa(struct drm_device *dev) |
2174 | { | |
2175 | #ifdef CONFIG_INTEL_IOMMU | |
2176 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2177 | return true; | |
2178 | #endif | |
2179 | return false; | |
2180 | } | |
2181 | ||
a57ce0b2 JB |
2182 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2183 | { | |
2184 | int tile_height; | |
2185 | ||
2186 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2187 | return ALIGN(height, tile_height); | |
2188 | } | |
2189 | ||
127bd2ac | 2190 | int |
48b956c5 | 2191 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2192 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2193 | struct intel_engine_cs *pipelined) |
6b95a207 | 2194 | { |
ce453d81 | 2195 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2196 | u32 alignment; |
2197 | int ret; | |
2198 | ||
05394f39 | 2199 | switch (obj->tiling_mode) { |
6b95a207 | 2200 | case I915_TILING_NONE: |
534843da CW |
2201 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2202 | alignment = 128 * 1024; | |
a6c45cf0 | 2203 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2204 | alignment = 4 * 1024; |
2205 | else | |
2206 | alignment = 64 * 1024; | |
6b95a207 KH |
2207 | break; |
2208 | case I915_TILING_X: | |
2209 | /* pin() will align the object as required by fence */ | |
2210 | alignment = 0; | |
2211 | break; | |
2212 | case I915_TILING_Y: | |
80075d49 | 2213 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2214 | return -EINVAL; |
2215 | default: | |
2216 | BUG(); | |
2217 | } | |
2218 | ||
693db184 CW |
2219 | /* Note that the w/a also requires 64 PTE of padding following the |
2220 | * bo. We currently fill all unused PTE with the shadow page and so | |
2221 | * we should always have valid PTE following the scanout preventing | |
2222 | * the VT-d warning. | |
2223 | */ | |
2224 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2225 | alignment = 256 * 1024; | |
2226 | ||
ce453d81 | 2227 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2228 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2229 | if (ret) |
ce453d81 | 2230 | goto err_interruptible; |
6b95a207 KH |
2231 | |
2232 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2233 | * fence, whereas 965+ only requires a fence if using | |
2234 | * framebuffer compression. For simplicity, we always install | |
2235 | * a fence as the cost is not that onerous. | |
2236 | */ | |
06d98131 | 2237 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2238 | if (ret) |
2239 | goto err_unpin; | |
1690e1eb | 2240 | |
9a5a53b3 | 2241 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2242 | |
ce453d81 | 2243 | dev_priv->mm.interruptible = true; |
6b95a207 | 2244 | return 0; |
48b956c5 CW |
2245 | |
2246 | err_unpin: | |
cc98b413 | 2247 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2248 | err_interruptible: |
2249 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2250 | return ret; |
6b95a207 KH |
2251 | } |
2252 | ||
1690e1eb CW |
2253 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2254 | { | |
2255 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2256 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2257 | } |
2258 | ||
c2c75131 DV |
2259 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2260 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2261 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2262 | unsigned int tiling_mode, | |
2263 | unsigned int cpp, | |
2264 | unsigned int pitch) | |
c2c75131 | 2265 | { |
bc752862 CW |
2266 | if (tiling_mode != I915_TILING_NONE) { |
2267 | unsigned int tile_rows, tiles; | |
c2c75131 | 2268 | |
bc752862 CW |
2269 | tile_rows = *y / 8; |
2270 | *y %= 8; | |
c2c75131 | 2271 | |
bc752862 CW |
2272 | tiles = *x / (512/cpp); |
2273 | *x %= 512/cpp; | |
2274 | ||
2275 | return tile_rows * pitch * 8 + tiles * 4096; | |
2276 | } else { | |
2277 | unsigned int offset; | |
2278 | ||
2279 | offset = *y * pitch + *x * cpp; | |
2280 | *y = 0; | |
2281 | *x = (offset & 4095) / cpp; | |
2282 | return offset & -4096; | |
2283 | } | |
c2c75131 DV |
2284 | } |
2285 | ||
46f297fb JB |
2286 | int intel_format_to_fourcc(int format) |
2287 | { | |
2288 | switch (format) { | |
2289 | case DISPPLANE_8BPP: | |
2290 | return DRM_FORMAT_C8; | |
2291 | case DISPPLANE_BGRX555: | |
2292 | return DRM_FORMAT_XRGB1555; | |
2293 | case DISPPLANE_BGRX565: | |
2294 | return DRM_FORMAT_RGB565; | |
2295 | default: | |
2296 | case DISPPLANE_BGRX888: | |
2297 | return DRM_FORMAT_XRGB8888; | |
2298 | case DISPPLANE_RGBX888: | |
2299 | return DRM_FORMAT_XBGR8888; | |
2300 | case DISPPLANE_BGRX101010: | |
2301 | return DRM_FORMAT_XRGB2101010; | |
2302 | case DISPPLANE_RGBX101010: | |
2303 | return DRM_FORMAT_XBGR2101010; | |
2304 | } | |
2305 | } | |
2306 | ||
484b41dd | 2307 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2308 | struct intel_plane_config *plane_config) |
2309 | { | |
2310 | struct drm_device *dev = crtc->base.dev; | |
2311 | struct drm_i915_gem_object *obj = NULL; | |
2312 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2313 | u32 base = plane_config->base; | |
2314 | ||
ff2652ea CW |
2315 | if (plane_config->size == 0) |
2316 | return false; | |
2317 | ||
46f297fb JB |
2318 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2319 | plane_config->size); | |
2320 | if (!obj) | |
484b41dd | 2321 | return false; |
46f297fb JB |
2322 | |
2323 | if (plane_config->tiled) { | |
2324 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2325 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2326 | } |
2327 | ||
66e514c1 DA |
2328 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2329 | mode_cmd.width = crtc->base.primary->fb->width; | |
2330 | mode_cmd.height = crtc->base.primary->fb->height; | |
2331 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2332 | |
2333 | mutex_lock(&dev->struct_mutex); | |
2334 | ||
66e514c1 | 2335 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2336 | &mode_cmd, obj)) { |
46f297fb JB |
2337 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2338 | goto out_unref_obj; | |
2339 | } | |
2340 | ||
a071fa00 | 2341 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2342 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2343 | |
2344 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2345 | return true; | |
46f297fb JB |
2346 | |
2347 | out_unref_obj: | |
2348 | drm_gem_object_unreference(&obj->base); | |
2349 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2350 | return false; |
2351 | } | |
2352 | ||
2353 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2354 | struct intel_plane_config *plane_config) | |
2355 | { | |
2356 | struct drm_device *dev = intel_crtc->base.dev; | |
2357 | struct drm_crtc *c; | |
2358 | struct intel_crtc *i; | |
2359 | struct intel_framebuffer *fb; | |
2360 | ||
66e514c1 | 2361 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2362 | return; |
2363 | ||
2364 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2365 | return; | |
2366 | ||
66e514c1 DA |
2367 | kfree(intel_crtc->base.primary->fb); |
2368 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2369 | |
2370 | /* | |
2371 | * Failed to alloc the obj, check to see if we should share | |
2372 | * an fb with another CRTC instead | |
2373 | */ | |
70e1e0ec | 2374 | for_each_crtc(dev, c) { |
484b41dd JB |
2375 | i = to_intel_crtc(c); |
2376 | ||
2377 | if (c == &intel_crtc->base) | |
2378 | continue; | |
2379 | ||
66e514c1 | 2380 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2381 | continue; |
2382 | ||
66e514c1 | 2383 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2384 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2385 | drm_framebuffer_reference(c->primary->fb); |
2386 | intel_crtc->base.primary->fb = c->primary->fb; | |
a071fa00 | 2387 | fb->obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2388 | break; |
2389 | } | |
2390 | } | |
46f297fb JB |
2391 | } |
2392 | ||
29b9bde6 DV |
2393 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2394 | struct drm_framebuffer *fb, | |
2395 | int x, int y) | |
81255565 JB |
2396 | { |
2397 | struct drm_device *dev = crtc->dev; | |
2398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2400 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2401 | struct drm_i915_gem_object *obj; |
81255565 | 2402 | int plane = intel_crtc->plane; |
e506a0c6 | 2403 | unsigned long linear_offset; |
81255565 | 2404 | u32 dspcntr; |
5eddb70b | 2405 | u32 reg; |
81255565 | 2406 | |
81255565 JB |
2407 | intel_fb = to_intel_framebuffer(fb); |
2408 | obj = intel_fb->obj; | |
81255565 | 2409 | |
5eddb70b CW |
2410 | reg = DSPCNTR(plane); |
2411 | dspcntr = I915_READ(reg); | |
81255565 JB |
2412 | /* Mask out pixel format bits in case we change it */ |
2413 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2414 | switch (fb->pixel_format) { |
2415 | case DRM_FORMAT_C8: | |
81255565 JB |
2416 | dspcntr |= DISPPLANE_8BPP; |
2417 | break; | |
57779d06 VS |
2418 | case DRM_FORMAT_XRGB1555: |
2419 | case DRM_FORMAT_ARGB1555: | |
2420 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2421 | break; |
57779d06 VS |
2422 | case DRM_FORMAT_RGB565: |
2423 | dspcntr |= DISPPLANE_BGRX565; | |
2424 | break; | |
2425 | case DRM_FORMAT_XRGB8888: | |
2426 | case DRM_FORMAT_ARGB8888: | |
2427 | dspcntr |= DISPPLANE_BGRX888; | |
2428 | break; | |
2429 | case DRM_FORMAT_XBGR8888: | |
2430 | case DRM_FORMAT_ABGR8888: | |
2431 | dspcntr |= DISPPLANE_RGBX888; | |
2432 | break; | |
2433 | case DRM_FORMAT_XRGB2101010: | |
2434 | case DRM_FORMAT_ARGB2101010: | |
2435 | dspcntr |= DISPPLANE_BGRX101010; | |
2436 | break; | |
2437 | case DRM_FORMAT_XBGR2101010: | |
2438 | case DRM_FORMAT_ABGR2101010: | |
2439 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2440 | break; |
2441 | default: | |
baba133a | 2442 | BUG(); |
81255565 | 2443 | } |
57779d06 | 2444 | |
a6c45cf0 | 2445 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2446 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2447 | dspcntr |= DISPPLANE_TILED; |
2448 | else | |
2449 | dspcntr &= ~DISPPLANE_TILED; | |
2450 | } | |
2451 | ||
de1aa629 VS |
2452 | if (IS_G4X(dev)) |
2453 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2454 | ||
5eddb70b | 2455 | I915_WRITE(reg, dspcntr); |
81255565 | 2456 | |
e506a0c6 | 2457 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2458 | |
c2c75131 DV |
2459 | if (INTEL_INFO(dev)->gen >= 4) { |
2460 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2461 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2462 | fb->bits_per_pixel / 8, | |
2463 | fb->pitches[0]); | |
c2c75131 DV |
2464 | linear_offset -= intel_crtc->dspaddr_offset; |
2465 | } else { | |
e506a0c6 | 2466 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2467 | } |
e506a0c6 | 2468 | |
f343c5f6 BW |
2469 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2470 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2471 | fb->pitches[0]); | |
01f2c773 | 2472 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2473 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2474 | I915_WRITE(DSPSURF(plane), |
2475 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2476 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2477 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2478 | } else |
f343c5f6 | 2479 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2480 | POSTING_READ(reg); |
17638cd6 JB |
2481 | } |
2482 | ||
29b9bde6 DV |
2483 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2484 | struct drm_framebuffer *fb, | |
2485 | int x, int y) | |
17638cd6 JB |
2486 | { |
2487 | struct drm_device *dev = crtc->dev; | |
2488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2490 | struct intel_framebuffer *intel_fb; | |
2491 | struct drm_i915_gem_object *obj; | |
2492 | int plane = intel_crtc->plane; | |
e506a0c6 | 2493 | unsigned long linear_offset; |
17638cd6 JB |
2494 | u32 dspcntr; |
2495 | u32 reg; | |
2496 | ||
17638cd6 JB |
2497 | intel_fb = to_intel_framebuffer(fb); |
2498 | obj = intel_fb->obj; | |
2499 | ||
2500 | reg = DSPCNTR(plane); | |
2501 | dspcntr = I915_READ(reg); | |
2502 | /* Mask out pixel format bits in case we change it */ | |
2503 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2504 | switch (fb->pixel_format) { |
2505 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2506 | dspcntr |= DISPPLANE_8BPP; |
2507 | break; | |
57779d06 VS |
2508 | case DRM_FORMAT_RGB565: |
2509 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2510 | break; |
57779d06 VS |
2511 | case DRM_FORMAT_XRGB8888: |
2512 | case DRM_FORMAT_ARGB8888: | |
2513 | dspcntr |= DISPPLANE_BGRX888; | |
2514 | break; | |
2515 | case DRM_FORMAT_XBGR8888: | |
2516 | case DRM_FORMAT_ABGR8888: | |
2517 | dspcntr |= DISPPLANE_RGBX888; | |
2518 | break; | |
2519 | case DRM_FORMAT_XRGB2101010: | |
2520 | case DRM_FORMAT_ARGB2101010: | |
2521 | dspcntr |= DISPPLANE_BGRX101010; | |
2522 | break; | |
2523 | case DRM_FORMAT_XBGR2101010: | |
2524 | case DRM_FORMAT_ABGR2101010: | |
2525 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2526 | break; |
2527 | default: | |
baba133a | 2528 | BUG(); |
17638cd6 JB |
2529 | } |
2530 | ||
2531 | if (obj->tiling_mode != I915_TILING_NONE) | |
2532 | dspcntr |= DISPPLANE_TILED; | |
2533 | else | |
2534 | dspcntr &= ~DISPPLANE_TILED; | |
2535 | ||
b42c6009 | 2536 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2537 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2538 | else | |
2539 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2540 | |
2541 | I915_WRITE(reg, dspcntr); | |
2542 | ||
e506a0c6 | 2543 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2544 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2545 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2546 | fb->bits_per_pixel / 8, | |
2547 | fb->pitches[0]); | |
c2c75131 | 2548 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2549 | |
f343c5f6 BW |
2550 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2551 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2552 | fb->pitches[0]); | |
01f2c773 | 2553 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2554 | I915_WRITE(DSPSURF(plane), |
2555 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2556 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2557 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2558 | } else { | |
2559 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2560 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2561 | } | |
17638cd6 | 2562 | POSTING_READ(reg); |
17638cd6 JB |
2563 | } |
2564 | ||
2565 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2566 | static int | |
2567 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2568 | int x, int y, enum mode_set_atomic state) | |
2569 | { | |
2570 | struct drm_device *dev = crtc->dev; | |
2571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2572 | |
6b8e6ed0 CW |
2573 | if (dev_priv->display.disable_fbc) |
2574 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2575 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2576 | |
29b9bde6 DV |
2577 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2578 | ||
2579 | return 0; | |
81255565 JB |
2580 | } |
2581 | ||
96a02917 VS |
2582 | void intel_display_handle_reset(struct drm_device *dev) |
2583 | { | |
2584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2585 | struct drm_crtc *crtc; | |
2586 | ||
2587 | /* | |
2588 | * Flips in the rings have been nuked by the reset, | |
2589 | * so complete all pending flips so that user space | |
2590 | * will get its events and not get stuck. | |
2591 | * | |
2592 | * Also update the base address of all primary | |
2593 | * planes to the the last fb to make sure we're | |
2594 | * showing the correct fb after a reset. | |
2595 | * | |
2596 | * Need to make two loops over the crtcs so that we | |
2597 | * don't try to grab a crtc mutex before the | |
2598 | * pending_flip_queue really got woken up. | |
2599 | */ | |
2600 | ||
70e1e0ec | 2601 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2603 | enum plane plane = intel_crtc->plane; | |
2604 | ||
2605 | intel_prepare_page_flip(dev, plane); | |
2606 | intel_finish_page_flip_plane(dev, plane); | |
2607 | } | |
2608 | ||
70e1e0ec | 2609 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2611 | ||
51fd371b | 2612 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2613 | /* |
2614 | * FIXME: Once we have proper support for primary planes (and | |
2615 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2616 | * a NULL crtc->primary->fb. |
947fdaad | 2617 | */ |
f4510a27 | 2618 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2619 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2620 | crtc->primary->fb, |
262ca2b0 MR |
2621 | crtc->x, |
2622 | crtc->y); | |
51fd371b | 2623 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2624 | } |
2625 | } | |
2626 | ||
14667a4b CW |
2627 | static int |
2628 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2629 | { | |
2630 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2631 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2632 | bool was_interruptible = dev_priv->mm.interruptible; | |
2633 | int ret; | |
2634 | ||
14667a4b CW |
2635 | /* Big Hammer, we also need to ensure that any pending |
2636 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2637 | * current scanout is retired before unpinning the old | |
2638 | * framebuffer. | |
2639 | * | |
2640 | * This should only fail upon a hung GPU, in which case we | |
2641 | * can safely continue. | |
2642 | */ | |
2643 | dev_priv->mm.interruptible = false; | |
2644 | ret = i915_gem_object_finish_gpu(obj); | |
2645 | dev_priv->mm.interruptible = was_interruptible; | |
2646 | ||
2647 | return ret; | |
2648 | } | |
2649 | ||
7d5e3799 CW |
2650 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2651 | { | |
2652 | struct drm_device *dev = crtc->dev; | |
2653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2655 | unsigned long flags; | |
2656 | bool pending; | |
2657 | ||
2658 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2659 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2660 | return false; | |
2661 | ||
2662 | spin_lock_irqsave(&dev->event_lock, flags); | |
2663 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2664 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2665 | ||
2666 | return pending; | |
2667 | } | |
2668 | ||
5c3b82e2 | 2669 | static int |
3c4fdcfb | 2670 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2671 | struct drm_framebuffer *fb) |
79e53945 JB |
2672 | { |
2673 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2674 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2676 | enum pipe pipe = intel_crtc->pipe; |
94352cf9 | 2677 | struct drm_framebuffer *old_fb; |
a071fa00 | 2678 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
91565c85 | 2679 | struct drm_i915_gem_object *old_obj; |
5c3b82e2 | 2680 | int ret; |
79e53945 | 2681 | |
7d5e3799 CW |
2682 | if (intel_crtc_has_pending_flip(crtc)) { |
2683 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2684 | return -EBUSY; | |
2685 | } | |
2686 | ||
79e53945 | 2687 | /* no fb bound */ |
94352cf9 | 2688 | if (!fb) { |
a5071c2f | 2689 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2690 | return 0; |
2691 | } | |
2692 | ||
7eb552ae | 2693 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2694 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2695 | plane_name(intel_crtc->plane), | |
2696 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2697 | return -EINVAL; |
79e53945 JB |
2698 | } |
2699 | ||
a071fa00 | 2700 | old_fb = crtc->primary->fb; |
91565c85 | 2701 | old_obj = old_fb ? to_intel_framebuffer(old_fb)->obj : NULL; |
a071fa00 | 2702 | |
5c3b82e2 | 2703 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2704 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2705 | if (ret == 0) | |
91565c85 | 2706 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2707 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2708 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2709 | if (ret != 0) { |
a5071c2f | 2710 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2711 | return ret; |
2712 | } | |
79e53945 | 2713 | |
bb2043de DL |
2714 | /* |
2715 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2716 | * that in compute_mode_changes we check the native mode (not the pfit | |
2717 | * mode) to see if we can flip rather than do a full mode set. In the | |
2718 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2719 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2720 | * sized surface. | |
2721 | * | |
2722 | * To fix this properly, we need to hoist the checks up into | |
2723 | * compute_mode_changes (or above), check the actual pfit state and | |
2724 | * whether the platform allows pfit disable with pipe active, and only | |
2725 | * then update the pipesrc and pfit state, even on the flip path. | |
2726 | */ | |
d330a953 | 2727 | if (i915.fastboot) { |
d7bf63f2 DL |
2728 | const struct drm_display_mode *adjusted_mode = |
2729 | &intel_crtc->config.adjusted_mode; | |
2730 | ||
4d6a3e63 | 2731 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2732 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2733 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2734 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2735 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2736 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2737 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2738 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2739 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2740 | } | |
0637d60d JB |
2741 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2742 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2743 | } |
2744 | ||
29b9bde6 | 2745 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2746 | |
f99d7069 DV |
2747 | if (intel_crtc->active) |
2748 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2749 | ||
f4510a27 | 2750 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2751 | crtc->x = x; |
2752 | crtc->y = y; | |
94352cf9 | 2753 | |
b7f1de28 | 2754 | if (old_fb) { |
d7697eea DV |
2755 | if (intel_crtc->active && old_fb != fb) |
2756 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2757 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2758 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2759 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2760 | } |
652c393a | 2761 | |
8ac36ec1 | 2762 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2763 | intel_update_fbc(dev); |
5c3b82e2 | 2764 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2765 | |
5c3b82e2 | 2766 | return 0; |
79e53945 JB |
2767 | } |
2768 | ||
5e84e1a4 ZW |
2769 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2770 | { | |
2771 | struct drm_device *dev = crtc->dev; | |
2772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2774 | int pipe = intel_crtc->pipe; | |
2775 | u32 reg, temp; | |
2776 | ||
2777 | /* enable normal train */ | |
2778 | reg = FDI_TX_CTL(pipe); | |
2779 | temp = I915_READ(reg); | |
61e499bf | 2780 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2781 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2782 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2783 | } else { |
2784 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2785 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2786 | } |
5e84e1a4 ZW |
2787 | I915_WRITE(reg, temp); |
2788 | ||
2789 | reg = FDI_RX_CTL(pipe); | |
2790 | temp = I915_READ(reg); | |
2791 | if (HAS_PCH_CPT(dev)) { | |
2792 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2793 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2794 | } else { | |
2795 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2796 | temp |= FDI_LINK_TRAIN_NONE; | |
2797 | } | |
2798 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2799 | ||
2800 | /* wait one idle pattern time */ | |
2801 | POSTING_READ(reg); | |
2802 | udelay(1000); | |
357555c0 JB |
2803 | |
2804 | /* IVB wants error correction enabled */ | |
2805 | if (IS_IVYBRIDGE(dev)) | |
2806 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2807 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2808 | } |
2809 | ||
1fbc0d78 | 2810 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2811 | { |
1fbc0d78 DV |
2812 | return crtc->base.enabled && crtc->active && |
2813 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2814 | } |
2815 | ||
01a415fd DV |
2816 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2817 | { | |
2818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2819 | struct intel_crtc *pipe_B_crtc = | |
2820 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2821 | struct intel_crtc *pipe_C_crtc = | |
2822 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2823 | uint32_t temp; | |
2824 | ||
1e833f40 DV |
2825 | /* |
2826 | * When everything is off disable fdi C so that we could enable fdi B | |
2827 | * with all lanes. Note that we don't care about enabled pipes without | |
2828 | * an enabled pch encoder. | |
2829 | */ | |
2830 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2831 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2832 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2833 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2834 | ||
2835 | temp = I915_READ(SOUTH_CHICKEN1); | |
2836 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2837 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2838 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2839 | } | |
2840 | } | |
2841 | ||
8db9d77b ZW |
2842 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2843 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2844 | { | |
2845 | struct drm_device *dev = crtc->dev; | |
2846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2848 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2849 | u32 reg, temp, tries; |
8db9d77b | 2850 | |
1c8562f6 | 2851 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2852 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2853 | |
e1a44743 AJ |
2854 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2855 | for train result */ | |
5eddb70b CW |
2856 | reg = FDI_RX_IMR(pipe); |
2857 | temp = I915_READ(reg); | |
e1a44743 AJ |
2858 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2859 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2860 | I915_WRITE(reg, temp); |
2861 | I915_READ(reg); | |
e1a44743 AJ |
2862 | udelay(150); |
2863 | ||
8db9d77b | 2864 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2865 | reg = FDI_TX_CTL(pipe); |
2866 | temp = I915_READ(reg); | |
627eb5a3 DV |
2867 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2868 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2869 | temp &= ~FDI_LINK_TRAIN_NONE; |
2870 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2871 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2872 | |
5eddb70b CW |
2873 | reg = FDI_RX_CTL(pipe); |
2874 | temp = I915_READ(reg); | |
8db9d77b ZW |
2875 | temp &= ~FDI_LINK_TRAIN_NONE; |
2876 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2877 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2878 | ||
2879 | POSTING_READ(reg); | |
8db9d77b ZW |
2880 | udelay(150); |
2881 | ||
5b2adf89 | 2882 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2883 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2884 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2885 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2886 | |
5eddb70b | 2887 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2888 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2889 | temp = I915_READ(reg); |
8db9d77b ZW |
2890 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2891 | ||
2892 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2893 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2894 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2895 | break; |
2896 | } | |
8db9d77b | 2897 | } |
e1a44743 | 2898 | if (tries == 5) |
5eddb70b | 2899 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2900 | |
2901 | /* Train 2 */ | |
5eddb70b CW |
2902 | reg = FDI_TX_CTL(pipe); |
2903 | temp = I915_READ(reg); | |
8db9d77b ZW |
2904 | temp &= ~FDI_LINK_TRAIN_NONE; |
2905 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2906 | I915_WRITE(reg, temp); |
8db9d77b | 2907 | |
5eddb70b CW |
2908 | reg = FDI_RX_CTL(pipe); |
2909 | temp = I915_READ(reg); | |
8db9d77b ZW |
2910 | temp &= ~FDI_LINK_TRAIN_NONE; |
2911 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2912 | I915_WRITE(reg, temp); |
8db9d77b | 2913 | |
5eddb70b CW |
2914 | POSTING_READ(reg); |
2915 | udelay(150); | |
8db9d77b | 2916 | |
5eddb70b | 2917 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2918 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2919 | temp = I915_READ(reg); |
8db9d77b ZW |
2920 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2921 | ||
2922 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2923 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2924 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2925 | break; | |
2926 | } | |
8db9d77b | 2927 | } |
e1a44743 | 2928 | if (tries == 5) |
5eddb70b | 2929 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2930 | |
2931 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2932 | |
8db9d77b ZW |
2933 | } |
2934 | ||
0206e353 | 2935 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2936 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2937 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2938 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2939 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2940 | }; | |
2941 | ||
2942 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2943 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2944 | { | |
2945 | struct drm_device *dev = crtc->dev; | |
2946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2948 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2949 | u32 reg, temp, i, retry; |
8db9d77b | 2950 | |
e1a44743 AJ |
2951 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2952 | for train result */ | |
5eddb70b CW |
2953 | reg = FDI_RX_IMR(pipe); |
2954 | temp = I915_READ(reg); | |
e1a44743 AJ |
2955 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2956 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2957 | I915_WRITE(reg, temp); |
2958 | ||
2959 | POSTING_READ(reg); | |
e1a44743 AJ |
2960 | udelay(150); |
2961 | ||
8db9d77b | 2962 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2963 | reg = FDI_TX_CTL(pipe); |
2964 | temp = I915_READ(reg); | |
627eb5a3 DV |
2965 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2966 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2967 | temp &= ~FDI_LINK_TRAIN_NONE; |
2968 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2969 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2970 | /* SNB-B */ | |
2971 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2972 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2973 | |
d74cf324 DV |
2974 | I915_WRITE(FDI_RX_MISC(pipe), |
2975 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2976 | ||
5eddb70b CW |
2977 | reg = FDI_RX_CTL(pipe); |
2978 | temp = I915_READ(reg); | |
8db9d77b ZW |
2979 | if (HAS_PCH_CPT(dev)) { |
2980 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2981 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2982 | } else { | |
2983 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2984 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2985 | } | |
5eddb70b CW |
2986 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2987 | ||
2988 | POSTING_READ(reg); | |
8db9d77b ZW |
2989 | udelay(150); |
2990 | ||
0206e353 | 2991 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2992 | reg = FDI_TX_CTL(pipe); |
2993 | temp = I915_READ(reg); | |
8db9d77b ZW |
2994 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2995 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2996 | I915_WRITE(reg, temp); |
2997 | ||
2998 | POSTING_READ(reg); | |
8db9d77b ZW |
2999 | udelay(500); |
3000 | ||
fa37d39e SP |
3001 | for (retry = 0; retry < 5; retry++) { |
3002 | reg = FDI_RX_IIR(pipe); | |
3003 | temp = I915_READ(reg); | |
3004 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3005 | if (temp & FDI_RX_BIT_LOCK) { | |
3006 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3007 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3008 | break; | |
3009 | } | |
3010 | udelay(50); | |
8db9d77b | 3011 | } |
fa37d39e SP |
3012 | if (retry < 5) |
3013 | break; | |
8db9d77b ZW |
3014 | } |
3015 | if (i == 4) | |
5eddb70b | 3016 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3017 | |
3018 | /* Train 2 */ | |
5eddb70b CW |
3019 | reg = FDI_TX_CTL(pipe); |
3020 | temp = I915_READ(reg); | |
8db9d77b ZW |
3021 | temp &= ~FDI_LINK_TRAIN_NONE; |
3022 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3023 | if (IS_GEN6(dev)) { | |
3024 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3025 | /* SNB-B */ | |
3026 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3027 | } | |
5eddb70b | 3028 | I915_WRITE(reg, temp); |
8db9d77b | 3029 | |
5eddb70b CW |
3030 | reg = FDI_RX_CTL(pipe); |
3031 | temp = I915_READ(reg); | |
8db9d77b ZW |
3032 | if (HAS_PCH_CPT(dev)) { |
3033 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3034 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3035 | } else { | |
3036 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3037 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3038 | } | |
5eddb70b CW |
3039 | I915_WRITE(reg, temp); |
3040 | ||
3041 | POSTING_READ(reg); | |
8db9d77b ZW |
3042 | udelay(150); |
3043 | ||
0206e353 | 3044 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3045 | reg = FDI_TX_CTL(pipe); |
3046 | temp = I915_READ(reg); | |
8db9d77b ZW |
3047 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3048 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3049 | I915_WRITE(reg, temp); |
3050 | ||
3051 | POSTING_READ(reg); | |
8db9d77b ZW |
3052 | udelay(500); |
3053 | ||
fa37d39e SP |
3054 | for (retry = 0; retry < 5; retry++) { |
3055 | reg = FDI_RX_IIR(pipe); | |
3056 | temp = I915_READ(reg); | |
3057 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3058 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3059 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3060 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3061 | break; | |
3062 | } | |
3063 | udelay(50); | |
8db9d77b | 3064 | } |
fa37d39e SP |
3065 | if (retry < 5) |
3066 | break; | |
8db9d77b ZW |
3067 | } |
3068 | if (i == 4) | |
5eddb70b | 3069 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3070 | |
3071 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3072 | } | |
3073 | ||
357555c0 JB |
3074 | /* Manual link training for Ivy Bridge A0 parts */ |
3075 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3076 | { | |
3077 | struct drm_device *dev = crtc->dev; | |
3078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3080 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3081 | u32 reg, temp, i, j; |
357555c0 JB |
3082 | |
3083 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3084 | for train result */ | |
3085 | reg = FDI_RX_IMR(pipe); | |
3086 | temp = I915_READ(reg); | |
3087 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3088 | temp &= ~FDI_RX_BIT_LOCK; | |
3089 | I915_WRITE(reg, temp); | |
3090 | ||
3091 | POSTING_READ(reg); | |
3092 | udelay(150); | |
3093 | ||
01a415fd DV |
3094 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3095 | I915_READ(FDI_RX_IIR(pipe))); | |
3096 | ||
139ccd3f JB |
3097 | /* Try each vswing and preemphasis setting twice before moving on */ |
3098 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3099 | /* disable first in case we need to retry */ | |
3100 | reg = FDI_TX_CTL(pipe); | |
3101 | temp = I915_READ(reg); | |
3102 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3103 | temp &= ~FDI_TX_ENABLE; | |
3104 | I915_WRITE(reg, temp); | |
357555c0 | 3105 | |
139ccd3f JB |
3106 | reg = FDI_RX_CTL(pipe); |
3107 | temp = I915_READ(reg); | |
3108 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3109 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3110 | temp &= ~FDI_RX_ENABLE; | |
3111 | I915_WRITE(reg, temp); | |
357555c0 | 3112 | |
139ccd3f | 3113 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3114 | reg = FDI_TX_CTL(pipe); |
3115 | temp = I915_READ(reg); | |
139ccd3f JB |
3116 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3117 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3118 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3119 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3120 | temp |= snb_b_fdi_train_param[j/2]; |
3121 | temp |= FDI_COMPOSITE_SYNC; | |
3122 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3123 | |
139ccd3f JB |
3124 | I915_WRITE(FDI_RX_MISC(pipe), |
3125 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3126 | |
139ccd3f | 3127 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3128 | temp = I915_READ(reg); |
139ccd3f JB |
3129 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3130 | temp |= FDI_COMPOSITE_SYNC; | |
3131 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3132 | |
139ccd3f JB |
3133 | POSTING_READ(reg); |
3134 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3135 | |
139ccd3f JB |
3136 | for (i = 0; i < 4; i++) { |
3137 | reg = FDI_RX_IIR(pipe); | |
3138 | temp = I915_READ(reg); | |
3139 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3140 | |
139ccd3f JB |
3141 | if (temp & FDI_RX_BIT_LOCK || |
3142 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3143 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3144 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3145 | i); | |
3146 | break; | |
3147 | } | |
3148 | udelay(1); /* should be 0.5us */ | |
3149 | } | |
3150 | if (i == 4) { | |
3151 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3152 | continue; | |
3153 | } | |
357555c0 | 3154 | |
139ccd3f | 3155 | /* Train 2 */ |
357555c0 JB |
3156 | reg = FDI_TX_CTL(pipe); |
3157 | temp = I915_READ(reg); | |
139ccd3f JB |
3158 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3159 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3160 | I915_WRITE(reg, temp); | |
3161 | ||
3162 | reg = FDI_RX_CTL(pipe); | |
3163 | temp = I915_READ(reg); | |
3164 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3165 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3166 | I915_WRITE(reg, temp); |
3167 | ||
3168 | POSTING_READ(reg); | |
139ccd3f | 3169 | udelay(2); /* should be 1.5us */ |
357555c0 | 3170 | |
139ccd3f JB |
3171 | for (i = 0; i < 4; i++) { |
3172 | reg = FDI_RX_IIR(pipe); | |
3173 | temp = I915_READ(reg); | |
3174 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3175 | |
139ccd3f JB |
3176 | if (temp & FDI_RX_SYMBOL_LOCK || |
3177 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3178 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3179 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3180 | i); | |
3181 | goto train_done; | |
3182 | } | |
3183 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3184 | } |
139ccd3f JB |
3185 | if (i == 4) |
3186 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3187 | } |
357555c0 | 3188 | |
139ccd3f | 3189 | train_done: |
357555c0 JB |
3190 | DRM_DEBUG_KMS("FDI train done.\n"); |
3191 | } | |
3192 | ||
88cefb6c | 3193 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3194 | { |
88cefb6c | 3195 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3196 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3197 | int pipe = intel_crtc->pipe; |
5eddb70b | 3198 | u32 reg, temp; |
79e53945 | 3199 | |
c64e311e | 3200 | |
c98e9dcf | 3201 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3202 | reg = FDI_RX_CTL(pipe); |
3203 | temp = I915_READ(reg); | |
627eb5a3 DV |
3204 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3205 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3206 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3207 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3208 | ||
3209 | POSTING_READ(reg); | |
c98e9dcf JB |
3210 | udelay(200); |
3211 | ||
3212 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3213 | temp = I915_READ(reg); |
3214 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3215 | ||
3216 | POSTING_READ(reg); | |
c98e9dcf JB |
3217 | udelay(200); |
3218 | ||
20749730 PZ |
3219 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3220 | reg = FDI_TX_CTL(pipe); | |
3221 | temp = I915_READ(reg); | |
3222 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3223 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3224 | |
20749730 PZ |
3225 | POSTING_READ(reg); |
3226 | udelay(100); | |
6be4a607 | 3227 | } |
0e23b99d JB |
3228 | } |
3229 | ||
88cefb6c DV |
3230 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3231 | { | |
3232 | struct drm_device *dev = intel_crtc->base.dev; | |
3233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3234 | int pipe = intel_crtc->pipe; | |
3235 | u32 reg, temp; | |
3236 | ||
3237 | /* Switch from PCDclk to Rawclk */ | |
3238 | reg = FDI_RX_CTL(pipe); | |
3239 | temp = I915_READ(reg); | |
3240 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3241 | ||
3242 | /* Disable CPU FDI TX PLL */ | |
3243 | reg = FDI_TX_CTL(pipe); | |
3244 | temp = I915_READ(reg); | |
3245 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3246 | ||
3247 | POSTING_READ(reg); | |
3248 | udelay(100); | |
3249 | ||
3250 | reg = FDI_RX_CTL(pipe); | |
3251 | temp = I915_READ(reg); | |
3252 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3253 | ||
3254 | /* Wait for the clocks to turn off. */ | |
3255 | POSTING_READ(reg); | |
3256 | udelay(100); | |
3257 | } | |
3258 | ||
0fc932b8 JB |
3259 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3260 | { | |
3261 | struct drm_device *dev = crtc->dev; | |
3262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3263 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3264 | int pipe = intel_crtc->pipe; | |
3265 | u32 reg, temp; | |
3266 | ||
3267 | /* disable CPU FDI tx and PCH FDI rx */ | |
3268 | reg = FDI_TX_CTL(pipe); | |
3269 | temp = I915_READ(reg); | |
3270 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3271 | POSTING_READ(reg); | |
3272 | ||
3273 | reg = FDI_RX_CTL(pipe); | |
3274 | temp = I915_READ(reg); | |
3275 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3276 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3277 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3278 | ||
3279 | POSTING_READ(reg); | |
3280 | udelay(100); | |
3281 | ||
3282 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3283 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3284 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3285 | |
3286 | /* still set train pattern 1 */ | |
3287 | reg = FDI_TX_CTL(pipe); | |
3288 | temp = I915_READ(reg); | |
3289 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3290 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3291 | I915_WRITE(reg, temp); | |
3292 | ||
3293 | reg = FDI_RX_CTL(pipe); | |
3294 | temp = I915_READ(reg); | |
3295 | if (HAS_PCH_CPT(dev)) { | |
3296 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3297 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3298 | } else { | |
3299 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3300 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3301 | } | |
3302 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3303 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3304 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3305 | I915_WRITE(reg, temp); |
3306 | ||
3307 | POSTING_READ(reg); | |
3308 | udelay(100); | |
3309 | } | |
3310 | ||
5dce5b93 CW |
3311 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3312 | { | |
3313 | struct intel_crtc *crtc; | |
3314 | ||
3315 | /* Note that we don't need to be called with mode_config.lock here | |
3316 | * as our list of CRTC objects is static for the lifetime of the | |
3317 | * device and so cannot disappear as we iterate. Similarly, we can | |
3318 | * happily treat the predicates as racy, atomic checks as userspace | |
3319 | * cannot claim and pin a new fb without at least acquring the | |
3320 | * struct_mutex and so serialising with us. | |
3321 | */ | |
d3fcc808 | 3322 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3323 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3324 | continue; | |
3325 | ||
3326 | if (crtc->unpin_work) | |
3327 | intel_wait_for_vblank(dev, crtc->pipe); | |
3328 | ||
3329 | return true; | |
3330 | } | |
3331 | ||
3332 | return false; | |
3333 | } | |
3334 | ||
46a55d30 | 3335 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3336 | { |
0f91128d | 3337 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3338 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3339 | |
f4510a27 | 3340 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3341 | return; |
3342 | ||
2c10d571 DV |
3343 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3344 | ||
eed6d67d DV |
3345 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3346 | !intel_crtc_has_pending_flip(crtc), | |
3347 | 60*HZ) == 0); | |
5bb61643 | 3348 | |
0f91128d | 3349 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3350 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3351 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3352 | } |
3353 | ||
e615efe4 ED |
3354 | /* Program iCLKIP clock to the desired frequency */ |
3355 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3356 | { | |
3357 | struct drm_device *dev = crtc->dev; | |
3358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3359 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3360 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3361 | u32 temp; | |
3362 | ||
09153000 DV |
3363 | mutex_lock(&dev_priv->dpio_lock); |
3364 | ||
e615efe4 ED |
3365 | /* It is necessary to ungate the pixclk gate prior to programming |
3366 | * the divisors, and gate it back when it is done. | |
3367 | */ | |
3368 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3369 | ||
3370 | /* Disable SSCCTL */ | |
3371 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3372 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3373 | SBI_SSCCTL_DISABLE, | |
3374 | SBI_ICLK); | |
e615efe4 ED |
3375 | |
3376 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3377 | if (clock == 20000) { |
e615efe4 ED |
3378 | auxdiv = 1; |
3379 | divsel = 0x41; | |
3380 | phaseinc = 0x20; | |
3381 | } else { | |
3382 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3383 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3384 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3385 | * convert the virtual clock precision to KHz here for higher |
3386 | * precision. | |
3387 | */ | |
3388 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3389 | u32 iclk_pi_range = 64; | |
3390 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3391 | ||
12d7ceed | 3392 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3393 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3394 | pi_value = desired_divisor % iclk_pi_range; | |
3395 | ||
3396 | auxdiv = 0; | |
3397 | divsel = msb_divisor_value - 2; | |
3398 | phaseinc = pi_value; | |
3399 | } | |
3400 | ||
3401 | /* This should not happen with any sane values */ | |
3402 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3403 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3404 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3405 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3406 | ||
3407 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3408 | clock, |
e615efe4 ED |
3409 | auxdiv, |
3410 | divsel, | |
3411 | phasedir, | |
3412 | phaseinc); | |
3413 | ||
3414 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3415 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3416 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3417 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3418 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3419 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3420 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3421 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3422 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3423 | |
3424 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3425 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3426 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3427 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3428 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3429 | |
3430 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3431 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3432 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3433 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3434 | |
3435 | /* Wait for initialization time */ | |
3436 | udelay(24); | |
3437 | ||
3438 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3439 | |
3440 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3441 | } |
3442 | ||
275f01b2 DV |
3443 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3444 | enum pipe pch_transcoder) | |
3445 | { | |
3446 | struct drm_device *dev = crtc->base.dev; | |
3447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3448 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3449 | ||
3450 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3451 | I915_READ(HTOTAL(cpu_transcoder))); | |
3452 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3453 | I915_READ(HBLANK(cpu_transcoder))); | |
3454 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3455 | I915_READ(HSYNC(cpu_transcoder))); | |
3456 | ||
3457 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3458 | I915_READ(VTOTAL(cpu_transcoder))); | |
3459 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3460 | I915_READ(VBLANK(cpu_transcoder))); | |
3461 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3462 | I915_READ(VSYNC(cpu_transcoder))); | |
3463 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3464 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3465 | } | |
3466 | ||
1fbc0d78 DV |
3467 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3468 | { | |
3469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3470 | uint32_t temp; | |
3471 | ||
3472 | temp = I915_READ(SOUTH_CHICKEN1); | |
3473 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3474 | return; | |
3475 | ||
3476 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3477 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3478 | ||
3479 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3480 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3481 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3482 | POSTING_READ(SOUTH_CHICKEN1); | |
3483 | } | |
3484 | ||
3485 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3486 | { | |
3487 | struct drm_device *dev = intel_crtc->base.dev; | |
3488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3489 | ||
3490 | switch (intel_crtc->pipe) { | |
3491 | case PIPE_A: | |
3492 | break; | |
3493 | case PIPE_B: | |
3494 | if (intel_crtc->config.fdi_lanes > 2) | |
3495 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3496 | else | |
3497 | cpt_enable_fdi_bc_bifurcation(dev); | |
3498 | ||
3499 | break; | |
3500 | case PIPE_C: | |
3501 | cpt_enable_fdi_bc_bifurcation(dev); | |
3502 | ||
3503 | break; | |
3504 | default: | |
3505 | BUG(); | |
3506 | } | |
3507 | } | |
3508 | ||
f67a559d JB |
3509 | /* |
3510 | * Enable PCH resources required for PCH ports: | |
3511 | * - PCH PLLs | |
3512 | * - FDI training & RX/TX | |
3513 | * - update transcoder timings | |
3514 | * - DP transcoding bits | |
3515 | * - transcoder | |
3516 | */ | |
3517 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3518 | { |
3519 | struct drm_device *dev = crtc->dev; | |
3520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3522 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3523 | u32 reg, temp; |
2c07245f | 3524 | |
ab9412ba | 3525 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3526 | |
1fbc0d78 DV |
3527 | if (IS_IVYBRIDGE(dev)) |
3528 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3529 | ||
cd986abb DV |
3530 | /* Write the TU size bits before fdi link training, so that error |
3531 | * detection works. */ | |
3532 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3533 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3534 | ||
c98e9dcf | 3535 | /* For PCH output, training FDI link */ |
674cf967 | 3536 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3537 | |
3ad8a208 DV |
3538 | /* We need to program the right clock selection before writing the pixel |
3539 | * mutliplier into the DPLL. */ | |
303b81e0 | 3540 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3541 | u32 sel; |
4b645f14 | 3542 | |
c98e9dcf | 3543 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3544 | temp |= TRANS_DPLL_ENABLE(pipe); |
3545 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3546 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3547 | temp |= sel; |
3548 | else | |
3549 | temp &= ~sel; | |
c98e9dcf | 3550 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3551 | } |
5eddb70b | 3552 | |
3ad8a208 DV |
3553 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3554 | * transcoder, and we actually should do this to not upset any PCH | |
3555 | * transcoder that already use the clock when we share it. | |
3556 | * | |
3557 | * Note that enable_shared_dpll tries to do the right thing, but | |
3558 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3559 | * the right LVDS enable sequence. */ | |
85b3894f | 3560 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3561 | |
d9b6cb56 JB |
3562 | /* set transcoder timing, panel must allow it */ |
3563 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3564 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3565 | |
303b81e0 | 3566 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3567 | |
c98e9dcf JB |
3568 | /* For PCH DP, enable TRANS_DP_CTL */ |
3569 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3570 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3571 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3572 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3573 | reg = TRANS_DP_CTL(pipe); |
3574 | temp = I915_READ(reg); | |
3575 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3576 | TRANS_DP_SYNC_MASK | |
3577 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3578 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3579 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3580 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3581 | |
3582 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3583 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3584 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3585 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3586 | |
3587 | switch (intel_trans_dp_port_sel(crtc)) { | |
3588 | case PCH_DP_B: | |
5eddb70b | 3589 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3590 | break; |
3591 | case PCH_DP_C: | |
5eddb70b | 3592 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3593 | break; |
3594 | case PCH_DP_D: | |
5eddb70b | 3595 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3596 | break; |
3597 | default: | |
e95d41e1 | 3598 | BUG(); |
32f9d658 | 3599 | } |
2c07245f | 3600 | |
5eddb70b | 3601 | I915_WRITE(reg, temp); |
6be4a607 | 3602 | } |
b52eb4dc | 3603 | |
b8a4f404 | 3604 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3605 | } |
3606 | ||
1507e5bd PZ |
3607 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3608 | { | |
3609 | struct drm_device *dev = crtc->dev; | |
3610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3611 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3612 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3613 | |
ab9412ba | 3614 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3615 | |
8c52b5e8 | 3616 | lpt_program_iclkip(crtc); |
1507e5bd | 3617 | |
0540e488 | 3618 | /* Set transcoder timing. */ |
275f01b2 | 3619 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3620 | |
937bb610 | 3621 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3622 | } |
3623 | ||
e2b78267 | 3624 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3625 | { |
e2b78267 | 3626 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3627 | |
3628 | if (pll == NULL) | |
3629 | return; | |
3630 | ||
3631 | if (pll->refcount == 0) { | |
46edb027 | 3632 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3633 | return; |
3634 | } | |
3635 | ||
f4a091c7 DV |
3636 | if (--pll->refcount == 0) { |
3637 | WARN_ON(pll->on); | |
3638 | WARN_ON(pll->active); | |
3639 | } | |
3640 | ||
a43f6e0f | 3641 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3642 | } |
3643 | ||
b89a1d39 | 3644 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3645 | { |
e2b78267 DV |
3646 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3647 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3648 | enum intel_dpll_id i; | |
ee7b9f93 | 3649 | |
ee7b9f93 | 3650 | if (pll) { |
46edb027 DV |
3651 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3652 | crtc->base.base.id, pll->name); | |
e2b78267 | 3653 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3654 | } |
3655 | ||
98b6bd99 DV |
3656 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3657 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3658 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3659 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3660 | |
46edb027 DV |
3661 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3662 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3663 | |
f2a69f44 DV |
3664 | WARN_ON(pll->refcount); |
3665 | ||
98b6bd99 DV |
3666 | goto found; |
3667 | } | |
3668 | ||
e72f9fbf DV |
3669 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3670 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3671 | |
3672 | /* Only want to check enabled timings first */ | |
3673 | if (pll->refcount == 0) | |
3674 | continue; | |
3675 | ||
b89a1d39 DV |
3676 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3677 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3678 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3679 | crtc->base.base.id, |
46edb027 | 3680 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3681 | |
3682 | goto found; | |
3683 | } | |
3684 | } | |
3685 | ||
3686 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3687 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3688 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3689 | if (pll->refcount == 0) { |
46edb027 DV |
3690 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3691 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3692 | goto found; |
3693 | } | |
3694 | } | |
3695 | ||
3696 | return NULL; | |
3697 | ||
3698 | found: | |
f2a69f44 DV |
3699 | if (pll->refcount == 0) |
3700 | pll->hw_state = crtc->config.dpll_hw_state; | |
3701 | ||
a43f6e0f | 3702 | crtc->config.shared_dpll = i; |
46edb027 DV |
3703 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3704 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3705 | |
cdbd2316 | 3706 | pll->refcount++; |
e04c7350 | 3707 | |
ee7b9f93 JB |
3708 | return pll; |
3709 | } | |
3710 | ||
a1520318 | 3711 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3712 | { |
3713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3714 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3715 | u32 temp; |
3716 | ||
3717 | temp = I915_READ(dslreg); | |
3718 | udelay(500); | |
3719 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3720 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3721 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3722 | } |
3723 | } | |
3724 | ||
b074cec8 JB |
3725 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3726 | { | |
3727 | struct drm_device *dev = crtc->base.dev; | |
3728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3729 | int pipe = crtc->pipe; | |
3730 | ||
fd4daa9c | 3731 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3732 | /* Force use of hard-coded filter coefficients |
3733 | * as some pre-programmed values are broken, | |
3734 | * e.g. x201. | |
3735 | */ | |
3736 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3737 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3738 | PF_PIPE_SEL_IVB(pipe)); | |
3739 | else | |
3740 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3741 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3742 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3743 | } |
3744 | } | |
3745 | ||
bb53d4ae VS |
3746 | static void intel_enable_planes(struct drm_crtc *crtc) |
3747 | { | |
3748 | struct drm_device *dev = crtc->dev; | |
3749 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3750 | struct drm_plane *plane; |
bb53d4ae VS |
3751 | struct intel_plane *intel_plane; |
3752 | ||
af2b653b MR |
3753 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3754 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3755 | if (intel_plane->pipe == pipe) |
3756 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3757 | } |
bb53d4ae VS |
3758 | } |
3759 | ||
3760 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3761 | { | |
3762 | struct drm_device *dev = crtc->dev; | |
3763 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3764 | struct drm_plane *plane; |
bb53d4ae VS |
3765 | struct intel_plane *intel_plane; |
3766 | ||
af2b653b MR |
3767 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3768 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3769 | if (intel_plane->pipe == pipe) |
3770 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3771 | } |
bb53d4ae VS |
3772 | } |
3773 | ||
20bc8673 | 3774 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3775 | { |
cea165c3 VS |
3776 | struct drm_device *dev = crtc->base.dev; |
3777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3778 | |
3779 | if (!crtc->config.ips_enabled) | |
3780 | return; | |
3781 | ||
cea165c3 VS |
3782 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3783 | intel_wait_for_vblank(dev, crtc->pipe); | |
3784 | ||
d77e4531 | 3785 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3786 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3787 | mutex_lock(&dev_priv->rps.hw_lock); |
3788 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3789 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3790 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3791 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3792 | * mailbox." Moreover, the mailbox may return a bogus state, |
3793 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3794 | */ |
3795 | } else { | |
3796 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3797 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3798 | * is essentially intel_wait_for_vblank. If we don't have this | |
3799 | * and don't wait for vblanks until the end of crtc_enable, then | |
3800 | * the HW state readout code will complain that the expected | |
3801 | * IPS_CTL value is not the one we read. */ | |
3802 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3803 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3804 | } | |
d77e4531 PZ |
3805 | } |
3806 | ||
20bc8673 | 3807 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3808 | { |
3809 | struct drm_device *dev = crtc->base.dev; | |
3810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3811 | ||
3812 | if (!crtc->config.ips_enabled) | |
3813 | return; | |
3814 | ||
3815 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3816 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3817 | mutex_lock(&dev_priv->rps.hw_lock); |
3818 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3819 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3820 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3821 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3822 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3823 | } else { |
2a114cc1 | 3824 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3825 | POSTING_READ(IPS_CTL); |
3826 | } | |
d77e4531 PZ |
3827 | |
3828 | /* We need to wait for a vblank before we can disable the plane. */ | |
3829 | intel_wait_for_vblank(dev, crtc->pipe); | |
3830 | } | |
3831 | ||
3832 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3833 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3834 | { | |
3835 | struct drm_device *dev = crtc->dev; | |
3836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3838 | enum pipe pipe = intel_crtc->pipe; | |
3839 | int palreg = PALETTE(pipe); | |
3840 | int i; | |
3841 | bool reenable_ips = false; | |
3842 | ||
3843 | /* The clocks have to be on to load the palette. */ | |
3844 | if (!crtc->enabled || !intel_crtc->active) | |
3845 | return; | |
3846 | ||
3847 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3848 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3849 | assert_dsi_pll_enabled(dev_priv); | |
3850 | else | |
3851 | assert_pll_enabled(dev_priv, pipe); | |
3852 | } | |
3853 | ||
3854 | /* use legacy palette for Ironlake */ | |
3855 | if (HAS_PCH_SPLIT(dev)) | |
3856 | palreg = LGC_PALETTE(pipe); | |
3857 | ||
3858 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3859 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3860 | */ | |
41e6fc4c | 3861 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3862 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3863 | GAMMA_MODE_MODE_SPLIT)) { | |
3864 | hsw_disable_ips(intel_crtc); | |
3865 | reenable_ips = true; | |
3866 | } | |
3867 | ||
3868 | for (i = 0; i < 256; i++) { | |
3869 | I915_WRITE(palreg + 4 * i, | |
3870 | (intel_crtc->lut_r[i] << 16) | | |
3871 | (intel_crtc->lut_g[i] << 8) | | |
3872 | intel_crtc->lut_b[i]); | |
3873 | } | |
3874 | ||
3875 | if (reenable_ips) | |
3876 | hsw_enable_ips(intel_crtc); | |
3877 | } | |
3878 | ||
d3eedb1a VS |
3879 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3880 | { | |
3881 | if (!enable && intel_crtc->overlay) { | |
3882 | struct drm_device *dev = intel_crtc->base.dev; | |
3883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3884 | ||
3885 | mutex_lock(&dev->struct_mutex); | |
3886 | dev_priv->mm.interruptible = false; | |
3887 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3888 | dev_priv->mm.interruptible = true; | |
3889 | mutex_unlock(&dev->struct_mutex); | |
3890 | } | |
3891 | ||
3892 | /* Let userspace switch the overlay on again. In most cases userspace | |
3893 | * has to recompute where to put it anyway. | |
3894 | */ | |
3895 | } | |
3896 | ||
d3eedb1a | 3897 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3898 | { |
3899 | struct drm_device *dev = crtc->dev; | |
3900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3902 | int pipe = intel_crtc->pipe; | |
3903 | int plane = intel_crtc->plane; | |
3904 | ||
f98551ae VS |
3905 | drm_vblank_on(dev, pipe); |
3906 | ||
a5c4d7bc VS |
3907 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3908 | intel_enable_planes(crtc); | |
3909 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 3910 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3911 | |
3912 | hsw_enable_ips(intel_crtc); | |
3913 | ||
3914 | mutex_lock(&dev->struct_mutex); | |
3915 | intel_update_fbc(dev); | |
3916 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
3917 | |
3918 | /* | |
3919 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3920 | * to compute the mask of flip planes precisely. For the time being | |
3921 | * consider this a flip from a NULL plane. | |
3922 | */ | |
3923 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
3924 | } |
3925 | ||
d3eedb1a | 3926 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3927 | { |
3928 | struct drm_device *dev = crtc->dev; | |
3929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3931 | int pipe = intel_crtc->pipe; | |
3932 | int plane = intel_crtc->plane; | |
3933 | ||
3934 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3935 | |
3936 | if (dev_priv->fbc.plane == plane) | |
3937 | intel_disable_fbc(dev); | |
3938 | ||
3939 | hsw_disable_ips(intel_crtc); | |
3940 | ||
d3eedb1a | 3941 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3942 | intel_crtc_update_cursor(crtc, false); |
3943 | intel_disable_planes(crtc); | |
3944 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
f98551ae | 3945 | |
f99d7069 DV |
3946 | /* |
3947 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3948 | * to compute the mask of flip planes precisely. For the time being | |
3949 | * consider this a flip to a NULL plane. | |
3950 | */ | |
3951 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
3952 | ||
f98551ae | 3953 | drm_vblank_off(dev, pipe); |
a5c4d7bc VS |
3954 | } |
3955 | ||
f67a559d JB |
3956 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3957 | { | |
3958 | struct drm_device *dev = crtc->dev; | |
3959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3961 | struct intel_encoder *encoder; |
f67a559d | 3962 | int pipe = intel_crtc->pipe; |
29407aab | 3963 | enum plane plane = intel_crtc->plane; |
f67a559d | 3964 | |
08a48469 DV |
3965 | WARN_ON(!crtc->enabled); |
3966 | ||
f67a559d JB |
3967 | if (intel_crtc->active) |
3968 | return; | |
3969 | ||
b14b1055 DV |
3970 | if (intel_crtc->config.has_pch_encoder) |
3971 | intel_prepare_shared_dpll(intel_crtc); | |
3972 | ||
29407aab DV |
3973 | if (intel_crtc->config.has_dp_encoder) |
3974 | intel_dp_set_m_n(intel_crtc); | |
3975 | ||
3976 | intel_set_pipe_timings(intel_crtc); | |
3977 | ||
3978 | if (intel_crtc->config.has_pch_encoder) { | |
3979 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
3980 | &intel_crtc->config.fdi_m_n); | |
3981 | } | |
3982 | ||
3983 | ironlake_set_pipeconf(crtc); | |
3984 | ||
3985 | /* Set up the display plane register */ | |
3986 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
3987 | POSTING_READ(DSPCNTR(plane)); | |
3988 | ||
3989 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
3990 | crtc->x, crtc->y); | |
3991 | ||
f67a559d | 3992 | intel_crtc->active = true; |
8664281b PZ |
3993 | |
3994 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3995 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3996 | ||
f6736a1a | 3997 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3998 | if (encoder->pre_enable) |
3999 | encoder->pre_enable(encoder); | |
f67a559d | 4000 | |
5bfe2ac0 | 4001 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4002 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4003 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4004 | * enabling. */ | |
88cefb6c | 4005 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4006 | } else { |
4007 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4008 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4009 | } | |
f67a559d | 4010 | |
b074cec8 | 4011 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4012 | |
9c54c0dd JB |
4013 | /* |
4014 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4015 | * clocks enabled | |
4016 | */ | |
4017 | intel_crtc_load_lut(crtc); | |
4018 | ||
f37fcc2a | 4019 | intel_update_watermarks(crtc); |
e1fdc473 | 4020 | intel_enable_pipe(intel_crtc); |
f67a559d | 4021 | |
5bfe2ac0 | 4022 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4023 | ironlake_pch_enable(crtc); |
c98e9dcf | 4024 | |
fa5c73b1 DV |
4025 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4026 | encoder->enable(encoder); | |
61b77ddd DV |
4027 | |
4028 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4029 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4030 | |
d3eedb1a | 4031 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4032 | } |
4033 | ||
42db64ef PZ |
4034 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4035 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4036 | { | |
f5adf94e | 4037 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4038 | } |
4039 | ||
e4916946 PZ |
4040 | /* |
4041 | * This implements the workaround described in the "notes" section of the mode | |
4042 | * set sequence documentation. When going from no pipes or single pipe to | |
4043 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4044 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4045 | */ | |
4046 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4047 | { | |
4048 | struct drm_device *dev = crtc->base.dev; | |
4049 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4050 | ||
4051 | /* We want to get the other_active_crtc only if there's only 1 other | |
4052 | * active crtc. */ | |
d3fcc808 | 4053 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4054 | if (!crtc_it->active || crtc_it == crtc) |
4055 | continue; | |
4056 | ||
4057 | if (other_active_crtc) | |
4058 | return; | |
4059 | ||
4060 | other_active_crtc = crtc_it; | |
4061 | } | |
4062 | if (!other_active_crtc) | |
4063 | return; | |
4064 | ||
4065 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4066 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4067 | } | |
4068 | ||
4f771f10 PZ |
4069 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4070 | { | |
4071 | struct drm_device *dev = crtc->dev; | |
4072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4074 | struct intel_encoder *encoder; | |
4075 | int pipe = intel_crtc->pipe; | |
229fca97 | 4076 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4077 | |
4078 | WARN_ON(!crtc->enabled); | |
4079 | ||
4080 | if (intel_crtc->active) | |
4081 | return; | |
4082 | ||
229fca97 DV |
4083 | if (intel_crtc->config.has_dp_encoder) |
4084 | intel_dp_set_m_n(intel_crtc); | |
4085 | ||
4086 | intel_set_pipe_timings(intel_crtc); | |
4087 | ||
4088 | if (intel_crtc->config.has_pch_encoder) { | |
4089 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4090 | &intel_crtc->config.fdi_m_n); | |
4091 | } | |
4092 | ||
4093 | haswell_set_pipeconf(crtc); | |
4094 | ||
4095 | intel_set_pipe_csc(crtc); | |
4096 | ||
4097 | /* Set up the display plane register */ | |
4098 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4099 | POSTING_READ(DSPCNTR(plane)); | |
4100 | ||
4101 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4102 | crtc->x, crtc->y); | |
4103 | ||
4f771f10 | 4104 | intel_crtc->active = true; |
8664281b PZ |
4105 | |
4106 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4107 | if (intel_crtc->config.has_pch_encoder) | |
4108 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4109 | ||
5bfe2ac0 | 4110 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4111 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4112 | |
4113 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4114 | if (encoder->pre_enable) | |
4115 | encoder->pre_enable(encoder); | |
4116 | ||
1f544388 | 4117 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4118 | |
b074cec8 | 4119 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4120 | |
4121 | /* | |
4122 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4123 | * clocks enabled | |
4124 | */ | |
4125 | intel_crtc_load_lut(crtc); | |
4126 | ||
1f544388 | 4127 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4128 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4129 | |
f37fcc2a | 4130 | intel_update_watermarks(crtc); |
e1fdc473 | 4131 | intel_enable_pipe(intel_crtc); |
42db64ef | 4132 | |
5bfe2ac0 | 4133 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4134 | lpt_pch_enable(crtc); |
4f771f10 | 4135 | |
8807e55b | 4136 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4137 | encoder->enable(encoder); |
8807e55b JN |
4138 | intel_opregion_notify_encoder(encoder, true); |
4139 | } | |
4f771f10 | 4140 | |
e4916946 PZ |
4141 | /* If we change the relative order between pipe/planes enabling, we need |
4142 | * to change the workaround. */ | |
4143 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4144 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4145 | } |
4146 | ||
3f8dce3a DV |
4147 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4148 | { | |
4149 | struct drm_device *dev = crtc->base.dev; | |
4150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4151 | int pipe = crtc->pipe; | |
4152 | ||
4153 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4154 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4155 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4156 | I915_WRITE(PF_CTL(pipe), 0); |
4157 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4158 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4159 | } | |
4160 | } | |
4161 | ||
6be4a607 JB |
4162 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4163 | { | |
4164 | struct drm_device *dev = crtc->dev; | |
4165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4167 | struct intel_encoder *encoder; |
6be4a607 | 4168 | int pipe = intel_crtc->pipe; |
5eddb70b | 4169 | u32 reg, temp; |
b52eb4dc | 4170 | |
f7abfe8b CW |
4171 | if (!intel_crtc->active) |
4172 | return; | |
4173 | ||
d3eedb1a | 4174 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4175 | |
ea9d758d DV |
4176 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4177 | encoder->disable(encoder); | |
4178 | ||
d925c59a DV |
4179 | if (intel_crtc->config.has_pch_encoder) |
4180 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4181 | ||
b24e7179 | 4182 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4183 | |
3f8dce3a | 4184 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4185 | |
bf49ec8c DV |
4186 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4187 | if (encoder->post_disable) | |
4188 | encoder->post_disable(encoder); | |
2c07245f | 4189 | |
d925c59a DV |
4190 | if (intel_crtc->config.has_pch_encoder) { |
4191 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4192 | |
d925c59a DV |
4193 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4194 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4195 | |
d925c59a DV |
4196 | if (HAS_PCH_CPT(dev)) { |
4197 | /* disable TRANS_DP_CTL */ | |
4198 | reg = TRANS_DP_CTL(pipe); | |
4199 | temp = I915_READ(reg); | |
4200 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4201 | TRANS_DP_PORT_SEL_MASK); | |
4202 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4203 | I915_WRITE(reg, temp); | |
4204 | ||
4205 | /* disable DPLL_SEL */ | |
4206 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4207 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4208 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4209 | } |
e3421a18 | 4210 | |
d925c59a | 4211 | /* disable PCH DPLL */ |
e72f9fbf | 4212 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4213 | |
d925c59a DV |
4214 | ironlake_fdi_pll_disable(intel_crtc); |
4215 | } | |
6b383a7f | 4216 | |
f7abfe8b | 4217 | intel_crtc->active = false; |
46ba614c | 4218 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4219 | |
4220 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4221 | intel_update_fbc(dev); |
d1ebd816 | 4222 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4223 | } |
1b3c7a47 | 4224 | |
4f771f10 | 4225 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4226 | { |
4f771f10 PZ |
4227 | struct drm_device *dev = crtc->dev; |
4228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4230 | struct intel_encoder *encoder; |
4231 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4232 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4233 | |
4f771f10 PZ |
4234 | if (!intel_crtc->active) |
4235 | return; | |
4236 | ||
d3eedb1a | 4237 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4238 | |
8807e55b JN |
4239 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4240 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4241 | encoder->disable(encoder); |
8807e55b | 4242 | } |
4f771f10 | 4243 | |
8664281b PZ |
4244 | if (intel_crtc->config.has_pch_encoder) |
4245 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4246 | intel_disable_pipe(dev_priv, pipe); |
4247 | ||
ad80a810 | 4248 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4249 | |
3f8dce3a | 4250 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4251 | |
1f544388 | 4252 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4253 | |
4254 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4255 | if (encoder->post_disable) | |
4256 | encoder->post_disable(encoder); | |
4257 | ||
88adfff1 | 4258 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4259 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4260 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4261 | intel_ddi_fdi_disable(crtc); |
83616634 | 4262 | } |
4f771f10 PZ |
4263 | |
4264 | intel_crtc->active = false; | |
46ba614c | 4265 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4266 | |
4267 | mutex_lock(&dev->struct_mutex); | |
4268 | intel_update_fbc(dev); | |
4269 | mutex_unlock(&dev->struct_mutex); | |
4270 | } | |
4271 | ||
ee7b9f93 JB |
4272 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4273 | { | |
4274 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4275 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4276 | } |
4277 | ||
6441ab5f PZ |
4278 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4279 | { | |
4280 | intel_ddi_put_crtc_pll(crtc); | |
4281 | } | |
4282 | ||
2dd24552 JB |
4283 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4284 | { | |
4285 | struct drm_device *dev = crtc->base.dev; | |
4286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4287 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4288 | ||
328d8e82 | 4289 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4290 | return; |
4291 | ||
2dd24552 | 4292 | /* |
c0b03411 DV |
4293 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4294 | * according to register description and PRM. | |
2dd24552 | 4295 | */ |
c0b03411 DV |
4296 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4297 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4298 | |
b074cec8 JB |
4299 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4300 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4301 | |
4302 | /* Border color in case we don't scale up to the full screen. Black by | |
4303 | * default, change to something else for debugging. */ | |
4304 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4305 | } |
4306 | ||
77d22dca ID |
4307 | #define for_each_power_domain(domain, mask) \ |
4308 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4309 | if ((1 << (domain)) & (mask)) | |
4310 | ||
319be8ae ID |
4311 | enum intel_display_power_domain |
4312 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4313 | { | |
4314 | struct drm_device *dev = intel_encoder->base.dev; | |
4315 | struct intel_digital_port *intel_dig_port; | |
4316 | ||
4317 | switch (intel_encoder->type) { | |
4318 | case INTEL_OUTPUT_UNKNOWN: | |
4319 | /* Only DDI platforms should ever use this output type */ | |
4320 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4321 | case INTEL_OUTPUT_DISPLAYPORT: | |
4322 | case INTEL_OUTPUT_HDMI: | |
4323 | case INTEL_OUTPUT_EDP: | |
4324 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4325 | switch (intel_dig_port->port) { | |
4326 | case PORT_A: | |
4327 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4328 | case PORT_B: | |
4329 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4330 | case PORT_C: | |
4331 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4332 | case PORT_D: | |
4333 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4334 | default: | |
4335 | WARN_ON_ONCE(1); | |
4336 | return POWER_DOMAIN_PORT_OTHER; | |
4337 | } | |
4338 | case INTEL_OUTPUT_ANALOG: | |
4339 | return POWER_DOMAIN_PORT_CRT; | |
4340 | case INTEL_OUTPUT_DSI: | |
4341 | return POWER_DOMAIN_PORT_DSI; | |
4342 | default: | |
4343 | return POWER_DOMAIN_PORT_OTHER; | |
4344 | } | |
4345 | } | |
4346 | ||
4347 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4348 | { |
319be8ae ID |
4349 | struct drm_device *dev = crtc->dev; |
4350 | struct intel_encoder *intel_encoder; | |
4351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4352 | enum pipe pipe = intel_crtc->pipe; | |
4353 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4354 | unsigned long mask; |
4355 | enum transcoder transcoder; | |
4356 | ||
4357 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4358 | ||
4359 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4360 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4361 | if (pfit_enabled) | |
4362 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4363 | ||
319be8ae ID |
4364 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4365 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4366 | ||
77d22dca ID |
4367 | return mask; |
4368 | } | |
4369 | ||
4370 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4371 | bool enable) | |
4372 | { | |
4373 | if (dev_priv->power_domains.init_power_on == enable) | |
4374 | return; | |
4375 | ||
4376 | if (enable) | |
4377 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4378 | else | |
4379 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4380 | ||
4381 | dev_priv->power_domains.init_power_on = enable; | |
4382 | } | |
4383 | ||
4384 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4385 | { | |
4386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4387 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4388 | struct intel_crtc *crtc; | |
4389 | ||
4390 | /* | |
4391 | * First get all needed power domains, then put all unneeded, to avoid | |
4392 | * any unnecessary toggling of the power wells. | |
4393 | */ | |
d3fcc808 | 4394 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4395 | enum intel_display_power_domain domain; |
4396 | ||
4397 | if (!crtc->base.enabled) | |
4398 | continue; | |
4399 | ||
319be8ae | 4400 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4401 | |
4402 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4403 | intel_display_power_get(dev_priv, domain); | |
4404 | } | |
4405 | ||
d3fcc808 | 4406 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4407 | enum intel_display_power_domain domain; |
4408 | ||
4409 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4410 | intel_display_power_put(dev_priv, domain); | |
4411 | ||
4412 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4413 | } | |
4414 | ||
4415 | intel_display_set_init_power(dev_priv, false); | |
4416 | } | |
4417 | ||
dfcab17e | 4418 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4419 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4420 | { |
586f49dc | 4421 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4422 | |
586f49dc JB |
4423 | /* Obtain SKU information */ |
4424 | mutex_lock(&dev_priv->dpio_lock); | |
4425 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4426 | CCK_FUSE_HPLL_FREQ_MASK; | |
4427 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4428 | |
dfcab17e | 4429 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4430 | } |
4431 | ||
f8bf63fd VS |
4432 | static void vlv_update_cdclk(struct drm_device *dev) |
4433 | { | |
4434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4435 | ||
4436 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
4437 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", | |
4438 | dev_priv->vlv_cdclk_freq); | |
4439 | ||
4440 | /* | |
4441 | * Program the gmbus_freq based on the cdclk frequency. | |
4442 | * BSpec erroneously claims we should aim for 4MHz, but | |
4443 | * in fact 1MHz is the correct frequency. | |
4444 | */ | |
4445 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); | |
4446 | } | |
4447 | ||
30a970c6 JB |
4448 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4449 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4450 | { | |
4451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4452 | u32 val, cmd; | |
4453 | ||
d197b7d3 | 4454 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4455 | |
dfcab17e | 4456 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4457 | cmd = 2; |
dfcab17e | 4458 | else if (cdclk == 266667) |
30a970c6 JB |
4459 | cmd = 1; |
4460 | else | |
4461 | cmd = 0; | |
4462 | ||
4463 | mutex_lock(&dev_priv->rps.hw_lock); | |
4464 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4465 | val &= ~DSPFREQGUAR_MASK; | |
4466 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4467 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4468 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4469 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4470 | 50)) { | |
4471 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4472 | } | |
4473 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4474 | ||
dfcab17e | 4475 | if (cdclk == 400000) { |
30a970c6 JB |
4476 | u32 divider, vco; |
4477 | ||
4478 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4479 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4480 | |
4481 | mutex_lock(&dev_priv->dpio_lock); | |
4482 | /* adjust cdclk divider */ | |
4483 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4484 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4485 | val |= divider; |
4486 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4487 | |
4488 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4489 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4490 | 50)) | |
4491 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4492 | mutex_unlock(&dev_priv->dpio_lock); |
4493 | } | |
4494 | ||
4495 | mutex_lock(&dev_priv->dpio_lock); | |
4496 | /* adjust self-refresh exit latency value */ | |
4497 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4498 | val &= ~0x7f; | |
4499 | ||
4500 | /* | |
4501 | * For high bandwidth configs, we set a higher latency in the bunit | |
4502 | * so that the core display fetch happens in time to avoid underruns. | |
4503 | */ | |
dfcab17e | 4504 | if (cdclk == 400000) |
30a970c6 JB |
4505 | val |= 4500 / 250; /* 4.5 usec */ |
4506 | else | |
4507 | val |= 3000 / 250; /* 3.0 usec */ | |
4508 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4509 | mutex_unlock(&dev_priv->dpio_lock); | |
4510 | ||
f8bf63fd | 4511 | vlv_update_cdclk(dev); |
30a970c6 JB |
4512 | } |
4513 | ||
30a970c6 JB |
4514 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4515 | int max_pixclk) | |
4516 | { | |
29dc7ef3 VS |
4517 | int vco = valleyview_get_vco(dev_priv); |
4518 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; | |
4519 | ||
30a970c6 JB |
4520 | /* |
4521 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4522 | * 200MHz | |
4523 | * 267MHz | |
29dc7ef3 | 4524 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4525 | * 400MHz |
4526 | * So we check to see whether we're above 90% of the lower bin and | |
4527 | * adjust if needed. | |
e37c67a1 VS |
4528 | * |
4529 | * We seem to get an unstable or solid color picture at 200MHz. | |
4530 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4531 | * are off. | |
30a970c6 | 4532 | */ |
29dc7ef3 | 4533 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4534 | return 400000; |
4535 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4536 | return freq_320; |
e37c67a1 | 4537 | else if (max_pixclk > 0) |
dfcab17e | 4538 | return 266667; |
e37c67a1 VS |
4539 | else |
4540 | return 200000; | |
30a970c6 JB |
4541 | } |
4542 | ||
2f2d7aa1 VS |
4543 | /* compute the max pixel clock for new configuration */ |
4544 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4545 | { |
4546 | struct drm_device *dev = dev_priv->dev; | |
4547 | struct intel_crtc *intel_crtc; | |
4548 | int max_pixclk = 0; | |
4549 | ||
d3fcc808 | 4550 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4551 | if (intel_crtc->new_enabled) |
30a970c6 | 4552 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4553 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4554 | } |
4555 | ||
4556 | return max_pixclk; | |
4557 | } | |
4558 | ||
4559 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4560 | unsigned *prepare_pipes) |
30a970c6 JB |
4561 | { |
4562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4563 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4564 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4565 | |
d60c4473 ID |
4566 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4567 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4568 | return; |
4569 | ||
2f2d7aa1 | 4570 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4571 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4572 | if (intel_crtc->base.enabled) |
4573 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4574 | } | |
4575 | ||
4576 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4577 | { | |
4578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4579 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4580 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4581 | ||
d60c4473 | 4582 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4583 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4584 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4585 | } |
4586 | ||
89b667f8 JB |
4587 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4588 | { | |
4589 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4590 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4592 | struct intel_encoder *encoder; | |
4593 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4594 | int plane = intel_crtc->plane; |
23538ef1 | 4595 | bool is_dsi; |
5b18e57c | 4596 | u32 dspcntr; |
89b667f8 JB |
4597 | |
4598 | WARN_ON(!crtc->enabled); | |
4599 | ||
4600 | if (intel_crtc->active) | |
4601 | return; | |
4602 | ||
8525a235 SK |
4603 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4604 | ||
4605 | if (!is_dsi && !IS_CHERRYVIEW(dev)) | |
4606 | vlv_prepare_pll(intel_crtc); | |
bdd4b6a6 | 4607 | |
5b18e57c DV |
4608 | /* Set up the display plane register */ |
4609 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4610 | ||
4611 | if (intel_crtc->config.has_dp_encoder) | |
4612 | intel_dp_set_m_n(intel_crtc); | |
4613 | ||
4614 | intel_set_pipe_timings(intel_crtc); | |
4615 | ||
4616 | /* pipesrc and dspsize control the size that is scaled from, | |
4617 | * which should always be the user's requested size. | |
4618 | */ | |
4619 | I915_WRITE(DSPSIZE(plane), | |
4620 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4621 | (intel_crtc->config.pipe_src_w - 1)); | |
4622 | I915_WRITE(DSPPOS(plane), 0); | |
4623 | ||
4624 | i9xx_set_pipeconf(intel_crtc); | |
4625 | ||
4626 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4627 | POSTING_READ(DSPCNTR(plane)); | |
4628 | ||
4629 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4630 | crtc->x, crtc->y); | |
4631 | ||
89b667f8 | 4632 | intel_crtc->active = true; |
89b667f8 | 4633 | |
4a3436e8 VS |
4634 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4635 | ||
89b667f8 JB |
4636 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4637 | if (encoder->pre_pll_enable) | |
4638 | encoder->pre_pll_enable(encoder); | |
4639 | ||
9d556c99 CML |
4640 | if (!is_dsi) { |
4641 | if (IS_CHERRYVIEW(dev)) | |
4642 | chv_enable_pll(intel_crtc); | |
4643 | else | |
4644 | vlv_enable_pll(intel_crtc); | |
4645 | } | |
89b667f8 JB |
4646 | |
4647 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4648 | if (encoder->pre_enable) | |
4649 | encoder->pre_enable(encoder); | |
4650 | ||
2dd24552 JB |
4651 | i9xx_pfit_enable(intel_crtc); |
4652 | ||
63cbb074 VS |
4653 | intel_crtc_load_lut(crtc); |
4654 | ||
f37fcc2a | 4655 | intel_update_watermarks(crtc); |
e1fdc473 | 4656 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4657 | |
5004945f JN |
4658 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4659 | encoder->enable(encoder); | |
9ab0460b VS |
4660 | |
4661 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4662 | |
56b80e1f VS |
4663 | /* Underruns don't raise interrupts, so check manually. */ |
4664 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4665 | } |
4666 | ||
f13c2ef3 DV |
4667 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4668 | { | |
4669 | struct drm_device *dev = crtc->base.dev; | |
4670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4671 | ||
4672 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4673 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4674 | } | |
4675 | ||
0b8765c6 | 4676 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4677 | { |
4678 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4679 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4680 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4681 | struct intel_encoder *encoder; |
79e53945 | 4682 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4683 | int plane = intel_crtc->plane; |
4684 | u32 dspcntr; | |
79e53945 | 4685 | |
08a48469 DV |
4686 | WARN_ON(!crtc->enabled); |
4687 | ||
f7abfe8b CW |
4688 | if (intel_crtc->active) |
4689 | return; | |
4690 | ||
f13c2ef3 DV |
4691 | i9xx_set_pll_dividers(intel_crtc); |
4692 | ||
5b18e57c DV |
4693 | /* Set up the display plane register */ |
4694 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4695 | ||
4696 | if (pipe == 0) | |
4697 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4698 | else | |
4699 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4700 | ||
4701 | if (intel_crtc->config.has_dp_encoder) | |
4702 | intel_dp_set_m_n(intel_crtc); | |
4703 | ||
4704 | intel_set_pipe_timings(intel_crtc); | |
4705 | ||
4706 | /* pipesrc and dspsize control the size that is scaled from, | |
4707 | * which should always be the user's requested size. | |
4708 | */ | |
4709 | I915_WRITE(DSPSIZE(plane), | |
4710 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4711 | (intel_crtc->config.pipe_src_w - 1)); | |
4712 | I915_WRITE(DSPPOS(plane), 0); | |
4713 | ||
4714 | i9xx_set_pipeconf(intel_crtc); | |
4715 | ||
4716 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4717 | POSTING_READ(DSPCNTR(plane)); | |
4718 | ||
4719 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4720 | crtc->x, crtc->y); | |
4721 | ||
f7abfe8b | 4722 | intel_crtc->active = true; |
6b383a7f | 4723 | |
4a3436e8 VS |
4724 | if (!IS_GEN2(dev)) |
4725 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4726 | ||
9d6d9f19 MK |
4727 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4728 | if (encoder->pre_enable) | |
4729 | encoder->pre_enable(encoder); | |
4730 | ||
f6736a1a DV |
4731 | i9xx_enable_pll(intel_crtc); |
4732 | ||
2dd24552 JB |
4733 | i9xx_pfit_enable(intel_crtc); |
4734 | ||
63cbb074 VS |
4735 | intel_crtc_load_lut(crtc); |
4736 | ||
f37fcc2a | 4737 | intel_update_watermarks(crtc); |
e1fdc473 | 4738 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4739 | |
fa5c73b1 DV |
4740 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4741 | encoder->enable(encoder); | |
9ab0460b VS |
4742 | |
4743 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4744 | |
4a3436e8 VS |
4745 | /* |
4746 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4747 | * So don't enable underrun reporting before at least some planes | |
4748 | * are enabled. | |
4749 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4750 | * but leave the pipe running. | |
4751 | */ | |
4752 | if (IS_GEN2(dev)) | |
4753 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4754 | ||
56b80e1f VS |
4755 | /* Underruns don't raise interrupts, so check manually. */ |
4756 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4757 | } |
79e53945 | 4758 | |
87476d63 DV |
4759 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4760 | { | |
4761 | struct drm_device *dev = crtc->base.dev; | |
4762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4763 | |
328d8e82 DV |
4764 | if (!crtc->config.gmch_pfit.control) |
4765 | return; | |
87476d63 | 4766 | |
328d8e82 | 4767 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4768 | |
328d8e82 DV |
4769 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4770 | I915_READ(PFIT_CONTROL)); | |
4771 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4772 | } |
4773 | ||
0b8765c6 JB |
4774 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4775 | { | |
4776 | struct drm_device *dev = crtc->dev; | |
4777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4778 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4779 | struct intel_encoder *encoder; |
0b8765c6 | 4780 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4781 | |
f7abfe8b CW |
4782 | if (!intel_crtc->active) |
4783 | return; | |
4784 | ||
4a3436e8 VS |
4785 | /* |
4786 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4787 | * So diasble underrun reporting before all the planes get disabled. | |
4788 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4789 | * but leave the pipe running. | |
4790 | */ | |
4791 | if (IS_GEN2(dev)) | |
4792 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4793 | ||
564ed191 ID |
4794 | /* |
4795 | * Vblank time updates from the shadow to live plane control register | |
4796 | * are blocked if the memory self-refresh mode is active at that | |
4797 | * moment. So to make sure the plane gets truly disabled, disable | |
4798 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4799 | * will be checked/applied by the HW only at the next frame start | |
4800 | * event which is after the vblank start event, so we need to have a | |
4801 | * wait-for-vblank between disabling the plane and the pipe. | |
4802 | */ | |
4803 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
4804 | intel_crtc_disable_planes(crtc); |
4805 | ||
ea9d758d DV |
4806 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4807 | encoder->disable(encoder); | |
4808 | ||
6304cd91 VS |
4809 | /* |
4810 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4811 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
4812 | * We also need to wait on all gmch platforms because of the |
4813 | * self-refresh mode constraint explained above. | |
6304cd91 | 4814 | */ |
564ed191 | 4815 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 4816 | |
b24e7179 | 4817 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4818 | |
87476d63 | 4819 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4820 | |
89b667f8 JB |
4821 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4822 | if (encoder->post_disable) | |
4823 | encoder->post_disable(encoder); | |
4824 | ||
076ed3b2 CML |
4825 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4826 | if (IS_CHERRYVIEW(dev)) | |
4827 | chv_disable_pll(dev_priv, pipe); | |
4828 | else if (IS_VALLEYVIEW(dev)) | |
4829 | vlv_disable_pll(dev_priv, pipe); | |
4830 | else | |
4831 | i9xx_disable_pll(dev_priv, pipe); | |
4832 | } | |
0b8765c6 | 4833 | |
4a3436e8 VS |
4834 | if (!IS_GEN2(dev)) |
4835 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4836 | ||
f7abfe8b | 4837 | intel_crtc->active = false; |
46ba614c | 4838 | intel_update_watermarks(crtc); |
f37fcc2a | 4839 | |
efa9624e | 4840 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4841 | intel_update_fbc(dev); |
efa9624e | 4842 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4843 | } |
4844 | ||
ee7b9f93 JB |
4845 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4846 | { | |
4847 | } | |
4848 | ||
976f8a20 DV |
4849 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4850 | bool enabled) | |
2c07245f ZW |
4851 | { |
4852 | struct drm_device *dev = crtc->dev; | |
4853 | struct drm_i915_master_private *master_priv; | |
4854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4855 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4856 | |
4857 | if (!dev->primary->master) | |
4858 | return; | |
4859 | ||
4860 | master_priv = dev->primary->master->driver_priv; | |
4861 | if (!master_priv->sarea_priv) | |
4862 | return; | |
4863 | ||
79e53945 JB |
4864 | switch (pipe) { |
4865 | case 0: | |
4866 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4867 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4868 | break; | |
4869 | case 1: | |
4870 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4871 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4872 | break; | |
4873 | default: | |
9db4a9c7 | 4874 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4875 | break; |
4876 | } | |
79e53945 JB |
4877 | } |
4878 | ||
976f8a20 DV |
4879 | /** |
4880 | * Sets the power management mode of the pipe and plane. | |
4881 | */ | |
4882 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4883 | { | |
4884 | struct drm_device *dev = crtc->dev; | |
4885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
976f8a20 | 4887 | struct intel_encoder *intel_encoder; |
0e572fe7 DV |
4888 | enum intel_display_power_domain domain; |
4889 | unsigned long domains; | |
976f8a20 DV |
4890 | bool enable = false; |
4891 | ||
4892 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4893 | enable |= intel_encoder->connectors_active; | |
4894 | ||
0e572fe7 DV |
4895 | if (enable) { |
4896 | if (!intel_crtc->active) { | |
4897 | /* | |
4898 | * FIXME: DDI plls and relevant code isn't converted | |
4899 | * yet, so do runtime PM for DPMS only for all other | |
4900 | * platforms for now. | |
4901 | */ | |
4902 | if (!HAS_DDI(dev)) { | |
4903 | domains = get_crtc_power_domains(crtc); | |
4904 | for_each_power_domain(domain, domains) | |
4905 | intel_display_power_get(dev_priv, domain); | |
4906 | intel_crtc->enabled_power_domains = domains; | |
4907 | } | |
4908 | ||
4909 | dev_priv->display.crtc_enable(crtc); | |
4910 | } | |
4911 | } else { | |
4912 | if (intel_crtc->active) { | |
4913 | dev_priv->display.crtc_disable(crtc); | |
4914 | ||
4915 | if (!HAS_DDI(dev)) { | |
4916 | domains = intel_crtc->enabled_power_domains; | |
4917 | for_each_power_domain(domain, domains) | |
4918 | intel_display_power_put(dev_priv, domain); | |
4919 | intel_crtc->enabled_power_domains = 0; | |
4920 | } | |
4921 | } | |
4922 | } | |
976f8a20 DV |
4923 | |
4924 | intel_crtc_update_sarea(crtc, enable); | |
4925 | } | |
4926 | ||
cdd59983 CW |
4927 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4928 | { | |
cdd59983 | 4929 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4930 | struct drm_connector *connector; |
ee7b9f93 | 4931 | struct drm_i915_private *dev_priv = dev->dev_private; |
a071fa00 DV |
4932 | struct drm_i915_gem_object *old_obj; |
4933 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
cdd59983 | 4934 | |
976f8a20 DV |
4935 | /* crtc should still be enabled when we disable it. */ |
4936 | WARN_ON(!crtc->enabled); | |
4937 | ||
4938 | dev_priv->display.crtc_disable(crtc); | |
4939 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4940 | dev_priv->display.off(crtc); |
4941 | ||
931872fc | 4942 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
a071fa00 DV |
4943 | assert_cursor_disabled(dev_priv, pipe); |
4944 | assert_pipe_disabled(dev->dev_private, pipe); | |
cdd59983 | 4945 | |
f4510a27 | 4946 | if (crtc->primary->fb) { |
a071fa00 | 4947 | old_obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
cdd59983 | 4948 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
4949 | intel_unpin_fb_obj(old_obj); |
4950 | i915_gem_track_fb(old_obj, NULL, | |
4951 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 4952 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4953 | crtc->primary->fb = NULL; |
976f8a20 DV |
4954 | } |
4955 | ||
4956 | /* Update computed state. */ | |
4957 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4958 | if (!connector->encoder || !connector->encoder->crtc) | |
4959 | continue; | |
4960 | ||
4961 | if (connector->encoder->crtc != crtc) | |
4962 | continue; | |
4963 | ||
4964 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4965 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4966 | } |
4967 | } | |
4968 | ||
ea5b213a | 4969 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4970 | { |
4ef69c7a | 4971 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4972 | |
ea5b213a CW |
4973 | drm_encoder_cleanup(encoder); |
4974 | kfree(intel_encoder); | |
7e7d76c3 JB |
4975 | } |
4976 | ||
9237329d | 4977 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4978 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4979 | * state of the entire output pipe. */ | |
9237329d | 4980 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4981 | { |
5ab432ef DV |
4982 | if (mode == DRM_MODE_DPMS_ON) { |
4983 | encoder->connectors_active = true; | |
4984 | ||
b2cabb0e | 4985 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4986 | } else { |
4987 | encoder->connectors_active = false; | |
4988 | ||
b2cabb0e | 4989 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4990 | } |
79e53945 JB |
4991 | } |
4992 | ||
0a91ca29 DV |
4993 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4994 | * internal consistency). */ | |
b980514c | 4995 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4996 | { |
0a91ca29 DV |
4997 | if (connector->get_hw_state(connector)) { |
4998 | struct intel_encoder *encoder = connector->encoder; | |
4999 | struct drm_crtc *crtc; | |
5000 | bool encoder_enabled; | |
5001 | enum pipe pipe; | |
5002 | ||
5003 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5004 | connector->base.base.id, | |
c23cc417 | 5005 | connector->base.name); |
0a91ca29 DV |
5006 | |
5007 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
5008 | "wrong connector dpms state\n"); | |
5009 | WARN(connector->base.encoder != &encoder->base, | |
5010 | "active connector not linked to encoder\n"); | |
5011 | WARN(!encoder->connectors_active, | |
5012 | "encoder->connectors_active not set\n"); | |
5013 | ||
5014 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5015 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5016 | if (WARN_ON(!encoder->base.crtc)) | |
5017 | return; | |
5018 | ||
5019 | crtc = encoder->base.crtc; | |
5020 | ||
5021 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
5022 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5023 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5024 | "encoder active on the wrong pipe\n"); | |
5025 | } | |
79e53945 JB |
5026 | } |
5027 | ||
5ab432ef DV |
5028 | /* Even simpler default implementation, if there's really no special case to |
5029 | * consider. */ | |
5030 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5031 | { |
5ab432ef DV |
5032 | /* All the simple cases only support two dpms states. */ |
5033 | if (mode != DRM_MODE_DPMS_ON) | |
5034 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5035 | |
5ab432ef DV |
5036 | if (mode == connector->dpms) |
5037 | return; | |
5038 | ||
5039 | connector->dpms = mode; | |
5040 | ||
5041 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5042 | if (connector->encoder) |
5043 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5044 | |
b980514c | 5045 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5046 | } |
5047 | ||
f0947c37 DV |
5048 | /* Simple connector->get_hw_state implementation for encoders that support only |
5049 | * one connector and no cloning and hence the encoder state determines the state | |
5050 | * of the connector. */ | |
5051 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5052 | { |
24929352 | 5053 | enum pipe pipe = 0; |
f0947c37 | 5054 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5055 | |
f0947c37 | 5056 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5057 | } |
5058 | ||
1857e1da DV |
5059 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5060 | struct intel_crtc_config *pipe_config) | |
5061 | { | |
5062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5063 | struct intel_crtc *pipe_B_crtc = | |
5064 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5065 | ||
5066 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5067 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5068 | if (pipe_config->fdi_lanes > 4) { | |
5069 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5070 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5071 | return false; | |
5072 | } | |
5073 | ||
bafb6553 | 5074 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5075 | if (pipe_config->fdi_lanes > 2) { |
5076 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5077 | pipe_config->fdi_lanes); | |
5078 | return false; | |
5079 | } else { | |
5080 | return true; | |
5081 | } | |
5082 | } | |
5083 | ||
5084 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5085 | return true; | |
5086 | ||
5087 | /* Ivybridge 3 pipe is really complicated */ | |
5088 | switch (pipe) { | |
5089 | case PIPE_A: | |
5090 | return true; | |
5091 | case PIPE_B: | |
5092 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5093 | pipe_config->fdi_lanes > 2) { | |
5094 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5095 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5096 | return false; | |
5097 | } | |
5098 | return true; | |
5099 | case PIPE_C: | |
1e833f40 | 5100 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5101 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5102 | if (pipe_config->fdi_lanes > 2) { | |
5103 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5104 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5105 | return false; | |
5106 | } | |
5107 | } else { | |
5108 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5109 | return false; | |
5110 | } | |
5111 | return true; | |
5112 | default: | |
5113 | BUG(); | |
5114 | } | |
5115 | } | |
5116 | ||
e29c22c0 DV |
5117 | #define RETRY 1 |
5118 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5119 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5120 | { |
1857e1da | 5121 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5122 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5123 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5124 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5125 | |
e29c22c0 | 5126 | retry: |
877d48d5 DV |
5127 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5128 | * each output octet as 10 bits. The actual frequency | |
5129 | * is stored as a divider into a 100MHz clock, and the | |
5130 | * mode pixel clock is stored in units of 1KHz. | |
5131 | * Hence the bw of each lane in terms of the mode signal | |
5132 | * is: | |
5133 | */ | |
5134 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5135 | ||
241bfc38 | 5136 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5137 | |
2bd89a07 | 5138 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5139 | pipe_config->pipe_bpp); |
5140 | ||
5141 | pipe_config->fdi_lanes = lane; | |
5142 | ||
2bd89a07 | 5143 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5144 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5145 | |
e29c22c0 DV |
5146 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5147 | intel_crtc->pipe, pipe_config); | |
5148 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5149 | pipe_config->pipe_bpp -= 2*3; | |
5150 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5151 | pipe_config->pipe_bpp); | |
5152 | needs_recompute = true; | |
5153 | pipe_config->bw_constrained = true; | |
5154 | ||
5155 | goto retry; | |
5156 | } | |
5157 | ||
5158 | if (needs_recompute) | |
5159 | return RETRY; | |
5160 | ||
5161 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5162 | } |
5163 | ||
42db64ef PZ |
5164 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5165 | struct intel_crtc_config *pipe_config) | |
5166 | { | |
d330a953 | 5167 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5168 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5169 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5170 | } |
5171 | ||
a43f6e0f | 5172 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5173 | struct intel_crtc_config *pipe_config) |
79e53945 | 5174 | { |
a43f6e0f | 5175 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5176 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5177 | |
ad3a4479 | 5178 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5179 | if (INTEL_INFO(dev)->gen < 4) { |
5180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5181 | int clock_limit = | |
5182 | dev_priv->display.get_display_clock_speed(dev); | |
5183 | ||
5184 | /* | |
5185 | * Enable pixel doubling when the dot clock | |
5186 | * is > 90% of the (display) core speed. | |
5187 | * | |
b397c96b VS |
5188 | * GDG double wide on either pipe, |
5189 | * otherwise pipe A only. | |
cf532bb2 | 5190 | */ |
b397c96b | 5191 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5192 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5193 | clock_limit *= 2; |
cf532bb2 | 5194 | pipe_config->double_wide = true; |
ad3a4479 VS |
5195 | } |
5196 | ||
241bfc38 | 5197 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5198 | return -EINVAL; |
2c07245f | 5199 | } |
89749350 | 5200 | |
1d1d0e27 VS |
5201 | /* |
5202 | * Pipe horizontal size must be even in: | |
5203 | * - DVO ganged mode | |
5204 | * - LVDS dual channel mode | |
5205 | * - Double wide pipe | |
5206 | */ | |
5207 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5208 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5209 | pipe_config->pipe_src_w &= ~1; | |
5210 | ||
8693a824 DL |
5211 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5212 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5213 | */ |
5214 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5215 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5216 | return -EINVAL; |
44f46b42 | 5217 | |
bd080ee5 | 5218 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5219 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5220 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5221 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5222 | * for lvds. */ | |
5223 | pipe_config->pipe_bpp = 8*3; | |
5224 | } | |
5225 | ||
f5adf94e | 5226 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5227 | hsw_compute_ips_config(crtc, pipe_config); |
5228 | ||
5229 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5230 | * clock survives for now. */ | |
5231 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5232 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5233 | |
877d48d5 | 5234 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5235 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5236 | |
e29c22c0 | 5237 | return 0; |
79e53945 JB |
5238 | } |
5239 | ||
25eb05fc JB |
5240 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5241 | { | |
d197b7d3 VS |
5242 | struct drm_i915_private *dev_priv = dev->dev_private; |
5243 | int vco = valleyview_get_vco(dev_priv); | |
5244 | u32 val; | |
5245 | int divider; | |
5246 | ||
5247 | mutex_lock(&dev_priv->dpio_lock); | |
5248 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5249 | mutex_unlock(&dev_priv->dpio_lock); | |
5250 | ||
5251 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5252 | ||
7d007f40 VS |
5253 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5254 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5255 | "cdclk change in progress\n"); | |
5256 | ||
d197b7d3 | 5257 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
25eb05fc JB |
5258 | } |
5259 | ||
e70236a8 JB |
5260 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5261 | { | |
5262 | return 400000; | |
5263 | } | |
79e53945 | 5264 | |
e70236a8 | 5265 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5266 | { |
e70236a8 JB |
5267 | return 333000; |
5268 | } | |
79e53945 | 5269 | |
e70236a8 JB |
5270 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5271 | { | |
5272 | return 200000; | |
5273 | } | |
79e53945 | 5274 | |
257a7ffc DV |
5275 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5276 | { | |
5277 | u16 gcfgc = 0; | |
5278 | ||
5279 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5280 | ||
5281 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5282 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5283 | return 267000; | |
5284 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5285 | return 333000; | |
5286 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5287 | return 444000; | |
5288 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5289 | return 200000; | |
5290 | default: | |
5291 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5292 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5293 | return 133000; | |
5294 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5295 | return 167000; | |
5296 | } | |
5297 | } | |
5298 | ||
e70236a8 JB |
5299 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5300 | { | |
5301 | u16 gcfgc = 0; | |
79e53945 | 5302 | |
e70236a8 JB |
5303 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5304 | ||
5305 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5306 | return 133000; | |
5307 | else { | |
5308 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5309 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5310 | return 333000; | |
5311 | default: | |
5312 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5313 | return 190000; | |
79e53945 | 5314 | } |
e70236a8 JB |
5315 | } |
5316 | } | |
5317 | ||
5318 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5319 | { | |
5320 | return 266000; | |
5321 | } | |
5322 | ||
5323 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5324 | { | |
5325 | u16 hpllcc = 0; | |
5326 | /* Assume that the hardware is in the high speed state. This | |
5327 | * should be the default. | |
5328 | */ | |
5329 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5330 | case GC_CLOCK_133_200: | |
5331 | case GC_CLOCK_100_200: | |
5332 | return 200000; | |
5333 | case GC_CLOCK_166_250: | |
5334 | return 250000; | |
5335 | case GC_CLOCK_100_133: | |
79e53945 | 5336 | return 133000; |
e70236a8 | 5337 | } |
79e53945 | 5338 | |
e70236a8 JB |
5339 | /* Shouldn't happen */ |
5340 | return 0; | |
5341 | } | |
79e53945 | 5342 | |
e70236a8 JB |
5343 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5344 | { | |
5345 | return 133000; | |
79e53945 JB |
5346 | } |
5347 | ||
2c07245f | 5348 | static void |
a65851af | 5349 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5350 | { |
a65851af VS |
5351 | while (*num > DATA_LINK_M_N_MASK || |
5352 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5353 | *num >>= 1; |
5354 | *den >>= 1; | |
5355 | } | |
5356 | } | |
5357 | ||
a65851af VS |
5358 | static void compute_m_n(unsigned int m, unsigned int n, |
5359 | uint32_t *ret_m, uint32_t *ret_n) | |
5360 | { | |
5361 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5362 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5363 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5364 | } | |
5365 | ||
e69d0bc1 DV |
5366 | void |
5367 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5368 | int pixel_clock, int link_clock, | |
5369 | struct intel_link_m_n *m_n) | |
2c07245f | 5370 | { |
e69d0bc1 | 5371 | m_n->tu = 64; |
a65851af VS |
5372 | |
5373 | compute_m_n(bits_per_pixel * pixel_clock, | |
5374 | link_clock * nlanes * 8, | |
5375 | &m_n->gmch_m, &m_n->gmch_n); | |
5376 | ||
5377 | compute_m_n(pixel_clock, link_clock, | |
5378 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5379 | } |
5380 | ||
a7615030 CW |
5381 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5382 | { | |
d330a953 JN |
5383 | if (i915.panel_use_ssc >= 0) |
5384 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5385 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5386 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5387 | } |
5388 | ||
c65d77d8 JB |
5389 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5390 | { | |
5391 | struct drm_device *dev = crtc->dev; | |
5392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5393 | int refclk; | |
5394 | ||
a0c4da24 | 5395 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5396 | refclk = 100000; |
a0c4da24 | 5397 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5398 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5399 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5400 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5401 | } else if (!IS_GEN2(dev)) { |
5402 | refclk = 96000; | |
5403 | } else { | |
5404 | refclk = 48000; | |
5405 | } | |
5406 | ||
5407 | return refclk; | |
5408 | } | |
5409 | ||
7429e9d4 | 5410 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5411 | { |
7df00d7a | 5412 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5413 | } |
f47709a9 | 5414 | |
7429e9d4 DV |
5415 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5416 | { | |
5417 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5418 | } |
5419 | ||
f47709a9 | 5420 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5421 | intel_clock_t *reduced_clock) |
5422 | { | |
f47709a9 | 5423 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5424 | u32 fp, fp2 = 0; |
5425 | ||
5426 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5427 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5428 | if (reduced_clock) |
7429e9d4 | 5429 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5430 | } else { |
7429e9d4 | 5431 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5432 | if (reduced_clock) |
7429e9d4 | 5433 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5434 | } |
5435 | ||
8bcc2795 | 5436 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5437 | |
f47709a9 DV |
5438 | crtc->lowfreq_avail = false; |
5439 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5440 | reduced_clock && i915.powersave) { |
8bcc2795 | 5441 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5442 | crtc->lowfreq_avail = true; |
a7516a05 | 5443 | } else { |
8bcc2795 | 5444 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5445 | } |
5446 | } | |
5447 | ||
5e69f97f CML |
5448 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5449 | pipe) | |
89b667f8 JB |
5450 | { |
5451 | u32 reg_val; | |
5452 | ||
5453 | /* | |
5454 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5455 | * and set it to a reasonable value instead. | |
5456 | */ | |
ab3c759a | 5457 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5458 | reg_val &= 0xffffff00; |
5459 | reg_val |= 0x00000030; | |
ab3c759a | 5460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5461 | |
ab3c759a | 5462 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5463 | reg_val &= 0x8cffffff; |
5464 | reg_val = 0x8c000000; | |
ab3c759a | 5465 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5466 | |
ab3c759a | 5467 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5468 | reg_val &= 0xffffff00; |
ab3c759a | 5469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5470 | |
ab3c759a | 5471 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5472 | reg_val &= 0x00ffffff; |
5473 | reg_val |= 0xb0000000; | |
ab3c759a | 5474 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5475 | } |
5476 | ||
b551842d DV |
5477 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5478 | struct intel_link_m_n *m_n) | |
5479 | { | |
5480 | struct drm_device *dev = crtc->base.dev; | |
5481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5482 | int pipe = crtc->pipe; | |
5483 | ||
e3b95f1e DV |
5484 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5485 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5486 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5487 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5488 | } |
5489 | ||
5490 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5491 | struct intel_link_m_n *m_n) | |
5492 | { | |
5493 | struct drm_device *dev = crtc->base.dev; | |
5494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5495 | int pipe = crtc->pipe; | |
5496 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5497 | ||
5498 | if (INTEL_INFO(dev)->gen >= 5) { | |
5499 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5500 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5501 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5502 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5503 | } else { | |
e3b95f1e DV |
5504 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5505 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5506 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5507 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5508 | } |
5509 | } | |
5510 | ||
03afc4a2 DV |
5511 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5512 | { | |
5513 | if (crtc->config.has_pch_encoder) | |
5514 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5515 | else | |
5516 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5517 | } | |
5518 | ||
f47709a9 | 5519 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5520 | { |
5521 | u32 dpll, dpll_md; | |
5522 | ||
5523 | /* | |
5524 | * Enable DPIO clock input. We should never disable the reference | |
5525 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5526 | * on it. | |
5527 | */ | |
5528 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5529 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5530 | /* We should never disable this, set it here for state tracking */ | |
5531 | if (crtc->pipe == PIPE_B) | |
5532 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5533 | dpll |= DPLL_VCO_ENABLE; | |
5534 | crtc->config.dpll_hw_state.dpll = dpll; | |
5535 | ||
5536 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5537 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5538 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5539 | } | |
5540 | ||
5541 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5542 | { |
f47709a9 | 5543 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5544 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5545 | int pipe = crtc->pipe; |
bdd4b6a6 | 5546 | u32 mdiv; |
a0c4da24 | 5547 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5548 | u32 coreclk, reg_val; |
a0c4da24 | 5549 | |
09153000 DV |
5550 | mutex_lock(&dev_priv->dpio_lock); |
5551 | ||
f47709a9 DV |
5552 | bestn = crtc->config.dpll.n; |
5553 | bestm1 = crtc->config.dpll.m1; | |
5554 | bestm2 = crtc->config.dpll.m2; | |
5555 | bestp1 = crtc->config.dpll.p1; | |
5556 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5557 | |
89b667f8 JB |
5558 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5559 | ||
5560 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5561 | if (pipe == PIPE_B) |
5e69f97f | 5562 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5563 | |
5564 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5565 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5566 | |
5567 | /* Disable target IRef on PLL */ | |
ab3c759a | 5568 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5569 | reg_val &= 0x00ffffff; |
ab3c759a | 5570 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5571 | |
5572 | /* Disable fast lock */ | |
ab3c759a | 5573 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5574 | |
5575 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5576 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5577 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5578 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5579 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5580 | |
5581 | /* | |
5582 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5583 | * but we don't support that). | |
5584 | * Note: don't use the DAC post divider as it seems unstable. | |
5585 | */ | |
5586 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5587 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5588 | |
a0c4da24 | 5589 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5590 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5591 | |
89b667f8 | 5592 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5593 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5594 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5595 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5596 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5597 | 0x009f0003); |
89b667f8 | 5598 | else |
ab3c759a | 5599 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5600 | 0x00d0000f); |
5601 | ||
5602 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5603 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5604 | /* Use SSC source */ | |
bdd4b6a6 | 5605 | if (pipe == PIPE_A) |
ab3c759a | 5606 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5607 | 0x0df40000); |
5608 | else | |
ab3c759a | 5609 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5610 | 0x0df70000); |
5611 | } else { /* HDMI or VGA */ | |
5612 | /* Use bend source */ | |
bdd4b6a6 | 5613 | if (pipe == PIPE_A) |
ab3c759a | 5614 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5615 | 0x0df70000); |
5616 | else | |
ab3c759a | 5617 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5618 | 0x0df40000); |
5619 | } | |
a0c4da24 | 5620 | |
ab3c759a | 5621 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5622 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5623 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5624 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5625 | coreclk |= 0x01000000; | |
ab3c759a | 5626 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5627 | |
ab3c759a | 5628 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5629 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5630 | } |
5631 | ||
9d556c99 CML |
5632 | static void chv_update_pll(struct intel_crtc *crtc) |
5633 | { | |
5634 | struct drm_device *dev = crtc->base.dev; | |
5635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5636 | int pipe = crtc->pipe; | |
5637 | int dpll_reg = DPLL(crtc->pipe); | |
5638 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5639 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5640 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5641 | int refclk; | |
5642 | ||
a11b0703 VS |
5643 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5644 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5645 | DPLL_VCO_ENABLE; | |
5646 | if (pipe != PIPE_A) | |
5647 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5648 | ||
5649 | crtc->config.dpll_hw_state.dpll_md = | |
5650 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5651 | |
5652 | bestn = crtc->config.dpll.n; | |
5653 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5654 | bestm1 = crtc->config.dpll.m1; | |
5655 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5656 | bestp1 = crtc->config.dpll.p1; | |
5657 | bestp2 = crtc->config.dpll.p2; | |
5658 | ||
5659 | /* | |
5660 | * Enable Refclk and SSC | |
5661 | */ | |
a11b0703 VS |
5662 | I915_WRITE(dpll_reg, |
5663 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5664 | ||
5665 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5666 | |
9d556c99 CML |
5667 | /* p1 and p2 divider */ |
5668 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5669 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5670 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5671 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5672 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5673 | ||
5674 | /* Feedback post-divider - m2 */ | |
5675 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5676 | ||
5677 | /* Feedback refclk divider - n and m1 */ | |
5678 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5679 | DPIO_CHV_M1_DIV_BY_2 | | |
5680 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5681 | ||
5682 | /* M2 fraction division */ | |
5683 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5684 | ||
5685 | /* M2 fraction division enable */ | |
5686 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5687 | DPIO_CHV_FRAC_DIV_EN | | |
5688 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5689 | ||
5690 | /* Loop filter */ | |
5691 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5692 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5693 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5694 | if (refclk == 100000) | |
5695 | intcoeff = 11; | |
5696 | else if (refclk == 38400) | |
5697 | intcoeff = 10; | |
5698 | else | |
5699 | intcoeff = 9; | |
5700 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5701 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5702 | ||
5703 | /* AFC Recal */ | |
5704 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5705 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5706 | DPIO_AFC_RECAL); | |
5707 | ||
5708 | mutex_unlock(&dev_priv->dpio_lock); | |
5709 | } | |
5710 | ||
f47709a9 DV |
5711 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5712 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5713 | int num_connectors) |
5714 | { | |
f47709a9 | 5715 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5716 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5717 | u32 dpll; |
5718 | bool is_sdvo; | |
f47709a9 | 5719 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5720 | |
f47709a9 | 5721 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5722 | |
f47709a9 DV |
5723 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5724 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5725 | |
5726 | dpll = DPLL_VGA_MODE_DIS; | |
5727 | ||
f47709a9 | 5728 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5729 | dpll |= DPLLB_MODE_LVDS; |
5730 | else | |
5731 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5732 | |
ef1b460d | 5733 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5734 | dpll |= (crtc->config.pixel_multiplier - 1) |
5735 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5736 | } |
198a037f DV |
5737 | |
5738 | if (is_sdvo) | |
4a33e48d | 5739 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5740 | |
f47709a9 | 5741 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5742 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5743 | |
5744 | /* compute bitmask from p1 value */ | |
5745 | if (IS_PINEVIEW(dev)) | |
5746 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5747 | else { | |
5748 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5749 | if (IS_G4X(dev) && reduced_clock) | |
5750 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5751 | } | |
5752 | switch (clock->p2) { | |
5753 | case 5: | |
5754 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5755 | break; | |
5756 | case 7: | |
5757 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5758 | break; | |
5759 | case 10: | |
5760 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5761 | break; | |
5762 | case 14: | |
5763 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5764 | break; | |
5765 | } | |
5766 | if (INTEL_INFO(dev)->gen >= 4) | |
5767 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5768 | ||
09ede541 | 5769 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5770 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5771 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5772 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5773 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5774 | else | |
5775 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5776 | ||
5777 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5778 | crtc->config.dpll_hw_state.dpll = dpll; |
5779 | ||
eb1cbe48 | 5780 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5781 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5782 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5783 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5784 | } |
5785 | } | |
5786 | ||
f47709a9 | 5787 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5788 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5789 | int num_connectors) |
5790 | { | |
f47709a9 | 5791 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5792 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5793 | u32 dpll; |
f47709a9 | 5794 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5795 | |
f47709a9 | 5796 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5797 | |
eb1cbe48 DV |
5798 | dpll = DPLL_VGA_MODE_DIS; |
5799 | ||
f47709a9 | 5800 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5801 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5802 | } else { | |
5803 | if (clock->p1 == 2) | |
5804 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5805 | else | |
5806 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5807 | if (clock->p2 == 4) | |
5808 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5809 | } | |
5810 | ||
4a33e48d DV |
5811 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5812 | dpll |= DPLL_DVO_2X_MODE; | |
5813 | ||
f47709a9 | 5814 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5815 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5816 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5817 | else | |
5818 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5819 | ||
5820 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5821 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5822 | } |
5823 | ||
8a654f3b | 5824 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5825 | { |
5826 | struct drm_device *dev = intel_crtc->base.dev; | |
5827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5828 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5829 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5830 | struct drm_display_mode *adjusted_mode = |
5831 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5832 | uint32_t crtc_vtotal, crtc_vblank_end; |
5833 | int vsyncshift = 0; | |
4d8a62ea DV |
5834 | |
5835 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5836 | * the hw state checker will get angry at the mismatch. */ | |
5837 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5838 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5839 | |
609aeaca | 5840 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5841 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5842 | crtc_vtotal -= 1; |
5843 | crtc_vblank_end -= 1; | |
609aeaca VS |
5844 | |
5845 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5846 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5847 | else | |
5848 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5849 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5850 | if (vsyncshift < 0) |
5851 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5852 | } |
5853 | ||
5854 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5855 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5856 | |
fe2b8f9d | 5857 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5858 | (adjusted_mode->crtc_hdisplay - 1) | |
5859 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5860 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5861 | (adjusted_mode->crtc_hblank_start - 1) | |
5862 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5863 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5864 | (adjusted_mode->crtc_hsync_start - 1) | |
5865 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5866 | ||
fe2b8f9d | 5867 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5868 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5869 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5870 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5871 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5872 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5873 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5874 | (adjusted_mode->crtc_vsync_start - 1) | |
5875 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5876 | ||
b5e508d4 PZ |
5877 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5878 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5879 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5880 | * bits. */ | |
5881 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5882 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5883 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5884 | ||
b0e77b9c PZ |
5885 | /* pipesrc controls the size that is scaled from, which should |
5886 | * always be the user's requested size. | |
5887 | */ | |
5888 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5889 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5890 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5891 | } |
5892 | ||
1bd1bd80 DV |
5893 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5894 | struct intel_crtc_config *pipe_config) | |
5895 | { | |
5896 | struct drm_device *dev = crtc->base.dev; | |
5897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5898 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5899 | uint32_t tmp; | |
5900 | ||
5901 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5902 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5903 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5904 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5905 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5906 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5907 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5908 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5909 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5910 | ||
5911 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5912 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5913 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5914 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5915 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5916 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5917 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5918 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5919 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5920 | ||
5921 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5922 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5923 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5924 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5925 | } | |
5926 | ||
5927 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5928 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5929 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5930 | ||
5931 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5932 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5933 | } |
5934 | ||
f6a83288 DV |
5935 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5936 | struct intel_crtc_config *pipe_config) | |
babea61d | 5937 | { |
f6a83288 DV |
5938 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5939 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5940 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5941 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5942 | |
f6a83288 DV |
5943 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5944 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5945 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5946 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5947 | |
f6a83288 | 5948 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5949 | |
f6a83288 DV |
5950 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5951 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5952 | } |
5953 | ||
84b046f3 DV |
5954 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5955 | { | |
5956 | struct drm_device *dev = intel_crtc->base.dev; | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | uint32_t pipeconf; | |
5959 | ||
9f11a9e4 | 5960 | pipeconf = 0; |
84b046f3 | 5961 | |
67c72a12 DV |
5962 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5963 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5964 | pipeconf |= PIPECONF_ENABLE; | |
5965 | ||
cf532bb2 VS |
5966 | if (intel_crtc->config.double_wide) |
5967 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5968 | |
ff9ce46e DV |
5969 | /* only g4x and later have fancy bpc/dither controls */ |
5970 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5971 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5972 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5973 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5974 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5975 | |
ff9ce46e DV |
5976 | switch (intel_crtc->config.pipe_bpp) { |
5977 | case 18: | |
5978 | pipeconf |= PIPECONF_6BPC; | |
5979 | break; | |
5980 | case 24: | |
5981 | pipeconf |= PIPECONF_8BPC; | |
5982 | break; | |
5983 | case 30: | |
5984 | pipeconf |= PIPECONF_10BPC; | |
5985 | break; | |
5986 | default: | |
5987 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5988 | BUG(); | |
84b046f3 DV |
5989 | } |
5990 | } | |
5991 | ||
5992 | if (HAS_PIPE_CXSR(dev)) { | |
5993 | if (intel_crtc->lowfreq_avail) { | |
5994 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5995 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5996 | } else { | |
5997 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5998 | } |
5999 | } | |
6000 | ||
efc2cfff VS |
6001 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6002 | if (INTEL_INFO(dev)->gen < 4 || | |
6003 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6004 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6005 | else | |
6006 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6007 | } else | |
84b046f3 DV |
6008 | pipeconf |= PIPECONF_PROGRESSIVE; |
6009 | ||
9f11a9e4 DV |
6010 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6011 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6012 | |
84b046f3 DV |
6013 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6014 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6015 | } | |
6016 | ||
f564048e | 6017 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6018 | int x, int y, |
94352cf9 | 6019 | struct drm_framebuffer *fb) |
79e53945 JB |
6020 | { |
6021 | struct drm_device *dev = crtc->dev; | |
6022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6024 | int refclk, num_connectors = 0; |
652c393a | 6025 | intel_clock_t clock, reduced_clock; |
a16af721 | 6026 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6027 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6028 | struct intel_encoder *encoder; |
d4906093 | 6029 | const intel_limit_t *limit; |
79e53945 | 6030 | |
6c2b7c12 | 6031 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6032 | switch (encoder->type) { |
79e53945 JB |
6033 | case INTEL_OUTPUT_LVDS: |
6034 | is_lvds = true; | |
6035 | break; | |
e9fd1c02 JN |
6036 | case INTEL_OUTPUT_DSI: |
6037 | is_dsi = true; | |
6038 | break; | |
79e53945 | 6039 | } |
43565a06 | 6040 | |
c751ce4f | 6041 | num_connectors++; |
79e53945 JB |
6042 | } |
6043 | ||
f2335330 | 6044 | if (is_dsi) |
5b18e57c | 6045 | return 0; |
f2335330 JN |
6046 | |
6047 | if (!intel_crtc->config.clock_set) { | |
6048 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6049 | |
e9fd1c02 JN |
6050 | /* |
6051 | * Returns a set of divisors for the desired target clock with | |
6052 | * the given refclk, or FALSE. The returned values represent | |
6053 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6054 | * 2) / p1 / p2. | |
6055 | */ | |
6056 | limit = intel_limit(crtc, refclk); | |
6057 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6058 | intel_crtc->config.port_clock, | |
6059 | refclk, NULL, &clock); | |
f2335330 | 6060 | if (!ok) { |
e9fd1c02 JN |
6061 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6062 | return -EINVAL; | |
6063 | } | |
79e53945 | 6064 | |
f2335330 JN |
6065 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6066 | /* | |
6067 | * Ensure we match the reduced clock's P to the target | |
6068 | * clock. If the clocks don't match, we can't switch | |
6069 | * the display clock by using the FP0/FP1. In such case | |
6070 | * we will disable the LVDS downclock feature. | |
6071 | */ | |
6072 | has_reduced_clock = | |
6073 | dev_priv->display.find_dpll(limit, crtc, | |
6074 | dev_priv->lvds_downclock, | |
6075 | refclk, &clock, | |
6076 | &reduced_clock); | |
6077 | } | |
6078 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6079 | intel_crtc->config.dpll.n = clock.n; |
6080 | intel_crtc->config.dpll.m1 = clock.m1; | |
6081 | intel_crtc->config.dpll.m2 = clock.m2; | |
6082 | intel_crtc->config.dpll.p1 = clock.p1; | |
6083 | intel_crtc->config.dpll.p2 = clock.p2; | |
6084 | } | |
7026d4ac | 6085 | |
e9fd1c02 | 6086 | if (IS_GEN2(dev)) { |
8a654f3b | 6087 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6088 | has_reduced_clock ? &reduced_clock : NULL, |
6089 | num_connectors); | |
9d556c99 CML |
6090 | } else if (IS_CHERRYVIEW(dev)) { |
6091 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6092 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6093 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6094 | } else { |
f47709a9 | 6095 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6096 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6097 | num_connectors); |
e9fd1c02 | 6098 | } |
79e53945 | 6099 | |
c8f7a0db | 6100 | return 0; |
f564048e EA |
6101 | } |
6102 | ||
2fa2fe9a DV |
6103 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6104 | struct intel_crtc_config *pipe_config) | |
6105 | { | |
6106 | struct drm_device *dev = crtc->base.dev; | |
6107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6108 | uint32_t tmp; | |
6109 | ||
dc9e7dec VS |
6110 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6111 | return; | |
6112 | ||
2fa2fe9a | 6113 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6114 | if (!(tmp & PFIT_ENABLE)) |
6115 | return; | |
2fa2fe9a | 6116 | |
06922821 | 6117 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6118 | if (INTEL_INFO(dev)->gen < 4) { |
6119 | if (crtc->pipe != PIPE_B) | |
6120 | return; | |
2fa2fe9a DV |
6121 | } else { |
6122 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6123 | return; | |
6124 | } | |
6125 | ||
06922821 | 6126 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6127 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6128 | if (INTEL_INFO(dev)->gen < 5) | |
6129 | pipe_config->gmch_pfit.lvds_border_bits = | |
6130 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6131 | } | |
6132 | ||
acbec814 JB |
6133 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6134 | struct intel_crtc_config *pipe_config) | |
6135 | { | |
6136 | struct drm_device *dev = crtc->base.dev; | |
6137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6138 | int pipe = pipe_config->cpu_transcoder; | |
6139 | intel_clock_t clock; | |
6140 | u32 mdiv; | |
662c6ecb | 6141 | int refclk = 100000; |
acbec814 JB |
6142 | |
6143 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6144 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6145 | mutex_unlock(&dev_priv->dpio_lock); |
6146 | ||
6147 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6148 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6149 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6150 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6151 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6152 | ||
f646628b | 6153 | vlv_clock(refclk, &clock); |
acbec814 | 6154 | |
f646628b VS |
6155 | /* clock.dot is the fast clock */ |
6156 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6157 | } |
6158 | ||
1ad292b5 JB |
6159 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6160 | struct intel_plane_config *plane_config) | |
6161 | { | |
6162 | struct drm_device *dev = crtc->base.dev; | |
6163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6164 | u32 val, base, offset; | |
6165 | int pipe = crtc->pipe, plane = crtc->plane; | |
6166 | int fourcc, pixel_format; | |
6167 | int aligned_height; | |
6168 | ||
66e514c1 DA |
6169 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6170 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6171 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6172 | return; | |
6173 | } | |
6174 | ||
6175 | val = I915_READ(DSPCNTR(plane)); | |
6176 | ||
6177 | if (INTEL_INFO(dev)->gen >= 4) | |
6178 | if (val & DISPPLANE_TILED) | |
6179 | plane_config->tiled = true; | |
6180 | ||
6181 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6182 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6183 | crtc->base.primary->fb->pixel_format = fourcc; |
6184 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6185 | drm_format_plane_cpp(fourcc, 0) * 8; |
6186 | ||
6187 | if (INTEL_INFO(dev)->gen >= 4) { | |
6188 | if (plane_config->tiled) | |
6189 | offset = I915_READ(DSPTILEOFF(plane)); | |
6190 | else | |
6191 | offset = I915_READ(DSPLINOFF(plane)); | |
6192 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6193 | } else { | |
6194 | base = I915_READ(DSPADDR(plane)); | |
6195 | } | |
6196 | plane_config->base = base; | |
6197 | ||
6198 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6199 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6200 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6201 | |
6202 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6203 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6204 | |
66e514c1 | 6205 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6206 | plane_config->tiled); |
6207 | ||
1267a26b FF |
6208 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6209 | aligned_height); | |
1ad292b5 JB |
6210 | |
6211 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6212 | pipe, plane, crtc->base.primary->fb->width, |
6213 | crtc->base.primary->fb->height, | |
6214 | crtc->base.primary->fb->bits_per_pixel, base, | |
6215 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6216 | plane_config->size); |
6217 | ||
6218 | } | |
6219 | ||
70b23a98 VS |
6220 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6221 | struct intel_crtc_config *pipe_config) | |
6222 | { | |
6223 | struct drm_device *dev = crtc->base.dev; | |
6224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6225 | int pipe = pipe_config->cpu_transcoder; | |
6226 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6227 | intel_clock_t clock; | |
6228 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6229 | int refclk = 100000; | |
6230 | ||
6231 | mutex_lock(&dev_priv->dpio_lock); | |
6232 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6233 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6234 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6235 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6236 | mutex_unlock(&dev_priv->dpio_lock); | |
6237 | ||
6238 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6239 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6240 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6241 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6242 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6243 | ||
6244 | chv_clock(refclk, &clock); | |
6245 | ||
6246 | /* clock.dot is the fast clock */ | |
6247 | pipe_config->port_clock = clock.dot / 5; | |
6248 | } | |
6249 | ||
0e8ffe1b DV |
6250 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6251 | struct intel_crtc_config *pipe_config) | |
6252 | { | |
6253 | struct drm_device *dev = crtc->base.dev; | |
6254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6255 | uint32_t tmp; | |
6256 | ||
b5482bd0 ID |
6257 | if (!intel_display_power_enabled(dev_priv, |
6258 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6259 | return false; | |
6260 | ||
e143a21c | 6261 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6262 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6263 | |
0e8ffe1b DV |
6264 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6265 | if (!(tmp & PIPECONF_ENABLE)) | |
6266 | return false; | |
6267 | ||
42571aef VS |
6268 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6269 | switch (tmp & PIPECONF_BPC_MASK) { | |
6270 | case PIPECONF_6BPC: | |
6271 | pipe_config->pipe_bpp = 18; | |
6272 | break; | |
6273 | case PIPECONF_8BPC: | |
6274 | pipe_config->pipe_bpp = 24; | |
6275 | break; | |
6276 | case PIPECONF_10BPC: | |
6277 | pipe_config->pipe_bpp = 30; | |
6278 | break; | |
6279 | default: | |
6280 | break; | |
6281 | } | |
6282 | } | |
6283 | ||
b5a9fa09 DV |
6284 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6285 | pipe_config->limited_color_range = true; | |
6286 | ||
282740f7 VS |
6287 | if (INTEL_INFO(dev)->gen < 4) |
6288 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6289 | ||
1bd1bd80 DV |
6290 | intel_get_pipe_timings(crtc, pipe_config); |
6291 | ||
2fa2fe9a DV |
6292 | i9xx_get_pfit_config(crtc, pipe_config); |
6293 | ||
6c49f241 DV |
6294 | if (INTEL_INFO(dev)->gen >= 4) { |
6295 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6296 | pipe_config->pixel_multiplier = | |
6297 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6298 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6299 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6300 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6301 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6302 | pipe_config->pixel_multiplier = | |
6303 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6304 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6305 | } else { | |
6306 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6307 | * port and will be fixed up in the encoder->get_config | |
6308 | * function. */ | |
6309 | pipe_config->pixel_multiplier = 1; | |
6310 | } | |
8bcc2795 DV |
6311 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6312 | if (!IS_VALLEYVIEW(dev)) { | |
6313 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6314 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6315 | } else { |
6316 | /* Mask out read-only status bits. */ | |
6317 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6318 | DPLL_PORTC_READY_MASK | | |
6319 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6320 | } |
6c49f241 | 6321 | |
70b23a98 VS |
6322 | if (IS_CHERRYVIEW(dev)) |
6323 | chv_crtc_clock_get(crtc, pipe_config); | |
6324 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6325 | vlv_crtc_clock_get(crtc, pipe_config); |
6326 | else | |
6327 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6328 | |
0e8ffe1b DV |
6329 | return true; |
6330 | } | |
6331 | ||
dde86e2d | 6332 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6333 | { |
6334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6335 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6336 | struct intel_encoder *encoder; |
74cfd7ac | 6337 | u32 val, final; |
13d83a67 | 6338 | bool has_lvds = false; |
199e5d79 | 6339 | bool has_cpu_edp = false; |
199e5d79 | 6340 | bool has_panel = false; |
99eb6a01 KP |
6341 | bool has_ck505 = false; |
6342 | bool can_ssc = false; | |
13d83a67 JB |
6343 | |
6344 | /* We need to take the global config into account */ | |
199e5d79 KP |
6345 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6346 | base.head) { | |
6347 | switch (encoder->type) { | |
6348 | case INTEL_OUTPUT_LVDS: | |
6349 | has_panel = true; | |
6350 | has_lvds = true; | |
6351 | break; | |
6352 | case INTEL_OUTPUT_EDP: | |
6353 | has_panel = true; | |
2de6905f | 6354 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6355 | has_cpu_edp = true; |
6356 | break; | |
13d83a67 JB |
6357 | } |
6358 | } | |
6359 | ||
99eb6a01 | 6360 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6361 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6362 | can_ssc = has_ck505; |
6363 | } else { | |
6364 | has_ck505 = false; | |
6365 | can_ssc = true; | |
6366 | } | |
6367 | ||
2de6905f ID |
6368 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6369 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6370 | |
6371 | /* Ironlake: try to setup display ref clock before DPLL | |
6372 | * enabling. This is only under driver's control after | |
6373 | * PCH B stepping, previous chipset stepping should be | |
6374 | * ignoring this setting. | |
6375 | */ | |
74cfd7ac CW |
6376 | val = I915_READ(PCH_DREF_CONTROL); |
6377 | ||
6378 | /* As we must carefully and slowly disable/enable each source in turn, | |
6379 | * compute the final state we want first and check if we need to | |
6380 | * make any changes at all. | |
6381 | */ | |
6382 | final = val; | |
6383 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6384 | if (has_ck505) | |
6385 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6386 | else | |
6387 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6388 | ||
6389 | final &= ~DREF_SSC_SOURCE_MASK; | |
6390 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6391 | final &= ~DREF_SSC1_ENABLE; | |
6392 | ||
6393 | if (has_panel) { | |
6394 | final |= DREF_SSC_SOURCE_ENABLE; | |
6395 | ||
6396 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6397 | final |= DREF_SSC1_ENABLE; | |
6398 | ||
6399 | if (has_cpu_edp) { | |
6400 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6401 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6402 | else | |
6403 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6404 | } else | |
6405 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6406 | } else { | |
6407 | final |= DREF_SSC_SOURCE_DISABLE; | |
6408 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6409 | } | |
6410 | ||
6411 | if (final == val) | |
6412 | return; | |
6413 | ||
13d83a67 | 6414 | /* Always enable nonspread source */ |
74cfd7ac | 6415 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6416 | |
99eb6a01 | 6417 | if (has_ck505) |
74cfd7ac | 6418 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6419 | else |
74cfd7ac | 6420 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6421 | |
199e5d79 | 6422 | if (has_panel) { |
74cfd7ac CW |
6423 | val &= ~DREF_SSC_SOURCE_MASK; |
6424 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6425 | |
199e5d79 | 6426 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6427 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6428 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6429 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6430 | } else |
74cfd7ac | 6431 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6432 | |
6433 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6434 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6435 | POSTING_READ(PCH_DREF_CONTROL); |
6436 | udelay(200); | |
6437 | ||
74cfd7ac | 6438 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6439 | |
6440 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6441 | if (has_cpu_edp) { |
99eb6a01 | 6442 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6443 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6444 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6445 | } else |
74cfd7ac | 6446 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6447 | } else |
74cfd7ac | 6448 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6449 | |
74cfd7ac | 6450 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6451 | POSTING_READ(PCH_DREF_CONTROL); |
6452 | udelay(200); | |
6453 | } else { | |
6454 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6455 | ||
74cfd7ac | 6456 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6457 | |
6458 | /* Turn off CPU output */ | |
74cfd7ac | 6459 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6460 | |
74cfd7ac | 6461 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6462 | POSTING_READ(PCH_DREF_CONTROL); |
6463 | udelay(200); | |
6464 | ||
6465 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6466 | val &= ~DREF_SSC_SOURCE_MASK; |
6467 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6468 | |
6469 | /* Turn off SSC1 */ | |
74cfd7ac | 6470 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6471 | |
74cfd7ac | 6472 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6473 | POSTING_READ(PCH_DREF_CONTROL); |
6474 | udelay(200); | |
6475 | } | |
74cfd7ac CW |
6476 | |
6477 | BUG_ON(val != final); | |
13d83a67 JB |
6478 | } |
6479 | ||
f31f2d55 | 6480 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6481 | { |
f31f2d55 | 6482 | uint32_t tmp; |
dde86e2d | 6483 | |
0ff066a9 PZ |
6484 | tmp = I915_READ(SOUTH_CHICKEN2); |
6485 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6486 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6487 | |
0ff066a9 PZ |
6488 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6489 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6490 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6491 | |
0ff066a9 PZ |
6492 | tmp = I915_READ(SOUTH_CHICKEN2); |
6493 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6494 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6495 | |
0ff066a9 PZ |
6496 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6497 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6498 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6499 | } |
6500 | ||
6501 | /* WaMPhyProgramming:hsw */ | |
6502 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6503 | { | |
6504 | uint32_t tmp; | |
dde86e2d PZ |
6505 | |
6506 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6507 | tmp &= ~(0xFF << 24); | |
6508 | tmp |= (0x12 << 24); | |
6509 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6510 | ||
dde86e2d PZ |
6511 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6512 | tmp |= (1 << 11); | |
6513 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6514 | ||
6515 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6516 | tmp |= (1 << 11); | |
6517 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6518 | ||
dde86e2d PZ |
6519 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6520 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6521 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6522 | ||
6523 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6524 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6525 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6526 | ||
0ff066a9 PZ |
6527 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6528 | tmp &= ~(7 << 13); | |
6529 | tmp |= (5 << 13); | |
6530 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6531 | |
0ff066a9 PZ |
6532 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6533 | tmp &= ~(7 << 13); | |
6534 | tmp |= (5 << 13); | |
6535 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6536 | |
6537 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6538 | tmp &= ~0xFF; | |
6539 | tmp |= 0x1C; | |
6540 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6541 | ||
6542 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6543 | tmp &= ~0xFF; | |
6544 | tmp |= 0x1C; | |
6545 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6546 | ||
6547 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6548 | tmp &= ~(0xFF << 16); | |
6549 | tmp |= (0x1C << 16); | |
6550 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6551 | ||
6552 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6553 | tmp &= ~(0xFF << 16); | |
6554 | tmp |= (0x1C << 16); | |
6555 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6556 | ||
0ff066a9 PZ |
6557 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6558 | tmp |= (1 << 27); | |
6559 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6560 | |
0ff066a9 PZ |
6561 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6562 | tmp |= (1 << 27); | |
6563 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6564 | |
0ff066a9 PZ |
6565 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6566 | tmp &= ~(0xF << 28); | |
6567 | tmp |= (4 << 28); | |
6568 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6569 | |
0ff066a9 PZ |
6570 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6571 | tmp &= ~(0xF << 28); | |
6572 | tmp |= (4 << 28); | |
6573 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6574 | } |
6575 | ||
2fa86a1f PZ |
6576 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6577 | * Programming" based on the parameters passed: | |
6578 | * - Sequence to enable CLKOUT_DP | |
6579 | * - Sequence to enable CLKOUT_DP without spread | |
6580 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6581 | */ | |
6582 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6583 | bool with_fdi) | |
f31f2d55 PZ |
6584 | { |
6585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6586 | uint32_t reg, tmp; |
6587 | ||
6588 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6589 | with_spread = true; | |
6590 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6591 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6592 | with_fdi = false; | |
f31f2d55 PZ |
6593 | |
6594 | mutex_lock(&dev_priv->dpio_lock); | |
6595 | ||
6596 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6597 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6598 | tmp |= SBI_SSCCTL_PATHALT; | |
6599 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6600 | ||
6601 | udelay(24); | |
6602 | ||
2fa86a1f PZ |
6603 | if (with_spread) { |
6604 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6605 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6606 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6607 | |
2fa86a1f PZ |
6608 | if (with_fdi) { |
6609 | lpt_reset_fdi_mphy(dev_priv); | |
6610 | lpt_program_fdi_mphy(dev_priv); | |
6611 | } | |
6612 | } | |
dde86e2d | 6613 | |
2fa86a1f PZ |
6614 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6615 | SBI_GEN0 : SBI_DBUFF0; | |
6616 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6617 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6618 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6619 | |
6620 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6621 | } |
6622 | ||
47701c3b PZ |
6623 | /* Sequence to disable CLKOUT_DP */ |
6624 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6625 | { | |
6626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6627 | uint32_t reg, tmp; | |
6628 | ||
6629 | mutex_lock(&dev_priv->dpio_lock); | |
6630 | ||
6631 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6632 | SBI_GEN0 : SBI_DBUFF0; | |
6633 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6634 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6635 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6636 | ||
6637 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6638 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6639 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6640 | tmp |= SBI_SSCCTL_PATHALT; | |
6641 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6642 | udelay(32); | |
6643 | } | |
6644 | tmp |= SBI_SSCCTL_DISABLE; | |
6645 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6646 | } | |
6647 | ||
6648 | mutex_unlock(&dev_priv->dpio_lock); | |
6649 | } | |
6650 | ||
bf8fa3d3 PZ |
6651 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6652 | { | |
6653 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6654 | struct intel_encoder *encoder; | |
6655 | bool has_vga = false; | |
6656 | ||
6657 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6658 | switch (encoder->type) { | |
6659 | case INTEL_OUTPUT_ANALOG: | |
6660 | has_vga = true; | |
6661 | break; | |
6662 | } | |
6663 | } | |
6664 | ||
47701c3b PZ |
6665 | if (has_vga) |
6666 | lpt_enable_clkout_dp(dev, true, true); | |
6667 | else | |
6668 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6669 | } |
6670 | ||
dde86e2d PZ |
6671 | /* |
6672 | * Initialize reference clocks when the driver loads | |
6673 | */ | |
6674 | void intel_init_pch_refclk(struct drm_device *dev) | |
6675 | { | |
6676 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6677 | ironlake_init_pch_refclk(dev); | |
6678 | else if (HAS_PCH_LPT(dev)) | |
6679 | lpt_init_pch_refclk(dev); | |
6680 | } | |
6681 | ||
d9d444cb JB |
6682 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6683 | { | |
6684 | struct drm_device *dev = crtc->dev; | |
6685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6686 | struct intel_encoder *encoder; | |
d9d444cb JB |
6687 | int num_connectors = 0; |
6688 | bool is_lvds = false; | |
6689 | ||
6c2b7c12 | 6690 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6691 | switch (encoder->type) { |
6692 | case INTEL_OUTPUT_LVDS: | |
6693 | is_lvds = true; | |
6694 | break; | |
d9d444cb JB |
6695 | } |
6696 | num_connectors++; | |
6697 | } | |
6698 | ||
6699 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6700 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6701 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6702 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6703 | } |
6704 | ||
6705 | return 120000; | |
6706 | } | |
6707 | ||
6ff93609 | 6708 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6709 | { |
c8203565 | 6710 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6712 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6713 | uint32_t val; |
6714 | ||
78114071 | 6715 | val = 0; |
c8203565 | 6716 | |
965e0c48 | 6717 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6718 | case 18: |
dfd07d72 | 6719 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6720 | break; |
6721 | case 24: | |
dfd07d72 | 6722 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6723 | break; |
6724 | case 30: | |
dfd07d72 | 6725 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6726 | break; |
6727 | case 36: | |
dfd07d72 | 6728 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6729 | break; |
6730 | default: | |
cc769b62 PZ |
6731 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6732 | BUG(); | |
c8203565 PZ |
6733 | } |
6734 | ||
d8b32247 | 6735 | if (intel_crtc->config.dither) |
c8203565 PZ |
6736 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6737 | ||
6ff93609 | 6738 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6739 | val |= PIPECONF_INTERLACED_ILK; |
6740 | else | |
6741 | val |= PIPECONF_PROGRESSIVE; | |
6742 | ||
50f3b016 | 6743 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6744 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6745 | |
c8203565 PZ |
6746 | I915_WRITE(PIPECONF(pipe), val); |
6747 | POSTING_READ(PIPECONF(pipe)); | |
6748 | } | |
6749 | ||
86d3efce VS |
6750 | /* |
6751 | * Set up the pipe CSC unit. | |
6752 | * | |
6753 | * Currently only full range RGB to limited range RGB conversion | |
6754 | * is supported, but eventually this should handle various | |
6755 | * RGB<->YCbCr scenarios as well. | |
6756 | */ | |
50f3b016 | 6757 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6758 | { |
6759 | struct drm_device *dev = crtc->dev; | |
6760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6762 | int pipe = intel_crtc->pipe; | |
6763 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6764 | ||
6765 | /* | |
6766 | * TODO: Check what kind of values actually come out of the pipe | |
6767 | * with these coeff/postoff values and adjust to get the best | |
6768 | * accuracy. Perhaps we even need to take the bpc value into | |
6769 | * consideration. | |
6770 | */ | |
6771 | ||
50f3b016 | 6772 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6773 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6774 | ||
6775 | /* | |
6776 | * GY/GU and RY/RU should be the other way around according | |
6777 | * to BSpec, but reality doesn't agree. Just set them up in | |
6778 | * a way that results in the correct picture. | |
6779 | */ | |
6780 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6781 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6782 | ||
6783 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6784 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6785 | ||
6786 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6787 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6788 | ||
6789 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6790 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6791 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6792 | ||
6793 | if (INTEL_INFO(dev)->gen > 6) { | |
6794 | uint16_t postoff = 0; | |
6795 | ||
50f3b016 | 6796 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6797 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6798 | |
6799 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6800 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6801 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6802 | ||
6803 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6804 | } else { | |
6805 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6806 | ||
50f3b016 | 6807 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6808 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6809 | ||
6810 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6811 | } | |
6812 | } | |
6813 | ||
6ff93609 | 6814 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6815 | { |
756f85cf PZ |
6816 | struct drm_device *dev = crtc->dev; |
6817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6819 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6820 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6821 | uint32_t val; |
6822 | ||
3eff4faa | 6823 | val = 0; |
ee2b0b38 | 6824 | |
756f85cf | 6825 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6826 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6827 | ||
6ff93609 | 6828 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6829 | val |= PIPECONF_INTERLACED_ILK; |
6830 | else | |
6831 | val |= PIPECONF_PROGRESSIVE; | |
6832 | ||
702e7a56 PZ |
6833 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6834 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6835 | |
6836 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6837 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6838 | |
6839 | if (IS_BROADWELL(dev)) { | |
6840 | val = 0; | |
6841 | ||
6842 | switch (intel_crtc->config.pipe_bpp) { | |
6843 | case 18: | |
6844 | val |= PIPEMISC_DITHER_6_BPC; | |
6845 | break; | |
6846 | case 24: | |
6847 | val |= PIPEMISC_DITHER_8_BPC; | |
6848 | break; | |
6849 | case 30: | |
6850 | val |= PIPEMISC_DITHER_10_BPC; | |
6851 | break; | |
6852 | case 36: | |
6853 | val |= PIPEMISC_DITHER_12_BPC; | |
6854 | break; | |
6855 | default: | |
6856 | /* Case prevented by pipe_config_set_bpp. */ | |
6857 | BUG(); | |
6858 | } | |
6859 | ||
6860 | if (intel_crtc->config.dither) | |
6861 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6862 | ||
6863 | I915_WRITE(PIPEMISC(pipe), val); | |
6864 | } | |
ee2b0b38 PZ |
6865 | } |
6866 | ||
6591c6e4 | 6867 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6868 | intel_clock_t *clock, |
6869 | bool *has_reduced_clock, | |
6870 | intel_clock_t *reduced_clock) | |
6871 | { | |
6872 | struct drm_device *dev = crtc->dev; | |
6873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6874 | struct intel_encoder *intel_encoder; | |
6875 | int refclk; | |
d4906093 | 6876 | const intel_limit_t *limit; |
a16af721 | 6877 | bool ret, is_lvds = false; |
79e53945 | 6878 | |
6591c6e4 PZ |
6879 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6880 | switch (intel_encoder->type) { | |
79e53945 JB |
6881 | case INTEL_OUTPUT_LVDS: |
6882 | is_lvds = true; | |
6883 | break; | |
79e53945 JB |
6884 | } |
6885 | } | |
6886 | ||
d9d444cb | 6887 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6888 | |
d4906093 ML |
6889 | /* |
6890 | * Returns a set of divisors for the desired target clock with the given | |
6891 | * refclk, or FALSE. The returned values represent the clock equation: | |
6892 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6893 | */ | |
1b894b59 | 6894 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6895 | ret = dev_priv->display.find_dpll(limit, crtc, |
6896 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6897 | refclk, NULL, clock); |
6591c6e4 PZ |
6898 | if (!ret) |
6899 | return false; | |
cda4b7d3 | 6900 | |
ddc9003c | 6901 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6902 | /* |
6903 | * Ensure we match the reduced clock's P to the target clock. | |
6904 | * If the clocks don't match, we can't switch the display clock | |
6905 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6906 | * downclock feature. | |
6907 | */ | |
ee9300bb DV |
6908 | *has_reduced_clock = |
6909 | dev_priv->display.find_dpll(limit, crtc, | |
6910 | dev_priv->lvds_downclock, | |
6911 | refclk, clock, | |
6912 | reduced_clock); | |
652c393a | 6913 | } |
61e9653f | 6914 | |
6591c6e4 PZ |
6915 | return true; |
6916 | } | |
6917 | ||
d4b1931c PZ |
6918 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6919 | { | |
6920 | /* | |
6921 | * Account for spread spectrum to avoid | |
6922 | * oversubscribing the link. Max center spread | |
6923 | * is 2.5%; use 5% for safety's sake. | |
6924 | */ | |
6925 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6926 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6927 | } |
6928 | ||
7429e9d4 | 6929 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6930 | { |
7429e9d4 | 6931 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6932 | } |
6933 | ||
de13a2e3 | 6934 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6935 | u32 *fp, |
9a7c7890 | 6936 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6937 | { |
de13a2e3 | 6938 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6939 | struct drm_device *dev = crtc->dev; |
6940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6941 | struct intel_encoder *intel_encoder; |
6942 | uint32_t dpll; | |
6cc5f341 | 6943 | int factor, num_connectors = 0; |
09ede541 | 6944 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6945 | |
de13a2e3 PZ |
6946 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6947 | switch (intel_encoder->type) { | |
79e53945 JB |
6948 | case INTEL_OUTPUT_LVDS: |
6949 | is_lvds = true; | |
6950 | break; | |
6951 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6952 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6953 | is_sdvo = true; |
79e53945 | 6954 | break; |
79e53945 | 6955 | } |
43565a06 | 6956 | |
c751ce4f | 6957 | num_connectors++; |
79e53945 | 6958 | } |
79e53945 | 6959 | |
c1858123 | 6960 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6961 | factor = 21; |
6962 | if (is_lvds) { | |
6963 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6964 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6965 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6966 | factor = 25; |
09ede541 | 6967 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6968 | factor = 20; |
c1858123 | 6969 | |
7429e9d4 | 6970 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6971 | *fp |= FP_CB_TUNE; |
2c07245f | 6972 | |
9a7c7890 DV |
6973 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6974 | *fp2 |= FP_CB_TUNE; | |
6975 | ||
5eddb70b | 6976 | dpll = 0; |
2c07245f | 6977 | |
a07d6787 EA |
6978 | if (is_lvds) |
6979 | dpll |= DPLLB_MODE_LVDS; | |
6980 | else | |
6981 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6982 | |
ef1b460d DV |
6983 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6984 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6985 | |
6986 | if (is_sdvo) | |
4a33e48d | 6987 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6988 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6989 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6990 | |
a07d6787 | 6991 | /* compute bitmask from p1 value */ |
7429e9d4 | 6992 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6993 | /* also FPA1 */ |
7429e9d4 | 6994 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6995 | |
7429e9d4 | 6996 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6997 | case 5: |
6998 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6999 | break; | |
7000 | case 7: | |
7001 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7002 | break; | |
7003 | case 10: | |
7004 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7005 | break; | |
7006 | case 14: | |
7007 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7008 | break; | |
79e53945 JB |
7009 | } |
7010 | ||
b4c09f3b | 7011 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7012 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7013 | else |
7014 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7015 | ||
959e16d6 | 7016 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7017 | } |
7018 | ||
7019 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7020 | int x, int y, |
7021 | struct drm_framebuffer *fb) | |
7022 | { | |
7023 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7025 | int num_connectors = 0; |
7026 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7027 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7028 | bool ok, has_reduced_clock = false; |
8b47047b | 7029 | bool is_lvds = false; |
de13a2e3 | 7030 | struct intel_encoder *encoder; |
e2b78267 | 7031 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7032 | |
7033 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7034 | switch (encoder->type) { | |
7035 | case INTEL_OUTPUT_LVDS: | |
7036 | is_lvds = true; | |
7037 | break; | |
de13a2e3 PZ |
7038 | } |
7039 | ||
7040 | num_connectors++; | |
a07d6787 | 7041 | } |
79e53945 | 7042 | |
5dc5298b PZ |
7043 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7044 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7045 | |
ff9a6750 | 7046 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7047 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7048 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7049 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7050 | return -EINVAL; | |
79e53945 | 7051 | } |
f47709a9 DV |
7052 | /* Compat-code for transition, will disappear. */ |
7053 | if (!intel_crtc->config.clock_set) { | |
7054 | intel_crtc->config.dpll.n = clock.n; | |
7055 | intel_crtc->config.dpll.m1 = clock.m1; | |
7056 | intel_crtc->config.dpll.m2 = clock.m2; | |
7057 | intel_crtc->config.dpll.p1 = clock.p1; | |
7058 | intel_crtc->config.dpll.p2 = clock.p2; | |
7059 | } | |
79e53945 | 7060 | |
5dc5298b | 7061 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7062 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7063 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7064 | if (has_reduced_clock) |
7429e9d4 | 7065 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7066 | |
7429e9d4 | 7067 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7068 | &fp, &reduced_clock, |
7069 | has_reduced_clock ? &fp2 : NULL); | |
7070 | ||
959e16d6 | 7071 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7072 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7073 | if (has_reduced_clock) | |
7074 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7075 | else | |
7076 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7077 | ||
b89a1d39 | 7078 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7079 | if (pll == NULL) { |
84f44ce7 | 7080 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7081 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7082 | return -EINVAL; |
7083 | } | |
ee7b9f93 | 7084 | } else |
e72f9fbf | 7085 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7086 | |
d330a953 | 7087 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7088 | intel_crtc->lowfreq_avail = true; |
7089 | else | |
7090 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7091 | |
c8f7a0db | 7092 | return 0; |
79e53945 JB |
7093 | } |
7094 | ||
eb14cb74 VS |
7095 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7096 | struct intel_link_m_n *m_n) | |
7097 | { | |
7098 | struct drm_device *dev = crtc->base.dev; | |
7099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7100 | enum pipe pipe = crtc->pipe; | |
7101 | ||
7102 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7103 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7104 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7105 | & ~TU_SIZE_MASK; | |
7106 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7107 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7108 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7109 | } | |
7110 | ||
7111 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7112 | enum transcoder transcoder, | |
7113 | struct intel_link_m_n *m_n) | |
72419203 DV |
7114 | { |
7115 | struct drm_device *dev = crtc->base.dev; | |
7116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7117 | enum pipe pipe = crtc->pipe; |
72419203 | 7118 | |
eb14cb74 VS |
7119 | if (INTEL_INFO(dev)->gen >= 5) { |
7120 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7121 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7122 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7123 | & ~TU_SIZE_MASK; | |
7124 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7125 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7126 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7127 | } else { | |
7128 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7129 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7130 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7131 | & ~TU_SIZE_MASK; | |
7132 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7133 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7134 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7135 | } | |
7136 | } | |
7137 | ||
7138 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7139 | struct intel_crtc_config *pipe_config) | |
7140 | { | |
7141 | if (crtc->config.has_pch_encoder) | |
7142 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7143 | else | |
7144 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7145 | &pipe_config->dp_m_n); | |
7146 | } | |
72419203 | 7147 | |
eb14cb74 VS |
7148 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7149 | struct intel_crtc_config *pipe_config) | |
7150 | { | |
7151 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7152 | &pipe_config->fdi_m_n); | |
72419203 DV |
7153 | } |
7154 | ||
2fa2fe9a DV |
7155 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7156 | struct intel_crtc_config *pipe_config) | |
7157 | { | |
7158 | struct drm_device *dev = crtc->base.dev; | |
7159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7160 | uint32_t tmp; | |
7161 | ||
7162 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7163 | ||
7164 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7165 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7166 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7167 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7168 | |
7169 | /* We currently do not free assignements of panel fitters on | |
7170 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7171 | * differentiates them) so just WARN about this case for now. */ | |
7172 | if (IS_GEN7(dev)) { | |
7173 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7174 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7175 | } | |
2fa2fe9a | 7176 | } |
79e53945 JB |
7177 | } |
7178 | ||
4c6baa59 JB |
7179 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7180 | struct intel_plane_config *plane_config) | |
7181 | { | |
7182 | struct drm_device *dev = crtc->base.dev; | |
7183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7184 | u32 val, base, offset; | |
7185 | int pipe = crtc->pipe, plane = crtc->plane; | |
7186 | int fourcc, pixel_format; | |
7187 | int aligned_height; | |
7188 | ||
66e514c1 DA |
7189 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7190 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7191 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7192 | return; | |
7193 | } | |
7194 | ||
7195 | val = I915_READ(DSPCNTR(plane)); | |
7196 | ||
7197 | if (INTEL_INFO(dev)->gen >= 4) | |
7198 | if (val & DISPPLANE_TILED) | |
7199 | plane_config->tiled = true; | |
7200 | ||
7201 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7202 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7203 | crtc->base.primary->fb->pixel_format = fourcc; |
7204 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7205 | drm_format_plane_cpp(fourcc, 0) * 8; |
7206 | ||
7207 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7208 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7209 | offset = I915_READ(DSPOFFSET(plane)); | |
7210 | } else { | |
7211 | if (plane_config->tiled) | |
7212 | offset = I915_READ(DSPTILEOFF(plane)); | |
7213 | else | |
7214 | offset = I915_READ(DSPLINOFF(plane)); | |
7215 | } | |
7216 | plane_config->base = base; | |
7217 | ||
7218 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7219 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7220 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7221 | |
7222 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7223 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7224 | |
66e514c1 | 7225 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7226 | plane_config->tiled); |
7227 | ||
1267a26b FF |
7228 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7229 | aligned_height); | |
4c6baa59 JB |
7230 | |
7231 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7232 | pipe, plane, crtc->base.primary->fb->width, |
7233 | crtc->base.primary->fb->height, | |
7234 | crtc->base.primary->fb->bits_per_pixel, base, | |
7235 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7236 | plane_config->size); |
7237 | } | |
7238 | ||
0e8ffe1b DV |
7239 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7240 | struct intel_crtc_config *pipe_config) | |
7241 | { | |
7242 | struct drm_device *dev = crtc->base.dev; | |
7243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7244 | uint32_t tmp; | |
7245 | ||
e143a21c | 7246 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7247 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7248 | |
0e8ffe1b DV |
7249 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7250 | if (!(tmp & PIPECONF_ENABLE)) | |
7251 | return false; | |
7252 | ||
42571aef VS |
7253 | switch (tmp & PIPECONF_BPC_MASK) { |
7254 | case PIPECONF_6BPC: | |
7255 | pipe_config->pipe_bpp = 18; | |
7256 | break; | |
7257 | case PIPECONF_8BPC: | |
7258 | pipe_config->pipe_bpp = 24; | |
7259 | break; | |
7260 | case PIPECONF_10BPC: | |
7261 | pipe_config->pipe_bpp = 30; | |
7262 | break; | |
7263 | case PIPECONF_12BPC: | |
7264 | pipe_config->pipe_bpp = 36; | |
7265 | break; | |
7266 | default: | |
7267 | break; | |
7268 | } | |
7269 | ||
b5a9fa09 DV |
7270 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7271 | pipe_config->limited_color_range = true; | |
7272 | ||
ab9412ba | 7273 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7274 | struct intel_shared_dpll *pll; |
7275 | ||
88adfff1 DV |
7276 | pipe_config->has_pch_encoder = true; |
7277 | ||
627eb5a3 DV |
7278 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7279 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7280 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7281 | |
7282 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7283 | |
c0d43d62 | 7284 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7285 | pipe_config->shared_dpll = |
7286 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7287 | } else { |
7288 | tmp = I915_READ(PCH_DPLL_SEL); | |
7289 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7290 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7291 | else | |
7292 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7293 | } | |
66e985c0 DV |
7294 | |
7295 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7296 | ||
7297 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7298 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7299 | |
7300 | tmp = pipe_config->dpll_hw_state.dpll; | |
7301 | pipe_config->pixel_multiplier = | |
7302 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7303 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7304 | |
7305 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7306 | } else { |
7307 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7308 | } |
7309 | ||
1bd1bd80 DV |
7310 | intel_get_pipe_timings(crtc, pipe_config); |
7311 | ||
2fa2fe9a DV |
7312 | ironlake_get_pfit_config(crtc, pipe_config); |
7313 | ||
0e8ffe1b DV |
7314 | return true; |
7315 | } | |
7316 | ||
be256dc7 PZ |
7317 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7318 | { | |
7319 | struct drm_device *dev = dev_priv->dev; | |
7320 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7321 | struct intel_crtc *crtc; | |
be256dc7 | 7322 | |
d3fcc808 | 7323 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7324 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7325 | pipe_name(crtc->pipe)); |
7326 | ||
7327 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7328 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7329 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7330 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7331 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7332 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7333 | "CPU PWM1 enabled\n"); | |
7334 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7335 | "CPU PWM2 enabled\n"); | |
7336 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7337 | "PCH PWM1 enabled\n"); | |
7338 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7339 | "Utility pin enabled\n"); | |
7340 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7341 | ||
9926ada1 PZ |
7342 | /* |
7343 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7344 | * interrupts remain enabled. We used to check for that, but since it's | |
7345 | * gen-specific and since we only disable LCPLL after we fully disable | |
7346 | * the interrupts, the check below should be enough. | |
7347 | */ | |
7348 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7349 | } |
7350 | ||
3c4c9b81 PZ |
7351 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7352 | { | |
7353 | struct drm_device *dev = dev_priv->dev; | |
7354 | ||
7355 | if (IS_HASWELL(dev)) { | |
7356 | mutex_lock(&dev_priv->rps.hw_lock); | |
7357 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7358 | val)) | |
7359 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7360 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7361 | } else { | |
7362 | I915_WRITE(D_COMP, val); | |
7363 | } | |
7364 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7365 | } |
7366 | ||
7367 | /* | |
7368 | * This function implements pieces of two sequences from BSpec: | |
7369 | * - Sequence for display software to disable LCPLL | |
7370 | * - Sequence for display software to allow package C8+ | |
7371 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7372 | * register. Callers should take care of disabling all the display engine | |
7373 | * functions, doing the mode unset, fixing interrupts, etc. | |
7374 | */ | |
6ff58d53 PZ |
7375 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7376 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7377 | { |
7378 | uint32_t val; | |
7379 | ||
7380 | assert_can_disable_lcpll(dev_priv); | |
7381 | ||
7382 | val = I915_READ(LCPLL_CTL); | |
7383 | ||
7384 | if (switch_to_fclk) { | |
7385 | val |= LCPLL_CD_SOURCE_FCLK; | |
7386 | I915_WRITE(LCPLL_CTL, val); | |
7387 | ||
7388 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7389 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7390 | DRM_ERROR("Switching to FCLK failed\n"); | |
7391 | ||
7392 | val = I915_READ(LCPLL_CTL); | |
7393 | } | |
7394 | ||
7395 | val |= LCPLL_PLL_DISABLE; | |
7396 | I915_WRITE(LCPLL_CTL, val); | |
7397 | POSTING_READ(LCPLL_CTL); | |
7398 | ||
7399 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7400 | DRM_ERROR("LCPLL still locked\n"); | |
7401 | ||
7402 | val = I915_READ(D_COMP); | |
7403 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7404 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7405 | ndelay(100); |
7406 | ||
7407 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7408 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7409 | ||
7410 | if (allow_power_down) { | |
7411 | val = I915_READ(LCPLL_CTL); | |
7412 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7413 | I915_WRITE(LCPLL_CTL, val); | |
7414 | POSTING_READ(LCPLL_CTL); | |
7415 | } | |
7416 | } | |
7417 | ||
7418 | /* | |
7419 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7420 | * source. | |
7421 | */ | |
6ff58d53 | 7422 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7423 | { |
7424 | uint32_t val; | |
a8a8bd54 | 7425 | unsigned long irqflags; |
be256dc7 PZ |
7426 | |
7427 | val = I915_READ(LCPLL_CTL); | |
7428 | ||
7429 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7430 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7431 | return; | |
7432 | ||
a8a8bd54 PZ |
7433 | /* |
7434 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7435 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7436 | * | |
7437 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7438 | * the runtime PM resume sequence, so we can't just call | |
7439 | * gen6_gt_force_wake_get() because that function calls | |
7440 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7441 | * while we are on the resume sequence. So to solve this problem we have | |
7442 | * to call special forcewake code that doesn't touch runtime PM and | |
7443 | * doesn't enable the forcewake delayed work. | |
7444 | */ | |
7445 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7446 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7447 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7448 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7449 | |
be256dc7 PZ |
7450 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7451 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7452 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7453 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7454 | } |
7455 | ||
7456 | val = I915_READ(D_COMP); | |
7457 | val |= D_COMP_COMP_FORCE; | |
7458 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7459 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7460 | |
7461 | val = I915_READ(LCPLL_CTL); | |
7462 | val &= ~LCPLL_PLL_DISABLE; | |
7463 | I915_WRITE(LCPLL_CTL, val); | |
7464 | ||
7465 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7466 | DRM_ERROR("LCPLL not locked yet\n"); | |
7467 | ||
7468 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7469 | val = I915_READ(LCPLL_CTL); | |
7470 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7471 | I915_WRITE(LCPLL_CTL, val); | |
7472 | ||
7473 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7474 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7475 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7476 | } | |
215733fa | 7477 | |
a8a8bd54 PZ |
7478 | /* See the big comment above. */ |
7479 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7480 | if (--dev_priv->uncore.forcewake_count == 0) | |
7481 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7482 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7483 | } |
7484 | ||
765dab67 PZ |
7485 | /* |
7486 | * Package states C8 and deeper are really deep PC states that can only be | |
7487 | * reached when all the devices on the system allow it, so even if the graphics | |
7488 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7489 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7490 | * | |
7491 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7492 | * well is disabled and most interrupts are disabled, and these are also | |
7493 | * requirements for runtime PM. When these conditions are met, we manually do | |
7494 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7495 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7496 | * hang the machine. | |
7497 | * | |
7498 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7499 | * the state of some registers, so when we come back from PC8+ we need to | |
7500 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7501 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7502 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7503 | * because of the runtime PM support). | |
7504 | * | |
7505 | * For more, read "Display Sequences for Package C8" on the hardware | |
7506 | * documentation. | |
7507 | */ | |
a14cb6fc | 7508 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7509 | { |
c67a470b PZ |
7510 | struct drm_device *dev = dev_priv->dev; |
7511 | uint32_t val; | |
7512 | ||
c67a470b PZ |
7513 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7514 | ||
c67a470b PZ |
7515 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7516 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7517 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7518 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7519 | } | |
7520 | ||
7521 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7522 | hsw_disable_lcpll(dev_priv, true, true); |
7523 | } | |
7524 | ||
a14cb6fc | 7525 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7526 | { |
7527 | struct drm_device *dev = dev_priv->dev; | |
7528 | uint32_t val; | |
7529 | ||
c67a470b PZ |
7530 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7531 | ||
7532 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7533 | lpt_init_pch_refclk(dev); |
7534 | ||
7535 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7536 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7537 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7538 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7539 | } | |
7540 | ||
7541 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7542 | } |
7543 | ||
9a952a0d PZ |
7544 | static void snb_modeset_global_resources(struct drm_device *dev) |
7545 | { | |
7546 | modeset_update_crtc_power_domains(dev); | |
7547 | } | |
7548 | ||
4f074129 ID |
7549 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7550 | { | |
da723569 | 7551 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7552 | } |
7553 | ||
09b4ddf9 | 7554 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7555 | int x, int y, |
7556 | struct drm_framebuffer *fb) | |
7557 | { | |
09b4ddf9 | 7558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7559 | |
566b734a | 7560 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7561 | return -EINVAL; |
566b734a | 7562 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7563 | |
644cef34 DV |
7564 | intel_crtc->lowfreq_avail = false; |
7565 | ||
c8f7a0db | 7566 | return 0; |
79e53945 JB |
7567 | } |
7568 | ||
0e8ffe1b DV |
7569 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7570 | struct intel_crtc_config *pipe_config) | |
7571 | { | |
7572 | struct drm_device *dev = crtc->base.dev; | |
7573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7574 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7575 | uint32_t tmp; |
7576 | ||
b5482bd0 ID |
7577 | if (!intel_display_power_enabled(dev_priv, |
7578 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7579 | return false; | |
7580 | ||
e143a21c | 7581 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7582 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7583 | ||
eccb140b DV |
7584 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7585 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7586 | enum pipe trans_edp_pipe; | |
7587 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7588 | default: | |
7589 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7590 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7591 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7592 | trans_edp_pipe = PIPE_A; | |
7593 | break; | |
7594 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7595 | trans_edp_pipe = PIPE_B; | |
7596 | break; | |
7597 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7598 | trans_edp_pipe = PIPE_C; | |
7599 | break; | |
7600 | } | |
7601 | ||
7602 | if (trans_edp_pipe == crtc->pipe) | |
7603 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7604 | } | |
7605 | ||
da7e29bd | 7606 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7607 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7608 | return false; |
7609 | ||
eccb140b | 7610 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7611 | if (!(tmp & PIPECONF_ENABLE)) |
7612 | return false; | |
7613 | ||
88adfff1 | 7614 | /* |
f196e6be | 7615 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7616 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7617 | * the PCH transcoder is on. | |
7618 | */ | |
eccb140b | 7619 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7620 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7621 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7622 | pipe_config->has_pch_encoder = true; |
7623 | ||
627eb5a3 DV |
7624 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7625 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7626 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7627 | |
7628 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7629 | } |
7630 | ||
1bd1bd80 DV |
7631 | intel_get_pipe_timings(crtc, pipe_config); |
7632 | ||
2fa2fe9a | 7633 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7634 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7635 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7636 | |
e59150dc JB |
7637 | if (IS_HASWELL(dev)) |
7638 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7639 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7640 | |
6c49f241 DV |
7641 | pipe_config->pixel_multiplier = 1; |
7642 | ||
0e8ffe1b DV |
7643 | return true; |
7644 | } | |
7645 | ||
1a91510d JN |
7646 | static struct { |
7647 | int clock; | |
7648 | u32 config; | |
7649 | } hdmi_audio_clock[] = { | |
7650 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7651 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7652 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7653 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7654 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7655 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7656 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7657 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7658 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7659 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7660 | }; | |
7661 | ||
7662 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7663 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7664 | { | |
7665 | int i; | |
7666 | ||
7667 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7668 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7669 | break; | |
7670 | } | |
7671 | ||
7672 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7673 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7674 | i = 1; | |
7675 | } | |
7676 | ||
7677 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7678 | hdmi_audio_clock[i].clock, | |
7679 | hdmi_audio_clock[i].config); | |
7680 | ||
7681 | return hdmi_audio_clock[i].config; | |
7682 | } | |
7683 | ||
3a9627f4 WF |
7684 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7685 | int reg_eldv, uint32_t bits_eldv, | |
7686 | int reg_elda, uint32_t bits_elda, | |
7687 | int reg_edid) | |
7688 | { | |
7689 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7690 | uint8_t *eld = connector->eld; | |
7691 | uint32_t i; | |
7692 | ||
7693 | i = I915_READ(reg_eldv); | |
7694 | i &= bits_eldv; | |
7695 | ||
7696 | if (!eld[0]) | |
7697 | return !i; | |
7698 | ||
7699 | if (!i) | |
7700 | return false; | |
7701 | ||
7702 | i = I915_READ(reg_elda); | |
7703 | i &= ~bits_elda; | |
7704 | I915_WRITE(reg_elda, i); | |
7705 | ||
7706 | for (i = 0; i < eld[2]; i++) | |
7707 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7708 | return false; | |
7709 | ||
7710 | return true; | |
7711 | } | |
7712 | ||
e0dac65e | 7713 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7714 | struct drm_crtc *crtc, |
7715 | struct drm_display_mode *mode) | |
e0dac65e WF |
7716 | { |
7717 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7718 | uint8_t *eld = connector->eld; | |
7719 | uint32_t eldv; | |
7720 | uint32_t len; | |
7721 | uint32_t i; | |
7722 | ||
7723 | i = I915_READ(G4X_AUD_VID_DID); | |
7724 | ||
7725 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7726 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7727 | else | |
7728 | eldv = G4X_ELDV_DEVCTG; | |
7729 | ||
3a9627f4 WF |
7730 | if (intel_eld_uptodate(connector, |
7731 | G4X_AUD_CNTL_ST, eldv, | |
7732 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7733 | G4X_HDMIW_HDMIEDID)) | |
7734 | return; | |
7735 | ||
e0dac65e WF |
7736 | i = I915_READ(G4X_AUD_CNTL_ST); |
7737 | i &= ~(eldv | G4X_ELD_ADDR); | |
7738 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7739 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7740 | ||
7741 | if (!eld[0]) | |
7742 | return; | |
7743 | ||
7744 | len = min_t(uint8_t, eld[2], len); | |
7745 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7746 | for (i = 0; i < len; i++) | |
7747 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7748 | ||
7749 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7750 | i |= eldv; | |
7751 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7752 | } | |
7753 | ||
83358c85 | 7754 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7755 | struct drm_crtc *crtc, |
7756 | struct drm_display_mode *mode) | |
83358c85 WX |
7757 | { |
7758 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7759 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7760 | uint32_t eldv; |
7761 | uint32_t i; | |
7762 | int len; | |
7763 | int pipe = to_intel_crtc(crtc)->pipe; | |
7764 | int tmp; | |
7765 | ||
7766 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7767 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7768 | int aud_config = HSW_AUD_CFG(pipe); | |
7769 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7770 | ||
83358c85 WX |
7771 | /* Audio output enable */ |
7772 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7773 | tmp = I915_READ(aud_cntrl_st2); | |
7774 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7775 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7776 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7777 | |
c7905792 | 7778 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7779 | |
7780 | /* Set ELD valid state */ | |
7781 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7782 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7783 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7784 | I915_WRITE(aud_cntrl_st2, tmp); | |
7785 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7786 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7787 | |
7788 | /* Enable HDMI mode */ | |
7789 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7790 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7791 | /* clear N_programing_enable and N_value_index */ |
7792 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7793 | I915_WRITE(aud_config, tmp); | |
7794 | ||
7795 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7796 | ||
7797 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7798 | ||
7799 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7800 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7801 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7802 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7803 | } else { |
7804 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7805 | } | |
83358c85 WX |
7806 | |
7807 | if (intel_eld_uptodate(connector, | |
7808 | aud_cntrl_st2, eldv, | |
7809 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7810 | hdmiw_hdmiedid)) | |
7811 | return; | |
7812 | ||
7813 | i = I915_READ(aud_cntrl_st2); | |
7814 | i &= ~eldv; | |
7815 | I915_WRITE(aud_cntrl_st2, i); | |
7816 | ||
7817 | if (!eld[0]) | |
7818 | return; | |
7819 | ||
7820 | i = I915_READ(aud_cntl_st); | |
7821 | i &= ~IBX_ELD_ADDRESS; | |
7822 | I915_WRITE(aud_cntl_st, i); | |
7823 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7824 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7825 | ||
7826 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7827 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7828 | for (i = 0; i < len; i++) | |
7829 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7830 | ||
7831 | i = I915_READ(aud_cntrl_st2); | |
7832 | i |= eldv; | |
7833 | I915_WRITE(aud_cntrl_st2, i); | |
7834 | ||
7835 | } | |
7836 | ||
e0dac65e | 7837 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7838 | struct drm_crtc *crtc, |
7839 | struct drm_display_mode *mode) | |
e0dac65e WF |
7840 | { |
7841 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7842 | uint8_t *eld = connector->eld; | |
7843 | uint32_t eldv; | |
7844 | uint32_t i; | |
7845 | int len; | |
7846 | int hdmiw_hdmiedid; | |
b6daa025 | 7847 | int aud_config; |
e0dac65e WF |
7848 | int aud_cntl_st; |
7849 | int aud_cntrl_st2; | |
9b138a83 | 7850 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7851 | |
b3f33cbf | 7852 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7853 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7854 | aud_config = IBX_AUD_CFG(pipe); | |
7855 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7856 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7857 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7858 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7859 | aud_config = VLV_AUD_CFG(pipe); | |
7860 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7861 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7862 | } else { |
9b138a83 WX |
7863 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7864 | aud_config = CPT_AUD_CFG(pipe); | |
7865 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7866 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7867 | } |
7868 | ||
9b138a83 | 7869 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7870 | |
9ca2fe73 ML |
7871 | if (IS_VALLEYVIEW(connector->dev)) { |
7872 | struct intel_encoder *intel_encoder; | |
7873 | struct intel_digital_port *intel_dig_port; | |
7874 | ||
7875 | intel_encoder = intel_attached_encoder(connector); | |
7876 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7877 | i = intel_dig_port->port; | |
7878 | } else { | |
7879 | i = I915_READ(aud_cntl_st); | |
7880 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7881 | /* DIP_Port_Select, 0x1 = PortB */ | |
7882 | } | |
7883 | ||
e0dac65e WF |
7884 | if (!i) { |
7885 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7886 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7887 | eldv = IBX_ELD_VALIDB; |
7888 | eldv |= IBX_ELD_VALIDB << 4; | |
7889 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7890 | } else { |
2582a850 | 7891 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7892 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7893 | } |
7894 | ||
3a9627f4 WF |
7895 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7896 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7897 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7898 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7899 | } else { |
7900 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7901 | } | |
e0dac65e | 7902 | |
3a9627f4 WF |
7903 | if (intel_eld_uptodate(connector, |
7904 | aud_cntrl_st2, eldv, | |
7905 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7906 | hdmiw_hdmiedid)) | |
7907 | return; | |
7908 | ||
e0dac65e WF |
7909 | i = I915_READ(aud_cntrl_st2); |
7910 | i &= ~eldv; | |
7911 | I915_WRITE(aud_cntrl_st2, i); | |
7912 | ||
7913 | if (!eld[0]) | |
7914 | return; | |
7915 | ||
e0dac65e | 7916 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7917 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7918 | I915_WRITE(aud_cntl_st, i); |
7919 | ||
7920 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7921 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7922 | for (i = 0; i < len; i++) | |
7923 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7924 | ||
7925 | i = I915_READ(aud_cntrl_st2); | |
7926 | i |= eldv; | |
7927 | I915_WRITE(aud_cntrl_st2, i); | |
7928 | } | |
7929 | ||
7930 | void intel_write_eld(struct drm_encoder *encoder, | |
7931 | struct drm_display_mode *mode) | |
7932 | { | |
7933 | struct drm_crtc *crtc = encoder->crtc; | |
7934 | struct drm_connector *connector; | |
7935 | struct drm_device *dev = encoder->dev; | |
7936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7937 | ||
7938 | connector = drm_select_eld(encoder, mode); | |
7939 | if (!connector) | |
7940 | return; | |
7941 | ||
7942 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7943 | connector->base.id, | |
c23cc417 | 7944 | connector->name, |
e0dac65e | 7945 | connector->encoder->base.id, |
8e329a03 | 7946 | connector->encoder->name); |
e0dac65e WF |
7947 | |
7948 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7949 | ||
7950 | if (dev_priv->display.write_eld) | |
34427052 | 7951 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7952 | } |
7953 | ||
560b85bb CW |
7954 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7955 | { | |
7956 | struct drm_device *dev = crtc->dev; | |
7957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4b0e333e | 7959 | uint32_t cntl; |
560b85bb | 7960 | |
4b0e333e | 7961 | if (base != intel_crtc->cursor_base) { |
560b85bb CW |
7962 | /* On these chipsets we can only modify the base whilst |
7963 | * the cursor is disabled. | |
7964 | */ | |
4b0e333e CW |
7965 | if (intel_crtc->cursor_cntl) { |
7966 | I915_WRITE(_CURACNTR, 0); | |
7967 | POSTING_READ(_CURACNTR); | |
7968 | intel_crtc->cursor_cntl = 0; | |
7969 | } | |
7970 | ||
9db4a9c7 | 7971 | I915_WRITE(_CURABASE, base); |
4b0e333e CW |
7972 | POSTING_READ(_CURABASE); |
7973 | } | |
560b85bb | 7974 | |
4b0e333e CW |
7975 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
7976 | cntl = 0; | |
7977 | if (base) | |
7978 | cntl = (CURSOR_ENABLE | | |
560b85bb | 7979 | CURSOR_GAMMA_ENABLE | |
4b0e333e CW |
7980 | CURSOR_FORMAT_ARGB); |
7981 | if (intel_crtc->cursor_cntl != cntl) { | |
7982 | I915_WRITE(_CURACNTR, cntl); | |
7983 | POSTING_READ(_CURACNTR); | |
7984 | intel_crtc->cursor_cntl = cntl; | |
7985 | } | |
560b85bb CW |
7986 | } |
7987 | ||
7988 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7989 | { | |
7990 | struct drm_device *dev = crtc->dev; | |
7991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7993 | int pipe = intel_crtc->pipe; | |
4b0e333e | 7994 | uint32_t cntl; |
4726e0b0 | 7995 | |
4b0e333e CW |
7996 | cntl = 0; |
7997 | if (base) { | |
7998 | cntl = MCURSOR_GAMMA_ENABLE; | |
7999 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8000 | case 64: |
8001 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8002 | break; | |
8003 | case 128: | |
8004 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8005 | break; | |
8006 | case 256: | |
8007 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8008 | break; | |
8009 | default: | |
8010 | WARN_ON(1); | |
8011 | return; | |
560b85bb | 8012 | } |
4b0e333e CW |
8013 | cntl |= pipe << 28; /* Connect to correct pipe */ |
8014 | } | |
8015 | if (intel_crtc->cursor_cntl != cntl) { | |
9db4a9c7 | 8016 | I915_WRITE(CURCNTR(pipe), cntl); |
4b0e333e CW |
8017 | POSTING_READ(CURCNTR(pipe)); |
8018 | intel_crtc->cursor_cntl = cntl; | |
560b85bb | 8019 | } |
4b0e333e | 8020 | |
560b85bb | 8021 | /* and commit changes on next vblank */ |
9db4a9c7 | 8022 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 8023 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
8024 | } |
8025 | ||
65a21cd6 JB |
8026 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8027 | { | |
8028 | struct drm_device *dev = crtc->dev; | |
8029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8031 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8032 | uint32_t cntl; |
8033 | ||
8034 | cntl = 0; | |
8035 | if (base) { | |
8036 | cntl = MCURSOR_GAMMA_ENABLE; | |
8037 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8038 | case 64: |
8039 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8040 | break; | |
8041 | case 128: | |
8042 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8043 | break; | |
8044 | case 256: | |
8045 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8046 | break; | |
8047 | default: | |
8048 | WARN_ON(1); | |
8049 | return; | |
65a21cd6 | 8050 | } |
4b0e333e CW |
8051 | } |
8052 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8053 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8054 | |
4b0e333e CW |
8055 | if (intel_crtc->cursor_cntl != cntl) { |
8056 | I915_WRITE(CURCNTR(pipe), cntl); | |
8057 | POSTING_READ(CURCNTR(pipe)); | |
8058 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8059 | } |
4b0e333e | 8060 | |
65a21cd6 | 8061 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8062 | I915_WRITE(CURBASE(pipe), base); |
8063 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8064 | } |
8065 | ||
cda4b7d3 | 8066 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8067 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8068 | bool on) | |
cda4b7d3 CW |
8069 | { |
8070 | struct drm_device *dev = crtc->dev; | |
8071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8073 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8074 | int x = crtc->cursor_x; |
8075 | int y = crtc->cursor_y; | |
d6e4db15 | 8076 | u32 base = 0, pos = 0; |
cda4b7d3 | 8077 | |
d6e4db15 | 8078 | if (on) |
cda4b7d3 | 8079 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8080 | |
d6e4db15 VS |
8081 | if (x >= intel_crtc->config.pipe_src_w) |
8082 | base = 0; | |
8083 | ||
8084 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8085 | base = 0; |
8086 | ||
8087 | if (x < 0) { | |
efc9064e | 8088 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8089 | base = 0; |
8090 | ||
8091 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8092 | x = -x; | |
8093 | } | |
8094 | pos |= x << CURSOR_X_SHIFT; | |
8095 | ||
8096 | if (y < 0) { | |
efc9064e | 8097 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8098 | base = 0; |
8099 | ||
8100 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8101 | y = -y; | |
8102 | } | |
8103 | pos |= y << CURSOR_Y_SHIFT; | |
8104 | ||
4b0e333e | 8105 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8106 | return; |
8107 | ||
5efb3e28 VS |
8108 | I915_WRITE(CURPOS(pipe), pos); |
8109 | ||
8110 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8111 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8112 | else if (IS_845G(dev) || IS_I865G(dev)) |
8113 | i845_update_cursor(crtc, base); | |
8114 | else | |
8115 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8116 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8117 | } |
8118 | ||
e3287951 MR |
8119 | /* |
8120 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8121 | * | |
8122 | * Note that the object's reference will be consumed if the update fails. If | |
8123 | * the update succeeds, the reference of the old object (if any) will be | |
8124 | * consumed. | |
8125 | */ | |
8126 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8127 | struct drm_i915_gem_object *obj, | |
8128 | uint32_t width, uint32_t height) | |
79e53945 JB |
8129 | { |
8130 | struct drm_device *dev = crtc->dev; | |
8131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a071fa00 | 8133 | enum pipe pipe = intel_crtc->pipe; |
64f962e3 | 8134 | unsigned old_width; |
cda4b7d3 | 8135 | uint32_t addr; |
3f8bc370 | 8136 | int ret; |
79e53945 | 8137 | |
79e53945 | 8138 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8139 | if (!obj) { |
28c97730 | 8140 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8141 | addr = 0; |
05394f39 | 8142 | obj = NULL; |
5004417d | 8143 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8144 | goto finish; |
79e53945 JB |
8145 | } |
8146 | ||
4726e0b0 SK |
8147 | /* Check for which cursor types we support */ |
8148 | if (!((width == 64 && height == 64) || | |
8149 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8150 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8151 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8152 | return -EINVAL; |
8153 | } | |
8154 | ||
05394f39 | 8155 | if (obj->base.size < width * height * 4) { |
e3287951 | 8156 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8157 | ret = -ENOMEM; |
8158 | goto fail; | |
79e53945 JB |
8159 | } |
8160 | ||
71acb5eb | 8161 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8162 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8163 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8164 | unsigned alignment; |
8165 | ||
d9e86c0e | 8166 | if (obj->tiling_mode) { |
3b25b31f | 8167 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8168 | ret = -EINVAL; |
8169 | goto fail_locked; | |
8170 | } | |
8171 | ||
693db184 CW |
8172 | /* Note that the w/a also requires 2 PTE of padding following |
8173 | * the bo. We currently fill all unused PTE with the shadow | |
8174 | * page and so we should always have valid PTE following the | |
8175 | * cursor preventing the VT-d warning. | |
8176 | */ | |
8177 | alignment = 0; | |
8178 | if (need_vtd_wa(dev)) | |
8179 | alignment = 64*1024; | |
8180 | ||
8181 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8182 | if (ret) { |
3b25b31f | 8183 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8184 | goto fail_locked; |
e7b526bb CW |
8185 | } |
8186 | ||
d9e86c0e CW |
8187 | ret = i915_gem_object_put_fence(obj); |
8188 | if (ret) { | |
3b25b31f | 8189 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8190 | goto fail_unpin; |
8191 | } | |
8192 | ||
f343c5f6 | 8193 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8194 | } else { |
6eeefaf3 | 8195 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8196 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8197 | if (ret) { |
3b25b31f | 8198 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8199 | goto fail_locked; |
71acb5eb | 8200 | } |
00731155 | 8201 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8202 | } |
8203 | ||
a6c45cf0 | 8204 | if (IS_GEN2(dev)) |
14b60391 JB |
8205 | I915_WRITE(CURSIZE, (height << 12) | width); |
8206 | ||
3f8bc370 | 8207 | finish: |
3f8bc370 | 8208 | if (intel_crtc->cursor_bo) { |
00731155 | 8209 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8210 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8211 | } |
80824003 | 8212 | |
a071fa00 DV |
8213 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8214 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8215 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8216 | |
64f962e3 CW |
8217 | old_width = intel_crtc->cursor_width; |
8218 | ||
3f8bc370 | 8219 | intel_crtc->cursor_addr = addr; |
05394f39 | 8220 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8221 | intel_crtc->cursor_width = width; |
8222 | intel_crtc->cursor_height = height; | |
8223 | ||
64f962e3 CW |
8224 | if (intel_crtc->active) { |
8225 | if (old_width != width) | |
8226 | intel_update_watermarks(crtc); | |
f2f5f771 | 8227 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8228 | } |
3f8bc370 | 8229 | |
f99d7069 DV |
8230 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8231 | ||
79e53945 | 8232 | return 0; |
e7b526bb | 8233 | fail_unpin: |
cc98b413 | 8234 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8235 | fail_locked: |
34b8686e | 8236 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8237 | fail: |
05394f39 | 8238 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8239 | return ret; |
79e53945 JB |
8240 | } |
8241 | ||
79e53945 | 8242 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8243 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8244 | { |
7203425a | 8245 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8246 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8247 | |
7203425a | 8248 | for (i = start; i < end; i++) { |
79e53945 JB |
8249 | intel_crtc->lut_r[i] = red[i] >> 8; |
8250 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8251 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8252 | } | |
8253 | ||
8254 | intel_crtc_load_lut(crtc); | |
8255 | } | |
8256 | ||
79e53945 JB |
8257 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8258 | static struct drm_display_mode load_detect_mode = { | |
8259 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8260 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8261 | }; | |
8262 | ||
a8bb6818 DV |
8263 | struct drm_framebuffer * |
8264 | __intel_framebuffer_create(struct drm_device *dev, | |
8265 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8266 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8267 | { |
8268 | struct intel_framebuffer *intel_fb; | |
8269 | int ret; | |
8270 | ||
8271 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8272 | if (!intel_fb) { | |
8273 | drm_gem_object_unreference_unlocked(&obj->base); | |
8274 | return ERR_PTR(-ENOMEM); | |
8275 | } | |
8276 | ||
8277 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8278 | if (ret) |
8279 | goto err; | |
d2dff872 CW |
8280 | |
8281 | return &intel_fb->base; | |
dd4916c5 DV |
8282 | err: |
8283 | drm_gem_object_unreference_unlocked(&obj->base); | |
8284 | kfree(intel_fb); | |
8285 | ||
8286 | return ERR_PTR(ret); | |
d2dff872 CW |
8287 | } |
8288 | ||
b5ea642a | 8289 | static struct drm_framebuffer * |
a8bb6818 DV |
8290 | intel_framebuffer_create(struct drm_device *dev, |
8291 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8292 | struct drm_i915_gem_object *obj) | |
8293 | { | |
8294 | struct drm_framebuffer *fb; | |
8295 | int ret; | |
8296 | ||
8297 | ret = i915_mutex_lock_interruptible(dev); | |
8298 | if (ret) | |
8299 | return ERR_PTR(ret); | |
8300 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8301 | mutex_unlock(&dev->struct_mutex); | |
8302 | ||
8303 | return fb; | |
8304 | } | |
8305 | ||
d2dff872 CW |
8306 | static u32 |
8307 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8308 | { | |
8309 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8310 | return ALIGN(pitch, 64); | |
8311 | } | |
8312 | ||
8313 | static u32 | |
8314 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8315 | { | |
8316 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8317 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8318 | } |
8319 | ||
8320 | static struct drm_framebuffer * | |
8321 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8322 | struct drm_display_mode *mode, | |
8323 | int depth, int bpp) | |
8324 | { | |
8325 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8326 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8327 | |
8328 | obj = i915_gem_alloc_object(dev, | |
8329 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8330 | if (obj == NULL) | |
8331 | return ERR_PTR(-ENOMEM); | |
8332 | ||
8333 | mode_cmd.width = mode->hdisplay; | |
8334 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8335 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8336 | bpp); | |
5ca0c34a | 8337 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8338 | |
8339 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8340 | } | |
8341 | ||
8342 | static struct drm_framebuffer * | |
8343 | mode_fits_in_fbdev(struct drm_device *dev, | |
8344 | struct drm_display_mode *mode) | |
8345 | { | |
4520f53a | 8346 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8347 | struct drm_i915_private *dev_priv = dev->dev_private; |
8348 | struct drm_i915_gem_object *obj; | |
8349 | struct drm_framebuffer *fb; | |
8350 | ||
4c0e5528 | 8351 | if (!dev_priv->fbdev) |
d2dff872 CW |
8352 | return NULL; |
8353 | ||
4c0e5528 | 8354 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8355 | return NULL; |
8356 | ||
4c0e5528 DV |
8357 | obj = dev_priv->fbdev->fb->obj; |
8358 | BUG_ON(!obj); | |
8359 | ||
8bcd4553 | 8360 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8361 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8362 | fb->bits_per_pixel)) | |
d2dff872 CW |
8363 | return NULL; |
8364 | ||
01f2c773 | 8365 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8366 | return NULL; |
8367 | ||
8368 | return fb; | |
4520f53a DV |
8369 | #else |
8370 | return NULL; | |
8371 | #endif | |
d2dff872 CW |
8372 | } |
8373 | ||
d2434ab7 | 8374 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8375 | struct drm_display_mode *mode, |
51fd371b RC |
8376 | struct intel_load_detect_pipe *old, |
8377 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8378 | { |
8379 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8380 | struct intel_encoder *intel_encoder = |
8381 | intel_attached_encoder(connector); | |
79e53945 | 8382 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8383 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8384 | struct drm_crtc *crtc = NULL; |
8385 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8386 | struct drm_framebuffer *fb; |
51fd371b RC |
8387 | struct drm_mode_config *config = &dev->mode_config; |
8388 | int ret, i = -1; | |
79e53945 | 8389 | |
d2dff872 | 8390 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8391 | connector->base.id, connector->name, |
8e329a03 | 8392 | encoder->base.id, encoder->name); |
d2dff872 | 8393 | |
51fd371b RC |
8394 | drm_modeset_acquire_init(ctx, 0); |
8395 | ||
8396 | retry: | |
8397 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8398 | if (ret) | |
8399 | goto fail_unlock; | |
6e9f798d | 8400 | |
79e53945 JB |
8401 | /* |
8402 | * Algorithm gets a little messy: | |
7a5e4805 | 8403 | * |
79e53945 JB |
8404 | * - if the connector already has an assigned crtc, use it (but make |
8405 | * sure it's on first) | |
7a5e4805 | 8406 | * |
79e53945 JB |
8407 | * - try to find the first unused crtc that can drive this connector, |
8408 | * and use that if we find one | |
79e53945 JB |
8409 | */ |
8410 | ||
8411 | /* See if we already have a CRTC for this connector */ | |
8412 | if (encoder->crtc) { | |
8413 | crtc = encoder->crtc; | |
8261b191 | 8414 | |
51fd371b RC |
8415 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8416 | if (ret) | |
8417 | goto fail_unlock; | |
7b24056b | 8418 | |
24218aac | 8419 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8420 | old->load_detect_temp = false; |
8421 | ||
8422 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8423 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8424 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8425 | |
7173188d | 8426 | return true; |
79e53945 JB |
8427 | } |
8428 | ||
8429 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8430 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8431 | i++; |
8432 | if (!(encoder->possible_crtcs & (1 << i))) | |
8433 | continue; | |
8434 | if (!possible_crtc->enabled) { | |
8435 | crtc = possible_crtc; | |
8436 | break; | |
8437 | } | |
79e53945 JB |
8438 | } |
8439 | ||
8440 | /* | |
8441 | * If we didn't find an unused CRTC, don't use any. | |
8442 | */ | |
8443 | if (!crtc) { | |
7173188d | 8444 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8445 | goto fail_unlock; |
79e53945 JB |
8446 | } |
8447 | ||
51fd371b RC |
8448 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8449 | if (ret) | |
8450 | goto fail_unlock; | |
fc303101 DV |
8451 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8452 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8453 | |
8454 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8455 | intel_crtc->new_enabled = true; |
8456 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8457 | old->dpms_mode = connector->dpms; |
8261b191 | 8458 | old->load_detect_temp = true; |
d2dff872 | 8459 | old->release_fb = NULL; |
79e53945 | 8460 | |
6492711d CW |
8461 | if (!mode) |
8462 | mode = &load_detect_mode; | |
79e53945 | 8463 | |
d2dff872 CW |
8464 | /* We need a framebuffer large enough to accommodate all accesses |
8465 | * that the plane may generate whilst we perform load detection. | |
8466 | * We can not rely on the fbcon either being present (we get called | |
8467 | * during its initialisation to detect all boot displays, or it may | |
8468 | * not even exist) or that it is large enough to satisfy the | |
8469 | * requested mode. | |
8470 | */ | |
94352cf9 DV |
8471 | fb = mode_fits_in_fbdev(dev, mode); |
8472 | if (fb == NULL) { | |
d2dff872 | 8473 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8474 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8475 | old->release_fb = fb; | |
d2dff872 CW |
8476 | } else |
8477 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8478 | if (IS_ERR(fb)) { |
d2dff872 | 8479 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8480 | goto fail; |
79e53945 | 8481 | } |
79e53945 | 8482 | |
c0c36b94 | 8483 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8484 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8485 | if (old->release_fb) |
8486 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8487 | goto fail; |
79e53945 | 8488 | } |
7173188d | 8489 | |
79e53945 | 8490 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8491 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8492 | return true; |
412b61d8 VS |
8493 | |
8494 | fail: | |
8495 | intel_crtc->new_enabled = crtc->enabled; | |
8496 | if (intel_crtc->new_enabled) | |
8497 | intel_crtc->new_config = &intel_crtc->config; | |
8498 | else | |
8499 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8500 | fail_unlock: |
8501 | if (ret == -EDEADLK) { | |
8502 | drm_modeset_backoff(ctx); | |
8503 | goto retry; | |
8504 | } | |
8505 | ||
8506 | drm_modeset_drop_locks(ctx); | |
8507 | drm_modeset_acquire_fini(ctx); | |
6e9f798d | 8508 | |
412b61d8 | 8509 | return false; |
79e53945 JB |
8510 | } |
8511 | ||
d2434ab7 | 8512 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
51fd371b RC |
8513 | struct intel_load_detect_pipe *old, |
8514 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 8515 | { |
d2434ab7 DV |
8516 | struct intel_encoder *intel_encoder = |
8517 | intel_attached_encoder(connector); | |
4ef69c7a | 8518 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8519 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8521 | |
d2dff872 | 8522 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8523 | connector->base.id, connector->name, |
8e329a03 | 8524 | encoder->base.id, encoder->name); |
d2dff872 | 8525 | |
8261b191 | 8526 | if (old->load_detect_temp) { |
fc303101 DV |
8527 | to_intel_connector(connector)->new_encoder = NULL; |
8528 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8529 | intel_crtc->new_enabled = false; |
8530 | intel_crtc->new_config = NULL; | |
fc303101 | 8531 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8532 | |
36206361 DV |
8533 | if (old->release_fb) { |
8534 | drm_framebuffer_unregister_private(old->release_fb); | |
8535 | drm_framebuffer_unreference(old->release_fb); | |
8536 | } | |
d2dff872 | 8537 | |
51fd371b | 8538 | goto unlock; |
0622a53c | 8539 | return; |
79e53945 JB |
8540 | } |
8541 | ||
c751ce4f | 8542 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8543 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8544 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b | 8545 | |
51fd371b RC |
8546 | unlock: |
8547 | drm_modeset_drop_locks(ctx); | |
8548 | drm_modeset_acquire_fini(ctx); | |
79e53945 JB |
8549 | } |
8550 | ||
da4a1efa VS |
8551 | static int i9xx_pll_refclk(struct drm_device *dev, |
8552 | const struct intel_crtc_config *pipe_config) | |
8553 | { | |
8554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8555 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8556 | ||
8557 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8558 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8559 | else if (HAS_PCH_SPLIT(dev)) |
8560 | return 120000; | |
8561 | else if (!IS_GEN2(dev)) | |
8562 | return 96000; | |
8563 | else | |
8564 | return 48000; | |
8565 | } | |
8566 | ||
79e53945 | 8567 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8568 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8569 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8570 | { |
f1f644dc | 8571 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8572 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8573 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8574 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8575 | u32 fp; |
8576 | intel_clock_t clock; | |
da4a1efa | 8577 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8578 | |
8579 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8580 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8581 | else |
293623f7 | 8582 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8583 | |
8584 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8585 | if (IS_PINEVIEW(dev)) { |
8586 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8587 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8588 | } else { |
8589 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8590 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8591 | } | |
8592 | ||
a6c45cf0 | 8593 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8594 | if (IS_PINEVIEW(dev)) |
8595 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8596 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8597 | else |
8598 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8599 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8600 | ||
8601 | switch (dpll & DPLL_MODE_MASK) { | |
8602 | case DPLLB_MODE_DAC_SERIAL: | |
8603 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8604 | 5 : 10; | |
8605 | break; | |
8606 | case DPLLB_MODE_LVDS: | |
8607 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8608 | 7 : 14; | |
8609 | break; | |
8610 | default: | |
28c97730 | 8611 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8612 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8613 | return; |
79e53945 JB |
8614 | } |
8615 | ||
ac58c3f0 | 8616 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8617 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8618 | else |
da4a1efa | 8619 | i9xx_clock(refclk, &clock); |
79e53945 | 8620 | } else { |
0fb58223 | 8621 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8622 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8623 | |
8624 | if (is_lvds) { | |
8625 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8626 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8627 | |
8628 | if (lvds & LVDS_CLKB_POWER_UP) | |
8629 | clock.p2 = 7; | |
8630 | else | |
8631 | clock.p2 = 14; | |
79e53945 JB |
8632 | } else { |
8633 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8634 | clock.p1 = 2; | |
8635 | else { | |
8636 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8637 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8638 | } | |
8639 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8640 | clock.p2 = 4; | |
8641 | else | |
8642 | clock.p2 = 2; | |
79e53945 | 8643 | } |
da4a1efa VS |
8644 | |
8645 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8646 | } |
8647 | ||
18442d08 VS |
8648 | /* |
8649 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8650 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8651 | * encoder's get_config() function. |
8652 | */ | |
8653 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8654 | } |
8655 | ||
6878da05 VS |
8656 | int intel_dotclock_calculate(int link_freq, |
8657 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8658 | { |
f1f644dc JB |
8659 | /* |
8660 | * The calculation for the data clock is: | |
1041a02f | 8661 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8662 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8663 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8664 | * |
8665 | * and the link clock is simpler: | |
1041a02f | 8666 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8667 | */ |
8668 | ||
6878da05 VS |
8669 | if (!m_n->link_n) |
8670 | return 0; | |
f1f644dc | 8671 | |
6878da05 VS |
8672 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8673 | } | |
f1f644dc | 8674 | |
18442d08 VS |
8675 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8676 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8677 | { |
8678 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8679 | |
18442d08 VS |
8680 | /* read out port_clock from the DPLL */ |
8681 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8682 | |
f1f644dc | 8683 | /* |
18442d08 | 8684 | * This value does not include pixel_multiplier. |
241bfc38 | 8685 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8686 | * agree once we know their relationship in the encoder's |
8687 | * get_config() function. | |
79e53945 | 8688 | */ |
241bfc38 | 8689 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8690 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8691 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8692 | } |
8693 | ||
8694 | /** Returns the currently programmed mode of the given pipe. */ | |
8695 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8696 | struct drm_crtc *crtc) | |
8697 | { | |
548f245b | 8698 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8700 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8701 | struct drm_display_mode *mode; |
f1f644dc | 8702 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8703 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8704 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8705 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8706 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8707 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8708 | |
8709 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8710 | if (!mode) | |
8711 | return NULL; | |
8712 | ||
f1f644dc JB |
8713 | /* |
8714 | * Construct a pipe_config sufficient for getting the clock info | |
8715 | * back out of crtc_clock_get. | |
8716 | * | |
8717 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8718 | * to use a real value here instead. | |
8719 | */ | |
293623f7 | 8720 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8721 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8722 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8723 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8724 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8725 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8726 | ||
773ae034 | 8727 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8728 | mode->hdisplay = (htot & 0xffff) + 1; |
8729 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8730 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8731 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8732 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8733 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8734 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8735 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8736 | ||
8737 | drm_mode_set_name(mode); | |
79e53945 JB |
8738 | |
8739 | return mode; | |
8740 | } | |
8741 | ||
cc36513c DV |
8742 | static void intel_increase_pllclock(struct drm_device *dev, |
8743 | enum pipe pipe) | |
652c393a | 8744 | { |
fbee40df | 8745 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
8746 | int dpll_reg = DPLL(pipe); |
8747 | int dpll; | |
652c393a | 8748 | |
bad720ff | 8749 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8750 | return; |
8751 | ||
8752 | if (!dev_priv->lvds_downclock_avail) | |
8753 | return; | |
8754 | ||
dbdc6479 | 8755 | dpll = I915_READ(dpll_reg); |
652c393a | 8756 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8757 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8758 | |
8ac5a6d5 | 8759 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8760 | |
8761 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8762 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8763 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8764 | |
652c393a JB |
8765 | dpll = I915_READ(dpll_reg); |
8766 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8767 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8768 | } |
652c393a JB |
8769 | } |
8770 | ||
8771 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8772 | { | |
8773 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8774 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8776 | |
bad720ff | 8777 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8778 | return; |
8779 | ||
8780 | if (!dev_priv->lvds_downclock_avail) | |
8781 | return; | |
8782 | ||
8783 | /* | |
8784 | * Since this is called by a timer, we should never get here in | |
8785 | * the manual case. | |
8786 | */ | |
8787 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8788 | int pipe = intel_crtc->pipe; |
8789 | int dpll_reg = DPLL(pipe); | |
8790 | int dpll; | |
f6e5b160 | 8791 | |
44d98a61 | 8792 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8793 | |
8ac5a6d5 | 8794 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8795 | |
dc257cf1 | 8796 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8797 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8798 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8799 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8800 | dpll = I915_READ(dpll_reg); |
8801 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8802 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8803 | } |
8804 | ||
8805 | } | |
8806 | ||
f047e395 CW |
8807 | void intel_mark_busy(struct drm_device *dev) |
8808 | { | |
c67a470b PZ |
8809 | struct drm_i915_private *dev_priv = dev->dev_private; |
8810 | ||
f62a0076 CW |
8811 | if (dev_priv->mm.busy) |
8812 | return; | |
8813 | ||
43694d69 | 8814 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8815 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8816 | dev_priv->mm.busy = true; |
f047e395 CW |
8817 | } |
8818 | ||
8819 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8820 | { |
c67a470b | 8821 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8822 | struct drm_crtc *crtc; |
652c393a | 8823 | |
f62a0076 CW |
8824 | if (!dev_priv->mm.busy) |
8825 | return; | |
8826 | ||
8827 | dev_priv->mm.busy = false; | |
8828 | ||
d330a953 | 8829 | if (!i915.powersave) |
bb4cdd53 | 8830 | goto out; |
652c393a | 8831 | |
70e1e0ec | 8832 | for_each_crtc(dev, crtc) { |
f4510a27 | 8833 | if (!crtc->primary->fb) |
652c393a JB |
8834 | continue; |
8835 | ||
725a5b54 | 8836 | intel_decrease_pllclock(crtc); |
652c393a | 8837 | } |
b29c19b6 | 8838 | |
3d13ef2e | 8839 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8840 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8841 | |
8842 | out: | |
43694d69 | 8843 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8844 | } |
8845 | ||
7c8f8a70 | 8846 | |
f99d7069 DV |
8847 | /** |
8848 | * intel_mark_fb_busy - mark given planes as busy | |
8849 | * @dev: DRM device | |
8850 | * @frontbuffer_bits: bits for the affected planes | |
8851 | * @ring: optional ring for asynchronous commands | |
8852 | * | |
8853 | * This function gets called every time the screen contents change. It can be | |
8854 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
8855 | */ | |
8856 | static void intel_mark_fb_busy(struct drm_device *dev, | |
8857 | unsigned frontbuffer_bits, | |
8858 | struct intel_engine_cs *ring) | |
652c393a | 8859 | { |
cc36513c | 8860 | enum pipe pipe; |
652c393a | 8861 | |
d330a953 | 8862 | if (!i915.powersave) |
acb87dfb CW |
8863 | return; |
8864 | ||
cc36513c | 8865 | for_each_pipe(pipe) { |
f99d7069 | 8866 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
8867 | continue; |
8868 | ||
cc36513c | 8869 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
8870 | if (ring && intel_fbc_enabled(dev)) |
8871 | ring->fbc_dirty = true; | |
652c393a JB |
8872 | } |
8873 | } | |
8874 | ||
f99d7069 DV |
8875 | /** |
8876 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
8877 | * @obj: GEM object to invalidate | |
8878 | * @ring: set for asynchronous rendering | |
8879 | * | |
8880 | * This function gets called every time rendering on the given object starts and | |
8881 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
8882 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
8883 | * until the rendering completes or a flip on this frontbuffer plane is | |
8884 | * scheduled. | |
8885 | */ | |
8886 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
8887 | struct intel_engine_cs *ring) | |
8888 | { | |
8889 | struct drm_device *dev = obj->base.dev; | |
8890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8891 | ||
8892 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
8893 | ||
8894 | if (!obj->frontbuffer_bits) | |
8895 | return; | |
8896 | ||
8897 | if (ring) { | |
8898 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8899 | dev_priv->fb_tracking.busy_bits | |
8900 | |= obj->frontbuffer_bits; | |
8901 | dev_priv->fb_tracking.flip_bits | |
8902 | &= ~obj->frontbuffer_bits; | |
8903 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8904 | } | |
8905 | ||
8906 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
8907 | ||
8908 | intel_edp_psr_exit(dev); | |
8909 | } | |
8910 | ||
8911 | /** | |
8912 | * intel_frontbuffer_flush - flush frontbuffer | |
8913 | * @dev: DRM device | |
8914 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
8915 | * | |
8916 | * This function gets called every time rendering on the given planes has | |
8917 | * completed and frontbuffer caching can be started again. Flushes will get | |
8918 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
8919 | * | |
8920 | * Can be called without any locks held. | |
8921 | */ | |
8922 | void intel_frontbuffer_flush(struct drm_device *dev, | |
8923 | unsigned frontbuffer_bits) | |
8924 | { | |
8925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8926 | ||
8927 | /* Delay flushing when rings are still busy.*/ | |
8928 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8929 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
8930 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8931 | ||
8932 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
8933 | ||
8934 | intel_edp_psr_exit(dev); | |
8935 | } | |
8936 | ||
8937 | /** | |
8938 | * intel_fb_obj_flush - flush frontbuffer object | |
8939 | * @obj: GEM object to flush | |
8940 | * @retire: set when retiring asynchronous rendering | |
8941 | * | |
8942 | * This function gets called every time rendering on the given object has | |
8943 | * completed and frontbuffer caching can be started again. If @retire is true | |
8944 | * then any delayed flushes will be unblocked. | |
8945 | */ | |
8946 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
8947 | bool retire) | |
8948 | { | |
8949 | struct drm_device *dev = obj->base.dev; | |
8950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8951 | unsigned frontbuffer_bits; | |
8952 | ||
8953 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
8954 | ||
8955 | if (!obj->frontbuffer_bits) | |
8956 | return; | |
8957 | ||
8958 | frontbuffer_bits = obj->frontbuffer_bits; | |
8959 | ||
8960 | if (retire) { | |
8961 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8962 | /* Filter out new bits since rendering started. */ | |
8963 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
8964 | ||
8965 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
8966 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8967 | } | |
8968 | ||
8969 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
8970 | } | |
8971 | ||
8972 | /** | |
8973 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
8974 | * @dev: DRM device | |
8975 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
8976 | * | |
8977 | * This function gets called after scheduling a flip on @obj. The actual | |
8978 | * frontbuffer flushing will be delayed until completion is signalled with | |
8979 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
8980 | * flush will be cancelled. | |
8981 | * | |
8982 | * Can be called without any locks held. | |
8983 | */ | |
8984 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
8985 | unsigned frontbuffer_bits) | |
8986 | { | |
8987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8988 | ||
8989 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8990 | dev_priv->fb_tracking.flip_bits | |
8991 | |= frontbuffer_bits; | |
8992 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8993 | } | |
8994 | ||
8995 | /** | |
8996 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
8997 | * @dev: DRM device | |
8998 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
8999 | * | |
9000 | * This function gets called after the flip has been latched and will complete | |
9001 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9002 | * | |
9003 | * Can be called without any locks held. | |
9004 | */ | |
9005 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9006 | unsigned frontbuffer_bits) | |
9007 | { | |
9008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9009 | ||
9010 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9011 | /* Mask any cancelled flips. */ | |
9012 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9013 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9014 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9015 | ||
9016 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9017 | } | |
9018 | ||
79e53945 JB |
9019 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9020 | { | |
9021 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9022 | struct drm_device *dev = crtc->dev; |
9023 | struct intel_unpin_work *work; | |
9024 | unsigned long flags; | |
9025 | ||
9026 | spin_lock_irqsave(&dev->event_lock, flags); | |
9027 | work = intel_crtc->unpin_work; | |
9028 | intel_crtc->unpin_work = NULL; | |
9029 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9030 | ||
9031 | if (work) { | |
9032 | cancel_work_sync(&work->work); | |
9033 | kfree(work); | |
9034 | } | |
79e53945 JB |
9035 | |
9036 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9037 | |
79e53945 JB |
9038 | kfree(intel_crtc); |
9039 | } | |
9040 | ||
6b95a207 KH |
9041 | static void intel_unpin_work_fn(struct work_struct *__work) |
9042 | { | |
9043 | struct intel_unpin_work *work = | |
9044 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9045 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9046 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9047 | |
b4a98e57 | 9048 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9049 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9050 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9051 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9052 | |
b4a98e57 CW |
9053 | intel_update_fbc(dev); |
9054 | mutex_unlock(&dev->struct_mutex); | |
9055 | ||
f99d7069 DV |
9056 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9057 | ||
b4a98e57 CW |
9058 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9059 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9060 | ||
6b95a207 KH |
9061 | kfree(work); |
9062 | } | |
9063 | ||
1afe3e9d | 9064 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9065 | struct drm_crtc *crtc) |
6b95a207 | 9066 | { |
fbee40df | 9067 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9069 | struct intel_unpin_work *work; | |
6b95a207 KH |
9070 | unsigned long flags; |
9071 | ||
9072 | /* Ignore early vblank irqs */ | |
9073 | if (intel_crtc == NULL) | |
9074 | return; | |
9075 | ||
9076 | spin_lock_irqsave(&dev->event_lock, flags); | |
9077 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9078 | |
9079 | /* Ensure we don't miss a work->pending update ... */ | |
9080 | smp_rmb(); | |
9081 | ||
9082 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9083 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9084 | return; | |
9085 | } | |
9086 | ||
e7d841ca CW |
9087 | /* and that the unpin work is consistent wrt ->pending. */ |
9088 | smp_rmb(); | |
9089 | ||
6b95a207 | 9090 | intel_crtc->unpin_work = NULL; |
6b95a207 | 9091 | |
45a066eb RC |
9092 | if (work->event) |
9093 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 9094 | |
87b6b101 | 9095 | drm_crtc_vblank_put(crtc); |
0af7e4df | 9096 | |
6b95a207 KH |
9097 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9098 | ||
2c10d571 | 9099 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
9100 | |
9101 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
9102 | |
9103 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
9104 | } |
9105 | ||
1afe3e9d JB |
9106 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9107 | { | |
fbee40df | 9108 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9109 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9110 | ||
49b14a5c | 9111 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9112 | } |
9113 | ||
9114 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9115 | { | |
fbee40df | 9116 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9117 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9118 | ||
49b14a5c | 9119 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9120 | } |
9121 | ||
75f7f3ec VS |
9122 | /* Is 'a' after or equal to 'b'? */ |
9123 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9124 | { | |
9125 | return !((a - b) & 0x80000000); | |
9126 | } | |
9127 | ||
9128 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9129 | { | |
9130 | struct drm_device *dev = crtc->base.dev; | |
9131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9132 | ||
9133 | /* | |
9134 | * The relevant registers doen't exist on pre-ctg. | |
9135 | * As the flip done interrupt doesn't trigger for mmio | |
9136 | * flips on gmch platforms, a flip count check isn't | |
9137 | * really needed there. But since ctg has the registers, | |
9138 | * include it in the check anyway. | |
9139 | */ | |
9140 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9141 | return true; | |
9142 | ||
9143 | /* | |
9144 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9145 | * used the same base address. In that case the mmio flip might | |
9146 | * have completed, but the CS hasn't even executed the flip yet. | |
9147 | * | |
9148 | * A flip count check isn't enough as the CS might have updated | |
9149 | * the base address just after start of vblank, but before we | |
9150 | * managed to process the interrupt. This means we'd complete the | |
9151 | * CS flip too soon. | |
9152 | * | |
9153 | * Combining both checks should get us a good enough result. It may | |
9154 | * still happen that the CS flip has been executed, but has not | |
9155 | * yet actually completed. But in case the base address is the same | |
9156 | * anyway, we don't really care. | |
9157 | */ | |
9158 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9159 | crtc->unpin_work->gtt_offset && | |
9160 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9161 | crtc->unpin_work->flip_count); | |
9162 | } | |
9163 | ||
6b95a207 KH |
9164 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9165 | { | |
fbee40df | 9166 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9167 | struct intel_crtc *intel_crtc = |
9168 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9169 | unsigned long flags; | |
9170 | ||
e7d841ca CW |
9171 | /* NB: An MMIO update of the plane base pointer will also |
9172 | * generate a page-flip completion irq, i.e. every modeset | |
9173 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9174 | */ | |
6b95a207 | 9175 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9176 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9177 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9178 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9179 | } | |
9180 | ||
eba905b2 | 9181 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9182 | { |
9183 | /* Ensure that the work item is consistent when activating it ... */ | |
9184 | smp_wmb(); | |
9185 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9186 | /* and that it is marked active as soon as the irq could fire. */ | |
9187 | smp_wmb(); | |
9188 | } | |
9189 | ||
8c9f3aaf JB |
9190 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9191 | struct drm_crtc *crtc, | |
9192 | struct drm_framebuffer *fb, | |
ed8d1975 | 9193 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9194 | struct intel_engine_cs *ring, |
ed8d1975 | 9195 | uint32_t flags) |
8c9f3aaf | 9196 | { |
8c9f3aaf | 9197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9198 | u32 flip_mask; |
9199 | int ret; | |
9200 | ||
6d90c952 | 9201 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9202 | if (ret) |
4fa62c89 | 9203 | return ret; |
8c9f3aaf JB |
9204 | |
9205 | /* Can't queue multiple flips, so wait for the previous | |
9206 | * one to finish before executing the next. | |
9207 | */ | |
9208 | if (intel_crtc->plane) | |
9209 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9210 | else | |
9211 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9212 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9213 | intel_ring_emit(ring, MI_NOOP); | |
9214 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9215 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9216 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9217 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9218 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9219 | |
9220 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9221 | __intel_ring_advance(ring); |
83d4092b | 9222 | return 0; |
8c9f3aaf JB |
9223 | } |
9224 | ||
9225 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9226 | struct drm_crtc *crtc, | |
9227 | struct drm_framebuffer *fb, | |
ed8d1975 | 9228 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9229 | struct intel_engine_cs *ring, |
ed8d1975 | 9230 | uint32_t flags) |
8c9f3aaf | 9231 | { |
8c9f3aaf | 9232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9233 | u32 flip_mask; |
9234 | int ret; | |
9235 | ||
6d90c952 | 9236 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9237 | if (ret) |
4fa62c89 | 9238 | return ret; |
8c9f3aaf JB |
9239 | |
9240 | if (intel_crtc->plane) | |
9241 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9242 | else | |
9243 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9244 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9245 | intel_ring_emit(ring, MI_NOOP); | |
9246 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9247 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9248 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9249 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9250 | intel_ring_emit(ring, MI_NOOP); |
9251 | ||
e7d841ca | 9252 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9253 | __intel_ring_advance(ring); |
83d4092b | 9254 | return 0; |
8c9f3aaf JB |
9255 | } |
9256 | ||
9257 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9258 | struct drm_crtc *crtc, | |
9259 | struct drm_framebuffer *fb, | |
ed8d1975 | 9260 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9261 | struct intel_engine_cs *ring, |
ed8d1975 | 9262 | uint32_t flags) |
8c9f3aaf JB |
9263 | { |
9264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9266 | uint32_t pf, pipesrc; | |
9267 | int ret; | |
9268 | ||
6d90c952 | 9269 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9270 | if (ret) |
4fa62c89 | 9271 | return ret; |
8c9f3aaf JB |
9272 | |
9273 | /* i965+ uses the linear or tiled offsets from the | |
9274 | * Display Registers (which do not change across a page-flip) | |
9275 | * so we need only reprogram the base address. | |
9276 | */ | |
6d90c952 DV |
9277 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9278 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9279 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9280 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9281 | obj->tiling_mode); |
8c9f3aaf JB |
9282 | |
9283 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9284 | * untested on non-native modes, so ignore it for now. | |
9285 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9286 | */ | |
9287 | pf = 0; | |
9288 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9289 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9290 | |
9291 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9292 | __intel_ring_advance(ring); |
83d4092b | 9293 | return 0; |
8c9f3aaf JB |
9294 | } |
9295 | ||
9296 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9297 | struct drm_crtc *crtc, | |
9298 | struct drm_framebuffer *fb, | |
ed8d1975 | 9299 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9300 | struct intel_engine_cs *ring, |
ed8d1975 | 9301 | uint32_t flags) |
8c9f3aaf JB |
9302 | { |
9303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9305 | uint32_t pf, pipesrc; | |
9306 | int ret; | |
9307 | ||
6d90c952 | 9308 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9309 | if (ret) |
4fa62c89 | 9310 | return ret; |
8c9f3aaf | 9311 | |
6d90c952 DV |
9312 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9313 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9314 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9315 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9316 | |
dc257cf1 DV |
9317 | /* Contrary to the suggestions in the documentation, |
9318 | * "Enable Panel Fitter" does not seem to be required when page | |
9319 | * flipping with a non-native mode, and worse causes a normal | |
9320 | * modeset to fail. | |
9321 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9322 | */ | |
9323 | pf = 0; | |
8c9f3aaf | 9324 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9325 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9326 | |
9327 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9328 | __intel_ring_advance(ring); |
83d4092b | 9329 | return 0; |
8c9f3aaf JB |
9330 | } |
9331 | ||
7c9017e5 JB |
9332 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9333 | struct drm_crtc *crtc, | |
9334 | struct drm_framebuffer *fb, | |
ed8d1975 | 9335 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9336 | struct intel_engine_cs *ring, |
ed8d1975 | 9337 | uint32_t flags) |
7c9017e5 | 9338 | { |
7c9017e5 | 9339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9340 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9341 | int len, ret; |
9342 | ||
eba905b2 | 9343 | switch (intel_crtc->plane) { |
cb05d8de DV |
9344 | case PLANE_A: |
9345 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9346 | break; | |
9347 | case PLANE_B: | |
9348 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9349 | break; | |
9350 | case PLANE_C: | |
9351 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9352 | break; | |
9353 | default: | |
9354 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9355 | return -ENODEV; |
cb05d8de DV |
9356 | } |
9357 | ||
ffe74d75 | 9358 | len = 4; |
f476828a | 9359 | if (ring->id == RCS) { |
ffe74d75 | 9360 | len += 6; |
f476828a DL |
9361 | /* |
9362 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9363 | * 48bits addresses, and we need a NOOP for the batch size to | |
9364 | * stay even. | |
9365 | */ | |
9366 | if (IS_GEN8(dev)) | |
9367 | len += 2; | |
9368 | } | |
ffe74d75 | 9369 | |
f66fab8e VS |
9370 | /* |
9371 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9372 | * "The full packet must be contained within the same cache line." | |
9373 | * | |
9374 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9375 | * cacheline, if we ever start emitting more commands before | |
9376 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9377 | * then do the cacheline alignment, and finally emit the | |
9378 | * MI_DISPLAY_FLIP. | |
9379 | */ | |
9380 | ret = intel_ring_cacheline_align(ring); | |
9381 | if (ret) | |
4fa62c89 | 9382 | return ret; |
f66fab8e | 9383 | |
ffe74d75 | 9384 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9385 | if (ret) |
4fa62c89 | 9386 | return ret; |
7c9017e5 | 9387 | |
ffe74d75 CW |
9388 | /* Unmask the flip-done completion message. Note that the bspec says that |
9389 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9390 | * more than one flip event at any time (or ensure that one flip message | |
9391 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9392 | * Experimentation says that BCS works despite DERRMR masking all | |
9393 | * flip-done completion events and that unmasking all planes at once | |
9394 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9395 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9396 | */ | |
9397 | if (ring->id == RCS) { | |
9398 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9399 | intel_ring_emit(ring, DERRMR); | |
9400 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9401 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9402 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9403 | if (IS_GEN8(dev)) |
9404 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9405 | MI_SRM_LRM_GLOBAL_GTT); | |
9406 | else | |
9407 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9408 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9409 | intel_ring_emit(ring, DERRMR); |
9410 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9411 | if (IS_GEN8(dev)) { |
9412 | intel_ring_emit(ring, 0); | |
9413 | intel_ring_emit(ring, MI_NOOP); | |
9414 | } | |
ffe74d75 CW |
9415 | } |
9416 | ||
cb05d8de | 9417 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9418 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9419 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9420 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9421 | |
9422 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9423 | __intel_ring_advance(ring); |
83d4092b | 9424 | return 0; |
7c9017e5 JB |
9425 | } |
9426 | ||
84c33a64 SG |
9427 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9428 | struct drm_i915_gem_object *obj) | |
9429 | { | |
9430 | /* | |
9431 | * This is not being used for older platforms, because | |
9432 | * non-availability of flip done interrupt forces us to use | |
9433 | * CS flips. Older platforms derive flip done using some clever | |
9434 | * tricks involving the flip_pending status bits and vblank irqs. | |
9435 | * So using MMIO flips there would disrupt this mechanism. | |
9436 | */ | |
9437 | ||
9438 | if (INTEL_INFO(ring->dev)->gen < 5) | |
9439 | return false; | |
9440 | ||
9441 | if (i915.use_mmio_flip < 0) | |
9442 | return false; | |
9443 | else if (i915.use_mmio_flip > 0) | |
9444 | return true; | |
9445 | else | |
9446 | return ring != obj->ring; | |
9447 | } | |
9448 | ||
9449 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9450 | { | |
9451 | struct drm_device *dev = intel_crtc->base.dev; | |
9452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9453 | struct intel_framebuffer *intel_fb = | |
9454 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9455 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9456 | u32 dspcntr; | |
9457 | u32 reg; | |
9458 | ||
9459 | intel_mark_page_flip_active(intel_crtc); | |
9460 | ||
9461 | reg = DSPCNTR(intel_crtc->plane); | |
9462 | dspcntr = I915_READ(reg); | |
9463 | ||
9464 | if (INTEL_INFO(dev)->gen >= 4) { | |
9465 | if (obj->tiling_mode != I915_TILING_NONE) | |
9466 | dspcntr |= DISPPLANE_TILED; | |
9467 | else | |
9468 | dspcntr &= ~DISPPLANE_TILED; | |
9469 | } | |
9470 | I915_WRITE(reg, dspcntr); | |
9471 | ||
9472 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9473 | intel_crtc->unpin_work->gtt_offset); | |
9474 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9475 | } | |
9476 | ||
9477 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9478 | { | |
9479 | struct intel_engine_cs *ring; | |
9480 | int ret; | |
9481 | ||
9482 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9483 | ||
9484 | if (!obj->last_write_seqno) | |
9485 | return 0; | |
9486 | ||
9487 | ring = obj->ring; | |
9488 | ||
9489 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9490 | obj->last_write_seqno)) | |
9491 | return 0; | |
9492 | ||
9493 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9494 | if (ret) | |
9495 | return ret; | |
9496 | ||
9497 | if (WARN_ON(!ring->irq_get(ring))) | |
9498 | return 0; | |
9499 | ||
9500 | return 1; | |
9501 | } | |
9502 | ||
9503 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9504 | { | |
9505 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9506 | struct intel_crtc *intel_crtc; | |
9507 | unsigned long irq_flags; | |
9508 | u32 seqno; | |
9509 | ||
9510 | seqno = ring->get_seqno(ring, false); | |
9511 | ||
9512 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9513 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9514 | struct intel_mmio_flip *mmio_flip; | |
9515 | ||
9516 | mmio_flip = &intel_crtc->mmio_flip; | |
9517 | if (mmio_flip->seqno == 0) | |
9518 | continue; | |
9519 | ||
9520 | if (ring->id != mmio_flip->ring_id) | |
9521 | continue; | |
9522 | ||
9523 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9524 | intel_do_mmio_flip(intel_crtc); | |
9525 | mmio_flip->seqno = 0; | |
9526 | ring->irq_put(ring); | |
9527 | } | |
9528 | } | |
9529 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9530 | } | |
9531 | ||
9532 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9533 | struct drm_crtc *crtc, | |
9534 | struct drm_framebuffer *fb, | |
9535 | struct drm_i915_gem_object *obj, | |
9536 | struct intel_engine_cs *ring, | |
9537 | uint32_t flags) | |
9538 | { | |
9539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9541 | unsigned long irq_flags; | |
9542 | int ret; | |
9543 | ||
9544 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9545 | return -EBUSY; | |
9546 | ||
9547 | ret = intel_postpone_flip(obj); | |
9548 | if (ret < 0) | |
9549 | return ret; | |
9550 | if (ret == 0) { | |
9551 | intel_do_mmio_flip(intel_crtc); | |
9552 | return 0; | |
9553 | } | |
9554 | ||
9555 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9556 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9557 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9558 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9559 | ||
9560 | /* | |
9561 | * Double check to catch cases where irq fired before | |
9562 | * mmio flip data was ready | |
9563 | */ | |
9564 | intel_notify_mmio_flip(obj->ring); | |
9565 | return 0; | |
9566 | } | |
9567 | ||
8c9f3aaf JB |
9568 | static int intel_default_queue_flip(struct drm_device *dev, |
9569 | struct drm_crtc *crtc, | |
9570 | struct drm_framebuffer *fb, | |
ed8d1975 | 9571 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9572 | struct intel_engine_cs *ring, |
ed8d1975 | 9573 | uint32_t flags) |
8c9f3aaf JB |
9574 | { |
9575 | return -ENODEV; | |
9576 | } | |
9577 | ||
6b95a207 KH |
9578 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9579 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9580 | struct drm_pending_vblank_event *event, |
9581 | uint32_t page_flip_flags) | |
6b95a207 KH |
9582 | { |
9583 | struct drm_device *dev = crtc->dev; | |
9584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9585 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9586 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 | 9587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9588 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9589 | struct intel_unpin_work *work; |
a4872ba6 | 9590 | struct intel_engine_cs *ring; |
8c9f3aaf | 9591 | unsigned long flags; |
52e68630 | 9592 | int ret; |
6b95a207 | 9593 | |
e6a595d2 | 9594 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9595 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9596 | return -EINVAL; |
9597 | ||
9598 | /* | |
9599 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9600 | * Note that pitch changes could also affect these register. | |
9601 | */ | |
9602 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9603 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9604 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9605 | return -EINVAL; |
9606 | ||
f900db47 CW |
9607 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9608 | goto out_hang; | |
9609 | ||
b14c5679 | 9610 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9611 | if (work == NULL) |
9612 | return -ENOMEM; | |
9613 | ||
6b95a207 | 9614 | work->event = event; |
b4a98e57 | 9615 | work->crtc = crtc; |
4a35f83b | 9616 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9617 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9618 | ||
87b6b101 | 9619 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9620 | if (ret) |
9621 | goto free_work; | |
9622 | ||
6b95a207 KH |
9623 | /* We borrow the event spin lock for protecting unpin_work */ |
9624 | spin_lock_irqsave(&dev->event_lock, flags); | |
9625 | if (intel_crtc->unpin_work) { | |
9626 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9627 | kfree(work); | |
87b6b101 | 9628 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9629 | |
9630 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9631 | return -EBUSY; |
9632 | } | |
9633 | intel_crtc->unpin_work = work; | |
9634 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9635 | ||
b4a98e57 CW |
9636 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9637 | flush_workqueue(dev_priv->wq); | |
9638 | ||
79158103 CW |
9639 | ret = i915_mutex_lock_interruptible(dev); |
9640 | if (ret) | |
9641 | goto cleanup; | |
6b95a207 | 9642 | |
75dfca80 | 9643 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9644 | drm_gem_object_reference(&work->old_fb_obj->base); |
9645 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9646 | |
f4510a27 | 9647 | crtc->primary->fb = fb; |
96b099fd | 9648 | |
e1f99ce6 | 9649 | work->pending_flip_obj = obj; |
e1f99ce6 | 9650 | |
4e5359cd SF |
9651 | work->enable_stall_check = true; |
9652 | ||
b4a98e57 | 9653 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9654 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9655 | |
75f7f3ec | 9656 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9657 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9658 | |
4fa62c89 VS |
9659 | if (IS_VALLEYVIEW(dev)) { |
9660 | ring = &dev_priv->ring[BCS]; | |
9661 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
9662 | ring = obj->ring; | |
9663 | if (ring == NULL || ring->id != RCS) | |
9664 | ring = &dev_priv->ring[BCS]; | |
9665 | } else { | |
9666 | ring = &dev_priv->ring[RCS]; | |
9667 | } | |
9668 | ||
9669 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9670 | if (ret) |
9671 | goto cleanup_pending; | |
6b95a207 | 9672 | |
4fa62c89 VS |
9673 | work->gtt_offset = |
9674 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9675 | ||
84c33a64 SG |
9676 | if (use_mmio_flip(ring, obj)) |
9677 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, | |
9678 | page_flip_flags); | |
9679 | else | |
9680 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, | |
9681 | page_flip_flags); | |
4fa62c89 VS |
9682 | if (ret) |
9683 | goto cleanup_unpin; | |
9684 | ||
a071fa00 DV |
9685 | i915_gem_track_fb(work->old_fb_obj, obj, |
9686 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9687 | ||
7782de3b | 9688 | intel_disable_fbc(dev); |
f99d7069 | 9689 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9690 | mutex_unlock(&dev->struct_mutex); |
9691 | ||
e5510fac JB |
9692 | trace_i915_flip_request(intel_crtc->plane, obj); |
9693 | ||
6b95a207 | 9694 | return 0; |
96b099fd | 9695 | |
4fa62c89 VS |
9696 | cleanup_unpin: |
9697 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9698 | cleanup_pending: |
b4a98e57 | 9699 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9700 | crtc->primary->fb = old_fb; |
05394f39 CW |
9701 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9702 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9703 | mutex_unlock(&dev->struct_mutex); |
9704 | ||
79158103 | 9705 | cleanup: |
96b099fd CW |
9706 | spin_lock_irqsave(&dev->event_lock, flags); |
9707 | intel_crtc->unpin_work = NULL; | |
9708 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9709 | ||
87b6b101 | 9710 | drm_crtc_vblank_put(crtc); |
7317c75e | 9711 | free_work: |
96b099fd CW |
9712 | kfree(work); |
9713 | ||
f900db47 CW |
9714 | if (ret == -EIO) { |
9715 | out_hang: | |
9716 | intel_crtc_wait_for_pending_flips(crtc); | |
9717 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9718 | if (ret == 0 && event) | |
a071fa00 | 9719 | drm_send_vblank_event(dev, pipe, event); |
f900db47 | 9720 | } |
96b099fd | 9721 | return ret; |
6b95a207 KH |
9722 | } |
9723 | ||
f6e5b160 | 9724 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9725 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9726 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9727 | }; |
9728 | ||
9a935856 DV |
9729 | /** |
9730 | * intel_modeset_update_staged_output_state | |
9731 | * | |
9732 | * Updates the staged output configuration state, e.g. after we've read out the | |
9733 | * current hw state. | |
9734 | */ | |
9735 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9736 | { |
7668851f | 9737 | struct intel_crtc *crtc; |
9a935856 DV |
9738 | struct intel_encoder *encoder; |
9739 | struct intel_connector *connector; | |
f6e5b160 | 9740 | |
9a935856 DV |
9741 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9742 | base.head) { | |
9743 | connector->new_encoder = | |
9744 | to_intel_encoder(connector->base.encoder); | |
9745 | } | |
f6e5b160 | 9746 | |
9a935856 DV |
9747 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9748 | base.head) { | |
9749 | encoder->new_crtc = | |
9750 | to_intel_crtc(encoder->base.crtc); | |
9751 | } | |
7668851f | 9752 | |
d3fcc808 | 9753 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9754 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9755 | |
9756 | if (crtc->new_enabled) | |
9757 | crtc->new_config = &crtc->config; | |
9758 | else | |
9759 | crtc->new_config = NULL; | |
7668851f | 9760 | } |
f6e5b160 CW |
9761 | } |
9762 | ||
9a935856 DV |
9763 | /** |
9764 | * intel_modeset_commit_output_state | |
9765 | * | |
9766 | * This function copies the stage display pipe configuration to the real one. | |
9767 | */ | |
9768 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9769 | { | |
7668851f | 9770 | struct intel_crtc *crtc; |
9a935856 DV |
9771 | struct intel_encoder *encoder; |
9772 | struct intel_connector *connector; | |
f6e5b160 | 9773 | |
9a935856 DV |
9774 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9775 | base.head) { | |
9776 | connector->base.encoder = &connector->new_encoder->base; | |
9777 | } | |
f6e5b160 | 9778 | |
9a935856 DV |
9779 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9780 | base.head) { | |
9781 | encoder->base.crtc = &encoder->new_crtc->base; | |
9782 | } | |
7668851f | 9783 | |
d3fcc808 | 9784 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9785 | crtc->base.enabled = crtc->new_enabled; |
9786 | } | |
9a935856 DV |
9787 | } |
9788 | ||
050f7aeb | 9789 | static void |
eba905b2 | 9790 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9791 | struct intel_crtc_config *pipe_config) |
9792 | { | |
9793 | int bpp = pipe_config->pipe_bpp; | |
9794 | ||
9795 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9796 | connector->base.base.id, | |
c23cc417 | 9797 | connector->base.name); |
050f7aeb DV |
9798 | |
9799 | /* Don't use an invalid EDID bpc value */ | |
9800 | if (connector->base.display_info.bpc && | |
9801 | connector->base.display_info.bpc * 3 < bpp) { | |
9802 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9803 | bpp, connector->base.display_info.bpc*3); | |
9804 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9805 | } | |
9806 | ||
9807 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9808 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9809 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9810 | bpp); | |
9811 | pipe_config->pipe_bpp = 24; | |
9812 | } | |
9813 | } | |
9814 | ||
4e53c2e0 | 9815 | static int |
050f7aeb DV |
9816 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9817 | struct drm_framebuffer *fb, | |
9818 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9819 | { |
050f7aeb DV |
9820 | struct drm_device *dev = crtc->base.dev; |
9821 | struct intel_connector *connector; | |
4e53c2e0 DV |
9822 | int bpp; |
9823 | ||
d42264b1 DV |
9824 | switch (fb->pixel_format) { |
9825 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9826 | bpp = 8*3; /* since we go through a colormap */ |
9827 | break; | |
d42264b1 DV |
9828 | case DRM_FORMAT_XRGB1555: |
9829 | case DRM_FORMAT_ARGB1555: | |
9830 | /* checked in intel_framebuffer_init already */ | |
9831 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9832 | return -EINVAL; | |
9833 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9834 | bpp = 6*3; /* min is 18bpp */ |
9835 | break; | |
d42264b1 DV |
9836 | case DRM_FORMAT_XBGR8888: |
9837 | case DRM_FORMAT_ABGR8888: | |
9838 | /* checked in intel_framebuffer_init already */ | |
9839 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9840 | return -EINVAL; | |
9841 | case DRM_FORMAT_XRGB8888: | |
9842 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9843 | bpp = 8*3; |
9844 | break; | |
d42264b1 DV |
9845 | case DRM_FORMAT_XRGB2101010: |
9846 | case DRM_FORMAT_ARGB2101010: | |
9847 | case DRM_FORMAT_XBGR2101010: | |
9848 | case DRM_FORMAT_ABGR2101010: | |
9849 | /* checked in intel_framebuffer_init already */ | |
9850 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9851 | return -EINVAL; |
4e53c2e0 DV |
9852 | bpp = 10*3; |
9853 | break; | |
baba133a | 9854 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9855 | default: |
9856 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9857 | return -EINVAL; | |
9858 | } | |
9859 | ||
4e53c2e0 DV |
9860 | pipe_config->pipe_bpp = bpp; |
9861 | ||
9862 | /* Clamp display bpp to EDID value */ | |
9863 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9864 | base.head) { |
1b829e05 DV |
9865 | if (!connector->new_encoder || |
9866 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9867 | continue; |
9868 | ||
050f7aeb | 9869 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9870 | } |
9871 | ||
9872 | return bpp; | |
9873 | } | |
9874 | ||
644db711 DV |
9875 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9876 | { | |
9877 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9878 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9879 | mode->crtc_clock, |
644db711 DV |
9880 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9881 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9882 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9883 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9884 | } | |
9885 | ||
c0b03411 DV |
9886 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9887 | struct intel_crtc_config *pipe_config, | |
9888 | const char *context) | |
9889 | { | |
9890 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9891 | context, pipe_name(crtc->pipe)); | |
9892 | ||
9893 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9894 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9895 | pipe_config->pipe_bpp, pipe_config->dither); | |
9896 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9897 | pipe_config->has_pch_encoder, | |
9898 | pipe_config->fdi_lanes, | |
9899 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9900 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9901 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9902 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9903 | pipe_config->has_dp_encoder, | |
9904 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9905 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9906 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9907 | DRM_DEBUG_KMS("requested mode:\n"); |
9908 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9909 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9910 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9911 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9912 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9913 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9914 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9915 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9916 | pipe_config->gmch_pfit.control, | |
9917 | pipe_config->gmch_pfit.pgm_ratios, | |
9918 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9919 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9920 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9921 | pipe_config->pch_pfit.size, |
9922 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9923 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9924 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9925 | } |
9926 | ||
bc079e8b VS |
9927 | static bool encoders_cloneable(const struct intel_encoder *a, |
9928 | const struct intel_encoder *b) | |
accfc0c5 | 9929 | { |
bc079e8b VS |
9930 | /* masks could be asymmetric, so check both ways */ |
9931 | return a == b || (a->cloneable & (1 << b->type) && | |
9932 | b->cloneable & (1 << a->type)); | |
9933 | } | |
9934 | ||
9935 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9936 | struct intel_encoder *encoder) | |
9937 | { | |
9938 | struct drm_device *dev = crtc->base.dev; | |
9939 | struct intel_encoder *source_encoder; | |
9940 | ||
9941 | list_for_each_entry(source_encoder, | |
9942 | &dev->mode_config.encoder_list, base.head) { | |
9943 | if (source_encoder->new_crtc != crtc) | |
9944 | continue; | |
9945 | ||
9946 | if (!encoders_cloneable(encoder, source_encoder)) | |
9947 | return false; | |
9948 | } | |
9949 | ||
9950 | return true; | |
9951 | } | |
9952 | ||
9953 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9954 | { | |
9955 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9956 | struct intel_encoder *encoder; |
9957 | ||
bc079e8b VS |
9958 | list_for_each_entry(encoder, |
9959 | &dev->mode_config.encoder_list, base.head) { | |
9960 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9961 | continue; |
9962 | ||
bc079e8b VS |
9963 | if (!check_single_encoder_cloning(crtc, encoder)) |
9964 | return false; | |
accfc0c5 DV |
9965 | } |
9966 | ||
bc079e8b | 9967 | return true; |
accfc0c5 DV |
9968 | } |
9969 | ||
b8cecdf5 DV |
9970 | static struct intel_crtc_config * |
9971 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9972 | struct drm_framebuffer *fb, |
b8cecdf5 | 9973 | struct drm_display_mode *mode) |
ee7b9f93 | 9974 | { |
7758a113 | 9975 | struct drm_device *dev = crtc->dev; |
7758a113 | 9976 | struct intel_encoder *encoder; |
b8cecdf5 | 9977 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9978 | int plane_bpp, ret = -EINVAL; |
9979 | bool retry = true; | |
ee7b9f93 | 9980 | |
bc079e8b | 9981 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9982 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9983 | return ERR_PTR(-EINVAL); | |
9984 | } | |
9985 | ||
b8cecdf5 DV |
9986 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9987 | if (!pipe_config) | |
7758a113 DV |
9988 | return ERR_PTR(-ENOMEM); |
9989 | ||
b8cecdf5 DV |
9990 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9991 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9992 | |
e143a21c DV |
9993 | pipe_config->cpu_transcoder = |
9994 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9995 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9996 | |
2960bc9c ID |
9997 | /* |
9998 | * Sanitize sync polarity flags based on requested ones. If neither | |
9999 | * positive or negative polarity is requested, treat this as meaning | |
10000 | * negative polarity. | |
10001 | */ | |
10002 | if (!(pipe_config->adjusted_mode.flags & | |
10003 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10004 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10005 | ||
10006 | if (!(pipe_config->adjusted_mode.flags & | |
10007 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10008 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10009 | ||
050f7aeb DV |
10010 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10011 | * plane pixel format and any sink constraints into account. Returns the | |
10012 | * source plane bpp so that dithering can be selected on mismatches | |
10013 | * after encoders and crtc also have had their say. */ | |
10014 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10015 | fb, pipe_config); | |
4e53c2e0 DV |
10016 | if (plane_bpp < 0) |
10017 | goto fail; | |
10018 | ||
e41a56be VS |
10019 | /* |
10020 | * Determine the real pipe dimensions. Note that stereo modes can | |
10021 | * increase the actual pipe size due to the frame doubling and | |
10022 | * insertion of additional space for blanks between the frame. This | |
10023 | * is stored in the crtc timings. We use the requested mode to do this | |
10024 | * computation to clearly distinguish it from the adjusted mode, which | |
10025 | * can be changed by the connectors in the below retry loop. | |
10026 | */ | |
10027 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10028 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10029 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10030 | ||
e29c22c0 | 10031 | encoder_retry: |
ef1b460d | 10032 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10033 | pipe_config->port_clock = 0; |
ef1b460d | 10034 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10035 | |
135c81b8 | 10036 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10037 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10038 | |
7758a113 DV |
10039 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10040 | * adjust it according to limitations or connector properties, and also | |
10041 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10042 | */ |
7758a113 DV |
10043 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10044 | base.head) { | |
47f1c6c9 | 10045 | |
7758a113 DV |
10046 | if (&encoder->new_crtc->base != crtc) |
10047 | continue; | |
7ae89233 | 10048 | |
efea6e8e DV |
10049 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10050 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10051 | goto fail; |
10052 | } | |
ee7b9f93 | 10053 | } |
47f1c6c9 | 10054 | |
ff9a6750 DV |
10055 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10056 | * done afterwards in case the encoder adjusts the mode. */ | |
10057 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10058 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10059 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10060 | |
a43f6e0f | 10061 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10062 | if (ret < 0) { |
7758a113 DV |
10063 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10064 | goto fail; | |
ee7b9f93 | 10065 | } |
e29c22c0 DV |
10066 | |
10067 | if (ret == RETRY) { | |
10068 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10069 | ret = -EINVAL; | |
10070 | goto fail; | |
10071 | } | |
10072 | ||
10073 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10074 | retry = false; | |
10075 | goto encoder_retry; | |
10076 | } | |
10077 | ||
4e53c2e0 DV |
10078 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10079 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10080 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10081 | ||
b8cecdf5 | 10082 | return pipe_config; |
7758a113 | 10083 | fail: |
b8cecdf5 | 10084 | kfree(pipe_config); |
e29c22c0 | 10085 | return ERR_PTR(ret); |
ee7b9f93 | 10086 | } |
47f1c6c9 | 10087 | |
e2e1ed41 DV |
10088 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10089 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10090 | static void | |
10091 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10092 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10093 | { |
10094 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10095 | struct drm_device *dev = crtc->dev; |
10096 | struct intel_encoder *encoder; | |
10097 | struct intel_connector *connector; | |
10098 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10099 | |
e2e1ed41 | 10100 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10101 | |
e2e1ed41 DV |
10102 | /* Check which crtcs have changed outputs connected to them, these need |
10103 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10104 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10105 | * bit set at most. */ | |
10106 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10107 | base.head) { | |
10108 | if (connector->base.encoder == &connector->new_encoder->base) | |
10109 | continue; | |
79e53945 | 10110 | |
e2e1ed41 DV |
10111 | if (connector->base.encoder) { |
10112 | tmp_crtc = connector->base.encoder->crtc; | |
10113 | ||
10114 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10115 | } | |
10116 | ||
10117 | if (connector->new_encoder) | |
10118 | *prepare_pipes |= | |
10119 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10120 | } |
10121 | ||
e2e1ed41 DV |
10122 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10123 | base.head) { | |
10124 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
10125 | continue; | |
10126 | ||
10127 | if (encoder->base.crtc) { | |
10128 | tmp_crtc = encoder->base.crtc; | |
10129 | ||
10130 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10131 | } | |
10132 | ||
10133 | if (encoder->new_crtc) | |
10134 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10135 | } |
10136 | ||
7668851f | 10137 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10138 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10139 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10140 | continue; |
7e7d76c3 | 10141 | |
7668851f | 10142 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10143 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10144 | else |
10145 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10146 | } |
10147 | ||
e2e1ed41 DV |
10148 | |
10149 | /* set_mode is also used to update properties on life display pipes. */ | |
10150 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10151 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10152 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10153 | ||
b6c5164d DV |
10154 | /* |
10155 | * For simplicity do a full modeset on any pipe where the output routing | |
10156 | * changed. We could be more clever, but that would require us to be | |
10157 | * more careful with calling the relevant encoder->mode_set functions. | |
10158 | */ | |
e2e1ed41 DV |
10159 | if (*prepare_pipes) |
10160 | *modeset_pipes = *prepare_pipes; | |
10161 | ||
10162 | /* ... and mask these out. */ | |
10163 | *modeset_pipes &= ~(*disable_pipes); | |
10164 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10165 | |
10166 | /* | |
10167 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10168 | * obies this rule, but the modeset restore mode of | |
10169 | * intel_modeset_setup_hw_state does not. | |
10170 | */ | |
10171 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10172 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10173 | |
10174 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10175 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10176 | } |
79e53945 | 10177 | |
ea9d758d | 10178 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10179 | { |
ea9d758d | 10180 | struct drm_encoder *encoder; |
f6e5b160 | 10181 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10182 | |
ea9d758d DV |
10183 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10184 | if (encoder->crtc == crtc) | |
10185 | return true; | |
10186 | ||
10187 | return false; | |
10188 | } | |
10189 | ||
10190 | static void | |
10191 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10192 | { | |
10193 | struct intel_encoder *intel_encoder; | |
10194 | struct intel_crtc *intel_crtc; | |
10195 | struct drm_connector *connector; | |
10196 | ||
10197 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
10198 | base.head) { | |
10199 | if (!intel_encoder->base.crtc) | |
10200 | continue; | |
10201 | ||
10202 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10203 | ||
10204 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10205 | intel_encoder->connectors_active = false; | |
10206 | } | |
10207 | ||
10208 | intel_modeset_commit_output_state(dev); | |
10209 | ||
7668851f | 10210 | /* Double check state. */ |
d3fcc808 | 10211 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10212 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10213 | WARN_ON(intel_crtc->new_config && |
10214 | intel_crtc->new_config != &intel_crtc->config); | |
10215 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10216 | } |
10217 | ||
10218 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10219 | if (!connector->encoder || !connector->encoder->crtc) | |
10220 | continue; | |
10221 | ||
10222 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10223 | ||
10224 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10225 | struct drm_property *dpms_property = |
10226 | dev->mode_config.dpms_property; | |
10227 | ||
ea9d758d | 10228 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10229 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10230 | dpms_property, |
10231 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10232 | |
10233 | intel_encoder = to_intel_encoder(connector->encoder); | |
10234 | intel_encoder->connectors_active = true; | |
10235 | } | |
10236 | } | |
10237 | ||
10238 | } | |
10239 | ||
3bd26263 | 10240 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10241 | { |
3bd26263 | 10242 | int diff; |
f1f644dc JB |
10243 | |
10244 | if (clock1 == clock2) | |
10245 | return true; | |
10246 | ||
10247 | if (!clock1 || !clock2) | |
10248 | return false; | |
10249 | ||
10250 | diff = abs(clock1 - clock2); | |
10251 | ||
10252 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10253 | return true; | |
10254 | ||
10255 | return false; | |
10256 | } | |
10257 | ||
25c5b266 DV |
10258 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10259 | list_for_each_entry((intel_crtc), \ | |
10260 | &(dev)->mode_config.crtc_list, \ | |
10261 | base.head) \ | |
0973f18f | 10262 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10263 | |
0e8ffe1b | 10264 | static bool |
2fa2fe9a DV |
10265 | intel_pipe_config_compare(struct drm_device *dev, |
10266 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10267 | struct intel_crtc_config *pipe_config) |
10268 | { | |
66e985c0 DV |
10269 | #define PIPE_CONF_CHECK_X(name) \ |
10270 | if (current_config->name != pipe_config->name) { \ | |
10271 | DRM_ERROR("mismatch in " #name " " \ | |
10272 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10273 | current_config->name, \ | |
10274 | pipe_config->name); \ | |
10275 | return false; \ | |
10276 | } | |
10277 | ||
08a24034 DV |
10278 | #define PIPE_CONF_CHECK_I(name) \ |
10279 | if (current_config->name != pipe_config->name) { \ | |
10280 | DRM_ERROR("mismatch in " #name " " \ | |
10281 | "(expected %i, found %i)\n", \ | |
10282 | current_config->name, \ | |
10283 | pipe_config->name); \ | |
10284 | return false; \ | |
88adfff1 DV |
10285 | } |
10286 | ||
1bd1bd80 DV |
10287 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10288 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10289 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10290 | "(expected %i, found %i)\n", \ |
10291 | current_config->name & (mask), \ | |
10292 | pipe_config->name & (mask)); \ | |
10293 | return false; \ | |
10294 | } | |
10295 | ||
5e550656 VS |
10296 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10297 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10298 | DRM_ERROR("mismatch in " #name " " \ | |
10299 | "(expected %i, found %i)\n", \ | |
10300 | current_config->name, \ | |
10301 | pipe_config->name); \ | |
10302 | return false; \ | |
10303 | } | |
10304 | ||
bb760063 DV |
10305 | #define PIPE_CONF_QUIRK(quirk) \ |
10306 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10307 | ||
eccb140b DV |
10308 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10309 | ||
08a24034 DV |
10310 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10311 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10312 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10313 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10314 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10315 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10316 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10317 | |
eb14cb74 VS |
10318 | PIPE_CONF_CHECK_I(has_dp_encoder); |
10319 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10320 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10321 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10322 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10323 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10324 | ||
1bd1bd80 DV |
10325 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10326 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10327 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10328 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10329 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10330 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10331 | ||
10332 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10333 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10334 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10335 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10336 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10337 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10338 | ||
c93f54cf | 10339 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10340 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10341 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10342 | IS_VALLEYVIEW(dev)) | |
10343 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10344 | |
9ed109a7 DV |
10345 | PIPE_CONF_CHECK_I(has_audio); |
10346 | ||
1bd1bd80 DV |
10347 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10348 | DRM_MODE_FLAG_INTERLACE); | |
10349 | ||
bb760063 DV |
10350 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10351 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10352 | DRM_MODE_FLAG_PHSYNC); | |
10353 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10354 | DRM_MODE_FLAG_NHSYNC); | |
10355 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10356 | DRM_MODE_FLAG_PVSYNC); | |
10357 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10358 | DRM_MODE_FLAG_NVSYNC); | |
10359 | } | |
045ac3b5 | 10360 | |
37327abd VS |
10361 | PIPE_CONF_CHECK_I(pipe_src_w); |
10362 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10363 | |
9953599b DV |
10364 | /* |
10365 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10366 | * screen. Since we don't yet re-compute the pipe config when moving | |
10367 | * just the lvds port away to another pipe the sw tracking won't match. | |
10368 | * | |
10369 | * Proper atomic modesets with recomputed global state will fix this. | |
10370 | * Until then just don't check gmch state for inherited modes. | |
10371 | */ | |
10372 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10373 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10374 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10375 | if (INTEL_INFO(dev)->gen < 4) | |
10376 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10377 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10378 | } | |
10379 | ||
fd4daa9c CW |
10380 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10381 | if (current_config->pch_pfit.enabled) { | |
10382 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10383 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10384 | } | |
2fa2fe9a | 10385 | |
e59150dc JB |
10386 | /* BDW+ don't expose a synchronous way to read the state */ |
10387 | if (IS_HASWELL(dev)) | |
10388 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10389 | |
282740f7 VS |
10390 | PIPE_CONF_CHECK_I(double_wide); |
10391 | ||
c0d43d62 | 10392 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10393 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10394 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10395 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10396 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 10397 | |
42571aef VS |
10398 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10399 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10400 | ||
a9a7e98a JB |
10401 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10402 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10403 | |
66e985c0 | 10404 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10405 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 10406 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10407 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10408 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10409 | |
0e8ffe1b DV |
10410 | return true; |
10411 | } | |
10412 | ||
91d1b4bd DV |
10413 | static void |
10414 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10415 | { |
8af6cf88 DV |
10416 | struct intel_connector *connector; |
10417 | ||
10418 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10419 | base.head) { | |
10420 | /* This also checks the encoder/connector hw state with the | |
10421 | * ->get_hw_state callbacks. */ | |
10422 | intel_connector_check_state(connector); | |
10423 | ||
10424 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10425 | "connector's staged encoder doesn't match current encoder\n"); | |
10426 | } | |
91d1b4bd DV |
10427 | } |
10428 | ||
10429 | static void | |
10430 | check_encoder_state(struct drm_device *dev) | |
10431 | { | |
10432 | struct intel_encoder *encoder; | |
10433 | struct intel_connector *connector; | |
8af6cf88 DV |
10434 | |
10435 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10436 | base.head) { | |
10437 | bool enabled = false; | |
10438 | bool active = false; | |
10439 | enum pipe pipe, tracked_pipe; | |
10440 | ||
10441 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10442 | encoder->base.base.id, | |
8e329a03 | 10443 | encoder->base.name); |
8af6cf88 DV |
10444 | |
10445 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10446 | "encoder's stage crtc doesn't match current crtc\n"); | |
10447 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10448 | "encoder's active_connectors set, but no crtc\n"); | |
10449 | ||
10450 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10451 | base.head) { | |
10452 | if (connector->base.encoder != &encoder->base) | |
10453 | continue; | |
10454 | enabled = true; | |
10455 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10456 | active = true; | |
10457 | } | |
10458 | WARN(!!encoder->base.crtc != enabled, | |
10459 | "encoder's enabled state mismatch " | |
10460 | "(expected %i, found %i)\n", | |
10461 | !!encoder->base.crtc, enabled); | |
10462 | WARN(active && !encoder->base.crtc, | |
10463 | "active encoder with no crtc\n"); | |
10464 | ||
10465 | WARN(encoder->connectors_active != active, | |
10466 | "encoder's computed active state doesn't match tracked active state " | |
10467 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10468 | ||
10469 | active = encoder->get_hw_state(encoder, &pipe); | |
10470 | WARN(active != encoder->connectors_active, | |
10471 | "encoder's hw state doesn't match sw tracking " | |
10472 | "(expected %i, found %i)\n", | |
10473 | encoder->connectors_active, active); | |
10474 | ||
10475 | if (!encoder->base.crtc) | |
10476 | continue; | |
10477 | ||
10478 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10479 | WARN(active && pipe != tracked_pipe, | |
10480 | "active encoder's pipe doesn't match" | |
10481 | "(expected %i, found %i)\n", | |
10482 | tracked_pipe, pipe); | |
10483 | ||
10484 | } | |
91d1b4bd DV |
10485 | } |
10486 | ||
10487 | static void | |
10488 | check_crtc_state(struct drm_device *dev) | |
10489 | { | |
fbee40df | 10490 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10491 | struct intel_crtc *crtc; |
10492 | struct intel_encoder *encoder; | |
10493 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10494 | |
d3fcc808 | 10495 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10496 | bool enabled = false; |
10497 | bool active = false; | |
10498 | ||
045ac3b5 JB |
10499 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10500 | ||
8af6cf88 DV |
10501 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10502 | crtc->base.base.id); | |
10503 | ||
10504 | WARN(crtc->active && !crtc->base.enabled, | |
10505 | "active crtc, but not enabled in sw tracking\n"); | |
10506 | ||
10507 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10508 | base.head) { | |
10509 | if (encoder->base.crtc != &crtc->base) | |
10510 | continue; | |
10511 | enabled = true; | |
10512 | if (encoder->connectors_active) | |
10513 | active = true; | |
10514 | } | |
6c49f241 | 10515 | |
8af6cf88 DV |
10516 | WARN(active != crtc->active, |
10517 | "crtc's computed active state doesn't match tracked active state " | |
10518 | "(expected %i, found %i)\n", active, crtc->active); | |
10519 | WARN(enabled != crtc->base.enabled, | |
10520 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10521 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10522 | ||
0e8ffe1b DV |
10523 | active = dev_priv->display.get_pipe_config(crtc, |
10524 | &pipe_config); | |
d62cf62a DV |
10525 | |
10526 | /* hw state is inconsistent with the pipe A quirk */ | |
10527 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10528 | active = crtc->active; | |
10529 | ||
6c49f241 DV |
10530 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10531 | base.head) { | |
3eaba51c | 10532 | enum pipe pipe; |
6c49f241 DV |
10533 | if (encoder->base.crtc != &crtc->base) |
10534 | continue; | |
1d37b689 | 10535 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10536 | encoder->get_config(encoder, &pipe_config); |
10537 | } | |
10538 | ||
0e8ffe1b DV |
10539 | WARN(crtc->active != active, |
10540 | "crtc active state doesn't match with hw state " | |
10541 | "(expected %i, found %i)\n", crtc->active, active); | |
10542 | ||
c0b03411 DV |
10543 | if (active && |
10544 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10545 | WARN(1, "pipe state doesn't match!\n"); | |
10546 | intel_dump_pipe_config(crtc, &pipe_config, | |
10547 | "[hw state]"); | |
10548 | intel_dump_pipe_config(crtc, &crtc->config, | |
10549 | "[sw state]"); | |
10550 | } | |
8af6cf88 DV |
10551 | } |
10552 | } | |
10553 | ||
91d1b4bd DV |
10554 | static void |
10555 | check_shared_dpll_state(struct drm_device *dev) | |
10556 | { | |
fbee40df | 10557 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10558 | struct intel_crtc *crtc; |
10559 | struct intel_dpll_hw_state dpll_hw_state; | |
10560 | int i; | |
5358901f DV |
10561 | |
10562 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10563 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10564 | int enabled_crtcs = 0, active_crtcs = 0; | |
10565 | bool active; | |
10566 | ||
10567 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10568 | ||
10569 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10570 | ||
10571 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10572 | ||
10573 | WARN(pll->active > pll->refcount, | |
10574 | "more active pll users than references: %i vs %i\n", | |
10575 | pll->active, pll->refcount); | |
10576 | WARN(pll->active && !pll->on, | |
10577 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10578 | WARN(pll->on && !pll->active, |
10579 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10580 | WARN(pll->on != active, |
10581 | "pll on state mismatch (expected %i, found %i)\n", | |
10582 | pll->on, active); | |
10583 | ||
d3fcc808 | 10584 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10585 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10586 | enabled_crtcs++; | |
10587 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10588 | active_crtcs++; | |
10589 | } | |
10590 | WARN(pll->active != active_crtcs, | |
10591 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10592 | pll->active, active_crtcs); | |
10593 | WARN(pll->refcount != enabled_crtcs, | |
10594 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10595 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10596 | |
10597 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10598 | sizeof(dpll_hw_state)), | |
10599 | "pll hw state mismatch\n"); | |
5358901f | 10600 | } |
8af6cf88 DV |
10601 | } |
10602 | ||
91d1b4bd DV |
10603 | void |
10604 | intel_modeset_check_state(struct drm_device *dev) | |
10605 | { | |
10606 | check_connector_state(dev); | |
10607 | check_encoder_state(dev); | |
10608 | check_crtc_state(dev); | |
10609 | check_shared_dpll_state(dev); | |
10610 | } | |
10611 | ||
18442d08 VS |
10612 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10613 | int dotclock) | |
10614 | { | |
10615 | /* | |
10616 | * FDI already provided one idea for the dotclock. | |
10617 | * Yell if the encoder disagrees. | |
10618 | */ | |
241bfc38 | 10619 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10620 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10621 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10622 | } |
10623 | ||
80715b2f VS |
10624 | static void update_scanline_offset(struct intel_crtc *crtc) |
10625 | { | |
10626 | struct drm_device *dev = crtc->base.dev; | |
10627 | ||
10628 | /* | |
10629 | * The scanline counter increments at the leading edge of hsync. | |
10630 | * | |
10631 | * On most platforms it starts counting from vtotal-1 on the | |
10632 | * first active line. That means the scanline counter value is | |
10633 | * always one less than what we would expect. Ie. just after | |
10634 | * start of vblank, which also occurs at start of hsync (on the | |
10635 | * last active line), the scanline counter will read vblank_start-1. | |
10636 | * | |
10637 | * On gen2 the scanline counter starts counting from 1 instead | |
10638 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10639 | * to keep the value positive), instead of adding one. | |
10640 | * | |
10641 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10642 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10643 | * there's an extra 1 line difference. So we need to add two instead of | |
10644 | * one to the value. | |
10645 | */ | |
10646 | if (IS_GEN2(dev)) { | |
10647 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10648 | int vtotal; | |
10649 | ||
10650 | vtotal = mode->crtc_vtotal; | |
10651 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10652 | vtotal /= 2; | |
10653 | ||
10654 | crtc->scanline_offset = vtotal - 1; | |
10655 | } else if (HAS_DDI(dev) && | |
10656 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10657 | crtc->scanline_offset = 2; | |
10658 | } else | |
10659 | crtc->scanline_offset = 1; | |
10660 | } | |
10661 | ||
f30da187 DV |
10662 | static int __intel_set_mode(struct drm_crtc *crtc, |
10663 | struct drm_display_mode *mode, | |
10664 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10665 | { |
10666 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10667 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10668 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10669 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10670 | struct intel_crtc *intel_crtc; |
10671 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10672 | int ret = 0; |
a6778b3c | 10673 | |
4b4b9238 | 10674 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10675 | if (!saved_mode) |
10676 | return -ENOMEM; | |
a6778b3c | 10677 | |
e2e1ed41 | 10678 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10679 | &prepare_pipes, &disable_pipes); |
10680 | ||
3ac18232 | 10681 | *saved_mode = crtc->mode; |
a6778b3c | 10682 | |
25c5b266 DV |
10683 | /* Hack: Because we don't (yet) support global modeset on multiple |
10684 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10685 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10686 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10687 | * changing their mode at the same time. */ | |
25c5b266 | 10688 | if (modeset_pipes) { |
4e53c2e0 | 10689 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10690 | if (IS_ERR(pipe_config)) { |
10691 | ret = PTR_ERR(pipe_config); | |
10692 | pipe_config = NULL; | |
10693 | ||
3ac18232 | 10694 | goto out; |
25c5b266 | 10695 | } |
c0b03411 DV |
10696 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10697 | "[modeset]"); | |
50741abc | 10698 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10699 | } |
a6778b3c | 10700 | |
30a970c6 JB |
10701 | /* |
10702 | * See if the config requires any additional preparation, e.g. | |
10703 | * to adjust global state with pipes off. We need to do this | |
10704 | * here so we can get the modeset_pipe updated config for the new | |
10705 | * mode set on this crtc. For other crtcs we need to use the | |
10706 | * adjusted_mode bits in the crtc directly. | |
10707 | */ | |
c164f833 | 10708 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10709 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10710 | |
c164f833 VS |
10711 | /* may have added more to prepare_pipes than we should */ |
10712 | prepare_pipes &= ~disable_pipes; | |
10713 | } | |
10714 | ||
460da916 DV |
10715 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10716 | intel_crtc_disable(&intel_crtc->base); | |
10717 | ||
ea9d758d DV |
10718 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10719 | if (intel_crtc->base.enabled) | |
10720 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10721 | } | |
a6778b3c | 10722 | |
6c4c86f5 DV |
10723 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10724 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10725 | */ |
b8cecdf5 | 10726 | if (modeset_pipes) { |
25c5b266 | 10727 | crtc->mode = *mode; |
b8cecdf5 DV |
10728 | /* mode_set/enable/disable functions rely on a correct pipe |
10729 | * config. */ | |
10730 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10731 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10732 | |
10733 | /* | |
10734 | * Calculate and store various constants which | |
10735 | * are later needed by vblank and swap-completion | |
10736 | * timestamping. They are derived from true hwmode. | |
10737 | */ | |
10738 | drm_calc_timestamping_constants(crtc, | |
10739 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10740 | } |
7758a113 | 10741 | |
ea9d758d DV |
10742 | /* Only after disabling all output pipelines that will be changed can we |
10743 | * update the the output configuration. */ | |
10744 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10745 | |
47fab737 DV |
10746 | if (dev_priv->display.modeset_global_resources) |
10747 | dev_priv->display.modeset_global_resources(dev); | |
10748 | ||
a6778b3c DV |
10749 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10750 | * on the DPLL. | |
f6e5b160 | 10751 | */ |
25c5b266 | 10752 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f | 10753 | struct drm_framebuffer *old_fb; |
a071fa00 DV |
10754 | struct drm_i915_gem_object *old_obj = NULL; |
10755 | struct drm_i915_gem_object *obj = | |
10756 | to_intel_framebuffer(fb)->obj; | |
4c10794f DV |
10757 | |
10758 | mutex_lock(&dev->struct_mutex); | |
10759 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 10760 | obj, |
4c10794f DV |
10761 | NULL); |
10762 | if (ret != 0) { | |
10763 | DRM_ERROR("pin & fence failed\n"); | |
10764 | mutex_unlock(&dev->struct_mutex); | |
10765 | goto done; | |
10766 | } | |
10767 | old_fb = crtc->primary->fb; | |
a071fa00 DV |
10768 | if (old_fb) { |
10769 | old_obj = to_intel_framebuffer(old_fb)->obj; | |
10770 | intel_unpin_fb_obj(old_obj); | |
10771 | } | |
10772 | i915_gem_track_fb(old_obj, obj, | |
10773 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
10774 | mutex_unlock(&dev->struct_mutex); |
10775 | ||
10776 | crtc->primary->fb = fb; | |
10777 | crtc->x = x; | |
10778 | crtc->y = y; | |
10779 | ||
4271b753 DV |
10780 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10781 | x, y, fb); | |
c0c36b94 CW |
10782 | if (ret) |
10783 | goto done; | |
a6778b3c DV |
10784 | } |
10785 | ||
10786 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10787 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10788 | update_scanline_offset(intel_crtc); | |
10789 | ||
25c5b266 | 10790 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10791 | } |
a6778b3c | 10792 | |
a6778b3c DV |
10793 | /* FIXME: add subpixel order */ |
10794 | done: | |
4b4b9238 | 10795 | if (ret && crtc->enabled) |
3ac18232 | 10796 | crtc->mode = *saved_mode; |
a6778b3c | 10797 | |
3ac18232 | 10798 | out: |
b8cecdf5 | 10799 | kfree(pipe_config); |
3ac18232 | 10800 | kfree(saved_mode); |
a6778b3c | 10801 | return ret; |
f6e5b160 CW |
10802 | } |
10803 | ||
e7457a9a DL |
10804 | static int intel_set_mode(struct drm_crtc *crtc, |
10805 | struct drm_display_mode *mode, | |
10806 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10807 | { |
10808 | int ret; | |
10809 | ||
10810 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10811 | ||
10812 | if (ret == 0) | |
10813 | intel_modeset_check_state(crtc->dev); | |
10814 | ||
10815 | return ret; | |
10816 | } | |
10817 | ||
c0c36b94 CW |
10818 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10819 | { | |
f4510a27 | 10820 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10821 | } |
10822 | ||
25c5b266 DV |
10823 | #undef for_each_intel_crtc_masked |
10824 | ||
d9e55608 DV |
10825 | static void intel_set_config_free(struct intel_set_config *config) |
10826 | { | |
10827 | if (!config) | |
10828 | return; | |
10829 | ||
1aa4b628 DV |
10830 | kfree(config->save_connector_encoders); |
10831 | kfree(config->save_encoder_crtcs); | |
7668851f | 10832 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10833 | kfree(config); |
10834 | } | |
10835 | ||
85f9eb71 DV |
10836 | static int intel_set_config_save_state(struct drm_device *dev, |
10837 | struct intel_set_config *config) | |
10838 | { | |
7668851f | 10839 | struct drm_crtc *crtc; |
85f9eb71 DV |
10840 | struct drm_encoder *encoder; |
10841 | struct drm_connector *connector; | |
10842 | int count; | |
10843 | ||
7668851f VS |
10844 | config->save_crtc_enabled = |
10845 | kcalloc(dev->mode_config.num_crtc, | |
10846 | sizeof(bool), GFP_KERNEL); | |
10847 | if (!config->save_crtc_enabled) | |
10848 | return -ENOMEM; | |
10849 | ||
1aa4b628 DV |
10850 | config->save_encoder_crtcs = |
10851 | kcalloc(dev->mode_config.num_encoder, | |
10852 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10853 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10854 | return -ENOMEM; |
10855 | ||
1aa4b628 DV |
10856 | config->save_connector_encoders = |
10857 | kcalloc(dev->mode_config.num_connector, | |
10858 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10859 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10860 | return -ENOMEM; |
10861 | ||
10862 | /* Copy data. Note that driver private data is not affected. | |
10863 | * Should anything bad happen only the expected state is | |
10864 | * restored, not the drivers personal bookkeeping. | |
10865 | */ | |
7668851f | 10866 | count = 0; |
70e1e0ec | 10867 | for_each_crtc(dev, crtc) { |
7668851f VS |
10868 | config->save_crtc_enabled[count++] = crtc->enabled; |
10869 | } | |
10870 | ||
85f9eb71 DV |
10871 | count = 0; |
10872 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10873 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10874 | } |
10875 | ||
10876 | count = 0; | |
10877 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10878 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10879 | } |
10880 | ||
10881 | return 0; | |
10882 | } | |
10883 | ||
10884 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10885 | struct intel_set_config *config) | |
10886 | { | |
7668851f | 10887 | struct intel_crtc *crtc; |
9a935856 DV |
10888 | struct intel_encoder *encoder; |
10889 | struct intel_connector *connector; | |
85f9eb71 DV |
10890 | int count; |
10891 | ||
7668851f | 10892 | count = 0; |
d3fcc808 | 10893 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10894 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10895 | |
10896 | if (crtc->new_enabled) | |
10897 | crtc->new_config = &crtc->config; | |
10898 | else | |
10899 | crtc->new_config = NULL; | |
7668851f VS |
10900 | } |
10901 | ||
85f9eb71 | 10902 | count = 0; |
9a935856 DV |
10903 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10904 | encoder->new_crtc = | |
10905 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10906 | } |
10907 | ||
10908 | count = 0; | |
9a935856 DV |
10909 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10910 | connector->new_encoder = | |
10911 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10912 | } |
10913 | } | |
10914 | ||
e3de42b6 | 10915 | static bool |
2e57f47d | 10916 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10917 | { |
10918 | int i; | |
10919 | ||
2e57f47d CW |
10920 | if (set->num_connectors == 0) |
10921 | return false; | |
10922 | ||
10923 | if (WARN_ON(set->connectors == NULL)) | |
10924 | return false; | |
10925 | ||
10926 | for (i = 0; i < set->num_connectors; i++) | |
10927 | if (set->connectors[i]->encoder && | |
10928 | set->connectors[i]->encoder->crtc == set->crtc && | |
10929 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10930 | return true; |
10931 | ||
10932 | return false; | |
10933 | } | |
10934 | ||
5e2b584e DV |
10935 | static void |
10936 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10937 | struct intel_set_config *config) | |
10938 | { | |
10939 | ||
10940 | /* We should be able to check here if the fb has the same properties | |
10941 | * and then just flip_or_move it */ | |
2e57f47d CW |
10942 | if (is_crtc_connector_off(set)) { |
10943 | config->mode_changed = true; | |
f4510a27 | 10944 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
10945 | /* |
10946 | * If we have no fb, we can only flip as long as the crtc is | |
10947 | * active, otherwise we need a full mode set. The crtc may | |
10948 | * be active if we've only disabled the primary plane, or | |
10949 | * in fastboot situations. | |
10950 | */ | |
f4510a27 | 10951 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10952 | struct intel_crtc *intel_crtc = |
10953 | to_intel_crtc(set->crtc); | |
10954 | ||
3b150f08 | 10955 | if (intel_crtc->active) { |
319d9827 JB |
10956 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10957 | config->fb_changed = true; | |
10958 | } else { | |
10959 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10960 | config->mode_changed = true; | |
10961 | } | |
5e2b584e DV |
10962 | } else if (set->fb == NULL) { |
10963 | config->mode_changed = true; | |
72f4901e | 10964 | } else if (set->fb->pixel_format != |
f4510a27 | 10965 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10966 | config->mode_changed = true; |
e3de42b6 | 10967 | } else { |
5e2b584e | 10968 | config->fb_changed = true; |
e3de42b6 | 10969 | } |
5e2b584e DV |
10970 | } |
10971 | ||
835c5873 | 10972 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10973 | config->fb_changed = true; |
10974 | ||
10975 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10976 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10977 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10978 | drm_mode_debug_printmodeline(set->mode); | |
10979 | config->mode_changed = true; | |
10980 | } | |
a1d95703 CW |
10981 | |
10982 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10983 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10984 | } |
10985 | ||
2e431051 | 10986 | static int |
9a935856 DV |
10987 | intel_modeset_stage_output_state(struct drm_device *dev, |
10988 | struct drm_mode_set *set, | |
10989 | struct intel_set_config *config) | |
50f56119 | 10990 | { |
9a935856 DV |
10991 | struct intel_connector *connector; |
10992 | struct intel_encoder *encoder; | |
7668851f | 10993 | struct intel_crtc *crtc; |
f3f08572 | 10994 | int ro; |
50f56119 | 10995 | |
9abdda74 | 10996 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10997 | * of connectors. For paranoia, double-check this. */ |
10998 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10999 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11000 | ||
9a935856 DV |
11001 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11002 | base.head) { | |
11003 | /* Otherwise traverse passed in connector list and get encoders | |
11004 | * for them. */ | |
50f56119 | 11005 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
11006 | if (set->connectors[ro] == &connector->base) { |
11007 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
11008 | break; |
11009 | } | |
11010 | } | |
11011 | ||
9a935856 DV |
11012 | /* If we disable the crtc, disable all its connectors. Also, if |
11013 | * the connector is on the changing crtc but not on the new | |
11014 | * connector list, disable it. */ | |
11015 | if ((!set->fb || ro == set->num_connectors) && | |
11016 | connector->base.encoder && | |
11017 | connector->base.encoder->crtc == set->crtc) { | |
11018 | connector->new_encoder = NULL; | |
11019 | ||
11020 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11021 | connector->base.base.id, | |
c23cc417 | 11022 | connector->base.name); |
9a935856 DV |
11023 | } |
11024 | ||
11025 | ||
11026 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11027 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11028 | config->mode_changed = true; |
50f56119 DV |
11029 | } |
11030 | } | |
9a935856 | 11031 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11032 | |
9a935856 | 11033 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11034 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11035 | base.head) { | |
7668851f VS |
11036 | struct drm_crtc *new_crtc; |
11037 | ||
9a935856 | 11038 | if (!connector->new_encoder) |
50f56119 DV |
11039 | continue; |
11040 | ||
9a935856 | 11041 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11042 | |
11043 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11044 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11045 | new_crtc = set->crtc; |
11046 | } | |
11047 | ||
11048 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11049 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11050 | new_crtc)) { | |
5e2b584e | 11051 | return -EINVAL; |
50f56119 | 11052 | } |
9a935856 DV |
11053 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
11054 | ||
11055 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11056 | connector->base.base.id, | |
c23cc417 | 11057 | connector->base.name, |
9a935856 DV |
11058 | new_crtc->base.id); |
11059 | } | |
11060 | ||
11061 | /* Check for any encoders that needs to be disabled. */ | |
11062 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11063 | base.head) { | |
5a65f358 | 11064 | int num_connectors = 0; |
9a935856 DV |
11065 | list_for_each_entry(connector, |
11066 | &dev->mode_config.connector_list, | |
11067 | base.head) { | |
11068 | if (connector->new_encoder == encoder) { | |
11069 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11070 | num_connectors++; |
9a935856 DV |
11071 | } |
11072 | } | |
5a65f358 PZ |
11073 | |
11074 | if (num_connectors == 0) | |
11075 | encoder->new_crtc = NULL; | |
11076 | else if (num_connectors > 1) | |
11077 | return -EINVAL; | |
11078 | ||
9a935856 DV |
11079 | /* Only now check for crtc changes so we don't miss encoders |
11080 | * that will be disabled. */ | |
11081 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11082 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11083 | config->mode_changed = true; |
50f56119 DV |
11084 | } |
11085 | } | |
9a935856 | 11086 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 11087 | |
d3fcc808 | 11088 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11089 | crtc->new_enabled = false; |
11090 | ||
11091 | list_for_each_entry(encoder, | |
11092 | &dev->mode_config.encoder_list, | |
11093 | base.head) { | |
11094 | if (encoder->new_crtc == crtc) { | |
11095 | crtc->new_enabled = true; | |
11096 | break; | |
11097 | } | |
11098 | } | |
11099 | ||
11100 | if (crtc->new_enabled != crtc->base.enabled) { | |
11101 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11102 | crtc->new_enabled ? "en" : "dis"); | |
11103 | config->mode_changed = true; | |
11104 | } | |
7bd0a8e7 VS |
11105 | |
11106 | if (crtc->new_enabled) | |
11107 | crtc->new_config = &crtc->config; | |
11108 | else | |
11109 | crtc->new_config = NULL; | |
7668851f VS |
11110 | } |
11111 | ||
2e431051 DV |
11112 | return 0; |
11113 | } | |
11114 | ||
7d00a1f5 VS |
11115 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11116 | { | |
11117 | struct drm_device *dev = crtc->base.dev; | |
11118 | struct intel_encoder *encoder; | |
11119 | struct intel_connector *connector; | |
11120 | ||
11121 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11122 | pipe_name(crtc->pipe)); | |
11123 | ||
11124 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11125 | if (connector->new_encoder && | |
11126 | connector->new_encoder->new_crtc == crtc) | |
11127 | connector->new_encoder = NULL; | |
11128 | } | |
11129 | ||
11130 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
11131 | if (encoder->new_crtc == crtc) | |
11132 | encoder->new_crtc = NULL; | |
11133 | } | |
11134 | ||
11135 | crtc->new_enabled = false; | |
7bd0a8e7 | 11136 | crtc->new_config = NULL; |
7d00a1f5 VS |
11137 | } |
11138 | ||
2e431051 DV |
11139 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11140 | { | |
11141 | struct drm_device *dev; | |
2e431051 DV |
11142 | struct drm_mode_set save_set; |
11143 | struct intel_set_config *config; | |
11144 | int ret; | |
2e431051 | 11145 | |
8d3e375e DV |
11146 | BUG_ON(!set); |
11147 | BUG_ON(!set->crtc); | |
11148 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11149 | |
7e53f3a4 DV |
11150 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11151 | BUG_ON(!set->mode && set->fb); | |
11152 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11153 | |
2e431051 DV |
11154 | if (set->fb) { |
11155 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11156 | set->crtc->base.id, set->fb->base.id, | |
11157 | (int)set->num_connectors, set->x, set->y); | |
11158 | } else { | |
11159 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11160 | } |
11161 | ||
11162 | dev = set->crtc->dev; | |
11163 | ||
11164 | ret = -ENOMEM; | |
11165 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11166 | if (!config) | |
11167 | goto out_config; | |
11168 | ||
11169 | ret = intel_set_config_save_state(dev, config); | |
11170 | if (ret) | |
11171 | goto out_config; | |
11172 | ||
11173 | save_set.crtc = set->crtc; | |
11174 | save_set.mode = &set->crtc->mode; | |
11175 | save_set.x = set->crtc->x; | |
11176 | save_set.y = set->crtc->y; | |
f4510a27 | 11177 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11178 | |
11179 | /* Compute whether we need a full modeset, only an fb base update or no | |
11180 | * change at all. In the future we might also check whether only the | |
11181 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11182 | * such cases. */ | |
11183 | intel_set_config_compute_mode_changes(set, config); | |
11184 | ||
9a935856 | 11185 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11186 | if (ret) |
11187 | goto fail; | |
11188 | ||
5e2b584e | 11189 | if (config->mode_changed) { |
c0c36b94 CW |
11190 | ret = intel_set_mode(set->crtc, set->mode, |
11191 | set->x, set->y, set->fb); | |
5e2b584e | 11192 | } else if (config->fb_changed) { |
3b150f08 MR |
11193 | struct drm_i915_private *dev_priv = dev->dev_private; |
11194 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); | |
11195 | ||
4878cae2 VS |
11196 | intel_crtc_wait_for_pending_flips(set->crtc); |
11197 | ||
4f660f49 | 11198 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11199 | set->x, set->y, set->fb); |
3b150f08 MR |
11200 | |
11201 | /* | |
11202 | * We need to make sure the primary plane is re-enabled if it | |
11203 | * has previously been turned off. | |
11204 | */ | |
11205 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11206 | WARN_ON(!intel_crtc->active); | |
11207 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11208 | intel_crtc->pipe); | |
11209 | } | |
11210 | ||
7ca51a3a JB |
11211 | /* |
11212 | * In the fastboot case this may be our only check of the | |
11213 | * state after boot. It would be better to only do it on | |
11214 | * the first update, but we don't have a nice way of doing that | |
11215 | * (and really, set_config isn't used much for high freq page | |
11216 | * flipping, so increasing its cost here shouldn't be a big | |
11217 | * deal). | |
11218 | */ | |
d330a953 | 11219 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11220 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11221 | } |
11222 | ||
2d05eae1 | 11223 | if (ret) { |
bf67dfeb DV |
11224 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11225 | set->crtc->base.id, ret); | |
50f56119 | 11226 | fail: |
2d05eae1 | 11227 | intel_set_config_restore_state(dev, config); |
50f56119 | 11228 | |
7d00a1f5 VS |
11229 | /* |
11230 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11231 | * force the pipe off to avoid oopsing in the modeset code | |
11232 | * due to fb==NULL. This should only happen during boot since | |
11233 | * we don't yet reconstruct the FB from the hardware state. | |
11234 | */ | |
11235 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11236 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11237 | ||
2d05eae1 CW |
11238 | /* Try to restore the config */ |
11239 | if (config->mode_changed && | |
11240 | intel_set_mode(save_set.crtc, save_set.mode, | |
11241 | save_set.x, save_set.y, save_set.fb)) | |
11242 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11243 | } | |
50f56119 | 11244 | |
d9e55608 DV |
11245 | out_config: |
11246 | intel_set_config_free(config); | |
50f56119 DV |
11247 | return ret; |
11248 | } | |
f6e5b160 CW |
11249 | |
11250 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11251 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11252 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11253 | .destroy = intel_crtc_destroy, |
11254 | .page_flip = intel_crtc_page_flip, | |
11255 | }; | |
11256 | ||
79f689aa PZ |
11257 | static void intel_cpu_pll_init(struct drm_device *dev) |
11258 | { | |
affa9354 | 11259 | if (HAS_DDI(dev)) |
79f689aa PZ |
11260 | intel_ddi_pll_init(dev); |
11261 | } | |
11262 | ||
5358901f DV |
11263 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11264 | struct intel_shared_dpll *pll, | |
11265 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11266 | { |
5358901f | 11267 | uint32_t val; |
ee7b9f93 | 11268 | |
5358901f | 11269 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11270 | hw_state->dpll = val; |
11271 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11272 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11273 | |
11274 | return val & DPLL_VCO_ENABLE; | |
11275 | } | |
11276 | ||
15bdd4cf DV |
11277 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11278 | struct intel_shared_dpll *pll) | |
11279 | { | |
11280 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11281 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11282 | } | |
11283 | ||
e7b903d2 DV |
11284 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11285 | struct intel_shared_dpll *pll) | |
11286 | { | |
e7b903d2 | 11287 | /* PCH refclock must be enabled first */ |
89eff4be | 11288 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11289 | |
15bdd4cf DV |
11290 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11291 | ||
11292 | /* Wait for the clocks to stabilize. */ | |
11293 | POSTING_READ(PCH_DPLL(pll->id)); | |
11294 | udelay(150); | |
11295 | ||
11296 | /* The pixel multiplier can only be updated once the | |
11297 | * DPLL is enabled and the clocks are stable. | |
11298 | * | |
11299 | * So write it again. | |
11300 | */ | |
11301 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11302 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11303 | udelay(200); |
11304 | } | |
11305 | ||
11306 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11307 | struct intel_shared_dpll *pll) | |
11308 | { | |
11309 | struct drm_device *dev = dev_priv->dev; | |
11310 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11311 | |
11312 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11313 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11314 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11315 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11316 | } |
11317 | ||
15bdd4cf DV |
11318 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11319 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11320 | udelay(200); |
11321 | } | |
11322 | ||
46edb027 DV |
11323 | static char *ibx_pch_dpll_names[] = { |
11324 | "PCH DPLL A", | |
11325 | "PCH DPLL B", | |
11326 | }; | |
11327 | ||
7c74ade1 | 11328 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11329 | { |
e7b903d2 | 11330 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11331 | int i; |
11332 | ||
7c74ade1 | 11333 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11334 | |
e72f9fbf | 11335 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11336 | dev_priv->shared_dplls[i].id = i; |
11337 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11338 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11339 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11340 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11341 | dev_priv->shared_dplls[i].get_hw_state = |
11342 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11343 | } |
11344 | } | |
11345 | ||
7c74ade1 DV |
11346 | static void intel_shared_dpll_init(struct drm_device *dev) |
11347 | { | |
e7b903d2 | 11348 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
11349 | |
11350 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
11351 | ibx_pch_dpll_init(dev); | |
11352 | else | |
11353 | dev_priv->num_shared_dpll = 0; | |
11354 | ||
11355 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11356 | } |
11357 | ||
465c120c MR |
11358 | static int |
11359 | intel_primary_plane_disable(struct drm_plane *plane) | |
11360 | { | |
11361 | struct drm_device *dev = plane->dev; | |
11362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11363 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11364 | struct intel_crtc *intel_crtc; | |
11365 | ||
11366 | if (!plane->fb) | |
11367 | return 0; | |
11368 | ||
11369 | BUG_ON(!plane->crtc); | |
11370 | ||
11371 | intel_crtc = to_intel_crtc(plane->crtc); | |
11372 | ||
11373 | /* | |
11374 | * Even though we checked plane->fb above, it's still possible that | |
11375 | * the primary plane has been implicitly disabled because the crtc | |
11376 | * coordinates given weren't visible, or because we detected | |
11377 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11378 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11379 | * In either case, we need to unpin the FB and let the fb pointer get | |
11380 | * updated, but otherwise we don't need to touch the hardware. | |
11381 | */ | |
11382 | if (!intel_crtc->primary_enabled) | |
11383 | goto disable_unpin; | |
11384 | ||
11385 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
11386 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, | |
11387 | intel_plane->pipe); | |
465c120c | 11388 | disable_unpin: |
a071fa00 DV |
11389 | i915_gem_track_fb(to_intel_framebuffer(plane->fb)->obj, NULL, |
11390 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11391 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); |
11392 | plane->fb = NULL; | |
11393 | ||
11394 | return 0; | |
11395 | } | |
11396 | ||
11397 | static int | |
11398 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11399 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11400 | unsigned int crtc_w, unsigned int crtc_h, | |
11401 | uint32_t src_x, uint32_t src_y, | |
11402 | uint32_t src_w, uint32_t src_h) | |
11403 | { | |
11404 | struct drm_device *dev = crtc->dev; | |
11405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11407 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
a071fa00 | 11408 | struct drm_i915_gem_object *obj, *old_obj = NULL; |
465c120c MR |
11409 | struct drm_rect dest = { |
11410 | /* integer pixels */ | |
11411 | .x1 = crtc_x, | |
11412 | .y1 = crtc_y, | |
11413 | .x2 = crtc_x + crtc_w, | |
11414 | .y2 = crtc_y + crtc_h, | |
11415 | }; | |
11416 | struct drm_rect src = { | |
11417 | /* 16.16 fixed point */ | |
11418 | .x1 = src_x, | |
11419 | .y1 = src_y, | |
11420 | .x2 = src_x + src_w, | |
11421 | .y2 = src_y + src_h, | |
11422 | }; | |
11423 | const struct drm_rect clip = { | |
11424 | /* integer pixels */ | |
11425 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11426 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11427 | }; | |
11428 | bool visible; | |
11429 | int ret; | |
11430 | ||
11431 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11432 | &src, &dest, &clip, | |
11433 | DRM_PLANE_HELPER_NO_SCALING, | |
11434 | DRM_PLANE_HELPER_NO_SCALING, | |
11435 | false, true, &visible); | |
11436 | ||
11437 | if (ret) | |
11438 | return ret; | |
11439 | ||
a071fa00 DV |
11440 | if (plane->fb) |
11441 | old_obj = to_intel_framebuffer(plane->fb)->obj; | |
11442 | obj = to_intel_framebuffer(fb)->obj; | |
11443 | ||
465c120c MR |
11444 | /* |
11445 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11446 | * updating the fb pointer, and returning without touching the | |
11447 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11448 | * turn on the display with all planes setup as desired. | |
11449 | */ | |
11450 | if (!crtc->enabled) { | |
11451 | /* | |
11452 | * If we already called setplane while the crtc was disabled, | |
11453 | * we may have an fb pinned; unpin it. | |
11454 | */ | |
11455 | if (plane->fb) | |
a071fa00 DV |
11456 | intel_unpin_fb_obj(old_obj); |
11457 | ||
11458 | i915_gem_track_fb(old_obj, obj, | |
11459 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11460 | |
11461 | /* Pin and return without programming hardware */ | |
a071fa00 | 11462 | return intel_pin_and_fence_fb_obj(dev, obj, NULL); |
465c120c MR |
11463 | } |
11464 | ||
11465 | intel_crtc_wait_for_pending_flips(crtc); | |
11466 | ||
11467 | /* | |
11468 | * If clipping results in a non-visible primary plane, we'll disable | |
11469 | * the primary plane. Note that this is a bit different than what | |
11470 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11471 | * because plane->fb still gets set and pinned. | |
11472 | */ | |
11473 | if (!visible) { | |
11474 | /* | |
11475 | * Try to pin the new fb first so that we can bail out if we | |
11476 | * fail. | |
11477 | */ | |
11478 | if (plane->fb != fb) { | |
a071fa00 | 11479 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
465c120c MR |
11480 | if (ret) |
11481 | return ret; | |
11482 | } | |
11483 | ||
a071fa00 DV |
11484 | i915_gem_track_fb(old_obj, obj, |
11485 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11486 | ||
465c120c MR |
11487 | if (intel_crtc->primary_enabled) |
11488 | intel_disable_primary_hw_plane(dev_priv, | |
11489 | intel_plane->plane, | |
11490 | intel_plane->pipe); | |
11491 | ||
11492 | ||
11493 | if (plane->fb != fb) | |
11494 | if (plane->fb) | |
a071fa00 | 11495 | intel_unpin_fb_obj(old_obj); |
465c120c MR |
11496 | |
11497 | return 0; | |
11498 | } | |
11499 | ||
11500 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); | |
11501 | if (ret) | |
11502 | return ret; | |
11503 | ||
11504 | if (!intel_crtc->primary_enabled) | |
11505 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11506 | intel_crtc->pipe); | |
11507 | ||
11508 | return 0; | |
11509 | } | |
11510 | ||
3d7d6510 MR |
11511 | /* Common destruction function for both primary and cursor planes */ |
11512 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11513 | { |
11514 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11515 | drm_plane_cleanup(plane); | |
11516 | kfree(intel_plane); | |
11517 | } | |
11518 | ||
11519 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11520 | .update_plane = intel_primary_plane_setplane, | |
11521 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11522 | .destroy = intel_plane_destroy, |
465c120c MR |
11523 | }; |
11524 | ||
11525 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11526 | int pipe) | |
11527 | { | |
11528 | struct intel_plane *primary; | |
11529 | const uint32_t *intel_primary_formats; | |
11530 | int num_formats; | |
11531 | ||
11532 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11533 | if (primary == NULL) | |
11534 | return NULL; | |
11535 | ||
11536 | primary->can_scale = false; | |
11537 | primary->max_downscale = 1; | |
11538 | primary->pipe = pipe; | |
11539 | primary->plane = pipe; | |
11540 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
11541 | primary->plane = !pipe; | |
11542 | ||
11543 | if (INTEL_INFO(dev)->gen <= 3) { | |
11544 | intel_primary_formats = intel_primary_formats_gen2; | |
11545 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11546 | } else { | |
11547 | intel_primary_formats = intel_primary_formats_gen4; | |
11548 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11549 | } | |
11550 | ||
11551 | drm_universal_plane_init(dev, &primary->base, 0, | |
11552 | &intel_primary_plane_funcs, | |
11553 | intel_primary_formats, num_formats, | |
11554 | DRM_PLANE_TYPE_PRIMARY); | |
11555 | return &primary->base; | |
11556 | } | |
11557 | ||
3d7d6510 MR |
11558 | static int |
11559 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11560 | { | |
11561 | if (!plane->fb) | |
11562 | return 0; | |
11563 | ||
11564 | BUG_ON(!plane->crtc); | |
11565 | ||
11566 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11567 | } | |
11568 | ||
11569 | static int | |
11570 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11571 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11572 | unsigned int crtc_w, unsigned int crtc_h, | |
11573 | uint32_t src_x, uint32_t src_y, | |
11574 | uint32_t src_w, uint32_t src_h) | |
11575 | { | |
11576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11577 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11578 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11579 | struct drm_rect dest = { | |
11580 | /* integer pixels */ | |
11581 | .x1 = crtc_x, | |
11582 | .y1 = crtc_y, | |
11583 | .x2 = crtc_x + crtc_w, | |
11584 | .y2 = crtc_y + crtc_h, | |
11585 | }; | |
11586 | struct drm_rect src = { | |
11587 | /* 16.16 fixed point */ | |
11588 | .x1 = src_x, | |
11589 | .y1 = src_y, | |
11590 | .x2 = src_x + src_w, | |
11591 | .y2 = src_y + src_h, | |
11592 | }; | |
11593 | const struct drm_rect clip = { | |
11594 | /* integer pixels */ | |
11595 | .x2 = intel_crtc->config.pipe_src_w, | |
11596 | .y2 = intel_crtc->config.pipe_src_h, | |
11597 | }; | |
11598 | bool visible; | |
11599 | int ret; | |
11600 | ||
11601 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11602 | &src, &dest, &clip, | |
11603 | DRM_PLANE_HELPER_NO_SCALING, | |
11604 | DRM_PLANE_HELPER_NO_SCALING, | |
11605 | true, true, &visible); | |
11606 | if (ret) | |
11607 | return ret; | |
11608 | ||
11609 | crtc->cursor_x = crtc_x; | |
11610 | crtc->cursor_y = crtc_y; | |
11611 | if (fb != crtc->cursor->fb) { | |
11612 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11613 | } else { | |
11614 | intel_crtc_update_cursor(crtc, visible); | |
11615 | return 0; | |
11616 | } | |
11617 | } | |
11618 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11619 | .update_plane = intel_cursor_plane_update, | |
11620 | .disable_plane = intel_cursor_plane_disable, | |
11621 | .destroy = intel_plane_destroy, | |
11622 | }; | |
11623 | ||
11624 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11625 | int pipe) | |
11626 | { | |
11627 | struct intel_plane *cursor; | |
11628 | ||
11629 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11630 | if (cursor == NULL) | |
11631 | return NULL; | |
11632 | ||
11633 | cursor->can_scale = false; | |
11634 | cursor->max_downscale = 1; | |
11635 | cursor->pipe = pipe; | |
11636 | cursor->plane = pipe; | |
11637 | ||
11638 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11639 | &intel_cursor_plane_funcs, | |
11640 | intel_cursor_formats, | |
11641 | ARRAY_SIZE(intel_cursor_formats), | |
11642 | DRM_PLANE_TYPE_CURSOR); | |
11643 | return &cursor->base; | |
11644 | } | |
11645 | ||
b358d0a6 | 11646 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11647 | { |
fbee40df | 11648 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11649 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11650 | struct drm_plane *primary = NULL; |
11651 | struct drm_plane *cursor = NULL; | |
465c120c | 11652 | int i, ret; |
79e53945 | 11653 | |
955382f3 | 11654 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11655 | if (intel_crtc == NULL) |
11656 | return; | |
11657 | ||
465c120c | 11658 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11659 | if (!primary) |
11660 | goto fail; | |
11661 | ||
11662 | cursor = intel_cursor_plane_create(dev, pipe); | |
11663 | if (!cursor) | |
11664 | goto fail; | |
11665 | ||
465c120c | 11666 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11667 | cursor, &intel_crtc_funcs); |
11668 | if (ret) | |
11669 | goto fail; | |
79e53945 JB |
11670 | |
11671 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11672 | for (i = 0; i < 256; i++) { |
11673 | intel_crtc->lut_r[i] = i; | |
11674 | intel_crtc->lut_g[i] = i; | |
11675 | intel_crtc->lut_b[i] = i; | |
11676 | } | |
11677 | ||
1f1c2e24 VS |
11678 | /* |
11679 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 11680 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 11681 | */ |
80824003 JB |
11682 | intel_crtc->pipe = pipe; |
11683 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11684 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11685 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11686 | intel_crtc->plane = !pipe; |
80824003 JB |
11687 | } |
11688 | ||
4b0e333e CW |
11689 | intel_crtc->cursor_base = ~0; |
11690 | intel_crtc->cursor_cntl = ~0; | |
11691 | ||
8d7849db VS |
11692 | init_waitqueue_head(&intel_crtc->vbl_wait); |
11693 | ||
22fd0fab JB |
11694 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11695 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11696 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11697 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11698 | ||
79e53945 | 11699 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11700 | |
11701 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11702 | return; |
11703 | ||
11704 | fail: | |
11705 | if (primary) | |
11706 | drm_plane_cleanup(primary); | |
11707 | if (cursor) | |
11708 | drm_plane_cleanup(cursor); | |
11709 | kfree(intel_crtc); | |
79e53945 JB |
11710 | } |
11711 | ||
752aa88a JB |
11712 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11713 | { | |
11714 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11715 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11716 | |
51fd371b | 11717 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11718 | |
11719 | if (!encoder) | |
11720 | return INVALID_PIPE; | |
11721 | ||
11722 | return to_intel_crtc(encoder->crtc)->pipe; | |
11723 | } | |
11724 | ||
08d7b3d1 | 11725 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11726 | struct drm_file *file) |
08d7b3d1 | 11727 | { |
08d7b3d1 | 11728 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
11729 | struct drm_mode_object *drmmode_obj; |
11730 | struct intel_crtc *crtc; | |
08d7b3d1 | 11731 | |
1cff8f6b DV |
11732 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11733 | return -ENODEV; | |
08d7b3d1 | 11734 | |
c05422d5 DV |
11735 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11736 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 11737 | |
c05422d5 | 11738 | if (!drmmode_obj) { |
08d7b3d1 | 11739 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11740 | return -ENOENT; |
08d7b3d1 CW |
11741 | } |
11742 | ||
c05422d5 DV |
11743 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11744 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 11745 | |
c05422d5 | 11746 | return 0; |
08d7b3d1 CW |
11747 | } |
11748 | ||
66a9278e | 11749 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11750 | { |
66a9278e DV |
11751 | struct drm_device *dev = encoder->base.dev; |
11752 | struct intel_encoder *source_encoder; | |
79e53945 | 11753 | int index_mask = 0; |
79e53945 JB |
11754 | int entry = 0; |
11755 | ||
66a9278e DV |
11756 | list_for_each_entry(source_encoder, |
11757 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11758 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11759 | index_mask |= (1 << entry); |
11760 | ||
79e53945 JB |
11761 | entry++; |
11762 | } | |
4ef69c7a | 11763 | |
79e53945 JB |
11764 | return index_mask; |
11765 | } | |
11766 | ||
4d302442 CW |
11767 | static bool has_edp_a(struct drm_device *dev) |
11768 | { | |
11769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11770 | ||
11771 | if (!IS_MOBILE(dev)) | |
11772 | return false; | |
11773 | ||
11774 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11775 | return false; | |
11776 | ||
e3589908 | 11777 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11778 | return false; |
11779 | ||
11780 | return true; | |
11781 | } | |
11782 | ||
ba0fbca4 DL |
11783 | const char *intel_output_name(int output) |
11784 | { | |
11785 | static const char *names[] = { | |
11786 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11787 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11788 | [INTEL_OUTPUT_DVO] = "DVO", | |
11789 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
11790 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
11791 | [INTEL_OUTPUT_TVOUT] = "TV", | |
11792 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
11793 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
11794 | [INTEL_OUTPUT_EDP] = "eDP", | |
11795 | [INTEL_OUTPUT_DSI] = "DSI", | |
11796 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
11797 | }; | |
11798 | ||
11799 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
11800 | return "Invalid"; | |
11801 | ||
11802 | return names[output]; | |
11803 | } | |
11804 | ||
84b4e042 JB |
11805 | static bool intel_crt_present(struct drm_device *dev) |
11806 | { | |
11807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11808 | ||
11809 | if (IS_ULT(dev)) | |
11810 | return false; | |
11811 | ||
11812 | if (IS_CHERRYVIEW(dev)) | |
11813 | return false; | |
11814 | ||
11815 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
11816 | return false; | |
11817 | ||
11818 | return true; | |
11819 | } | |
11820 | ||
79e53945 JB |
11821 | static void intel_setup_outputs(struct drm_device *dev) |
11822 | { | |
725e30ad | 11823 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 11824 | struct intel_encoder *encoder; |
cb0953d7 | 11825 | bool dpd_is_edp = false; |
79e53945 | 11826 | |
c9093354 | 11827 | intel_lvds_init(dev); |
79e53945 | 11828 | |
84b4e042 | 11829 | if (intel_crt_present(dev)) |
79935fca | 11830 | intel_crt_init(dev); |
cb0953d7 | 11831 | |
affa9354 | 11832 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11833 | int found; |
11834 | ||
11835 | /* Haswell uses DDI functions to detect digital outputs */ | |
11836 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11837 | /* DDI A only supports eDP */ | |
11838 | if (found) | |
11839 | intel_ddi_init(dev, PORT_A); | |
11840 | ||
11841 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11842 | * register */ | |
11843 | found = I915_READ(SFUSE_STRAP); | |
11844 | ||
11845 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11846 | intel_ddi_init(dev, PORT_B); | |
11847 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11848 | intel_ddi_init(dev, PORT_C); | |
11849 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11850 | intel_ddi_init(dev, PORT_D); | |
11851 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11852 | int found; |
5d8a7752 | 11853 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11854 | |
11855 | if (has_edp_a(dev)) | |
11856 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11857 | |
dc0fa718 | 11858 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11859 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11860 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11861 | if (!found) |
e2debe91 | 11862 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11863 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11864 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11865 | } |
11866 | ||
dc0fa718 | 11867 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11868 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11869 | |
dc0fa718 | 11870 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11871 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11872 | |
5eb08b69 | 11873 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11874 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11875 | |
270b3042 | 11876 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11877 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11878 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11879 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11880 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11881 | PORT_B); | |
11882 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11883 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11884 | } | |
11885 | ||
6f6005a5 JB |
11886 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11887 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11888 | PORT_C); | |
11889 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11890 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11891 | } |
19c03924 | 11892 | |
9418c1f1 VS |
11893 | if (IS_CHERRYVIEW(dev)) { |
11894 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11895 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11896 | PORT_D); | |
11897 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11898 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11899 | } | |
11900 | } | |
11901 | ||
3cfca973 | 11902 | intel_dsi_init(dev); |
103a196f | 11903 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11904 | bool found = false; |
7d57382e | 11905 | |
e2debe91 | 11906 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11907 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11908 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11909 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11910 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11911 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11912 | } |
27185ae1 | 11913 | |
e7281eab | 11914 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11915 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11916 | } |
13520b05 KH |
11917 | |
11918 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11919 | |
e2debe91 | 11920 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11921 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11922 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11923 | } |
27185ae1 | 11924 | |
e2debe91 | 11925 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11926 | |
b01f2c3a JB |
11927 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11928 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11929 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11930 | } |
e7281eab | 11931 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11932 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11933 | } |
27185ae1 | 11934 | |
b01f2c3a | 11935 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11936 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11937 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11938 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11939 | intel_dvo_init(dev); |
11940 | ||
103a196f | 11941 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11942 | intel_tv_init(dev); |
11943 | ||
7c8f8a70 RV |
11944 | intel_edp_psr_init(dev); |
11945 | ||
4ef69c7a CW |
11946 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11947 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11948 | encoder->base.possible_clones = | |
66a9278e | 11949 | intel_encoder_clones(encoder); |
79e53945 | 11950 | } |
47356eb6 | 11951 | |
dde86e2d | 11952 | intel_init_pch_refclk(dev); |
270b3042 DV |
11953 | |
11954 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11955 | } |
11956 | ||
11957 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11958 | { | |
60a5ca01 | 11959 | struct drm_device *dev = fb->dev; |
79e53945 | 11960 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 11961 | |
ef2d633e | 11962 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 11963 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 11964 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
11965 | drm_gem_object_unreference(&intel_fb->obj->base); |
11966 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
11967 | kfree(intel_fb); |
11968 | } | |
11969 | ||
11970 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11971 | struct drm_file *file, |
79e53945 JB |
11972 | unsigned int *handle) |
11973 | { | |
11974 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11975 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11976 | |
05394f39 | 11977 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11978 | } |
11979 | ||
11980 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11981 | .destroy = intel_user_framebuffer_destroy, | |
11982 | .create_handle = intel_user_framebuffer_create_handle, | |
11983 | }; | |
11984 | ||
b5ea642a DV |
11985 | static int intel_framebuffer_init(struct drm_device *dev, |
11986 | struct intel_framebuffer *intel_fb, | |
11987 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11988 | struct drm_i915_gem_object *obj) | |
79e53945 | 11989 | { |
a57ce0b2 | 11990 | int aligned_height; |
a35cdaa0 | 11991 | int pitch_limit; |
79e53945 JB |
11992 | int ret; |
11993 | ||
dd4916c5 DV |
11994 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11995 | ||
c16ed4be CW |
11996 | if (obj->tiling_mode == I915_TILING_Y) { |
11997 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11998 | return -EINVAL; |
c16ed4be | 11999 | } |
57cd6508 | 12000 | |
c16ed4be CW |
12001 | if (mode_cmd->pitches[0] & 63) { |
12002 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12003 | mode_cmd->pitches[0]); | |
57cd6508 | 12004 | return -EINVAL; |
c16ed4be | 12005 | } |
57cd6508 | 12006 | |
a35cdaa0 CW |
12007 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12008 | pitch_limit = 32*1024; | |
12009 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12010 | if (obj->tiling_mode) | |
12011 | pitch_limit = 16*1024; | |
12012 | else | |
12013 | pitch_limit = 32*1024; | |
12014 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12015 | if (obj->tiling_mode) | |
12016 | pitch_limit = 8*1024; | |
12017 | else | |
12018 | pitch_limit = 16*1024; | |
12019 | } else | |
12020 | /* XXX DSPC is limited to 4k tiled */ | |
12021 | pitch_limit = 8*1024; | |
12022 | ||
12023 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12024 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12025 | obj->tiling_mode ? "tiled" : "linear", | |
12026 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12027 | return -EINVAL; |
c16ed4be | 12028 | } |
5d7bd705 VS |
12029 | |
12030 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12031 | mode_cmd->pitches[0] != obj->stride) { |
12032 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12033 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12034 | return -EINVAL; |
c16ed4be | 12035 | } |
5d7bd705 | 12036 | |
57779d06 | 12037 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12038 | switch (mode_cmd->pixel_format) { |
57779d06 | 12039 | case DRM_FORMAT_C8: |
04b3924d VS |
12040 | case DRM_FORMAT_RGB565: |
12041 | case DRM_FORMAT_XRGB8888: | |
12042 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12043 | break; |
12044 | case DRM_FORMAT_XRGB1555: | |
12045 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12046 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12047 | DRM_DEBUG("unsupported pixel format: %s\n", |
12048 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12049 | return -EINVAL; |
c16ed4be | 12050 | } |
57779d06 VS |
12051 | break; |
12052 | case DRM_FORMAT_XBGR8888: | |
12053 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12054 | case DRM_FORMAT_XRGB2101010: |
12055 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12056 | case DRM_FORMAT_XBGR2101010: |
12057 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12058 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12059 | DRM_DEBUG("unsupported pixel format: %s\n", |
12060 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12061 | return -EINVAL; |
c16ed4be | 12062 | } |
b5626747 | 12063 | break; |
04b3924d VS |
12064 | case DRM_FORMAT_YUYV: |
12065 | case DRM_FORMAT_UYVY: | |
12066 | case DRM_FORMAT_YVYU: | |
12067 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12068 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12069 | DRM_DEBUG("unsupported pixel format: %s\n", |
12070 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12071 | return -EINVAL; |
c16ed4be | 12072 | } |
57cd6508 CW |
12073 | break; |
12074 | default: | |
4ee62c76 VS |
12075 | DRM_DEBUG("unsupported pixel format: %s\n", |
12076 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12077 | return -EINVAL; |
12078 | } | |
12079 | ||
90f9a336 VS |
12080 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12081 | if (mode_cmd->offsets[0] != 0) | |
12082 | return -EINVAL; | |
12083 | ||
a57ce0b2 JB |
12084 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12085 | obj->tiling_mode); | |
53155c0a DV |
12086 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12087 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12088 | return -EINVAL; | |
12089 | ||
c7d73f6a DV |
12090 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12091 | intel_fb->obj = obj; | |
80075d49 | 12092 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12093 | |
79e53945 JB |
12094 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12095 | if (ret) { | |
12096 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12097 | return ret; | |
12098 | } | |
12099 | ||
79e53945 JB |
12100 | return 0; |
12101 | } | |
12102 | ||
79e53945 JB |
12103 | static struct drm_framebuffer * |
12104 | intel_user_framebuffer_create(struct drm_device *dev, | |
12105 | struct drm_file *filp, | |
308e5bcb | 12106 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12107 | { |
05394f39 | 12108 | struct drm_i915_gem_object *obj; |
79e53945 | 12109 | |
308e5bcb JB |
12110 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12111 | mode_cmd->handles[0])); | |
c8725226 | 12112 | if (&obj->base == NULL) |
cce13ff7 | 12113 | return ERR_PTR(-ENOENT); |
79e53945 | 12114 | |
d2dff872 | 12115 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12116 | } |
12117 | ||
4520f53a | 12118 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12119 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12120 | { |
12121 | } | |
12122 | #endif | |
12123 | ||
79e53945 | 12124 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12125 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12126 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12127 | }; |
12128 | ||
e70236a8 JB |
12129 | /* Set up chip specific display functions */ |
12130 | static void intel_init_display(struct drm_device *dev) | |
12131 | { | |
12132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12133 | ||
ee9300bb DV |
12134 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12135 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12136 | else if (IS_CHERRYVIEW(dev)) |
12137 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12138 | else if (IS_VALLEYVIEW(dev)) |
12139 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12140 | else if (IS_PINEVIEW(dev)) | |
12141 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12142 | else | |
12143 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12144 | ||
affa9354 | 12145 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12146 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12147 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12148 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12149 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12150 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 12151 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
12152 | dev_priv->display.update_primary_plane = |
12153 | ironlake_update_primary_plane; | |
09b4ddf9 | 12154 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12155 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12156 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12157 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12158 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12159 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12160 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12161 | dev_priv->display.update_primary_plane = |
12162 | ironlake_update_primary_plane; | |
89b667f8 JB |
12163 | } else if (IS_VALLEYVIEW(dev)) { |
12164 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12165 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12166 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12167 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12168 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12169 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12170 | dev_priv->display.update_primary_plane = |
12171 | i9xx_update_primary_plane; | |
f564048e | 12172 | } else { |
0e8ffe1b | 12173 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12174 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12175 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12176 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12177 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12178 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12179 | dev_priv->display.update_primary_plane = |
12180 | i9xx_update_primary_plane; | |
f564048e | 12181 | } |
e70236a8 | 12182 | |
e70236a8 | 12183 | /* Returns the core display clock speed */ |
25eb05fc JB |
12184 | if (IS_VALLEYVIEW(dev)) |
12185 | dev_priv->display.get_display_clock_speed = | |
12186 | valleyview_get_display_clock_speed; | |
12187 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12188 | dev_priv->display.get_display_clock_speed = |
12189 | i945_get_display_clock_speed; | |
12190 | else if (IS_I915G(dev)) | |
12191 | dev_priv->display.get_display_clock_speed = | |
12192 | i915_get_display_clock_speed; | |
257a7ffc | 12193 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12194 | dev_priv->display.get_display_clock_speed = |
12195 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12196 | else if (IS_PINEVIEW(dev)) |
12197 | dev_priv->display.get_display_clock_speed = | |
12198 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12199 | else if (IS_I915GM(dev)) |
12200 | dev_priv->display.get_display_clock_speed = | |
12201 | i915gm_get_display_clock_speed; | |
12202 | else if (IS_I865G(dev)) | |
12203 | dev_priv->display.get_display_clock_speed = | |
12204 | i865_get_display_clock_speed; | |
f0f8a9ce | 12205 | else if (IS_I85X(dev)) |
e70236a8 JB |
12206 | dev_priv->display.get_display_clock_speed = |
12207 | i855_get_display_clock_speed; | |
12208 | else /* 852, 830 */ | |
12209 | dev_priv->display.get_display_clock_speed = | |
12210 | i830_get_display_clock_speed; | |
12211 | ||
7f8a8569 | 12212 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 12213 | if (IS_GEN5(dev)) { |
674cf967 | 12214 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 12215 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 12216 | } else if (IS_GEN6(dev)) { |
674cf967 | 12217 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 12218 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
12219 | dev_priv->display.modeset_global_resources = |
12220 | snb_modeset_global_resources; | |
357555c0 JB |
12221 | } else if (IS_IVYBRIDGE(dev)) { |
12222 | /* FIXME: detect B0+ stepping and use auto training */ | |
12223 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 12224 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
12225 | dev_priv->display.modeset_global_resources = |
12226 | ivb_modeset_global_resources; | |
4e0bbc31 | 12227 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 12228 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 12229 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
12230 | dev_priv->display.modeset_global_resources = |
12231 | haswell_modeset_global_resources; | |
a0e63c22 | 12232 | } |
6067aaea | 12233 | } else if (IS_G4X(dev)) { |
e0dac65e | 12234 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
12235 | } else if (IS_VALLEYVIEW(dev)) { |
12236 | dev_priv->display.modeset_global_resources = | |
12237 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12238 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12239 | } |
8c9f3aaf JB |
12240 | |
12241 | /* Default just returns -ENODEV to indicate unsupported */ | |
12242 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12243 | ||
12244 | switch (INTEL_INFO(dev)->gen) { | |
12245 | case 2: | |
12246 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12247 | break; | |
12248 | ||
12249 | case 3: | |
12250 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12251 | break; | |
12252 | ||
12253 | case 4: | |
12254 | case 5: | |
12255 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12256 | break; | |
12257 | ||
12258 | case 6: | |
12259 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12260 | break; | |
7c9017e5 | 12261 | case 7: |
4e0bbc31 | 12262 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12263 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12264 | break; | |
8c9f3aaf | 12265 | } |
7bd688cd JN |
12266 | |
12267 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
12268 | } |
12269 | ||
b690e96c JB |
12270 | /* |
12271 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12272 | * resume, or other times. This quirk makes sure that's the case for | |
12273 | * affected systems. | |
12274 | */ | |
0206e353 | 12275 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12276 | { |
12277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12278 | ||
12279 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12280 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12281 | } |
12282 | ||
435793df KP |
12283 | /* |
12284 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12285 | */ | |
12286 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12287 | { | |
12288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12289 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12290 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12291 | } |
12292 | ||
4dca20ef | 12293 | /* |
5a15ab5b CE |
12294 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12295 | * brightness value | |
4dca20ef CE |
12296 | */ |
12297 | static void quirk_invert_brightness(struct drm_device *dev) | |
12298 | { | |
12299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12300 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12301 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12302 | } |
12303 | ||
b690e96c JB |
12304 | struct intel_quirk { |
12305 | int device; | |
12306 | int subsystem_vendor; | |
12307 | int subsystem_device; | |
12308 | void (*hook)(struct drm_device *dev); | |
12309 | }; | |
12310 | ||
5f85f176 EE |
12311 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12312 | struct intel_dmi_quirk { | |
12313 | void (*hook)(struct drm_device *dev); | |
12314 | const struct dmi_system_id (*dmi_id_list)[]; | |
12315 | }; | |
12316 | ||
12317 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12318 | { | |
12319 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12320 | return 1; | |
12321 | } | |
12322 | ||
12323 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12324 | { | |
12325 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12326 | { | |
12327 | .callback = intel_dmi_reverse_brightness, | |
12328 | .ident = "NCR Corporation", | |
12329 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12330 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12331 | }, | |
12332 | }, | |
12333 | { } /* terminating entry */ | |
12334 | }, | |
12335 | .hook = quirk_invert_brightness, | |
12336 | }, | |
12337 | }; | |
12338 | ||
c43b5634 | 12339 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12340 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12341 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12342 | |
b690e96c JB |
12343 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12344 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12345 | ||
b690e96c JB |
12346 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12347 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12348 | ||
435793df KP |
12349 | /* Lenovo U160 cannot use SSC on LVDS */ |
12350 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12351 | |
12352 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12353 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12354 | |
be505f64 AH |
12355 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12356 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12357 | ||
12358 | /* Acer/eMachines G725 */ | |
12359 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12360 | ||
12361 | /* Acer/eMachines e725 */ | |
12362 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12363 | ||
12364 | /* Acer/Packard Bell NCL20 */ | |
12365 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12366 | ||
12367 | /* Acer Aspire 4736Z */ | |
12368 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12369 | |
12370 | /* Acer Aspire 5336 */ | |
12371 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
12372 | }; |
12373 | ||
12374 | static void intel_init_quirks(struct drm_device *dev) | |
12375 | { | |
12376 | struct pci_dev *d = dev->pdev; | |
12377 | int i; | |
12378 | ||
12379 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12380 | struct intel_quirk *q = &intel_quirks[i]; | |
12381 | ||
12382 | if (d->device == q->device && | |
12383 | (d->subsystem_vendor == q->subsystem_vendor || | |
12384 | q->subsystem_vendor == PCI_ANY_ID) && | |
12385 | (d->subsystem_device == q->subsystem_device || | |
12386 | q->subsystem_device == PCI_ANY_ID)) | |
12387 | q->hook(dev); | |
12388 | } | |
5f85f176 EE |
12389 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12390 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12391 | intel_dmi_quirks[i].hook(dev); | |
12392 | } | |
b690e96c JB |
12393 | } |
12394 | ||
9cce37f4 JB |
12395 | /* Disable the VGA plane that we never use */ |
12396 | static void i915_disable_vga(struct drm_device *dev) | |
12397 | { | |
12398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12399 | u8 sr1; | |
766aa1c4 | 12400 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12401 | |
2b37c616 | 12402 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12403 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12404 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12405 | sr1 = inb(VGA_SR_DATA); |
12406 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12407 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12408 | udelay(300); | |
12409 | ||
12410 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12411 | POSTING_READ(vga_reg); | |
12412 | } | |
12413 | ||
f817586c DV |
12414 | void intel_modeset_init_hw(struct drm_device *dev) |
12415 | { | |
a8f78b58 ED |
12416 | intel_prepare_ddi(dev); |
12417 | ||
f8bf63fd VS |
12418 | if (IS_VALLEYVIEW(dev)) |
12419 | vlv_update_cdclk(dev); | |
12420 | ||
f817586c DV |
12421 | intel_init_clock_gating(dev); |
12422 | ||
5382f5f3 | 12423 | intel_reset_dpio(dev); |
40e9cf64 | 12424 | |
8090c6b9 | 12425 | intel_enable_gt_powersave(dev); |
f817586c DV |
12426 | } |
12427 | ||
7d708ee4 ID |
12428 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12429 | { | |
12430 | intel_suspend_hw(dev); | |
12431 | } | |
12432 | ||
79e53945 JB |
12433 | void intel_modeset_init(struct drm_device *dev) |
12434 | { | |
652c393a | 12435 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12436 | int sprite, ret; |
8cc87b75 | 12437 | enum pipe pipe; |
46f297fb | 12438 | struct intel_crtc *crtc; |
79e53945 JB |
12439 | |
12440 | drm_mode_config_init(dev); | |
12441 | ||
12442 | dev->mode_config.min_width = 0; | |
12443 | dev->mode_config.min_height = 0; | |
12444 | ||
019d96cb DA |
12445 | dev->mode_config.preferred_depth = 24; |
12446 | dev->mode_config.prefer_shadow = 1; | |
12447 | ||
e6ecefaa | 12448 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12449 | |
b690e96c JB |
12450 | intel_init_quirks(dev); |
12451 | ||
1fa61106 ED |
12452 | intel_init_pm(dev); |
12453 | ||
e3c74757 BW |
12454 | if (INTEL_INFO(dev)->num_pipes == 0) |
12455 | return; | |
12456 | ||
e70236a8 JB |
12457 | intel_init_display(dev); |
12458 | ||
a6c45cf0 CW |
12459 | if (IS_GEN2(dev)) { |
12460 | dev->mode_config.max_width = 2048; | |
12461 | dev->mode_config.max_height = 2048; | |
12462 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12463 | dev->mode_config.max_width = 4096; |
12464 | dev->mode_config.max_height = 4096; | |
79e53945 | 12465 | } else { |
a6c45cf0 CW |
12466 | dev->mode_config.max_width = 8192; |
12467 | dev->mode_config.max_height = 8192; | |
79e53945 | 12468 | } |
068be561 DL |
12469 | |
12470 | if (IS_GEN2(dev)) { | |
12471 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
12472 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12473 | } else { | |
12474 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12475 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12476 | } | |
12477 | ||
5d4545ae | 12478 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12479 | |
28c97730 | 12480 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12481 | INTEL_INFO(dev)->num_pipes, |
12482 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12483 | |
8cc87b75 DL |
12484 | for_each_pipe(pipe) { |
12485 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
12486 | for_each_sprite(pipe, sprite) { |
12487 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12488 | if (ret) |
06da8da2 | 12489 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12490 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12491 | } |
79e53945 JB |
12492 | } |
12493 | ||
f42bb70d | 12494 | intel_init_dpio(dev); |
5382f5f3 | 12495 | intel_reset_dpio(dev); |
f42bb70d | 12496 | |
79f689aa | 12497 | intel_cpu_pll_init(dev); |
e72f9fbf | 12498 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12499 | |
9cce37f4 JB |
12500 | /* Just disable it once at startup */ |
12501 | i915_disable_vga(dev); | |
79e53945 | 12502 | intel_setup_outputs(dev); |
11be49eb CW |
12503 | |
12504 | /* Just in case the BIOS is doing something questionable. */ | |
12505 | intel_disable_fbc(dev); | |
fa9fa083 | 12506 | |
6e9f798d | 12507 | drm_modeset_lock_all(dev); |
fa9fa083 | 12508 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12509 | drm_modeset_unlock_all(dev); |
46f297fb | 12510 | |
d3fcc808 | 12511 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12512 | if (!crtc->active) |
12513 | continue; | |
12514 | ||
46f297fb | 12515 | /* |
46f297fb JB |
12516 | * Note that reserving the BIOS fb up front prevents us |
12517 | * from stuffing other stolen allocations like the ring | |
12518 | * on top. This prevents some ugliness at boot time, and | |
12519 | * can even allow for smooth boot transitions if the BIOS | |
12520 | * fb is large enough for the active pipe configuration. | |
12521 | */ | |
12522 | if (dev_priv->display.get_plane_config) { | |
12523 | dev_priv->display.get_plane_config(crtc, | |
12524 | &crtc->plane_config); | |
12525 | /* | |
12526 | * If the fb is shared between multiple heads, we'll | |
12527 | * just get the first one. | |
12528 | */ | |
484b41dd | 12529 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12530 | } |
46f297fb | 12531 | } |
2c7111db CW |
12532 | } |
12533 | ||
7fad798e DV |
12534 | static void intel_enable_pipe_a(struct drm_device *dev) |
12535 | { | |
12536 | struct intel_connector *connector; | |
12537 | struct drm_connector *crt = NULL; | |
12538 | struct intel_load_detect_pipe load_detect_temp; | |
51fd371b | 12539 | struct drm_modeset_acquire_ctx ctx; |
7fad798e DV |
12540 | |
12541 | /* We can't just switch on the pipe A, we need to set things up with a | |
12542 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12543 | * by enabling the load detect pipe once. */ | |
12544 | list_for_each_entry(connector, | |
12545 | &dev->mode_config.connector_list, | |
12546 | base.head) { | |
12547 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12548 | crt = &connector->base; | |
12549 | break; | |
12550 | } | |
12551 | } | |
12552 | ||
12553 | if (!crt) | |
12554 | return; | |
12555 | ||
51fd371b RC |
12556 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) |
12557 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | |
7fad798e | 12558 | |
652c393a | 12559 | |
7fad798e DV |
12560 | } |
12561 | ||
fa555837 DV |
12562 | static bool |
12563 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12564 | { | |
7eb552ae BW |
12565 | struct drm_device *dev = crtc->base.dev; |
12566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12567 | u32 reg, val; |
12568 | ||
7eb552ae | 12569 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12570 | return true; |
12571 | ||
12572 | reg = DSPCNTR(!crtc->plane); | |
12573 | val = I915_READ(reg); | |
12574 | ||
12575 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12576 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12577 | return false; | |
12578 | ||
12579 | return true; | |
12580 | } | |
12581 | ||
24929352 DV |
12582 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12583 | { | |
12584 | struct drm_device *dev = crtc->base.dev; | |
12585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12586 | u32 reg; |
24929352 | 12587 | |
24929352 | 12588 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12589 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12590 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12591 | ||
d3eaf884 VS |
12592 | /* restore vblank interrupts to correct state */ |
12593 | if (crtc->active) | |
12594 | drm_vblank_on(dev, crtc->pipe); | |
12595 | else | |
12596 | drm_vblank_off(dev, crtc->pipe); | |
12597 | ||
24929352 | 12598 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12599 | * disable the crtc (and hence change the state) if it is wrong. Note |
12600 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12601 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12602 | struct intel_connector *connector; |
12603 | bool plane; | |
12604 | ||
24929352 DV |
12605 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12606 | crtc->base.base.id); | |
12607 | ||
12608 | /* Pipe has the wrong plane attached and the plane is active. | |
12609 | * Temporarily change the plane mapping and disable everything | |
12610 | * ... */ | |
12611 | plane = crtc->plane; | |
12612 | crtc->plane = !plane; | |
12613 | dev_priv->display.crtc_disable(&crtc->base); | |
12614 | crtc->plane = plane; | |
12615 | ||
12616 | /* ... and break all links. */ | |
12617 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12618 | base.head) { | |
12619 | if (connector->encoder->base.crtc != &crtc->base) | |
12620 | continue; | |
12621 | ||
7f1950fb EE |
12622 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12623 | connector->base.encoder = NULL; | |
24929352 | 12624 | } |
7f1950fb EE |
12625 | /* multiple connectors may have the same encoder: |
12626 | * handle them and break crtc link separately */ | |
12627 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12628 | base.head) | |
12629 | if (connector->encoder->base.crtc == &crtc->base) { | |
12630 | connector->encoder->base.crtc = NULL; | |
12631 | connector->encoder->connectors_active = false; | |
12632 | } | |
24929352 DV |
12633 | |
12634 | WARN_ON(crtc->active); | |
12635 | crtc->base.enabled = false; | |
12636 | } | |
24929352 | 12637 | |
7fad798e DV |
12638 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12639 | crtc->pipe == PIPE_A && !crtc->active) { | |
12640 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12641 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12642 | * call below we restore the pipe to the right state, but leave | |
12643 | * the required bits on. */ | |
12644 | intel_enable_pipe_a(dev); | |
12645 | } | |
12646 | ||
24929352 DV |
12647 | /* Adjust the state of the output pipe according to whether we |
12648 | * have active connectors/encoders. */ | |
12649 | intel_crtc_update_dpms(&crtc->base); | |
12650 | ||
12651 | if (crtc->active != crtc->base.enabled) { | |
12652 | struct intel_encoder *encoder; | |
12653 | ||
12654 | /* This can happen either due to bugs in the get_hw_state | |
12655 | * functions or because the pipe is force-enabled due to the | |
12656 | * pipe A quirk. */ | |
12657 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12658 | crtc->base.base.id, | |
12659 | crtc->base.enabled ? "enabled" : "disabled", | |
12660 | crtc->active ? "enabled" : "disabled"); | |
12661 | ||
12662 | crtc->base.enabled = crtc->active; | |
12663 | ||
12664 | /* Because we only establish the connector -> encoder -> | |
12665 | * crtc links if something is active, this means the | |
12666 | * crtc is now deactivated. Break the links. connector | |
12667 | * -> encoder links are only establish when things are | |
12668 | * actually up, hence no need to break them. */ | |
12669 | WARN_ON(crtc->active); | |
12670 | ||
12671 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12672 | WARN_ON(encoder->connectors_active); | |
12673 | encoder->base.crtc = NULL; | |
12674 | } | |
12675 | } | |
c5ab3bc0 DV |
12676 | |
12677 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12678 | /* |
12679 | * We start out with underrun reporting disabled to avoid races. | |
12680 | * For correct bookkeeping mark this on active crtcs. | |
12681 | * | |
c5ab3bc0 DV |
12682 | * Also on gmch platforms we dont have any hardware bits to |
12683 | * disable the underrun reporting. Which means we need to start | |
12684 | * out with underrun reporting disabled also on inactive pipes, | |
12685 | * since otherwise we'll complain about the garbage we read when | |
12686 | * e.g. coming up after runtime pm. | |
12687 | * | |
4cc31489 DV |
12688 | * No protection against concurrent access is required - at |
12689 | * worst a fifo underrun happens which also sets this to false. | |
12690 | */ | |
12691 | crtc->cpu_fifo_underrun_disabled = true; | |
12692 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12693 | |
12694 | update_scanline_offset(crtc); | |
4cc31489 | 12695 | } |
24929352 DV |
12696 | } |
12697 | ||
12698 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12699 | { | |
12700 | struct intel_connector *connector; | |
12701 | struct drm_device *dev = encoder->base.dev; | |
12702 | ||
12703 | /* We need to check both for a crtc link (meaning that the | |
12704 | * encoder is active and trying to read from a pipe) and the | |
12705 | * pipe itself being active. */ | |
12706 | bool has_active_crtc = encoder->base.crtc && | |
12707 | to_intel_crtc(encoder->base.crtc)->active; | |
12708 | ||
12709 | if (encoder->connectors_active && !has_active_crtc) { | |
12710 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12711 | encoder->base.base.id, | |
8e329a03 | 12712 | encoder->base.name); |
24929352 DV |
12713 | |
12714 | /* Connector is active, but has no active pipe. This is | |
12715 | * fallout from our resume register restoring. Disable | |
12716 | * the encoder manually again. */ | |
12717 | if (encoder->base.crtc) { | |
12718 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
12719 | encoder->base.base.id, | |
8e329a03 | 12720 | encoder->base.name); |
24929352 DV |
12721 | encoder->disable(encoder); |
12722 | } | |
7f1950fb EE |
12723 | encoder->base.crtc = NULL; |
12724 | encoder->connectors_active = false; | |
24929352 DV |
12725 | |
12726 | /* Inconsistent output/port/pipe state happens presumably due to | |
12727 | * a bug in one of the get_hw_state functions. Or someplace else | |
12728 | * in our code, like the register restore mess on resume. Clamp | |
12729 | * things to off as a safer default. */ | |
12730 | list_for_each_entry(connector, | |
12731 | &dev->mode_config.connector_list, | |
12732 | base.head) { | |
12733 | if (connector->encoder != encoder) | |
12734 | continue; | |
7f1950fb EE |
12735 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12736 | connector->base.encoder = NULL; | |
24929352 DV |
12737 | } |
12738 | } | |
12739 | /* Enabled encoders without active connectors will be fixed in | |
12740 | * the crtc fixup. */ | |
12741 | } | |
12742 | ||
04098753 | 12743 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
12744 | { |
12745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 12746 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 12747 | |
04098753 ID |
12748 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12749 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
12750 | i915_disable_vga(dev); | |
12751 | } | |
12752 | } | |
12753 | ||
12754 | void i915_redisable_vga(struct drm_device *dev) | |
12755 | { | |
12756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12757 | ||
8dc8a27c PZ |
12758 | /* This function can be called both from intel_modeset_setup_hw_state or |
12759 | * at a very early point in our resume sequence, where the power well | |
12760 | * structures are not yet restored. Since this function is at a very | |
12761 | * paranoid "someone might have enabled VGA while we were not looking" | |
12762 | * level, just check if the power well is enabled instead of trying to | |
12763 | * follow the "don't touch the power well if we don't need it" policy | |
12764 | * the rest of the driver uses. */ | |
04098753 | 12765 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12766 | return; |
12767 | ||
04098753 | 12768 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12769 | } |
12770 | ||
98ec7739 VS |
12771 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12772 | { | |
12773 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
12774 | ||
12775 | if (!crtc->active) | |
12776 | return false; | |
12777 | ||
12778 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
12779 | } | |
12780 | ||
30e984df | 12781 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
12782 | { |
12783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12784 | enum pipe pipe; | |
24929352 DV |
12785 | struct intel_crtc *crtc; |
12786 | struct intel_encoder *encoder; | |
12787 | struct intel_connector *connector; | |
5358901f | 12788 | int i; |
24929352 | 12789 | |
d3fcc808 | 12790 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 12791 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 12792 | |
9953599b DV |
12793 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
12794 | ||
0e8ffe1b DV |
12795 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12796 | &crtc->config); | |
24929352 DV |
12797 | |
12798 | crtc->base.enabled = crtc->active; | |
98ec7739 | 12799 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
12800 | |
12801 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
12802 | crtc->base.base.id, | |
12803 | crtc->active ? "enabled" : "disabled"); | |
12804 | } | |
12805 | ||
5358901f | 12806 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 12807 | if (HAS_DDI(dev)) |
6441ab5f PZ |
12808 | intel_ddi_setup_hw_pll_state(dev); |
12809 | ||
5358901f DV |
12810 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12811 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12812 | ||
12813 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
12814 | pll->active = 0; | |
d3fcc808 | 12815 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
12816 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12817 | pll->active++; | |
12818 | } | |
12819 | pll->refcount = pll->active; | |
12820 | ||
35c95375 DV |
12821 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12822 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
12823 | } |
12824 | ||
24929352 DV |
12825 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12826 | base.head) { | |
12827 | pipe = 0; | |
12828 | ||
12829 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
12830 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12831 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 12832 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
12833 | } else { |
12834 | encoder->base.crtc = NULL; | |
12835 | } | |
12836 | ||
12837 | encoder->connectors_active = false; | |
6f2bcceb | 12838 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 12839 | encoder->base.base.id, |
8e329a03 | 12840 | encoder->base.name, |
24929352 | 12841 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 12842 | pipe_name(pipe)); |
24929352 DV |
12843 | } |
12844 | ||
12845 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12846 | base.head) { | |
12847 | if (connector->get_hw_state(connector)) { | |
12848 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
12849 | connector->encoder->connectors_active = true; | |
12850 | connector->base.encoder = &connector->encoder->base; | |
12851 | } else { | |
12852 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
12853 | connector->base.encoder = NULL; | |
12854 | } | |
12855 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12856 | connector->base.base.id, | |
c23cc417 | 12857 | connector->base.name, |
24929352 DV |
12858 | connector->base.encoder ? "enabled" : "disabled"); |
12859 | } | |
30e984df DV |
12860 | } |
12861 | ||
12862 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12863 | * and i915 state tracking structures. */ | |
12864 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12865 | bool force_restore) | |
12866 | { | |
12867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12868 | enum pipe pipe; | |
30e984df DV |
12869 | struct intel_crtc *crtc; |
12870 | struct intel_encoder *encoder; | |
35c95375 | 12871 | int i; |
30e984df DV |
12872 | |
12873 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12874 | |
babea61d JB |
12875 | /* |
12876 | * Now that we have the config, copy it to each CRTC struct | |
12877 | * Note that this could go away if we move to using crtc_config | |
12878 | * checking everywhere. | |
12879 | */ | |
d3fcc808 | 12880 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12881 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12882 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12883 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12884 | crtc->base.base.id); | |
12885 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12886 | } | |
12887 | } | |
12888 | ||
24929352 DV |
12889 | /* HW state is read out, now we need to sanitize this mess. */ |
12890 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12891 | base.head) { | |
12892 | intel_sanitize_encoder(encoder); | |
12893 | } | |
12894 | ||
12895 | for_each_pipe(pipe) { | |
12896 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12897 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12898 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12899 | } |
9a935856 | 12900 | |
35c95375 DV |
12901 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12902 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12903 | ||
12904 | if (!pll->on || pll->active) | |
12905 | continue; | |
12906 | ||
12907 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12908 | ||
12909 | pll->disable(dev_priv, pll); | |
12910 | pll->on = false; | |
12911 | } | |
12912 | ||
96f90c54 | 12913 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12914 | ilk_wm_get_hw_state(dev); |
12915 | ||
45e2b5f6 | 12916 | if (force_restore) { |
7d0bc1ea VS |
12917 | i915_redisable_vga(dev); |
12918 | ||
f30da187 DV |
12919 | /* |
12920 | * We need to use raw interfaces for restoring state to avoid | |
12921 | * checking (bogus) intermediate states. | |
12922 | */ | |
45e2b5f6 | 12923 | for_each_pipe(pipe) { |
b5644d05 JB |
12924 | struct drm_crtc *crtc = |
12925 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12926 | |
12927 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12928 | crtc->primary->fb); |
45e2b5f6 DV |
12929 | } |
12930 | } else { | |
12931 | intel_modeset_update_staged_output_state(dev); | |
12932 | } | |
8af6cf88 DV |
12933 | |
12934 | intel_modeset_check_state(dev); | |
2c7111db CW |
12935 | } |
12936 | ||
12937 | void intel_modeset_gem_init(struct drm_device *dev) | |
12938 | { | |
484b41dd JB |
12939 | struct drm_crtc *c; |
12940 | struct intel_framebuffer *fb; | |
12941 | ||
ae48434c ID |
12942 | mutex_lock(&dev->struct_mutex); |
12943 | intel_init_gt_powersave(dev); | |
12944 | mutex_unlock(&dev->struct_mutex); | |
12945 | ||
1833b134 | 12946 | intel_modeset_init_hw(dev); |
02e792fb DV |
12947 | |
12948 | intel_setup_overlay(dev); | |
484b41dd JB |
12949 | |
12950 | /* | |
12951 | * Make sure any fbs we allocated at startup are properly | |
12952 | * pinned & fenced. When we do the allocation it's too early | |
12953 | * for this. | |
12954 | */ | |
12955 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12956 | for_each_crtc(dev, c) { |
66e514c1 | 12957 | if (!c->primary->fb) |
484b41dd JB |
12958 | continue; |
12959 | ||
66e514c1 | 12960 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12961 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12962 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12963 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12964 | drm_framebuffer_unreference(c->primary->fb); |
12965 | c->primary->fb = NULL; | |
484b41dd JB |
12966 | } |
12967 | } | |
12968 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12969 | } |
12970 | ||
4932e2c3 ID |
12971 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12972 | { | |
12973 | struct drm_connector *connector = &intel_connector->base; | |
12974 | ||
12975 | intel_panel_destroy_backlight(connector); | |
12976 | drm_sysfs_connector_remove(connector); | |
12977 | } | |
12978 | ||
79e53945 JB |
12979 | void intel_modeset_cleanup(struct drm_device *dev) |
12980 | { | |
652c393a | 12981 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 12982 | struct drm_connector *connector; |
652c393a | 12983 | |
fd0c0642 DV |
12984 | /* |
12985 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12986 | * Too much stuff here (turning of rps, connectors, ...) would | |
12987 | * experience fancy races otherwise. | |
12988 | */ | |
12989 | drm_irq_uninstall(dev); | |
12990 | cancel_work_sync(&dev_priv->hotplug_work); | |
12991 | /* | |
12992 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12993 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12994 | */ | |
f87ea761 | 12995 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12996 | |
652c393a JB |
12997 | mutex_lock(&dev->struct_mutex); |
12998 | ||
723bfd70 JB |
12999 | intel_unregister_dsm_handler(); |
13000 | ||
973d04f9 | 13001 | intel_disable_fbc(dev); |
e70236a8 | 13002 | |
8090c6b9 | 13003 | intel_disable_gt_powersave(dev); |
0cdab21f | 13004 | |
930ebb46 DV |
13005 | ironlake_teardown_rc6(dev); |
13006 | ||
69341a5e KH |
13007 | mutex_unlock(&dev->struct_mutex); |
13008 | ||
1630fe75 CW |
13009 | /* flush any delayed tasks or pending work */ |
13010 | flush_scheduled_work(); | |
13011 | ||
db31af1d JN |
13012 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13013 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13014 | struct intel_connector *intel_connector; |
13015 | ||
13016 | intel_connector = to_intel_connector(connector); | |
13017 | intel_connector->unregister(intel_connector); | |
db31af1d | 13018 | } |
d9255d57 | 13019 | |
79e53945 | 13020 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13021 | |
13022 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13023 | |
13024 | mutex_lock(&dev->struct_mutex); | |
13025 | intel_cleanup_gt_powersave(dev); | |
13026 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13027 | } |
13028 | ||
f1c79df3 ZW |
13029 | /* |
13030 | * Return which encoder is currently attached for connector. | |
13031 | */ | |
df0e9248 | 13032 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13033 | { |
df0e9248 CW |
13034 | return &intel_attached_encoder(connector)->base; |
13035 | } | |
f1c79df3 | 13036 | |
df0e9248 CW |
13037 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13038 | struct intel_encoder *encoder) | |
13039 | { | |
13040 | connector->encoder = encoder; | |
13041 | drm_mode_connector_attach_encoder(&connector->base, | |
13042 | &encoder->base); | |
79e53945 | 13043 | } |
28d52043 DA |
13044 | |
13045 | /* | |
13046 | * set vga decode state - true == enable VGA decode | |
13047 | */ | |
13048 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13049 | { | |
13050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13051 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13052 | u16 gmch_ctrl; |
13053 | ||
75fa041d CW |
13054 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13055 | DRM_ERROR("failed to read control word\n"); | |
13056 | return -EIO; | |
13057 | } | |
13058 | ||
c0cc8a55 CW |
13059 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13060 | return 0; | |
13061 | ||
28d52043 DA |
13062 | if (state) |
13063 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13064 | else | |
13065 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13066 | |
13067 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13068 | DRM_ERROR("failed to write control word\n"); | |
13069 | return -EIO; | |
13070 | } | |
13071 | ||
28d52043 DA |
13072 | return 0; |
13073 | } | |
c4a1d9e4 | 13074 | |
c4a1d9e4 | 13075 | struct intel_display_error_state { |
ff57f1b0 PZ |
13076 | |
13077 | u32 power_well_driver; | |
13078 | ||
63b66e5b CW |
13079 | int num_transcoders; |
13080 | ||
c4a1d9e4 CW |
13081 | struct intel_cursor_error_state { |
13082 | u32 control; | |
13083 | u32 position; | |
13084 | u32 base; | |
13085 | u32 size; | |
52331309 | 13086 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13087 | |
13088 | struct intel_pipe_error_state { | |
ddf9c536 | 13089 | bool power_domain_on; |
c4a1d9e4 | 13090 | u32 source; |
f301b1e1 | 13091 | u32 stat; |
52331309 | 13092 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13093 | |
13094 | struct intel_plane_error_state { | |
13095 | u32 control; | |
13096 | u32 stride; | |
13097 | u32 size; | |
13098 | u32 pos; | |
13099 | u32 addr; | |
13100 | u32 surface; | |
13101 | u32 tile_offset; | |
52331309 | 13102 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13103 | |
13104 | struct intel_transcoder_error_state { | |
ddf9c536 | 13105 | bool power_domain_on; |
63b66e5b CW |
13106 | enum transcoder cpu_transcoder; |
13107 | ||
13108 | u32 conf; | |
13109 | ||
13110 | u32 htotal; | |
13111 | u32 hblank; | |
13112 | u32 hsync; | |
13113 | u32 vtotal; | |
13114 | u32 vblank; | |
13115 | u32 vsync; | |
13116 | } transcoder[4]; | |
c4a1d9e4 CW |
13117 | }; |
13118 | ||
13119 | struct intel_display_error_state * | |
13120 | intel_display_capture_error_state(struct drm_device *dev) | |
13121 | { | |
fbee40df | 13122 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13123 | struct intel_display_error_state *error; |
63b66e5b CW |
13124 | int transcoders[] = { |
13125 | TRANSCODER_A, | |
13126 | TRANSCODER_B, | |
13127 | TRANSCODER_C, | |
13128 | TRANSCODER_EDP, | |
13129 | }; | |
c4a1d9e4 CW |
13130 | int i; |
13131 | ||
63b66e5b CW |
13132 | if (INTEL_INFO(dev)->num_pipes == 0) |
13133 | return NULL; | |
13134 | ||
9d1cb914 | 13135 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13136 | if (error == NULL) |
13137 | return NULL; | |
13138 | ||
190be112 | 13139 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13140 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13141 | ||
52331309 | 13142 | for_each_pipe(i) { |
ddf9c536 | 13143 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13144 | intel_display_power_enabled_unlocked(dev_priv, |
13145 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13146 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13147 | continue; |
13148 | ||
5efb3e28 VS |
13149 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13150 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13151 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13152 | |
13153 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13154 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13155 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13156 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13157 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13158 | } | |
ca291363 PZ |
13159 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13160 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13161 | if (INTEL_INFO(dev)->gen >= 4) { |
13162 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13163 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13164 | } | |
13165 | ||
c4a1d9e4 | 13166 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
13167 | |
13168 | if (!HAS_PCH_SPLIT(dev)) | |
13169 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
13170 | } |
13171 | ||
13172 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13173 | if (HAS_DDI(dev_priv->dev)) | |
13174 | error->num_transcoders++; /* Account for eDP. */ | |
13175 | ||
13176 | for (i = 0; i < error->num_transcoders; i++) { | |
13177 | enum transcoder cpu_transcoder = transcoders[i]; | |
13178 | ||
ddf9c536 | 13179 | error->transcoder[i].power_domain_on = |
bfafe93a | 13180 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13181 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13182 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13183 | continue; |
13184 | ||
63b66e5b CW |
13185 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13186 | ||
13187 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13188 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13189 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13190 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13191 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13192 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13193 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13194 | } |
13195 | ||
13196 | return error; | |
13197 | } | |
13198 | ||
edc3d884 MK |
13199 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13200 | ||
c4a1d9e4 | 13201 | void |
edc3d884 | 13202 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13203 | struct drm_device *dev, |
13204 | struct intel_display_error_state *error) | |
13205 | { | |
13206 | int i; | |
13207 | ||
63b66e5b CW |
13208 | if (!error) |
13209 | return; | |
13210 | ||
edc3d884 | 13211 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13212 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13213 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13214 | error->power_well_driver); |
52331309 | 13215 | for_each_pipe(i) { |
edc3d884 | 13216 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13217 | err_printf(m, " Power: %s\n", |
13218 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13219 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13220 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13221 | |
13222 | err_printf(m, "Plane [%d]:\n", i); | |
13223 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13224 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13225 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13226 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13227 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13228 | } |
4b71a570 | 13229 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13230 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13231 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13232 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13233 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13234 | } |
13235 | ||
edc3d884 MK |
13236 | err_printf(m, "Cursor [%d]:\n", i); |
13237 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13238 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13239 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13240 | } |
63b66e5b CW |
13241 | |
13242 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13243 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13244 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13245 | err_printf(m, " Power: %s\n", |
13246 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13247 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13248 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13249 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13250 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13251 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13252 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13253 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13254 | } | |
c4a1d9e4 | 13255 | } |